From ec7123d54ce7c00e10ceff2452ed60cda4c12d68 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Sat, 16 Jul 2022 16:47:00 +0800 Subject: [PATCH] Support riscv, starfive CPU. Signed-off-by: Steven Liu --- trunk/src/core/srs_core.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/trunk/src/core/srs_core.hpp b/trunk/src/core/srs_core.hpp index f98b3c125..7be007663 100644 --- a/trunk/src/core/srs_core.hpp +++ b/trunk/src/core/srs_core.hpp @@ -58,8 +58,8 @@ (void)0 // Check CPU for ST(state-threads), please read https://github.com/ossrs/state-threads/issues/22 -#if !defined(__amd64__) && !defined(__x86_64__) && !defined(__i386__) && !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__loongarch__) - #error "Only support i386/amd64/x86_64/arm/aarch64/mips/loongarch cpu" +#if !defined(__amd64__) && !defined(__x86_64__) && !defined(__i386__) && !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__loongarch__) && !defined(__riscv) + #error "Only support i386/amd64/x86_64/arm/aarch64/mips/loongarch/riscv cpu" #endif // Error predefined for all modules.