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382 lines
9.9 KiB
NASM
382 lines
9.9 KiB
NASM
;; Copyright 2012-2016 The OpenSSL Project Authors. All Rights Reserved.
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;;
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;; Licensed under the OpenSSL license (the "License"). You may not use
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;; this file except in compliance with the License. You can obtain a copy
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;; in the file LICENSE in the source distribution or at
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;; https://www.openssl.org/source/license.html
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;;
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;;====================================================================
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;; Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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;; project.
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;;
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;; Rights for redistribution and usage in source and binary forms are
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;; granted according to the OpenSSL license. Warranty of any kind is
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;; disclaimed.
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;;====================================================================
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;; Compiler-generated multiply-n-add SPLOOP runs at 12*n cycles, n
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;; being the number of 32-bit words, addition - 8*n. Corresponding 4x
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;; unrolled SPLOOP-free loops - at ~8*n and ~5*n. Below assembler
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;; SPLOOPs spin at ... 2*n cycles [plus epilogue].
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;;====================================================================
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.text
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.if .ASSEMBLER_VERSION<7000000
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.asg 0,__TI_EABI__
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.endif
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.if __TI_EABI__
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.asg bn_mul_add_words,_bn_mul_add_words
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.asg bn_mul_words,_bn_mul_words
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.asg bn_sqr_words,_bn_sqr_words
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.asg bn_add_words,_bn_add_words
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.asg bn_sub_words,_bn_sub_words
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.asg bn_div_words,_bn_div_words
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.asg bn_sqr_comba8,_bn_sqr_comba8
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.asg bn_mul_comba8,_bn_mul_comba8
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.asg bn_sqr_comba4,_bn_sqr_comba4
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.asg bn_mul_comba4,_bn_mul_comba4
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.endif
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.asg B3,RA
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.asg A4,ARG0
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.asg B4,ARG1
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.asg A6,ARG2
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.asg B6,ARG3
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.asg A8,ARG4
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.asg B8,ARG5
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.asg A4,RET
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.asg A15,FP
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.asg B14,DP
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.asg B15,SP
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.global _bn_mul_add_words
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_bn_mul_add_words:
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.asmfunc
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MV ARG2,B0
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[!B0] BNOP RA
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||[!B0] MVK 0,RET
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[B0] MVC B0,ILC
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[B0] ZERO A19 ; high part of accumulator
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|| [B0] MV ARG0,A2
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|| [B0] MV ARG3,A3
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NOP 3
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SPLOOP 2 ; 2*n+10
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;;====================================================================
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LDW *ARG1++,B7 ; ap[i]
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NOP 3
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LDW *ARG0++,A7 ; rp[i]
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MPY32U B7,A3,A17:A16
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NOP 3 ; [2,0] in epilogue
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ADDU A16,A7,A21:A20
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ADDU A19,A21:A20,A19:A18
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|| MV.S A17,A23
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SPKERNEL 2,1 ; leave slot for "return value"
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|| STW A18,*A2++ ; rp[i]
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|| ADD A19,A23,A19
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;;====================================================================
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BNOP RA,4
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MV A19,RET ; return value
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.endasmfunc
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.global _bn_mul_words
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_bn_mul_words:
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.asmfunc
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MV ARG2,B0
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[!B0] BNOP RA
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||[!B0] MVK 0,RET
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[B0] MVC B0,ILC
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[B0] ZERO A19 ; high part of accumulator
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NOP 3
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SPLOOP 2 ; 2*n+10
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;;====================================================================
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LDW *ARG1++,A7 ; ap[i]
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NOP 4
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MPY32U A7,ARG3,A17:A16
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NOP 4 ; [2,0] in epiloque
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ADDU A19,A16,A19:A18
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|| MV.S A17,A21
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SPKERNEL 2,1 ; leave slot for "return value"
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|| STW A18,*ARG0++ ; rp[i]
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|| ADD.L A19,A21,A19
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;;====================================================================
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BNOP RA,4
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MV A19,RET ; return value
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.endasmfunc
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.global _bn_sqr_words
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_bn_sqr_words:
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.asmfunc
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MV ARG2,B0
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[!B0] BNOP RA
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||[!B0] MVK 0,RET
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[B0] MVC B0,ILC
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[B0] MV ARG0,B2
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|| [B0] ADD 4,ARG0,ARG0
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NOP 3
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SPLOOP 2 ; 2*n+10
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;;====================================================================
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LDW *ARG1++,B7 ; ap[i]
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NOP 4
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MPY32U B7,B7,B1:B0
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NOP 3 ; [2,0] in epilogue
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STW B0,*B2++(8) ; rp[2*i]
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MV B1,A1
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SPKERNEL 2,0 ; fully overlap BNOP RA,5
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|| STW A1,*ARG0++(8) ; rp[2*i+1]
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;;====================================================================
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BNOP RA,5
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.endasmfunc
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.global _bn_add_words
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_bn_add_words:
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.asmfunc
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MV ARG3,B0
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[!B0] BNOP RA
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||[!B0] MVK 0,RET
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[B0] MVC B0,ILC
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[B0] ZERO A1 ; carry flag
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|| [B0] MV ARG0,A3
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NOP 3
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SPLOOP 2 ; 2*n+6
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;;====================================================================
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LDW *ARG2++,A7 ; bp[i]
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|| LDW *ARG1++,B7 ; ap[i]
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NOP 4
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ADDU A7,B7,A9:A8
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ADDU A1,A9:A8,A1:A0
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SPKERNEL 0,0 ; fully overlap BNOP RA,5
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|| STW A0,*A3++ ; write result
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|| MV A1,RET ; keep carry flag in RET
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;;====================================================================
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BNOP RA,5
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.endasmfunc
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.global _bn_sub_words
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_bn_sub_words:
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.asmfunc
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MV ARG3,B0
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[!B0] BNOP RA
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||[!B0] MVK 0,RET
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[B0] MVC B0,ILC
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[B0] ZERO A2 ; borrow flag
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|| [B0] MV ARG0,A3
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NOP 3
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SPLOOP 2 ; 2*n+6
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;;====================================================================
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LDW *ARG2++,A7 ; bp[i]
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|| LDW *ARG1++,B7 ; ap[i]
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NOP 4
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SUBU B7,A7,A1:A0
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[A2] SUB A1:A0,1,A1:A0
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SPKERNEL 0,1 ; leave slot for "return borrow flag"
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|| STW A0,*A3++ ; write result
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|| AND 1,A1,A2 ; pass on borrow flag
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;;====================================================================
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BNOP RA,4
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AND 1,A1,RET ; return borrow flag
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.endasmfunc
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.global _bn_div_words
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_bn_div_words:
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.asmfunc
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LMBD 1,A6,A0 ; leading zero bits in dv
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LMBD 1,A4,A1 ; leading zero bits in hi
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|| MVK 32,B0
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CMPLTU A1,A0,A2
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|| ADD A0,B0,B0
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[ A2] BNOP RA
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||[ A2] MVK -1,A4 ; return overflow
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||[!A2] MV A4,A3 ; reassign hi
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[!A2] MV B4,A4 ; reassign lo, will be quotient
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||[!A2] MVC B0,ILC
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[!A2] SHL A6,A0,A6 ; normalize dv
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|| MVK 1,A1
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[!A2] CMPLTU A3,A6,A1 ; hi<dv?
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||[!A2] SHL A4,1,A5:A4 ; lo<<1
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[!A1] SUB A3,A6,A3 ; hi-=dv
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||[!A1] OR 1,A4,A4
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[!A2] SHRU A3,31,A1 ; upper bit
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||[!A2] ADDAH A5,A3,A3 ; hi<<1|lo>>31
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SPLOOP 3
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[!A1] CMPLTU A3,A6,A1 ; hi<dv?
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||[ A1] ZERO A1
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|| SHL A4,1,A5:A4 ; lo<<1
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[!A1] SUB A3,A6,A3 ; hi-=dv
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||[!A1] OR 1,A4,A4 ; quotient
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SHRU A3,31,A1 ; upper bit
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|| ADDAH A5,A3,A3 ; hi<<1|lo>>31
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SPKERNEL
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BNOP RA,5
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.endasmfunc
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;;====================================================================
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;; Not really Comba algorithm, just straightforward NxM... Dedicated
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;; fully unrolled real Comba implementations are asymptotically 2x
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;; faster, but naturally larger undertaking. Purpose of this exercise
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;; was rather to learn to master nested SPLOOPs...
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;;====================================================================
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.global _bn_sqr_comba8
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.global _bn_mul_comba8
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_bn_sqr_comba8:
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MV ARG1,ARG2
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_bn_mul_comba8:
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.asmfunc
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MVK 8,B0 ; N, RILC
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|| MVK 8,A0 ; M, outer loop counter
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|| MV ARG1,A5 ; copy ap
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|| MV ARG0,B4 ; copy rp
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|| ZERO B19 ; high part of accumulator
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MVC B0,RILC
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|| SUB B0,2,B1 ; N-2, initial ILC
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|| SUB B0,1,B2 ; const B2=N-1
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|| LDW *A5++,B6 ; ap[0]
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|| MV A0,A3 ; const A3=M
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sploopNxM?: ; for best performance arrange M<=N
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[A0] SPLOOPD 2 ; 2*n+10
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|| MVC B1,ILC
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|| ADDAW B4,B0,B5
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|| ZERO B7
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|| LDW *A5++,A9 ; pre-fetch ap[1]
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|| ZERO A1
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|| SUB A0,1,A0
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;;====================================================================
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;; SPLOOP from bn_mul_add_words, but with flipped A<>B register files.
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;; This is because of Advisory 15 from TI publication SPRZ247I.
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LDW *ARG2++,A7 ; bp[i]
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NOP 3
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[A1] LDW *B5++,B7 ; rp[i]
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MPY32U A7,B6,B17:B16
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NOP 3
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ADDU B16,B7,B21:B20
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ADDU B19,B21:B20,B19:B18
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|| MV.S B17,B23
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SPKERNEL
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|| STW B18,*B4++ ; rp[i]
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|| ADD.S B19,B23,B19
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;;====================================================================
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outer?: ; m*2*(n+1)+10
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SUBAW ARG2,A3,ARG2 ; rewind bp to bp[0]
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SPMASKR
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|| CMPGT A0,1,A2 ; done pre-fetching ap[i+1]?
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MVD A9,B6 ; move through .M unit(*)
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[A2] LDW *A5++,A9 ; pre-fetch ap[i+1]
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SUBAW B5,B2,B5 ; rewind rp to rp[1]
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MVK 1,A1
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[A0] BNOP.S1 outer?,4
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|| [A0] SUB.L A0,1,A0
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STW B19,*B4--[B2] ; rewind rp tp rp[1]
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|| ZERO.S B19 ; high part of accumulator
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;; end of outer?
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BNOP RA,5 ; return
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.endasmfunc
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;; (*) It should be noted that B6 is used as input to MPY32U in
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;; chronologically next cycle in *preceding* SPLOOP iteration.
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;; Normally such arrangement would require DINT, but at this
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;; point SPLOOP is draining and interrupts are disabled
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;; implicitly.
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.global _bn_sqr_comba4
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.global _bn_mul_comba4
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_bn_sqr_comba4:
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MV ARG1,ARG2
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_bn_mul_comba4:
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.asmfunc
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.if 0
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BNOP sploopNxM?,3
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;; Above mentioned m*2*(n+1)+10 does not apply in n=m=4 case,
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;; because of low-counter effect, when prologue phase finishes
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;; before SPKERNEL instruction is reached. As result it's 25%
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;; slower than expected...
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MVK 4,B0 ; N, RILC
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|| MVK 4,A0 ; M, outer loop counter
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|| MV ARG1,A5 ; copy ap
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|| MV ARG0,B4 ; copy rp
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|| ZERO B19 ; high part of accumulator
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MVC B0,RILC
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|| SUB B0,2,B1 ; first ILC
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|| SUB B0,1,B2 ; const B2=N-1
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|| LDW *A5++,B6 ; ap[0]
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|| MV A0,A3 ; const A3=M
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.else
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;; This alternative is an exercise in fully unrolled Comba
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;; algorithm implementation that operates at n*(n+1)+12, or
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;; as little as 32 cycles...
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LDW *ARG1[0],B16 ; a[0]
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|| LDW *ARG2[0],A16 ; b[0]
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LDW *ARG1[1],B17 ; a[1]
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|| LDW *ARG2[1],A17 ; b[1]
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LDW *ARG1[2],B18 ; a[2]
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|| LDW *ARG2[2],A18 ; b[2]
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LDW *ARG1[3],B19 ; a[3]
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|| LDW *ARG2[3],A19 ; b[3]
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NOP
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MPY32U A16,B16,A1:A0 ; a[0]*b[0]
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MPY32U A17,B16,A23:A22 ; a[0]*b[1]
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MPY32U A16,B17,A25:A24 ; a[1]*b[0]
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MPY32U A16,B18,A27:A26 ; a[2]*b[0]
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STW A0,*ARG0[0]
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|| MPY32U A17,B17,A29:A28 ; a[1]*b[1]
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MPY32U A18,B16,A31:A30 ; a[0]*b[2]
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|| ADDU A22,A1,A1:A0
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MV A23,B0
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|| MPY32U A19,B16,A21:A20 ; a[3]*b[0]
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|| ADDU A24,A1:A0,A1:A0
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ADDU A25,B0,B1:B0
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|| STW A0,*ARG0[1]
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|| MPY32U A18,B17,A23:A22 ; a[2]*b[1]
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|| ADDU A26,A1,A9:A8
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ADDU A27,B1,B9:B8
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|| MPY32U A17,B18,A25:A24 ; a[1]*b[2]
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|| ADDU A28,A9:A8,A9:A8
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ADDU A29,B9:B8,B9:B8
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|| MPY32U A16,B19,A27:A26 ; a[0]*b[3]
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|| ADDU A30,A9:A8,A9:A8
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ADDU A31,B9:B8,B9:B8
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|| ADDU B0,A9:A8,A9:A8
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STW A8,*ARG0[2]
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|| ADDU A20,A9,A1:A0
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ADDU A21,B9,B1:B0
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|| MPY32U A19,B17,A21:A20 ; a[3]*b[1]
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|| ADDU A22,A1:A0,A1:A0
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ADDU A23,B1:B0,B1:B0
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|| MPY32U A18,B18,A23:A22 ; a[2]*b[2]
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|| ADDU A24,A1:A0,A1:A0
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ADDU A25,B1:B0,B1:B0
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|| MPY32U A17,B19,A25:A24 ; a[1]*b[3]
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|| ADDU A26,A1:A0,A1:A0
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ADDU A27,B1:B0,B1:B0
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|| ADDU B8,A1:A0,A1:A0
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STW A0,*ARG0[3]
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|| MPY32U A19,B18,A27:A26 ; a[3]*b[2]
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|| ADDU A20,A1,A9:A8
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ADDU A21,B1,B9:B8
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|| MPY32U A18,B19,A29:A28 ; a[2]*b[3]
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|| ADDU A22,A9:A8,A9:A8
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ADDU A23,B9:B8,B9:B8
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|| MPY32U A19,B19,A31:A30 ; a[3]*b[3]
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|| ADDU A24,A9:A8,A9:A8
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ADDU A25,B9:B8,B9:B8
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|| ADDU B0,A9:A8,A9:A8
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STW A8,*ARG0[4]
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|| ADDU A26,A9,A1:A0
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ADDU A27,B9,B1:B0
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|| ADDU A28,A1:A0,A1:A0
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ADDU A29,B1:B0,B1:B0
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|| BNOP RA
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|| ADDU B8,A1:A0,A1:A0
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STW A0,*ARG0[5]
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|| ADDU A30,A1,A9:A8
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ADD A31,B1,B8
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ADDU B0,A9:A8,A9:A8 ; removed || to avoid cross-path stall below
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ADD B8,A9,A9
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|| STW A8,*ARG0[6]
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STW A9,*ARG0[7]
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.endif
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.endasmfunc
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