diff --git a/qca/aq-fw-download/Makefile b/qca/aq-fw-download/Makefile new file mode 100644 index 000000000..7e864b42a --- /dev/null +++ b/qca/aq-fw-download/Makefile @@ -0,0 +1,55 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=aq-fw-download +PKG_BRANCH:=master +PKG_VERSION:=1.0 +PKG_RELEASE:=1 + +PKG_BUILD_DIR:=$(BUILD_DIR)/aq-fw-download + +include $(INCLUDE_DIR)/package.mk + +define AquantiaUtil + + define Package/aq-fw-download + SECTION:=utils + CATEGORY:=Utilities + DEPENDS:=@TARGET_ipq806x||TARGET_ipq||TARGET_ipq40xx||TARGET_ipq807x_32||TARGET_ipq807x + TITLE:=Aquantia FW downloader utitlity + endef + + define Package/aq-fw-download/description + Aquantia FW downloader utitlity + endef + +TARGET_CPPFLAGS := \ + -D_GNU_SOURCE \ + -I$(LINUX_SRC_DIR)/include \ + -I$(LINUX_SRC_DIR)/arch/$(LINUX_KARCH)/include \ + -I$(PKG_BUILD_DIR) \ + $(TARGET_CPPFLAGS) + + define Build/Prepare + mkdir -p $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + endef + + define Build/Compile + CFLAGS="$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + $(MAKE) -C $(PKG_BUILD_DIR) \ + $(TARGET_CONFIGURE_OPTS) + endef + + define Package/aq-fw-download/install + $(INSTALL_DIR) $$(1)/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $$(1)/sbin/aq-fw-download + endef + + $$(eval $$(call BuildPackage,aq-fw-download)) +endef + +#Build/Compile=true + +$(eval $(call AquantiaUtil)) diff --git a/qca/aq-fw-download/src/Makefile b/qca/aq-fw-download/src/Makefile new file mode 100644 index 000000000..dc141be0e --- /dev/null +++ b/qca/aq-fw-download/src/Makefile @@ -0,0 +1,14 @@ +ifndef CFLAGS +CFLAGS = -O2 -g +endif +INCLUDES=-Iinclude -Iinclude/registerMap \ + -Iinclude/registerMap/APPIA \ + -Iinclude/registerMap/HHD + +all: aq-fw-download + +%.o: %.c + $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ + +aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o + $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/qca/aq-fw-download/src/include/AQ_API.h b/qca/aq-fw-download/src/include/AQ_API.h new file mode 100644 index 000000000..9a0b4c20a --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_API.h @@ -0,0 +1,246 @@ +/* +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +/*! \file + This file contains the AQ_API function and datatype declarations. */ + + +#ifndef AQ_API_TOKEN +#define AQ_API_TOKEN + +#include + +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +/******************************************************************* + General +*******************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! This typedef defines the bool datatype which takes the values +true and false.*/ +typedef enum {False = 0, True = 1} AQ_boolean; + + +/*@}*/ + + +/******************************************************************* + Device Identity +*******************************************************************/ + +/*! \defgroup deviceIdentity Device Identity +All AQ_API functions accept a parameter identifying the target PHY that +should be acted upon. */ +/*@{*/ + + +/*! This enumeration is used to describe the different types of + Aquantia PHY.*/ +typedef enum +{ + /*! 1/2/4-port package, 40nm architechture.*/ + AQ_DEVICE_APPIA, + /*! 1/2/4-port package, 28nm architechture.*/ + AQ_DEVICE_HHD +} AQ_API_Device; + +/*! This structure is used to specify a particular Aquantia PHY port + within the system.*/ +typedef struct +{ + /*! The type of Aquantia PHY*/ + AQ_API_Device device; + /*! Uniquely identifies the port within the system. AQ_Port must be + defined to whatever data type is suitable for the platform. + AQ_API functions will never do anything with PHY_ID other than + pass it down to the platform's PHY register read/write + functions.*/ + AQ_Port PHY_ID; +} AQ_API_Port; + +/*@}*/ + + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH). During boot-load of each + Aquantia PHY, the processor is halted, and after programming is + complete the processor is released. Note that calling this + function leaves the daisy-chain disabled to prevent RAM over- + write. To exit MDIO boot-load mode, use the function + AQ_API_EnableDaisyChain. + Unlike most of the other functions in this API, this function can + operate on a group of PHYs simultaneously. This is referred to as + gang-loading. To facilitate this, this function takes as + parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and + resultCodes. The length of these arrays must be identical, and is + specified by the num_PHY_IDs parameter. + In order to check the integrity of the boot-load operation, a + CRC-16 value is calculated over the IRAM and DRAM. After the image + has been loaded, this value is directly compared against each + PHY's Mailbox CRC-16 in 1E.0201. + The value of register 1E.C441 must be the same for all the boot- + loaded PHYs. This will be checked before the boot-load is + performed, and if a non-uniform value is read from any of the + PHYs, the function will fail before any writes are performed. + A separate result code is returned for each of the boot-loaded + PHYs, in the OUT parameter, resultCodes. + Individual Port Return codes: + AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address + was outside of the permitted range. + AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) + that must be uniform across the ports being bootloaded were not + uniform. + AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into + memory, but the after the port exited bootload the running + checksum that was read from the uP memory mailbox was not the + expected value. This indicates that the memory has potentially + been corrupted, and the PHY should be reset before trying the + bootload again. + Overall Return codes (the return value from the function call): + AQ_RET_OK: all ports were successfully bootloaded. + AQ_RET_ERROR: One or more ports were not successfully bootloaded. + */ +AQ_Retcode AQ_API_WriteBootLoadImage +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort +); + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH), as well as a separately + provided provisioning table image file.The provisioning table + image allows additional provisioning to be provided, beyond what + is built in to the .cld image. If provTableSizePointer or + provTableImage are NULL, this function behaves like + AQ_API_WriteBootLoadImage. + Aside from the additional provisioing table, this function behaves + exactly the same as AQ_API_WriteBootLoadImage. For additional + documentation and information on return codes, refer to + AQ_API_WriteBootLoadImage. + Individual Port Return codes (same as AQ_API_WriteBootLoadImage, + plus): + AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning + table image does not fit within the alloted space.*/ +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort, + /*! A pointer to the size of the provTableImage (in bytes) that is + being loaded into the Aquantia PHY.*/ + uint32_t* provTableSizePointer, + /*! The additional provisioning table image being loaded into the + Aquantia PHY.*/ + uint8_t* provTableImage +); + +/*! Calling this function disables boot-loading and enables the daisy- + chain. This would typically be called after using MDIO boot- + loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain + after performing an MDIO bootload will cause the PHY to reboot + from FLASH.*/ +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PhyInterface.h b/qca/aq-fw-download/src/include/AQ_PhyInterface.h new file mode 100644 index 000000000..66eb817be --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PhyInterface.h @@ -0,0 +1,171 @@ +/* AQ_PhyInterface.h */ + +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the base PHY register read and write functions that are +* called by the API functions. The platform integrator must provide +* the implementation of these routines. +* +***********************************************************************/ + + +/*! \file + * Declares the base PHY register read and write functions that are + * called by the API functions. The platform integrator must provide + * the implementation of these routines. */ + + +#ifndef AQ_PHY_INTERFACE_TOKEN +#define AQ_PHY_INTERFACE_TOKEN + + +#include "AQ_API.h" +#include "AQ_User.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + MDIO Access Functions +*******************************************************************/ + +/*! \defgroup mdioAccessFunctions MDIO Access Functions +The MDIO access functions are required by the API to access the register space +of each Aquantia PHY deployed in a system. The body of these functions needs to +be written by the system designer, as the method of accessing the PHY will +be unique to the target system. They are designed to be generic read and +write access functions, as the MDIO addressing scheme relies on each +MMD to maintain a 16 bit address pointer that determines the register where +the next read or write is coming from. Consequently, various levels of +optimization of the MDIO interface are possible: from re-writing the MMD +address pointer on every transaction, to storing shadow copies of the MMD +address pointers and only updating the MMD address pointer as necessary. +Thus these functions leave the MDIO optimization to the system engineer. + */ +/*@{*/ + + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +/*! Provides generic asynchronous/buffered PHY register write functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this write + * operation. The write need not necessarily have been completed by the time + * this function returns. All register reads and writes to a particular PHY_ID + * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. */ +void AQ_API_MDIO_BlockWrite +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic asynchronous/buffered PHY register read functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this read + * operation. All register reads and writes to a particular PHY_ID that + * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. The register value + * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ +void AQ_API_MDIO_BlockRead +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +/* Retrieve the results of all PHY register reads to PHY_ID previously + * requested via calls to AQ_API_MDIO_BlockRead. The read and write + * operations previously performed by calls to AQ_API_MDIO_BlockRead and + * AQ_API_MDIO_BlockRead must have all been completed by the time this + * function returns, in the order that the calls were performed. The + * return value is an array representing the fetched results of all + * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls + * were performed. Callers should track the number of pending block + * reads to determine the size of the returned array. */ +unsigned int * AQ_API_MDIO_BlockOperationExecute +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID +); + +/* Returns the maximum number of asynchronous/buffered PHY register + * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute + * before issuing additional calls to AQ_API_MDIO_BlockWrite or + * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ +unsigned int AQ_API_MDIO_MaxBlockOperations +( +); + +#endif + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h new file mode 100644 index 000000000..9a16d6408 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h @@ -0,0 +1,71 @@ +/*AQ_PlatformRoutines.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the platform interface functions that will be called by AQ_API +* functions. The platform integrator must provide the implementation of +* these functions. +* +************************************************************************************/ + +/*! \file + * Declares the platform interface functions that will be called by AQ_API + * functions. The platform integrator must provide the implementation of + * these functions. */ + + +#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN +#define AQ_PHY_PLATFORMROUTINES_TOKEN + +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + Time Delay +*******************************************************************/ + +/*! \defgroup delay Time Delay + @{ +*/ + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * in a platform-approriate way. AQ_API functions will call this function to + * block for the specified period of time. If necessary, PHY register reads + * may be performed on port to busy-wait. */ +void AQ_API_Wait +( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ +); + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_RegMacro.h b/qca/aq-fw-download/src/include/AQ_RegMacro.h new file mode 100644 index 000000000..8dcca522b --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_RegMacro.h @@ -0,0 +1,323 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +/*! \file + This file contains macros for accessing the AQ PHYs' registers + using the device-specific register map data structures and definitions. +*/ + +#ifndef AQ_REG_MACRO_TOKEN +#define AQ_REG_MACRO_TOKEN + +#include "AQ_PhyInterface.h" + + +#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0))) + +#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0))) + +#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#endif + +#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) + +#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) + +#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) + + +#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) + +#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) + +#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) + + +#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0))) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) + + +#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0))) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) + + +#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) + +#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0))) + +#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) + + +#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0))) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) + + +#endif + diff --git a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h new file mode 100644 index 000000000..bff083b03 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h @@ -0,0 +1,113 @@ +/* AQ_ReturnCodes.h */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file defines the AQ_API functions' integral return codes. +* +* +************************************************************************************/ + +/*! \file + This file defines the AQ_API functions' integral return codes. +*/ + +#ifndef AQ_RETURNCODES_TOKEN +#define AQ_RETURNCODES_TOKEN + + +/*! \defgroup ReturnCodes + @{ +*/ + +/*! Most AQ_API functions return AQ_Retcode to report success or failure. + * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. + * Callers should prefer to test the return values by equivalence to these + * symbols, rather than using the integer values directly, as these may + * not be stable across releases. The set of possible return codes that may + * be returned by a particular API function can be found in the function's + * documentation, as well as information on how to interpret each of the + * possible return codes. */ +typedef unsigned int AQ_Retcode; + +/*! \defgroup Success + @{ */ +#define AQ_RET_OK 0 +/*@}*/ + + +/*! \defgroup GeneralErrors + @{ */ +#define AQ_RET_ERROR 100 +#define AQ_RET_UP_BUSY_TIMEOUT 101 +/*@}*/ + +/*! \defgroup FunctionSpecificResults + @{ */ +#define AQ_RET_FLASH_READY 200 +#define AQ_RET_FLASH_READINESS_TIMEOUT 204 + +#define AQ_RET_FLASHINTF_READY 201 +#define AQ_RET_FLASHINTF_NOTREADY 202 +#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 + +#define AQ_RET_FLASH_TYPE_UNKNOWN 205 +#define AQ_RET_FLASH_TYPE_BAD 206 + +#define AQ_RET_FLASH_IMAGE_CORRUPT 207 +#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 +#define AQ_RET_FLASH_IMAGE_MISMATCH 209 + +#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 + +#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 +#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 +#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 +#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 + +#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 + +#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 +#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 + +#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 +#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 +#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 +#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 +#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 +#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 + +#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 +#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 +#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 +#define AQ_RET_SERDESEYE_LANE_OOR 232 +#define AQ_RET_SERDESEYE_COORD_OOR 233 + +#define AQ_RET_PIFMAILBOX_ERROR 234 +#define AQ_RET_PIFMAILBOX_TIMEOUT 235 + +#define AQ_RET_SEC_TABLE_INDEX_OOR 236 +/*@}*/ + +/*@}*/ + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_User.h b/qca/aq-fw-download/src/include/AQ_User.h new file mode 100644 index 000000000..c7526a7cb --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_User.h @@ -0,0 +1,97 @@ +/*AQ_User.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains preprocessor symbol definitions and type definitions +* for the platform-integrator controlled compile-time AQ_API options. +* +************************************************************************************/ + +/*! \file + This file contains preprocessor symbol definitions and type definitions + for the platform-integrator controlled compile-time AQ_API options. +*/ + +#ifndef AQ_USER_TOKEN +#define AQ_USER_TOKEN + +/*! \defgroup User User Definitions +This module contains the definitions used to configure AQ_API behavior as desired. */ +/*@{*/ + + +/*! Specify the proper data type for AQ_Port. This will depend on the + * platform-specific implementation of the PHY register read/write functions.*/ +typedef unsigned int AQ_Port; + + +/*! If defined, AQ_API functions will print various error and info messages + * to stdout. If not, nothing will be printed and AQ_API.c will NOT include + * stdio.h. */ +#define AQ_VERBOSE + + +/*! If defined, the PHY interface supports block (asynchronous) read/write + * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then + * the API will call the block-operation functions and so implementations + * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not + * defined, they will not be called, and need not be implemented. */ +#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + + +/*! If defined, time.h exists, and so the associated functions wil be used to + * compute the elapsed time spent in a polling loop, to ensure that the + * maximum time-out period will not be exceeded. If not defined, then + * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible + * elapsed time. */ +#define AQ_TIME_T_EXISTS + + +/*! The maximum number of synchronous PHY register reads that can be performed + * per second. A worst case number can be derived as follows: + * + * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 + * + * If using MDIO preamble suppression, multiply this number by 2 + * + * For instance, if a 5MHz MDIO clock is being used without preamble supression + * AQ_MDIO_READS_PER_SECOND = 78125 + * + * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be + * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ +#define AQ_MDIO_READS_PER_SECOND 78125 + + +/*! If defined, after writing to one of the registers that can trigger a + * processor-intensive MDIO operation, AQ_API functions will poll the + * the "processor intensive MDIO operation in progress" bit and wait for it + * to be zero before proceeding. */ +#define AQ_ENABLE_UP_BUSY_CHECKS + + +/*! If defined, the register map header files containing reverse-packed + * structs will be included. If not, the register map header files containing + * non-reverse-packed structs will be included. The proper choice is typically + * a function of the endianness of the platform; on big-endian systems the + * reverse-packed structs should be used, and on little-endian systems the + * non-reverse-packed structs should be used. */ +/*#define AQ_REVERSED_BITFIELD_ORDERING*/ + +/*@}*/ +#endif + diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h new file mode 100644 index 000000000..a9485f5a4 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved2 : 2; + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + unsigned int reserved1 : 2; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h new file mode 100644 index 000000000..9c7bb5cb5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h @@ -0,0 +1,2134 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER +#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 +/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 +/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_chipRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 +/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_romRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h new file mode 100644 index 000000000..89e02c325 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + unsigned int reserved2 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 2; + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h new file mode 100644 index 000000000..08e255860 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h @@ -0,0 +1,387 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +#ifndef AQ_REG_GROUP_MAX_SIZES +#define AQ_REG_GROUP_MAX_SIZES + +#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD +#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD +#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD +#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD +#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD +#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA +#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD +#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD +#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD +#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD +#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD +#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD +#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD +#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD +#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD +#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD +#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD +#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD +#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA +#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD +#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD +#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD +#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD +#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD +#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD +#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD +#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD +#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD +#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD +#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD +#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD +#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD +#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD +#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD +#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD +#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD +#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD +#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA +#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD +#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD +#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD +#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD +#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD +#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD +#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD +#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD +#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA +#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA +#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA +#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD +#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD +#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD +#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD +#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD +#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD +#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD +#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD +#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD +#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD +#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD +#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD +#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD +#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD +#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD +#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD +#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD +#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD +#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD +#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA +#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD +#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD +#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD +#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD +#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD +#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD +#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD +#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD +#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD +#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD +#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD +#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD +#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD +#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD +#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD +#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD +#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD +#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD +#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD +#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD +#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD +#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD +#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD +#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD +#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD +#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD +#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD +#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD +#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD +#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD +#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD +#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD +#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD +#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD +#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD +#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD +#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD +#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD +#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD +#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD +#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD +#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD +#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD +#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD +#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD +#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD +#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD +#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD +#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD +#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD +#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD +#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD +#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD +#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD +#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD +#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD +#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD +#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD +#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD +#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD +#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD +#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD +#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD +#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD +#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD +#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD +#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD +#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA +#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD +#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD +#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD +#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD +#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD +#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD +#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD +#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA +#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD +#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD +#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD +#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD +#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD +#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD +#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD +#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD +#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD +#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD +#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD +#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD +#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD +#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD +#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD +#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD +#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD +#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD +#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD +#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD +#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD +#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD +#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA +#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD +#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA +#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD +#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD +#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD +#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD +#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD +#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD +#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD +#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD +#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD +#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD +#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD +#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD +#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD +#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD +#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD +#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD +#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD +#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD +#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD +#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD +#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD +#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD +#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD +#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD +#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD +#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD +#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD +#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD +#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD +#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD +#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD +#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD +#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD +#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD +#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD +#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD +#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD +#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD +#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD +#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD +#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD +#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD +#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD +#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD +#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD +#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD +#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD +#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD +#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD +#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD +#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD +#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD +#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD +#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD +#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD +#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD +#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD +#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD +#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD +#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD +#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD +#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD +#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD +#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD +#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD +#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD +#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD +#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD +#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD +#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD +#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD +#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD +#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD +#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD +#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD +#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD +#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD +#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD +#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD +#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD +#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD +#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD +#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD +#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD +#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD +#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD +#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD +#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD +#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD +#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD +#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD +#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD +#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD +#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD +#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD +#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD +#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD +#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD +#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD +#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD +#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD +#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD +#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD +#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD +#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD +#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD +#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD +#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD +#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD +#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h new file mode 100644 index 000000000..52a24e385 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h @@ -0,0 +1,69 @@ +/*AQ_RegMaps.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. +* +************************************************************************************/ + +/*! \file +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. + */ + +#ifndef AQ_REGISTERMAPS_HEADER +#define AQ_REGISTERMAPS_HEADER + +#include "AQ_User.h" +#include "AQ_RegGroupMaxSizes.h" + + +#ifndef AQ_REVERSED_BITFIELD_ORDERING +/* + * Include non-reversed header files (bitfields ordered from LSbit to MSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#else +/* + * Include reversed header files (bitfields ordered from MSbit to LSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers_reversed.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers_reversed.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h new file mode 100644 index 000000000..e0a2fa27b --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved0 : 14; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + unsigned int reserved0 : 3; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved3 : 2; + unsigned int reserved2 : 1; + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + unsigned int reserved0 : 11; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + unsigned int reserved0 : 9; + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved1 : 4; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved0 : 11; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved1 : 3; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + unsigned int reserved0 : 9; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 1; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + unsigned int reserved0 : 5; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved1 : 1; + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved2 : 1; + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h new file mode 100644 index 000000000..d9a4429d5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h @@ -0,0 +1,4413 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER +#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 +/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C +/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E +/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 +/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C +/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E +/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 +/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 +/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 +/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 +/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 +/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 +/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 +/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E +/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 +/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 +/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 +/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 +/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 +/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C +/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 +/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 +/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 +/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C +/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 +/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 +/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 +/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C +/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 +/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 +/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 +/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C +/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 +/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 +/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C +/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 +/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A +/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C +/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E +/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 +/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E +/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 +/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 +/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 +/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 +/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 +/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A +/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 +/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 +/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 +/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 + +/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 +/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E +/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 +/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 +/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 +/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 +/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 +/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C +/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 +/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 +/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 +/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C +/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 +/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 +/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 +/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C +/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 +/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 +/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 +/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C +/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 +/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 +/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C +/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 +/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 +/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rate 10 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 + +/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C +/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxData 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 +/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 +/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 +/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_dcMasterN 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ +#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ +#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_provisioningID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_dteStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_rate 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_dteStatusChange 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h new file mode 100644 index 000000000..f6fe99831 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved1 : 1; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + unsigned int reserved0 : 3; + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + unsigned int reserved2 : 1; + unsigned int reserved3 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved1 : 4; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 3; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + unsigned int reserved2 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/mdioBootLoadCLD.c b/qca/aq-fw-download/src/mdioBootLoadCLD.c new file mode 100644 index 000000000..a8e09d8c9 --- /dev/null +++ b/qca/aq-fw-download/src/mdioBootLoadCLD.c @@ -0,0 +1,193 @@ +/* mdioBootLoadCLD.c */ + +/************************************************************************************ +* Copyright (c) 2015 Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ +* +* $Revision: #12 $ +* +* $DateTime: 2014/05/19 15:34:49 $ +* +* $Author: joshd $ +* +* $Label: $ +* +************************************************************************************/ + +/*! \file +This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target +Aquantia PHY using the AQ_API. This program calls the API function:

+ + uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

+ +to boot load a cld flash image into an Aquantia PHY */ + +/*! \addtogroup mdioBootLoad +@{ +*/ + + + +/*! \def DEBUG +Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, +and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ +/* #define DEBUG */ + +/*! The debug source file name */ +#define DEBUG_FILENAME "HelloWorld.cld" + +/*! The debug PHY ID */ +#define DEBUG_PHY_ID 0 + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "AQ_API.h" +#include "AQ_PhyInterface.h" + +int sock; +char devname[7]; + +int sock_init() +{ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { + fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); + return -1; + } + + return 0; +} + +int main ( int argc, char **argp) +{ + /* declare local variables */ + FILE *pFile; + uint8_t* image; + uint8_t byte; + unsigned int PHY_ID; + AQ_Retcode resultCode; + AQ_Retcode resultCodes[4]; + uint32_t i; + uint32_t imageSize; + char sourceFileName[1000]; + AQ_API_Port targetPort0; + AQ_API_Port* targetPorts[1]; + AQ_API_Port broadcastPort; + unsigned int provisioningAddresses[1] = {0}; + uint32_t reg1, reg2; + + targetPorts[0] = &targetPort0; + + if(argc < 4) { + fprintf (stderr, "enter file name/netdev name/phy address\n"); + return (101); + } + + /*Copy the file name from command line arg*/ + if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { + fprintf (stderr, "Filename: %s too long \n", argp[1]); + return (101); + } + /*Copy the interface name from command line arg*/ + strlcpy (devname, argp[2], sizeof(devname)); + /*Get PHY Address from command line arg*/ + PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); + + /* FIXME: set port and device type */ + targetPort0.device = AQ_DEVICE_HHD; + targetPort0.PHY_ID = PHY_ID; + + broadcastPort.device = AQ_DEVICE_HHD; + broadcastPort.PHY_ID = PHY_ID; + + /* open the source in binary read mode */ + pFile = fopen(sourceFileName, "rb"); + if (pFile == NULL) + { + fprintf (stderr, "Unable to open source file %s\n", sourceFileName); + return (101); + } + fseek (pFile, 0, SEEK_END); + imageSize = ftell (pFile); + + image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); + fseek (pFile, 0, SEEK_SET); + + /* load the file */ + for (i = 0; i < imageSize; i++) + { + byte = (uint8_t) fgetc (pFile); + image[i] = byte; + } + fclose(pFile); + + + if (sock_init() < 0) + { + fprintf (stderr, "Unable to initialize interface\n"); + return (200); + } + + /* Write in the Auantia phy scratch pad register, + * read back the same reg and match the values written. + */ + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); + reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); + reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); + if(reg1 != 0xdead && reg2 != 0xbeaf) { + fprintf (stderr, "Scratchpad Read/Write test fail\n"); + return (101); + } + + /* call the boot-load function */ + resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); + + switch (resultCode) + { + case 0: + printf("Image load good - mailbox CRC-16 matches\n"); + free (image); + close(sock); + return 0; + + case 1: + fprintf (stderr, "CRC-16 on file is bad\n"); + free (image); + close(sock); + return 1; + + case 2: + fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); + free (image); + close(sock); + return 2; + + default: + fprintf (stderr, "Invalid return code\n"); + free (image); + close(sock); + } + return 12; +} +/*@}*/ diff --git a/qca/aq-fw-download/src/src/AQ_API.c b/qca/aq-fw-download/src/src/AQ_API.c new file mode 100644 index 000000000..89e73344f --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_API.c @@ -0,0 +1,1021 @@ +/*AQ_API.c*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains the code for all of the API functions defined in AQ_API.h +* +************************************************************************************/ + + +/*! \file +* This file contains the code for all of the API functions defined in AQ_API.h + */ + +#include +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_RegMacro.h" +#include "AQ_PlatformRoutines.h" +#include "AQ_RegMaps.h" +#include "AQ_ReturnCodes.h" + +#ifdef AQ_VERBOSE + #include + #include +#endif + + +#ifndef AQ_TIME_T_EXISTS + #ifndef AQ_MDIO_READS_PER_SECOND + #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! + #endif +#endif + +#ifdef AQ_TIME_T_EXISTS + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AQ_ENABLE_UP_BUSY_CHECKS + #ifdef AQ_VERBOSE + #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); + #else + #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ + #endif + + #ifdef AQ_TIME_T_EXISTS + #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + clock_t startTime; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + startTime = clock(); \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #else + #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + uint32_t numChecks; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + numChecks = 0; \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #endif + + /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return + * retval. retval should be a return code defined in AQ_ReturnCodes. */ + #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); + +#else + #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ + #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ + #define AQ_API_RETURN_UP_BUSY(retval) return retval; +#endif + + +/*! FW image version string maximum length. */ +#define AQ_VERSION_STRING_SIZE 0x40 + +/*! The byte offset from top of DRAM to the FW image version string. */ +#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 + +/*! The byte address, in processor memory, of the start of the IRAM segment. */ +#define AQ_IRAM_BASE_ADDRESS 0x40000000 + +/*! The byte address, in processor memory, of the start of the DRAM segment. */ +#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 + +/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 + +/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 + +/*! The offset, from the start of DRAM, where the provisioning block begins. */ +#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 + +/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ +#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C + +/*! The size of the space alloted within the PHY image for the provisioning table. */ +#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 + +/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ +#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 + +/*! The maximum number of ports that can be MDIO bootloaded at once. */ +#define AQ_MAX_NUM_PHY_IDS 48 + +/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ +#define AQ_MAX_FREEZE_CHECKS 2000 + +/*! The maximum size of the debug trace buffer. */ +#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 + +/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ +#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 + +/*! The maximum allowed number of times to poll for PIF mailbox status. */ +#define MAX_NUM_COMMAND_STATUS_POLLS 700 + +/* REGDOC_START */ + + +/********************************************************************************************************************** +* MDIO Boot Load +**********************************************************************************************************************/ + +const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; + +/*! \addtogroup writingImages + @{ +*/ + +/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableMDIO_BootLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress +) +{ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + + AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) + + + /* disable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); + + /* override the hop-count */ + AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, + /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + daisy_chainHop_countOverrideValue, provisioningAddress); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + enableDaisy_chainHop_countOverride, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, + AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); + + return; +} + + +/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO + * address to be used during the bootload process. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress, + /*! The PHY's MDIO address will be changed to this value during the + * bootload process. */ + unsigned int gangLoadAddress +) +{ + /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ + AQ_API_Variable(AQ_GlobalGeneralProvisioning) + + + /* Get ready for MDIO bootloading. */ + AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); + + /* Enable gangload mode. After doing this, the PHY will be + * addressable at the MDIO address indicated by gangLoadAddress. + * Now that the PHY is in gangload mode, MDIO reads are prohibited + * until AQ_API_DisableGangLoadMode is called. */ + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ + AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, + gangLoadMdioAddress, gangLoadAddress); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastAddressConfiguration, gangLoadAddress); + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastModeEnable, 1); + } + + return; +} + + +/*! Restore the PHY's MDIO address to the pin-specified value. Should be + * called when MDIO bootloading is complete, to return to normal MDIO + * addressing. + * This is a gang-load function, hence write-only! */ +void AQ_API_DisableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ + uint16_t origVal_GGP1 +) +{ + AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) + + + /* Restore the original value of globalGeneralProvisioning.u1, and set + * the MDIO address reset bit. This will cause the MDIO address to be + * reset to the value indicated by the pins. */ + AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioAddressReset, 1); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioBroadcastModeEnable, 0); + } + /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, + AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); + + /* The PHY has now exited gang-load mode. */ + return; +} + + +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort, + uint32_t* provTableSizePointer, + uint8_t* provTableImage +) +{ + /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ + /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ + /* operation */ + /*---------------------------------------------------------------------------------------------------------------*/ + + AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) + + AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) + AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) + + AQ_API_Port* port; + uint32_t primaryHeaderPtr = 0x00000000; + uint32_t primaryIramPtr = 0x00000000; + uint32_t primaryDramPtr = 0x00000000; + uint32_t primaryIramSize = 0x00000000; + uint32_t primaryDramSize = 0x00000000; + uint32_t terminatorPtr = 0x00000000; + uint32_t phyImageHeaderContentOffset; + uint32_t i; + uint32_t j; + uint32_t imageSize; + uint32_t provTableImageSize = 0; + uint32_t bytePointer; + uint32_t byteSize; + uint32_t dWordSize; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count + in order to ensure we don't exceed the maximum pending operations. */ +#endif + uint16_t msw; + uint16_t lsw; + uint16_t crc16Calculated; + uint16_t provTableCrc16Calculated; + uint16_t fileCRC; + uint16_t provTableFileCRC; + uint16_t mailboxCRC; + uint16_t mailboxWrite; + uint16_t bootLoadMode; + uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore + the AQ_GlobalGeneralProvisioning.u1 register values. */ + + + /* store the CRC-16 for the image, which is the last two bytes */ + imageSize = *imageSizePointer; + fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; + + /*------------------------------------- Check the image integrity ------------------------------------------------*/ + crc16Calculated = 0x0000; + for (i = 0; i < imageSize-2; i++) + { + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; + } + + if (crc16Calculated != fileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", + fileCRC, crc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } +#ifdef AQ_VERBOSE + else + { + printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); + } +#endif + + /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + provTableImageSize = (*provTableSizePointer) - 2; + provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | + provTableImage[provTableImageSize]; + + provTableCrc16Calculated = 0x0000; + for (i = 0; i < provTableImageSize; i++) + { + provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ + AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; + } + + if (provTableCrc16Calculated != provTableFileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", + provTableFileCRC, provTableCrc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } + #ifdef AQ_VERBOSE + else + { + printf ("CRC check good on provisioning table file (0x%04X)\n", + provTableCrc16Calculated); + } + #endif + } + + /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ + for (j = 0; j < numPorts; j++) + { + if (provisioningAddresses[j] > 47) + { + #ifdef AQ_VERBOSE + printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, + * so that we can restore it later after exiting gangload mode. */ + port = ports[j]; + /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ + recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); + + /* If any of the PHYs' GGP1 values don't match the others, set the appropriate + * error code and return. */ + if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) + { + #ifdef AQ_VERBOSE + printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", + recordedGGP1Values[0], recordedGGP1Values[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ + resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); + } + /* Set up the port context for using device-restricted macros while in + * gangload mode. */ + port = gangloadPort; + + /*------------------------------------- Stall the uP ------------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + + /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); + mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); + + /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ + primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; + + if (AQ_DEVICE_APPIA == port->device) + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; + else /* HHD */ + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + + primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; + primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; + primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; + primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; + + if (AQ_DEVICE_HHD == port->device) + { + primaryIramPtr += primaryHeaderPtr; + primaryDramPtr += primaryHeaderPtr; + } + +#ifdef AQ_VERBOSE + printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); + printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); + printf ("Primary Iram Size: 0x%x\n", primaryIramSize); + printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); + printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); +#endif + + /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + /* Locate the terminator of the built-in provisioning table */ + terminatorPtr = primaryDramPtr + + ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | + image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); + + #ifdef AQ_VERBOSE + printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); + #endif + + /* Check that the supplied provisioning table will fit within the alloted + * space. */ + if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + + provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) + { + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning + * table too large". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; + } + return AQ_RET_ERROR; + } + + /* Write the supplied provisioning table into the image, starting at the + * terminator address. */ + for (i = 0; i < provTableImageSize; i++) + { + image[terminatorPtr + i] = provTableImage[i]; + } + } + + /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ + /* clear the mailbox CRC */ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, + AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); + + crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ + + /* load the IRAM */ +#ifdef AQ_VERBOSE + printf ("\nLoading IRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryIramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryIramPtr; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + countPendingOps = 0; +#endif + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /* load the DRAM */ +#ifdef AQ_VERBOSE + printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); + printf ("\nLoading DRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryDramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryDramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ + AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); + + /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ + /* check to make sure the mailbox CRC matches the calculated CRC */ + /*foundMailboxCRCMismatch = False;*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ + mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); + if (mailboxCRC != crc16Calculated) + { + #ifdef AQ_VERBOSE + printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", + j, mailboxCRC, crc16Calculated); + #endif + /* Note that we can't just return here, because we still need to + * release the uPs for the other PHYs that might have been + * bootloaded successfully. */ + resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; + } + #ifdef AQ_VERBOSE + else + { + printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", + j, mailboxCRC); + resultCodes[j] = AQ_RET_OK; + } + #endif + } + + /*------------------------------------- Clear any resets ---------------------------------------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); + } + + /*------------------------------------- Release the uP -----------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* Need to wait at least 100us. */ + AQ_API_Wait(1, ports[0]); + + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); + for (j = 0; j < numPorts; j++) + { + if (AQ_DEVICE_APPIA == port->device) + { + /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the + * uP run stall override bit. If we did, the uP would stall. */ + /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ + AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); + if (bootLoadMode == 0x1) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + else + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); + } + } + else + { + /* For post-APPIA devices, always set the uP stall override bit to + * smooth over any packaging differences WRT the boot load pin. */ + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ + + /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ + for (j = 0; j < numPorts; j++) + { + if (resultCodes[j] != AQ_RET_OK) + return AQ_RET_ERROR; + } + + /* All ports were bootloaded successfully. */ + return AQ_RET_OK; +} + + +AQ_Retcode AQ_API_WriteBootLoadImage +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort +) +{ + return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, + provisioningAddresses, resultCodes, imageSizePointer, image, + gangload_MDIO_address, gangloadPort, NULL, NULL); +} + + +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +) +{ + + /* declare local variables */ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + AQ_API_Variable(AQ_GlobalReservedProvisioning) + + /* disable the hop-count override */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); + + /* enable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); + + return AQ_RET_OK; +} + +/*@}*/ + + +#ifdef __cplusplus +} +#endif diff --git a/qca/aq-fw-download/src/src/AQ_PhyInterface.c b/qca/aq-fw-download/src/src/AQ_PhyInterface.c new file mode 100644 index 000000000..a82c87e99 --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_PhyInterface.c @@ -0,0 +1,141 @@ +/* AQ_PhyInterface.c */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Revision: #12 $ +* +* $DateTime: 2015/02/25 15:34:49 $ +* +* $Label: $ +* +************************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "AQ_PhyInterface.h" +#include "AQ_PlatformRoutines.h" + +#define MII_ADDR_C45 (0x8000) + +extern int sock; +extern char devname[7]; + +static struct ifreq ifr; + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + mii.val_in = data; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + } + + return; +} + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + return -1; + } else { + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + } + + + return mii.val_out; +} + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * * in a platform-approriate way. AQ_API functions will call this function to + * * block for the specified period of time. If necessary, PHY register reads + * * may be performed on port to busy-wait. */ +void AQ_API_Wait( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) +{ + unsigned long long mirco = milliseconds *1000; + usleep(mirco); +} diff --git a/qca/ath11k-firmware/Makefile b/qca/ath11k-firmware/Makefile new file mode 100644 index 000000000..5ffb45f17 --- /dev/null +++ b/qca/ath11k-firmware/Makefile @@ -0,0 +1,123 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=ath11k-firmware +PKG_VERSION:=19 + +PKG_MAINTAINER:=John Crispin + +include $(INCLUDE_DIR)/package.mk + +define Package/ath11k-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:= +endef + +define Package/ath11k-firmware-ipq50xx +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ50xx devices + DEPENDS:=@TARGET_ipq807x_ipq50xx +endef + +define Package/ath11k-firmware-ipq50xx-spruce +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ50xx devices with spruce + DEPENDS:=@TARGET_ipq807x_ipq50xx +endef + +define Package/ath11k-firmware-ipq60xx +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ60xx devices + DEPENDS:=@TARGET_ipq807x_ipq60xx||TARGET_ipq60xx +endef + +define Package/ath11k-firmware-ipq807x +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ807x devices + DEPENDS:=@TARGET_ipq807x_ipq807x +endef + +define Package/ath11k-firmware-qcn6122 +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for QCN6122 devices + DEPENDS:=@TARGET_ipq807x_ipq50xx +endef + +define Package/ath11k-firmware-qcn9000 +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for QCN9000 devices + DEPENDS:=@TARGET_ipq807x +endef + +define Package/ath11k-firmware-ipq50xx/description +Standard ath11k firmware for IPQ50xx from QCA +endef + +define Package/ath11k-firmware-ipq50xx-spruce/description +Standard ath11k firmware for IPQ50xx/spruce from QCA +endef + +define Package/ath11k-firmware-ipq60xx/description +Standard ath11k firmware for IPQ60xx from QCA +endef + +define Package/ath11k-firmware-ipq807x/description +Standard ath11k firmware for IPQ807x from QCA +endef + +define Package/ath11k-firmware-qcn6122/description +Standard ath11k firmware for QCN6122 from QCA +endef + +define Package/ath11k-firmware-qcn9000/description +Standard ath11k firmware for QCN9000 from QCA +endef + +define Build/Compile + +endef + +define Package/ath11k-firmware-ipq50xx/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ5018 + $(INSTALL_DATA) ./files/IPQ5018/* \ + $(1)/lib/firmware/IPQ5018/ +endef + +define Package/ath11k-firmware-ipq50xx-spruce/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ5018 + $(INSTALL_DATA) ./files/IPQ5018_spruce/* \ + $(1)/lib/firmware/IPQ5018/ +endef + +define Package/ath11k-firmware-ipq60xx/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ6018 + $(INSTALL_DATA) ./files/IPQ6018/* \ + $(1)/lib/firmware/IPQ6018/ +endef + +define Package/ath11k-firmware-ipq807x/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 + $(INSTALL_DATA) ./files/IPQ8074/* \ + $(1)/lib/firmware/IPQ8074 +endef + +define Package/ath11k-firmware-qcn6122/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/qcn6122 + $(INSTALL_DIR) $(1)/lib/firmware/qcn6122 + $(INSTALL_DATA) ./files/QCN6122/* \ + $(1)/lib/firmware/qcn6122/ +endef + +define Package/ath11k-firmware-qcn9000/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ + $(INSTALL_DATA) ./files/QCN9000/* \ + $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ +endef + +$(eval $(call BuildPackage,ath11k-firmware-ipq50xx)) +$(eval $(call BuildPackage,ath11k-firmware-ipq50xx-spruce)) +$(eval $(call BuildPackage,ath11k-firmware-ipq60xx)) +$(eval $(call BuildPackage,ath11k-firmware-ipq807x)) +$(eval $(call BuildPackage,ath11k-firmware-qcn6122)) +$(eval $(call BuildPackage,ath11k-firmware-qcn9000)) diff --git a/qca/ath11k-firmware/files/IPQ5018/Notice.txt b/qca/ath11k-firmware/files/IPQ5018/Notice.txt new file mode 100644 index 000000000..b078d54cc --- /dev/null +++ b/qca/ath11k-firmware/files/IPQ5018/Notice.txt @@ -0,0 +1,802 @@ +This Notice.txt file contains certain notices of software components included with the software that Qualcomm Atheros, Inc. +(“Qualcomm Atheros”) is required to provide you. Except where prohibited by the open source license, the content of this +notices file is only provided to satisfy Qualcomm Atheros's attribution and notice requirement; your use of these software +components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as “Software”) is +subject to the terms of your agreement from Qualcomm Atheros. Compliance with all copyright laws and software license agreements +included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, trademarks, copyrights, or other intellectual property of +Qualcomm Incorporated or any of its subsidiaries. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated +trademarks are used with permission. Other products and brand names may be trademarks or registered trademarks of their respective +owners. + +-------------------- + + /* + * WPA definitions shared between hostapd and wpa_supplicant + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + + /* WPA/RSN - Shared functions for supplicant and authenticator + * EAP common peer/server definitions + * EAP peer state machines (RFC 4137) + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * AES-based functions + * + * + * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394) + * - One-Key CBC MAC (OMAC1) hash with AES-128 + * - AES-128 CTR mode encryption + * - AES-128 EAX mode encryption/decryption + * - AES-128 CBC + * + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * SHA1 hash implementation and interface functions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / wrapper functions for crypto libraries + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + * + * This file defines the cryptographic functions that need to be implemented + * for wpa_supplicant and hostapd. When TLS is not used, internal + * implementation of MD5, SHA1, and AES is used and no external libraries are + * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the + * crypto library used by the TLS implementation is expected to be used for + * non-TLS needs, too, in order to save space by not implementing these + * functions twice. + * + * Wrapper code for using each crypto library is in its own file (crypto*.c) + * and one of these files is build and linked in to provide the functions + * defined here. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - Common definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - WPA state machine and EAPOL-Key processing + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / Configuration file structures + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + /* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2008-2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Qualcomm Atheros, Inc. has chosen to take madwifi subject to the BSD license and terms. + * + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - Internal WPA state machine definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - WPA definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant/hostapd / common helper functions, etc. + * Copyright (c) 2002-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + * Australian Public Licence B (OZPLB) + * + * Version 1-0 + * + * Copyright (c) 2004, National ICT Australia + * Copyright (c) 2007, Open Kernel Labs, Inc. + * + * All rights reserved. + * + * Developed by: Embedded, Real-time and Operating Systems Program (ERTOS) + * National ICT Australia + * http://www.ertos.nicta.com.au + * + * Permission is granted by National ICT Australia, free of charge, to + * any person obtaining a copy of this software and any associated + * documentation files (the "Software") to deal with the Software without + * restriction, including (without limitation) the rights to use, copy, + * modify, adapt, merge, publish, distribute, communicate to the public, + * sublicense, and/or sell, lend or rent out copies of the Software, and + * to permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimers. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimers in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of National ICT Australia, nor the names of its + * contributors, may be used to endorse or promote products derived + * from this Software without specific prior written permission. + * + * EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT + * PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND + * NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS, + * WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS + * REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE, + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, + * THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF + * ERRORS, WHETHER OR NOT DISCOVERABLE. + * + * TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL + * NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL + * THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER + * LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR + * OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS + * OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR + * OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT, + * CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN + * CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER + * DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS + * CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS, + * DAMAGES OR OTHER LIABILITY. + * + * If applicable legislation implies representations, warranties, or + * conditions, or imposes obligations or liability on National ICT + * Australia or one of its contributors in respect of the Software that + * cannot be wholly or partly excluded, restricted or modified, the + * liability of National ICT Australia or the contributor is limited, to + * the full extent permitted by the applicable legislation, at its + * option, to: + * a. in the case of goods, any one or more of the following: + * i. the replacement of the goods or the supply of equivalent goods; + * ii. the repair of the goods; + * iii. the payment of the cost of replacing the goods or of acquiring + * equivalent goods; + * iv. the payment of the cost of having the goods repaired; or + * b. in the case of services: + * i. the supplying of the services again; or + * ii. the payment of the cost of having the services supplied again. + * + * The construction, validity and performance of this licence is governed + * by the laws in force in New South Wales, Australia. + +-------------------- + + * Copyright (c) 2002-2004, Karlsruhe University + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + /* + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + * + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +-------------------- + + * AUTHOR: Aaron D. Gifford - http://www.aarongifford.com/ + * + * Copyright (c) 2000-2001, Aaron D. Gifford + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTOR(S) ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTOR(S) BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1982, 1986, 1990, 1991, 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- +# Copyright (c) 2012-2015 Qualcomm Technologies, Inc. +# 2012-2015 Qualcomm Atheros, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +/* $OpenBSD: string.h,v 1.17 2006/01/06 18:53:04 millert Exp $ */ +/* $NetBSD: string.h,v 1.6 1994/10/26 00:56:30 cgd Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 5.10 (Berkeley) 3/9/91 + */ + +-------------------- + + // Copyright (c) 1991, 1993 + // The Regents of the University of California. All rights reserved. + // $ATH_LICENSE_NULL$ + // + // Redistribution and use in source and binary forms, with or without + // modification, are permitted provided that the following conditions + // are met: + // 1. Redistributions of source code must retain the above copyright + // notice, this list of conditions and the following disclaimer. + // 2. Redistributions in binary form must reproduce the above copyright + // notice, this list of conditions and the following disclaimer in the + // documentation and/or other materials provided with the distribution. + // 3. All advertising materials mentioning features or use of this software + // must display the following acknowledgement: + // This product includes software developed by the University of + // California, Berkeley and its contributors. + // 4. Neither the name of the University nor the names of its contributors + // may be used to endorse or promote products derived from this software + // without specific prior written permission. + // + // THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + // ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + // SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1998, 2010 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + +/* + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +-------------------- + +** Copyright (c) 2004-2010, Atheros Communications Inc. +** +** Permission to use, copy, modify, and/or distribute this software for any +** purpose with or without fee is hereby granted, provided that the above +** copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +** WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +** ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +** WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +** ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +** OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +** +** This module is the Atheros specific ioctl/iwconfig/iwpriv interface +** to the ATH object, normally instantiated as wifiX, where X is the +** instance number (e.g. wifi0, wifi1). +** +** This provides a mechanism to configure the ATH object within the +** Linux OS enviornment. This file is OS specific. + +-------------------- + +/* + * Copyright (c) 2012 Qualcomm Technologies, Inc. + * 2012 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +//- +// Copyright (c) 2002-2004 Sam Leffler, Errno Consulting +// All rights reserved. +// $ATH_LICENSE_NULL$ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer, +// without modification. +// 2. Redistributions in binary form must reproduce at minimum a disclaimer +// similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +// redistribution must be conditioned upon including a substantially +// similar Disclaimer requirement for further binary redistribution. +// 3. Neither the names of the above-listed copyright holders nor the names +// of any contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// Alternatively, this software may be distributed under the terms of the +// GNU General Public License ("GPL") version 2 as published by the Free +// Software Foundation. +// +// NO WARRANTY +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +// THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +// IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGES. + +-------------------- + + /* + * AES SIV (RFC 5297) + * Copyright (c) 2013 Cozybit, Inc. + * + * This software may be distributed under the terms of the BSD license. + */ + +-------------------- + + * Copyright 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + +-------------------- + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +-------------------- + +// This code implements the MD5 message-digest algorithm. +// The algorithm is due to Ron Rivest. This code was +// written by Colin Plumb in 1993, no copyright is claimed. +// This code is in the public domain; do with it what you wish. +// +// Equivalent code is available from RSA Data Security, Inc. +// This code has been tested against that, and is equivalent, +// except that you don't need to include two pages of legalese +// with every copy. +// + +-------------------- diff --git a/qca/ath11k-firmware/files/IPQ5018/fw_version.txt b/qca/ath11k-firmware/files/IPQ5018/fw_version.txt new file mode 100644 index 000000000..89949d659 --- /dev/null +++ b/qca/ath11k-firmware/files/IPQ5018/fw_version.txt @@ -0,0 +1 @@ +WLAN.HK.2.5.0.1-01192-QCAHKSWPL_SILICONZ-1 v1 diff --git a/qca/ath11k-firmware/files/IPQ5018/m3_fw.b00 b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b00 new file mode 100644 index 000000000..5b4dc0728 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b00 differ diff --git a/qca/ath11k-firmware/files/IPQ5018/m3_fw.b01 b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b01 new file mode 100644 index 000000000..3b1bc00f6 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b01 differ diff --git a/qca/ath11k-firmware/files/IPQ5018/m3_fw.b02 b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b02 new file mode 100644 index 000000000..c0ed8f7b7 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ5018/m3_fw.b02 differ diff --git a/qca/ath11k-firmware/files/IPQ5018/m3_fw.flist b/qca/ath11k-firmware/files/IPQ5018/m3_fw.flist new file mode 100644 index 000000000..94807ccc4 --- /dev/null +++ b/qca/ath11k-firmware/files/IPQ5018/m3_fw.flist @@ -0,0 +1,3 @@ +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b00 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b01 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b02 diff --git a/qca/ath11k-firmware/files/IPQ5018/m3_fw.mdt b/qca/ath11k-firmware/files/IPQ5018/m3_fw.mdt new file mode 100644 index 000000000..e7f8f321d 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+build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b21 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b22 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b23 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b25 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b26 diff --git a/qca/ath11k-firmware/files/IPQ5018/q6_fw.mdt b/qca/ath11k-firmware/files/IPQ5018/q6_fw.mdt new file mode 100644 index 000000000..ae9b07e5e Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ5018/q6_fw.mdt differ diff --git a/qca/ath11k-firmware/files/IPQ5018_spruce/Notice.txt b/qca/ath11k-firmware/files/IPQ5018_spruce/Notice.txt new file mode 100644 index 000000000..b078d54cc --- /dev/null +++ b/qca/ath11k-firmware/files/IPQ5018_spruce/Notice.txt @@ -0,0 +1,802 @@ +This Notice.txt file contains certain notices of software components included with the software that Qualcomm Atheros, Inc. +(“Qualcomm Atheros”) is required to provide you. Except where prohibited by the open source license, the content of this +notices file is only provided to satisfy Qualcomm Atheros's attribution and notice requirement; your use of these software +components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as “Software”) is +subject to the terms of your agreement from Qualcomm Atheros. Compliance with all copyright laws and software license agreements +included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, trademarks, copyrights, or other intellectual property of +Qualcomm Incorporated or any of its subsidiaries. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated +trademarks are used with permission. Other products and brand names may be trademarks or registered trademarks of their respective +owners. + +-------------------- + + /* + * WPA definitions shared between hostapd and wpa_supplicant + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + + /* WPA/RSN - Shared functions for supplicant and authenticator + * EAP common peer/server definitions + * EAP peer state machines (RFC 4137) + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * AES-based functions + * + * + * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394) + * - One-Key CBC MAC (OMAC1) hash with AES-128 + * - AES-128 CTR mode encryption + * - AES-128 EAX mode encryption/decryption + * - AES-128 CBC + * + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * SHA1 hash implementation and interface functions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / wrapper functions for crypto libraries + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + * + * This file defines the cryptographic functions that need to be implemented + * for wpa_supplicant and hostapd. When TLS is not used, internal + * implementation of MD5, SHA1, and AES is used and no external libraries are + * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the + * crypto library used by the TLS implementation is expected to be used for + * non-TLS needs, too, in order to save space by not implementing these + * functions twice. + * + * Wrapper code for using each crypto library is in its own file (crypto*.c) + * and one of these files is build and linked in to provide the functions + * defined here. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - Common definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - WPA state machine and EAPOL-Key processing + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / Configuration file structures + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + /* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2008-2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Qualcomm Atheros, Inc. has chosen to take madwifi subject to the BSD license and terms. + * + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - Internal WPA state machine definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - WPA definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant/hostapd / common helper functions, etc. + * Copyright (c) 2002-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + * Australian Public Licence B (OZPLB) + * + * Version 1-0 + * + * Copyright (c) 2004, National ICT Australia + * Copyright (c) 2007, Open Kernel Labs, Inc. + * + * All rights reserved. + * + * Developed by: Embedded, Real-time and Operating Systems Program (ERTOS) + * National ICT Australia + * http://www.ertos.nicta.com.au + * + * Permission is granted by National ICT Australia, free of charge, to + * any person obtaining a copy of this software and any associated + * documentation files (the "Software") to deal with the Software without + * restriction, including (without limitation) the rights to use, copy, + * modify, adapt, merge, publish, distribute, communicate to the public, + * sublicense, and/or sell, lend or rent out copies of the Software, and + * to permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimers. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimers in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of National ICT Australia, nor the names of its + * contributors, may be used to endorse or promote products derived + * from this Software without specific prior written permission. + * + * EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT + * PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND + * NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS, + * WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS + * REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE, + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, + * THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF + * ERRORS, WHETHER OR NOT DISCOVERABLE. + * + * TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL + * NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL + * THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER + * LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR + * OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS + * OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR + * OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT, + * CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN + * CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER + * DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS + * CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS, + * DAMAGES OR OTHER LIABILITY. + * + * If applicable legislation implies representations, warranties, or + * conditions, or imposes obligations or liability on National ICT + * Australia or one of its contributors in respect of the Software that + * cannot be wholly or partly excluded, restricted or modified, the + * liability of National ICT Australia or the contributor is limited, to + * the full extent permitted by the applicable legislation, at its + * option, to: + * a. in the case of goods, any one or more of the following: + * i. the replacement of the goods or the supply of equivalent goods; + * ii. the repair of the goods; + * iii. the payment of the cost of replacing the goods or of acquiring + * equivalent goods; + * iv. the payment of the cost of having the goods repaired; or + * b. in the case of services: + * i. the supplying of the services again; or + * ii. the payment of the cost of having the services supplied again. + * + * The construction, validity and performance of this licence is governed + * by the laws in force in New South Wales, Australia. + +-------------------- + + * Copyright (c) 2002-2004, Karlsruhe University + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + /* + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + * + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +-------------------- + + * AUTHOR: Aaron D. Gifford - http://www.aarongifford.com/ + * + * Copyright (c) 2000-2001, Aaron D. Gifford + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTOR(S) ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTOR(S) BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1982, 1986, 1990, 1991, 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- +# Copyright (c) 2012-2015 Qualcomm Technologies, Inc. +# 2012-2015 Qualcomm Atheros, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +/* $OpenBSD: string.h,v 1.17 2006/01/06 18:53:04 millert Exp $ */ +/* $NetBSD: string.h,v 1.6 1994/10/26 00:56:30 cgd Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 5.10 (Berkeley) 3/9/91 + */ + +-------------------- + + // Copyright (c) 1991, 1993 + // The Regents of the University of California. All rights reserved. + // $ATH_LICENSE_NULL$ + // + // Redistribution and use in source and binary forms, with or without + // modification, are permitted provided that the following conditions + // are met: + // 1. Redistributions of source code must retain the above copyright + // notice, this list of conditions and the following disclaimer. + // 2. Redistributions in binary form must reproduce the above copyright + // notice, this list of conditions and the following disclaimer in the + // documentation and/or other materials provided with the distribution. + // 3. All advertising materials mentioning features or use of this software + // must display the following acknowledgement: + // This product includes software developed by the University of + // California, Berkeley and its contributors. + // 4. Neither the name of the University nor the names of its contributors + // may be used to endorse or promote products derived from this software + // without specific prior written permission. + // + // THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + // ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + // SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1998, 2010 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + +/* + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +-------------------- + +** Copyright (c) 2004-2010, Atheros Communications Inc. +** +** Permission to use, copy, modify, and/or distribute this software for any +** purpose with or without fee is hereby granted, provided that the above +** copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +** WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +** ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +** WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +** ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +** OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +** +** This module is the Atheros specific ioctl/iwconfig/iwpriv interface +** to the ATH object, normally instantiated as wifiX, where X is the +** instance number (e.g. wifi0, wifi1). +** +** This provides a mechanism to configure the ATH object within the +** Linux OS enviornment. This file is OS specific. + +-------------------- + +/* + * Copyright (c) 2012 Qualcomm Technologies, Inc. + * 2012 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +//- +// Copyright (c) 2002-2004 Sam Leffler, Errno Consulting +// All rights reserved. +// $ATH_LICENSE_NULL$ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer, +// without modification. +// 2. Redistributions in binary form must reproduce at minimum a disclaimer +// similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +// redistribution must be conditioned upon including a substantially +// similar Disclaimer requirement for further binary redistribution. +// 3. Neither the names of the above-listed copyright holders nor the names +// of any contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// Alternatively, this software may be distributed under the terms of the +// GNU General Public License ("GPL") version 2 as published by the Free +// Software Foundation. +// +// NO WARRANTY +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +// THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +// IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGES. + +-------------------- + + /* + * AES SIV (RFC 5297) + * Copyright (c) 2013 Cozybit, Inc. + * + * This software may be distributed under the terms of the BSD license. + */ + +-------------------- + + * Copyright 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + +-------------------- + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +-------------------- + +// This code implements the MD5 message-digest algorithm. +// The algorithm is due to Ron Rivest. This code was +// written by Colin Plumb in 1993, no copyright is claimed. +// This code is in the public domain; do with it what you wish. +// +// Equivalent code is available from RSA Data Security, Inc. +// This code has been tested against that, and is equivalent, +// except that you don't need to include two pages of legalese +// with every copy. +// + +-------------------- diff --git a/qca/ath11k-firmware/files/IPQ5018_spruce/fw_version.txt b/qca/ath11k-firmware/files/IPQ5018_spruce/fw_version.txt new file mode 100644 index 000000000..c616f08b9 --- /dev/null +++ b/qca/ath11k-firmware/files/IPQ5018_spruce/fw_version.txt @@ -0,0 +1 @@ +WLAN.HK.2.5.r4-00745-QCAHKSWPL_SILICONZ-1 v1 diff --git a/qca/ath11k-firmware/files/IPQ5018_spruce/m3_fw.b00 b/qca/ath11k-firmware/files/IPQ5018_spruce/m3_fw.b00 new file mode 100644 index 000000000..5b4dc0728 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ5018_spruce/m3_fw.b00 differ diff --git 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Except where prohibited by the open source license, the content of this +notices file is only provided to satisfy Qualcomm Atheros's attribution and notice requirement; your use of these software +components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as “Software”) is +subject to the terms of your agreement from Qualcomm Atheros. Compliance with all copyright laws and software license agreements +included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, trademarks, copyrights, or other intellectual property of +Qualcomm Incorporated or any of its subsidiaries. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated +trademarks are used with permission. Other products and brand names may be trademarks or registered trademarks of their respective +owners. + +-------------------- + + /* + * WPA definitions shared between hostapd and wpa_supplicant + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + + /* WPA/RSN - Shared functions for supplicant and authenticator + * EAP common peer/server definitions + * EAP peer state machines (RFC 4137) + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * AES-based functions + * + * + * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394) + * - One-Key CBC MAC (OMAC1) hash with AES-128 + * - AES-128 CTR mode encryption + * - AES-128 EAX mode encryption/decryption + * - AES-128 CBC + * + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * SHA1 hash implementation and interface functions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / wrapper functions for crypto libraries + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + * + * This file defines the cryptographic functions that need to be implemented + * for wpa_supplicant and hostapd. When TLS is not used, internal + * implementation of MD5, SHA1, and AES is used and no external libraries are + * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the + * crypto library used by the TLS implementation is expected to be used for + * non-TLS needs, too, in order to save space by not implementing these + * functions twice. + * + * Wrapper code for using each crypto library is in its own file (crypto*.c) + * and one of these files is build and linked in to provide the functions + * defined here. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - Common definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - WPA state machine and EAPOL-Key processing + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / Configuration file structures + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + /* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2008-2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Qualcomm Atheros, Inc. has chosen to take madwifi subject to the BSD license and terms. + * + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - Internal WPA state machine definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - WPA definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant/hostapd / common helper functions, etc. + * Copyright (c) 2002-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + * Australian Public Licence B (OZPLB) + * + * Version 1-0 + * + * Copyright (c) 2004, National ICT Australia + * Copyright (c) 2007, Open Kernel Labs, Inc. + * + * All rights reserved. + * + * Developed by: Embedded, Real-time and Operating Systems Program (ERTOS) + * National ICT Australia + * http://www.ertos.nicta.com.au + * + * Permission is granted by National ICT Australia, free of charge, to + * any person obtaining a copy of this software and any associated + * documentation files (the "Software") to deal with the Software without + * restriction, including (without limitation) the rights to use, copy, + * modify, adapt, merge, publish, distribute, communicate to the public, + * sublicense, and/or sell, lend or rent out copies of the Software, and + * to permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimers. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimers in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of National ICT Australia, nor the names of its + * contributors, may be used to endorse or promote products derived + * from this Software without specific prior written permission. + * + * EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT + * PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND + * NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS, + * WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS + * REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE, + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, + * THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF + * ERRORS, WHETHER OR NOT DISCOVERABLE. + * + * TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL + * NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL + * THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER + * LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR + * OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS + * OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR + * OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT, + * CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN + * CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER + * DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS + * CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS, + * DAMAGES OR OTHER LIABILITY. + * + * If applicable legislation implies representations, warranties, or + * conditions, or imposes obligations or liability on National ICT + * Australia or one of its contributors in respect of the Software that + * cannot be wholly or partly excluded, restricted or modified, the + * liability of National ICT Australia or the contributor is limited, to + * the full extent permitted by the applicable legislation, at its + * option, to: + * a. in the case of goods, any one or more of the following: + * i. the replacement of the goods or the supply of equivalent goods; + * ii. the repair of the goods; + * iii. the payment of the cost of replacing the goods or of acquiring + * equivalent goods; + * iv. the payment of the cost of having the goods repaired; or + * b. in the case of services: + * i. the supplying of the services again; or + * ii. the payment of the cost of having the services supplied again. + * + * The construction, validity and performance of this licence is governed + * by the laws in force in New South Wales, Australia. + +-------------------- + + * Copyright (c) 2002-2004, Karlsruhe University + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + /* + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + * + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +-------------------- + + * AUTHOR: Aaron D. Gifford - http://www.aarongifford.com/ + * + * Copyright (c) 2000-2001, Aaron D. Gifford + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTOR(S) ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTOR(S) BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1982, 1986, 1990, 1991, 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- +# Copyright (c) 2012-2015 Qualcomm Technologies, Inc. +# 2012-2015 Qualcomm Atheros, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +/* $OpenBSD: string.h,v 1.17 2006/01/06 18:53:04 millert Exp $ */ +/* $NetBSD: string.h,v 1.6 1994/10/26 00:56:30 cgd Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 5.10 (Berkeley) 3/9/91 + */ + +-------------------- + + // Copyright (c) 1991, 1993 + // The Regents of the University of California. All rights reserved. + // $ATH_LICENSE_NULL$ + // + // Redistribution and use in source and binary forms, with or without + // modification, are permitted provided that the following conditions + // are met: + // 1. Redistributions of source code must retain the above copyright + // notice, this list of conditions and the following disclaimer. + // 2. Redistributions in binary form must reproduce the above copyright + // notice, this list of conditions and the following disclaimer in the + // documentation and/or other materials provided with the distribution. + // 3. All advertising materials mentioning features or use of this software + // must display the following acknowledgement: + // This product includes software developed by the University of + // California, Berkeley and its contributors. + // 4. Neither the name of the University nor the names of its contributors + // may be used to endorse or promote products derived from this software + // without specific prior written permission. + // + // THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + // ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + // SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1998, 2010 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + +/* + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +-------------------- + +** Copyright (c) 2004-2010, Atheros Communications Inc. +** +** Permission to use, copy, modify, and/or distribute this software for any +** purpose with or without fee is hereby granted, provided that the above +** copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +** WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +** ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +** WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +** ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +** OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +** +** This module is the Atheros specific ioctl/iwconfig/iwpriv interface +** to the ATH object, normally instantiated as wifiX, where X is the +** instance number (e.g. wifi0, wifi1). +** +** This provides a mechanism to configure the ATH object within the +** Linux OS enviornment. This file is OS specific. + +-------------------- + +/* + * Copyright (c) 2012 Qualcomm Technologies, Inc. + * 2012 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +//- +// Copyright (c) 2002-2004 Sam Leffler, Errno Consulting +// All rights reserved. +// $ATH_LICENSE_NULL$ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer, +// without modification. +// 2. Redistributions in binary form must reproduce at minimum a disclaimer +// similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +// redistribution must be conditioned upon including a substantially +// similar Disclaimer requirement for further binary redistribution. +// 3. Neither the names of the above-listed copyright holders nor the names +// of any contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// Alternatively, this software may be distributed under the terms of the +// GNU General Public License ("GPL") version 2 as published by the Free +// Software Foundation. +// +// NO WARRANTY +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +// THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +// IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGES. + +-------------------- + + /* + * AES SIV (RFC 5297) + * Copyright (c) 2013 Cozybit, Inc. + * + * This software may be distributed under the terms of the BSD license. + */ + +-------------------- + + * Copyright 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + +-------------------- + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +-------------------- + +// This code implements the MD5 message-digest algorithm. +// The algorithm is due to Ron Rivest. This code was +// written by Colin Plumb in 1993, no copyright is claimed. +// This code is in the public domain; do with it what you wish. +// +// Equivalent code is available from RSA Data Security, Inc. +// This code has been tested against that, and is equivalent, +// except that you don't need to include two pages of legalese +// with every copy. +// + +-------------------- diff --git a/qca/ath11k-firmware/files/IPQ6018/m3_fw.b00 b/qca/ath11k-firmware/files/IPQ6018/m3_fw.b00 new file mode 100644 index 000000000..b000539b7 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ6018/m3_fw.b00 differ diff --git a/qca/ath11k-firmware/files/IPQ6018/m3_fw.b01 b/qca/ath11k-firmware/files/IPQ6018/m3_fw.b01 new file mode 100644 index 000000000..aaa43f532 Binary files /dev/null and b/qca/ath11k-firmware/files/IPQ6018/m3_fw.b01 differ diff --git a/qca/ath11k-firmware/files/IPQ6018/m3_fw.b02 b/qca/ath11k-firmware/files/IPQ6018/m3_fw.b02 new file mode 100644 index 000000000..5bed604af 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a/qca/ath11k-firmware/files/QCN6122/Notice.txt b/qca/ath11k-firmware/files/QCN6122/Notice.txt new file mode 100644 index 000000000..b078d54cc --- /dev/null +++ b/qca/ath11k-firmware/files/QCN6122/Notice.txt @@ -0,0 +1,802 @@ +This Notice.txt file contains certain notices of software components included with the software that Qualcomm Atheros, Inc. +(“Qualcomm Atheros”) is required to provide you. Except where prohibited by the open source license, the content of this +notices file is only provided to satisfy Qualcomm Atheros's attribution and notice requirement; your use of these software +components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as “Software”) is +subject to the terms of your agreement from Qualcomm Atheros. Compliance with all copyright laws and software license agreements +included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, trademarks, copyrights, or other intellectual property of +Qualcomm Incorporated or any of its subsidiaries. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated +trademarks are used with permission. Other products and brand names may be trademarks or registered trademarks of their respective +owners. + +-------------------- + + /* + * WPA definitions shared between hostapd and wpa_supplicant + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + + /* WPA/RSN - Shared functions for supplicant and authenticator + * EAP common peer/server definitions + * EAP peer state machines (RFC 4137) + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * AES-based functions + * + * + * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394) + * - One-Key CBC MAC (OMAC1) hash with AES-128 + * - AES-128 CTR mode encryption + * - AES-128 EAX mode encryption/decryption + * - AES-128 CBC + * + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * SHA1 hash implementation and interface functions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / wrapper functions for crypto libraries + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + * + * This file defines the cryptographic functions that need to be implemented + * for wpa_supplicant and hostapd. When TLS is not used, internal + * implementation of MD5, SHA1, and AES is used and no external libraries are + * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the + * crypto library used by the TLS implementation is expected to be used for + * non-TLS needs, too, in order to save space by not implementing these + * functions twice. + * + * Wrapper code for using each crypto library is in its own file (crypto*.c) + * and one of these files is build and linked in to provide the functions + * defined here. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - Common definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - WPA state machine and EAPOL-Key processing + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / Configuration file structures + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + /* + * Copyright (c) 2011 Qualcomm Technologies, Inc. + * 2008-2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * Qualcomm Atheros, Inc. has chosen to take madwifi subject to the BSD license and terms. + * + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - Internal WPA state machine definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - WPA definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant/hostapd / common helper functions, etc. + * Copyright (c) 2002-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + * Australian Public Licence B (OZPLB) + * + * Version 1-0 + * + * Copyright (c) 2004, National ICT Australia + * Copyright (c) 2007, Open Kernel Labs, Inc. + * + * All rights reserved. + * + * Developed by: Embedded, Real-time and Operating Systems Program (ERTOS) + * National ICT Australia + * http://www.ertos.nicta.com.au + * + * Permission is granted by National ICT Australia, free of charge, to + * any person obtaining a copy of this software and any associated + * documentation files (the "Software") to deal with the Software without + * restriction, including (without limitation) the rights to use, copy, + * modify, adapt, merge, publish, distribute, communicate to the public, + * sublicense, and/or sell, lend or rent out copies of the Software, and + * to permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimers. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimers in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of National ICT Australia, nor the names of its + * contributors, may be used to endorse or promote products derived + * from this Software without specific prior written permission. + * + * EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT + * PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND + * NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS, + * WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS + * REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE, + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, + * THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF + * ERRORS, WHETHER OR NOT DISCOVERABLE. + * + * TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL + * NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL + * THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER + * LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR + * OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS + * OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR + * OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT, + * CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN + * CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER + * DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS + * CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS, + * DAMAGES OR OTHER LIABILITY. + * + * If applicable legislation implies representations, warranties, or + * conditions, or imposes obligations or liability on National ICT + * Australia or one of its contributors in respect of the Software that + * cannot be wholly or partly excluded, restricted or modified, the + * liability of National ICT Australia or the contributor is limited, to + * the full extent permitted by the applicable legislation, at its + * option, to: + * a. in the case of goods, any one or more of the following: + * i. the replacement of the goods or the supply of equivalent goods; + * ii. the repair of the goods; + * iii. the payment of the cost of replacing the goods or of acquiring + * equivalent goods; + * iv. the payment of the cost of having the goods repaired; or + * b. in the case of services: + * i. the supplying of the services again; or + * ii. the payment of the cost of having the services supplied again. + * + * The construction, validity and performance of this licence is governed + * by the laws in force in New South Wales, Australia. + +-------------------- + + * Copyright (c) 2002-2004, Karlsruhe University + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + /* + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + * + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +-------------------- + + * AUTHOR: Aaron D. Gifford - http://www.aarongifford.com/ + * + * Copyright (c) 2000-2001, Aaron D. Gifford + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTOR(S) ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTOR(S) BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1982, 1986, 1990, 1991, 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- +# Copyright (c) 2012-2015 Qualcomm Technologies, Inc. +# 2012-2015 Qualcomm Atheros, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +/* $OpenBSD: string.h,v 1.17 2006/01/06 18:53:04 millert Exp $ */ +/* $NetBSD: string.h,v 1.6 1994/10/26 00:56:30 cgd Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 5.10 (Berkeley) 3/9/91 + */ + +-------------------- + + // Copyright (c) 1991, 1993 + // The Regents of the University of California. All rights reserved. + // $ATH_LICENSE_NULL$ + // + // Redistribution and use in source and binary forms, with or without + // modification, are permitted provided that the following conditions + // are met: + // 1. Redistributions of source code must retain the above copyright + // notice, this list of conditions and the following disclaimer. + // 2. Redistributions in binary form must reproduce the above copyright + // notice, this list of conditions and the following disclaimer in the + // documentation and/or other materials provided with the distribution. + // 3. All advertising materials mentioning features or use of this software + // must display the following acknowledgement: + // This product includes software developed by the University of + // California, Berkeley and its contributors. + // 4. Neither the name of the University nor the names of its contributors + // may be used to endorse or promote products derived from this software + // without specific prior written permission. + // + // THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + // ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + // SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1998, 2010 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + +/* + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +-------------------- + +** Copyright (c) 2004-2010, Atheros Communications Inc. +** +** Permission to use, copy, modify, and/or distribute this software for any +** purpose with or without fee is hereby granted, provided that the above +** copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +** WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +** ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +** WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +** ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +** OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +** +** This module is the Atheros specific ioctl/iwconfig/iwpriv interface +** to the ATH object, normally instantiated as wifiX, where X is the +** instance number (e.g. wifi0, wifi1). +** +** This provides a mechanism to configure the ATH object within the +** Linux OS enviornment. This file is OS specific. + +-------------------- + +/* + * Copyright (c) 2012 Qualcomm Technologies, Inc. + * 2012 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +//- +// Copyright (c) 2002-2004 Sam Leffler, Errno Consulting +// All rights reserved. +// $ATH_LICENSE_NULL$ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer, +// without modification. +// 2. Redistributions in binary form must reproduce at minimum a disclaimer +// similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +// redistribution must be conditioned upon including a substantially +// similar Disclaimer requirement for further binary redistribution. +// 3. Neither the names of the above-listed copyright holders nor the names +// of any contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// Alternatively, this software may be distributed under the terms of the +// GNU General Public License ("GPL") version 2 as published by the Free +// Software Foundation. +// +// NO WARRANTY +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +// THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +// IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGES. + +-------------------- + + /* + * AES SIV (RFC 5297) + * Copyright (c) 2013 Cozybit, Inc. + * + * This software may be distributed under the terms of the BSD license. + */ + +-------------------- + + * Copyright 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + +-------------------- + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +-------------------- + +// This code implements the MD5 message-digest algorithm. +// The algorithm is due to Ron Rivest. This code was +// written by Colin Plumb in 1993, no copyright is claimed. +// This code is in the public domain; do with it what you wish. +// +// Equivalent code is available from RSA Data Security, Inc. +// This code has been tested against that, and is equivalent, +// except that you don't need to include two pages of legalese +// with every copy. +// + +-------------------- diff --git a/qca/ath11k-firmware/files/QCN6122/m3_fw.b00 b/qca/ath11k-firmware/files/QCN6122/m3_fw.b00 new file mode 100644 index 000000000..6b45772e9 Binary files /dev/null and b/qca/ath11k-firmware/files/QCN6122/m3_fw.b00 differ diff --git a/qca/ath11k-firmware/files/QCN6122/m3_fw.b01 b/qca/ath11k-firmware/files/QCN6122/m3_fw.b01 new file mode 100644 index 000000000..430272775 Binary files /dev/null and b/qca/ath11k-firmware/files/QCN6122/m3_fw.b01 differ diff --git a/qca/ath11k-firmware/files/QCN6122/m3_fw.b02 b/qca/ath11k-firmware/files/QCN6122/m3_fw.b02 new file mode 100644 index 000000000..50c8fa4ef Binary files /dev/null and b/qca/ath11k-firmware/files/QCN6122/m3_fw.b02 differ diff --git a/qca/ath11k-firmware/files/QCN6122/m3_fw.flist b/qca/ath11k-firmware/files/QCN6122/m3_fw.flist new file mode 100644 index 000000000..be3c989af --- /dev/null +++ b/qca/ath11k-firmware/files/QCN6122/m3_fw.flist @@ -0,0 +1,3 @@ +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b00 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b01 +build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b02 diff --git a/qca/ath11k-firmware/files/QCN6122/m3_fw.mdt b/qca/ath11k-firmware/files/QCN6122/m3_fw.mdt new file mode 100644 index 000000000..e9fe01524 Binary files /dev/null and b/qca/ath11k-firmware/files/QCN6122/m3_fw.mdt differ diff --git a/qca/ath11k-firmware/files/QCN9000/Data.msc b/qca/ath11k-firmware/files/QCN9000/Data.msc new file mode 100644 index 000000000..84ec80ade --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/Data.msc @@ -0,0 +1,7150 @@ +VERSION:637829981 + +2,,[ LMGoProcessing.c : 62 ] LM_DBG: NULL pdev return +1,Ii,[ LMGoProcessing.c : 78 ] LM_DBG: ABI on-period tx_duration_data %ld(US) current_time(MS) %d +0,Ii,[ LMGoProcessing.c : 295 ] LM_DBG: ABI off-period tx_duration_data(US) %ld curTime(MS) %d +64,Ii,[ cmdProcessTlv2.c : 5185 ] %s: #### Getting cal version:bdfvertype: %d ! + +63,iii,[ cmdProcessTlv2.c : 2284 ] PHYDBGdump2Handler(Phy:%d, Option:%d capture_bank:%d) +62,IiI,[ cmdProcessTlv2.c : 2292 ] ### data_ptr %p size %d status 0x%x + +61,Ii,[ cmdProcessTlv2.c : 2301 ] ### data_ptr %p stream_cnt %d + +60,,[ cmdProcessTlv2.c : 2304 ] ### Data buffer stream ended + +59,ii,[ cmdProcessTlv2.c : 2696 ] PHYDBGdumpHandler(Phy:%d, Option:%d) + +58,IiI,[ cmdProcessTlv2.c : 2704 ] ### data_ptr %p size %d status 0x%x + +57,Ii,[ cmdProcessTlv2.c : 2713 ] ### data_ptr %p stream_cnt %d + +56,,[ cmdProcessTlv2.c : 2716 ] ### Data buffer stream ended + +55,Ii,[ cmdProcessTlv2.c : 5162 ] %s :set cal version , bdfvertype: %d ! + +54,i,[ cmdProcessTlv2.c : 4422 ] Channel index out of bounds %d +53,i,[ cmdProcessTlv2.c : 4430 ] Power offset Index out of bounds %d +52,ii,[ cmdProcessTlv2.c : 4438 ] 2G index %d flag %d +51,ii,[ cmdProcessTlv2.c : 4451 ] values written 2G %d 5G %d +50,i,[ cmdProcessTlv2.c : 4512 ] Channel index out of bounds %d +49,i,[ cmdProcessTlv2.c : 4593 ] Channel index out of bounds %d +48,i,[ cmdProcessTlv2.c : 4608 ] Target Power index out of bounds %d +47,i,[ cmdProcessTlv2.c : 4623 ] Gain index out of bounds %d +46,,[ cmdProcessTlv2.c : 4939 ] OPC_OTP_WRITE:Ready to send response! + +45,I,[ cmdProcessTlv2.c : 4940 ] OTP Write status, 0x%x +44,,[ cmdProcessTlv2.c : 4952 ] OPC_OTP_WRITE:send response done! + +43,,[ cmdProcessTlv2.c : 3341 ] bdGetSizeHandler + +42,iIii,[ cmdProcessTlv2.c : 3368 ] bdReadHandler: bdSize %d, offset 0x%x, size %d, source %d + +41,i,[ cmdProcessTlv2.c : 3409 ] error in bdReadHandler: status %d + +40,Ii,[ cmdProcessTlv2.c : 4839 ] bdWriteHandler: offset 0x%x, size %d + +39,ii,[ cmdProcessTlv2.c : 2588 ] combCalGroupHandler(): phyId = %d; cmdid = %d +38,IIII,[ cmdProcessTlv2.c : 5064 ] %s: offset %ld, size %ld, totalsize %ld +37,III,[ cmdProcessTlv2.c : 5133 ] %s: offset %ld, size %ld +36,,[ cmdProcessTlv2.c : 213 ] ftm_termperature_timer_handler::MAC sleeping +35,,[ cmdProcessTlv2.c : 1939 ] UTFCMD: genericUtfCmdHandler +34,,[ cmdProcessTlv2.c : 1975 ] Failed Rx Stop +33,ii,[ cmdProcessTlv2.c : 1989 ] UTFCMD: UTF_CMD_CHANGECHAINMASK phyId=%d tcmd_state[phyId].specialCmds=%d +32,i,[ cmdProcessTlv2.c : 2018 ] UTFCMD: UTF_CMD_WARM_RESET phid %d +31,ii,[ cmdProcessTlv2.c : 2025 ] UTFCMD: UTF_CMD_SET_MM_CMD_SEQID phid %d MMSeqID %d +30,,[ cmdProcessTlv2.c : 2032 ] ### genericUtfCmdHandler: InValid CmdID#### +29,,[ cmdProcessTlv2.c : 2046 ] UTFCMD: genericUtfCmdHandler exit +28,i,[ cmdProcessTlv2.c : 542 ] FATAL ERROR!! Trying to access phy %d which is not present +27,i,[ cmdProcessTlv2.c : 553 ] FATAL ERROR!! Trying to access phy %d which is inactive +26,I,[ cmdProcessTlv2.c : 4693 ] modifyBDFOTPFlagsHandler: modifyBdfOtpFlags 0x%x +25,,[ cmdProcessTlv2.c : 4711 ] modifyBDFOTPFlagsHandler: pCmdStream is NULL +24,,[ cmdProcessTlv2.c : 4045 ] OFDMA TonePlan + +23,,[ cmdProcessTlv2.c : 5235 ] Failed Rx Stop +22,ii,[ cmdProcessTlv2.c : 675 ] FTM :: pktgen_complete_timer_handler: pktgen_complete_timer_handler: Pktgen Tx STOP completion callback failure for phyId %d g_pktgen_done_assert_count %d +21,iiiiiii,[ cmdProcessTlv2.c : 1306 ] rxHandler: phyId %d rxMode %d wlanMode %d freq %d freq2 %d chainMask %d wifiStandard %d +20,i,[ cmdProcessTlv2.c : 1320 ] RX operation not allowed on phyID %d one operation ongoing +19,,[ cmdProcessTlv2.c : 4730 ] #### per chain forced pwr TLV called! + +18,iI,[ cmdProcessTlv2.c : 3032 ] setPhyRfModeHandler: DBS/SBS is not supported, phyRfMode %d status 0x%x +17,I,[ cmdProcessTlv2.c : 1467 ] pdev %u +16,I,[ cmdProcessTlv2.c : 1493 ] pdev %u +15,iiiiiII,[ cmdProcessTlv2.c : 1509 ] curChan->band_center_freq1 %d, curChan->band_center_freq2 %d, PHYRF_BW_IDX(curChan) %d curChan->phy_mode %d num_20_bw %d rx_CM %x, tx_CM %x +14,ii,[ cmdProcessTlv2.c : 1577 ] pilot_evm pilot_evm_dB_mean[%d] = %d +13,I,[ cmdProcessTlv2.c : 637 ] FTM :: tlv2SendTxStatus: timestamp = %ld +12,iiii,[ cmdProcessTlv2.c : 3816 ] Tx Gain Control:Chain %d, Gain %d, dacGain %d, forceCal %d + +11,i,[ cmdProcessTlv2.c : 786 ] FTM phyid %d :: txHandler invoked + +10,i,[ cmdProcessTlv2.c : 845 ] FTM :: txHandler: TX operation not allowed on phyID %d one operation ongoing +9,IIII,[ cmdProcessTlv2.c : 1024 ] FTM :: txHandler: ret:0x%x, ret1:0x%x, ret2:0x%x, ret3:0x%x +8,ii,[ cmdProcessTlv2.c : 1043 ] FTM :: txHandler dev running state=%d iterations_taken_to_flush=%d +7,iI,[ cmdProcessTlv2.c : 1056 ] FTM :: txHandler: Sent response to host with status =%d, timestamp =%ld +6,iiiiiiiI,[ cmdProcessTlv2.c : 795 ] FTM :: txHandler: phyId %d txMode %d freq %d freq2 %d wlanMode %d chainMask %d wifiStandard %d timestamp =%ld +5,iiI,[ cmdProcessTlv2.c : 1098 ] FTM :: txStatusHandler: INSIDE txStatusHandler phyId =%d pParms->needReport=%d timestamp : %u +4,ii,[ cmdProcessTlv2.c : 1112 ] FTM :: txStatusHandler: pParms->needReport=%d pParms->stopTx=%d +3,IIII,[ cmdProcessTlv2.c : 1143 ] FTM :: txStatusHandler: ret:0x%x, ret1:0x%x, ret2:0x%x, ret3:0x%x +66,II,[ cmdProcessing.c : 283 ] FTM_DEBUG :: txCmdProcessor, TxMiscFlags : 0x%x txParms->aifsn=0x%x +65,iiiii,[ cmdProcessing.c : 391 ] FTM :: txCmdProcessor channel=%d txPwr=%d dataRrate=%d numPkt=%d txChain=%d + +68,iIi,[ dpdTuning.c : 283 ] GetDpdLoopbackInfoHandler phyId %d chainMask 0x%x GlutIdx %d +67,ii,[ dpdTuning.c : 312 ] GetDpdLoopbackInfoHandler nmse %d, nmse_nondpd %d +105,I,[ tcmd.c : 5683 ] Invalid pdev %lu +104,ii,[ tcmd.c : 4861 ] ftm_txoff_dur_calc: txtime = %d->%d +103,,[ tcmd.c : 1292 ] A: NEW COMMAND ISSUED +102,,[ tcmd.c : 2838 ] ERROR: payloadLenEHT is NULL +101,,[ tcmd.c : 2850 ] ERROR: payloadLen is NULL +100,iiiiI,[ tcmd.c : 2860 ] [UL-OFDMA]ruIdx=%d, dataRate=%d, NSS=%d, pktSz=%d, miscFlags=0x%x +99,,[ tcmd.c : 4989 ] Could not find valid ruIdx in tone plan +98,,[ tcmd.c : 1663 ] Error Unknown PHY mode +97,i,[ tcmd.c : 4077 ] tcmd_cont_rx_begin: phyId=%d, chain mask 0 + +96,i,[ tcmd.c : 4126 ] tcmd_cont_rx_begin: phyId=%d, tcmd_setup_channel failure + +95,Ii,[ tcmd.c : 3665 ] tcmd_cont_rx_cmd - flags 0x%x; act %d +94,ii,[ tcmd.c : 3673 ] aId[%d] = %d +93,,[ tcmd.c : 3679 ] Could not find valid aID in tone plan +92,ii,[ tcmd.c : 3935 ] pilot_evm g_ftmrxstats[phyId].pilotEvmDbMean[%d] = %d +91,iii,[ tcmd.c : 3137 ] TCMD: TPC force glutindex: chain%d: gainindex%d: dacgain=%d + +90,iii,[ tcmd.c : 3161 ] PAPRD TCMD: Chain %d Glut Idx %d Gain Idx %d + +89,iiiii,[ tcmd.c : 3225 ] TCMD: mode %d pkt type %d, Pkt size %d, PPDU duration %d, max PPDU duration %d +88,iiii,[ tcmd.c : 3276 ] TCMD: Setup chan failed: freq %d, freq2 %d, wlanMd %d, bw %d + +87,,[ tcmd.c : 3595 ] Error tcmd_cont_txunsupport mode! +86,ii,[ tcmd.c : 5555 ] CW enable %d, gain idx %d +85,i,[ tcmd.c : 4721 ] Enabled SIFS bursting for Tx99 (dpd_tx_counter=%d) +84,i,[ tcmd.c : 1772 ] Unknown WLAN mode %d +83,i,[ tcmd.c : 1822 ] Unknown WLAN mode %d +82,i,[ tcmd.c : 1860 ] Invalid frequency %d +81,i,[ tcmd.c : 2355 ] pktType Invalid %d +80,IiiiiII,[ tcmd.c : 2562 ] wlanMode: %lu ch: %d freq1 %d freq2 %d, fcMode %d phy mode 0x%x, chan flags 0x%x +79,i,[ tcmd.c : 2608 ] 165 MHz frequency %d +78,i,[ tcmd.c : 2612 ] Invalid frequency %d +77,iiII,[ tcmd.c : 4352 ] tcmd_setup_channel_real: phyId=%d,Failure: chan.phy_mode=%d, rx_tcmdParms.u.para.pktType=0x%x, rx_tcmdParms.miscFlags=0x%x + +76,II,[ tcmd.c : 4508 ] tcmd() Before GI 0x%x LTF 0x%x +75,II,[ tcmd.c : 4543 ] tcmd() After GI 0x%x LTF 0x%x +74,,[ tcmd.c : 1477 ] tcmd_tx_complete_handler() tcmd_tx_irq: spurious tx irq +73,iI,[ tcmd.c : 1547 ] A: TCMD TX COMP CB - MADE STOP TX = 2 phyId [%d] | Time : %u +72,I,[ tcmd.c : 5143 ] tcmd() Before RC flag 0x%x +71,Iii,[ tcmd.c : 5164 ] tcmd() After RC flag 0x%x GI %d LTF %d +70,ii,[ tcmd.c : 5272 ] FTM_DEBUG :: TCMD :: FTM Mode %d Bursting Mode %d +69,ii,[ tcmd.c : 5364 ] [UL-OFDMA]gi=%d, ltf=%d +112,,[ tcmd_rx.c : 337 ] RX_TCMD: RETURN if((g_ftm_frame_enacap_config[phyId].da_addr == NULL) || (g_ftm_frame_enacap_config[phyId].bss_addr == NULL)) +111,,[ tcmd_rx.c : 366 ] RX WAL PEER A_PANIC +110,ii,[ tcmd_rx.c : 385 ] RX_TCMD: wal_vdev_attach vdevId[%d]=%d +109,,[ tcmd_rx.c : 397 ] RX_TCMD: wal_peer_alloc rx peer 1 +108,,[ tcmd_rx.c : 407 ] RX_TCMD: wal_peer_alloc rx peer 2 +107,,[ tcmd_rx.c : 354 ] RX_TCMD: page fault condition, all vdev is null +106,,[ tcmd_rx.c : 363 ] RX_TCMD: Inside if(g_tcmd_wal_rx_ctxt[phyId].vdev == NULL) +130,ii,[ tcmd_tx.c : 1443 ] [MU] sched_algo_mu_tx_peer_assoc() peer[%d] AID %d +129,,[ tcmd_tx.c : 1559 ] A: INSIDE tcmd_wal_peer_free +128,ii,[ tcmd_tx.c : 999 ] tcmd_wal_setup_data_rate: rc %d invalid for freq %d +127,ii,[ tcmd_tx.c : 426 ] ftm_tid_create_handler: phyId %d, tid %d +126,,[ tcmd_tx.c : 1584 ] A: RETURN if((g_ftm_frame_enacap_config[phyId].bss_addr == NULL) || (g_ftm_frame_enacap_config[phyId].da_addr == NULL)) +125,,[ tcmd_tx.c : 1590 ] A: if((g_tcmd_wal_config[phyId].vdev) == NULL) +124,,[ tcmd_tx.c : 1593 ] A: if(((g_bss_peer[phyId]) == NULL) || (g_ftm_ctxt[phyId].peer == NULL)) +123,,[ tcmd_tx.c : 1598 ] A: RETURN if((g_bss_track_peer != NULL) || (g_ctxt_track_peer != NULL)) +122,,[ tcmd_tx.c : 1162 ] A: peer_use_4cal +121,iiI,[ tcmd_tx.c : 1182 ] A: g_bss_peer[%d]=%d g_ftm_bss_peer[phyId]= %08x +120,I,[ tcmd_tx.c : 1183 ] cwc wal_peer_alloc for bss_peer %08x <= +119,I,[ tcmd_tx.c : 1186 ] A: ctxt->peer=0x%x +118,iI,[ tcmd_tx.c : 1187 ] A: g_ftm_frame_enacap_config[%d].da_addr=0x%x +117,iI,[ tcmd_tx.c : 1188 ] A: g_ftm_frame_enacap_config[%d].bss_addr=0x%x +116,Ii,[ tcmd_tx.c : 1198 ] A: wal_peer_alloc ctxt->peer[%08x] %d times +115,,[ tcmd_tx.c : 1201 ] A: wal_peer_alloc peer_use_4cal ctxt->peer +114,iiI,[ tcmd_tx.c : 1165 ] A: g_bss_peer[%d]=%d g_ftm_bss_peer[phyId]= %08x +113,,[ tcmd_tx.c : 1172 ] A: peer_use_4cal wal_peer_alloc bss_peer +151,iiiiiiii,[ rxGainCal.c : 740 ] cust_rxGainCal_dbg: Saving Results for rssiDBr=%d phyId %d, chainIdx %d, PNFdBr %d PNFdBm %d, Expected Pkt Cnt %d, Actual Pkt Cnt %d minCcaThreshold=%d +150,,[ rxGainCal.c : 685 ] cust_rxGainCal_dbg: Cleared Rxgain Caldata for band + +149,i,[ rxGainCal.c : 772 ] cust_rxGainCal_dbg: Rxgain Caldata Saved with status %d + +148,iii,[ rxGainCal.c : 778 ] cust_rxGainCal_dbg: Rx Gain cal result Save Failure for phyId %d,Invalid Channel %d chainIdx %d +147,,[ rxGainCal.c : 634 ] cust_rxGainCal_dbg: GET_INIT + +146,,[ rxGainCal.c : 638 ] cust_rxGainCal_dbg: GET_CUST_RXGAINCAL_TARGET_PARAMS + +145,,[ rxGainCal.c : 642 ] cust_rxGainCal_dbg: SET_CUST_RXGAINCAL_TARGET_PARAMS + +144,,[ rxGainCal.c : 646 ] cust_rxGainCal_dbg: Invalid CUST_RXGAINCAL Argument + +143,iiiiii,[ rxGainCal.c : 134 ] rxGainCal:: Starting Rx on phyId %d, is2Ghz %d, Chain %d Chan %d, rxMode %d refISS Level %d +142,i,[ rxGainCal.c : 215 ] rxGainCal:: Error on chainIdx %d + +141,i,[ rxGainCal.c : 225 ] rxGainCal:: Error on chainIdx %d + +140,i,[ rxGainCal.c : 239 ] rxGainCal:: Error on chainIdx status %d + +139,iiii,[ rxGainCal.c : 809 ] cust_rxGainCal_dbg::: Sent to Host status=%d NFdbr=%d NFdbm=%d minccaThreshold=%d +138,I,[ rxGainCal.c : 820 ] cust_rxGainCal_dbg:: Sent to Host pCmdStream=%p +137,iiii,[ rxGainCal.c : 570 ] rxGainCal:: CMD_RXGAINCALRSP phyId=%d band=%d refISS=%d bandWidth=%d +136,iiii,[ rxGainCal.c : 575 ] rxGainCal:: CMD_RXGAINCALRSP chanIdx=%d chainIdx=%d numPackets=%d freq=%d +135,ii,[ rxGainCal.c : 283 ] rxGainCal:: Host error: phyId %d, veryFirstRxGainCal %d +134,iiiiii,[ rxGainCal.c : 297 ] rxGainCal:: Host error: phyId %d, chainIdx %d, ChanIdx %d, Expected Pkt Cnt %d, Actual Pkt Cnt %d, rxGainCalState.status %d +133,iiiiiiiii,[ rxGainCal.c : 341 ] rxGainCal:: rssiDBr=%d Saving Results for phyId %d, chainIdx %d, ChanIdx %d, PNFdBr %d, PNFdBm %d, Expected Pkt Cnt %d, Actual Pkt Cnt %d minCCAThreshold=%d +132,iiiiii,[ rxGainCal.c : 347 ] rxGainCal:: Saving Results for phyId %d, chainIdx %d, ChanIdx %d, Expected Pkt Cnt %d, Actual Pkt Cnt %d totalPkt=%d +131,,[ rxGainCal.c : 357 ] nextLoopRxCal is NULL +243,iii,[ tpcCal.c : 659 ] chk1 Max_TX_CAL_Gain_ID_5G:%d Max_TX_CAL_Gain_ID_2G %d Max_TX_CAL_Gain_ID_6G %d +242,IIII,[ tpcCal.c : 794 ] tpccal::5G opcChan[%u] %u, tpcChan[%u] %u +241,IIII,[ tpcCal.c : 815 ] tpccal::6G opcChan[%u] %u, tpcChan[%u] %u +240,Ii,[ tpcCal.c : 895 ] greenTxGainIndGrpFlag2G:%x, greenTxGainIndGrpFlag5G:%d + +239,iiii,[ tpcCal.c : 984 ] 5G IdxGainEndGrp1:%d IdxGainEndGrp2:%d IdxGainEndGrp3:%d IdxGainEndGrp4:%d + +238,i,[ tpcCal.c : 738 ] tpccal chan::6g %d +237,IIII,[ tpcCal.c : 769 ] tpccal::2G opcChan[%u] %u, tpcChan[%u] %u +236,iiiii,[ tpcCal.c : 1358 ] freq %d gIdx %d dacGain %d paCfg %d chMask %d + +235,III,[ tpcCal.c : 1396 ] tpccal::Stopping tx before starting for Chan %u, Chain %u, Gain %u +234,,[ tpcCal.c : 2699 ] tpccal::Generating Caldata +233,ii,[ tpcCal.c : 2782 ] tpcCal::Generating Caldata for Channel %d dacGainforCal %d +232,i,[ tpcCal.c : 2786 ] tpcCal::Generating Caldata for Chain %d +231,iii,[ tpcCal.c : 2793 ] tpcCal::Generating Caldata for GLUT Gain Idx %d txgainIdx %d meas_pwr %d +230,iii,[ tpcCal.c : 2804 ] tpcCal::Generating Caldata for GLUT EXT Gain Idx %d txgainIdx %d meas_pwr %d +229,iii,[ tpcCal.c : 2814 ] tpcCal::Generating Caldata for PLUT Gain Idx %d pdadc_read %d meas_pwr %d +228,iii,[ tpcCal.c : 2860 ] tpcCal::Generating Caldata for Chain %d sbsOffset %d NUM_CAL_GAINS_SELECTED_4_GLUT:%d +227,iii,[ tpcCal.c : 2868 ] tpcCal::Generating Caldata for GLUT Gain Idx %d txgainIdx %d meas_pwr %d +226,iiii,[ tpcCal.c : 2879 ] tpcCal::Generating Caldata for GLUT EXT Gain Idx %d txgainIdx %d meas_pwr %d numGlutEntries_5G:%d +225,iii,[ tpcCal.c : 2889 ] tpcCal::Generating Caldata for PLUT Gain Idx %d pdadc_read %d meas_pwr %d +224,iii,[ tpcCal.c : 2907 ] phyId:%d cmask:%d pwrAtPdadc:%d +223,III,[ tpcCal.c : 1886 ] getNextLoop fail curLoop->idxCalPt %u, Chain %u, Gain %u +222,iiiii,[ tpcCal.c : 1913 ] bef, band %d ch %d numCh %d chain %d gain %d + +221,,[ tpcCal.c : 1918 ] end loop0 + +220,iiii,[ tpcCal.c : 1931 ] inc calPt %d ch %d chn %d, numGain %d + +219,ii,[ tpcCal.c : 1939 ] inc chain AI %d %d + +218,ii,[ tpcCal.c : 1947 ] inc ch AI %d %d + +217,ii,[ tpcCal.c : 1955 ] inc band AI %d %d + +216,,[ tpcCal.c : 1959 ] end loop + +215,iiii,[ tpcCal.c : 2020 ] pwr est %d band %d numEst %d, idx %d +214,iiiii,[ tpcCal.c : 2024 ] sG %d %d %d %d %d +213,i,[ tpcCal.c : 2025 ] %d + +212,i,[ tpcCal.c : 3551 ] available_gainIdxs:%d +211,iiii,[ tpcCal.c : 3557 ] Iteration m:%d glutsfilled[%d]:%d Max_Glut_Map[band][grpId]:%d +210,i,[ tpcCal.c : 3558 ] tpcCalResult[band][chan].measPwr[chain][m]:%d +209,,[ tpcCal.c : 3561 ] ERR: BAD CAL TARGETs CONFIGURED for: +208,i,[ tpcCal.c : 3568 ] Picked limiting gainidx:%d +207,i,[ tpcCal.c : 3582 ] Picked gainidx:%d +206,,[ tpcCal.c : 3586 ] Moving up gainidxs to guarantee GLUT count! +205,ii,[ tpcCal.c : 3589 ] currIndx:%d Updated endPwrIdxGrp:%d +204,,[ tpcCal.c : 3594 ] BAD CAL TARGETs CONFIGURED for +203,ii,[ tpcCal.c : 3599 ] Picked max gainidx:%d from group :%d +202,,[ tpcCal.c : 3602 ] Invalid pick_glut_entry condition! +201,,[ tpcCal.c : 2317 ] tpccal::Post processing CLPC Caldata +200,iii,[ tpcCal.c : 2388 ] tpccal:: PowerSave:: skip gainIdx %d Previous PDADC %d meas PDADC %d +199,,[ tpcCal.c : 2461 ] tpccal::Post processing CLPC Caldata +198,,[ tpcCal.c : 2177 ] tpccal::Post processing OLPC Caldata +197,,[ tpcCal.c : 2185 ] pp OLPC + +196,iiiii,[ tpcCal.c : 2209 ] meaPwr %d tgtPwr %d, bn %d ch %d chn %d, + +195,i,[ tpcCal.c : 2210 ] numValidMeas = %d + +194,iiii,[ tpcCal.c : 2217 ] bkof %d bn %d ch %d chn %d + +193,iiii,[ tpcCal.c : 2236 ] stPwrIdx %d bn %d ch %d chn %d + +192,iiiiiiii,[ tpcCal.c : 2287 ] iMeas %d iGainIdx %d tgt %d ch %d chn %d sel pwr %d gIdx %d dac %d + +191,,[ tpcCal.c : 3621 ] postProcessingOLPCCALData_gtx +190,iiii,[ tpcCal.c : 3660 ] BegiN: Band:%d chan:%d startPwrIdxGrp:%d endPwrIdxGrp:%d +189,ii,[ tpcCal.c : 3661 ] gtx tgtpwridx:%d , GlutPwrMapGrpNum:%d +188,iii,[ tpcCal.c : 3668 ] gtx startPwrIdxGrp:%d , endPwrIdxGrp:%d modifiedTarget:%d +187,i,[ tpcCal.c : 3670 ] endPwrIdxGrp:%d +186,iii,[ tpcCal.c : 3676 ] gtx startPwrIdxGrp:%d , endPwrIdxGrp:%d modifiedTarget:%d +185,i,[ tpcCal.c : 3678 ] endPwrIdxGrp:%d +184,iiii,[ tpcCal.c : 3685 ] gtx startPwrIdxGrp:%d , endPwrIdxGrp:%d tpcCfg[band].IdxGainEndGrp3:%d modifiedTarget:%d +183,i,[ tpcCal.c : 3687 ] endPwrIdxGrp:%d +182,iiii,[ tpcCal.c : 3693 ] gtx startPwrIdxGrp:%d , endPwrIdxGrp:%d tpcCfg[band].IdxGainEndGrp4:%d modifiedTarget:%d +181,i,[ tpcCal.c : 3695 ] endPwrIdxGrp:%d +180,iii,[ tpcCal.c : 3699 ] gtx Invalid TPC_GLUT_PWR_MAP_GRP Id ! from Band:%d Chain:%d tgtpwridx:%d +179,ii,[ tpcCal.c : 2618 ] tpccal:: PowerSave:: Switch Gainindex %d switchpwrIndex %d +178,ii,[ tpcCal.c : 1180 ] Sending to host freq2G %d, freq5G %d + +177,iii,[ tpcCal.c : 1790 ] Sending to host freq2G %d, freq5G %d, chain %d +176,iiii,[ tpcCal.c : 1791 ] gain %d pwr %d numChain %d numCalpt %d + +175,IIII,[ tpcCal.c : 1795 ] tpccal::Sending to host to look for measurements inChan2G %u, Chan5G %u, ChainMask(User) %u, Gain %u +174,iii,[ tpcCal.c : 1797 ] Sending to host freq2G %d, freq5G %d, chain %d + +173,iiii,[ tpcCal.c : 1798 ] gain %d pwr %d numChain %d numCalpt %d + +172,,[ tpcCal.c : 2652 ] tpccal::Sending Caldata to host +171,,[ tpcCal.c : 1469 ] tpccal::Starting ... +170,,[ tpcCal.c : 1606 ] TPC Cal message check + +169,ii,[ tpcCal.c : 1660 ] tpcCALScheme: %d, phyID %d + +168,,[ tpcCal.c : 2074 ] tpccal::Completed +167,,[ tpcCal.c : 2099 ] FTM_REGEN_CALDB: Initiating cold boot calibration in FTM... + +166,,[ tpcCal.c : 3166 ] tpccal::Out of sync power measurement report! + +165,i,[ tpcCal.c : 3335 ] skipping slope for gainIdx = %d +164,iIIII,[ tpcCal.c : 3199 ] tpccal::Got measurement %d from host for Chan %u Chain %u Chain(user) %u Gain %u +163,iIIIII,[ tpcCal.c : 3219 ] tpccal::Thermoffset %d for Band %u tpcChan %u opcChan[%u] %u Chain %u +162,iiii,[ tpcCal.c : 3235 ] Got Power from host Chan %d , GainIdx %d , MeasPwr %d , Read pdadc %d +161,ii,[ tpcCal.c : 3271 ] tpccal:: PowerSave:: enabled %d ignore non-linerarity at Gainidx switch %d +160,ii,[ tpcCal.c : 3298 ] Received identical power meas:%d prevMeas:%d .Failing calloop +159,iii,[ tpcCal.c : 3327 ] Get 10Log(pdadc) prev:%d curr:%d slope:%d +158,ii,[ tpcCal.c : 3330 ] Get Power meas:%d prevMeas:%d +157,iiii,[ tpcCal.c : 3331 ] calFail:%d, gainIdx:%d, idxCalPt:%d skipSlope_gtx_bndry:%d +156,III,[ tpcCal.c : 2051 ] tpccal::Starting tx for Chan %u, Chain %u, Gain %u +155,i,[ tpcCal.c : 2058 ] tpccal:: PowerSave:: Gainindex Switch %d +154,iiiii,[ tpcCal.c : 3518 ] Write to tpcCalPostProcResult[%d][%d].olpc.measPwrExt[%d][%d]:%d +153,iiiii,[ tpcCal.c : 3525 ] Write to tpcCalPostProcResult[%d][%d].olpc.measPwr[%d][%d]:%d +152,ii,[ tpcCal.c : 3535 ] glutsfilled[%d]:%d +272,,[ tpcOnepointCal.c : 897 ] cust_OPC_dbg: GET_INIT + +271,,[ tpcOnepointCal.c : 901 ] cust_OPC_dbg: GET_OPC_TARGET_PARAMS + +270,,[ tpcOnepointCal.c : 905 ] cust_OPC_dbg: SET_OPC_TARGET_PARAMS + +269,,[ tpcOnepointCal.c : 909 ] cust_OPC_dbg: Invalid OPC Argument + +268,Iiii,[ tpcOnepointCal.c : 298 ] tpcOnepointCal::Starting Tx for phy %u, freq %d, chainMask %d, txPwr_db2 %d +267,Iiii,[ tpcOnepointCal.c : 301 ] tpcOnepointCal::Stopping Tx for phy %u, freq %d, chainMask %d, txPwr_db2 %d +266,iii,[ tpcOnepointCal.c : 618 ] tpcOnepointCal::Failure at BandIdx:%d chanIdx:%d chainIdx:%d +265,,[ tpcOnepointCal.c : 628 ] tpcOnepointCal:: end loop 1 +264,,[ tpcOnepointCal.c : 638 ] tpcOnepointCal:: break +263,,[ tpcOnepointCal.c : 684 ] tpcOnepointCal:: end loop +262,i,[ tpcOnepointCal.c : 145 ] tpcOnepointCal::chan::2g %d +261,ii,[ tpcOnepointCal.c : 190 ] tpcOnepointCal::TPC_DBG 5G numChain %d 2G numChain %d +260,i,[ tpcOnepointCal.c : 155 ] tpcOnepointCal::chan::5g %d +259,i,[ tpcOnepointCal.c : 162 ] tpcOnepointCal::chan::6g %d +258,ii,[ tpcOnepointCal.c : 702 ] tpcOnepointCal::TPC_DBG band %d idxChan %d +257,iii,[ tpcOnepointCal.c : 1019 ] cust_OPC_dbg: Sent to Host status=%d glutoffset=%d thermaloffset=%d +256,I,[ tpcOnepointCal.c : 1030 ] cust_OPC_dbg: Sent to Host pCmdStream=%p +255,IIII,[ tpcOnepointCal.c : 520 ] tpcOnepointCal::Requesting pwr measurement for phy %u, freq %u, chainMask %u,tgtPwr_db8 %u +254,IIII,[ tpcOnepointCal.c : 534 ] tpcOnepointCal::Requesting pwr measurement for phy %u, freq %u, chainMask %u,tgtPwr_db8 %u +253,IIII,[ tpcOnepointCal.c : 550 ] tpcOnepointCal::Requesting pwr measurement for phy %u, freq %u, chainMask %u,tgtPwr_db8 %u +252,,[ tpcOnepointCal.c : 761 ] tpcOnepointcal::Completed +251,Iii,[ tpcOnepointCal.c : 948 ] cust_OPC_dbg: Pwr measurement for phy %u, glutoffset %d, thermOffset %d +250,ii,[ tpcOnepointCal.c : 432 ] tpcOnepointCal::TPC_DBG 5G numChain %d 2G numChain %d +249,i,[ tpcOnepointCal.c : 983 ] cust_OPC_dbg: OPC Caldata Saved with status %d + +248,i,[ tpcOnepointCal.c : 986 ] cust_OPC_dbg: Invalid Frequency:%d + +247,,[ tpcOnepointCal.c : 324 ] tpcOnepointCAL::Starting... +246,,[ tpcOnepointCal.c : 803 ] tpcOnepointcal::Failure, -999 power detected +245,IIIiiI,[ tpcOnepointCal.c : 819 ] tpcOnepointCal::Pwr measurement for phy %u, freq %u, chainMask %u, glutOffset %d, thermOffset %d, measPwr_db8 is %u +244,,[ tpcOnepointCal.c : 109 ] tpcOnepointCal::tpcPowerMeasurementDelayTimeout +274,ii,[ xtalCal.c : 277 ] [TLV2_CTRL_W_OTP]capIn=%d, capOut=%d +273,ii,[ xtalCal.c : 281 ] [ERROR][TLV2_CTRL_W_OTP]OTP has data %d, %d +275,ii,[ wmi_ftm_attach.c : 226 ] ERROR: ftm_parse_unifiedcmd: dataLen %d is LESS than sizeof(segHdrInfo) %d +277,II,[ whal_coex.c : 876 ] WHAL_COEX_BT_CHAIN: whal_set_bt_chain WLAN_id(%u) chain(%u) +276,II,[ whal_coex.c : 852 ] WHAL_COEX_GAIN: set_agc_gain WLAN_id(%u) level(%u) +280,IIIIiIIII,[ whal_mci.c : 1014 ] WAL_COEX_CONT_INFO: INFO|NACK|RST|TX[0x%x]: Prio(%u), LinkId(%u) Ch(%u) Rssi_pwr(%d) btClock|priIdx[0x%x] nack_wght(%u) PT|JO|FRAB|POT[0x%x] po_bm(0x%x) +279,i,[ whal_mci.c : 211 ] BTCOEX_DBG_MCI_2: Coex Band setting. WLAN1(%d) + +278,I,[ whal_mci.c : 489 ] COEX_GENERIC_ERROR: MCIIntfTimeout(%u) +284,iiii,[ whal_pta.c : 46 ] COEX_PTA_INT_STATS: Pta1BtStomped(%d) Pta1WlanStomped(%d) Pta1BtHighPriFaling(%d) Pta1BtHighPriRising(%d) +283,iiii,[ whal_pta.c : 68 ] COEX_PTA_INT_STATS: Pta2BtLowPriFalling(%d) Pta2BtLowPriRising(%d) Pta2BtActiveFalling(%d) Pta2BtActiveRising(%d) +282,iiii,[ whal_pta.c : 53 ] COEX_PTA_INT_STATS: Pta1BtLowPriFalling(%d) Pta1BtLowPriRising(%d) Pta1BtActiveFalling(%d) Pta1BtActiveRising(%d) +281,iiii,[ whal_pta.c : 61 ] COEX_PTA_INT_STATS: Pta2BtStomped(%d) Pta2WlanStomped(%d) Pta2BtHighPriFaling(%d) Pta2BtHighPriRising(%d) +286,i,[ whal_coex_init_ext.c : 257 ] En Soft Abort %d +285,IIii,[ whal_coex_init_ext.c : 274 ] Flex Req Param FlushBmap 0x%x TidBmap 0x%x CCATimeout%d MaxReqLim %d +291,,[ whal_coex_gpm.c : 186 ] ERROR_COEX_MCI_GPM: invalid GPM +290,II,[ whal_coex_gpm.c : 194 ] ERROR_COEX_MCI_GPM: Drop GPM, Recovery in progress: SWGpmIndex(%u) NumGPM(%u) +289,II,[ whal_coex_gpm.c : 147 ] ERROR_COEX_MCI_GPM: Drop GPM, Recovery in progress: SWGpmIndex(%u) NumGPM(%u) +288,I,[ whal_coex_gpm.c : 76 ] ERROR_COEX_MCI_GPM: ERROR - MCI Init is NOT complete ! Dropping GPM - 0x%x +287,IIIIIIII,[ whal_coex_gpm.c : 79 ] ERROR_COEX_MCI_GPM: AnyMacPowerUp (%u) IsMCIBusPaused (%u), whal_mci_get_sleep_state(%u), SleepOverride(%u), IsMciHWBusy(%u) IsMciInitComplete(%u) MCIBasicSyncError(%u) whal_mci_get_wsi_state(%u) + +294,I,[ whal_coex_smh.c : 69 ] WHAL_COEX_SMH_ISR: Error(0x%x) +293,I,[ whal_coex_smh.c : 158 ] WHAL_COEX_SMH_HNDLR: Error(0x%x) +292,,[ whal_coex_smh.c : 83 ] NULL: Buffers not allocated +299,,[ whal_coex_bmh.c : 108 ] COEX_MCI_ISR_IntRaw: BMH ISR overflow +298,IIIIIII,[ whal_coex_bmh.c : 125 ] WHAL_COEX_BMH_ISR: Tx(%u) Rx(%u) BmhIntRaw(0x%x) BmhRxMsgRaw(0x%x) BmhInt1Raw(0x%x) invalid_hdr(%u) cont_info_to(%u) +297,I,[ whal_coex_bmh.c : 408 ] WHAL_COEX_BMH_HNDLR: Error(0x%x) +296,III,[ whal_coex_bmh.c : 494 ] WAL_COEX_SCHED_INFO: sched_info start 0x%x, stop 0x%x wbts 0x%x +295,IIIIiII,[ whal_coex_bmh.c : 504 ] WAL_COEX_SCHED_INFO: i=%u Prio(%u) Tag(%u) tx(%u) Txp(%d) Link(%u) Dur(%u) +302,iii,[ whal_coex_lmh.c : 49 ] COEX_LNA_LOCK_INFO: gain_idx = %d, lna_in_use= %d, lna_bt_lock= %d +301,,[ whal_coex_lmh.c : 53 ] COEX_MCI_ISR_IntRaw: LMH ISR overflow +300,I,[ whal_coex_lmh.c : 93 ] WHAL_COEX_LMH_HNDLR: Error(0x%x) +304,I,[ whal_coex_mcim.c : 68 ] COEX_MCIM_ISR: Error(0x%x) +303,I,[ whal_coex_mcim.c : 204 ] WHAL_COEX_MCIM_HNDLR: Error(0x%x) +310,,[ whal_coex_pmh.c : 84 ] BTCOEX_DBG_MCI_1: No CONT_INFO/RST msg received after sys waking message +309,,[ whal_coex_pmh.c : 88 ] COEX_MCI_ISR_IntRaw: PMH ISR overflow +308,I,[ whal_coex_pmh.c : 128 ] WHAL_COEX_PMH_ERR: err(0x%x) +307,i,[ whal_coex_pmh.c : 321 ] COEX_POWER_CHANGE: WMAC is not right! wmac(%d) +306,iii,[ whal_coex_pmh.c : 325 ] COEX_POWER_CHANGE: INIT_STATUS(%d) INIT_RESULT(%d) wmac(%d) +305,,[ whal_coex_pmh.c : 391 ] BTCOEX_DBG_MCI_2: Trying to power up. due to POWERUP_FAILURE, return + +312,,[ whal_coex_recipes.c : 46 ] BTCOEX_DBG_MCI_2: Calling cxc power down + +311,ii,[ whal_coex_recipes.c : 151 ] BTCOEX_DBG_MCI_2: _whal_mci_powerup Power up wmac%d, and band is %dG + +326,ii,[ whal_debug.c : 5870 ] config_reg_dump: Entries exceeded MAX REG DUMP ENTRY :%d! :%d + +325,I,[ whal_debug.c : 5875 ] config_reg_dump: Invalid register physical address! :0x%x + +324,iIIII,[ whal_debug.c : 3627 ] CRYPTO_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +323,iII,[ whal_debug.c : 3497 ] HWSCH_TRACER_LOG: mac(%d), tbus_index(0x%x), debug_trace(0x%x) +322,iIIII,[ whal_debug.c : 3595 ] PDG_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +321,iIIII,[ whal_debug.c : 4447 ] RXDMA1_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +320,iIIII,[ whal_debug.c : 4393 ] RXDMA_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +319,iIIII,[ whal_debug.c : 3691 ] RXOLE_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +318,iIIII,[ whal_debug.c : 3562 ] RXPCU_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +317,iIIII,[ whal_debug.c : 4503 ] TXDMA_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +316,iIIII,[ whal_debug.c : 3659 ] TXOLE_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +315,iIIII,[ whal_debug.c : 3530 ] TXPCU_TRACER_LOG: mac(%d), tbus_index(0x%x), dbg_select(0x%x), debug_trace(0x%x,0x%x) +314,IIIIII,[ whal_debug.c : 5895 ] TBUS_0x34 0x%x, MAC_IDLE 0x%x, TLV_READY 0x%x, ISR_S0 0x%x, ISR_S16 0x%x, SM_STATES 0x%x + +313,IIIIIIII,[ whal_debug.c : 5939 ] TXPCU_R1_DEBUG registers : DEBUG_STATE 0x%x TX_FES_0 0x%x TX_FES_1 0x%x TX_FES_2 0x%x INT_OR_ERR_STATUS 0x%x LAST_INT_OR_ERR_STATUS_MASK 0x%x LAST_INT_OR_ERR_STATUS 0x%x TRACE_BUS_UPPER 0x%x + +334,II,[ whal_hwsch.c : 3958 ] hwsch2_wdog_timeout: reg_wdog=%x, reg_cmd_ring_wdog=%x +333,II,[ whal_hwsch.c : 4157 ] cca_watchdog=%x, reg_axi_err=%x +332,II,[ whal_hwsch.c : 4202 ] ul-q(%i), reg:%x +331,III,[ whal_hwsch.c : 4208 ] val_0=%x, val_1=%x, val_2=%x +330,I,[ whal_hwsch.c : 4449 ] WHAL_FATAL_ERR_UNKNOWN:%x +329,i,[ whal_hwsch.c : 4463 ] WHAL_FATAL_ERR_UNKNOWN: pdev_id:%d - Ignore, since wdog statuses got cleared +328,iiIii,[ whal_hwsch.c : 5069 ] config_txop_sel (pdev=%d,q=%d): reg=0x%x, lifetime_exp=%d, txop_sel=%d +327,iii,[ whal_hwsch.c : 2246 ] PM_STATE_DBG: sw_peer_id=%d, pmfilter=%d, twtfilter=%d +368,I,[ whal_interrupt.c : 3448 ] SM_IX_2 value:%x +367,II,[ whal_interrupt.c : 1011 ] Clear false RXPCU WDOG, status %x, limit %x +366,I,[ whal_interrupt.c : 1728 ] GetPendingInterrupts-whalPending:0x%x +365,iII,[ whal_interrupt.c : 3823 ] AMPI WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +364,iII,[ whal_interrupt.c : 4450 ] AMPI panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +363,iII,[ whal_interrupt.c : 3693 ] CRYPTO WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +362,iII,[ whal_interrupt.c : 3838 ] CRYPTO panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +361,iII,[ whal_interrupt.c : 3781 ] HWSCH WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +360,iII,[ whal_interrupt.c : 4331 ] HWSCH panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +359,iII,[ whal_interrupt.c : 4681 ] MCMN panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +358,iIII,[ whal_interrupt.c : 3805 ] MXI WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x GXI-err-stats-reg 0x%x + +357,iIII,[ whal_interrupt.c : 4363 ] MXI panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x GXI-err-stats-reg 0x%x + +356,iII,[ whal_interrupt.c : 3731 ] PDG WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +355,iII,[ whal_interrupt.c : 4219 ] PDG panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +354,iII,[ whal_interrupt.c : 4664 ] RXDMA1_DST_RNG panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +353,iII,[ whal_interrupt.c : 4595 ] RXDMA1 panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +352,iII,[ whal_interrupt.c : 4611 ] RXDMA1_SRC_RNG panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +351,iII,[ whal_interrupt.c : 4647 ] RXDMA_DST_RNG panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +350,iII,[ whal_interrupt.c : 3714 ] RXDMA WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +349,iII,[ whal_interrupt.c : 4168 ] RXDMA panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +348,iII,[ whal_interrupt.c : 4630 ] RXDMA_SRC_RNG panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +347,iII,[ whal_interrupt.c : 3663 ] RXOLE WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +346,iII,[ whal_interrupt.c : 4541 ] RXOLE panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +345,iII,[ whal_interrupt.c : 3517 ] RXPCU WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +344,iII,[ whal_interrupt.c : 4185 ] RXPCU0 panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +343,iII,[ whal_interrupt.c : 3538 ] RXPCU1 WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +342,iII,[ whal_interrupt.c : 4203 ] RXPCU1 panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +341,iII,[ whal_interrupt.c : 4557 ] SFM panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +340,iII,[ whal_interrupt.c : 3600 ] TXDMA WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +339,iII,[ whal_interrupt.c : 4065 ] TXDMA panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +338,iII,[ whal_interrupt.c : 3680 ] TXOLE WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +337,iII,[ whal_interrupt.c : 4466 ] TXOLE panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +336,iIII,[ whal_interrupt.c : 3573 ] TXPCU WDOG error interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x, PhyErr 0x%x +335,iII,[ whal_interrupt.c : 3911 ] TXPCU0 panic interrupt on PDEV ID-%d, mask 0x%x, total count 0x%x + +371,iiii,[ whal_cce.c : 956 ] whal_debug_reg_dump: cce_drop_1=%d, cce_drop_2=%d, cce_drop_3=%d, cce_drop_4=%d +370,IIII,[ whal_cce.c : 965 ] whal_debug_reg_dump: cce_rule_drop_1=0x%0x, cce_rule_drop_2=0x%0x, cce_rule_drop_3=0x%0x, cce_rule_drop_4=0x%0x +369,,[ whal_cce.c : 578 ] poll MCMN_R0_MCMN_MAC_IDLE/HWIO_MCMN_R0_MCMN_MAC_IDLE_RXOLE_BMSK timeout + +382,III,[ whal_recv.c : 6846 ] fse_watchdog %x, sm_state_reg %x, cache_response %x +381,II,[ whal_recv.c : 5670 ] rssi_legacy rssi_comb,rssi_comb_ppdu :0x%x chain0, 1:0x%x +380,III,[ whal_recv.c : 7897 ] whalSetBssColor: parameters bsscolor|en|bss_id = %08x, caller = 0x%x:0x%x +379,iii,[ whal_recv.c : 1407 ] startPcuReceive on mac:%d, phy_is_off:%d leave_phy_off:%d +378,iII,[ whal_recv.c : 1597 ] StopPcuReceive on mac:%d, phy on-%x, force_rx_abort-%x +377,IIII,[ whal_recv.c : 1605 ] Before TXPCU_R1_DEBUG_RX_MESSAGE: COUNT0 0x%x, COUNT1 0x%x, COUNT2 0x%x RXPCU_R1_DEBUG_RX_MESSAGE_COUNT0: 0x%x +376,IIII,[ whal_recv.c : 1695 ] After TXPCU_R1_DEBUG_RX_MESSAGE: COUNT0 0x%x, COUNT1 0x%x, COUNT2 0x%x RXPCU_R1_DEBUG_RX_MESSAGE_COUNT0: 0x%x +375,I,[ whal_recv.c : 9442 ] TxRx overlap TLV_READY reg_val: 0x%x + +374,IIII,[ whal_recv.c : 600 ] RXPCU_FSM_STATUS 0/1/2: 0x%x, 0x%x, 0x%x, SFM_R0_AVAILABLE_BUFFERS : 0x%x +373,Ii,[ whal_recv.c : 9272 ] %s: invalid lmac id %d + +372,,[ whal_recv.c : 9303 ] Link desc leakage due to SFM issue Jira 1206 + +408,,[ whal_recv_recovery.c : 81 ] SW2RXDMA_BUF ring empty +407,,[ whal_recv_recovery.c : 124 ] FW2RXDMA_BUF ring empty +406,,[ whal_recv_recovery.c : 145 ] RX_RING_FW_BUF ring empty caused by RX_RING_WMI_EVT +405,,[ whal_recv_recovery.c : 169 ] FW2RXDMA_STATBUF ring empty +404,,[ whal_recv_recovery.c : 176 ] FW2RXDMA_STATBUF ring empty +403,I,[ whal_recv_recovery.c : 220 ] whalBufRingEmptyCheck invalid dev_id:%x +402,,[ whal_recv_recovery.c : 260 ] WBM2RXDMA_LINK ring empty +401,,[ whal_recv_recovery.c : 267 ] WBM2RXDMA_LINK ring empty +400,,[ whal_recv_recovery.c : 88 ] SW2RXDMA_BUF ring empty +399,,[ whal_recv_recovery.c : 292 ] FW2RXDMA_LINK ring empty +398,,[ whal_recv_recovery.c : 299 ] FW2RXDMA_LINK ring empty +397,,[ whal_recv_recovery.c : 326 ] MO SW2RXDMA_BUF ring empty +396,,[ whal_recv_recovery.c : 333 ] MO SW2RXDMA_BUF ring empty +395,,[ whal_recv_recovery.c : 358 ] MO FW2RXDMA_STATBUF ring empty +394,,[ whal_recv_recovery.c : 365 ] MO FW2RXDMA_STATBUF ring empty +393,,[ whal_recv_recovery.c : 390 ] MO FW2RXDMA_LINK ring empty +392,,[ whal_recv_recovery.c : 397 ] MO FW2RXDMA_LINK ring empty +391,IIIIII,[ whal_recv_recovery.c : 443 ] ring type [0x%x] empty error ts-0x%x, pre hp:0x%x, ts 0x%x, hp 0x%x, tp 0x%x +390,IiI,[ whal_recv_recovery.c : 454 ] ring type [0x%x] wmi pending:%d, empty %x +389,,[ whal_recv_recovery.c : 117 ] FW2RXDMA_BUF ring empty +388,IIIIIIII,[ whal_recv_recovery.c : 577 ] ring [0x%x] full ts-0x%x, hp 0x%x, tp 0x%x, reo2sw1: 0x%x, reo2sw4:0x%x, reo2tcl:0x%x, rxdma2sw:0x%x +387,IiIIII,[ whal_recv_recovery.c : 1894 ] RXDMA hang type [0x%x], cnt %d, error ts-0x%x, rin type: %x, mask 0x%x:0x%x +386,IiIII,[ whal_recv_recovery.c : 1106 ] RXOLE hang type [0x%x], cnt %d, error ts-0x%x, rin type: %x, mask 0x%x +385,IIII,[ whal_recv_recovery.c : 1282 ] RXPCU hang type [0x%x] empty error ts-0x%x, mask 0x%x, 0x%x +384,IIII,[ whal_recv_recovery.c : 2042 ] RXCRYPTO hang type [0x%x] empty error ts-0x%x, mask 0x%x, 0x%x +383,i,[ whal_recv_recovery.c : 841 ] TXRX OVLAP hit on MAC-%d +409,II,[ whal_reo.c : 323 ] whal_reo_remote_data_ind addr:0x%x:0x%x +426,iiiii,[ whal_reset.c : 3690 ] channelSwitch: INI = %d TPC = %d Cal = %d Tot = %d PF = %d +425,iiiiiiii,[ whal_reset.c : 3718 ] channelSwitch: Homechan = %d Mac = %d HALPHY_CLK_RESET= %d INI = %d MAC_MTU = %d TPC = %d HALPHY_SetChan = %d WHAL_XMIT = %d +424,iiiiiii,[ whal_reset.c : 3729 ] channelSwitch: Homechan = %d ANI = %d Reset_Synth_Spur = %d Cal = %d Mutex_Unlock = %d Tot = %d PF = %d +423,i,[ whal_reset.c : 2840 ] whalConfigProxyStaParams Unhandled BSS_ID :%d +422,,[ whal_reset.c : 1206 ] DEBUG_RESTORE::Invalid access type + +421,II,[ whal_reset.c : 1223 ] DEBUG_RESTORE::Read::addr=0x%x, value=0x%x + +420,IiiI,[ whal_reset.c : 1240 ] DEBUG_RESTORE::Bitmask Read::addr=0x%x, bitmask=%d, bitshift=%d, value=0x%x + +419,II,[ whal_reset.c : 1253 ] DEBUG_RESTORE::Write::addr=0x%x, value=0x%x + +418,IiiI,[ whal_reset.c : 1271 ] DEBUG_RESTORE::Bitmask Write::addr=0x%x, bitmask=%d, bitshift=%d, value=0x%x + +417,i,[ whal_reset.c : 1276 ] DEBUG_RESTORE::Invalid num_args_type at idx = %d + +416,,[ whal_reset.c : 1168 ] DEBUG_CACHE::Invalid Access type + +415,I,[ whal_reset.c : 1652 ] whalSetMACNAVOverrideCfg: value = 0x%x +414,,[ whal_reset.c : 1100 ] DEBUG_CACHE::Clearing the cache + +413,,[ whal_reset.c : 1145 ] DEBUG_CACHE::Invalid num args type + +412,,[ whal_reset.c : 1106 ] DEBUG_CACHE::Invalid address + +411,,[ whal_reset.c : 1112 ] DEBUG_CACHE::Reseting the cache idx + +410,iIiiI,[ whal_reset.c : 1078 ] DEBUG_CACHE::args_type=%d, addr=0x%x, bitmask=%d, bitshift=%d, value=0x%x + +448,iiIiiiiii,[ whal_rtt.c : 511 ] RTT-rtt_get_delay_ps: delay_tbl_idx=%d toda_type=%d preamble=%u whalRate%d chainNum=%d preamble=%d, pkBW=%d, HELTF=%d, rt_mode=%d +447,ii,[ whal_rtt.c : 1647 ] whal_cfir_setup_fixed_rx_rtt_chain: mode %d rtt_rx_chain_idx%d +446,iiIIII,[ whal_rtt.c : 1150 ] DEBUG-TKNS: %d,%d,%lu,%lu,%lu,%lu +445,IIIIIIIIi,[ whal_rtt.c : 1162 ] DEBUG-PERF: %lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%d +444,II,[ whal_rtt.c : 1168 ] DEBUG-PERF: %lu,%lu +443,iiIIIIII,[ whal_rtt.c : 1119 ] DEBUG-PERF: %d,%d,%lu,%lu,%lu,%lu,%lu,%lu +442,II,[ whal_rtt.c : 1125 ] DEBUG-PERF: %lu,%lu +441,IIIIIIIII,[ whal_rtt.c : 593 ] RXLocInf1 0x%08x,0x%08x,0x%08x,0x%08x,0x%08x,0x%08x,0x%08x,0x%08x,0x%08x +440,I,[ whal_rtt.c : 594 ] RXLocInf2 %u +439,,[ whal_rtt.c : 229 ] whal_rtt_frame_prepare() HW is already prepared for RTT return !!! +438,,[ whal_rtt.c : 351 ] whal_rtt_frame_recover() HW was not configured for RTT!!! return +437,I,[ whal_rtt.c : 718 ] ar_wal_get_rssi_chain: invalid rssi_info for %p +436,II,[ whal_rtt.c : 726 ] ar_wal_rtt_get_rssi_chain: rssi_info 0x%08x%08x +435,IiIiii,[ whal_rtt.c : 1098 ] rtt_get_toda: txrx_msg_buf=%p toda_type=%d toda_phy_clk=%u ppdu_id=%d txrx_delay=%d status=%d +434,ii,[ whal_rtt.c : 574 ] rtt_get_tx_rate: rate: %d bit_rate_kbps: %d +433,Ii,[ whal_rtt.c : 957 ] recv sta rssi 0x%08x chain:%d +432,ii,[ whal_rtt.c : 1201 ] rtt_recv_sta_get_rxbw: rx_bw=%d rx_preamble=%d +431,iiIIiIi,[ whal_rtt.c : 181 ] whal_rtt_recv_sta_txrx_chain_handle_event: mode %d event %d tx_mask 0x%02x rx_mask 0x%02x tx_dirty %d rtt_selfgen_tx_chain_idx %u rtt_rx_chain_idx %d +430,Ii,[ whal_rtt.c : 984 ] send sta rssi 0x%08x chain:%d +429,I,[ whal_rtt.c : 1243 ] rtt_send_sta_get_rxbw: rtt_pkt_bw=0x%x +428,I,[ whal_rtt.c : 1223 ] rtt_send_sta_get_txbw: packet_bw=0x%x +427,,[ whal_rtt.c : 1362 ] ar_wal_rtt_tx_ppdu_completion_handler: excess zero values in receive_rssi_info +450,iii,[ whal_cfir.c : 276 ] whal_cfir_configure: rtt %d capture_cfr %d capture_cir %d +449,iiI,[ whal_cfir.c : 199 ] whal_cfir_enable: enaRttPerBurst %d enaFixedStrChain %d fixedStrChainIdx 0x%02x +452,I,[ whal_tqm.c : 413 ] link_Desc_tshd register value:%02x +451,I,[ whal_tqm.c : 423 ] link_Desc_tshd register value:%02x +477,IIIIII,[ whal_xmit.c : 22724 ] fsm_client0 = %lu, fsm_client1 = %lu, fsm_client2 = %lu, fsm_client3 = %lu, fsm_client4 = %lu, fsm_client5 = %lu +476,IIIIiII,[ whal_xmit.c : 22726 ] fsm_client6 = %lu, fsm_client7 = %lu, fsm_client8 = %lu, fsm_client9 = %lu, num of times sfm issue got hit = %d, sfm_status = %u, sfm_limit = %u +475,i,[ whal_xmit.c : 22603 ] NAN virtual CCA: war_enable=%d +474,I,[ whal_xmit.c : 23257 ] LMAC Reg value mac_idle_chk_reg 0x%x +473,iiIII,[ whal_xmit.c : 17002 ] TPCDBG: HWAdjust: tpc=%d,%d cm=%x c=%08x:%08x +472,ii,[ whal_xmit.c : 12612 ] InfoTPC: Max TPC = %d Min TPC = %d + +471,II,[ whal_xmit.c : 22355 ] FIPS hp %x tp %x +470,I,[ whal_xmit.c : 22373 ] FIPS nxt_p %x +469,,[ whal_xmit.c : 22397 ] FIPS hp null +468,I,[ whal_xmit.c : 22426 ] FIPS %x +467,,[ whal_xmit.c : 22437 ] FIPS nxt_p null +466,I,[ whal_xmit.c : 22465 ] FIPS %x +465,I,[ whal_xmit.c : 22514 ] FIPS %x +464,,[ whal_xmit.c : 22624 ] NAN disable CCA profiling +463,iiIII,[ whal_xmit.c : 5675 ] TPCDBG: selfGen: tpc=%d,%d cm=%x c=%08x:%08x +462,II,[ whal_xmit.c : 11593 ] whalSetupCbfRateParams: rate code %x, flags %x +461,iii,[ whal_xmit.c : 15715 ] LDC: sch_wait_instr_txpath tlv_tag = %d, tlv_len = %d, send_tqm_tlvs_during_wait = %d +460,I,[ whal_xmit.c : 22115 ] TXDMA WDG TXDMA_R1_DEBUG_STATES_0 reg_val: 0x%x + +459,III,[ whal_xmit.c : 6109 ] Old mcs %x New mcs %x New rate_mask %x +458,iiiiiii,[ whal_xmit.c : 10161 ] whalXmitReset: HomeChan = %d Init_ResetTxQueue = %d InitPowerCtlTbl = %d HEMisConfig_Inits = %d GenRespChainMask_CCK_OFDM = %d Rtt = %d GenRespChainMask_11ax = %d +457,iii,[ whal_xmit.c : 10168 ] whalXmitReset: RegisterWrites = %d bkoff_cca_mask = %d Total = %d +456,iIII,[ whal_xmit.c : 17556 ] TPCDBG: override: tpc=%d reason=%x c=%08x:%08x +455,II,[ whal_xmit.c : 18224 ] Info: TPC = %u, %u + +454,,[ whal_xmit.c : 23082 ] wal_sw_peer_key allocation failed...!!! +453,,[ whal_xmit.c : 23085 ] wal_sw_peer_key allocation SUCCESS +479,iIIII,[ data_rx.c : 663 ] DATA_TXRX_DBGID_DUP_CHECK vdev_id = %d tcp_info=0x%x SN=0x%x last_pn_valid=0x%x offset_winsize=0x%x +478,iIIII,[ data_rx.c : 768 ] DATA_TXRX_DBGID_DUP_CHECK vdev_id = %d SN=0x%x Len=0x%x WalRxCnt=0x%x DataRxCnt=0x%x +481,III,[ data_rx_pn.c : 157 ] DATA_TXRX_DBGID_REPLAY_CHECK_WAR KeyId=0x%x oldPN=0x%llx newPN=0x%llx +480,IIII,[ data_rx_pn.c : 200 ] DATA_TXRX_DBGID_REPLAY_CHECK 0x%x KeyId=0x%x oldPN=0x%x newPN=0x%x +491,ii,[ blockack.c : 2595 ] wal_ba_check_pending_teardown reserve delba: peer %d tid %d +490,i,[ blockack.c : 761 ] BA tear down on mismatch ack type for tid:%d +489,ii,[ blockack.c : 608 ] ADDBA Req dropped WEP:%d MFP_SUPPORT:%d +488,ii,[ blockack.c : 326 ] wal_ba_event_peer_rx: amsdusupported=%d, buffersize=%d +487,I,[ blockack.c : 790 ] wal_ba_event_retry_timeout peer:%x +486,ii,[ blockack.c : 2299 ] wal_ba_rx_sm: their_buf_size:%d, our_buf_size:%d +485,ii,[ blockack.c : 1530 ] wal_ba_send_addba_rsp: amsdusupported=%d, buffersize=%d +484,,[ blockack.c : 2918 ] BA-Link-Monitor implementation Start +483,i,[ blockack.c : 1613 ] Error: ba_handle is NULL for wal_peer_id = %d +482,iI,[ blockack.c : 1700 ] TX_BA_LOG: ADDBA request pending in frameQ: tid=%d bmap=0x%x +496,iii,[ wal_lp_bar.c : 191 ] LP_BAR_DBG: lp_complete_cnt=%d,tid_num = %d, session_id = %d +495,,[ wal_lp_bar.c : 46 ] LP_BAR_DBG: Local frame completion +494,,[ wal_lp_bar.c : 79 ] LP_BAR_DBG: Alloc failed +493,,[ wal_lp_bar.c : 91 ] LP_BAR_DBG: BA session not established +492,Iiiii,[ wal_lp_bar.c : 113 ] LP_BAR_DBG: Resp_ctxt info = %x, peer_id = %d,tid_num = %d, session_id = %d, repeat_cnt = %d +499,iiiii,[ wal_hif_prio_mgr.c : 308 ] htt_in %d, wmi_drop %d, htt_drop %d, max_hif_ele %d, max_full_per %d +498,Ii,[ wal_hif_prio_mgr.c : 313 ] WMI_Event 0x%x Drop_cnt %d +497,Iiiiiiiii,[ wal_hif_prio_mgr.c : 329 ] bp_dur %u, drop_cnt %d, hp_ingress %d, lp_ingress %d, ce1 %d, ce2 %d, fifo_ele_max %d, fifo_max %d, evt_enqd_cnt %d +506,iiiIIi,[ htt_tgt_rx.c : 336 ] htt_tgt_fse_setup:[%d] [%d] [%d] [0x%lx] [0x%lx] RT: [%d] + +505,iiiii,[ htt_tgt_rx.c : 399 ] htt_tgt_fse_operation pdev,ipsec,src/dest ports,proto:[%d][%d] [%d][%d] [%d] + +504,IIIIIIII,[ htt_tgt_rx.c : 409 ] IP src [%x][%x][%x][%x] dest [%x][%x][%x][%x] + +503,II,[ htt_tgt_rx.c : 486 ] 3-tuple Configuration value rcvd : + flow_id_toeplitz_enable : [%x] + toeplitz_2_or_4_field_enable : [%x] + +502,IIIIIII,[ htt_tgt_rx.c : 857 ] ring_selection_cfg [%x] [%x] [%x] [%x] [%x] [%x] [%x] + +501,iiiiii,[ htt_tgt_rx.c : 63 ] htt_tgt_sring_setup [%d] [%d] [%d] [%d] [%d] [%d] + +500,i,[ htt_tgt_rx.c : 701 ] htt_tgt_sring_setup_done -[%d] + +508,III,[ htt_tgt_rx_event.c : 564 ] RX event msg buf_len type[%x] peer_id [%x] vdev_id [%x] + +507,IIIIII,[ htt_tgt_rx_event.c : 978 ] htt_tgt_rx_event_backpressure -[%x], [%x], [%x], [%x], [%x], [%x] + +510,III,[ mac_core_main.c : 225 ] assert:r0=0x%x, r1=0x%x, line:0x%x + +509,I,[ mac_core_main.c : 147 ] mac_core_work_loop_init: invalid wlan_driver_mode 0x%x +522,iii,[ pktgen.c : 200 ] pktgen_calc_aggr_size: adjust pkt len: orig=%d adjust=%d mpdu=%d +521,iii,[ pktgen.c : 1692 ] pktgen_tx_msg_handler msg hdlr: pkt len = %d pdev_id = %d mode = %d + +520,I,[ pktgen.c : 1652 ] pktgen_data_tx_start_msg_send dev->running=0x%x +519,,[ pktgen.c : 1875 ] pktgen_data_tx_stop_msg_send + +518,I,[ pktgen.c : 890 ] %s: Unable to get tcl entry + +517,I,[ pktgen.c : 908 ] %s: Unable to get tcl entry + +516,II,[ pktgen.c : 1186 ] %s: we're dead - %u is in use now +Bitmap +515,I,[ pktgen.c : 1195 ] 0x%X +514,I,[ pktgen.c : 783 ] Tx done MAC id %lu + +513,II,[ pktgen.c : 1309 ] %s: we're dead - try to free cookie %lu notused +Bitmap: +512,I,[ pktgen.c : 1318 ] 0x%x +511,,[ pktgen.c : 1321 ] + +528,IIii,[ pktlog.c : 205 ] _pktlog_getbuf: pool_list_alloc failed with size %u type=%u qheap=%d missed=%d +527,i,[ pktlog.c : 361 ] Dropped buffer for pktlog_type:%d +526,I,[ pktlog.c : 778 ] FLUSHSTATS INFRA_4 HIF RINGSEND buffer:0x%x +525,I,[ pktlog.c : 714 ] _pktlog_disable: already disabled, bmap=0x%x +524,I,[ pktlog.c : 588 ] _pktlog_enable: already enabled, bmap=0x%x +523,II,[ pktlog.c : 593 ] _pktlog_enable: enable %u evlist %08x +535,iii,[ wal_channel_change_hw.c : 796 ] ADFS_DUMPS MAC-Received agile channel command for center_freq1:%d center_freq2:%d flags=%d + +534,i,[ wal_channel_change_hw.c : 802 ] ADFS_DUMPS rc=%d + +533,IiIIII,[ wal_channel_change_hw.c : 469 ] WAL_DBGID_CHANNEL_CHANGE_FORCE_RESET: mhz = %04d mac_id = %d phy_mode = %02d flags = 0x%04x rx_stop|tx_stop = 0x%x pf_cnt = %02d +532,iiii,[ wal_channel_change_hw.c : 679 ] wal_channel_change: DPD_AbortSpectral = %d AbortTxRx = %d WhalChanSwitch_TxRxResume = %d DPD_ResumeSpectral = %d +531,IiIII,[ wal_channel_change_hw.c : 478 ] WAL_DBGID_CHANNEL_CHANGE: mhz = %04d mac_id = %d phy_mode = %02d flags = 0x%04x pf_cnt = %02d +530,ii,[ wal_channel_change_hw.c : 586 ] phyId %d Caling DPD SM for home channel %d + +529,iiii,[ wal_channel_change_hw.c : 716 ] GreenAP wal_set_greenap_channel error tx/rx chainmask: %d/%d, phy_mode: %d, flag: %d +560,IiIiiIii,[ ar_wal_tx_de.c : 2738 ] security: WAL_DBGID_TX_EAPOL_PKT typeorlen:0x%x sw_peer_id:%d peer_mac:0x%x encap_type:%d hdr_len:%d msdu_ethertype:0x%x eapol_pkt_type:%d len:%d +559,iiiiI,[ ar_wal_tx_de.c : 2879 ] security: WAL_DBGID_TX_EAPOL_PKT sw_peer_id:%d M%d or G%d key_type:%d key_val:0x%x +558,,[ ar_wal_tx_de.c : 1784 ] DE classify: invalid bcast mcast +557,iiiI,[ ar_wal_tx_de.c : 1916 ] DE enq: ARP req|actual_tid_num = %d %d arp_debug_cnt = %d arp_type = %x +556,IIIIIIII,[ ar_wal_tx_de.c : 1918 ] ARP packet details = %x %x %x %x %x %x %x %x + +555,,[ ar_wal_tx_de.c : 1921 ] DEBUG_NUD_FAILURE: MAX consecutive ARPs enqueued with out response +554,ii,[ ar_wal_tx_de.c : 1964 ] DE enq: DHCP|actual_tid_num = %d %d +553,,[ ar_wal_tx_de.c : 2494 ] WAL_DBGID_TX_EAPOL_PKT peer is disassoced +552,,[ ar_wal_tx_de.c : 2501 ] WAL_DBGID_TX_EAPOL_PKT qpeer is not valid +551,iiIiIiI,[ ar_wal_tx_de.c : 1629 ] DE enq: sw_peer_id=%d tid=%d fc=0x%x type=%d msdu_flags=0x%x len=%d id=0x%x +550,iIiIiIIii,[ ar_wal_tx_de.c : 1648 ] security: WAL_DBGID_TX_EAPOL_PKT DE enq: sw_peer_id:%d peer_flags:0x%x tid:%d tid_flags:0x%x is_rc4:%d, fc:0x%x msdu_flags:0x%x len:%d enq_status:%d +549,i,[ ar_wal_tx_de.c : 1663 ] security: WAL_DBGID_TX_EAPOL_PKT lookup failed: enq_discard ret:%d +548,ii,[ ar_wal_tx_de.c : 407 ] wal_tx_de_wbm_complete_handler vdev_id = %d, buffer_id = %d +547,ii,[ ar_wal_tx_de.c : 413 ] wal_tx_de_wbm_complete_handler WAL_BUFFERID_TX_DELETE_ALL_PEER_TCL_DUMMY_FRAME vdev_id = %d, peer_id = %d +546,i,[ ar_wal_tx_de.c : 424 ] wal_tx_de_wbm_complete_handler WAL_VDEV_DEL_ALL_PEER_TCL_DUMMY_FRAME_DONE vdev_id = %d +545,ii,[ ar_wal_tx_de.c : 429 ] wal_tx_de_wbm_complete_handler WAL_BUFFERID_TX_DELETE_ALL_PEER_TQM_DUMMY_FRAME vdev_id = %d, peer_id = %d +544,i,[ ar_wal_tx_de.c : 440 ] wal_tx_de_wbm_complete_handler WAL_VDEV_DEL_ALL_PEER_TQM_DUMMY_FRAME_DONE vdev_id = %d +543,i,[ ar_wal_tx_de.c : 455 ] wal_tx_de_wbm_complete_handler WAL_VDEV_DEL_ALL_PEER_TCL_DUMMY_FRAME_DONE & WAL_VDEV_DEL_ALL_PEER_TQM_DUMMY_FRAME_DONE vdev_id = %d +542,iii,[ ar_wal_tx_de.c : 458 ] wal_tx_de_wbm_complete_handler vdev_id = %d, thread_id = %d, msg_id = %d +541,IiIiii,[ ar_wal_tx_de.c : 3052 ] DE wbm2fw: cookie=0x%x sw_peer_id=%d flags=0x%x msdu_len=%d rel_md=%d,rel_reason=%d +540,iIIiii,[ ar_wal_tx_de.c : 3074 ] security: WAL_DBGID_TX_EAPOL_PKT wbm2fw: sw_peer_id:%d cookie:0x%x flags:0x%x msdu_len:%d rel_md:%d rel_reason:%d +539,i,[ ar_wal_tx_de.c : 3813 ] wal_tx_de_delete_all_peer_handler vdev_id = %d +538,,[ ar_wal_tx_de.c : 3157 ] invalid_msdu - about to free to FW +537,,[ ar_wal_tx_de.c : 3162 ] invalid_msdu - about to free to host +536,IIII,[ ar_wal_tx_de.c : 3791 ] restore SN: tid=%x, mpdu_last_seq_num=%X, frameq=%p %x +622,,[ wal_phy_dev_hw.c : 10544 ] AWGN_INT_DBG : cca_int reduce BW 20Mhz + +621,,[ wal_phy_dev_hw.c : 10547 ] AWGN_INT_DBG : cca_int reduce BW 40Mhz + +620,,[ wal_phy_dev_hw.c : 10551 ] AWGN_INT_DBG : cca_in Primary + +619,,[ wal_phy_dev_hw.c : 10555 ] AWGN_INT_DBG : cca_int reduce BW 80Mhz + +618,,[ wal_phy_dev_hw.c : 10576 ] AWGN_INT_DBG : cca_int ack restore + +617,i,[ wal_phy_dev_hw.c : 10582 ] AWGN_INT_DBG : cca_int bw restore cur_bw = %d + +616,I,[ wal_phy_dev_hw.c : 10604 ] AWGN_INT_DBG : bw_drop cca_seg =0x%x + +615,i,[ wal_phy_dev_hw.c : 10612 ] AWGN_INT_DBG : bw_drop restore cur_bw = %d + +614,,[ wal_phy_dev_hw.c : 10620 ] AWGN_INT_DBG : pkt_drop ack blk + +613,,[ wal_phy_dev_hw.c : 10627 ] AWGN_INT_DBG : pkt_drop ack restore + +612,Iiii,[ wal_phy_dev_hw.c : 10633 ] AWGN_INT_DBG : Sending WMI Event cca_seg =0x%x cca_int = %d pkt_drop = %d bw_drop = %d + +611,II,[ wal_phy_dev_hw.c : 10661 ] AWGN_INT_DBG : setting awgn_hw_cca_mask = 0x%x g_awgn_ed_mask[cur_bw]) = 0x%x + +610,I,[ wal_phy_dev_hw.c : 10670 ] AWGN_INT_DBG : restore awgn_hw_cca_mask = 0x%x + +609,I,[ wal_phy_dev_hw.c : 8600 ] WAL_DBGID_DEV_TX_TIMEOUT 0x%x +608,iIIIII,[ wal_phy_dev_hw.c : 7842 ] %d [CCA:myRxFrame]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +607,iIIIII,[ wal_phy_dev_hw.c : 7847 ] %d [CCA:rxFrame]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +606,iIIIII,[ wal_phy_dev_hw.c : 7852 ] %d [CCA:rx_busy_cnt]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +605,iIIIII,[ wal_phy_dev_hw.c : 7857 ] %d [CCA:tx_frame_cnt]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +604,,[ wal_phy_dev_hw.c : 2190 ] Don't reset as CHIP IS IN POWER DOWN STATE +603,II,[ wal_phy_dev_hw.c : 2724 ] ctrl_path_stats_dbg: mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x + +602,ii,[ wal_phy_dev_hw.c : 9995 ] unit_test_cmd : AXI latency Read :%d module: %d +601,ii,[ wal_phy_dev_hw.c : 9998 ] unit_test_cmd : AXI latency Write :%d module: %d +600,i,[ wal_phy_dev_hw.c : 9805 ] unit_test_cmd : wal_hw_err_reinjection_timer_hdlr pm_mac_state %d +599,i,[ wal_phy_dev_hw.c : 9817 ] unit_test_cmd : TX flush count %d +598,i,[ wal_phy_dev_hw.c : 9831 ] unit_test_cmd : RX abort count %d +597,i,[ wal_phy_dev_hw.c : 9844 ] unit_test_cmd : RX flush count %d +596,i,[ wal_phy_dev_hw.c : 9866 ] unit_test_cmd : Host2HW Ring count %d +595,i,[ wal_phy_dev_hw.c : 9904 ] unit_test_cmd : FW2HW Ring count %d +594,i,[ wal_phy_dev_hw.c : 9936 ] unit_test_cmd : HW2HW Ring count %d +593,ii,[ wal_phy_dev_hw.c : 9967 ] unit_test_cmd : Rx data path error type:%d count %d +592,,[ wal_phy_dev_hw.c : 9982 ] unit_test_cmd : Timer stop +591,I,[ wal_phy_dev_hw.c : 7603 ] PHY M3 requested WARM reset for PHY: %x + +590,I,[ wal_phy_dev_hw.c : 7624 ] PHY M3 Assert for PHY: %x + +589,I,[ wal_phy_dev_hw.c : 7610 ] PHY M3 SSR is enabled, restarting M3: %x + +588,III,[ wal_phy_dev_hw.c : 7617 ] M3SSR asserted on pdev:%x MAC_ID:%x ts:%x + +587,Iii,[ wal_phy_dev_hw.c : 10465 ] AWGN_INT_DBG get = 0x%x period = %d inited = %d +586,IIIIIII,[ wal_phy_dev_hw.c : 10157 ] AWGN_INT_DBG register read ed = 0x%x gi = 0x%x sec_mask = 0x%x seg =0x%x intr = 0x%x bw = 0x%x bw_mask = 0x%x + +585,I,[ wal_phy_dev_hw.c : 10392 ] AWGN_INT_DBG Interrupt detected at Segment = 0x%x + +584,I,[ wal_phy_dev_hw.c : 10407 ] AWGN_INT_DBG Interrupt detected at Segment = 0x%x + +583,II,[ wal_phy_dev_hw.c : 10432 ] AWGN_INT_DBG Pri gi_mask = 0x%x mask = 0x%x + +582,II,[ wal_phy_dev_hw.c : 10447 ] AWGN_INT_DBG Sec gi_mask = 0x%x mask = 0x%x + +581,IiiiiIii,[ wal_phy_dev_hw.c : 10176 ] AWGN_INT_DBG compute_cca current_time = %ld cca1 = %d cca2 = %d ed_mu = %d gi_mu = %d cc_cnt = %ld tx_frm = %d rx_frm = %d + +580,iiiiii,[ wal_phy_dev_hw.c : 10188 ] AWGN_INT_DBG tx_frame_1 = %d tx_frame = %d rx_frame_1 = %d rx_frame = %d cc_1 = %d cc = %d + +579,iii,[ wal_phy_dev_hw.c : 10196 ] AWGN_INT_DBG tx_prop = %d rx_prop = %d cc_diff = %d + +578,iiii,[ wal_phy_dev_hw.c : 10238 ] AWGN_INT_DBG p_cca1 = %d p_cca2 = %d time_diff = %d fudge_fact = %d + +577,IIiiiiii,[ wal_phy_dev_hw.c : 10272 ] AWGN_INT_DBG cur_time = 0x%x current_time = %ld cca1 = %d cca2 = %d ed_mu = %d gi_mu = %d awgn_cca_edmu_ind = %d interference_count = %d + +576,iii,[ wal_phy_dev_hw.c : 10282 ] AWGN_INT_DBG awgn_cca_cnt_hit = %d tx_prop = %d rx_prop = %d + +575,i,[ wal_phy_dev_hw.c : 10288 ] AWGN_INT_DBG awgn_cca_cnt_hit = %d + +574,iii,[ wal_phy_dev_hw.c : 10320 ] AWGN_INT_DBG time_diff = %d ccaCntr1 = %d ccaCntr2 = %d + +573,iiiiii,[ wal_phy_dev_hw.c : 10331 ] AWGN_INT_DBG tx_frame_1 = %d tx_frame = %d rx_frame_1 = %d rx_frame = %d cc_1 = %d cc = %d + +572,iii,[ wal_phy_dev_hw.c : 10336 ] AWGN_INT_DBG tx_prop = %d fudge_fact = %d cc_diff = %d + +571,III,[ wal_phy_dev_hw.c : 10353 ] AWGN_INT_DBG compute_seg ed_mu = 0x%x gi_mu = 0x%x int_detected = 0x%x + +570,II,[ wal_phy_dev_hw.c : 10374 ] AWGN_INT_DBG Interrrupt Not detected gi_mask = 0x%x sec_mask = 0x%x + +569,iii,[ wal_phy_dev_hw.c : 1997 ] WAL_PDEV_RESUME_REQ req = %d, is_pdev_pause = %d pdev_state = %d +568,iiiiii,[ wal_phy_dev_hw.c : 1908 ] WAL_PDEV_SUSPEND_REQ req = %d, reason %d, is_pdev_pause = %d, force_sync = %d, resume_inline = %d pdev_state = %d +567,iIIIII,[ wal_phy_dev_hw.c : 8039 ] %d [TX_RX_STATS:hw_queued]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +566,iIIIII,[ wal_phy_dev_hw.c : 8048 ] %d [TX_RX_STATS:hw_reaped]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +565,iIIIII,[ wal_phy_dev_hw.c : 8058 ] %d [TX_RX_STATS:hw_flush]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +564,iIIIII,[ wal_phy_dev_hw.c : 8068 ] %d [TX_RX_STATS:hw_filt]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +563,iIIIII,[ wal_phy_dev_hw.c : 8078 ] %d [TX_RX_STATS:ppdu_recvd]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +562,iIIIII,[ wal_phy_dev_hw.c : 8088 ] %d [TX_RX_STATS:mpdu_cnt_fcs_ok]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +561,iIIIII,[ wal_phy_dev_hw.c : 8098 ] %d [TX_RX_STATS:ppdu_recvd]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +642,II,[ wal_soc_dev_hw.c : 370 ] TCL0 panic interrupt mask : 0x%x, total count 0x%x + +641,II,[ wal_soc_dev_hw.c : 381 ] TCL1 panic interrupt mask : 0x%x, total count 0x%x + +640,II,[ wal_soc_dev_hw.c : 475 ] TQM0 panic interrupt mask : 0x%x, total count 0x%x + +639,II,[ wal_soc_dev_hw.c : 518 ] TQM1 panic interrupt mask : 0x%x, total count 0x%x + +638,II,[ wal_soc_dev_hw.c : 604 ] TQM2 panic interrupt mask : 0x%x, total count 0x%x + +637,II,[ wal_soc_dev_hw.c : 740 ] APB panic interrupt mask : 0x%x, total count 0x%x + +636,II,[ wal_soc_dev_hw.c : 749 ] MEM panic interrupt mask : 0x%x, total count 0x%x + +635,II,[ wal_soc_dev_hw.c : 758 ] WBM0 panic interrupt mask : 0x%x, total count 0x%x + +634,II,[ wal_soc_dev_hw.c : 814 ] WBM1 panic interrupt mask : 0x%x, total count 0x%x + +633,II,[ wal_soc_dev_hw.c : 831 ] WBM2 panic interrupt mask : 0x%x, total count 0x%x + +632,II,[ wal_soc_dev_hw.c : 845 ] RE0 panic interrupt mask : 0x%x, total count 0x%x + +631,II,[ wal_soc_dev_hw.c : 854 ] REO1 panic interrupt mask : 0x%x, total count 0x%x + +630,II,[ wal_soc_dev_hw.c : 863 ] REO2 panic interrupt mask : 0x%x, total count 0x%x + +629,II,[ wal_soc_dev_hw.c : 872 ] REO3 panic interrupt mask : 0x%x, total count 0x%x + +628,II,[ wal_soc_dev_hw.c : 898 ] REO4 panic interrupt mask : 0x%x, total count 0x%x + +627,II,[ wal_soc_dev_hw.c : 907 ] GXI panic interrupt mask : 0x%x, total count 0x%x + +626,I,[ wal_soc_dev_hw.c : 1712 ] PN dummy MSDU(%x) returned +625,iII,[ wal_soc_dev_hw.c : 1250 ] Enter/Exit WoW mode :%d,timestamp:%x, reo2sw1:0x%x +624,,[ wal_soc_dev_hw.c : 1295 ] Entering into WoW mode is done +623,,[ wal_soc_dev_hw.c : 1320 ] Exiting from WoW mode is done +643,iIiiii,[ ar_wal_vdev_hw.c : 366 ] VDEV migration sync: ba_migrate, thread_id=%d, peer=%p, vdev_id=%d, vdev_type=%d, pdev_id=%d:%d +667,iiii,[ wal_soc_debug.c : 544 ] wal_unit_test: num_args = %d test_cmd = %d arg[1] = %d arg[2] = %d +666,,[ wal_soc_debug.c : 1038 ] Recorded page fault count reset to 0 +665,i,[ wal_soc_debug.c : 1040 ] Total page fault count: %d +664,i,[ wal_soc_debug.c : 1044 ] Recorded page fault count: %d +663,i,[ wal_soc_debug.c : 1046 ] Total page fault count: %d +662,i,[ wal_soc_debug.c : 1190 ] Triggering forced crash into PHY M3: PHY ID %d +661,IIIII,[ wal_soc_debug.c : 1211 ] pcss_ring_feeder num_interrupts:%u, num_pcss_elem_zero:%u, num_in_elem_zero:%u, num_out_elem_zero:%u, num_elem_moved:%u + +660,iiii,[ wal_soc_debug.c : 1393 ] wal_unit_test: num_args = %d test_cmd = %d arg[1] = %d arg[2] = %d +659,I,[ wal_soc_debug.c : 904 ] page fault in wow: 0x%x +658,,[ wal_soc_debug.c : 1427 ] +657,,[ wal_soc_debug.c : 1428 ] Hardware Address Search Table +656,,[ wal_soc_debug.c : 1429 ] +655,,[ wal_soc_debug.c : 1437 ] DDR AST Entries +654,i,[ wal_soc_debug.c : 1438 ] Num AST Entries : %d +653,,[ wal_soc_debug.c : 1445 ] +652,iiIIIIII,[ wal_soc_debug.c : 1446 ] %d) AST index : %d MAC Address : %x:%x:%x:%x:%x:%x +651,iii,[ wal_soc_debug.c : 1447 ] sw_peer_id : %d next_hop : %d mcast : %d +650,,[ wal_soc_debug.c : 1451 ] +649,,[ wal_soc_debug.c : 1452 ] On-Chip AST Entries +648,i,[ wal_soc_debug.c : 1037 ] Recorded page fault count: %d +647,i,[ wal_soc_debug.c : 1453 ] Num AST Entries : %d +646,,[ wal_soc_debug.c : 1461 ] +645,iiIIIIII,[ wal_soc_debug.c : 1462 ] %d) AST index : %d MAC Address : %x:%x:%x:%x:%x:%x +644,iii,[ wal_soc_debug.c : 1463 ] sw_peer_id : %d next_hop : %d mcast : %d +668,Ii,[ direct_dma_config.c : 212 ] dma_prepare %p status %d +674,IIIIIIII,[ host_ring_reader.c : 348 ] host ring reader %p has base address 0x%08x%08x, %u elements, tail address 0x%08x%08x, head address 0x%08x%08x +673,IIIIII,[ host_ring_reader.c : 162 ] host_ring_reader_read_elems: reader %p head_idx %u tail_idx %u shadow_tail_idx %u num_avail %u num_free %u +672,III,[ host_ring_reader.c : 183 ] tail dirty host ring reader %p head index is %u, shadow tail index is %u +671,II,[ host_ring_reader.c : 81 ] host_ring_reader_read_elems_compl: host ring reader %p read %u elements +670,I,[ host_ring_reader.c : 298 ] host ring reader %p stop request +669,IIIi,[ host_ring_reader.c : 39 ] host ring reader %p failed to copy from address 0x%08x%08x with status %d +679,iiI,[ pcss_ring_feeder.c : 242 ] PHY %d ring %d has %u elements remaining +678,III,[ pcss_ring_feeder.c : 268 ] pcss_ring_feeder_handle_ipc : head = %u shadow_head = %u and num_elems = %u for out_ring +677,I,[ pcss_ring_feeder.c : 279 ] pcss_ring_feeder_handle_ipc : num elems_dmaed = %u for out_ring +676,iiII,[ pcss_ring_feeder.c : 383 ] PHY %d ring %d needs %u elements; have %u +675,iiIIIIII,[ pcss_ring_feeder.c : 503 ] pcss_ring_status_print: PHY %d ring %d event %c%u head_idx %u tail_idx %u num_avail %u num_free %u +709,IIiIi,[ ar_wal_local_frames.c : 2768 ] LOCAL abf completion internal,peer=%x,abf=%x,flags=%d,abf_thread=%x,cur_thread=%d +708,IIiIi,[ ar_wal_local_frames.c : 2774 ] LOCAL abf completion internal,peer=%x,abf=%x,flags=%d,abf_thread=%x,cur_thread=%d +707,IIiIiI,[ ar_wal_local_frames.c : 2666 ] LOCAL abf completion msg:peer_id=%x,abf=%x,flag=%d,abf_thread=%x,cur_thread=%d,target_thread=%x +706,IIIiII,[ ar_wal_local_frames.c : 2623 ] Deliver LOCAL buffer sending msg failure: tid=%x,peer=%x,abf=%x,flag=%d,target_thread=%x, is_data:%x +705,ii,[ ar_wal_local_frames.c : 1526 ] Local data send: use default tid, requested TID:%d, tid_alloc_status=%d +704,II,[ ar_wal_local_frames.c : 1730 ] Local EAPOL M4 duplicated, peer:%x, qpeer-flag=%x +703,iiI,[ ar_wal_local_frames.c : 1786 ] Local data send: use tqm-tid %d, num:%d, flags:0x%x +702,iiIII,[ ar_wal_local_frames.c : 1850 ] local_data_frame_send vdev_id=%d mac_id=%d seq_num=0x%x type=0x%x status =0x%x +701,III,[ ar_wal_local_frames.c : 231 ] MGMT_TX_WMI_FROM_HOST TX COMP: flags = 0x%x buffer_id = 0x%x fc = 0x%x +700,IIIiii,[ ar_wal_local_frames.c : 503 ] local_frame_handle_completion: SN=%u/%u, type=0x%x, thread=%d/%d, status=%d +699,iii,[ ar_wal_local_frames.c : 518 ] local_frame_handle_completion: thread=%d/%d, status=%d +698,iiIIIIi,[ ar_wal_local_frames.c : 380 ] WAL_DBGID_TX_MGMT_COMP_DESCID_STATUS vdev_id=%d mac_id=%d dec_id=0x%x tx_status=0x%x tid=0x%x buffer_id=0x%x reset_cnt=%d +697,iI,[ ar_wal_local_frames.c : 384 ] WAL_DBGID_TX_MGMT_COMP_DESCID_STATUS vdev_id=%d tx_status=0x%x +696,IIIIiiIiI,[ ar_wal_local_frames.c : 623 ] local_frame_handle_completion_tqm, DA:%X-%X,type=0x%X,DATA:0x%X,thread=%d/%d,cookie=%X,status=%d,flags=0x%x +695,ii,[ ar_wal_local_frames.c : 1151 ] WAL_DBGID_TX_MGMT_ENQUEUE_FAILED vdev_id = %d tid:%d +694,II,[ ar_wal_local_frames.c : 1179 ] tid=%x isnt pre-allocated, qpeer_flags=%x +693,iiIIIII,[ ar_wal_local_frames.c : 1380 ] WAL_DBGID_TX_MGMT_DESCID_SEQ_TYPE_LEN vdev_id=%d mac_id=%d cookie=0x%x seq_num=0x%x type=0x%x len=0x%x tid_flg=0x%x +692,iiIIIII,[ ar_wal_local_frames.c : 1391 ] DBG WAL_DBGID_TX_MGMT_DESCID_SEQ_TYPE_LEN vdev_id=%d mac_id=%d cookie=0x%x seq_num=0x%x type=0x%x len=0x%x tid_flg=0x%x +691,IIi,[ ar_wal_local_frames.c : 1416 ] ctrl_path_stats_dbg: mac_address equal mac_0 = 0x%x mac_2 =0x%x subtype = %d + +690,iII,[ ar_wal_local_frames.c : 2551 ] send local buffer fail: sw_peer_id=%d migration in progress mac_addr_31_0=%x mac_addr_47_32=%x +689,II,[ ar_wal_local_frames.c : 2581 ] send local buffer fail: status=%x, flags=%x +688,IIII,[ ar_wal_local_frames.c : 2514 ] local_data, peer(%p, sw_peer_id:%x) pdev mismatch(%p:%p) +687,IIII,[ ar_wal_local_frames.c : 2459 ] local_mgmt, peer(%p, sw_peer_id:%x) pdev mismatch(%p:%p) +686,ii,[ ar_wal_local_frames.c : 2021 ] WAL_DBGID_TX_MGMT_ENQUEUE_FAILED vdev_id = %d tid:%d +685,IIII,[ ar_wal_local_frames.c : 2076 ] host_mgmt, peer(%p, sw_peer_id:%x) pdev mismatch(%p:%p) +684,Ii,[ ar_wal_local_frames.c : 2098 ] MGMT_TX_WMI_FROM_HOST flags = %x, is_wmi = %d +683,iiIIII,[ ar_wal_local_frames.c : 2239 ] WAL_DBGID_TX_MGMT_DESCID_SEQ_TYPE_LEN vdev_id=%d mac_id=%d cookie=0x%x seq_num=0x%x type=0x%x len=0x%x +682,iiIIII,[ ar_wal_local_frames.c : 2249 ] DBG WAL_DBGID_TX_MGMT_DESCID_SEQ_TYPE_LEN vdev_id=%d mac_id=%d cookie=0x%x seq_num=0x%x type=0x%x len=0x%x +681,IIi,[ ar_wal_local_frames.c : 2271 ] ctrl_path_stats_dbg: mac_address equal mac_0 = 0x%x mac_2 =0x%x subtype = %d + +680,iIiiI,[ ar_wal_local_frames.c : 2306 ] WAL_DBGID_MGMT_TX_FAIL vdev_id=%d, err_code=%x, cookie=%d, status=%d, fc[0]=%x +735,iiiii,[ ar_wal_monitor.c : 1455 ] wal_monitor, wbm2sw2 monitor: pdev %d: timestamp(ms)=%d ring hp=%d tp=%d free_buf_cnt=%d +734,i,[ ar_wal_monitor.c : 1466 ] dev-%d:POLICY_ENFORCE_STATE --> MONITOR_TIMER_RUNNING_STATE +733,i,[ ar_wal_monitor.c : 517 ] dev-%d:TIMER_RUNNING_STATE --> MONITOR_STATS_COLLECTION_STATE +732,i,[ ar_wal_monitor.c : 544 ] dev-%d:WAIT_POLICY_ENFORCE_STATE --> MONITOR_POLICY_ENFORCE_STATE +731,iii,[ ar_wal_monitor.c : 423 ] Tput Monitor pdev_id: %d, Bandwidth: %d.%d Gbits/sec +730,iii,[ ar_wal_monitor.c : 427 ] Tput Monitor pdev_id: %d, Bandwidth: %d.%d Mbits/sec +729,ii,[ ar_wal_monitor.c : 431 ] Tput Monitor pdev_id: %d, Bandwidth: %d Kbits/sec +728,ii,[ ar_wal_monitor.c : 436 ] Tput Monitor pdev_id: %d, Bandwidth: %d bits/sec +727,iIIIIIIII,[ ar_wal_monitor.c : 449 ] Tput Monitor pdev_id: %d, mpdu_byte_cnt -> [BE]:0x%x%x, [BK]:0x%x%x, [VI]:0x%x%x, [VO]:0x%x%x +726,iii,[ ar_wal_monitor.c : 462 ] Tput Monitor pdev_id: %d, MSDU Bandwidth: %d.%d Gbits/sec +725,iii,[ ar_wal_monitor.c : 466 ] Tput Monitor pdev_id: %d, MSDU Bandwidth: %d.%d Mbits/sec +724,ii,[ ar_wal_monitor.c : 470 ] Tput Monitor pdev_id: %d, MSDU Bandwidth: %d Kbits/sec +723,ii,[ ar_wal_monitor.c : 475 ] Tput Monitor pdev_id: %d, MSDU Bandwidth: %d bits/sec +722,iIIIIIIII,[ ar_wal_monitor.c : 488 ] Tput Monitor pdev_id: %d, msdu_byte_cnt -> [BE]:0x%x%x, [BK]:0x%x%x, [VI]:0x%x%x, [VO]:0x%x%x +721,i,[ ar_wal_monitor.c : 976 ] dev-%d:STATS_COLLECTION_STATE --> MONITOR_WAIT_POLICY_ENFORCE_STATE +720,ii,[ ar_wal_monitor.c : 988 ] dev-%d:STATS_COLLECTION_STATE --> MONITOR_STATS_COLLECTION_STATE last_peer_idx:%d +719,i,[ ar_wal_monitor.c : 390 ] dev-%d:INIT_STATE --> MONITOR_TIMER_RUNNING_STATE +718,IIiI,[ ar_wal_monitor.c : 394 ] %s %s send signal=%d to thread=%s to start timer + +717,IIiI,[ ar_wal_monitor.c : 106 ] %s %s send signal=%d to thread=%s to yield + +716,iiii,[ ar_wal_monitor.c : 1192 ] CONGCTRL HOST_CONTROL UPDATE aid:%d tid_num:%d threshold_1:%d threshold_2:%d + +715,iii,[ ar_wal_monitor.c : 1217 ] CONGCTRL HOST_CONTROL UPDATE aid:%d tid_num:%d new drop_threshold:%d +714,iii,[ ar_wal_monitor.c : 1258 ] CONGCTRL FW_CONTROL UPDATE aid:%d tid_num:%d new drop_threshold:%d +713,iiI,[ ar_wal_monitor.c : 1293 ] CONGCTRL peer_id:%d tid_num:%d msduq_mask:0x%08x +712,iiiiiii,[ ar_wal_monitor.c : 1104 ] CONGCTRL HOST_CONTROL peer_id:%d tid_num:%d traffic_enq:%d drop:%d deq:%d old_threshold:%d new_threshold:%d +711,iii,[ ar_wal_monitor.c : 845 ] qstats_update peer_id:%d tid_num:%d qtype:%d +710,IIIIIi,[ ar_wal_monitor.c : 309 ] _wal_txrx_monitor_pdev_record: type %x rx msdu %x ppdu %x, tx msdu %x ppdu %x phy_mode %d + +758,,[ ar_wal_ast.c : 609 ] WAL_DBGID_AST_ENTRY_FULL WAL_ENOSPC +757,Ii,[ ar_wal_ast.c : 661 ] onchip_ast_idx:0x%x sw_peer_id:%d +756,,[ ar_wal_ast.c : 1837 ] WAL_DBGID_AST_ENTRY_EXIST WAL_EEXIST +755,IIII,[ ar_wal_ast.c : 1846 ] WAL_AST_ALLOC_PEER peer_mac:0x%x ast_index:0x%x sw_peer_id:0x%x ast_flags:0x%x +754,i,[ ar_wal_ast.c : 1796 ] ar_wal_ast_dummy_alloc_peer ast_index = %d +753,III,[ ar_wal_ast.c : 739 ] WAL_DBGID_AST_DEL_WDS_ENTRY 0x%x 0x%x 0x%x +752,IIII,[ ar_wal_ast.c : 1981 ] WAL_DBGID_AST_ADD_MONITOR_DIRECT_ENTRY 0x%x 0x%x 0x%x 0x%x +751,IIII,[ ar_wal_ast.c : 1998 ] WAL_DBGID_AST_ADD_MONITOR_DIRECT_ENTRY 0x%x 0x%x 0x%x 0x%x +750,IIIIi,[ ar_wal_ast.c : 2003 ] WAL_DBGID_AST_ADD_MONITOR_DIRECT_ENTRY 0x%x 0x%x 0x%x 0x%x pdev_id:%d +749,IIIII,[ ar_wal_ast.c : 1426 ] WAL_DBGID_AST_ADD_WDS_ENTRY 0x%x 0x%x 0x%x 0x%x 0x%x +748,IIIII,[ ar_wal_ast.c : 1462 ] WAL_DBGID_AST_ADD_WDS_ENTRY 0x%x 0x%x 0x%x 0x%x 0x%x +747,IIIIIi,[ ar_wal_ast.c : 1476 ] WAL_DBGID_AST_ADD_WDS_ENTRY 0x%x 0x%x 0x%x 0x%x 0x%x pdev_id:%d +746,II,[ ar_wal_ast.c : 2147 ] WAL_DBGID_AST_DEL_ALL_MONITOR_DIRECT_ENTRY 0x%x 0x%x +745,II,[ ar_wal_ast.c : 1613 ] WAL_DBGID_AST_FREE_WDS_ENTRY des_mac is not next_hop or monitor direct 0x%x 0x%x +744,IIII,[ ar_wal_ast.c : 2050 ] WAL_DBGID_AST_DEL_MONITOR_DIRECT_ENTRY 0x%x 0x%x 0x%x 0x%x +743,IIII,[ ar_wal_ast.c : 2091 ] WAL_DBGID_AST_DEL_MONITOR_DIRECT_ENTRY 0x%x 0x%x 0x%x 0x%x +742,I,[ ar_wal_ast.c : 2511 ] SW peer key not found, peer_mac-0x%x +741,IiIIIII,[ ar_wal_ast.c : 2525 ] Update reorder queue peer_mac-0x%x, sw_peer_id-%d, queue_addr-0x%x:0x%x, queue-%x, ba_win-0x%x:0x%x +740,IIII,[ ar_wal_ast.c : 2571 ] HIF_memcpy: rx_reo_queue_desc_addr_31_0:%x rx_reo_queue_desc_addr_39_32:%x queue_addr_lo:%x queue_addr_hi:%x +739,IIi,[ ar_wal_ast.c : 1525 ] WAL_DBGID_AST_UPDATE_WDS_ENTRY FAILED due to peer mac search failed 0x%x 0x%x pdev_id:%d +738,IIi,[ ar_wal_ast.c : 1533 ] WAL_DBGID_AST_UPDATE_WDS_ENTRY FAILED due to dest mac search failed 0x%x 0x%x pdev_id:%d +737,IIII,[ ar_wal_ast.c : 1554 ] WAL_DBGID_AST_UPDATE_WDS_ENTRY 0x%x 0x%x 0x%x 0x%x +736,IIII,[ ar_wal_ast.c : 1564 ] WAL_DBGID_AST_UPDATE_WDS_ENTRY des_mac is not next_hop 0x%x 0x%x 0x%x 0x%x +851,ii,[ ar_wal_peer.c : 11672 ] _wal_peer_alloc_tid: got tid flush handle for tidno %d sw_peer_id:%d + +850,IiiiI,[ ar_wal_peer.c : 11753 ] ul_dbg_tid_alloc: peer=0x%x, tidno=%d, ac=%d, timeout_ms=%d, tid_ptr=0x%x +849,i,[ ar_wal_peer.c : 11803 ] _wal_peer_alloc_tid: adding tid %d to temp tid list + +848,iIIIII,[ ar_wal_peer.c : 1293 ] pdev_id: %d ar_wal_peer_clean_up_flow:%x,%x,%x,%x,%x, +847,III,[ ar_wal_peer.c : 1306 ] ar_wal_peer_clean_up_flow:%x,%x,%x +846,IIIII,[ ar_wal_peer.c : 3556 ] FREE_AST_ENTRY: peer=%p mac_addr=0x%x %x ast_index=0x%x valid_bmap[ast_index]=0x%x +845,ii,[ ar_wal_peer.c : 11925 ] _ar_wal_peer_free_tid: sw_peer_id=%d, tidno=%d +844,ii,[ ar_wal_peer.c : 11939 ] _ar_wal_peer_free_tid: sending tid flush cmd to tac thread_id=%d, tidno=%d + +843,iiIiII,[ ar_wal_peer.c : 15293 ] mpdu_reconstruct_block_cb:pdev(%d)peer %d,flags=0x%x,del=%d,block=0x%x,recon=0x%x +842,IIIIII,[ ar_wal_peer.c : 5241 ] pdev(%x)peer %x blocked for tidLen update,refcnt=%x,htc=%x,remap=%x,security=%x +841,iIiI,[ ar_wal_peer.c : 5428 ] security: ar_wal_peer_set_key_block_cb: peer_id:%d peer_flags:%02x authrized:%d qpeer_flags:%x +840,iIi,[ ar_wal_peer.c : 5477 ] security: ar_wal_peer_set_mcast_key_block_cb: peer_id:%d peer_flags:%02x authrized:%d +839,,[ ar_wal_peer.c : 10759 ] qdepth_thresh_update_cmd_handler: Invalid sw_peer_key +838,,[ ar_wal_peer.c : 10766 ] qdepth_thresh_update_cmd_handler: Invalid peer +837,,[ ar_wal_peer.c : 10776 ] qdepth_thresh_update_cmd_handler: is_self_peer or bss_peer +836,,[ ar_wal_peer.c : 10786 ] qdepth_thresh_update_cmd_handler: peer delete in progress +835,i,[ ar_wal_peer.c : 10807 ] qdepth_thresh_update_cmd_handler: not valid TID give tidno:%d +834,i,[ ar_wal_peer.c : 10819 ] qdepth_thresh_update_cmd_handler: not valid tqm tid tidno:%d +833,ii,[ ar_wal_peer.c : 10839 ] qdepth_thresh_update_cmd_handler: qtype:%d host_drop_th:%d +832,ii,[ ar_wal_peer.c : 11968 ] _ar_wal_peer_tidq_empty: thread_id =%d,tidq->tid_num=%d + +831,IIIIIII,[ ar_wal_peer.c : 5146 ] update MPDUq hdrlen, peer=%x,tid_num=%x,tid_flg=%x %x,orig=%x,new=%x,wow=%x +830,IIii,[ ar_wal_peer.c : 1496 ] ar_wal_sw_peer_key_alloc sw_peer_key 0x%x alloc_flag 0x%x remote_sw_peer_key_in_local_mem %d remote_sw_peer_key_cnt_in_local_mem %d +829,Iii,[ ar_wal_peer.c : 1675 ] ar_wal_sw_peer_key_free sw_peer_key 0x%x remote_sw_peer_key_in_local_mem %d remote_sw_peer_key_cnt_in_local_mem %d +828,,[ ar_wal_peer.c : 13812 ] wal_htt_peer_stats_reset: Peer pointer is NULL +827,II,[ ar_wal_peer.c : 13869 ] Htt stats is requested without setting in_progress: Caller 0 %x Caller 1 %x +826,IIii,[ ar_wal_peer.c : 2697 ] WAL_ALLOC_PEER_AST_FAIL peer_addr 0x04%x08%x peer_type:%d, error:%d +825,i,[ ar_wal_peer.c : 3018 ] PEER_ALLOC: peer_id=%d: Fail to allocate wmm_param +824,II,[ ar_wal_peer.c : 3221 ] ADDR_TYPE_A: mac_adr_31_0=0x%x, mac_addr_32_47=0x%x +823,II,[ ar_wal_peer.c : 3224 ] ADDR_TYPE_B peer: mac_adr_31_0=0x%x, mac_addr_32_47=0x%x +822,II,[ ar_wal_peer.c : 3227 ] ADDR_TYPE_C self: mac_adr_31_0=0x%x, mac_addr_32_47=0x%x +821,III,[ ar_wal_peer.c : 14246 ] OMI: Change a_ctrl from 0x%lx to 0x%lx, ULMU Disable is 0x%lx + +820,ii,[ ar_wal_peer.c : 4010 ] wal_peer_delete_conf_msg_hdlr: peer=%d,num_del_in_pro=%d +819,ii,[ ar_wal_peer.c : 4038 ] wal_peer_delete_conf_msg_hdlr: peer = %d, pdev_peer_deletes_in_progress = %d + +818,iiI,[ ar_wal_peer.c : 3898 ] _wal_peer_del_msg_hdlr: thread_id =%d, sw_peer_id=%d, peer->peer_flgs=0x%x + +817,iii,[ ar_wal_peer.c : 4247 ] wal_peer_delete_resume: peer = %d, delete_in_progress %d pdev_peer_deletes_in_progress = %d + +816,,[ ar_wal_peer.c : 15572 ] wal_peer_disable_pdg_notify_acceleration update bss notify reg 1 +815,IiiiiI,[ ar_wal_peer.c : 15578 ] wal_peer_disable_pdg_notify_acceleration sw_peer_id %x notify_acc_enabled %d notify_reg_index %d peer_count %d vdev_type %d rate_code %x +814,iII,[ ar_wal_peer.c : 15136 ] security: WAL_DBGID_SECURITY_PM4_SENT peer_id:%d, peer_flag:0x%x, qpeer_flag:0x%x +813,i,[ ar_wal_peer.c : 12627 ] wal_peer_mcast_cfg AST entry not found for key_id:%d +812,Iii,[ ar_wal_peer.c : 12631 ] wal_peer_fill_mcast_key_info: peer :%0x key_id:%d key_id_type:%d +811,ii,[ ar_wal_peer.c : 4168 ] _wal_peer_free: peer = %d delete_in_progress %d +810,iii,[ ar_wal_peer.c : 12706 ] wal_pm_mcast_cfg: enable :%d encr_en:%d decap_type:%d +809,Ii,[ ar_wal_peer.c : 12592 ] _wal_peer_mcast_key_id_update: peer :%0x key_id:%d +808,IIII,[ ar_wal_peer.c : 14873 ] peer_migrate failed: rx:%x, tx:%x MAC:%x, reset_cause %x +807,iiIiI,[ ar_wal_peer.c : 15338 ] mpdu_reconstruct:pdev(%d)peer %d,flags=0x%x,del=%d,recon=0x%x +806,,[ ar_wal_peer.c : 15383 ] reconstruct_tqm_mpdus: no TIDs to block +805,iIII,[ ar_wal_peer.c : 15215 ] Index= %d, time_stamp_32_61 = 0x%x, time_stamp_0_31= 0x%x, flags = 0x%x +804,II,[ ar_wal_peer.c : 15220 ] A_TIMER_CURRENT_TIME_IN_TICKS time_stamp_32_61 = 0x%x time_stamp_0_31 = 0x%x +803,iIiiiI,[ ar_wal_peer.c : 4417 ] security: wal_peer_set_key: peer:%d, key_info:%p, key_id:%d is_mcast:%d key_type:%d key_flags:%02x +802,i,[ ar_wal_peer.c : 4440 ] _wal_peer_set_key: key_id:%d ignored, PMF +801,i,[ ar_wal_peer.c : 4640 ] _wal_peer_set_key: is_already_set_key_pending:%d +800,II,[ ar_wal_peer.c : 4755 ] WAL_DBGID_SECURITY_UCAST_KEY_SET 0x%x MAC:%x +799,I,[ ar_wal_peer.c : 4764 ] WAL_DBGID_SECURITY_MCAST_KEY_SET 0x%x +798,iI,[ ar_wal_peer.c : 4939 ] security: postponing set key for peer_id:%d peer_flags:%02x +797,iI,[ ar_wal_peer.c : 4969 ] security: wal_peer_set_key: peer:%d peer_flags:%02x +796,i,[ ar_wal_peer.c : 7013 ] WAL_DBGID_SECURITY_SAFE_MODE on: %d +795,iii,[ ar_wal_peer.c : 7068 ] qos: flag: %d and peer_id is %d and qos_flag_rcvd:%d +794,iIii,[ ar_wal_peer.c : 7152 ] security: set_param_authorized: peer:%d peer_flags:%02x, is_remote_peer:%d, is_assoc_link:%d +793,iii,[ ar_wal_peer.c : 7212 ] DYN_MIMO_PS : sw_peer_id %d, dyn_mimo_ps %d, force_dyn_mimo_ps %d + +792,Iii,[ ar_wal_peer.c : 7293 ] security: WAL_PEER_PARAM_TX_KEYID peer_key:%p and peer:%d val:%d + +791,iIIII,[ ar_wal_peer.c : 7439 ] security: WAL_DBGID_SECURITY_ENCR_EN, peer %d, refcnt=%x,htc=%x,remap=%x,security=%x +790,I,[ ar_wal_peer.c : 7849 ] OMI: Set new nss = 0x%lx + +789,I,[ ar_wal_peer.c : 7856 ] OMI: Set new bw = 0x%lx + +788,I,[ ar_wal_peer.c : 7862 ] OMI: Set new a_ctrl = 0x%lx + +787,I,[ ar_wal_peer.c : 7874 ] HTC-block tids, peer:%x +786,I,[ ar_wal_peer.c : 7977 ] WAL_DBGID_SET_M4_SENT_MANUALLY PEER = 0X%X +785,I,[ ar_wal_peer.c : 7982 ] WAL_DBGID_UNSET_M4_SENT_MANUALLY peer = 0x%x +784,I,[ ar_wal_peer.c : 8071 ] WAL_PEER_PARAM_FW_CONGESTION_DISABLE:%x +783,i,[ ar_wal_peer.c : 5980 ] WAL_DBGID_SECURITY_SAFE_MODE on: %d +782,iii,[ ar_wal_peer.c : 6035 ] qos: flag: %d and peer_id is %d and qos_flag_rcvd:%d +781,iIIII,[ ar_wal_peer.c : 6107 ] security: WAL_DBGID_SECURITY_ENCR_EN, peer %d, refcnt=%x,htc=%x,remap=%x,security=%x +780,I,[ ar_wal_peer.c : 6317 ] OMI: Set new nss = 0x%lx + +779,I,[ ar_wal_peer.c : 6324 ] OMI: Set new bw = 0x%lx + +778,I,[ ar_wal_peer.c : 6330 ] OMI: Set new a_ctrl = 0x%lx + +777,I,[ ar_wal_peer.c : 6342 ] HTC-block tids, peer:%x +776,Iii,[ ar_wal_peer.c : 6661 ] security: WAL_PEER_PARAM_TX_KEYID peer_key:%p and peer:%d val:%d + +775,iIii,[ ar_wal_peer.c : 6786 ] security: set_param_authorized: peer:%d peer_flags:%02x, is_remote_peer:%d, is_assoc_link:%d +774,IiiiiI,[ ar_wal_peer.c : 15485 ] wal_peer_set_pdg_notify_reg_set sw_peer_id %x notify_acc_enabled %d notify_reg_index %d peer_count %d vdev_type %d rate_code %x +773,iiIii,[ ar_wal_peer.c : 15002 ] PDEV:%d, peer id=%d, QCU:%x/%d, ena=%d +772,,[ ar_wal_peer.c : 14037 ] Memory ERROR: Cannot retrieve peer stats + +771,,[ ar_wal_peer.c : 14041 ] Invalid stats. Please try again + +770,iIi,[ ar_wal_peer.c : 5509 ] security: wal_peer_tid_flush_handler: peer_id:%d peer_flags:%02x authrized:%d +769,ii,[ ar_wal_peer.c : 11355 ] wal_peer_tid_free_mem: sw_peer_id=%d, tidno = %d +768,i,[ ar_wal_peer.c : 11400 ] delete_all_peer wal_peer_tid_free_mem: WLAN_THREAD_COMM_FUNC_VDEV_DEL_ALL_PEER peer_id:%d +767,II,[ ar_wal_peer.c : 14752 ] TRIGGER PDEV MISMATCH, thread:%x, tid:%x +766,III,[ ar_wal_peer.c : 15547 ] wal_peer_update_reg_pdg_notify_params sw_peer_id %x rate_code=%x preamble=%x +765,IIIIIII,[ ar_wal_peer.c : 5067 ] security:pdev(%x)peer %x,flag %x, unblocked for tidLen update,refcnt=%x,htc=%x,remap=%x,security=%x +764,iII,[ ar_wal_peer.c : 5611 ] security: wal_tqm_setkey_update_sync_cb_func: sw_peer_id:%d peer_flags:0x%x, qpeer_flags=0x%x +763,II,[ ar_wal_peer.c : 5636 ] security: wal_tqm_setkey_update_unblock_cb_func: peer:%p peer_flags:%02x +762,II,[ ar_wal_peer.c : 1027 ] alloc msduq for tid_num = %u, wal_msdu_qtype = %u +761,ii,[ ar_wal_peer.c : 689 ] HW overwritten tx_flow_number:%d and corressponding sw_peer_id:%d +760,iii,[ ar_wal_peer.c : 13102 ] wal_vdev_delete_all_peer_queue_dummy_frame_into_tcl: vdev = %d, sw_cookie = %d, buffer_id = %d + +759,iii,[ ar_wal_peer.c : 12974 ] wal_vdev_delete_all_peer_queue_dummy_frame_into_tqm: vdev = %d, sw_cookie = %d, buffer_id = %d + +859,I,[ wal_rc.c : 265 ] Phy rate=0, rix=%x +858,ii,[ wal_rc.c : 428 ] CHAINMASk_DBG orig_cm=%d pdev_cm=%d +857,Iiii,[ wal_rc.c : 439 ] CHAINMASk_DBG overwrite tx chainmask, peer%p, sw_peer_id:%d rate_Sched_chainmask %d tx_mask %d +856,i,[ wal_rc.c : 1668 ] [HT Sig]MCS value is not correct (%d) +855,i,[ wal_rc.c : 1750 ] MCS value is not correct (%d) +854,i,[ wal_rc.c : 1880 ] [he_sig_b2_ofdma]MCS value is not correct (%d) +853,i,[ wal_rc.c : 2002 ] [he_sig_a]MCS value is not correct (%d) +852,IIII,[ wal_rc.c : 2982 ] MU_EDCA_DEBUG: total_msdu: %lu, tcp_msdu: %lu, udp_msdu: %lu, other_msdu: %lu +860,iiiiiiiii,[ wal_rc_ul.c : 537 ] UL_TPC_DBG: AID: %d, bw: %d, ru_size: %d, mcs: %d, delta_p_mcs_100x: %d, delta_p_ru_100x: %d, rssi_ref_100x: %d, target_rssi_error_100x: %d => target_rssi_100x: %d +862,IiI,[ ar_wal_rtt.c : 95 ] Deliver RX Ind msg:%p s_thr:%d to RT at ticks:0x%x +861,i,[ ar_wal_rtt.c : 36 ] _wal_fac_handler: report type %d +879,IIIIII,[ ar_wal_rx.c : 2174 ] rxdma_error_code: %x, sw_peer_id =%x ,sw group_id %x, %x,%x, ts= %u +878,IIi,[ ar_wal_rx.c : 2430 ] ctrl_path_stats_dbg rx: mac_address equal mac_0 = 0x%x mac_2 =0x%x subtype = %d + +877,IIII,[ ar_wal_rx.c : 2348 ] rx msg 0x%p, head:0x%p, 0x%p, %x buffers +876,IIII,[ ar_wal_rx.c : 1791 ] rx pop ppdu %x, sw_frame_group_id %x, err code %x, peer %p +875,iII,[ ar_wal_rx.c : 3633 ] RX PhyErr:dev=%d,err=%x,rx_err_cnt=%x +874,iiiiii,[ ar_wal_rx.c : 3724 ] RX PPDU dev: %d peer_id: %d ts: %d mcs: %d nss: %d,dur: %d + +873,iiiiiII,[ ar_wal_rx.c : 3734 ] RX PPDU dev: %d peer_id: %d seq_no: %d mpdu_ok: %d mpdu_fail: %d fcs_err_bmap_L32 0x: %x fcs_err_bmap_U32 0x: %x + +872,iiII,[ ar_wal_rx.c : 6128 ] rx resume on pdev :%d, module:%d, flag:%x, caller:0x%x +871,IiI,[ ar_wal_rx.c : 620 ] pdev %x, rx reap error sq %d, buffer 0x%x +870,IiI,[ ar_wal_rx.c : 785 ] pdev %x, rx reap normal sq %d, buffer[%x] +869,iiiII,[ ar_wal_rx.c : 6037 ] rx_suspend on pdev:%d, module:%d, status:%d, flags %x, caller: %x +868,i,[ ar_wal_rx.c : 1334 ] wal_rx_delete_all_peer_hdlr vdev_id = %d +867,IIIIIII,[ ar_wal_rx.c : 6369 ] wal_rx_restore_ring_from_offload: [%x] [%x] [%x] [%x] [%x] [%x] [%x] + +866,II,[ ar_wal_rx.c : 6388 ] wal_rx_setup_ring_for_offload: [%x] [%x] + +865,III,[ ar_wal_rx.c : 6719 ] %s: filter0 (0x%x) filter1 (0x%x) + +864,IIIIII,[ ar_wal_rx.c : 6257 ] WAL_DBGID_RX_BA_SETUP 0x%x 0x%x 0x%x 0x%x 0x%x MAC:%x +863,iiIIII,[ ar_wal_rx.c : 5475 ] rx_suspend_resume_msg on pdev:%d, data_value:%d, status ring flag %x, head %x, tail %x, ms:%x +895,IiI,[ ar_wal_rx_recovery.c : 326 ] pdev %x, rx empty recovery sq %d, buffer[%x] +894,IiI,[ ar_wal_rx_recovery.c : 356 ] pdev %x, rx reap recovery sq %d, buffer[%x] +893,iii,[ ar_wal_rx_recovery.c : 872 ] RX phy error count: CNT_1:%d CNT_2:%d CNT_3:%d +892,iII,[ ar_wal_rx_recovery.c : 1072 ] UL OFDMA usr index: %d, Qos Control value: 0x%x, Qos Control count: 0x%x + +891,ii,[ ar_wal_rx_recovery.c : 1277 ] pkt_route: %d type_bmap: %d +890,iIIII,[ ar_wal_rx_recovery.c : 1353 ] RX ppdu sfm no resource drop count is valid? %d :%x,%x mpdu drop count:%x,%x +889,IIi,[ ar_wal_rx_recovery.c : 1452 ] SFM_PENDING_RXPCU DETECTION_TYPE: 0x%x RECOVERY_TYPE = 0x%x NUM_RESETS : %d +888,I,[ ar_wal_rx_recovery.c : 1523 ] RX set crash mask 0x%x +887,,[ ar_wal_rx_recovery.c : 1527 ] clear crash mask +886,I,[ ar_wal_rx_recovery.c : 1539 ] g_dbg_local_buf_debug_enable %x +885,iiI,[ ar_wal_rx_recovery.c : 1599 ] mu edca timer stop thru frame handler: pdev_id=%d, peer_id=%d, ac_bitmap = %08x +884,iII,[ ar_wal_rx_recovery.c : 1045 ] UL OFDMA usr index: %d, HE Control value: 0x%x, HE Control count: 0x%x + +883,IIII,[ ar_wal_rx_recovery.c : 576 ] SFM_PENDING_RXPCU (SFM_REG) detected dev_id:0x%x,rxpcu_sfm_num_dwords=0x%x,MCMN_R0_MCMN_MAC_IDLE=0x%x,detection_type= 0x%x +882,i,[ ar_wal_rx_recovery.c : 521 ] restart remote timers for pdev:%d +881,ii,[ ar_wal_rx_recovery.c : 491 ] wal_rx_rings_reset pdev:%d, cnt:%d +880,,[ ar_wal_rx_recovery.c : 550 ] SFM_PENDING_RXPCU ignored.. +903,i,[ ar_wal_rx_refill.c : 113 ] Skip host ring TP updating for inactive pdev %d +902,i,[ ar_wal_rx_refill.c : 203 ] Skip monitor ring HP updating for inactive pdev %d +901,i,[ ar_wal_rx_refill.c : 334 ] Skip refill ring HP updating on pdev %d +900,ii,[ ar_wal_rx_refill.c : 2121 ] pdev %d CE pending in refill ring %d +899,ii,[ ar_wal_rx_refill.c : 2130 ] pdev %d CE pending in dest ring %d +898,ii,[ ar_wal_rx_refill.c : 2138 ] pdev %d CE pending in dest ring %d +897,ii,[ ar_wal_rx_refill.c : 2147 ] pdev %d CE pending in src ring %d +896,,[ ar_wal_rx_refill.c : 1544 ] Buffer leaked! +926,I,[ ar_wal_rx_uplink.c : 1529 ] ul_dbg_fake_qdepth_timer_handler: pdev=0x%x +925,Ii,[ ar_wal_rx_uplink.c : 1567 ] ul_dbg_fake_qdepth_updated: peer=0x%x, ac=%d +924,iii,[ ar_wal_rx_uplink.c : 1917 ] FDRSSI: rx done %d, ipc done %d, flush out %d. + +923,iiiiiiii,[ ar_wal_rx_uplink.c : 1725 ] UL_ACTIVITY_DBG: TRIG_TYPE=%d, NUM_USER=%d, RX_DONE=%d, TX_DONE=%d, RX_FLUSH_TIMEOUT=%d CMD_RESULT=%d TSF=%d TSTAMP_MS=%d +922,iiiiiiiii,[ ar_wal_rx_uplink.c : 1785 ] UL_ACTIVITY_DBG_USR: PEER_ID=%d, USER_INDEX=%d, BASIC_FAIL=%d, BASIC_SUCCESS=%d, QDEPTH_RESET=%d, BASIC_TRIG=%d, BSR_TRIG=%d, RX_DONE=%d, UL_MPDU_OK=%d +921,,[ ar_wal_rx_uplink.c : 881 ] smart_basic_trig : Reset parameters due to consecutive QOS NULLs +920,iIii,[ ar_wal_rx_uplink.c : 961 ] smart_basic_trig : qos_ctrl_info sample_count=%d, average_ul_qdepth_bytes=%u, qdepth_curr=%d, is_11ax_pkt=%d +919,Iiiiiiii,[ ar_wal_rx_uplink.c : 969 ] smart_basic_trig : qos_ctrl_info buffer_depletion_time=%lu, buffer_filling_interval=%d, buffer_filling_interval_bytes=%d, received_bytes=%d, bsr_trig=%d, ignore_received_bytes=%d, ac=%d, aid=%d + +918,iiIIIIII,[ ar_wal_rx_uplink.c : 994 ] ul_dbg_update_peer_ul_data QOS_BITMAP: peer_aid=%d, tid_num=%d, ul_tid_state=0x%x, tid_bitmap=0x%x, eosp_bitmap=0x%x, qsize=%u, qos_ctrl_15_8=%u, ul_trig_info=0x%x +917,IIIIII,[ ar_wal_rx_uplink.c : 1006 ] ul_dbg_update_peer_ul_data_for_bsr: time_delta=%u,qdepth_prev=%u, qdepth_curr=%u, time_now_ms=%u, bsr_timeout_ms=%u, last_non_zero_update_ts=%u +916,iiIIIII,[ ar_wal_rx_uplink.c : 1018 ] ULMU_QUEUE_TRACK: peer_aid=%d ,peer_aid=%d, rx_mpdu_ok: %lu, rx_mpdu_fail: %lu, rx_mpdu_bytes_count: %lu, tcp_ack_msdu_cnt=%lu, ppdu_dur_us=%u +915,iIIIIII,[ ar_wal_rx_uplink.c : 1027 ] ul_dbg_efficiency: peer_aid=%d,rx_mpdu_ok: %lu, rx_mpdu_fail: %lu, rx_mpdu_bytes_count: %lu, extra_delim_bytes: %lu, tcp_ack_msdu_cnt=%lu, ppdu_dur_us=%u +914,iIIIII,[ ar_wal_rx_uplink.c : 1055 ] UL_MAX_PPDU_SIZE_DBG_1: aid: %d,average_mpdu_len: %lu, rx_mpdu_count: %lu, rx_mpdu_bytes_count: %lu, rx_null_delim_bytes: %lu, sum_qdepth_bytes: %lu +913,iII,[ ar_wal_rx_uplink.c : 1094 ] UL_MAX_PPDU_SIZE_DBG_2: aid: %d, rx_mpdu_bytes_count: %lu, ul_ofdma_estimated_max_ppdu_bytes: %lu +912,III,[ ar_wal_rx_uplink.c : 2242 ] FDRSSI Skip: CRC check failed - SCHEDULE ID : %x CRC from uCode : %x, num_ul_user = %u + +911,iiiiiiiii,[ ar_wal_rx_uplink.c : 2321 ] FDRSSI: sw_peer_id: %d, ul_mu_type %d, user %d, nss %d, ru_size %d, ru_idx %d, min_total_gain %d, Raw %d, Final %d. +910,iiiiiiiii,[ ar_wal_rx_uplink.c : 2183 ] UL_MUMIMO_DBG, EVM, mu_type %d, user %d, stream %d, pilot %d, raw_evm %d, sig_pwr_db4 %d, evm_pwr_db4 %d, pilot_evm_dB %d, mean_pilot_evm %d +909,IIII,[ ar_wal_rx_uplink.c : 384 ] ul_dbg_update_peer_queue_stats_from_HT_CTRL: aci_bitmap=0x%x, aci_high=0x%x, qsize_all=%u, qsize_high=%u +908,iIIIIII,[ ar_wal_rx_uplink.c : 537 ] ul_dbg_update_peer_queue_stats_from_HT_CTRL ac=%d, time_delta=%u, qdepth_prev=%u, qdepth_curr=%u, time_now_ms=%u, bsr timeout=%u, last_non_zero_qdepth_ts=%u +907,iIi,[ ar_wal_rx_uplink.c : 457 ] UL_MUMIMO_DBG: update from_htctrl. aid %d, queue size %u, ptid_tidno=%d reset UL implicit +906,Iiiiiiii,[ ar_wal_rx_uplink.c : 497 ] smart_basic_trig : stats_from_htctrl_field buffer_depletion_time=%lu, buffer_filling_interval=%d, buffer_filling_interval_bytes=%d, sample_count=%d, smart_basic_trigger=%d, qdepth_curr=%d, ac=%d, aid=%d + +905,IIiI,[ ar_wal_rx_uplink.c : 1273 ] ul_dbg_update_peer_ul_data: peer=0x%x, ul_rate_info=0x%x, bsr_recvd=%d, bsr_trig=%u +904,IIIIIIII,[ ar_wal_rx_uplink.c : 1282 ] ul_dbg_update_peer_ul_data: fc_valid:%x, fc_field:0x%x, ht_ctrl_valid=%x, ht_control_field=0x%x,ht_ctrl_null_valid=%x, ht_control_null_field=0x%x,qos_data_tid_bitmap=0x%x, qos_data_tid_eosp_bitmap=0x%x +929,III,[ ar_wal_rx_offload.c : 220 ] rx local notify: 0x%p, flags: 0x%x, ts: %u +928,IIII,[ ar_wal_rx_offload.c : 319 ] %s: empty len: 0x%x, addr:0x%x:0x%x +927,IIII,[ ar_wal_rx_offload.c : 381 ] %s: offload len: 0x%x, addr:0x%x:0x%x +948,,[ wal_htt_ppdu_stats.c : 562 ] Dropped ppdu stats due to ring full +947,,[ wal_htt_ppdu_stats.c : 1093 ] Dropped ppdu stats due to full QHEAP +946,,[ wal_htt_ppdu_stats.c : 1809 ] Dropped ppdu stats due to full QHEAP +945,,[ wal_htt_ppdu_stats.c : 1939 ] Dropped ppdu stats due to full QHEAP +944,,[ wal_htt_ppdu_stats.c : 2209 ] Dropped flush stats due to ring full +943,,[ wal_htt_ppdu_stats.c : 2220 ] Dropped flush stats due to full QHEAP +942,,[ wal_htt_ppdu_stats.c : 2007 ] Dropped mgmt ppdu tlv due to ring full +941,,[ wal_htt_ppdu_stats.c : 2064 ] Dropped ppdu stats due to full QHEAP +940,,[ wal_htt_ppdu_stats.c : 676 ] Dropped ppdu stats due to full QHEAP +939,,[ wal_htt_ppdu_stats.c : 1274 ] Dropped ppdu stats due to full QHEAP +938,,[ wal_htt_ppdu_stats.c : 836 ] Dropped ppdu stats due to full QHEAP +937,,[ wal_htt_ppdu_stats.c : 966 ] Dropped ppdu stats due to full QHEAP +936,,[ wal_htt_ppdu_stats.c : 906 ] Dropped ppdu stats due to full QHEAP +935,,[ wal_htt_ppdu_stats.c : 1492 ] Dropped ppdu stats due to full QHEAP +934,,[ wal_htt_ppdu_stats.c : 1391 ] Dropped tqm ppdu stats due to ring full +933,,[ wal_htt_ppdu_stats.c : 1405 ] Dropped tqm ppdu stats due to full QHEAP +932,,[ wal_htt_ppdu_stats.c : 1660 ] Dropped tac ppdu stats due to full QHEAP +931,,[ wal_htt_ppdu_stats.c : 2161 ] Dropped ppdu stats due to full QHEAP +930,i,[ wal_htt_ppdu_stats.c : 2110 ] Dropped self gen ppdu tlv due to ring full ring_id:%d +949,iiii,[ ar_wal_thermal.c : 465 ] pdev_id(%d),tx_chainmask(%d), rx_chainmask(%d), num_chains(%d) +969,IIII,[ ar_wal_tqm.c : 688 ] peer_id=0x%x, _set_flow_to_be_cleanup:%x, tx_flow_number:%x,caller:%x +968,ii,[ ar_wal_tqm.c : 880 ] qos: %d and peer_id is %d tickle tid +967,I,[ ar_wal_tqm.c : 918 ] wal_tqm_process_flow_not_empty_status new flow:%x +966,iii,[ ar_wal_tqm.c : 8232 ] soft_msduq_delete: Requesting soft msduq delete peer_id:%d tid_num:%d, qtype:%d +965,i,[ ar_wal_tqm.c : 420 ] wal_tqm_flow_empty_helper not_init, counter:%d +964,II,[ ar_wal_tqm.c : 331 ] wal_tqm_flow_update_helper not_init, fw_initialized:%x, counter:%x +963,,[ ar_wal_tqm.c : 5024 ] TCL rings unpaused +962,i,[ ar_wal_tqm.c : 5030 ] Fired timer again TQM link descriptor counter:%d +961,ii,[ ar_wal_tqm.c : 8290 ] wal_tqm_peer_qos_update_helper() sw_peer_id:%d qos:%d +960,iiii,[ ar_wal_tqm.c : 3339 ] Fired timer and paused TCL rings ring link descriptor counters mac0:%d mac1:%d mac2:%d sum:%d +959,IIII,[ ar_wal_tqm.c : 2873 ] peer_id= 0x%x, wal_tqm_process_flush_cache_status:%x,%x,%x +958,,[ ar_wal_tqm.c : 1244 ] wal_tqm_process_gen_mpdus_status: Null ptid +957,IIIIII,[ ar_wal_tqm.c : 2197 ] DROP flowq peer_id:%u tid:%u qtype:%u drops %u deque %u enque %u +956,III,[ ar_wal_tqm.c : 2231 ] qstats_status peer_id:%u tid_num:%u qtype:%u +955,IIII,[ ar_wal_tqm.c : 1707 ] DROP wal_tqm_process_remove_mpdu_status peer_id:%u tid:%u msdu_removed: %u mpdu_removed: %u +954,IIII,[ ar_wal_tqm.c : 1807 ] peer_id= 0x%x, wal_tqm_process_remove_msdu_status:%x,%x,%x +953,III,[ ar_wal_tqm.c : 1909 ] DROP wal_tqm_process_remove_msdu_status peer_id:%u tid:%u msdu_removed: %u +952,ii,[ ar_wal_tqm.c : 496 ] _wal_tqm_process_update_tx_msdu_flow_status tx_flow_number:%d update_requirements_not_met:%d +951,iii,[ ar_wal_tqm.c : 2410 ] soft_msduq_delete: msduq got deleted sw_peer_id:%d, tid_num=%d, qtype:%d +950,iii,[ ar_wal_tqm.c : 2414 ] soft_msduq_delete: delete req dropped sw_peer_id:%d, tid_num=%d, qtype:%d +974,IIIIII,[ ar_tx_q_enque.c : 455 ] tx_q_enque_tqm_bypass: tid_num=0x%x, pdev_id=0x%0x, tid_paused=0x%x, type=0x%0x, len=0x%0x, num_mpdus_in_fq=0x%0x +973,IIIIIIII,[ ar_tx_q_enque.c : 736 ] pn_alloc:fc=%x,comp_type=%x,flen=%lx,msdu_flags=%lx,id=%x,buffer_id=%x,enque_id=%x,pending_local=%x +972,II,[ ar_tx_q_enque.c : 1151 ] WAL_DBGID_TX_DISCARD id: %x, flag:%lx + +971,IIIIIII,[ ar_tx_q_enque.c : 821 ] pn_alloc_complete:fc=%x,flen=%lx,msdu_flags=%lx,tid_num=%x,enque_id=%x,pn_idx=%x,pn=%llx +970,IIIIII,[ ar_tx_q_enque.c : 864 ] pn_alloc failed: id:%x,flags:%x,tid_no:%x,fc:%x,enqeu_id=%x,pending_local=%x +1134,IIIIIII,[ ar_wal_tx_dbg.c : 914 ] txbf_su_ppdu_stats (legacy su = %lu)(ol ac su = %lu)(txbf ac su = %lu)(txbf ac = %lu)(ol ax su = %lu)(txbf ax su = %lu)(txbf ax = %lu) +1133,III,[ ar_wal_tx_dbg.c : 1843 ] TXDEWDOG TQM1:%u dummy_queued:%u last_time:%u +1132,,[ ar_wal_tx_dbg.c : 2141 ] No ul_resp_vdev or BSS-peer assigned !! +1131,I,[ ar_wal_tx_dbg.c : 2146 ] invalid ACTRL:%x +1130,iii,[ ar_wal_tx_dbg.c : 2224 ] fudge_txtime=%d, legacy_burst=%d, vht_burst=%d +1129,iii,[ ar_wal_tx_dbg.c : 2230 ] short_pkt_min_msdu_size=%d, legacy_burst_per=%d, vht_burst_per=%d +1128,III,[ ar_wal_tx_dbg.c : 963 ] txbf_su_mpdu_stats AX OL(ol ax su tried = %lu)(ol ax su failed = %lu)(ol ax su retried = %lu) +1127,iii,[ ar_wal_tx_dbg.c : 2290 ] mu_mimo_ppdu_dur_hist_200us_bin_%d (Nr_%d) : %d +1126,iiiiiiiii,[ ar_wal_tx_dbg.c : 2306 ] mu_mimo_total_txop_ms_hist_MU%d_bin_%d - %d (Nr_%d) : %d, %d, %d, %d, %d +1125,iiii,[ ar_wal_tx_dbg.c : 2315 ] mu_mimo_mpdus_failed_hist_%d - %d (Nr_%d) : %d +1124,iiii,[ ar_wal_tx_dbg.c : 2320 ] mu_mimo_mpdus_failed_hist_%d - %d (Nr_%d) : %d +1123,iii,[ ar_wal_tx_dbg.c : 2329 ] mu_mimo_mpdus_tried_hist_%d (Nr_%d) : %d +1122,iiii,[ ar_wal_tx_dbg.c : 2334 ] mu_mimo_mpdus_tried_hist_%d - %d (Nr_%d) : %d +1121,iiii,[ ar_wal_tx_dbg.c : 2339 ] mu_mimo_mpdus_tried_hist_%d - %d (Nr_%d) : %d +1120,II,[ ar_wal_tx_dbg.c : 2367 ] TXDEWDOG prev_timeout:%u current_timeout:%u +1119,II,[ ar_wal_tx_dbg.c : 2463 ] read addr: 0x%x, value = 0x%x +1118,IIIII,[ ar_wal_tx_dbg.c : 2590 ] ax_mu_mimo_ndpa_sch_status : WHAL_TXERR_NONE = %lu,WHAL_TXERR_RESP = %lu,WHAL_TXERR_FILT = %lu,WHAL_TXERR_FIFO = %lu,WHAL_TXERR_SWABORT = %lu + +1117,IIIIII,[ ar_wal_tx_dbg.c : 980 ] txbf_su_mpdu_stats AX (txbf sifs ax su tried = %lu)(txbf sifs ax su failed = %lu)(txbf sifs ax su retried = %lu)(txbf rbo ax su tried = %lu)(txbf rbo ax su failed = %lu)(txbf rbo ax su retried = %lu) +1116,IIIII,[ ar_wal_tx_dbg.c : 2604 ] ax_mu_mimo_ndp_sch_status : WHAL_TXERR_NONE = %lu,WHAL_TXERR_RESP = %lu,WHAL_TXERR_FILT = %lu,WHAL_TXERR_FIFO = %lu,WHAL_TXERR_SWABORT = %lu + +1115,IIIII,[ ar_wal_tx_dbg.c : 2620 ] ax_mu_brp_sch_status : WHAL_TXERR_NONE = %lu,WHAL_TXERR_RESP = %lu,WHAL_TXERR_FILT = %lu,WHAL_TXERR_FIFO = %lu,WHAL_TXERR_SWABORT = %lu + +1114,I,[ ar_wal_tx_dbg.c : 2625 ] ax_mu_brp_trigger_hw_paused = %lu + +1113,IIIIIII,[ ar_wal_tx_dbg.c : 2645 ] ax_mu_mimo_ndp_sch_flag_err : WHAL_SCH_TSFLAG_FLUSH_RCVD_ERR = %lu,WHAL_SCH_TSFLAG_FILT_SCHED_CMD_ERR = %lu,WHAL_SCH_TSFLAG_RESP_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR = %lu,WHAL_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR = %lu + +1112,IIIIIII,[ ar_wal_tx_dbg.c : 2665 ] ax_mu_mimo_brp_sch_flag_err : WHAL_SCH_TSFLAG_FLUSH_RCVD_ERR = %lu,WHAL_SCH_TSFLAG_FILT_SCHED_CMD_ERR = %lu,WHAL_SCH_TSFLAG_RESP_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR = %lu,WHAL_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR = %lu,WHAL_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR = %lu + +1111,IIIII,[ ar_wal_tx_dbg.c : 2681 ] ax_mu_mimo_ndpa_user_status : WHAL_TXERR_NONE = %lu,WHAL_TXERR_RESP = %lu,WHAL_TXERR_FILT = %lu,WHAL_TXERR_FIFO = %lu,WHAL_TXERR_SWABORT = %lu + +1110,IIIII,[ ar_wal_tx_dbg.c : 2695 ] ax_mu_mimo_ndp_user_status : WHAL_TXERR_NONE = %lu,WHAL_TXERR_RESP = %lu,WHAL_TXERR_FILT = %lu,WHAL_TXERR_FIFO = %lu,WHAL_TXERR_SWABORT = %lu + +1109,IIIII,[ ar_wal_tx_dbg.c : 2709 ] ax_mu_mimo_ndp_user_flag_err : WHAL_USER_TSFLAG_RESP_MISMATCH_ERR = %lu,WHAL_USER_TSFLAG_RESP_MIMO_CTRL_MISMATCH_ERR = %lu,WHAL_USER_TSFLAG_RESP_CRC_FAIL_ERR = %lu,WHAL_USER_TSFLAG_RESP_TIMEOUT_ERR = %lu,WHAL_USER_TSFLAG_RESP_PROT_TIMEOUT_ERR = %lu + +1108,IIIII,[ ar_wal_tx_dbg.c : 2725 ] ax_mu_brp_user_flag_err : WHAL_USER_TSFLAG_RESP_MISMATCH_ERR = %lu,WHAL_USER_TSFLAG_RESP_MIMO_CTRL_MISMATCH_ERR = %lu,WHAL_USER_TSFLAG_RESP_CRC_FAIL_ERR = %lu,WHAL_USER_TSFLAG_RESP_TIMEOUT_ERR = %lu,WHAL_USER_TSFLAG_RESP_PROT_TIMEOUT_ERR = %lu + +1107,,[ ar_wal_tx_dbg.c : 2878 ] DEBUG_CACHE::Invalid Reg Operation + +1106,III,[ ar_wal_tx_dbg.c : 991 ] txbf_snd_stats(txbf_ac_snd = %lu)(txbf_ax_snd = %lu)rx_txbf_stats (rx_txbf = %lu) +1105,Ii,[ ar_wal_tx_dbg.c : 3087 ] sifs burst enable: 0x%x, pdev=%d + +1104,i,[ ar_wal_tx_dbg.c : 3112 ] # of MU-RTS : %d + +1103,IIIIII,[ ar_wal_tx_dbg.c : 3211 ] flush_38_hist: %02d %02d %02d %02d %02d %02d +1102,i,[ ar_wal_tx_dbg.c : 3282 ] WAL_PPDU: MU PPDU VAL:%d +1101,i,[ ar_wal_tx_dbg.c : 3324 ] g_ack_all_6Mbps : %d + +1100,IIIII,[ ar_wal_tx_dbg.c : 3379 ] PHYDBG: g_dbg_phydbg_default_events: 0x%08x, g_dbg_phydbg_pmi_events: 0x%08x, g_dbg_phydbg_mpi_events: 0x%08x, g_dbg_phydbg_rxtd_events: 0x%08x, g_dbg_phydbg_robe_events: 0x%08x +1099,IIIII,[ ar_wal_tx_dbg.c : 3545 ] twt_dbg_leak_hist_dl: Bins0-4: %u, %u, %u, %u, %u +1098,IIIII,[ ar_wal_tx_dbg.c : 3550 ] twt_dbg_leak_hist_dl: Bins5-9: %u, %u, %u, %u, %u +1097,IIIII,[ ar_wal_tx_dbg.c : 3556 ] twt_dbg_leak_hist_ul: Bins0-4: %u, %u, %u, %u, %u +1096,IIIII,[ ar_wal_tx_dbg.c : 3562 ] twt_dbg_leak_hist_ul: Bins0-4: %u, %u, %u, %u, %u +1095,iii,[ ar_wal_tx_dbg.c : 1003 ] %dms Burst: avg_txop_burst(ms) = %d,txop_on_burst_complete(ms) = %d + +1094,i,[ ar_wal_tx_dbg.c : 3996 ] SelfGenResp: Dev id %d is in power saving state, not able to print. +1093,ii,[ ar_wal_tx_dbg.c : 4056 ] LOCAL: msduq_pool_ctxt total_alloc_cnt:%d cur_alloc_cnt:%d +1092,ii,[ ar_wal_tx_dbg.c : 4060 ] REMOTE: msduq_pool_ctxt total_alloc_cnt:%d cur_alloc_cnt:%d +1091,ii,[ ar_wal_tx_dbg.c : 4065 ] LOCAL: tid_swap_pool_ctxt total_alloc_cnt:%d cur_alloc_cnt:%d +1090,ii,[ ar_wal_tx_dbg.c : 4068 ] REMOTE: tid_swap_pool_ctxt total_alloc_cnt:%d cur_alloc_cnt:%d +1089,ii,[ ar_wal_tx_dbg.c : 4073 ] LOCAL: tid_state_pool total_alloc_cnt:%d cur_alloc_cnt:%d +1088,ii,[ ar_wal_tx_dbg.c : 4076 ] REMOTE: tid_state_pool total_alloc_cnt:%d cur_alloc_cnt:%d +1087,ii,[ ar_wal_tx_dbg.c : 4080 ] LOCAL: ul_tid_state_pool total_alloc_cnt:%d cur_alloc_cnt:%d +1086,ii,[ ar_wal_tx_dbg.c : 4083 ] REMOTE: ul_tid_state_pool total_alloc_cnt:%d cur_alloc_cnt:%d +1085,ii,[ ar_wal_tx_dbg.c : 4290 ] Profile Enabled : %d hist_intvl : %d +1084,iiiiiiii,[ ar_wal_tx_dbg.c : 1245 ] sched_cmd_result[0] to sched_cmd_result[6] for HWQ id %d = {%d,%d,%d,%d,%d,%d,%d} + +1083,iiii,[ ar_wal_tx_dbg.c : 4318 ] Profile ID : %d Count: %d Min : %d Max : %d +1082,iiiii,[ ar_wal_tx_dbg.c : 4330 ] Profile ID : %d hist_intvl: %d hist[0] : %d hist[1] : %d hist[2] : %d +1081,,[ ar_wal_tx_dbg.c : 4473 ] ctrl_path_stats_dbg : Disabling peer_dbg logs + +1080,,[ ar_wal_tx_dbg.c : 4480 ] ctrl_path_stats_dbg : Error seen + Usage +ctrl_path_stats_dbg: To Enable Stats: wifitool athX setUnitTestCmd 0x48 8 244 1 +ctrl_path_stats_dbg: To Disable Stats: wifitool athX setUnitTestCmd 0x48 2 244 0 + +1079,IIIIII,[ ar_wal_tx_dbg.c : 4503 ] ctrl_path_stats_dbg : args[2] = 0x%x args[3] = 0x%x args[4] = 0x%x args[5] = 0x%x args[6] = 0x%x args[7] = 0x%x + +1078,II,[ ar_wal_tx_dbg.c : 4506 ] ctrl_path_stats_dbg : mac_addr_31_0 = 0x%x mac_addr_47_32 = 0x%x + +1077,,[ ar_wal_tx_dbg.c : 4508 ] ctrl_path_stats_dbg: SW Peer ID Check + +1076,i,[ ar_wal_tx_dbg.c : 4511 ] ctrl_path_stats_dbg: vdev %d + +1075,,[ ar_wal_tx_dbg.c : 4519 ] ctrl_path_stats_dbg: bss +1074,,[ ar_wal_tx_dbg.c : 4521 ] ctrl_path_stats_dbg: self +1073,iiiiiii,[ ar_wal_tx_dbg.c : 1255 ] sched_cmd_result[7] to sched_cmd_result[12] for HWQ id %d = {%d,%d,%d,%d,%d, %d} + +1072,iII,[ ar_wal_tx_dbg.c : 4524 ] ctrl_path_stats_dbg: peer %d, mac %x %x + +1071,iII,[ ar_wal_tx_dbg.c : 4526 ] ctrl_path_stats_dbg: sw_peer_id found peer %d, mac %x %x + +1070,,[ ar_wal_tx_dbg.c : 4561 ] s_stats!ERROR!:use:wifitool athX setUnitTestCmd 0x48 2 260 0/1 + +1069,II,[ ar_wal_tx_dbg.c : 4619 ] s_stats: dbg_num_bufs: %u, dbg_num_evt: %u + +1068,III,[ ar_wal_tx_dbg.c : 4620 ] s_stats: HOST_ring_HI : %u, TI : %u, S_TI : %u +1067,IIII,[ ar_wal_tx_dbg.c : 4621 ] s_stats: IN/SHADOW_ring_HI : %u, TI : %u, S_TI : %u, S_HI : %u +1066,IIII,[ ar_wal_tx_dbg.c : 4622 ] s_stats: OUT_ring_HI : %u TI : %u, S_TI : %u, S_HI : %u +1065,IIIII,[ ar_wal_tx_dbg.c : 4625 ] s_stats: IPC_ring_%u : HI : %u TI : %u, S_TI : %u, S_HI : %u +1064,,[ ar_wal_tx_dbg.c : 4627 ] s_stats: VREG_DET0 : + +1063,III,[ ar_wal_tx_dbg.c : 4628 ] s_stats: ScanPri : %u, SCount : %u, SPrd : %u + +1062,i,[ ar_wal_tx_dbg.c : 1303 ] TX_IST_TRIGGER SENT %d + +1061,III,[ ar_wal_tx_dbg.c : 4629 ] s_stats: ChnMask : %u, SEna : %u, SUpdtMask : 0x%x + +1060,IIII,[ ar_wal_tx_dbg.c : 4630 ] s_stats: SRdyIntrpt : %u, SPfmd : %u, IntrptsSent : %u, Scanpending : %u + + +1059,,[ ar_wal_tx_dbg.c : 4632 ] s_stats: VREG_DET1: + +1058,III,[ ar_wal_tx_dbg.c : 4633 ] s_stats: ScanPri : %u, SCount : %u, SPrd : %u + +1057,III,[ ar_wal_tx_dbg.c : 4634 ] s_stats: ChnMask : %u, SEna : %u, SUpdtMask : 0x%x + +1056,IIII,[ ar_wal_tx_dbg.c : 4635 ] s_stats: SRdyIntrpt : %u, SPfmd : %u, IntrptsSent : %u , Scanpending : %u + +1055,,[ ar_wal_tx_dbg.c : 4638 ] s_stats: VREG_DET_AGILE : + +1054,III,[ ar_wal_tx_dbg.c : 4639 ] s_stats: ScanPri : %u, SCount : %u, SPrd : %u + +1053,III,[ ar_wal_tx_dbg.c : 4640 ] s_stats: ChnMask : %u, SEna : %u, SUpdtMask : 0x%x + +1052,IIII,[ ar_wal_tx_dbg.c : 4641 ] s_stats: SRdyIntrpt : %u, SPfmd : %u, IntrptsSent : %u, Scanpending : %u + +1051,IIIIII,[ ar_wal_tx_dbg.c : 935 ] txbf_su_mpdu_stats (legacy su tried = %lu)(legacy su failed = %lu)(legacy su retried = %lu) ------------------------txbf_su_mpdu_stats AC OL(ol ac su tried = %lu)(ol ac su failed = %lu)(ol ac su retried = %lu) +1050,,[ ar_wal_tx_dbg.c : 1347 ] pdev_id can't be > 2, usage: wifitool ath0 setUnitTestCmd 0x48 2 56 +1049,,[ ar_wal_tx_dbg.c : 4894 ] s_stats!ERROR!:use:wifitool athX setUnitTestCmd 0x48 2 283 + +1048,I,[ ar_wal_tx_dbg.c : 4913 ] Exception stats min time %x +1047,I,[ ar_wal_tx_dbg.c : 4914 ] Exception stats max time %x +1046,iI,[ ar_wal_tx_dbg.c : 4916 ] Exception stats service_time_below%d_count %x +1045,iiI,[ ar_wal_tx_dbg.c : 4917 ] Exception stats service_time_above%d_below%d_count %x +1044,iI,[ ar_wal_tx_dbg.c : 4918 ] Exception stats service_time_above%d_count %x +1043,iii,[ ar_wal_tx_dbg.c : 4990 ] VOW_TTL dbg_tid_ttl_start_time %d dbg_tid_ttl_last_time %d dbg_tid_ttl_count %d +1042,iiii,[ ar_wal_tx_dbg.c : 5047 ] delimiter user track: Number of total MU PPDU %d, MU PPDUs with delimiter users: %d, Percent:%d Average MU number of delimiter users %d +1041,i,[ ar_wal_tx_dbg.c : 5423 ] Num of sched commands dropped due to session ID mismatch - %d +1040,i,[ ar_wal_tx_dbg.c : 5424 ] Num of sched commands during TX abort - %d +1039,iiiiiiii,[ ar_wal_tx_dbg.c : 1367 ] WHAL_STATS for pdev id = %d: last_unpause_ppdu_id = %d hwsch_unpause_wait_tqm_write = %d hwsch_dummy_tlv_skipped = %d hwsch_misaligned_offset_received = %d hwsch_reset_count = %d hwsch_dev_reset_war = %d hwsch_delayed_pause = %d +1038,ii,[ ar_wal_tx_dbg.c : 5426 ] Num of seq start during resume: ISR - %d, DSR - %d +1037,,[ ar_wal_tx_dbg.c : 5439 ] TX abort/resume in progress. Ignoring request! +1036,iiii,[ ar_wal_tx_dbg.c : 5458 ] SFM_FLUSH_ISSUE sfm_wdg_with_flush_issue = %d, sfm_wdg_without_flush_issue = %d sfm_fatal_unknown = %d, num of times sfm issue got hit = %d +1035,ii,[ ar_wal_tx_dbg.c : 5493 ] NOC_PENDING_TRANSACTIONS lmac_noc_transaction_pending_cnt %d lmac_noc_trans_recurring_reset %d +1034,iiiii,[ ar_wal_tx_dbg.c : 5601 ] CONG_CTRL Multicast_DBG buf_id:%d hcm_bin_idx:%d cur:%d, min:%d, max:%d +1033,iI,[ ar_wal_tx_dbg.c : 5667 ] mu edca timer stop: pdev_id = %d, ac_bitmap = %08x +1032,i,[ ar_wal_tx_dbg.c : 5676 ] Sending Delayed TX DELBA msg on vdev %d +1031,i,[ ar_wal_tx_dbg.c : 5726 ] IPA wbm2sw2 ring monitor configure: logging hp/tp in every %d sec +1030,iiiii,[ ar_wal_tx_dbg.c : 5802 ] tqm_sync_pipeling_stats: tqm_sync_sent = %d, tqm_sync_proc = %d, TAC/IST post = %d, tqm_sync_not_proc = %d, tqm_ist post = %d +1029,i,[ ar_wal_tx_dbg.c : 5824 ] MAC clock gating: %d +1028,iiiiiiii,[ ar_wal_tx_dbg.c : 1387 ] hwsch_long_delayed_pause = %d sch_rx_ppdu_no_response = %d sch_selfgen_response = %d sch_rx_sifs_resp_trigger = %d sch_mpdu_info_bitmap_missed = %d hwsch_qcdd03911334 = %d hwsch_qcdd04031456 = %d hwsch_qcdd03955078 = %d +1027,IIIIII,[ ar_wal_tx_dbg.c : 5879 ] PM_STATE_DBG: for %2x:%2x:%2x:%2x:%2x:%2x +1026,,[ ar_wal_tx_dbg.c : 5886 ] DUMP_CONN_PAUSE_PEER_STATE: Peer not found +1025,II,[ ar_wal_tx_dbg.c : 5902 ] twt_debug: g_dbg_stop_seq_cnt:%u,g_dbg_stop_burst_seq_for_twt:%u +1024,i,[ ar_wal_tx_dbg.c : 5960 ] err injection omitted due to MAC inactive. pm_mac_state %d +1023,ii,[ ar_wal_tx_dbg.c : 5972 ] unit_test_cmd : TX flush interval %d enable %d +1022,,[ ar_wal_tx_dbg.c : 5975 ] HW_ERR_REINJECTION : Invalid no. of arguments during mac flush err injection +1021,iii,[ ar_wal_tx_dbg.c : 5992 ] unit_test_cmd : Host2HW Ring %d Duration %d is_on %d +1020,,[ ar_wal_tx_dbg.c : 5998 ] HW_ERR_REINJECTION : Invalid host ring id during host ring bkpressure err injection +1019,,[ ar_wal_tx_dbg.c : 6001 ] HW_ERR_REINJECTION : Invalid no. of arguments during host ring bkpressure err injection +1018,iii,[ ar_wal_tx_dbg.c : 6016 ] unit_test_cmd : FW2HW Ring %d Duration %d is_on %d +1017,iiiiiii,[ ar_wal_tx_dbg.c : 1405 ] hwsch_backpressure_wdog = %d hwsch_pause_wdog = %d hwsch_fes_start_wdog = %d hwsch_life_time_expiry_valid_fes_offset = %d crypto_wdog_tmout = %d pdg_sfm_leak_rst_cnt = %d hwsch_cmd_ring_reset_war_dummy_completions = %d +1016,,[ ar_wal_tx_dbg.c : 6019 ] HW_ERR_REINJECTION : Invalid fw ring id during fw ring bkpressure err injection +1015,,[ ar_wal_tx_dbg.c : 6022 ] HW_ERR_REINJECTION : Invalid no. of arguments during fw ring bkpressure err injection +1014,iii,[ ar_wal_tx_dbg.c : 6037 ] unit_test_cmd : HW2HW Ring %d Duration %d is_on %d +1013,,[ ar_wal_tx_dbg.c : 6040 ] HW_ERR_REINJECTION : Invalid hw ring id during hw ring bkpressure err injection +1012,,[ ar_wal_tx_dbg.c : 6043 ] HW_ERR_REINJECTION : Invalid no. of arguments during hw ring bkpressure err injection +1011,ii,[ ar_wal_tx_dbg.c : 6055 ] unit_test_cmd : RX abort interval %d enable %d +1010,,[ ar_wal_tx_dbg.c : 6058 ] HW_ERR_REINJECTION : Invalid no. of arguments during rx abort err injection +1009,,[ ar_wal_tx_dbg.c : 6071 ] HW_ERR_REINJECTION : Invalid no of arguements +1008,,[ ar_wal_tx_dbg.c : 6081 ] HW_ERR_REINJECTION : Invalid no of arguements for axi +1007,,[ ar_wal_tx_dbg.c : 6086 ] HW_ERR_REINJECTION : Invalid module for axi read latency injection +1006,iiiiiiii,[ ar_wal_tx_dbg.c : 1425 ] hwsch_flush_not_done = %d flush_tx_not_idle = %d hwsch_wd_unknown_reset = %d hwsch_mtu_wrap_wdog = %d crypto_fatal_unknown = %d txdma_fatal_unknown = %d sfm_fatal_unknown = %d mcmn_fatal_unknown = %d +1005,iii,[ ar_wal_tx_dbg.c : 6098 ] KAJAL TEST type:%d is_on:%d, num_args:%d +1004,,[ ar_wal_tx_dbg.c : 6101 ] HW_ERR_REINJECTION : Invalid no of arguements for rx data path error +1003,ii,[ ar_wal_tx_dbg.c : 6113 ] unit_test_cmd : RX flush interval %d enable %d +1002,,[ ar_wal_tx_dbg.c : 6116 ] HW_ERR_REINJECTION : Invalid no. of arguments during rx flush err injection +1001,i,[ ar_wal_tx_dbg.c : 6161 ] RTT LUT enabled : %d +1000,,[ ar_wal_tx_dbg.c : 6179 ] g_debug_arp_assert not set +999,i,[ ar_wal_tx_dbg.c : 6185 ] g_debug_arp_assert set %d +998,,[ ar_wal_tx_dbg.c : 6197 ] g_debug_mgmt_fail_assert not set +997,III,[ ar_wal_tx_dbg.c : 6205 ] g_debug_mgmt_fail_assert set %08x %08x %08x +996,,[ ar_wal_tx_dbg.c : 6265 ] AWGN_INT_DBG Wrong Input: wifitool athX setUnitTestCmd 0x48 4 400 1 +995,iiiiiiii,[ ar_wal_tx_dbg.c : 1445 ] txpcu_wdog_tout = %d txpcu_recd_lt_mpdu = %d txpcu_recd_gt_mpdu= %d pdg_fatal_unknown = %d hwsch_fatal_unknown = %d hwsch_wdog_unknown = %d mxi_fatal_unknown = %d txole_fatal_unknown = %d +994,ii,[ ar_wal_tx_dbg.c : 6270 ] AWGN_INT_DBG : intr = %d seg = %d +993,,[ ar_wal_tx_dbg.c : 6278 ] AWGN_INT_DBG Wrong Input: wifitool athX setUnitTestCmd 0x48 3 400 2 +992,ii,[ ar_wal_tx_dbg.c : 6282 ] AWGN_INT_DBG : intr = %d seg = %d +991,,[ ar_wal_tx_dbg.c : 6290 ] AWGN_INT_DBG Wrong Input: wifitool athX setUnitTestCmd 0x48 4 400 3 +990,ii,[ ar_wal_tx_dbg.c : 6295 ] AWGN_INT_DBG : tx_prop = %d rx_prop = %d +989,,[ ar_wal_tx_dbg.c : 6303 ] AWGN_INT_DBG Wrong Input: wifitool athX setUnitTestCmd 0x48 3 400 4 +988,i,[ ar_wal_tx_dbg.c : 6307 ] AWGN_INT_DBG : g_dbg_awgn_cca_mask_enable = %d + +987,,[ ar_wal_tx_dbg.c : 6311 ] AWGN_INT_DBG : wrong input + +986,iii,[ ar_wal_tx_dbg.c : 6576 ] WBM delink: Recovery WAR hit count rxpcu1_ooo_error_rx_flush : %d, rxdma_tlv_frm_err_rx_flush : %d, PDEVID %d + +985,iiiiiii,[ ar_wal_tx_dbg.c : 1493 ] tx_flush_tlv_tag_oor_err = %d tx_flush_tlv_len_oor_err = %d tx_flush_tlv_taglen_mismatch_err = %d tx_flush_unexpected_tlv_end_err = %d tx_steer_frm_cnt = %d tx_flush_txdma_sfm_busy = %d phy_warm_reset = %d +984,,[ ar_wal_tx_dbg.c : 1509 ] pdev_id can't be > 2, usage: wifitool ath0 setUnitTestCmd 0x48 2 57 +983,,[ ar_wal_tx_dbg.c : 1520 ] No ul_resp_vdev assigned !! +982,II,[ ar_wal_tx_dbg.c : 1524 ] ac:%x already in MU mode, reset timer to %x +981,IIIIII,[ ar_wal_tx_dbg.c : 952 ] txbf_su_mpdu_stats AC (txbf sifs ac su tried = %lu)(txbf sifs ac su failed = %lu)(txbf sifs ac su retried = %lu)(txbf rbo ac su tried = %lu)(txbf rbo ac su failed = %lu)(txbf rbo ac su retried = %lu) +980,I,[ ar_wal_tx_dbg.c : 1527 ] ac:%x switch to MU mode +979,I,[ ar_wal_tx_dbg.c : 1680 ] flush hwq mask:%x +978,I,[ ar_wal_tx_dbg.c : 1685 ] flush hwq mask:%x, ul_resp is not enabled +977,iii,[ ar_wal_tx_dbg.c : 1761 ] g_eapol_rekey_min_rate_enable num_args:%d %d, %d +976,IIII,[ ar_wal_tx_dbg.c : 1840 ] TXDEWDOG TCL1:%u full_ignore:%u dummy_queued:%u last_time:%u +975,III,[ ar_wal_tx_dbg.c : 547 ] data_stall debug support is not allowed as the vdev_type is not STA pdev_id:8/vdev_id:8 0x%08x vdev:0x%x pdev:0x%x +1135,ii,[ ar_wal_tx_send_selfgen.c : 4977 ] UL_MUMIMO_DBG, seq_type %d, is_ul_mumimo: %d +1142,,[ ar_wal_tx_halphy_send.c : 652 ] HALPHY_TX_TBTT_FLUSH : DPD packet is flushed out +1141,,[ ar_wal_tx_halphy_send.c : 661 ] HALPHY_TX_ABORT : DPD packet is aborted +1140,,[ ar_wal_tx_halphy_send.c : 755 ] tx_send_halphy_abort_ppdu : DPD packet is aborted +1139,i,[ ar_wal_tx_halphy_send.c : 222 ] PAPRD dpd start tlv event : start evt latency %d +1138,i,[ ar_wal_tx_halphy_send.c : 1273 ] wal_check_ppdu_status DPD ppdu is stuck in the hardware queue %d +1137,i,[ ar_wal_tx_halphy_send.c : 1259 ] thread id %d +1136,iiiii,[ ar_wal_tx_halphy_send.c : 931 ] PAPRD Total PHY OFF %d Tx suspend fail %d Rx suspend fail %d Tx suspend %d, Tx suspend %d +1146,,[ ar_wal_tx_disa_send.c : 197 ] disa tx_frame NOT EXPECTED since no status would be recv +1145,i,[ ar_wal_tx_disa_send.c : 139 ] DISA tx_frame tx_buf_count %d +1144,i,[ ar_wal_tx_disa_send.c : 152 ] DISA tx_frame After Delay tx_buf_count %d +1143,i,[ ar_wal_tx_disa_send.c : 162 ] DISA tx_frame After Delay tx_buf_count %d +1147,iI,[ ar_wal_tx_flush.c : 568 ] _wal_peer_flush_tids: send msg to SCHED_ALGO, thread_id =%d tid_bitmap=0x%x + +1148,i,[ ar_wal_tx_send_isr.c : 552 ] TX_IST_TRIGGER RECEIVED %d + +1196,I,[ ar_wal_tx_send.c : 13179 ] TX_ABORT FAILED 0x%x +1195,Ii,[ ar_wal_tx_send.c : 4074 ] tx_send_attach failed 0x%x, line:%d +1194,iiii,[ ar_wal_tx_send.c : 13547 ] CONSECUTIVE_FLUSH9: pdev id %d,reset_mode %d consecutive flush 9 happen for %d times.Total WAR trigger %d times. +1193,ii,[ ar_wal_tx_send.c : 18427 ] pdev %d, WIFIMISSING_MPDU_INFO_E cnt: %d + +1192,i,[ ar_wal_tx_send.c : 18522 ] Retried BAR for %d times, clear BAR flag + +1191,iI,[ ar_wal_tx_send.c : 18535 ] BAR tx failure tid_num: %d, tid_flags:0x%x + +1190,II,[ ar_wal_tx_send.c : 18758 ] TX resuming on MAC: %p, %lx + +1189,III,[ ar_wal_tx_send.c : 18791 ] seq not cleaned ! queue_id:%x, txq:%p, seq_ctrl:%p + +1188,ii,[ ar_wal_tx_send.c : 11946 ] tx_send_dsr_ppdu_done increment peer->consecutive_eap_cnt : %d, sw_peer_id: %d +1187,ii,[ ar_wal_tx_send.c : 11953 ] tx_send_dsr_ppdu_done clear peer->consecutive_eap_cnt : %d, sw_peer_id: %d +1186,Iii,[ ar_wal_tx_send.c : 11967 ] tx_send_dsr_proc_ppdu_done consecutive_pm_filter_cnt %0x %d, %d MAC reset counter + +1185,iiiIIiii,[ ar_wal_tx_send.c : 12031 ] twt_dbg/ul_tcp: dsr_proc_ppdu_done txqid=%d, sched_id=%d, tx_status=%d, peer=%u, ftype=%u, queued=%d, tried=%d, failed=%d + +1184,II,[ ar_wal_tx_send.c : 19624 ] Pause UL ring - wal_txq_id:%x,wal_txq_id_sta_ul:%x +1183,iiiiiIII,[ ar_wal_tx_send.c : 19639 ] TTL tid:%d ppdu:%d %d,cmd:%d txq_id:%d,flg:%x %x,caller:%x +1182,iiii,[ ar_wal_tx_send.c : 19391 ] MSDUTTL TQM peer_id:%d deq:%d tid_num:%d qtype:%d +1181,I,[ ar_wal_tx_send.c : 20522 ] Received GTK frame for Qpeer=%p, but PTK not set +1180,III,[ ar_wal_tx_send.c : 21670 ] pdev:%u, RING(%x) pause finished(%x) +1179,III,[ ar_wal_tx_send.c : 21743 ] pdev:%u, pause ring(%x:%x) +1178,ii,[ ar_wal_tx_send.c : 8612 ] LDC: tlv's not setting due to mcs=%d and bw=%d +1177,Iiiii,[ ar_wal_tx_send.c : 8897 ] allow_n_flags 0x%x sendn_frms_allowed %d sendn_frms_tried %d subfrms_max %d encap_type %d +1176,iiI,[ ar_wal_tx_send.c : 9256 ] tx_send_post_data_ppdu g_dbg_tx_profile delta1 %d seq_type %d frm_ctrl 0x%0x +1175,II,[ ar_wal_tx_send.c : 20332 ] peer:%p, tid:16/SSN:16 0x%08x +1174,II,[ ar_wal_tx_send.c : 20338 ] peer:%p, PN=%X +1173,I,[ ar_wal_tx_send.c : 6689 ] legacy frame with HT-ctrl not allowed if QPEER_ALLOW_DATA, tid=%x +1172,I,[ ar_wal_tx_send.c : 6693 ] legacy frame with HT-ctrl, tid=%x +1171,II,[ ar_wal_tx_send.c : 7002 ] ppdu start time (%u) is in the past of current tsf (%u), deliver 1ms +1170,iiIiI,[ ar_wal_tx_send.c : 20936 ] tx_send_stop_mu_edca_timer: pdev:%d can't stop muedca timer vdev:%d mu_resp:%08X mu_edca_en:%d ac_bitmap:%08x +1169,ii,[ ar_wal_tx_send.c : 20964 ] tx_send_stop_mu_edca_timer: pdev:%d ac:%d stop muedca timer and back to legacy edca +1168,iiIiI,[ ar_wal_tx_send.c : 14193 ] tx_send_stop_muedca_timer: pdev:%d can't stop muedca timer vdev:%d mu_resp:%08X mu_edca_en:%d ac_bitmap:%08x +1167,,[ ar_wal_tx_send.c : 18114 ] INVALID TPC REGISTER + +1166,IIIIIIIII,[ ar_wal_tx_send.c : 16197 ] TXPPDU_0 peerid_tidnum_hwq:0x%08x ppdu_id:0x%08x tstamp:0x%08x%08x dur:%5u sw_sched_id__mpdutried__failed:0x%08x mcs_nss_bw_pream:0x%08x seqnum__sifs__sch:0x%08x tries__fes__flush:0x%08x +1165,IIIII,[ ar_wal_tx_send.c : 16215 ] TXPPDU_1_064 ssn__basn:0x%08x enq_bitmap:%08x_%08x compl_bitmap:%08x_%08x +1164,IIIIIIIII,[ ar_wal_tx_send.c : 16229 ] TXPPDU_1_256 ssn__basn:0x%08x compl_bitmap:%08x_%08x_%08x_%08x_%08x_%08x_%08x_%08x +1163,IIIIIIIII,[ ar_wal_tx_send.c : 16277 ] TXPPDU_2 sched_id:%08x sch_flg:%08x swppdu_flg:%08x msdu_mpdu:%08x tpc_lb1_lb0_cmndpwr1_pwr0:%08x cca_cycle:%08x txrx_frm:%08x pwrsurge_timestmp_size1cnt_rssi:%08x pad1_ani_cck_ofdma_leg_ovs_abort_crc:%08x +1162,II,[ ar_wal_tx_send.c : 16282 ] TXPPDU_3 seq_ctrl:%08x seq_ctrl_flags:%08x +1161,III,[ ar_wal_tx_send.c : 21598 ] pdev:%u, RING(%x) pause WAR triggered(%x) +1160,i,[ ar_wal_tx_send.c : 15444 ] delimiter user track: peer_aid:%d runs out of data +1159,i,[ ar_wal_tx_send.c : 15526 ] delimiter user track: peer_aid:%d runs out of data +1158,IiiI,[ ar_wal_tx_send.c : 17021 ] TXPPDU_0 ppdu_id:0x%08x sched_result:%d flush_reason:%d uid1__uid2:0x%08x +1157,iiIiiiiII,[ ar_wal_tx_send.c : 16483 ] twt_dbg: update_dl_stats txqid=%d, sched_id=%d, ftype=%u, tx_status=%d, queued=%d, tried=%d, failed=%d,sched_ref_time_start=%u, sched_ref_time_end=%u + +1156,IIIII,[ ar_wal_tx_send.c : 16519 ] twt_dbg_leak: update_dl_stats: start_tsTstamp=%u, duration_us=%u, sch_eval_end_ts=%u, twt_sp_end=%u, offset_tsf2=%u + +1155,I,[ ar_wal_tx_send.c : 16523 ] twt_dbg_leak: update_dl_stats twt_sp leakage detected by %u us +1154,iiiIIIII,[ ar_wal_tx_send.c : 16555 ] twt_dbg_leak_ul: update_ul_stats: txqid=%d, sched_id=%d, tx_sw_status=%d, fes_start=%u, fes_end=%u, fes_duration=%u, sched_ref_time_start=%u, sched_ref_time_end=%u + +1153,IIII,[ ar_wal_tx_send.c : 16590 ] twt_dbg_leak_ul: update_ul_stats: sch_eval_start_ts=%u, sch_eval_end_ts=%u, twt_sp_end=%u, offset_tsf2=%u + +1152,I,[ ar_wal_tx_send.c : 16594 ] twt_dbg_leak_ul: update_ul_stats twt_sp leakage detected by %u us +1151,IIIIIIII,[ ar_wal_tx_send.c : 14045 ] update_hw_wmm_params: ac:%x,ul_resp=%x,txqid=%x,cw_min/cw_max:%x,aifs:%x,type=%x,txop_limit=%x %x +1150,iIi,[ ar_wal_tx_send.c : 2665 ] update pdev(%d) vdev(%p) wmm params, type=%d +1149,,[ ar_wal_tx_send.c : 2706 ] MU-EDCA being used while update its WMM parameters. +1202,I,[ ar_wal_tx_seq.c : 6023 ] tx_send_seq_is_sched_cmd_cache_matched result 0x%0x +1201,iiii,[ ar_wal_tx_seq.c : 6518 ] PATTERN_DBG: search for seq_ctrl max pat idx: pidx: %d, num_pat: %d, pattern_bw: %d, max_bw: %d + +1200,II,[ ar_wal_tx_seq.c : 5443 ] tx_send_seq_trig_dsr_done_SAVE_CACHE seq_ctrl 0x%0x to txq 0x%0x +1199,,[ ar_wal_tx_seq.c : 5019 ] CW reset +1198,iiiiiii,[ ar_wal_tx_seq.c : 7605 ] 6G FCC: BW recipe state: max_bw_restricted - %d, max_queued_bw - %d, current_transmitted_bw - %d, resp_bw - %d, num_intereference_at_sec[%d/%d/%d] +1197,ii,[ ar_wal_tx_seq.c : 7773 ] tx_seq_trigger_ppdu_start_event_isr: can not switch to MUEDCA %d %d +1209,iiiiiiiii,[ tx_cong_ctrl.c : 256 ] CONGCTRL FW_CONTROL *OVERRIDE* peer_id:%d tid_num:%d traffic_enq:%d drop:%d deq:%d tot_deq:%d rate_max_allowed:%d old_threshold:%d max_extra:%d +1208,iiiiiiiii,[ tx_cong_ctrl.c : 269 ] CONGCTRL FW_CONTROL *DISABLED* peer_id:%d tid_num:%d traffic_enq:%d drop:%d deq:%d tot_deq:%d rate_max_allowed:%d old_threshold:%d max_extra:%d +1207,iIiiiiiii,[ tx_cong_ctrl.c : 285 ] CONGCTRL FW_CONTROL peer_id:%d tid_num__qtype__msduq_masks:0x%08x traffic_enq:%d drop:%d deq:%d tot_deq:%d rate_max_allowed:%d old_threshold:%d max_extra:%d +1206,iiiiii,[ tx_cong_ctrl.c : 55 ] CONG_CTRL_FD sw_pid:%d tid_num:%d buf_id:%d desc_id:%d bin_idx:%d cur:%d +1205,iii,[ tx_cong_ctrl.c : 73 ] CONG_CTRL_DiscD sw_pid:%d tid_num:%d buf_id:%d +1204,iiiiii,[ tx_cong_ctrl.c : 61 ] CONG_CTRL_AD sw_pid:%d tid_num:%d buf_id:%d desc_id:%d bin_idx:%d cur:%d +1203,iii,[ tx_cong_ctrl.c : 67 ] CONG_CTRL_DropD sw_pid:%d tid_num:%d buf_id:%d +1222,II,[ ar_wal_txbf.c : 1255 ] wal_txbf_cv_buf_get DMA not done cv_buf->sw_peer_id 0x%x pdev_id %u +1221,,[ ar_wal_txbf.c : 1500 ] WAL_POWER_STATE_FULL_SLEEP +1220,,[ ar_wal_txbf.c : 1527 ] WAL_POWER_STATE_AWAKE +1219,IIII,[ ar_wal_txbf.c : 1392 ] txbf_peer_setup:Peer_caps VHT:SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1218,IIII,[ ar_wal_txbf.c : 1400 ] txbf_peer_setup:Peer_caps HE :SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1217,IIII,[ ar_wal_txbf.c : 1408 ] txbf_peer_setup:Vdev_caps VHT :SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1216,IIII,[ ar_wal_txbf.c : 1416 ] txbf_peer_setup:Vdev_caps HE :SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1215,II,[ ar_wal_txbf.c : 1436 ] txbf_peer_setup:Txbfer:0x%x and txbfee count:0x%x +1214,IIII,[ ar_wal_txbf.c : 596 ] txbf_peer_teardown:Peer_caps VHT :SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1213,IIII,[ ar_wal_txbf.c : 604 ] txbf_peer_teardown:Peer_caps HE :SU:bfee=%x,bfer=%x MU:Bfee=%x,bfer=%x +1212,III,[ ar_wal_txbf.c : 619 ] txbf_peer_setup:vdev %x Txbfer:0x%x and txbfee count:0x%x +1211,iI,[ ar_wal_txbf.c : 1474 ] wal_txbf_update_txbfee_filter:en:%d,txbfee_dis_bitmap:0x%x +1210,ii,[ ar_wal_txbf.c : 987 ] PHY set gid:%d, pos:%d +1224,IIIi,[ offload_common.c : 219 ] wlan_rx_dup_chk_fail: NULL pointer passed 0x%x 0x%x 0x%x %d + +1223,iIIII,[ offload_common.c : 249 ] wlan_rx_dup_chk_fail(%d): Dropping Duplicate Frame_info:%x Seq:%x Time:%x Last_Time:%x + +1226,IIi,[ wal_powersave_sta.c : 347 ] _wal_ps_sta_process_rx_event: frame_control=%0x, qos_control=%0x, thread_id=%d +1225,,[ wal_powersave_sta.c : 362 ] wal_ps_sta_process_rx_event: leaky AP detected +1238,iiiii,[ wal_powersave_ap.c : 1455 ] wal_ps_ap_is_out_of_sync_sta: AssocID=%d, Timestamp=%d, OldestTxBufferedWaitingMs=%d, detect_thresh=%d, QDepeth=%d +1237,iI,[ wal_powersave_ap.c : 695 ] wal_ps_ap_sa_thread_msg_handler: peer=%d, cmd_id:%u +1236,iiii,[ wal_powersave_ap.c : 1602 ] WAL_AP_PS_DBGID_SLEEP_STA_DEC vdev_id = %d num_sleeping_sta:%d is_tid_paused:%d tid_pause_bitmap:%d +1235,iiii,[ wal_powersave_ap.c : 1543 ] WAL_AP_PS_DBGID_SLEEP_STA_INC vdev_id = %d num_sleeping_sta:%d is_tid_paused:%d tid_pause_bitmap:%d +1234,iiii,[ wal_powersave_ap.c : 425 ] WAL_AP_PS_DBGID_PSPOLL_REQ AssocID = %d Aid = %d PeerPSEnabled = %d SendNInProgress = %d +1233,iii,[ wal_powersave_ap.c : 474 ] WAL_AP_PS_DBGID_DUPLICATE_TRIGGER AssocID = %d SeqNO = %d Tid = %d +1232,iii,[ wal_powersave_ap.c : 490 ] WAL_AP_PS_DBGID_NO_TRIGGER AssocID = %d peer_handle->uapsd_trigger_tids = %d Tid = %d +1231,iIiI,[ wal_powersave_ap.c : 546 ] wal_ps_buf_peer_rx_event_handler(RX): aid=%d, fc=0x%x, seq=%d, timestamp_us=%u +1230,iIiII,[ wal_powersave_ap.c : 568 ] wal_ps_buf_peer_rx_event_handler(DATA_PPDU): aid=%d, fc=0x%x, seq=%d, qos=0x%x, timestamp_us=%u +1229,,[ wal_powersave_ap.c : 316 ] error: no WAL_PEER_EVENT_SEND_COMPLETE for BUF_STA +1228,iiii,[ wal_powersave_ap.c : 1296 ] WAL_AP_PS_DBGIG_SET_PARAM vdev_id = %d AssocID = %d Param = %d Value = %d +1227,iiII,[ wal_powersave_ap.c : 1358 ] WAL_AP_PS_DBGIG_UAPSD_CFG vdev_id = %d AssocID = %d UAPSDTriggerTids = 0x%x UAPSDDeliveryTids = 0x%x +1252,iii,[ wal_powersave_buf_peer_sm.c : 1190 ] WAL_ML_AP_PS: WAL_AP_PS_DBGID_UPDATE_TIM vdev_id = %d AssocID = %d IsTimSet = %d +1251,iiiii,[ wal_powersave_buf_peer_sm.c : 984 ] WAL_AP_PS_DBGID_NEXT_RESPONSE vdev_id = %d AssocID = %d USPActive = %d PendingUSP = %d PendingPollResp = %d +1250,iiI,[ wal_powersave_buf_peer_sm.c : 993 ] WAL_AP_PS_DBGID_START_SP vdev_id = %d AssocID = %d last_rx_trigger_time = %u +1249,iiII,[ wal_powersave_buf_peer_sm.c : 1024 ] WAL_AP_PS_DBGID_COMPLETED_EOSP vdev_id = %d AssocID = %d tx_comp_ts = %u last_rx_trigger_time = %u +1248,iii,[ wal_powersave_buf_peer_sm.c : 1043 ] WAL_AP_PS_DBGID_COMPLETED_EOSP vdev_id = %d AssocID = %d retried %d +1247,iiIIii,[ wal_powersave_buf_peer_sm.c : 1078 ] WAL_AP_PS_DBGID_SEND_COMPLETE vdev_id = %d AssocID = %d FrameCtrl = 0x%x QoSCtrl = 0x%x USPActive = %d PendingPollResp = %d +1246,iiii,[ wal_powersave_buf_peer_sm.c : 1140 ] WAL_AP_PS_DBGID_SEND_N_COMPLETE vdev_id = %d AssocID = %d USPActive = %d PendingPollResp = %d +1245,iiIii,[ wal_powersave_buf_peer_sm.c : 756 ] WAL_AP_PS_DBGID_TRIGGER vdev_id = %d AssocID = %d A_MILLISECONDS = %u USPActive = %d SendNInProgress = %d +1244,iiI,[ wal_powersave_buf_peer_sm.c : 773 ] WAL_AP_PS_DBGID_START_SP vdev_id = %d AssocID = %d A_MILLISECONDS = %u +1243,iiiIIII,[ wal_powersave_buf_peer_sm.c : 487 ] WAL_AP_PS_DBGID_PSPOLL vdev_id = %d AssocID = %d Tid = %d Flags = 0x%x legacy_tidmask = 0x%x allowed_legacy_tidmask = 0x%x pending_legacy_tidmap = 0x%x +1242,iiiII,[ wal_powersave_buf_peer_sm.c : 499 ] WAL_AP_PS_DBGID_PSPOLL_ERROR vdev_id = %d AssocID = %d TidPaused = %d AllowdLegacyTidMask = 0x%x LegacyTidMask = 0x%x +1241,iiiiiIII,[ wal_powersave_buf_peer_sm.c : 700 ] WAL_AP_PS_DBGID_UAPSD_RESPONSE vdev_id = %d AssocID = %d Tid = %d NumMPDUToSend = %d need_extra_qnull = %d Flags = 0x%x allow_n_flags_qnull = 0x%x SPLength = 0x%x +1240,iiIIII,[ wal_powersave_buf_peer_sm.c : 737 ] WAL_AP_PS_DBGID_UAPSD_RESPONSE_ERROR vdev_id = %d AssocID = %d Tid/Paused = 0x%x AllowedUAPSDTidMask = 0x%x PendingTidMap = 0x%x SPLength = 0x%x +1239,iiIi,[ wal_powersave_buf_peer_sm.c : 1263 ] WAP_ML_AP_PS: WAL_AP_PS_DBGID_SYNC_TIM vdev_id = %d AssocID = %d Tids = 0x%x TimSet = %d +1256,i,[ twt_protocol.c : 398 ] twt_info unexpected: resp_req(%d)!=0 +1255,i,[ twt_protocol.c : 402 ] twt_info unexpected: next_req(%d)!=0 +1254,I,[ twt_protocol.c : 471 ] twt_parse_teardown_frame(!wake_tbtt_nego): twt_flow=%u +1253,,[ twt_protocol.c : 67 ] twt_power_2_mantissa wrong parameters +1297,i,[ twt_ap.c : 1945 ] %d: UAPSD+TWT Not allowed +1296,i,[ twt_ap.c : 1981 ] ap_twt_add_i_session(send_failed): status=%d +1295,ii,[ twt_ap.c : 415 ] ap_twt_check_send_del_all_frame FAIL for peer:%d after %d attempts +1294,iiIi,[ twt_ap.c : 450 ] ap_twt_check_send_del_frame FAIL for peer:%d session:%d flags:%x after %d attempts +1293,ii,[ twt_ap.c : 2037 ] ap_twt_del_dialog[unknown dialog_id]: peer=%d, dialog_id=%d +1292,i,[ twt_ap.c : 981 ] twt_ap_twt_session_t == NULL, session_id=%d +1291,i,[ twt_ap.c : 1409 ] %d: AP TWT not initialized on this MAC +1290,i,[ twt_ap.c : 1415 ] %d: AP TWT: disable cmd cannot find SOC handle +1289,i,[ twt_ap.c : 996 ] twt_ap_twt_session_t == NULL, session_id=%d +1288,i,[ twt_ap.c : 1433 ] %d: AP TWT not initialized on this MAC +1287,i,[ twt_ap.c : 1439 ] %d: AP TWT: disable cmd cannot find SOC handle +1286,i,[ twt_ap.c : 1013 ] twt_ap_twt_session_t == NULL, session_id=%d +1285,iiiii,[ twt_ap.c : 363 ] ap_twt_send_del_event Error: %d %d %d %d %d +1284,,[ twt_ap.c : 244 ] POOL ALLOC FAILURE +1283,i,[ twt_ap.c : 710 ] %d: ap_twt_setup_tx_completion: parse_setup_frame error +1282,ii,[ twt_ap.c : 714 ] ap_twt_setup_tx_completion: status=%d, comp_ctxt=%d +1281,ii,[ twt_ap.c : 820 ] ap_twt_teardown_tx_completion err: status=%d, comp_ctxt=%d +1280,i,[ twt_ap.c : 2055 ] %d: AP TWT not enabled on this vdev +1279,i,[ twt_ap.c : 2068 ] %d: AP TWT not enabled on this peer +1278,i,[ twt_ap.c : 2206 ] %d: AP TWT not enabled on this vdev +1277,i,[ twt_ap.c : 2217 ] %d: AP TWT peer memory not available on this vdev +1276,i,[ twt_ap.c : 3271 ] TWT AP Unexpected frame type %d +1275,i,[ twt_ap.c : 2118 ] %d: AP TWT not enabled on this vdev +1274,i,[ twt_ap.c : 2142 ] %d: AP TWT not enabled on this peer +1273,i,[ twt_ap.c : 2266 ] %d: AP TWT not enabled on this peer +1272,i,[ twt_ap.c : 2272 ] %d: AP TWT not enabled on this vdev +1271,i,[ twt_ap.c : 1385 ] %d: AP TWT not initialized on this MAC +1270,i,[ twt_ap.c : 1391 ] %d: AP TWT: disable cmd cannot find SOC handle +1269,ii,[ twt_ap.c : 2725 ] %d: session not found: session_id=%d +1268,i,[ twt_ap.c : 3450 ] %d: AP TWT not initialized on this MAC +1267,i,[ twt_ap.c : 2988 ] %d: TWT AP, setup frame details is NULL +1266,i,[ twt_ap.c : 2636 ] %d: AP TWT not enabled on this peer +1265,i,[ twt_ap.c : 2641 ] AP TWT duplicate dialog token(%d) received +1264,i,[ twt_ap.c : 2673 ] TWT AP Unexpected command %d +1263,i,[ twt_ap.c : 1328 ] %d: AP TWT not initialized on this MAC +1262,ii,[ twt_ap.c : 1338 ] %d: AP TWT disable on MAC:%d +1261,ii,[ twt_ap.c : 1253 ] %d: AP TWT not initialized on this MAC %d +1260,ii,[ twt_ap.c : 1263 ] %d: AP TWT enable on MAC %d +1259,iii,[ twt_ap.c : 1189 ] %d: Mismatch between reported number ofsessions %d and actual number of sessions %d +1258,iIii,[ twt_ap.c : 1575 ] %d: DUPLICATE REQ twt_ap_vdev_migrate for vdev:%x migrating from MAC%d to MAC%d +1257,iIIiiI,[ twt_ap.c : 1584 ] %d: twt_ap_vdev_migrate complete, vdev:%x twt_vdev:%x migrate from MAC%d to MAC%d new_twt_pdev:%x +1300,i,[ twt_ap_session_sm.c : 569 ] sending pause frame failed: status=%d +1299,iiiI,[ twt_ap_session_sm.c : 458 ] ap_twt_session_state_renegotiating_event failed after %d attempts for peer=%d session:%d flags:%x +1298,i,[ twt_ap_session_sm.c : 762 ] sending resume frame failed: status=%d +1302,I,[ twt_ap_adaptor.c : 749 ] TWT_ADD_TIME_POINT: tsf_cnt(%u) >= arr_len +1301,I,[ twt_ap_adaptor.c : 752 ] TWT_ADD_TIME_POINT: tsf_cnt(%u) >= arr_len +1310,I,[ twt_ap_btwt.c : 553 ] ap_btwt_check_persist error: b_twt_persistence(%u) > 254 +1309,II,[ twt_ap_btwt.c : 560 ] ap_btwt_check_persist error: reducing more than 1, cur=%u, new=%u +1308,ii,[ twt_ap_btwt.c : 757 ] %d: session not found: session_id=%d +1307,i,[ twt_ap_btwt.c : 577 ] ap_btwt_session == NULL, session_id=%d +1306,,[ twt_ap_btwt.c : 816 ] btwt get session failure +1305,,[ twt_ap_btwt.c : 384 ] POOL ALLOC FAILURE +1304,,[ twt_ap_btwt.c : 613 ] btwt get session failure +1303,i,[ twt_ap_btwt.c : 1066 ] sending pause frame failed: status=%d +1318,,[ twt_ap_smartwt.c : 498 ] twt_assign_peer POOL ALLOC FAILURE +1317,,[ twt_ap_smartwt.c : 522 ] twt_assign_peer POOL ALLOC FAILURE +1316,,[ twt_ap_smartwt.c : 428 ] twt_slot POOL ALLOC FAILURE +1315,III,[ twt_ap_smartwt.c : 266 ] ap_smartwt_get_slot_idx_start_time_end_time last_slot_extra_dur_us %llu temp %llu diff_in_time %llu +1314,IIiI,[ twt_ap_smartwt.c : 34 ] : num_peer=%d, flags=0x%x +1313,IiiI,[ twt_ap_smartwt.c : 40 ] [slot%u] peer=%d, session=%d, flags=0x%x +1312,i,[ twt_ap_smartwt.c : 699 ] ap_smartwt_setup_comp(slot_match failed): slot_id=%d +1311,i,[ twt_ap_smartwt.c : 1632 ] ap_smartwt_setup_teardown_peers(send_failed): status=%d +1327,,[ wal_swba.c : 715 ] no vaps to send beacon. swba_map is empty +1326,II,[ wal_swba.c : 806 ] Staggered beacon drift: next_beacon = %u, next_hw_tbtt = %u +1325,III,[ wal_swba.c : 816 ] Staggered beacon drift recover: next_beacon = %u, beacon_period = %u, until_next_tbtt = %u +1324,I,[ wal_swba.c : 836 ] cur_tsf %u +1323,II,[ wal_swba.c : 917 ] Burst beacon drift: next_beacon = %u, next_hw_tbtt = %u +1322,III,[ wal_swba.c : 927 ] Burst beacon drift recover: next_beacon = %u, beacon_period = %u, until_next_tbtt = %u +1321,IIIIII,[ wal_swba.c : 781 ] swba_intr: misc=0x%x,period=%u,tsf=%u,tbtt-curr=%u/next=%u,diff=%u +1320,,[ wal_swba.c : 277 ] next beacon tsf slot is not proper +1319,IIII,[ wal_swba.c : 1789 ] _wal_swba_set_and_fire: cur_tsf=0x%x sta_offset=0x%x next_beacon=0x%x next_beacon_slot=%u +1331,I,[ wal_chain_mgmt.c : 74 ] WAL_DBGID_GET_HW_CHAINMASK SHIFTED_RF_CM: Rx:0x%x +1330,I,[ wal_chain_mgmt.c : 57 ] WAL_DBGID_GET_HW_CHAINMASK SHIFTED_RF_CM: Tx:0x%x +1329,II,[ wal_chain_mgmt.c : 39 ] WAL_DBGID_GET_HW_CHAINMASK Tx:0x%x Rx:0x%x +1328,III,[ wal_chain_mgmt.c : 169 ] WAL_DBGID_SET_HW_CHAINMASK 0x%x 0x%x 0x%x +1332,i,[ wal_channel_change.c : 139 ] _wal_set_home_channel : num home chans = %d +1353,III,[ wal_coex_main.c : 367 ] WAL_COEX_CONFIG_MGR: state(0x%x) stimulus(%u) band(%u) +1352,IIIII,[ wal_coex_main.c : 3018 ] COEX_ENTER_CRITICAL_OCS: Error(0x%x) Dur(%u) Intrvl(%u) TransState(0x%x) Status(%u) +1351,III,[ wal_coex_main.c : 1842 ] COEX_ENTER_OCS: OCSTransitionState(%u) Status(%u) DynOCSStatus(%u) +1350,I,[ wal_coex_main.c : 2743 ] COEX_ERR_FREQ_OCS_ENTER: ERROR: Time since since OCS exit = %u +1349,IIIII,[ wal_coex_main.c : 2798 ] COEX_ENTER_OCS: Error(0x%x) Dur(%u) Intrvl(%u) TranState(0x%x) Status(%u) +1348,II,[ wal_coex_main.c : 779 ] WAL_COEX_ENTER_PSP: Error(0x%x) TX_SEND_BURST disabled (0x%x) +1347,II,[ wal_coex_main.c : 3099 ] COEX_EXIT_CRITICAL_OCS: TransState(%u) Status(%u) +1346,II,[ wal_coex_main.c : 1759 ] COEX_EXIT_OCS: OCSTransitionState(0x%x) DynOCSStatus(%u) +1345,III,[ wal_coex_main.c : 2866 ] COEX_EXIT_OCS: TranState(%u) Status(%u) Exit Reason(%u) +1344,,[ wal_coex_main.c : 794 ] WAL_COEX_EXIT_PSP: Exit PSP is already in progress +1343,III,[ wal_coex_main.c : 835 ] WAL_COEX_EXIT_PSP: Error(0x%x) TX_SEND_BURST enabled (0x%x), reason:%u +1342,II,[ wal_coex_main.c : 3203 ] WAL_COEX_BDF: Flags(0x%x) Config(0x%x) +1341,IIIIIII,[ wal_coex_main.c : 2335 ] WAL_COEX_MNGR: Error(0x%x) mac(%u) Stimulus(%u) Reason(%u) BTSMState(0x%x) SysUpdateResult(%u) ConfigMngr(0x%x) +1340,III,[ wal_coex_main.c : 861 ] WAL_COEX_PSP: Error(0x%x) MinInterval(%u) BtIdleTime(%u) +1339,II,[ wal_coex_main.c : 505 ] COEX_SET_NSS: VdevId(%u) NumStreams(%u) +1338,IIIIIIIII,[ wal_coex_main.c : 1619 ] COEX_SYSTEM_UPDATE: status(%u) stimulus(%u) hw_mode(%u) num_chains(%u) aggr_lim(%u) 3ant[bt_sep_ant(%u) ant_iso(%u) cfg_mode(%u) run_mode(%u)] +1337,IIII,[ wal_coex_main.c : 3132 ] COEX_UPDATE_CRITICAL_OCS: Dur(%u) Intrvl(%u) TransState(0x%x) Status(%u) +1336,IIII,[ wal_coex_main.c : 2898 ] COEX_UPDATE_OCS: Dur(%u) Intrvl(%u) TransState(0x%x) Status(%u) +1335,I,[ wal_coex_main.c : 3362 ] WAL_COEX_WSI: Error(0x%x) +1334,I,[ wal_coex_main.c : 3384 ] WAL_COEX_WSI_TMR: enable(%u) +1333,I,[ wal_coex_main.c : 3389 ] WAL_COEX_WSI_TMR: enable(%u) +1362,,[ wal_coex_sys_monitor.c : 905 ] COEX_GENERIC_ERROR: COEX_ERROR_GET_RSSI +1361,,[ wal_coex_sys_monitor.c : 930 ] COEX_GENERIC_ERROR: COEX_ERROR_GET_RSSI_SEQ +1360,IIIII,[ wal_coex_sys_monitor.c : 757 ] COEX_RX_RATE_THRESHOLD: RSSIType(%u) LowKbpsThresh(%u) UpperKbpsThresh(%u) NumPPDUsBelowThresh(%u) NumPPDUsAboveThresh(%u) +1359,IIII,[ wal_coex_sys_monitor.c : 553 ] COEX_RX_RATE_THRESHOLD: ChWidth(0xFF) TriggRate(%u) XputMonitorActiveNum(%u) TotalCoexIntrvls(%u) EventType(%u) +1358,IIIII,[ wal_coex_sys_monitor.c : 582 ] COEX_RX_RATE_THRESHOLD: ChWidth(%u) TriggRate(%u) XputMonitorActiveNum(%u) TotalCoexIntrvls(%u) EventType(%u) +1357,II,[ wal_coex_sys_monitor.c : 674 ] COEX_GENERIC_ERROR: ErrCode(%u) RSSIType(%u) +1356,I,[ wal_coex_sys_monitor.c : 679 ] COEX_GENERIC_ERROR: ErrCode(%u) +1355,IIIIIIIII,[ wal_coex_sys_monitor.c : 532 ] COEX_SYS_MON_BT: [bt_on|pmh|non_link|acl_int|passive_bt|ba_active](0x%06x) num_prof(%u) ACL(%u) sniff(%u) [3DD|APTX_LL|A2DP](0x%03x) HID(%u) HFP/RVP(%u) BA(%u) ISO|ASHA|LE(0x%03x) +1354,IIIIIIIi,[ wal_coex_sys_monitor.c : 539 ] COEX_SYS_MON_WLAN: mac(%u) rx_crit(%u) rx_state(0x%x) wlan0_state(0x%x) wlan1_state(0x%x) 2g_pdev_idle(%u) probe_req_def(%u) low_latency_en(%d) +1369,,[ wal_coex_wlan_event_handler.c : 1217 ] COEX_GENERIC_ERROR: COEX_LIST_OVERFLOW_ERROR +1368,,[ wal_coex_wlan_event_handler.c : 494 ] COEX_VDEV_STATE: 2g vdev not paused +1367,,[ wal_coex_wlan_event_handler.c : 541 ] COEX_VDEV_STATE: 2g vdev not unpaused +1366,III,[ wal_coex_wlan_event_handler.c : 289 ] BTCOEX_DBG_MCI_2: wal_coex_process_vdev_start_stop - opmode(%u) subop(%u) chan(0x%x) +1365,,[ wal_coex_wlan_event_handler.c : 323 ] COEX_VDEV_STATE: Disabling PTA coex because vdev is brought down +1364,II,[ wal_coex_wlan_event_handler.c : 1188 ] UPDATE_SPECIFIC_AP_STATE: connected:%u, behaviour:%u +1363,III,[ wal_coex_wlan_event_handler.c : 1093 ] WAL_COEX_VDEV_STATE: Error(0x%x) stimulus(%u) status(%u) +1371,IIII,[ wal_coex_sys_update.c : 324 ] WAL_COEX_RC_CHAINMASK: pdev_id(%u) RFBand(%u) ShareIndx(%u) NumWlanRfChains(%u) +1370,IIIIIII,[ wal_coex_sys_update.c : 418 ] WAL_COEX_ALT_CHM: pdev(%u) chm(0x%x) enable_alt(%u) is_2gchan(%u) alt_chm(%u) selfgenAltChm (%u) pending(%u) +1374,IIIIII,[ wal_coex_cts2s.c : 360 ] WAL_COEX_CTS2S_RESULT: result(%u) pdev(%u) ts(%u) cts2s_tx_latency(%u) cts2s_max_time(%u) dut_nav(%u) +1373,III,[ wal_coex_cts2s.c : 411 ] COEX_CTS2S_SEND: Dur(%u) Time2Discard(%u) CurrTime(%u) +1372,III,[ wal_coex_cts2s.c : 295 ] WAL_COEX_TRF_CTS2: T2NonWlan(%u) Now(%u) Now+NonWlanDuration(%u) +1396,I,[ wal_coex_bt.c : 2779 ] COEX_GENERIC_ERROR: ACL Active SCO Timer expired ! AclActiveScoTimerState = 0x%x +1395,IIII,[ wal_coex_bt.c : 1332 ] WAL_COEX_BT_ALLOC: Ret(%u) LocalId(%u) Remote_Id(%u) MinFreeLinkId(%u) +1394,III,[ wal_coex_bt.c : 1350 ] WAL_COEX_BT_DEALLOC: LocalId(%u) Remote_Id(%u) MinFreeLinkId(%u) +1393,IIIIIIII,[ wal_coex_bt.c : 2356 ] WAL_COEX_SCHED_INTERVAL: Error(0x%x) Warn(0x%x) bt_grant(%u) bt_duration(%u) interval(%u) bt_traffic_status(%u) is_bt_heavy(%u) WlanScanType(%u) +1392,IIiII,[ wal_coex_bt.c : 1734 ] WAL_COEX_PROC_GPM: Error(0x%x) Warn(0x%x) status(%d) type(%u) subtype(%u) +1391,II,[ wal_coex_bt.c : 927 ] COEX_MCI_RECOVER: StimulusState(0x%x) RecoveryState(0x%x) +1390,I,[ wal_coex_bt.c : 882 ] COEX_MCI_TIMER_HANDLER: Recovery(0x%x) +1389,II,[ wal_coex_bt.c : 721 ] COEX_WAL_PAUSE_RESUME: Pause(%u) State(0x%x) +1388,IIIII,[ wal_coex_bt.c : 2157 ] COEX_BT_INTERVAL_START: Error(0x%x) Warn(0x%x) bt_intrvl_cnt(%u) duration(%u) enable_bt_bw_lim(%u) +1387,II,[ wal_coex_bt.c : 2194 ] COEX_WLAN_POSTPAUSE_INTERVAL_START: Dur(%u) Wght(%u) +1386,IIII,[ wal_coex_bt.c : 2176 ] COEX_WLAN_INTERVAL_START: Error(0x%x) Warn(0x%x) wlan_intrvl_cnt(%u) duration(%u) +1385,IIII,[ wal_coex_bt.c : 775 ] COEX_UPDATE_AFH: IsAdd(%u) Freq(%u), 2G(%u) HT20(%u) +1384,ii,[ wal_coex_bt.c : 2246 ] COEX_BT_RXSS_THRES: NewRSSI(%d) 1 LowerThresh(%d) +1383,III,[ wal_coex_bt.c : 1592 ] COEX_BT_PRIO_BUDGET: idle(%u) low(%u) hi(%u) +1382,Ii,[ wal_coex_bt.c : 3092 ] WAL_COEX_GPM_RECV: Subtype[0x%x] is not present in bt2wlan_gpm_indx entries or field index[%d] exceeding +1381,IIIIIIII,[ wal_coex_bt.c : 2992 ] WAL_COEX_GPM_RECV: subtype[0x%x] timer(%u) F1(0x%lx) F2(0x%lx) F3(0x%lx) F4(0x%lx) F5(0x%lx) F6(0x%lx) +1380,I,[ wal_coex_bt.c : 3017 ] WAL_COEX_GPM_RECV: Subtype[0x%x] is not present in bt2wlan_gpm_indx entries +1379,IIII,[ wal_coex_bt.c : 3031 ] WAL_COEX_GPM_RECV: type[0x%x] subtype[0x%x] timer[%u], wbtime(%u) +1378,IIIII,[ wal_coex_bt.c : 3038 ] WAL_COEX_GPM_RECV: type[0x%x] timer[%u]: [BT 5g tx chain1] status[0x%x] dutyCycle[%u] threshold[%u] +1377,III,[ wal_coex_bt.c : 3045 ] COEX_INVALID_GPM: type[0x%x] subtype[0x%x] timer[%u] : [Unknown GPM type subtype] +1376,IIIII,[ wal_coex_bt.c : 3000 ] WAL_COEX_GPM_RECV: subtype[0x%x] F7(0x%lx) F8(0x%lx) F9(0x%lx) F10(0x%lx) +1375,IIIIIIII,[ wal_coex_bt.c : 3012 ] WAL_COEX_GPM_RECV: subtype[0x%x] timer(%u) F1(0x%lx) F2(0x%lx) F3(0x%lx) F4(0x%lx) F5(0x%lx) F6(0x%lx) +1404,III,[ wal_coex_bt_gpm_handler.c : 1651 ] WAL_COEX_BTPROF_ADD: Status(%u) RemoteId(%u) ProfileType(%u) +1403,I,[ wal_coex_bt_gpm_handler.c : 1511 ] WAL_COEX_BTQ: Overflow(%u) +1402,I,[ wal_coex_bt_gpm_handler.c : 897 ] COEX_GENERIC_ERROR: SCO/RVP link entered PWR_SAVE state. AclActiveScoTimerState = 0x%x +1401,I,[ wal_coex_bt_gpm_handler.c : 910 ] COEX_GENERIC_ERROR: SCO/RVP link entered ACTIVE state. AclActiveScoTimerState = 0x%x +1400,I,[ wal_coex_bt_gpm_handler.c : 454 ] WAL_COEX_STATUS_UPDATE: No record for existing link (%u) +1399,II,[ wal_coex_bt_gpm_handler.c : 1270 ] WAL_COEX_BT_CSB: Type(%u) Id(%u) +1398,III,[ wal_coex_bt_gpm_handler.c : 1679 ] WAL_COEX_BTPROF_DEL: Status(%u) RemoteId(%u) ProfileType(%u) +1397,III,[ wal_coex_bt_gpm_handler.c : 352 ] WAL_COEX_BT_DEL_PROF: Invalid link: Type(%u) State(0x%x), id(%u) +1405,iIII,[ wal_coex_bt_utils.c : 222 ] WAL_COEX_TRAF_STAT: traf_status(%d). TxBW(0x%08x), RxBW(0x%08x), intvl(0x%08x) +1410,,[ wal_coex_btle.c : 357 ] WAL_COEX_LE_ADV_RX: LE Adv Rx Timer Expired +1409,IIIIIII,[ wal_coex_btle.c : 254 ] WAL_COEX_LE_LR: status(%u) state(0x%x) cmd_status(0x%x) local_id(%u) remote_id(%u) max_tx(%u) max_rx(%u) +1408,IIIIII,[ wal_coex_btle.c : 181 ] WAL_COEX_LE_LR: state(0x%x) write(%u) local_id(%u) remote_id(%u) max_tx(%u) max_rx(%u) +1407,III,[ wal_coex_btle.c : 300 ] WAL_COEX_LE_ASHA: result(%u) curr(%u) prev(%u) +1406,IIIII,[ wal_coex_btle.c : 341 ] WAL_COEX_LE_ASHA: result(%u) id(%u) offset(%u) thresh(%u) is_asha(%u) +1415,II,[ wal_coex_utils.c : 590 ] COEX_GENERIC_ERROR: id(%u) isPaused(%u) +1414,ii,[ wal_coex_utils.c : 1472 ] WAL_COEX_GET_DATA: Datatype : (%d) | inparam : (%d) is NULL +1413,,[ wal_coex_utils.c : 1971 ] WAL_COEX_TLV_CONTROL: Coex TLV Control commands only enabled on HMT1.0 +1412,IIIII,[ wal_coex_utils.c : 1171 ] COEX_FORCE_OCS: wlan_dur(%u) bt_dur(%u) wlan_wght(%u) bt_wght(%u) algo(%u) +1411,i,[ wal_coex_utils.c : 990 ] COEX_FORCED_WGHT: en_force_pkt_prio:%d +1424,IIIIIIII,[ wal_coex_wghts.c : 1135 ] COEX_SET_COEX_WEIGHT: wght_grp(%u) reason(%u) wlan_idle(%u) [hid_con_tx_o|bcon_tx_o|bcon_rx_o](0x%03x) prio_wlan_fc(%u) flow_ctrl(0x%x) concur_tx(%u) BcnTxPrioEn(%u) +1423,I,[ wal_coex_wghts.c : 1137 ] COEX_SET_COEX_WEIGHT: Invalid wght_grp(%u) +1422,iii,[ wal_coex_wghts.c : 1513 ] WAL_COEX_FORCED_WGHTS: frame_type(%d), wlan_dur_wght(%d), bt_dur_wght(%d) +1421,iiiiiiii,[ wal_coex_wghts.c : 1420 ] WAL_COEX_WGHTS: Static: W0[wl_idle(%d) sw_ctrl3(%d) sw_ctrl2(%d) sw_ctrl1(%d)] W1[sw_ctrl0(%d) wait_bcn(%d) wait_ack_cts(%d) selfgen(%d] +1420,iiiiiiii,[ wal_coex_wghts.c : 1434 ] WAL_COEX_WGHTS: FES Tx: W2[bcn(%d) conn(%d) scan(%d) ibss(%d)] W3[psp(%d) bar(%d) cts(%d) data_VI(%d)] +1419,iiiiiiii,[ wal_coex_wghts.c : 1444 ] WAL_COEX_WGHTS: FES Tx: W4[null(%d) data_BE(%d) data_VO(%d) data_BK(%d)] W5[om(%d) oc(%d) od(%d) oo(%d)] +1418,iiiiiiii,[ wal_coex_wghts.c : 1477 ] WAL_COEX_WGHTS: FES Rx: W6[bcn(%d) conn(%d) scan(%d) ibss(%d)] W7[psp(%d) bar(%d) cts(%d) rsvd(%d)] +1417,iiiiiiii,[ wal_coex_wghts.c : 1487 ] WAL_COEX_WGHTS: FES Rx: W8[null(%d) data(%d) qos(%d) rsvd(%d)] W9[om(%d) oc(%d) od(%d) oo(%d)] +1416,iiii,[ wal_coex_wghts.c : 1423 ] WAL_COEX_WGHTS: Static: W10[rx_lvl3(%d) rx_lvl2(%d) rx_lvl1(%d) (%d)] +1430,I,[ wal_coex_wlan.c : 407 ] COEX_CHANNEL_CHANGE: Invalid pdev_id %u was passed +1429,iii,[ wal_coex_wlan.c : 112 ] COEX_DHCP_TMR_EXPIRED: DHCP tmr expired: DHCP flag (%d), DHCP Detected (%d) vdev_id(%d) +1428,ii,[ wal_coex_wlan.c : 1292 ] COEX_MWS_ANT_DIVERSITY: Entering FAS opmode %d, vdevid %d +1427,IIIIIIII,[ wal_coex_wlan.c : 354 ] WAL_COEX_BAND_CHANGE: status(%u) band_changed(%u) single_mac(%u) mac(%u) 2x2(%u) new_freq(%u) cur_band(%u) cxc(0x%x) +1426,III,[ wal_coex_wlan.c : 505 ] BTCOEX_DBG_MCI_2: wal_coex_reassess_wlanstate - mac(%u) band(%u) state(0x%x) +1425,IIIIIIIII,[ wal_coex_wlan.c : 919 ] WAL_COEX_VDEV_STATE: Error(0x%x) id(%u) stimulus(%u) vdev_state(0x%x) strict_dur_scan(%u) num_peers(%u) pdev(%u) chan(%u) [op|subop](0x%02x) +1445,iIIIi,[ wal_coex_sched.c : 1681 ] COEX_GET_T2BT: status(%d) t2bt(%u) sched_time(%u) curr_time(%u) duration(%d) +1444,,[ wal_coex_sched.c : 955 ] COEX_EXIT_OCS: Error - Switching to FREE_RUN for 10msecs due to ENTER_DYNAMIC_OCS failure +1443,,[ wal_coex_sched.c : 1222 ] COEX_EXIT_OCS: Error - Switching to FREE_RUN for 10msecs due to UPDATE_OCS failure +1442,,[ wal_coex_sched.c : 1245 ] COEX_EXIT_OCS: Error - Switching to FREE_RUN for 10msecs due to ENTER_OCS failure +1441,IIIIIII,[ wal_coex_sched.c : 1614 ] WAL_COEX_SCHEDULER: Error(0x%x) status(%u) sched_req(%u) mngr_policy(%u) next_intrvl(%u) coex_mac(%u) sched_algo(%u) +1440,IIIIIIIII,[ wal_coex_sched.c : 775 ] COEX_TRF_SHAPE_OCS: interval(%u) Dur(%u) Latency(%u) VdevPauseDelay(%u) ConcurrState(0x%x) nonlinkExtraIntervals(%u) wlan_2g(%u) a2dp_crit(%u) bt_qos_pct(%u) +1439,ii,[ wal_coex_sched.c : 2284 ] COEX_SET_WEIGHT_GROUP3: Setting coex weight group 3 BT hasn't been non-critical pCoexDev->DynamicOcsSchedReq = %d pBtCoexWeightDev->resetWtVdevPause= %d +1438,ii,[ wal_coex_sched.c : 2305 ] COEX_SET_WEIGHT_GROUP3: Else part pCoexDev->DynamicOcsSchedReq = %d pBtCoexWeightDev->resetWtVdevPause= %d +1437,i,[ wal_coex_sched.c : 2296 ] COEX_SET_WEIGHT_GROUP6: Setting coex weight group six pCoexDev->DynamicOcsSchedReq %d +1436,IIIIII,[ wal_coex_sched.c : 387 ] COEX_TRF_FREERUN: NextIntvl(%u) SchedIntvl(%u) AllocatedBtIntervals(%u) BtIntervalCnt(%u) AllocatedWlanIntervals(%u) WlanIntervalCnt(%u) +1435,IIII,[ wal_coex_sched.c : 109 ] COEX_TRF_FREERUN_FTM: NextIntvl(%u) SchedIntvl(%u) BtIntervalCnt(%u) WlanIntervalCnt(%u) +1434,IIIII,[ wal_coex_sched.c : 594 ] COEX_TRF_SHAPE_OCS: interval(%u) Dur(%u) Latency(%u) ConcurrState(0x%x) wlan_2g(%u) +1433,IIIIII,[ wal_coex_sched.c : 1894 ] COEX_TRF_SHAPE_PSP: Error(0x%x) NextInterval(%u) wght(%u) IntrvalDur(%u) BtTriggerRecieved(%u) IS_PSP_ALG_WLAN_CRITICAL(%u) +1432,II,[ wal_coex_sched.c : 2449 ] WAL_COEX_GET_INTERVAL: GET: OCS_Duration(%u) OCS_Interval(%u) +1431,II,[ wal_coex_sched.c : 2458 ] WAL_COEX_SET_INTERVAL: SET: OCS_Duration(%u) OCS_Interval(%u) +1446,IIII,[ wal_coex_policy.c : 1031 ] WAL_COEX_ALGO: algo(%u) prev_algo(%u) [ftm|sep_ant|lte|nan|a2dp|hid|aptx_ll|voice](0x%08x), [wlan_ll|asha|ba|ant|not_conn|mpta_hlpr|force_pol](0x%08x) +1451,i,[ wal_coex_ftm.c : 145 ] WAL_COEX_FTM: wal_coex_ftm.c LINE=%d FTM_CAL_START +1450,iii,[ wal_coex_ftm.c : 186 ] WAL_COEX_FTM: wal_coex_ftm.c LINE=%d FTM_TX_RX_STOP state=%d chan=%d +1449,i,[ wal_coex_ftm.c : 154 ] WAL_COEX_FTM: wal_coex_ftm.c LINE=%d FTM_CAL_STOP +1448,iii,[ wal_coex_ftm.c : 163 ] WAL_COEX_FTM: wal_coex_ftm.c LINE=%d FTM_TX_RX_START state=%d, chan=%d +1447,i,[ wal_coex_ftm.c : 46 ] WAL_COEX_FTM: wal_coex_ftm.c LINE=%d FTM_INIT +1458,ii,[ wal_coex_pta.c : 86 ] COEX_PTA_ENABLE: [AP] coex enable.. en_coex = %d, dis_bttx_concurrency = %d +1457,Iii,[ wal_coex_pta.c : 238 ] COEX_WAL_PTA_COEX_INIT: bdf_flag(0x%x), pta_feature_enabled(%d), disableBTTxConcurrency(%d) +1456,iIIIII,[ wal_coex_pta.c : 247 ] COEX_WAL_PTA_COEX_INIT: pta_num(%d) ,pta_mode(0x%x) first_slot_time(0x%x) bt_priority_time(0x%x) pta_algo(0x%x) pta_priority(0x%x) +1455,iIIIII,[ wal_coex_pta.c : 259 ] COEX_WAL_PTA_COEX_INIT: pta_num(%d) pta_mode(0x%x) first_slot_time(0x%x) bt_priority_time(0x%x) pta_algo(0x%x) pta_priority(0x%x) +1454,iiii,[ wal_coex_pta.c : 207 ] COEX_GENERIC_ERROR: [AP] Either Invalid Duty Cycle or OCS not Configured.Current duty_cycle:(%d),wlan_duration:(%d),pta0_algo:(%d), pta1_algo:(%d) +1453,,[ wal_coex_pta.c : 210 ] COEX_GENERIC_ERROR: Failed To Enable Coex. CXC HW Module not Powered Up +1452,,[ wal_coex_pta.c : 224 ] COEX_GENERIC_ERROR: Either Invalid 2G MacID or 2G Mac is not Enabled +1461,IIIIII,[ wal_coex_power.c : 761 ] WAL_COEX_POWER_CHANGE: Error(0x%x) mac(%u) event_type(%u) cur_state(0x%x) new_state(0x%x) all_mac_sleeping(%u) +1460,i,[ wal_coex_power.c : 766 ] WAL_COEX_POWER_CHANGE: Invalid wlan_id from power event, wlan_id=%d +1459,i,[ wal_coex_power.c : 505 ] COEX_POWER_CHANGE: PHY is ON - Coex recipe change is best effort. mac_id(%d) +1466,iiiiii,[ wal_coex_stats.c : 42 ] COEX_STATS_PDG_CNTRS: COEX STATS PDG CNTRS Ant %d Mcs %d Pwr %d Bw %d TxWin %d RxWin %d +1465,iiiiiiii,[ wal_coex_stats.c : 90 ] COEX_STATS_CONC_CNTRS: tx_status_fes_tx_end_cntr %d tx_status_fes_tx_start_cntr %d, tx_flush_cntr %d tbtt_cntr %d, wl_in_tx_abort_cntr %d wl_tx_auto_resp_req_cntr %d, wl_tx_req_ack_cntr %d wl_tx_req_cntr %d +1464,i,[ wal_coex_stats.c : 96 ] COEX_STATS_BT: Invalid mac ID %d +1463,iiiiiiii,[ wal_coex_stats.c : 62 ] COEX_STATS_CONC_CNTRS: bt_tx_req_cntr %d bt_rx_req_cntr %d concurrent_bt_rx_wl_rx_cntr %d concurrent_bt_tx_wl_rx_cntr %d concurrent_bt_rx_wl_tx_cntr %d concurrent_bt_tx_wl_tx_cntr %d tx_status_resp_tx_start_cntr %d tx_status_fes_end_cntr %d +1462,iiiiiiii,[ wal_coex_stats.c : 76 ] COEX_STATS_CONC_CNTRS: wl_tx_req_nack_schd_bt_reason_cntr %d wl_tx_req_nack_current_bt_reason_cntr %d, wl_tx_req_nack_other_wlan_tx_reason_cntr %d wl_tx_req_nack_lcmh_reason_cntr %d, tx_resp_concurrent_wlan_tx_cntr %d tx_resp_alt_based_cntr %d, tx_resp_default_based_cntr %d tx_status_resp_tx_end_cntr %d +1470,I,[ wal_coex_cal.c : 296 ] COEX_POLL_BT_CAL_DONE_TIMEOUT: BtCalState(0x%x) +1469,III,[ wal_coex_cal.c : 86 ] COEX_RX_MCI_GPM_BT_CAL_MSG: OpCode(0x%x) WlanCalState(0x%x) BtCalState(0x%x) +1468,IIII,[ wal_coex_cal.c : 243 ] COEX_WLAN_CAL_END: caltype: %u, BtCalState(0x%x) WlanCalState(0x%x), mhz: %u +1467,IIII,[ wal_coex_cal.c : 185 ] COEX_WLAN_CAL_START: caltype: %u, BtCalState(0x%x) WlanCalState(0x%x), mhz: %u +1501,III,[ wal_coex_gpm.c : 225 ] WAL_MCI_GPM_SENT: UpdatePendingFlag - pending_msg_bm (0x%08x), QFlags (0x%08x) gpm_ack_bm (0x%08x) +1500,IIIIIIIII,[ wal_coex_gpm.c : 562 ] WHAL_MCI_GPM_SENT: [0x%x] [0x%x]- WLAN Conn Status Report : chain0_5g(0x%x) chain0_2g(0x%x) chain1_5g(0x%x) chain1_2g(0x%x) operating_mode(0x%x) wlm(0x%x) coexLL (%u) +1499,IIII,[ wal_coex_gpm.c : 699 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - WLAN set ACL Inactivity Report : InactivityThresh(0x%x) LinkID(0x%x) +1498,IIIIIII,[ wal_coex_gpm.c : 578 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x]- WLAN Unused channels : 0x%x 0x%x 0x%x 0x%x 0x%x +1497,IIII,[ wal_coex_gpm.c : 1147 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - ASD Status Indication: grant(%u) reason(%u) +1496,III,[ wal_coex_gpm.c : 1053 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Start BT RSSI Reporting: period(0x%x)second +1495,IIII,[ wal_coex_gpm.c : 919 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - BT Airtime Stats Req: NumOfDelivery(0x%x) TestInterval(0x%x) +1494,IIII,[ wal_coex_gpm.c : 649 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - BT Update flags : Opcode(0x%x) BT Flags(0x%x) +1493,III,[ wal_coex_gpm.c : 1032 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Limit BT Max TX power : power(0x%x)dbm +1492,IIIII,[ wal_coex_gpm.c : 679 ] WAL_MCI_GPM_SENT: OBSOLETE[0x%x] [0x%x] - BT Pause profile : PauseSlot(0x%x) ProfileBitmap(0x%x) Data(0x%x) +1491,IIIII,[ wal_coex_gpm.c : 727 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - BT remote registry write : Address(0x%x) Value(0x%x) Op(0x%x) +1490,II,[ wal_coex_gpm.c : 745 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Query BT RXSS Minimum Threshold +1489,III,[ wal_coex_gpm.c : 766 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Set BT RXSS Minimum Threshold : Threshold(0x%x) +1488,IIIIII,[ wal_coex_gpm.c : 601 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x]- Status Query : WLAN QueryType(0x%x) Source 0x%x pending_msg_bm (0x%x) pending_msg_ack_bm (0x%x) +1487,III,[ wal_coex_gpm.c : 1011 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Read BT TX power : LinkId(0x%x) +1486,I,[ wal_coex_gpm.c : 463 ] WAL_MCI_GPM_SENT: [0x%x] - CAL DONE +1485,I,[ wal_coex_gpm.c : 429 ] WAL_MCI_GPM_SENT: [0x%x] - CAL GRANT +1484,I,[ wal_coex_gpm.c : 446 ] WAL_MCI_GPM_SENT: GPM Sent [0x%x] - CAL REQ +1483,IIIIII,[ wal_coex_gpm.c : 1168 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Coex Policy Indication: policy(%u), grant_bt(%u) wlan_dur(%u), bt_dur(%u) +1482,III,[ wal_coex_gpm.c : 1075 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - concurrent TX on chain0(%u) +1481,IIII,[ wal_coex_gpm.c : 891 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Send group priority config : Op(0x%x) Priority(0x%x) +1480,III,[ wal_coex_gpm.c : 622 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Disable BT GPM : State(0x%x) +1479,IIIIII,[ wal_coex_gpm.c : 943 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - LE Data Len Req : op(%u) id(%u) max_tx(%u) max_rx(%u) +1478,IIIII,[ wal_coex_gpm.c : 827 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Send priority config : Op(0x%x) Priority(0x%x) IsRead(0x%x) +1477,IIIIII,[ wal_coex_gpm.c : 797 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - Sched info trigger : TriggerEnaNum(0x%x) TriggerType(0x%x) LowerBound(0x%x) UpperBound(0x%x) +1476,IIIIIII,[ wal_coex_gpm.c : 492 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x]- Version query Major(0x%x) Minor(0%x) Cap_cfg(0x%x) pending_msg_bm (0x%x) pending_msg_ack_bm (0x%x) +1475,IIIII,[ wal_coex_gpm.c : 517 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - WLAN Version resp. : Major(0x%x) Minor(0x%x) Cap_cfg(0x%x) +1474,IIIIII,[ wal_coex_gpm.c : 1127 ] WHAL_MCI_GPM_SENT: [0x%x] [0x%x] WLAN Capabilities ctr(0x%x) cap W1(0x%x) cap W2(0x%x) cap B3(0x%x) +1473,III,[ wal_coex_gpm.c : 991 ] WAL_MCI_GPM_SENT: [0x%x] [0x%x] - WLAN Status Update : Status(0x%x) +1472,I,[ wal_coex_gpm.c : 1222 ] WHAL_MCI_GPM_SENT: GAIN Id error(0x%x) +1471,III,[ wal_coex_gpm.c : 1240 ] WHAL_MCI_GPM_SENT: [0x%x] [0x%x] - SET BT GAIN Id(0x%x) +1503,IIIIIII,[ wal_coex_dbs.c : 130 ] WAL_COEX_MODE_CHANGE: new_mode(%u) old_mode(%u) band_mac_map(0x%x) mac0_settings(0x%x) mac1_settings(0x%x) mac0_2x2(%u) mac1_2x2(%u) +1502,III,[ wal_coex_dbs.c : 240 ] WAL_COEX_VDEV_STATE: COEX_VDEV_MIGRATE: old_mac_id %u, new_mac_id %u, old_mac_pwr_state %u +1504,Ii,[ wal_coex_asd.c : 80 ] WAL_COEX_ASD: Status mismatch: bt_status(0x%x) prev_grant(0x%d) +1511,,[ wal_cold_boot_cal.c : 485 ] cold boot cal start +1510,ii,[ wal_cold_boot_cal.c : 553 ] Cold Boot Cal, 8 second timeout: actual time taken = %d, coexFlags = %d +1509,iiiii,[ wal_cold_boot_cal.c : 610 ] CBC:: pdev %d phy_mode %d mhz %d freq1 %d freq2 %d +1508,I,[ wal_cold_boot_cal.c : 673 ] CBC:: Total time taken for CBC = %u us +1507,iI,[ wal_cold_boot_cal.c : 536 ] CBC:: phy mode %d cal duration so far %u us +1506,ii,[ wal_cold_boot_cal.c : 545 ] Cold Boot Cal, 4 second timeout: actual time taken = %d, coexFlags = %d +1505,i,[ wal_cold_boot_cal.c : 273 ] cold_boot_cal start time in USecs: %d +1522,iiiIIII,[ wal_concurrency.c : 551 ] tsf_alloc: pdev_id = %d vdev_id = %d type = %d tsf_id = 0x%x bss_id = 0x%x pdev_tsf_id_map = 0x%x pdev_bss_id_map = 0x%x +1521,iiIIIiII,[ wal_concurrency.c : 1012 ] staid_alloc: pdev_id = %d vdev_id = %d (%x.%x.%x) type = %d sta_id = 0x%x pdev_sta_id_map = 0x%x +1520,iiIIIiII,[ wal_concurrency.c : 1124 ] staid_free: pdev_id = %d vdev_id = %d (%x.%x.%x) type = %d sta_id = 0x%x pdev_sta_id_map = 0x%x +1519,ii,[ wal_concurrency.c : 1055 ] wal_concurrency_vdev_attach: vdev_id = %d defer_mac_addr_reg = %d +1518,iiiIIII,[ wal_concurrency.c : 860 ] tsf_free: pdev_id = %d vdev_id = %d type = %d tsf_id = 0x%x bss_id = 0x%x pdev_tsf_id_map = 0x%x pdev_bss_id_map = 0x%x +1517,iiIII,[ wal_concurrency.c : 1565 ] wal_vdev_add_random_mac_addr: pdev_id = %d vdev_id = %d spoof_mac=%x.%x.%x +1516,iiIII,[ wal_concurrency.c : 1607 ] wal_vdev_del_random_mac_addr: pdev_id = %d vdev_id = %d spoof_mac=%x.%x.%x +1515,IiiiIIII,[ wal_concurrency.c : 642 ] tsf_realloc (flag=0x%x): pdev_id = %d vdev_id = %d type = %d tsf_id = 0x%x bss_id = 0x%x pdev_tsf_id_map = 0x%x pdev_bss_id_map = 0x%x +1514,iiiII,[ wal_concurrency.c : 1495 ] wal_vdev_restore_mac: pdev_id = %d vdev_id = %d spoof_type = %d sta_id = 0x%x spoof_sta_id=0x%x +1513,iiIIIIII,[ wal_concurrency.c : 1514 ] wal_vdev_set_mac_addr: pdev_id = %d vdev_id = %d mac=%02x:%02x:%02x:%02x:%02x:%02x +1512,iiIIIiII,[ wal_concurrency.c : 1415 ] wal_vdev_set_spoofed_mac_addr: pdev_id = %d vdev_id = %d spoof_mac=%x.%x.%x spoof_type=%d sta_id = 0x%x spoof_sta_id=0x%x +1534,,[ ar_wal_soc_dev.c : 2349 ] _wal_soc_pkt_info_run_algo: No monitored phy mode or device in sleep mode, enabled pktlog. + +1533,iiiiii,[ ar_wal_soc_dev.c : 2404 ] pktlog from %d to %d: tx_msdu %d, threshold %d, tx_ppdu %d, threshold %d. + +1532,iiiiii,[ ar_wal_soc_dev.c : 2413 ] pktlog from %d to %d: rx_msdu %d, threshold %d, rx_ppdu %d, threshold %d. + +1531,iiiiiii,[ ar_wal_soc_dev.c : 2422 ] pktlog from %d to %d: tx_msdu %d, sum_msdu %d, threshold %d, sum_ppdu %d, threshold %d. + +1530,IIII,[ ar_wal_soc_dev.c : 2540 ] _wal_soc_register_pkt_info_handler 0x%x, 0x%x, 0x%x, 0x%x +1529,,[ ar_wal_soc_dev.c : 3467 ] wal_soc_set_gpio_with_txrx_abort: start to abort tx&rx. +1528,iiii,[ ar_wal_soc_dev.c : 3487 ] wal_soc_set_gpio_with_txrx_abort: mac_no=%d, tx_stop=%d, rx_stop=%d reset=%d +1527,ii,[ ar_wal_soc_dev.c : 769 ] wal_soc_set_mac_active: nss applied for mac0 - %d and %d +1526,iiiii,[ ar_wal_soc_dev.c : 807 ] wal_soc_set_mac_active: mhz=%d mac_id=%d tx_resumed=%d last_pdev_state=%d dpd_cal=%d +1525,i,[ ar_wal_soc_dev.c : 1124 ] wal_soc_switch_mode: Start switching to mode = %d +1524,iiii,[ ar_wal_soc_dev.c : 1148 ] wal_soc_switch_mode: mac_id=%d Tx/Rx chainmask: %d %d pdev_state = %d +1523,IIII,[ ar_wal_soc_dev.c : 2586 ] _wal_soc_unregister_pkt_info_handler 0x%x, 0x%x, 0x%x, 0x%x +1568,i,[ ar_wal_phy_dev.c : 6307 ] Carrier Config features: %d +1567,IIIIiiI,[ ar_wal_phy_dev.c : 1653 ] _wal_dev_reset: mode=%x reason=%x,c0=%lx,c1=%lx,inprog=%d,dis=%d,en=%x +1566,ii,[ ar_wal_phy_dev.c : 5070 ] SMART ANTENNA : config_enable : %d config_mode : %d + +1565,,[ ar_wal_phy_dev.c : 565 ] Data stall force reset condition met, cal fdmt +1564,,[ ar_wal_phy_dev.c : 568 ] Data stall force reset condition met +1563,iii,[ ar_wal_phy_dev.c : 609 ] DATA_STALL: Type=%d FAIL_CNT[%d]=%d +1562,i,[ ar_wal_phy_dev.c : 341 ] DATA_STALL detection: PAUSE, pdev_id:%d +1561,iii,[ ar_wal_phy_dev.c : 839 ] DATA_STALL monitor: TIMEOUT, pdev_id:%d pause_countdown:%d active_vdev_cnt:%d +1560,i,[ ar_wal_phy_dev.c : 3178 ] wal_pdev_flush_all_non_pause_tids: send msg to SCHED_ALGO, thread_id =%d + +1559,IIIIII,[ ar_wal_phy_dev.c : 5982 ] DISPLAY_TPC_STATS: ctl_array_type is %lu ctl_array_len is %lu d1 is %lu d2 is %lu d3 is %lu d4 is %lu +1558,,[ ar_wal_phy_dev.c : 6011 ] DISPLAY_TPC_STATS: CTL array contents do not match! +1557,,[ ar_wal_phy_dev.c : 6036 ] DISPLAY_TPC_STATS: CTL array contents do not match! +1556,II,[ ar_wal_phy_dev.c : 5857 ] DISPLAY_TPC_STATS: rate_array_type is %lu rate_array_len is %lu +1555,,[ ar_wal_phy_dev.c : 5881 ] DISPLAY_TPC_STATS: Rates array contents do not match! +1554,I,[ ar_wal_phy_dev.c : 5644 ] DISPLAY_TPC_STATS: wal_pdev_get_ctl_array_len totalSize = %lu +1553,I,[ ar_wal_phy_dev.c : 5669 ] DISPLAY_TPC_STATS: wal_pdev_get_rates_array_len: totalSize = %lu +1552,ii,[ ar_wal_phy_dev.c : 358 ] DATA_STALL: rssi:%d vdev_id:%d +1551,IIIIII,[ ar_wal_phy_dev.c : 5738 ] DISPLAY_TPC_STATS: reg_power_type is %lu reg_power_array_len is %lu d1 is %lu d2 is %lu d3 is %lu d4 is %lu +1550,,[ ar_wal_phy_dev.c : 5764 ] DISPLAY_TPC_STATS: Regulatory array contents do not match! +1549,,[ ar_wal_phy_dev.c : 5779 ] DISPLAY_TPC_STATS: Regulatory array contents do not match! +1548,,[ ar_wal_phy_dev.c : 5796 ] DISPLAY_TPC_STATS: Regulatory array contents do not match! +1547,,[ ar_wal_phy_dev.c : 5813 ] DISPLAY_TPC_STATS: Regulatory array contents do not match! +1546,III,[ ar_wal_phy_dev.c : 5595 ] DISPLAY_TPC_STATS: wmi_tpc_config tlv header is %lu, chanFreq is %lu, phyMode is %lu +1545,IIiIIIII,[ ar_wal_phy_dev.c : 5597 ] DISPLAY_TPC_STATS: maxAntennaGain is %lu twiceMaxRDPower is %lu userAntennaGain is %d powerLimit is %lu rateMax is %lu numTxChain is %lu cfgctl is %lu flags is %lu +1544,iiI,[ ar_wal_phy_dev.c : 3283 ] SU PPDU_DURATION %d AMSDU agg_type %d amsdu_factor %f +1543,iiI,[ ar_wal_phy_dev.c : 3284 ] MU PPDU_DURATION %d AMSDU agg_type %d amsdu_factor %f +1542,iII,[ ar_wal_phy_dev.c : 2816 ] WAL_DBGID_SET_POWER_STATE pdev = %d current = 0x%x desired = 0x%x +1541,iiI,[ ar_wal_phy_dev.c : 3438 ] SET_PDEV_PARAM: pdev_id=%d: param=%d value=0x%x +1540,I,[ ar_wal_phy_dev.c : 3568 ] SET_PDEV_PARAM: WAL_PDEV_PARAM_SCAN_RADIO_TX_ON_DFS value=0x%x +1539,,[ ar_wal_phy_dev.c : 3594 ] SET_PDEV_PARAM: TXPOWER_LIMIT2G Invalid Band/PowerLimit +1538,,[ ar_wal_phy_dev.c : 3606 ] SET_PDEV_PARAM: TXPOWER_LIMIT5G Invalid Band/PowerLimit +1537,i,[ ar_wal_phy_dev.c : 4030 ] SET_PDEV_PARAM: DATA_STALL flag param=%d +1536,ii,[ ar_wal_phy_dev.c : 5080 ] SMART ANTENNA : config_enable : %d rx_antenna : %d + +1535,i,[ ar_wal_phy_dev.c : 6274 ] VOW enable %d +1616,i,[ ar_wal_vdev.c : 967 ] start hwbmiss delay wake tmr, timeout:%d +1615,III,[ ar_wal_vdev.c : 7190 ] AWGN_INT_DBG bw = 0x%x ed = 0x%x gi = 0x%x + +1614,ii,[ ar_wal_vdev.c : 232 ] WAL_DBGID_VDEV_ADDR_REGISTER vdev_id = %d pdev_id = %d +1613,ii,[ ar_wal_vdev.c : 245 ] WAL_DBGID_VDEV_ADDR_UNREGISTER vdev_id = %d pdev_id = %d +1612,ii,[ ar_wal_vdev.c : 6958 ] wal_vdev_delete_all_peer_msg_hdlr: thread_id =%d, vdev_id=%d + +1611,ii,[ ar_wal_vdev.c : 6888 ] wal_vdev_delete_all_peer_resume: vdev = %d, delete_all_peer_in_progress %d + +1610,i,[ ar_wal_vdev.c : 6910 ] wal_vdev_delete_all_peer_resume: vdev = %d, set WAL_VDEV_DEL_ALL_PEER_CONF_FROM_LOCAL_FRAME_COMPL + +1609,iii,[ ar_wal_vdev.c : 6923 ] wal_vdev_delete_all_peer_resume: vdev = %d, thread_id = %d, msg_id = %d + +1608,iii,[ ar_wal_vdev.c : 6929 ] wal_vdev_delete_all_peer_resume: vdev = %d, thread_id = %d, msg_id = %d + +1607,iiiIi,[ ar_wal_vdev.c : 2427 ] wal_vdev_down pdev_id %d vdev_id %d vdev_type %d flags 0x%x cnt_per_opmode %d +1606,,[ ar_wal_vdev.c : 2526 ] AWGN_INT_DBG vdev_down clearing timer handler +1605,I,[ ar_wal_vdev.c : 4928 ] %s: NULL pointer + +1604,II,[ ar_wal_vdev.c : 425 ] flow_config: 0x%x 0x%x +1603,iiI,[ ar_wal_vdev.c : 7069 ] delete_all_peer wal_vdev_free_event_confirmation: vdev_id=%d, flag = %d, vdev_flag_mask = %x + +1602,iiiiiii,[ ar_wal_vdev.c : 7075 ] delete_all_peer wal_vdev_free_event_confirmation: vdev_id=%d, dbg_rt_del_all_peer_num=%d, dbg_be_del_all_peer_num=%d, dbg_tx_de_del_all_peer_num=%d, dbg_sched_del_all_peer_num=%d, dbg_tqm_del_all_peer_num=%d, dbg_conf_del_all_peer_num = %d + +1601,iii,[ ar_wal_vdev.c : 7091 ] delete_all_peer wal_vdev_free_event_confirmation DEL_ALL_PEER_DEL_CONF: vdev_id=%d, thread_id = %d, msg_id = %d + +1600,iii,[ ar_wal_vdev.c : 7102 ] vdev_id:%d, prev_channel:%d, current_channel=%d +1599,iIiiii,[ ar_wal_vdev.c : 5853 ] wal_vdev_migrate (%d, 0x%x): pdev %d->%d, active=%d/%d +1598,ii,[ ar_wal_vdev.c : 5674 ] _wal_vdev_migrate_bring_up: vdev_id = %d rssi_beacon = %d +1597,iIII,[ ar_wal_vdev.c : 5710 ] _wal_vdev_migrate_bring_up: vdev_id = %d cur_tsf_64 = 0x%x sta_bss_tstamp = 0x%x time_at_sta_bss_tstamp = 0x%x +1596,ii,[ ar_wal_vdev.c : 5587 ] _wal_vdev_migrate_tear_down: vdev_id = %d rssi_beacon = %d +1595,iII,[ ar_wal_vdev.c : 5602 ] _wal_vdev_migrate_tear_down: vdev_id = %d sta_bss_tstamp = 0x%x time_at_sta_bss_tstamp = 0x%x +1594,iIi,[ ar_wal_vdev.c : 370 ] wal_vdev_event_handler: vdev_id=%d event_type=0x%x remote_peer_count=%d +1593,,[ ar_wal_vdev.c : 204 ] peer_bitmap POOL ALLOC FAILURE +1592,ii,[ ar_wal_vdev.c : 5534 ] wal_vdev_post_migrate - old_pdev is %d, new_pdev is = %d +1591,ii,[ ar_wal_vdev.c : 5403 ] wal_vdev_pre_migrate - old_pdev is %d, new_pdev is = %d +1590,ii,[ ar_wal_vdev.c : 1353 ] wal_vdev_reconfig vdev_id %d tsf_id is %d +1589,iII,[ ar_wal_vdev.c : 2655 ] [ERP_PROTECTION]: ignore duplicate msg to enable prot from host ! param_val %d default profile 0x%x new profile 0x%x +1588,iII,[ ar_wal_vdev.c : 2680 ] [ERP_PROTECTION]: param_val %d default profile 0x%x new profile 0x%x +1587,ii,[ ar_wal_vdev.c : 2906 ] WAL_VDEV_PARAM_HE_RTS_THRESHOLD_TU: new_rts_thres=%d vdev_id=%d +1586,Ii,[ ar_wal_vdev.c : 3120 ] #### NEW_STATS MGMT_HDR_dbg monitor vdev %x packet_capture_mode %d #### +1585,i,[ ar_wal_vdev.c : 3131 ] #### stale_period_sec %d #### +1584,i,[ ar_wal_vdev.c : 3136 ] #### mcast_dra_enabled %d #### +1583,i,[ ar_wal_vdev.c : 3273 ] NON_QOS_STEER txbf_non_qos_enable %d +1582,iIII,[ ar_wal_vdev.c : 3764 ] WAL_DBGID_SETUP_RSSI_INTERRUPTS vdev_id = %d 0x%x 0x%x 0x%x +1581,iiii,[ ar_wal_vdev.c : 1796 ] wal_vdev_start vdev_id %d vdev_type %d vdev's mac %dbss_peer %d +1580,,[ ar_wal_vdev.c : 6445 ] _wal_vdev_state_publish: Entry +1579,ii,[ ar_wal_vdev.c : 6449 ] _wal_vdev_state_publish: bytes is %d, less than output size = %d +1578,i,[ ar_wal_vdev.c : 6456 ] _wal_vdev_state_publish: vdev_id_map %d +1577,i,[ ar_wal_vdev.c : 6461 ] _wal_vdev_state_publish: vdev %d +1576,ii,[ ar_wal_vdev.c : 6487 ] _wal_vdev_state_publish: vdev_type_state is %d, vdev_id_state = %d +1575,iiiiii,[ ar_wal_vdev.c : 6496 ] _wal_vdev_state_publish: mac_address is %d:%d:%d:%d:%d:%d +1574,,[ ar_wal_vdev.c : 6501 ] _wal_vdev_state_publish: Exit +1573,i,[ ar_wal_vdev.c : 1920 ] Spectral disabled as vdevs are zero: pdev:%d +1572,ii,[ ar_wal_vdev.c : 1937 ] wal_vdev_stop vdev_id %d vdev_type %d +1571,IIIIII,[ ar_wal_vdev.c : 2236 ] pdev(%x)peer %x,vdev-up for tidLen update,refcnt=%x,htc=%x,remap=%x,security=%x +1570,,[ ar_wal_vdev.c : 2356 ] AWGN_INT_DBG vdev_up: type AWGN Timer initialised + +1569,iiiIi,[ ar_wal_vdev.c : 2347 ] wal_vdev_up: pdev_id %d vdev_id %d, vdev_type %d flags 0x%x cnt_per_opmode %d +1617,,[ ar_wal_dev_init.c : 1290 ] wal_coex_init() +1665,i,[ wal_dfs.c : 1204 ] Clear NOL list %d +1664,,[ wal_dfs.c : 1207 ] 2G band : NOL is invalid +1663,ii,[ wal_dfs.c : 1218 ] removing NOL %d MHz / %d MHz +1662,i,[ wal_dfs.c : 387 ] DFS Domain=%d +1661,,[ wal_dfs.c : 959 ] DFS wal_dfs_disable_nol_tx_timeout_hdlr Blocking all tx activity Timer Triggered for 1 min +1660,iiiiii,[ wal_dfs.c : 747 ] seg=%d, sidx=%d, offset=%d, chirp=%d, phy_mode=%d, f=%d +1659,iiii,[ wal_dfs.c : 753 ] su_center_chan =%d ,freq1 = %d, freq2 = %d, offset=%d +1658,i,[ wal_dfs.c : 765 ] 20MHZ=%d +1657,i,[ wal_dfs.c : 773 ] 40MHZ=%d +1656,i,[ wal_dfs.c : 787 ] 80MHZ=%d +1655,i,[ wal_dfs.c : 790 ] channel phy_mode=%d is invalid +1654,ii,[ wal_dfs.c : 805 ] sub channel offset=%d, channel=%d +1653,iii,[ wal_dfs.c : 821 ] offset=%d, chan_freq=%d, f=%d +1652,I,[ wal_dfs.c : 446 ] b20MHZ=0x%x +1651,iiii,[ wal_dfs.c : 473 ] NOL - 80_80 MHz %d %d %d %d + +1650,I,[ wal_dfs.c : 487 ] b160MHZ=0x%x +1649,iiiiiiiii,[ wal_dfs.c : 505 ] 160 MHZ ADFS FW NOL - center freq %d %d %d %d %d %d %d %d %d +1648,iiiii,[ wal_dfs.c : 523 ] 165 MHz ADFS FW NOL Freq1 %d %d %d %d %d +1647,iiii,[ wal_dfs.c : 531 ] center_chan =%d ,freq1 = %d, freq2 = %d, phymode = %d +1646,I,[ wal_dfs.c : 452 ] b40MHZ=0x%x +1645,I,[ wal_dfs.c : 461 ] b80MHZ=0x%x +1644,i,[ wal_dfs.c : 402 ] current Channel in DFS=%d +1643,,[ wal_dfs.c : 1914 ] DFS_DBG wal_dfs_get_nol_elem dfs is NULL +1642,,[ wal_dfs.c : 1100 ] dfs is NULL +1641,,[ wal_dfs.c : 1105 ] adfs list is empty +1640,ii,[ wal_dfs.c : 1116 ] update NOL %d MHz / %d MHz +1639,iiIi,[ wal_dfs.c : 1147 ] new NOL channel %d MHz / %d MHz, %llu, threadid = %d +1638,,[ wal_dfs.c : 1153 ] failed to allocate memory for nol entry +1637,ii,[ wal_dfs.c : 1348 ] check NOL %d MHz / %d MHz +1636,,[ wal_dfs.c : 1361 ] NOL check Failed +1635,ii,[ wal_dfs.c : 1367 ] wal_dfs_nol_checknol: num %d, status=%d +1634,ii,[ wal_dfs.c : 1279 ] delete NOL %d MHz / %d MHz +1633,,[ wal_dfs.c : 1290 ] dfs_nol_count < 0 +1632,i,[ wal_dfs.c : 1239 ] FreeElem %d +1631,ii,[ wal_dfs.c : 1250 ] removing NOL %d MHz / %d MHz +1630,,[ wal_dfs.c : 1166 ] DFS_DBG wal_dfs_print_nol dfs is NULL +1629,iiiII,[ wal_dfs.c : 1182 ] DFS_DBG wal_dfs_print_nol nol:%d channel=%d MHz width=%d MHz time left=%u seconds nol starttick=%llu +1628,Ii,[ wal_dfs.c : 1184 ] DFS_DBG wal_dfs_print_nol timeout=%llu pdev_id %d +1627,ii,[ wal_dfs.c : 1670 ] DFS segment Id %d offset %d +1626,i,[ wal_dfs.c : 1686 ] Invalid num channels: %d +1625,I,[ wal_dfs.c : 1712 ] ch_freq=0x%x Added to NOL +1624,i,[ wal_dfs.c : 1861 ] res TX Status=%d +1623,i,[ wal_dfs.c : 1824 ] res SCHED Status=%d +1622,i,[ wal_dfs.c : 1795 ] res SCHED Status=%d +1621,ii,[ wal_dfs.c : 334 ] WAL_DFS_SCHED_SUSPEND_HNDLR thrd_id = %d pdev_id = %d +1620,II,[ wal_dfs.c : 354 ] %s: thread_id=%lx received DFS_SUSPEND msg + +1619,i,[ wal_dfs.c : 1767 ] sus TX Status=%d +1618,,[ wal_dfs.c : 877 ] DFS WAL_PDEV_PARAM_SET_USE_NOL command received, Triggered Timer +1672,I,[ wal_disa.c : 77 ] crc32_calc: CRC=0x%08x +1671,I,[ wal_disa.c : 434 ] tx_send_disa_frame: Seq No = 0x%x +1670,,[ wal_disa.c : 461 ] No MEMORY for DISA frame!!! +1669,i,[ wal_disa.c : 447 ] DISA HW configuration failed!!! Status=%d +1668,,[ wal_disa.c : 133 ] disa_frm_buf allocation failed...!!! +1667,ii,[ wal_disa.c : 136 ] disa_frm_buf allocation success...%d %d !!! +1666,,[ wal_disa.c : 369 ] _wal_disa_prepare_80211_frame: QoS frame with order bit set to 1 +1720,Ii,[ ar_wal_connection_pause.c : 2017 ] Tx_Pause: WAL_PEER_EVENT_SEND_N_COMPLETE sent: peer:0x%x, tid_num:%d +1719,,[ ar_wal_connection_pause.c : 3344 ] POOL ALLOC FAILURE +1718,,[ ar_wal_connection_pause.c : 3937 ] wal_tx_pause_alloc_handle POOL ALLOC FAILURE +1717,,[ ar_wal_connection_pause.c : 3031 ] Tx_Pause: ar_wal_tx_pause_check_pending_pdev_cmd_completions: (qpeer == NULL) +1716,IiiI,[ ar_wal_connection_pause.c : 3691 ] Tx_Pause: WAL_PEER_SEND_N_REQ rcvd: peer:0x%x, tidno:%d, num_frames:%d, flags:0x%x [No_Resp] +1715,i,[ ar_wal_connection_pause.c : 3737 ] Tx_Pause: WAL_VDEV_TX_PAUSE_RESET_IND rcvd: vdev_id:%d [No_Resp] +1714,Ii,[ ar_wal_connection_pause.c : 3748 ] Tx_Pause: WAL_TX_PAUSE_TID_CREATE rcvd: peer:0x%x, tid_num:%d [No_Resp] +1713,i,[ ar_wal_connection_pause.c : 3758 ] Tx_Pause: WAL_TX_PAUSE_VDEV_CREATE rcvd: vdev_id:%d [No_Resp] +1712,I,[ ar_wal_connection_pause.c : 3768 ] Tx_Pause: WAL_TX_PAUSE_PEER_RESET rcvd: peer:0x%x [No_Resp] +1711,i,[ ar_wal_connection_pause.c : 3778 ] Tx_Pause: WAL_TX_PAUSE_HWQ_EMPTY rcvd: tid_num:%d [No_Resp] +1710,i,[ ar_wal_connection_pause.c : 3788 ] Tx_Pause: WAL_CHECK_PENDING_CMDS_VDEV rcvd: vdev_id:%d [No_Resp] +1709,i,[ ar_wal_connection_pause.c : 3798 ] Tx_Pause: WAL_CHECK_PENDING_CMDS_PDEV rcvd: pdev_id:%d [No_Resp] +1708,i,[ ar_wal_connection_pause.c : 3806 ] Tx_Pause: unsupported no-resp request id:%d +1707,IiiI,[ ar_wal_connection_pause.c : 3727 ] Tx_Pause: WAL_PEER_PS_PRE_REQ rcvd: peer:0x%x, force_ps:%d, pm_ts:%d, paused_tidmask:0x%x [No_Resp] +1706,iiii,[ ar_wal_connection_pause.c : 3373 ] Tx_Pause: WAL_PDEV_TX_PAUSE_REQ rcvd: pdev_id:%d, module_id:%d, block:%d, filter:%d +1705,iii,[ ar_wal_connection_pause.c : 3402 ] Tx_Pause: WAL_PDEV_TX_UNPAUSE_REQ rcvd: pdev_id:%d, module_id:%d, block:%d +1704,i,[ ar_wal_connection_pause.c : 3422 ] Tx_Pause: unsupported pdev request id:%d +1703,IiIIii,[ ar_wal_connection_pause.c : 3584 ] Tx_Pause: req rcvd: peer:0x%x, mod_id:%d, tids_to_block:0x%x, tids_to_unblock:0x%x, filter:%d, requester_hw_link_id:%d +1702,IiIIi,[ ar_wal_connection_pause.c : 3625 ] Tx_Pause: req rcvd: 1st_peer:%u, module_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x, filter:%d +1701,i,[ ar_wal_connection_pause.c : 3651 ] Tx_Pause: unsupported peer request id:%d +1700,IiII,[ ar_wal_connection_pause.c : 2546 ] Tx_Pause: WAL_PEER_TX_PAUSE_UNPAUSE_COMPLETE sent: peer:0x%p, module_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x +1699,IiII,[ ar_wal_connection_pause.c : 2579 ] Tx_Pause: WAL_PEER_TX_BLOCK_UNBLOCK_COMPLETE sent: peer:0x%p, module_id:%d, tids_to_block:0x%x, tids_to_unblock:0x%x +1698,iii,[ ar_wal_connection_pause.c : 2609 ] Tx_Pause: WAL_VDEV_TX_PAUSE_COMPLETE sent: vdev_id:%d, module_id:%d, block:%d +1697,iii,[ ar_wal_connection_pause.c : 2636 ] Tx_Pause: WAL_VDEV_TX_UNPAUSE_COMPLETE sent: vdev_id:%d, module_id:%d, block:%d +1696,iii,[ ar_wal_connection_pause.c : 2663 ] Tx_Pause: WAL_PDEV_TX_PAUSE_COMPLETE sent: pdev_id:%d, module_id:%d, block:%d +1695,iii,[ ar_wal_connection_pause.c : 2690 ] Tx_Pause: WAL_PDEV_TX_UNPAUSE_COMPLETE sent: pdev_id:%d, module_id:%d, block:%d +1694,IiII,[ ar_wal_connection_pause.c : 2721 ] Tx_Pause: WAL_PEER_TX_PAUSE_UNPAUSE_EXT_COMPLETE sent: 1st_peer:0x%x, module_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x +1693,IiIIi,[ ar_wal_connection_pause.c : 2766 ] Tx_Pause: comp: peer:0x%x, mod_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x, requester_hw_link_id:%d +1692,IiIIi,[ ar_wal_connection_pause.c : 2780 ] Tx_Pause: comp: peer:0x%x, mod_id:%d, tids_to_block:0x%x, tids_to_unblock:0x%x, requester_hw_link_id:%d +1691,iii,[ ar_wal_connection_pause.c : 2791 ] Tx_Pause: WAL_VDEV_TX_PAUSE_REQ comp: vdev_id:%d, module_id:%d, block:%d +1690,iii,[ ar_wal_connection_pause.c : 2802 ] Tx_Pause: WAL_VDEV_TX_UNPAUSE_REQ comp: vdev_id:%d, module_id:%d, block:%d +1689,iii,[ ar_wal_connection_pause.c : 2813 ] Tx_Pause: WAL_PDEV_TX_PAUSE_REQ comp: pdev_id:%d, module_id:%d, block:%d +1688,iii,[ ar_wal_connection_pause.c : 2824 ] Tx_Pause: WAL_PDEV_TX_UNPAUSE_REQ comp: pdev_id:%d, module_id:%d, block:%d +1687,IiII,[ ar_wal_connection_pause.c : 2837 ] Tx_Pause: WAL_PEER_TX_PAUSE_UNPAUSE_EXT_REQ comp: 1st_peer:%u, module_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x +1686,iiii,[ ar_wal_connection_pause.c : 3445 ] Tx_Pause: WAL_VDEV_TX_PAUSE_REQ rcvd: vdev_id:%d, module_id:%d, block:%d, filter:%d +1685,iii,[ ar_wal_connection_pause.c : 3465 ] Tx_Pause: WAL_VDEV_TX_UNPAUSE_REQ rcvd: vdev_id:%d, module_id:%d, block:%d +1684,i,[ ar_wal_connection_pause.c : 3476 ] Tx_Pause: unsupported vdev request id:%d +1683,iiiI,[ ar_wal_connection_pause.c : 4076 ] tid_pause_data_stall tid_num:%d pause_module_id_map:%d block_module_id_map:%d peer:0x%x +1682,IIIII,[ ar_wal_connection_pause.c : 4134 ] PM_STATE_DBG: PEER_STATE: peer:0x%p, all_tids_pause_module_bitmap:0x%x, all_tids_block_module_bitmap:0x%x data_tids_pause_module_bitmap:0x%x, data_tids_block_module_bitmap:0x%x +1681,IiIIII,[ ar_wal_connection_pause.c : 4141 ] PM_STATE_DBG: TID_STATE: peer:0x%p, tid_num:%d, flags:0x%x, ext_flags:0x%x, pause_module_id_map:0x%x, block_module_id_map:0x%x +1680,IiIIi,[ ar_wal_connection_pause.c : 3513 ] Tx_Pause: req rcvd: peer:0x%p, mod_id:%d, tids_to_pause:0x%x, tids_to_unpause:0x%x, filter:%d +1679,I,[ ar_wal_connection_pause.c : 2376 ] Tx_Pause: Pdev event PEER_CREATE for peer:0x%x rcvd +1678,II,[ ar_wal_connection_pause.c : 771 ] Tx_Pause: wal_connection_pause_en_dis_ext: NULL peer list, mod=%u, is_en=%u +1677,II,[ ar_wal_connection_pause.c : 778 ] Tx_Pause: wal_connection_pause_en_dis_ext: (qpeer == NULL), mod=%u, is_en=%u +1676,,[ ar_wal_connection_pause.c : 356 ] qcache_peer is NULL +1675,,[ ar_wal_connection_pause.c : 314 ] qcache_peer is NULL +1674,,[ ar_wal_connection_pause.c : 335 ] qcache_peer is NULL +1673,i,[ ar_wal_connection_pause.c : 3853 ] Tx_Pause: unsupported request id:%d +1728,Iii,[ wal_avg_bmiss.c : 143 ] %p bcn_cnt:%d, bmiss_cnt:%d + +1727,I,[ wal_avg_bmiss.c : 167 ] %p enter high bmiss mode +1726,I,[ wal_avg_bmiss.c : 145 ] b:0x%08x + +1725,I,[ wal_avg_bmiss.c : 161 ] %p can't find vdev + +1724,Iii,[ wal_avg_bmiss.c : 198 ] %p bcn_cnt:%d, bmiss_cnt:%d + +1723,I,[ wal_avg_bmiss.c : 200 ] b:0x%08x + +1722,I,[ wal_avg_bmiss.c : 218 ] %p can't find vdev + +1721,I,[ wal_avg_bmiss.c : 226 ] %p enter low bmiss mode +1736,ii,[ wal_rc_peer.c : 2559 ] rx cck Stats publish :: input buffer size = %d ofdm stats buffer size = %d +1735,ii,[ wal_rc_peer.c : 2390 ] rx mcs 3d Stats publish :: input buffer size = %d 3d stats buffer size = %d +1734,iiI,[ wal_rc_peer.c : 2486 ] rx mcs Stats publish :: input buffer size = %d mcs stats buffer size = %d, nss:8/bw:8 0x%08x +1733,ii,[ wal_rc_peer.c : 2523 ] rx ofdm Stats publish :: input buffer size = %d ofdm stats buffer size = %d +1732,ii,[ wal_rc_peer.c : 2631 ] tx cck Stats publish :: input buffer size = %d ofdm stats buffer size = %d +1731,ii,[ wal_rc_peer.c : 2348 ] tx mcs 3d Stats publish :: input buffer size = %d 3d stats buffer size = %d +1730,iiI,[ wal_rc_peer.c : 2439 ] tx mcs Stats publish :: input buffer size = %d mcs stats buffer size = %d, nss:8/bw:8 0x%08x +1729,ii,[ wal_rc_peer.c : 2595 ] tx ofdm Stats publish :: input buffer size = %d ofdm stats buffer size = %d +1739,II,[ wal_rc_vdev.c : 655 ] RATECTRL_DBGID_WAL_SET_VDEV_DATA_RX: rc=0x%x data_rc=0x%x +1738,Ii,[ wal_rc_vdev.c : 222 ] RATECTRL_DBGID wal_vdev_set_non_data_rc_pdg_notify vdev non data notify rc %x phy_mode %d +1737,II,[ wal_rc_vdev.c : 129 ] RATECTRL_DBGID_WAL_SET_VDEV_UL_DATA_RC rc=0x%x data_rc=0x%x +1741,Iii,[ wal_rc_pdev.c : 2234 ] rate_sched:bw_mask:8/max_bw:8=0x%08x,flags=%d rix=%d +1740,iii,[ wal_rc_pdev.c : 791 ] SET tx_chain_mask[%d]: new=%d old=%d +1788,iii,[ wal_rtt.c : 178 ] Detected Outlier. i: %d rtt: %d bw: %d +1787,iiii,[ wal_rtt.c : 243 ] chain: %d cumilative_rtt_per_chain: %d, num_samples: %d min_mean_rtt: %d +1786,ii,[ wal_rtt.c : 2189 ] _wal_collect_report_info: pre %d bw %d +1785,IIi,[ wal_rtt.c : 1678 ] _wal_report_type2_buffer_done() buff = %p, curr: %p len: %d +1784,IIii,[ wal_rtt.c : 1661 ] _wal_report_type2_buffer_init buff = %p cur_p = %p chan = %d report_type = %d +1783,iiiiii,[ wal_rtt.c : 2367 ] _wal_report_type2_collect_report_info: total_time = %d num_frms = %d info1 = %d info2 = %d info3 = %d start_ts = %d +1782,IIi,[ wal_rtt.c : 2418 ] RTT_INITR_TSTAMP: t2= 0x%08x%08x fac= %d +1781,iIiiIIII,[ wal_rtt.c : 2478 ] _wal_report_type2_collect_report_info: rtt_ps: %d rssi=0x%x tx_preamble=%d tx_bw=%d tx_rate_info1 = 0x%x tx_rate_info2= 0x%x rx_rate_info1=0x%x, rx_rate_info2 = 0x%x +1780,IIiIIiiiI,[ wal_rtt.c : 2508 ] RTT_INITR_TSTAMP: t2=%u, t3=%u t3_del=%d t1=%u t4=%u t4_del=%d rtt=%d meas_count=%d num_rtt_per_frame_info_saved: %u +1779,IIII,[ wal_rtt.c : 2530 ] _wal_report_type2_collect_report_info: tx_rate_info1=0x%x, tx_rate_info2 =0x%x, rx_rate_info1=0x%x, rx_rate_info2=0x%x +1778,IIiIII,[ wal_rtt.c : 2556 ] RTT_INITR_TSTAMP: t2= 0x%08x%08x fac= %d rx_preamble=%u, rx_bw=%u rssi = 0x%x +1777,,[ wal_rtt.c : 2400 ] DISCARDING MEASUREMENT!! T3 not captured +1776,I,[ wal_rtt.c : 1874 ] _wal_report_type2_update_start_ts: start_ts(rtt_ctxt) start_ts(peer_head) %u +1775,III,[ wal_rtt.c : 1454 ] _wal_rtt_attach() pdev = %p rtt_pdev_ctxt = %p wal_rtt_ctxt = %p +1774,iiii,[ wal_rtt.c : 348 ] rtt_compute_distance num_meas: %d mean_rtt: %d median_rtt: %d distance_cm: %d +1773,iiiiiii,[ wal_rtt.c : 1960 ] wal_rtt_ctxt_clean: rxoffld_under_cnt: %d rxoffld_alloc_cnt: %d rxind_under_cnt: %d rxind_alloc_cnt: %d tm_rx_comp_cnt: %d rxoffld_drop_cnt: %d rxind_drop_cnt: %d +1772,iiiiII,[ wal_rtt.c : 1610 ] _wal_rtt_ctxt_init() :freq: %d is_qca: %d force_legacy_ack: %d enable_ht_vht_ack :%d self_mac: %08x%04x +1771,IIIIII,[ wal_rtt.c : 511 ] _wal_rtt_get_buffer_ptr:max_len:0x%x rem_len:0x%x reqd_len:0x%x buff:0x%x buf_p:0x%x cur_p:0x%x +1770,iIIIi,[ wal_rtt.c : 1484 ] _wal_rtt_init() pdev_id = %d rtt_ctxt: %p alloc_buff = %p buff = %p max_buff_len = %d +1769,I,[ wal_rtt.c : 2012 ] rtt_local_send() Not a valid rtt frame type, retrun error! txrx_cb_flags: 0x%x +1768,iIIIi,[ wal_rtt.c : 2075 ] _wal_rtt_local_frame_send_with_rate: acks%d tid_num 0x%x rate_info 0x%08x%08x report %d +1767,IIiiI,[ wal_rtt.c : 3640 ] _wal_rtt_mt_cb: msg:0x%x id:0x%x s_thr:%d d_thr:%d ticks:0x%x +1766,,[ wal_rtt.c : 2605 ] TX completion message was dropped. Report failure +1765,,[ wal_rtt.c : 2611 ] _wal_rtt_null_ack_hdl() is called after RTT session is completed !!! +1764,II,[ wal_rtt.c : 2618 ] Ignore NULL ack for stale entry: ath_buf: %p: last queued NULL frame ath_buf: %p +1763,iiiiiiii,[ wal_rtt.c : 384 ] index: %d count: %d rtt_ps: %d sum_rtt: %d tx_bw: %d, rx_bw: %d tx_ch_idx: %d rx_ch_idx: %d +1762,,[ wal_rtt.c : 2664 ] TX completion message was dropped. Report failure +1761,,[ wal_rtt.c : 2670 ] _wal_rtt_tm_ack_hdl() is called after RTT session is completed !!! +1760,II,[ wal_rtt.c : 2677 ] Ignore TM ack for stale entry: ath_buf: %p: last queued TM frame ath_buf: %p +1759,,[ wal_rtt.c : 2947 ] _wal_rtt_tm_rx_hdl: TM frame not directed to me. Don't process +1758,,[ wal_rtt.c : 2959 ] _wal_rtt_tm_rx_hdl: Not a valid TM frame. Don't process +1757,III,[ wal_rtt.c : 3066 ] _wal_rtt_tm_rx_hdl: rx_ts %10u now_ts %10u rx_proc_delay %10u +1756,i,[ wal_rtt.c : 3140 ] _wal_rtt_tm_rx_hdl: HT_VHT ack enable RTT_TM_FTM1 %d +1755,iii,[ wal_rtt.c : 3145 ] _wal_rtt_tm_rx_hdl: expect_token=%d, dia_token=%d, follow_token=%d +1754,IIII,[ wal_rtt.c : 3245 ] _wal_rtt_tm_rx_hdl: t1_32=0x%x, t1_0=0x%x, t4_32=0x%x, t4_0=0x%x +1753,II,[ wal_rtt.c : 3266 ] CFR/CIR report queue full; CFR/CIR data at 0x%04x%04x will be dropped +1752,i,[ wal_rtt.c : 3270 ] no CFR/CIR pending for report type %d +1751,iII,[ wal_rtt.c : 3277 ] CFR/CIR pending for report type %d; CFR/CIR data at 0x%04x%04x will be dropped +1750,,[ wal_rtt.c : 3420 ] wal_rtt_tx_ppdu_done(): rx_location_info is found to be invalid +1749,IIIIIIIIi,[ wal_rtt.c : 3625 ] _wal_rtt_tx_ppdu_done(%u-sided): abf: 0x0 tx_preamble=%u, retries=%u tod_32=%u tod_0=%u toa_32=%u toa_0=%u fac_valid: %u fac=%d +1748,II,[ wal_rtt.c : 3472 ] CFR/CIR report queue full; CFR/CIR data at 0x%04x%04x will be dropped +1747,i,[ wal_rtt.c : 3476 ] no CFR/CIR pending for report type %d +1746,iII,[ wal_rtt.c : 3483 ] CFR/CIR pending for report type %d; CFR/CIR data at 0x%04x%04x will be dropped +1745,II,[ wal_rtt.c : 3529 ] CFR/CIR report queue full; CFR/CIR data at 0x%04x%04x will be dropped +1744,i,[ wal_rtt.c : 3533 ] no CFR/CIR pending for responder report type %d +1743,iII,[ wal_rtt.c : 3540 ] CFR/CIR pending for responder report type %d; CFR/CIR data at 0x%04x%04x will be dropped +1742,ii,[ wal_rtt.c : 3768 ] wal_rtt_unit_test: debug_cnt[%d] = %d +1790,iII,[ wal_rtt_init.c : 83 ] _wal_rtt_psoc_init() wal_rtt_ctxt idx in rtt_psoc_handle: %d rtt_ctxt: %p alloc_buff_p: %p +1789,Iiii,[ wal_rtt_init.c : 92 ] _wal_rtt_psoc_init() psoc_rtt handle: %p sizes rtt_tx_pool: %d rtt_rx_pool handle: %d, rtt_rx_ofld_pool: %d +1792,iIIi,[ wal_cfir.c : 52 ] wal_cfir_resolve: pdev %d cfg 0x%08x => 0x%08x status %d +1791,I,[ wal_cfir.c : 95 ] wal_cfir_req_unregister: req %p already unregistered +1802,ii,[ wal_spectral.c : 399 ] Pdev id : %d WMI event with reset_delay %d +1801,iIIi,[ wal_spectral.c : 490 ] <%d>: WMI event called %p with %u buffers for module %d +1800,ii,[ wal_spectral.c : 548 ] out_ring reap : Before read shadow_tail_idx %d & After read shadow_tail_idx %d +1799,ii,[ wal_spectral.c : 584 ] SSCAN: cfg.ScanCountCopy %d cfg.ScanCount %d +1798,i,[ wal_spectral.c : 795 ] pdev_id = %d: spectral sig handler +1797,i,[ wal_spectral.c : 820 ] pdev_id = %d: spectral sig handler +1796,i,[ wal_spectral.c : 845 ] pdev_id = %d: spectral sig handler +1795,i,[ wal_spectral.c : 681 ] Resume SSCAN : pending elements in out_ring %d +1794,iiii,[ wal_spectral.c : 182 ] SSCAN_DUMP mac_id = %d: trigger = %d enable = %d scan_mode = %d +1793,I,[ wal_spectral.c : 194 ] SSCAN_DUMP: wal_spectral_scan_get_config called %p +1804,i,[ direct_dma_wmi.c : 212 ] pdev_id = %d: DMA is not attached +1803,i,[ direct_dma_wmi.c : 235 ] pdev_id = %d: DMA is not attached +1816,Iiii,[ wal_tx_common.c : 641 ] wal_peer_wow_null_per_stats_update: stats_start_time = 0x%x null_success = %d, null_fail = %d, cumulative_wake_time_ps_sta_ms = %d +1815,Ii,[ wal_tx_common.c : 51 ] WAL_DBGID_STA_KICKOUT: peer=0x%x consecutive_null_failure=%d +1814,iii,[ wal_tx_common.c : 55 ] WAL_DBGID_STA_KICKOUT: null_ppdu_fail_time:%dms delta:%dms vdev_type:%d +1813,iIiIIIIII,[ wal_tx_common.c : 705 ] WAL_DBGID_STA_KICKOUT: KICKOUT_REASON_NULL_PER_CHECK_FAILURE_TH null_per= %d% wake_per= %d% null_fail_count= 0x%x, null_pass_count= 0x%x cumulative_wake_time_ps_sta_ms= 0x%x , null_per_stats_start_time = 0x%x, curr_time= 0x%x +1812,iiIIIi,[ wal_tx_common.c : 178 ] consecutive_failure_reset : pdev=%d, vdev=%d, peer=0x%x, tid=0x%x (flags=0x%x), failure=%d -> 0 +1811,IIIIII,[ wal_tx_common.c : 371 ] tpc:16/rc_extended_flags:16 =0x%08x sch_cmd_result:0x%x flush_reason:0x%xfes_sched_try:0x%x fes_result:0x%x tsFlags:8/tsAttempts:8 0x%08x + +1810,IIIIiiIIi,[ wal_tx_common.c : 379 ] pdev_vdev_id=0x%x, peer=0x%x,tid=0x%x (flags=0x%x), consecutive failure=%d, kickout thresh=%d rate_code=0x%x, tsRate flags=0x%x, ppdu_mprot_type:%d +1809,IIIIIii,[ wal_tx_common.c : 383 ] pdev:8/vdev:8 =0x%08x, peer=0x%x,tid=0x%x (flags=0x%x %x), consecutive failure=%d, kickout thresh=%d +1808,IIiIIII,[ wal_tx_common.c : 417 ] pdev:8/vdev:8 0x%08x peer=0x%x consecutive_failure:%d cur_time:%x elapsed_ppdu_fail_time:%x tid_retryfailure:%x vdevtype:%x +1807,II,[ wal_tx_common.c : 509 ] WAL_DBGID_STA_KICKOUT 0x%x 0x%x +1806,IIII,[ wal_tx_common.c : 513 ] ppdu_fail_time:%x current_time:%x delta:%x type:%x +1805,III,[ wal_tx_common.c : 288 ] WAL_DBGID_XCESS_FAILURES %p 0x%x MAC:%x +1830,III,[ wal_wmm.c : 43 ] WMMAC_PAUSE_CB: peer=0x%x blocked tids=0x%x/0x%x +1829,Iiii,[ wal_wmm.c : 72 ] WMMAC_Q_REPRIO: peer=0x%x tid=%d qid:%d->%d +1828,iI,[ wal_wmm.c : 78 ] WMMAC_PAUSE_CB: unblock tid(%d)=0x%x +1827,Iiii,[ wal_wmm.c : 347 ] WMMAC_Q_DEPRIO: peer=0x%x tid=%d qid:%d->%d +1826,IiI,[ wal_wmm.c : 357 ] WMMAC_Q_DROP: peer=0x%x tid(%d)=0x%x +1825,Iiiiii,[ wal_wmm.c : 400 ] WMMAC_STATUS: peer=0x%x, used=%d, admitted=%d, txq_sts=%d/%d, downgrade=%d +1824,iIiii,[ wal_wmm.c : 431 ] WMMAC_TXQ_STATUS ac=%d txq_status=0x%02x used=%d admitted=%d downgrade=%d +1823,iiiII,[ wal_wmm.c : 115 ] WMMAC_ADD_DELTS: ac=%d admitted=%d acm=%d block=0x%x downgrade=0x%x +1822,iii,[ wal_wmm.c : 163 ] WMMAC_UPDATE: used_time=%d admitted_time=%d, downgrade=%d +1821,IIII,[ wal_wmm.c : 469 ] WMMAC_PERIODIC_UPDATE 0x%x 0x%x 0x%x 0x%x +1820,I,[ wal_wmm.c : 479 ] WMMAC_NO_DOWNGRADE: unblock tid mask=0x%x +1819,Iii,[ wal_wmm.c : 500 ] WMMAC_PERIODIC_UPDATE (VO): peer=0x%x, used=%d, admitted=%d +1818,Iii,[ wal_wmm.c : 510 ] WMMAC_PERIODIC_UPDATE (VI): peer=0x%x, used=%d, admitted=%d +1817,iii,[ wal_wmm.c : 188 ] WMMAC_USED_TIME_EXCEED: used=%d admitted=%d wmmac_q=%d +1849,ii,[ wlan_buf.c : 1048 ] MGMT buf get failure: mgmtbufCnt = %d, bsmall = %d +1848,ii,[ wlan_buf.c : 1080 ] MGMT buf get beacon: mac_id:%d, rsvd:%d +1847,I,[ wlan_buf.c : 1110 ] MGMT buf abf at start : 0x%x +1846,iii,[ wlan_buf.c : 1115 ] MGMT buf abf failure: smgmtbufCnt = %d, bsmall = %d mgmtBufCnt = %d +1845,Ii,[ wlan_buf.c : 1122 ] Remove MGMT buf from start abf : 0x%x, mgmtBufCnt : %d +1844,IiiiI,[ wlan_buf.c : 1139 ] MGMT buf get success: abf = 0x%x mgmtBufCnt =%d smgmtbuffcnt = %d bsmall = %d,flags = 0x%x +1843,,[ wlan_buf.c : 1228 ] wlan_buf_mac_buffer_dispatcher no buffers available in chain +1842,i,[ wlan_buf.c : 1241 ] wlan_buf_mac_buffer_dispatcher mac_id=%d + +1841,,[ wlan_buf.c : 1244 ] wlan_buf_mac_buffer_dispatcher oops +1840,,[ wlan_buf.c : 1256 ] wlan_buf_mac_buffer_dispatcher oops +1839,Ii,[ wlan_buf.c : 485 ] MGMT buf allocation auth_buf :0x%x , mgmtBufCnt : %d +1838,IiI,[ wlan_buf.c : 828 ] buf free: free the reused abf:0x%x, thread:%d, cb flags:0x%x +1837,Ii,[ wlan_buf.c : 895 ] MGMT buf returned to the mgt pool : abf:0x%x, mgmtBufCnt: %d +1836,iIiiI,[ wlan_buf.c : 906 ] MGMT buf free,small:%d,abf:0x%x,thread:%d,bufCnt:%d,caller:%x +1835,IiIi,[ wlan_buf.c : 836 ] free beacon abf:0x%x, thread:%d, cb flags:0x%x,rsvd:%d +1834,iIii,[ wlan_buf.c : 881 ] SMGMT buf free,small:%d,abf:0x%x,thread:%d,bufCnt:%d +1833,i,[ wlan_buf.c : 1289 ] wlan_buf_rxbuf_requeue mac_id=%d + +1832,,[ wlan_buf.c : 1294 ] wlan_buf_mac_buffer_dispatcher oops +1831,,[ wlan_buf.c : 1320 ] wlan_buf_mac_buffer_dispatcher oops +1853,ii,[ mu_gid_mgmt.c : 98 ] 11ac MU-MIMO GID MGMT: user successfully assigned completed: SW_PEER_ID: %d, mu_user_id: %d +1852,iii,[ mu_gid_mgmt.c : 116 ] 11ac MU-MIMO GID MGMT: Send GID MGMT failed. SW_PEER_ID: %d, mu_user_id: %d, status: %d +1851,iiIIIIII,[ mu_gid_mgmt.c : 162 ] 11ac MU-MIMO GID MGMT: Sending GID MGMT frame: SW_PEER_ID: %d, mu_user_id: %d, grp_status[0]: 0x%08x, grp_status[1]: 0x%08x, user_pos_map[0]: 0x%08x, user_pos_map[1]: 0x%08x, user_pos_map[2]: 0x%08x, user_pos_map[3]: 0x%08x +1850,ii,[ mu_gid_mgmt.c : 169 ] 11ac MU-MIMO GID MGMT: Send GID MGMT failed. SW_PEER_ID: %d, mu_user_id: %d +1865,II,[ ratectrl.c : 8430 ] rc_get_nondata_rc: %x for peer:%p +1864,II,[ ratectrl.c : 8488 ] rc_get_ofdm_nondatarc: %x for peer:%p +1863,iIIII,[ ratectrl.c : 8626 ] pdev_id:%d rc_leg_rate_allowed=0x%x rc_legacy_mask=0x%x temp_cck_rate_bitmap=0x%x module_id=0x%x +1862,iIIIII,[ ratectrl.c : 8656 ] FINAL: pdev_id:%d rc_leg_rate_allowed=0x%x rc_legacy_mask=0x%x pdev->rc_legacy_mask: BT=0x%x LTE_COEX=0x%x HE_ASSOC=0x%x + +1861,,[ ratectrl.c : 6887 ] Set INVALID!!! RTS Rate Index +1860,ii,[ ratectrl.c : 6897 ] _RATE_SetRtsCtsRate: Def RTS Rate Rix %d Alt RTS Rate Rix %d +1859,I,[ ratectrl.c : 6245 ] SEC_RETRY skip PER update flags:0x%x +1858,iiiii,[ ratectrl.c : 6479 ] Prot failure:%d(%d,%d),rts_en(%d,%d) +1857,IIIII,[ ratectrl.c : 9013 ] rc_update_rts_per: rts_rix 0x%x def_rix 0x%x alt_rix 0x%x curr_rix 0x%x ni_legacy_rate_set 0x%x + +1856,iiIiiI,[ ratectrl.c : 2876 ] NSS Mismatch: 160nss %d, 160_mcs_nss_set %d, 160_mcs_nss_map %x, 80nss %d, 80_mcs_nss_set %d, 80_mcs_nss_map %x +1855,II,[ ratectrl.c : 2678 ] rc_validate_rateset/NON_HT: Before mask update ni_legacy_rate_set 0x%x validTxRateMask 0x%x +1854,II,[ ratectrl.c : 2717 ] rc_validate_rateset/NON_HT: After mask update ni_legacy_rate_set 0x%x validTxRateMask 0x%x +1872,I,[ ratectrl_if.c : 106 ] is_rc_peer_mem_optimized: peer is invalid vdev:0x%x +1871,IIi,[ ratectrl_if.c : 1961 ] AUTORATE_RESET_USER_START_RATE: peer phymode:8/ht:8/vht:8 : 0x%08x ni_flags 0x%x user_start_rate %d +1870,,[ ratectrl_if.c : 1654 ] RATE_EnableCCKRatesInHTMode: No vdev's attached to pdev, rejecting WLAN_PDEV_ENABLE_CCK_RATE ! + +1869,IiiIiii,[ ratectrl_if.c : 1719 ] Enabling coex restriction (pdev - 0x%x) enable %d min_rate:%d on wlan_peer:0x%x rc_mode:%d rateMax:%d bestRate:%d +1868,i,[ ratectrl_if.c : 1729 ] vdev[%d] is NULL, rejecting WLAN_PDEV_ENABLE_CCK_RATE ! + +1867,IiiIiii,[ ratectrl_if.c : 1706 ] Enabling coex restriction (pdev - 0x%x) enable %d min_rate:%d on wlan_peer:0x%x rc_mode:%d rateMax:%d bestRate:%d +1866,IIiII,[ ratectrl_if.c : 2137 ] +org_rc_mask_null pdev_rc_mask[0]:%x pdev_rc_mask[1]:%x phymode:%d ni_legacy_rate_set:%x rc_legacy_mask_final:%llx +1904,,[ ratectrl_debug.c : 411 ] RA reset debug test +1903,II,[ ratectrl_debug.c : 1087 ] PEER_CAPS: ni_vht_mcs_set: 0x%x, vht_caps: 0x%x + +1902,I,[ ratectrl_debug.c : 1092 ] PEER_CAPS: he_cap_info: 0x%x + +1901,iI,[ ratectrl_debug.c : 1096 ] PEER_CAPS: he_cap_phy[%d]: 0x%x + +1900,iIiI,[ ratectrl_debug.c : 1103 ] PEER_CAPS: he_mcs_nss_set.map[%d].rx: 0x%x, he_mcs_nss_set.map[%d].tx: 0x%x + +1899,i,[ ratectrl_debug.c : 1126 ] NSS_CLAMP: Invalid pdev id %d + +1898,Ii,[ ratectrl_debug.c : 501 ] RTS_DEBUG: vdev id:8/rts cts type:8/rts cts profile:16 0x%08x rts_rix %d + +1897,I,[ ratectrl_debug.c : 1153 ] NSS_CLAMP: dyn_nss_mask %x + +1896,iiiiII,[ ratectrl_debug.c : 1166 ] rate_ctrl_unit_test use fixed TPC args[0]:%d args[1]:%d args[2]:%d args[3]:%d wal_vdev:0x%x pdev:0x%x +1895,I,[ ratectrl_debug.c : 577 ] RA_DBG_CMDID_TEST_PER_CONV_UL_MUMIMO: ltPer:8/stPer:8/curr_per:8 : 0x%08x +1894,iiiiiiii,[ ratectrl_debug.c : 669 ] MCAST_RC: vdev_id: %d, Is mcast dra enabled: %d +MCAST_RC: stale_period_sec: %d +MCAST_RC: Number of stale clients: %d +MCAST_RC: Default Mcast rate: %d Mbps, rix: %d +MCAST_RC: Auto Mcast rate: %d Mbps, rix: %d + +1893,iiii,[ ratectrl_debug.c : 672 ] MCAST_DBG_RC: RC queries %d, RC updates %d, RIX error: %d, Peer count error: %d + +1892,iii,[ ratectrl_debug.c : 677 ] MCAST_DBG_RC: Last stale peer id %d, current time %d, stale tx time %d + +1891,ii,[ ratectrl_debug.c : 684 ] MCAST_DBG_RC: %d Mbps - %d + +1890,iiiii,[ ratectrl_debug.c : 700 ] MCAST_DBG_RC: peer id: %d, rate kbps: %d, mcast rate kbps: %d, rix:%d, mcast rix:%d + +1889,iii,[ ratectrl_debug.c : 440 ] Number of invalid peer assoc capabilities for HT %d, VHT %d, HE %d + +1888,,[ ratectrl_debug.c : 825 ] DISABLE_INVALID_RATES: Invalid arg count +1887,,[ ratectrl_debug.c : 830 ] DISABLE_INVALID_RATES: Invalid arg count +1886,,[ ratectrl_debug.c : 849 ] DISABLE_INVALID_RATES: Invalid preamble or bw or nss +1885,,[ ratectrl_debug.c : 855 ] DISABLE_INVALID_RATES: Invalid MCS +1884,,[ ratectrl_debug.c : 866 ] DISABLE_INVALID_RATES: Exceeded max invalid rate count, Disable and add invalid rate +1883,,[ ratectrl_debug.c : 884 ] DISABLE_INVALID_RATES: Invalid arg count +1882,,[ ratectrl_debug.c : 1012 ] PEER_CAPS: USAGE: wifitool athX setUnitTestCmd 10 3 39 + +1881,i,[ ratectrl_debug.c : 1027 ] PEER_CAPS: Invalid pdev id %d + +1880,I,[ ratectrl_debug.c : 1053 ] PEER_CAPS: dyn_nss_mask %x + +1879,IIIII,[ ratectrl_debug.c : 1061 ] PEER_CAPS: aid 0x%x, sw_peer_id: 0x%x, ni_flags: 0x%x, phymode: 0x%x, peer_nss :0x%x + +1878,i,[ ratectrl_debug.c : 466 ] g_dbg_enable_he_short_gi: %d + +1877,I,[ ratectrl_debug.c : 1065 ] PEER_CAPS: peer_nss_160: 0x%x + +1876,I,[ ratectrl_debug.c : 1070 ] PEER_CAPS: peer_ul_nss: 0x%x + +1875,I,[ ratectrl_debug.c : 1074 ] PEER_CAPS: ni_legacy_rate_set: 0x%x + +1874,iI,[ ratectrl_debug.c : 1079 ] PEER_CAPS: ni_ht_mcs_set[%d]: 0x%x + +1873,I,[ ratectrl_debug.c : 1083 ] PEER_CAPS: ht_caps: 0x%x + +1908,iiiiiii,[ ratectrl_ofdma.c : 1643 ] UL_PSD_BOOST_DBG: AID: %d, bw: %d, ref_mcs: %d, ref_nss: %d, ru_try: %d, boosted mcs: %d, boosted nss: %d +1907,iiiIIi,[ ratectrl_ofdma.c : 1865 ] UL_PSD_BOOST_DBG: idx: %d, AID: %d, MRU RU Size: %d, Out of Date Bmap: 0x%08x, Invalid RU Size Bmap: 0x%08x, Lgest uptodate ru: %d +1906,iiIiiiiiI,[ ratectrl_ofdma.c : 1888 ] UL_PSD_BOOST_DBG: idx: %d, AID: %d, cur_time: %u, ru_size: %d, dst_mcs: %d, dst_nss: %d, src_mcs: %d, src_nss: %d, src_tstamp: %u +1905,iiiiii,[ ratectrl_ofdma.c : 1178 ] OFDMA_RC_DBG: aid: %d, ref_rix: %d, trialBaseRate: %d, complMismatchCnt: %d, ru_size: %d, rc_mode: %d +1960,IIIiIII,[ sched_algo.c : 12901 ] AGGR_DBG: aid: %u avg_msdu_bytes: %u, amsdu_estimate: %u, required_bits: %d, required_mpdu: %u, ppdu duration: %u, phy_rate_kbps: %u +1959,iIIii,[ sched_algo.c : 2339 ] smart_basic_trig : skip_no_ul_data service_interval=%d, time_diff=%lu, last_sched_tsmp=%lu, aid=%d, tid_num=%d + +1958,iiIIii,[ sched_algo.c : 2345 ] smart_basic_trig : service_interval=%d, exp_bytes=%d, time_diff=%lu, last_sched_tsmp=%lu, aid=%d, tid_num=%d + +1957,I,[ sched_algo.c : 2406 ] ul_dbg_check_eligibility: No UL Trig: is_wmm_txq_ul_trig_disabled=%u +1956,IiiiIIII,[ sched_algo.c : 2503 ] ul_dbg_check_eligibility: tid_q=%x, tid_num=%d, is_bsr_timeout=%d, num_frms=%d, curr_time = %u, tsf_now=%u, bsr_ts=%u, bsr_timeout_ms=%u +1955,i,[ sched_algo.c : 2510 ] ul_dbg_check_eligibility: trigger_state=%d +1954,iiii,[ sched_algo.c : 2574 ] OFDMA_SCHED_DECISION: aid: %d, tid_num: %d, unreliable_basic_trigger: %d, unreliable_metric: %d +1953,iIi,[ sched_algo.c : 7587 ] MISSING_BSR_DEBUG: aid: %d, trigger in flight=false, updated_ac_bmap: 0x%08x, miss_count: %d +1952,iIi,[ sched_algo.c : 7603 ] MISSING_BSR_DEBUG2: aid: %d, trigger in flight=false, updated_ac_bmap: 0x%08x, miss_count: %d +1951,iiii,[ sched_algo.c : 7634 ] MISSING_BSR_DEBUG: aid: %d, trigger in flight=false, ac=%d, orig_timeout: %d, new_timeout: %d +1950,iiIIiIII,[ sched_algo.c : 7672 ] twt_dbg/ul_dbg: sched_cmd_completion txqid=%d, sched_id=%d, seq_type=%u, peer_id=%u, pending_commands=%d,compl_ts=%u, user_resp=%u, seq_compl_flags=0x%x + +1949,IIIII,[ sched_algo.c : 7684 ] twt_dbg: sched_cmd_completion peer_id=%u, tid_num=%u, sched_flags=0x%x, trigger_state=%u, eosp_state=%u + +1948,i,[ sched_algo.c : 3904 ] STANDALONE:sched_algo_cmd_update_user_info NDPA FLAG NOT SET $$$tid_num=%d +1947,IIII,[ sched_algo.c : 6028 ] sched_algo_configure_ul_rts_protection: t_success_rts: %u, t_success_no_rts: %u, t_fail_no_rts: %u, t_fail_rts: %u +1946,iIIIIII,[ sched_algo.c : 6099 ] sched_algo_configure_ul_rts_protection: ac: %d, num_users: %u, tb_ppdu_duration: %u, trig_rix: %u, mba_rix: %u, min_coll_prob_to_enable_rts_cts: %u, cur_fail_pct: %u +1945,iII,[ sched_algo.c : 13570 ] sched_algo_disable_sched_mode_bmap_update: IN: txq_id: %d, disabled_sched_mode_bmap_req: 0x%08x, disabled_sched_mode_bmap: 0x%08x +1944,iII,[ sched_algo.c : 13597 ] sched_algo_disable_sched_mode_bmap_update: OUT: txq_id: %d, disabled_sched_mode_bmap_req: 0x%08x, disabled_sched_mode_bmap: 0x%08x +1943,IiiiiII,[ sched_algo.c : 6404 ] ul_dbg_sched_dispatch_result: tsf_lsb=%u, sched_mode=%d, tx_mode=%d, seq_type=%d, num_users=%d, tx_time_us=%u, txop_time_us=%u +1942,i,[ sched_algo.c : 6718 ] MISSING_BSR_DEBUG: aid: %d, trigger in flight=true +1941,,[ sched_algo.c : 6827 ] MBSSID_CTRL_FRM_DBG MBSSID Ctrl Frame Feature is in use +1940,,[ sched_algo.c : 6850 ] sched_algo_configure_ul_rts_protection: using shorter RTS duration for non-repeater environment +1939,iiiIiIII,[ sched_algo.c : 7000 ] twt_dbg_eosp / ul_dbg: sched_dispatch_sched_cmd txqid=%d, sched_id=%d, posted_commands=%d,sched_cmd_flags=0x%x, is_partial=%d, tsf_low=%u, start_time=%u, end_time=%u + +1938,IiiIII,[ sched_algo.c : 11687 ] twt_dbg_eosp: sched_algo_dl_eligible_check peer_id=%u, is_announced=%d, is_ul_received=%d,tidq->tid_num=%u, tid_ext_flags=0x%x, eosp_state=%u +1937,ii,[ sched_algo.c : 5597 ] TTL dropped count:%d, tid:%d +1936,iii,[ sched_algo.c : 12453 ] UL_FD_RSSI_DBG:sw peer id %d ulmumimo_fd_rssi_100x %d dbg_ulmumimo_fd_rssi_threshold_100x %d + +1935,iiiIiii,[ sched_algo.c : 12490 ] UL_MU_MIMO_TX_PARAMS: AID %d: NSS %d: MCS: %d, qdepth bytes: %lu, txtime %d, num frames: %d tidq_ul_mumimo_eligible %d + +1934,iiiii,[ sched_algo.c : 12624 ] OFDMA_SCHED_DECISION: top level eligibility: aid: %d, tid_num: %d, sta_is_lowq: %d, avg_txtime_us: %d, average_ul_qdepth_bytes: %d +1933,III,[ sched_algo.c : 10274 ] migrate peer in delete prog %p, flags:%x, sw_peer_id:%x +1932,iII,[ sched_algo.c : 10304 ] migrate peer %d, already on MAC(%u %u) +1931,II,[ sched_algo.c : 13490 ] MBSSID_CTRL_FRM_DBG peer_a RXCFM cap = %u, peer_b RXCFM cap = %u +1930,,[ sched_algo.c : 13500 ] MBSSID_CTRL_FRM_DBG Using MBSSID Control Frame - Triggering peers on different vdevs +1929,,[ sched_algo.c : 13518 ] MBSSID_CTRL_FRM_DBG Using MBSSID Control Frame - Triggering peers on different vdevs +1928,iiiiiiI,[ sched_algo.c : 4754 ] PPDU Duration debug: sched_id=%d, num_users=%d, txop_us=%d,txtime_us=%d, seq_type=%d, sched_type=%d flags = 0x%x +1927,iiI,[ sched_algo.c : 8959 ] soft_msduq_delete: tickle dropped :%d qtype:%d 0x%x +1926,IIIIII,[ sched_algo.c : 8979 ] sched_algo_process_trigger non_paused_tid enter: tid=0x%x,pdev=0x%x:0x%x,flag=0x%x, paused=0x%0x num_mpdus_in_fq=0x%0x +1925,IIIII,[ sched_algo.c : 8993 ] discard trigger msg as pdev mismatch peer_id=%x,tid=%x,pdev=%x:%x,flag=%x +1924,IIIIII,[ sched_algo.c : 9185 ] sched_algo_process_trigger non_paused_tid run_scheduler: tid=0x%x,pdev=0x%x:0x%x,flag=0x%x, paused=0x%0x num_mpdus_in_fq=0x%0x +1923,i,[ sched_algo.c : 10905 ] sched_algo_req_handler: unsupported msg type:%d +1922,iiiiii,[ sched_algo.c : 3169 ] twt_dbg: twt_sched_algo_return (slot ended):txqid=%d, tsf_now_msb=%d, lsb=%d, curr_slot_end msb=%d, lsb=%d slot_valid:%d +1921,iiI,[ sched_algo.c : 3226 ] ul_dbg_sched_new_run: txqid=%d, sched_cmd_space=%d, flags=0x%x +1920,iiI,[ sched_algo.c : 3305 ] twt_dbg: twt_sched_algo_run_policy: txqid=%d, sched_cmd_space=%d, flags=%x +1919,iiII,[ sched_algo.c : 8098 ] TTL tid:%d txq_id:%d, flg-clr:%x %x +1918,ii,[ sched_algo.c : 438 ] STANDALONE : SEND MESSAGE TO SCHEDULER %d thread id %d +1917,IIIIIIII,[ sched_algo.c : 5712 ] tcp_ul_dbg_sched_dispatch_result: tx_mode=%u, peer_sw_id=%u, sched_id=0x%x, qdepth_adv =%u, qdepth_implicit=%u, qdepth_implicit_final=%u, ru_size=%u, ru_idx=%u +1916,ii,[ sched_algo.c : 1972 ] ul_dbg_sched_algo_tid_register: num_frames=%d, tid_num=%d +1915,iiiIi,[ sched_algo.c : 2016 ] TID REG:peer %d tidnum %d txqid %d flags %x num active %d + +1914,ii,[ sched_algo.c : 2113 ] ul_dbg_sched_algo_tid_unregister: num_frames=%d, tid_num=%d +1913,iiiIii,[ sched_algo.c : 2173 ] TID UNREG:peer %d tidnum %d txq %d flags %x num active %d, pause_tid:%d +1912,II,[ sched_algo.c : 3600 ] sched_algo_cmd_update_user_info: g_qnull_peer_id%x %x +1911,,[ sched_algo.c : 3606 ] NEW_STATS: qnull set +1910,iiiii,[ sched_algo.c : 12978 ] AGGR_DBG: user %d: assigned: %d, rate_kbps: %d, qdepth: %d, target_mpdu: %d + +1909,Iii,[ sched_algo.c : 4713 ] smart_basic_trig : last_sched_tsmp=%lu aid=%d, tid_num=%d + +1961,ii,[ sched_algo_rr.c : 380 ] twt_dbg: sched_algo_run_rr_scheduler_tidq0 skip tid tid:%d elgble: %d +1965,iiiiii,[ sched_algo_qos.c : 415 ] FORCE_SU_UL_TRIG: peer aid: %d, force_single_user_ul_ofdma: %d, cur_peer_requires_su_trigger: %d, force_2users_in_160_trigger %d, primary peer aid: %d, cur_time: %d +1964,IIIIII,[ sched_algo_qos.c : 2128 ] twt_dbg: check_eligibility:curr_time_us=%u, txqid=%u, peer_id=%u, tid_num=%u, is_skip_tid=%u, sched_eligible=%u +1963,i,[ sched_algo_qos.c : 1031 ] twt_dbg: twt_sched_algo_qos returned (CL empty): txqid=%d +1962,Ii,[ sched_algo_qos.c : 3169 ] ul_dbg_tid_unregister_qos: qpeer=0x%x, tid_num=%d +1966,Iiiiii,[ sched_algo_mu.c : 510 ] MU_RATE_INFO CACHE HIT RIX %x rc mode %d mcs %d nss %d sched type %d tput mpbs %d + +1983,iii,[ ru_allocator.c : 6497 ] RU Power imbalance Adjust: pre mcs %d, per_tone_pwr %d, interference_from_pre %d +1982,iii,[ ru_allocator.c : 6515 ] RU Power imbalance Adjust: next mcs %d, per_tone_pwr %d, interference_from_next %d +1981,iiiiii,[ ru_allocator.c : 6548 ] RU Power imbalance Adjust: mcs %d, pre mcs %d per_tone_pwr %d, interference_from_neigbor %d, margin %d, num_notches %d +1980,,[ ru_allocator.c : 6852 ] UL_OFDMA_USR_CAP_DBG - Setting 4x HE-LTF and 3200ns GI for large user UL trigger +1979,II,[ ru_allocator.c : 6242 ] RU_ALLOC_DBG: Dyn PPDU Duration - user_min_bytes = %u, addnl_bytes_added = %u +1978,I,[ ru_allocator.c : 6332 ] RU_ALLOC_DBG: Dyn PPDU Duration - Picking min dur by default for UL data = %u +1977,II,[ ru_allocator.c : 6342 ] RU_ALLOC_DBG: Dyn PPDU Duration - Picking max dur due to small delta = %u, max_dur = %u +1976,III,[ ru_allocator.c : 6353 ] RU_ALLOC_DBG: Dyn PPDU Duration - min_dur = %u, max_dur = %u, final_selected_dur = %u +1975,ii,[ ru_allocator.c : 366 ] Dropping Static RU Unit Test Cmd - Num Args %d : Max Users: %d +1974,iii,[ ru_allocator.c : 393 ] RU idx exceeds max idx - ru_idx: %d : ru_size: %d : tx_bw: %d +1973,iii,[ ru_allocator.c : 400 ] Incorrect Static RU allocation - ru_idx: %d : ru_size: %d : tx_bw: %d +1972,iIIii,[ ru_allocator.c : 8043 ] RU_ALLOC DBG: id: %d, ru_input: flags: 0x%08x, pat_mask 0x%08x, ppdu_time: %d, input user count: %d +1971,iiiiIiii,[ ru_allocator.c : 8063 ] RU_ALLOC DBG: id: %d, aid: %d, max_bw: %d, rix: %d, queue_depth: %u, qos_weight: %d, consec_no_mpdu_tried: %d, consec_skip_cnt: %d +1970,iiiIiii,[ ru_allocator.c : 8087 ] RU_ALLOC DBG: id: %d, ru_result: ret_val: %d, num_users: %d, pat_mask 0x%08x, data_ppdu_dur[0]: %d, data_ppdu_dur[1]: %d, data_ppdu_dur[2]: %d +1969,iiii,[ ru_allocator.c : 8100 ] RU_ALLOC DBG: id: %d, ru_result: ul_ba_ppdu_duration_us[0]: %d, ul_ba_ppdu_duration_us[1]: %d, ul_ba_ppdu_duration_us[2]: %d +1968,ii,[ ru_allocator.c : 8110 ] RU_ALLOC DBG: id: %d, DROPPED_USER: aid: %d +1967,,[ ru_allocator.c : 5649 ] UL_OFDMA_USR_CAP_DBG - Dropping User +2194,,[ sched_algo_dbg.c : 7715 ] Charter Carrier NA in ATF DISABLE +2193,iiiiiiiii,[ sched_algo_dbg.c : 7497 ] AMSDU_DEBUG_CALC: rix=%d preamble=%d nss=%d mcs=%d gi=%d amsdu_64=%d amsdu_128=%d bw=%d rate_kbps=%d + +2192,iiiiiiiii,[ sched_algo_dbg.c : 7509 ] AMSDU_DEBUG_TBL: rix=%d preamble=%d nss=%d mcs=%d gi=%d amsdu_64=%d amsdu_128=%d bw=%d rate_kbps=%d + +2191,IiiIiIi,[ sched_algo_dbg.c : 6551 ] Tput Monitor tid_mask: 0x%x peer_id: %d, airtime: %d.%03d s, total Duration: %d.%03d s, Duration_percent: %d +2190,IiiIiIi,[ sched_algo_dbg.c : 6555 ] Tput Monitor tid_mask: 0x%x peer_id: %d, airtime: %d.%03d ms, total Duration: %d.%03d s, Duration_percent: %d +2189,IiiiIi,[ sched_algo_dbg.c : 6559 ] Tput Monitor tid_mask: 0x%x peer_id: %d, airtime: %d us, total Duration: %d.%03d s, Duration_percent: %d +2188,IiiI,[ sched_algo_dbg.c : 6573 ] Tput Monitor tid_mask: 0x%x peer_id: %d, Bandwidth: %d.%03d Gbits/sec +2187,IiiI,[ sched_algo_dbg.c : 6577 ] Tput Monitor tid_mask: 0x%x peer_id: %d, Bandwidth: %d.%03d Mbits/sec +2186,Iii,[ sched_algo_dbg.c : 6581 ] Tput Monitor tid_mask: 0x%x peer_id: %d, Bandwidth: %d Kbits/sec +2185,Iii,[ sched_algo_dbg.c : 6586 ] Tput Monitor tid_mask: 0x%x peer_id: %d, Bandwidth: %d bits/sec +2184,IiiI,[ sched_algo_dbg.c : 6600 ] Tput Monitor tid_mask: 0x%x peer_id: %d, MSDU Bandwidth: %d.%03d Gbits/sec +2183,IiiI,[ sched_algo_dbg.c : 6604 ] Tput Monitor tid_mask: 0x%x peer_id: %d, MSDU Bandwidth: %d.%03d Mbits/sec +2182,Iii,[ sched_algo_dbg.c : 6608 ] Tput Monitor tid_mask: 0x%x peer_id: %d, MSDU Bandwidth: %d Kbits/sec +2181,Iii,[ sched_algo_dbg.c : 6613 ] Tput Monitor tid_mask: 0x%x peer_id: %d, MSDU Bandwidth: %d bits/sec +2180,iiiiii,[ sched_algo_dbg.c : 7929 ] SCH_LATENCY : sched_latency = ,%d, %d, %d, %d, %d, %d +2179,iiiiii,[ sched_algo_dbg.c : 7933 ] SCH_LATENCY : rtxop_sched_latency = ,%d, %d, %d, %d, %d, %d +2178,iiiiii,[ sched_algo_dbg.c : 7937 ] SCH_LATENCY : tid_reg_latency = ,%d, %d, %d, %d, %d, %d +2177,ii,[ sched_algo_dbg.c : 7940 ] SCH_LATENCY : tid registered = %d, unregistered = %d +2176,ii,[ sched_algo_dbg.c : 245 ] STANDALONE : TICKLE SCHEDULER %d thread id %d +2175,,[ sched_algo_dbg.c : 454 ] ATF stats + +2174,ii,[ sched_algo_dbg.c : 1409 ] ULMU_PRINT, ul_bsr_cnt %d, total_cnt %d +2173,iiiiiiii,[ sched_algo_dbg.c : 1421 ] ULMU_PRINT, dl_cnt[0-3] %d, %d, %d, %d ul_cnt[0-3] %d, %d, %d, %d +2172,iiiiiiii,[ sched_algo_dbg.c : 1432 ] ULMU_PRINT, dl_cnt[4-7] %d, %d, %d, %d ul_cnt[4-7] %d, %d, %d, %d +2171,iiiiii,[ sched_algo_dbg.c : 1489 ] ULMU_PRINT, mpdu_ok_per_AID, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d +2170,iiiiii,[ sched_algo_dbg.c : 1500 ] ULMU_PRINT, mpdu_fail_per_AID, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d +2169,,[ sched_algo_dbg.c : 487 ] bss +2168,iiiiiiii,[ sched_algo_dbg.c : 1877 ] mu_mimo_grp_stats:mu_grp_best_grp_size -> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2167,iiii,[ sched_algo_dbg.c : 1903 ] mu_mimo_grp_stats:mu_grp_best_num_users -> (%d, %d, %d, %d) + +2166,iiiii,[ sched_algo_dbg.c : 1914 ] mu_mimo_grp_stats:mu_mimo_tputs_observed (0-1500Mbps)> (%d, %d, %d, %d, %d ) + +2165,iiiii,[ sched_algo_dbg.c : 1925 ] mu_mimo_grp_stats:mu_mimo_tputs_observed (1500-3000Mbps) (%d, %d, %d, %d, %d) + +2164,iiiiiiiii,[ sched_algo_dbg.c : 1939 ] mu_mimo_grp_stats:num_mu_mimo_candidate(0-8 users)-> ( %d, %d, %d, %d, %d, %d, %d, %d, %d ) + +2163,iiiiiiii,[ sched_algo_dbg.c : 1952 ] mu_mimo_grp_stats:num_mu_mimo_candidate(9-16 users)-> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2162,iiiiiiii,[ sched_algo_dbg.c : 1965 ] mu_mimo_grp_stats:num_mu_mimo_candidate_nr4 -> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2161,iiiiiiii,[ sched_algo_dbg.c : 1978 ] mu_mimo_grp_stats:num_mu_mimo_candidate_nr8 -> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2160,iiiii,[ sched_algo_dbg.c : 1988 ] mu_mimo_grp_stats:sched_type -> (%d, %d, %d, %d, %d ) + +2159,i,[ sched_algo_dbg.c : 1991 ] mu_mimo_grp_stats:Group_id: %d +2158,,[ sched_algo_dbg.c : 489 ] self +2157,iiii,[ sched_algo_dbg.c : 2017 ] mu_mimo_grp_stats:cd_num_entries -> (%d, %d, %d, %d ) + +2156,iiiii,[ sched_algo_dbg.c : 2029 ] mu_mimo_grp_stats:tputs for this group id (0 - 1500 Mbps)-> (%d, %d, %d, %d, %d) +2155,iiiii,[ sched_algo_dbg.c : 2039 ] mu_mimo_grp_stats:tputs for this group id(1500-3000 Mbps) -> (%d, %d, %d, %d, %d) +2154,,[ sched_algo_dbg.c : 2042 ] mu_mimo_grp_stats:candidate_rc_mode -> + +2153,iiiii,[ sched_algo_dbg.c : 2072 ] mu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d) + +2152,,[ sched_algo_dbg.c : 2078 ] mu_mimo_grp_stats:candidate_best_nss -> + +2151,iiiii,[ sched_algo_dbg.c : 2108 ] mu_mimo_grp_stats:user %d -> (%d, %d, %d, %d) +2150,,[ sched_algo_dbg.c : 2114 ] mu_mimo_grp_stats:candidate_sched_type -> + +2149,iiiiii,[ sched_algo_dbg.c : 2131 ] mu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d, %d) +2148,,[ sched_algo_dbg.c : 2135 ] mu_mimo_grp_stats:candidate_sched_compatibility -> + +2147,iIIIIii,[ sched_algo_dbg.c : 500 ] peer %d, mac %x %x, tx resource consumption %u, rx resource consumption %u, atf units: expected %d actual %d + +2146,iiiiiiiii,[ sched_algo_dbg.c : 2158 ] mu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d, %d, %d, %d, %d) +2145,,[ sched_algo_dbg.c : 2162 ] mu_mimo_grp_stats:candidate_nr_index -> + +2144,iiiiiiiii,[ sched_algo_dbg.c : 2177 ] mu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d, %d, %d, %d, %d) +2143,iiii,[ sched_algo_dbg.c : 2205 ] mu_mimo_grp_stats:cd_num_eligible -> (%d, %d, %d, %d ) + +2142,,[ sched_algo_dbg.c : 2209 ] mu_mimo_grp_stats:mu_group_eligible_skip -> + +2141,iiiiiiiii,[ sched_algo_dbg.c : 2232 ] mu_mimo_grp_stats:user %d ->( %d, %d, %d, %d, %d, %d, %d, %d) +2140,iiiiiiiii,[ sched_algo_dbg.c : 2249 ] mu_mimo_grp_stats: mu_grp_invalid -> (%d, %d, %d, %d, %d, %d, %d, %d %d ) + +2139,i,[ sched_algo_dbg.c : 2255 ] mu_mimo_grp_stats:mu_grp_ineligible -> %d + +2138,i,[ sched_algo_dbg.c : 2261 ] mu_mimo_grp_stats:mu_grp_eligible -> %d + +2137,i,[ sched_algo_dbg.c : 2502 ] SCHED_RU_ALLOC_DBG: g_sched_algo_cfg.dbg.cnt.dl_mode_allocation_failed: %d +2136,,[ sched_algo_dbg.c : 518 ] Resetting ATF stats + +2135,i,[ sched_algo_dbg.c : 2506 ] SCHED_RU_ALLOC_DBG: g_sched_algo_cfg.dbg.cnt.ul_mode_allocation_failed: %d +2134,ii,[ sched_algo_dbg.c : 2515 ] SCHED_RU_ALLOC_DBG: g_sched_algo_cfg.dbg.cnt.sched_mode_disabled[%d]: %d +2133,i,[ sched_algo_dbg.c : 2522 ] SCHED_RU_ALLOC_DBG: g_dbg_ul_ofdma_160mhz_ru_war.peers_ineligible: %d +2132,i,[ sched_algo_dbg.c : 2526 ] SCHED_RU_ALLOC_DBG: g_dbg_ul_ofdma_160mhz_ru_war.peers_ineligible_ul_ofdma: %d +2131,i,[ sched_algo_dbg.c : 2530 ] SCHED_RU_ALLOC_DBG: g_dbg_ul_ofdma_160mhz_ru_war.peers_eligible_ul_ofdma: %d +2130,i,[ sched_algo_dbg.c : 2766 ] pdev %d not initialized + +2129,ii,[ sched_algo_dbg.c : 2770 ] pdev %d rx_ps_fifo_drop %d + +2128,iiii,[ sched_algo_dbg.c : 2951 ] ULMU_PRINT, FDRSSI_per_usr_nss_bin, %d, %d, %d: %d +2127,iiiiii,[ sched_algo_dbg.c : 3042 ] ULMU_PRINT, mcs_0_5_per_AID, 1, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2126,iiiiii,[ sched_algo_dbg.c : 3052 ] ULMU_PRINT, mcs_6_11_per_AID, 1, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2125,iiiii,[ sched_algo_dbg.c : 566 ] SCHED_LOGS: Num active tids in txq %d %d, %d, %d, %d + +2124,iiiiii,[ sched_algo_dbg.c : 3062 ] ULMU_PRINT, mcs_0_5_per_AID, 2, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2123,iiiiii,[ sched_algo_dbg.c : 3072 ] ULMU_PRINT, mcs_6_11_per_AID, 2, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2122,iiiiii,[ sched_algo_dbg.c : 3082 ] ULMU_PRINT, mcs_0_5_per_AID, 3, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2121,iiiiii,[ sched_algo_dbg.c : 3092 ] ULMU_PRINT, mcs_6_11_per_AID, 3, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2120,iiiiii,[ sched_algo_dbg.c : 3102 ] ULMU_PRINT, mcs_0_5_per_AID, 4, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2119,iiiiii,[ sched_algo_dbg.c : 3112 ] ULMU_PRINT, mcs_6_11_per_AID, 4, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2118,iiiiii,[ sched_algo_dbg.c : 3122 ] ULMU_PRINT, mcs_0_5_per_AID, 5, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2117,iiiiii,[ sched_algo_dbg.c : 3132 ] ULMU_PRINT, mcs_6_11_per_AID, 5, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2116,iiiiii,[ sched_algo_dbg.c : 3142 ] ULMU_PRINT, mcs_0_5_per_AID, 6, 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d +2115,iiiiii,[ sched_algo_dbg.c : 3152 ] ULMU_PRINT, mcs_6_11_per_AID, 6, 6:%d, 7:%d, 8:%d, 9:%d, 10:%d, 11:%d +2114,ii,[ sched_algo_dbg.c : 570 ] SCHED_LOGS: Registered tids in txq %d list %d + +2113,iiii,[ sched_algo_dbg.c : 3176 ] ULMU_PRINT, FDRSSI_per_AID_nss_bin, %d, %d, %d: %d +2112,iii,[ sched_algo_dbg.c : 3202 ] ULMU_PRINT, Target_RSSI_per_AID_bin, %d, %d: %d +2111,iiiiiii,[ sched_algo_dbg.c : 3554 ] ATM: group_id %d, group_units %d, flags %d, wmm_be_units %d, wmm_bk_units %d, wmm_vo_units %d, wmm_vi_units %d +2110,iiii,[ sched_algo_dbg.c : 3560 ] ATM: ERR_STATS Ivalid grp_id %d, Invalid group %d, Invalid group units %d, Invalid peer %d +2109,iiii,[ sched_algo_dbg.c : 3568 ] ATM: Eligibility counters 0: %d, 1: %d, 2: %d, 3: %d +2108,iii,[ sched_algo_dbg.c : 3609 ] STANDALONE INVALID SW PEER ID cmd num %d pdev id %d sw peer id %d +2107,iii,[ sched_algo_dbg.c : 3612 ] STANDALONE cmd num %d pdev id %d sw peer id %d +2106,I,[ sched_algo_dbg.c : 3675 ] effective_tput_gain_factor: %u. +2105,IIIII,[ sched_algo_dbg.c : 3740 ] UL_SCHED_DEC_STATS: ac: %u, count: %u, latency_sensitive: %u, psd_boost: %u, collision_reduction: %u +2104,II,[ sched_algo_dbg.c : 3770 ] PARTIAL_SND_STATS: : MU2 1:%u 2:%u +2103,i,[ sched_algo_dbg.c : 574 ] SCHED_LOGS: peer id %d + +2102,III,[ sched_algo_dbg.c : 3775 ] PARTIAL_SND_STATS: : MU3 1:%u 2:%u 3:%u +2101,IIII,[ sched_algo_dbg.c : 3781 ] PARTIAL_SND_STATS: : MU4 1:%u 2:%u 3:%u 4:%u +2100,II,[ sched_algo_dbg.c : 3906 ] dl_mu_mimo_my_cv_sync g_dbg_mu_cv_sync_counter: %u, g_dbg_mu_cv_sync_counter_invalid_idx: %u. +2099,iiiiii,[ sched_algo_dbg.c : 4049 ] SCHED_CMD_DBG: AVG Tx: %d, AVG legacy Rx %d, AVG HE Rx: %d rx < tx | rx < ax_rx: %d, rx > tx -> 1. With pending sched cmds %d 2. No sched cmd %d +2098,,[ sched_algo_dbg.c : 4081 ] SU_STATS_DBG: usage: wifitool athX setUnitTestCmd 0x47 3 258 < 0 / 1 > +2097,,[ sched_algo_dbg.c : 4105 ] SU_STATS_DBG: ---Cleared all SU Multi Destination and SU Only stats--- +2096,iiii,[ sched_algo_dbg.c : 4111 ] SU_STATS_DBG: num_su_multi_dest_scheduled: BK: %d | BE = %d | VI = %d | VO = %d +2095,iiii,[ sched_algo_dbg.c : 4117 ] SU_STATS_DBG: num_su_only_scheduled: BK: %d | BE = %d | VI = %d | VO = %d +2094,i,[ sched_algo_dbg.c : 4175 ] STANDALONE INVALID SW PEER ID %d +2093,,[ sched_algo_dbg.c : 4181 ] STANDALONE SEND MSG SUCCESSFUL +2092,iii,[ sched_algo_dbg.c : 461 ] atf pdev %d tx resource consumption %d, rx resource consumption %d + +2091,iii,[ sched_algo_dbg.c : 580 ] SCHED_LOGS: Pdev id %d, txq %d, last sched order idx %d + +2090,,[ sched_algo_dbg.c : 4183 ] STANDALONE SEND MSG FAILED +2089,iiii,[ sched_algo_dbg.c : 4205 ] AC_DBG: Requests BE: %d, BK: %d, VI: %d, VO: %d +2088,iiii,[ sched_algo_dbg.c : 4206 ] AC_DBG: Counters Data Txq : %d, Other Txq: %d, i/p max_sched_cmd < pending sched_cmds: %d, default %d +2087,I,[ sched_algo_dbg.c : 4318 ] CV_UPLOAD cv_fcs_err : %u +2086,I,[ sched_algo_dbg.c : 4321 ] CV_UPLOAD cv_frag_idx_mismatch : %u +2085,I,[ sched_algo_dbg.c : 4324 ] CV_UPLOAD cv_invalid_peer_id : %u +2084,I,[ sched_algo_dbg.c : 4327 ] CV_UPLOAD cv_dma_not_done_err : %u +2083,I,[ sched_algo_dbg.c : 4330 ] CV_UPLOAD cv_nc_idx_mismatch : %u +2082,I,[ sched_algo_dbg.c : 4333 ] CV_UPLOAD cv_expiry_in_update : %u +2081,I,[ sched_algo_dbg.c : 4336 ] CV_UPLOAD cv_update_failed : %u +2080,iiiii,[ sched_algo_dbg.c : 589 ] SCHED_LOGS: last scheduled peer ids %d, %d, %d, %d, %d +2079,I,[ sched_algo_dbg.c : 4339 ] CV_UPLOAD cv_pkt_bw_exceed : %u +2078,I,[ sched_algo_dbg.c : 4342 ] CV_UPLOAD cv_no_txbf_setup : %u +2077,I,[ sched_algo_dbg.c : 4394 ] DYN_MIMO_PS num_seq_posted: %u +2076,II,[ sched_algo_dbg.c : 4399 ] DYN_MIMO_PS num_dyn_mimo_ps_users [%u]: %u +2075,II,[ sched_algo_dbg.c : 4405 ] DYN_MIMO_PS num_users_posted [%u]: %u +2074,II,[ sched_algo_dbg.c : 4464 ] ULMU_PRINT: Num Triggers %u: %u +2073,II,[ sched_algo_dbg.c : 4467 ] ULMU_PRINT: Total Txop %u: %u +2072,iiiiiiii,[ sched_algo_dbg.c : 4572 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_grp_best_grp_size -> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2071,iiii,[ sched_algo_dbg.c : 4598 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_grp_best_num_users -> (%d, %d, %d, %d ) + +2070,iiiii,[ sched_algo_dbg.c : 4609 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_mimo_tputs_observed (0-1500Mbps)> (%d, %d, %d, %d, %d ) + +2069,iiiii,[ sched_algo_dbg.c : 1010 ] ac_mu_mimo : Num_users %d Per user txtime user%d_bin_%d - %d : %d +2068,iiiii,[ sched_algo_dbg.c : 4619 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_mimo_tputs_observed (1500-3000Mbps) (%d, %d, %d, %d, %d) + +2067,iiiiiiiii,[ sched_algo_dbg.c : 4633 ] ULMU_PRINT : ulmu_mimo_grp_stats:num_mu_mimo_candidate(0-8 users)-> ( %d, %d, %d, %d, %d, %d, %d, %d, %d ) + +2066,iiiiiiii,[ sched_algo_dbg.c : 4645 ] ULMU_PRINT: ulmu_mimo_grp_stats:num_mu_mimo_candidate(9-16 users)-> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2065,i,[ sched_algo_dbg.c : 4648 ] ULMU_PRINT: ulmu_mimo_grp_stats:Group_id: %d +2064,iiii,[ sched_algo_dbg.c : 4674 ] ULMU_PRINT: ulmu_mimo_grp_stats:cd_num_entries -> (%d, %d, %d, %d ) + +2063,iiiii,[ sched_algo_dbg.c : 4686 ] ULMU_PRINT: ulmu_mimo_grp_stats:tputs for this group id (0 - 1500 Mbps)-> (%d, %d, %d, %d, %d) +2062,iiiii,[ sched_algo_dbg.c : 4696 ] ULMU_PRINT: ulmu_mimo_grp_stats:tputs for this group id(1500-3000 Mbps) -> (%d, %d, %d, %d, %d) +2061,,[ sched_algo_dbg.c : 4699 ] ULMU_PRINT: ulmu_mimo_grp_stats:candidate_rc_mode -> + +2060,iiiii,[ sched_algo_dbg.c : 4729 ] ULMU_PRINT: ulmu_mimo_grp_stats:user %d -> (%d, %d, %d ,%d) + +2059,,[ sched_algo_dbg.c : 4735 ] ULMU_PRINT: ulmu_mimo_grp_stats:candidate_best_nss -> + +2058,ii,[ sched_algo_dbg.c : 1020 ] ac_mu_mimo : Num schedules with num_users as %d : %d +2057,iiiiiiiii,[ sched_algo_dbg.c : 4765 ] ULMU_PRINT: ulmu_mimo_grp_stats:user %d -> (%d, %d, %d, %d, %d, %d, %d, %d) +2056,,[ sched_algo_dbg.c : 4770 ] ULMU_PRINT: ulmu_mimo_grp_stats:candidate_sched_compatibility -> + +2055,iiiiiiiii,[ sched_algo_dbg.c : 4793 ] ULMU_PRINT: ulmu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d, %d, %d, %d, %d) +2054,,[ sched_algo_dbg.c : 4797 ] ULMU_PRINT: ulmu_mimo_grp_stats:candidate_nr_index -> + +2053,iiiiiiiii,[ sched_algo_dbg.c : 4812 ] ULMU_PRINT: ulmu_mimo_grp_stats:user %d -> ( %d, %d, %d, %d, %d, %d, %d, %d) +2052,iiii,[ sched_algo_dbg.c : 4841 ] ULMU_PRINT: ulmu_mimo_grp_stats:cd_num_eligible -> (%d, %d, %d, %d ) + +2051,,[ sched_algo_dbg.c : 4845 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_group_eligible_skip -> + +2050,iiiiiiiii,[ sched_algo_dbg.c : 4868 ] ULMU_PRINT: ulmu_mimo_grp_stats:user %d ->( %d, %d, %d, %d, %d, %d, %d, %d) +2049,iiiiiiii,[ sched_algo_dbg.c : 4883 ] ULMU_PRINT: ulmu_mimo_grp_stats: mu_grp_invalid -> (%d, %d, %d, %d, %d, %d, %d, %d ) + +2048,i,[ sched_algo_dbg.c : 4889 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_grp_ineligible -> %d + +2047,iiiii,[ sched_algo_dbg.c : 1074 ] SCHED_LOGS: Peer AID %d: num_schedules = %d, ppdus_queued = %d, mpdus_enqueued = %d, mpdus_failed = %d + +2046,i,[ sched_algo_dbg.c : 4895 ] ULMU_PRINT: ulmu_mimo_grp_stats:mu_grp_eligible -> %d + +2045,II,[ sched_algo_dbg.c : 5032 ] DYN_MIMO_PS sw_peer_id: %u, dyn_mimo_ps_enabled: %u. +2044,,[ sched_algo_dbg.c : 5127 ] punc stats + +2043,i,[ sched_algo_dbg.c : 5130 ] punc vdev %d + +2042,,[ sched_algo_dbg.c : 5143 ] punc bss +2041,,[ sched_algo_dbg.c : 5145 ] punc self +2040,iIIII,[ sched_algo_dbg.c : 5155 ] peer %d, mac %x %x, punc capability %x, host config %x + +2039,i,[ sched_algo_dbg.c : 5176 ] punc case 242 %d + +2038,i,[ sched_algo_dbg.c : 5177 ] punc empty case 242 %d + +2037,i,[ sched_algo_dbg.c : 5178 ] punc case 484 0 %d + +2036,I,[ sched_algo_dbg.c : 1128 ] SCHED_LOGS: Tx_SCHEDULE_CMD Tx mode = %u + +2035,i,[ sched_algo_dbg.c : 5179 ] punc case 484 1 %d + +2034,i,[ sched_algo_dbg.c : 5180 ] punc case 996 0 %d + +2033,i,[ sched_algo_dbg.c : 5181 ] punc case 996 1 %d + +2032,i,[ sched_algo_dbg.c : 5182 ] punc patt 1 %d + +2031,i,[ sched_algo_dbg.c : 5183 ] punc patt 2 %d + +2030,i,[ sched_algo_dbg.c : 5184 ] punc patt 3 %d + +2029,i,[ sched_algo_dbg.c : 5185 ] punc patt 4 %d + +2028,i,[ sched_algo_dbg.c : 5186 ] punc patt %d + +2027,i,[ sched_algo_dbg.c : 5187 ] punc legal_ru dl %d + +2026,i,[ sched_algo_dbg.c : 5188 ] punc legal_ru ul %d + +2025,IIiI,[ sched_algo_dbg.c : 1137 ] SCHED_LOGS: peer_aid = %u, weight = %u, OFDMA_status = %d, ru_width = %u + +2024,i,[ sched_algo_dbg.c : 5189 ] punc TLVs %d + +2023,i,[ sched_algo_dbg.c : 5190 ] punc BW 20 %d + +2022,i,[ sched_algo_dbg.c : 5191 ] punc BW 40 %d + +2021,i,[ sched_algo_dbg.c : 5192 ] punc BW 80 %d + +2020,i,[ sched_algo_dbg.c : 5193 ] punc BW 160 %d + +2019,i,[ sched_algo_dbg.c : 5196 ] punc ru242_idx %d + +2018,I,[ sched_algo_dbg.c : 5297 ] twt_dbg: g_dbg_disable_triggers_from_wmm_txq = %u +2017,I,[ sched_algo_dbg.c : 5410 ] dbg: g_dbg_disable_timeout_based_bsr_trigger = %u +2016,i,[ sched_algo_dbg.c : 5551 ] MBO txmode current AC : %d + +2015,ii,[ sched_algo_dbg.c : 5553 ] MBO txmode %d : %d + +2014,,[ sched_algo_dbg.c : 1142 ] SCHED_LOGS: PPDU_COMPLETION + +2013,I,[ sched_algo_dbg.c : 5578 ] Updated Idle condition trigger count as value = %u +2012,I,[ sched_algo_dbg.c : 5662 ] CV_UPLOAD cv_nc_mismatch : %u +2011,I,[ sched_algo_dbg.c : 5665 ] CV_UPLOAD cv_nr_mismatch : %u +2010,I,[ sched_algo_dbg.c : 5668 ] CV_UPLOAD cv_fb_type_mismatch : %u +2009,I,[ sched_algo_dbg.c : 5671 ] CV_UPLOAD cv_ofdma_bw_mismatch : %u +2008,I,[ sched_algo_dbg.c : 5674 ] CV_UPLOAD cv_bw_mismatch : %u +2007,I,[ sched_algo_dbg.c : 5677 ] CV_UPLOAD cv_pattern_mismatch : %u +2006,I,[ sched_algo_dbg.c : 5680 ] CV_UPLOAD cv_preamble_mismatch : %u +2005,I,[ sched_algo_dbg.c : 5683 ] CV_UPLOAD cv_in_use_cnt_exceeded : %u +2004,I,[ sched_algo_dbg.c : 5686 ] CV_UPLOAD cv_found : %u +2003,IIIIII,[ sched_algo_dbg.c : 1151 ] SCHED_LOGS: peer_aid = %u, ru_size = %u, rtxop = %u, ppdu_duration = %u, nss_usr = %u, BW = %u + +2002,I,[ sched_algo_dbg.c : 5689 ] CV_UPLOAD cv_not_found : %u +2001,I,[ sched_algo_dbg.c : 5692 ] CV_UPLOAD cv_forced_sounding : %u +2000,I,[ sched_algo_dbg.c : 5695 ] CV_UPLOAD cv_standalone_sounding : %u +1999,I,[ sched_algo_dbg.c : 5698 ] CV_UPLOAD cv_total_query : %u +1998,I,[ sched_algo_dbg.c : 5701 ] CV_UPLOAD cv_total_bw_query : %u +1997,I,[ sched_algo_dbg.c : 5704 ] CV_UPLOAD cv_total_pattern_query : %u +1996,I,[ sched_algo_dbg.c : 5918 ] Updated PPDU Max-Min delta threshold as value = %u +1995,i,[ sched_algo_dbg.c : 5954 ] MU Sched Delay: Number of schedules delayed waiting for MU2 = %d +1994,i,[ sched_algo_dbg.c : 5956 ] MU Sched Delay: Number of schedules delayed waiting for MU3 = %d +1993,i,[ sched_algo_dbg.c : 5958 ] MU Sched Delay: Number of schedules delayed waiting for MU4 = %d +1992,II,[ sched_algo_dbg.c : 1158 ] SCHED_LOGS: Last populated index TxScheduleCmd = %u, PPDUCompletion = %u + +1991,I,[ sched_algo_dbg.c : 5994 ] Updated MU-MIMO Idle condition trigger count as value = %u +1990,i,[ sched_algo_dbg.c : 6244 ] SCH_LATENCY : sw_peer_id = %d +1989,i,[ sched_algo_dbg.c : 464 ] atf vdev %d + +1988,iiiiiiii,[ sched_algo_dbg.c : 1340 ] ULMU_PRINT, Avg_FDRSSI NSS:0 - 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, 7:%d +1987,iiiiiiii,[ sched_algo_dbg.c : 1348 ] ULMU_PRINT, Avg_FDRSSI NSS:1 - 0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, 7:%d +1986,iiiiiiii,[ sched_algo_dbg.c : 1372 ] ULMU_PRINT, Avg_FDRSSI_AID NSS:0 - 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, 7:%d, 8:%d +1985,iiiiiiii,[ sched_algo_dbg.c : 1379 ] ULMU_PRINT, Avg_FDRSSI_AID NSS:1 - 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, 7:%d, 8:%d +1984,iiiiiiii,[ sched_algo_dbg.c : 1403 ] ULMU_PRINT, Avg_Target_RSSI AID - 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, 7:%d, 8:%d +2206,IIIII,[ sched_algo_twt.c : 237 ] twt_dbg: twt_construct_cl_super_cycle:peer_id=%u, START_TSF msb=%u, lsb=%u, peer_end_tsf msb=%u, lsb=%u +2205,I,[ sched_algo_twt.c : 246 ] twt_dbg: twt_construct_cl_super_cycle peer_id=%u +2204,IIiII,[ sched_algo_twt.c : 55 ] twt_dbg: twt_scheduler_timer1: tsf_now_msb=%u, lsb=%u, curr_slot_idx=%d, curr_slot_start msb=%u, lsb=%u +2203,iiII,[ sched_algo_twt.c : 62 ] twt_dbg: twt_scheduler_timer1: 5ghz=%d, next_slot_idx=%d, next_slot_start msb=%u, lsb=%u +2202,IIIi,[ sched_algo_twt.c : 97 ] twt_dbg: twt_scheduler_timer:peer_id=%u, peer_end_tsf msb=%u, lsb=%u, twt_qid=%d +2201,IIIIIIII,[ sched_algo_twt.c : 1005 ] twt_dbg_eosp: check_eosp_eligibility:tid_num=%u, inactivity_time_us=%u, last_activity_ts=%u, frms_swq=%u, frms_hwq=%u, is_eosp_eligible=%u,elapsed_time=%u, remaining_time=%u + +2200,II,[ sched_algo_twt.c : 648 ] twt_dbg: twt_peer_register peer_id=%u, twt_peer_count=%u +2199,II,[ sched_algo_twt.c : 652 ] twt_dbg: twt_peer_register g_dbg_disable_triggers_from_wmm_txq = %u; peer->is_wmm_txq_ul_trig_disabled = %u +2198,III,[ sched_algo_twt.c : 697 ] twt_dbg: twt_peer_unregister peer_id=%u, twt_peer_count=%u, peer_twt_state=0x%x +2197,Iii,[ sched_algo_twt.c : 540 ] twt_dbg: sched_algo_twt_sp_info_update peer_id=%u, is_announced=%d, is_ul_received=%d +2196,I,[ sched_algo_twt.c : 567 ] twt_dbg: sched_algo_twt_sp_info_update_triggered_super_cycle peer_id=%u +2195,IIIII,[ sched_algo_twt.c : 487 ] twt_dbg: twt_update_start_end_time peer_id=%u, start_time=%u, end_time=%u, flags=0x%x, valid=%u +2213,IiIiii,[ sched_algo_ul_mumimo.c : 1126 ] UL_MUMIMO_DBG allocate1: peer=0x%x, tid_num=%d, tx_bw_mask=0x%x, ru_size_20=%d, ru_index_20=%d, stream_offset_20=%d +2212,iiiiii,[ sched_algo_ul_mumimo.c : 1137 ] UL_MUMIMO_DBG allocate2: ru_size_40=%d, ru_index_40=%d, ru_size_80=%d, ru_index_80=%d, stream_offset_40=%d, stream_offset_80=%d +2211,iiiiii,[ sched_algo_ul_mumimo.c : 633 ] UL_MUMIMO_PIH_DBG, Use UPH for weak user, weak_user_AID:%d, nss:%d, mcs:%d, max_delta_pwr:%d, tolerable_imb:%d, uph:%d + +2210,iiii,[ sched_algo_ul_mumimo.c : 713 ] UL_MUMIMO_PIH_DBG, After PIH, AID:%d, target_rssi:%d, nss:%d, mcs:%d +2209,iiiiii,[ sched_algo_ul_mumimo.c : 668 ] UL_MUMIMO_PIH_DBG, Power dropped for strong user, strong_user_AID:%d, intf_adjust_pwr:%d, old_pwr:%d, new_pwr:%d, mcs:%d, remaining_delta:%d + +2208,iiii,[ sched_algo_ul_mumimo.c : 689 ] UL_MUMIMO_PIH_DBG, mcs dropped for weak user AID:%d, delta_pwr:%d, old_mcs:%d, new_mcs:%d +2207,iiiiii,[ sched_algo_ul_mumimo.c : 368 ] UL_MUMIMO_PIH_DBG, Before PIH, AID:%d, nss:%d, mcs:%d, target_rssi:%d, uncapped_target_rssi:%d, uph:%d +2217,i,[ sched_algo_ulmu_grouping.c : 949 ] UL_MUMIMO_DBG: truncate UL MU-MIMO candidate list. num_entries %d +2216,i,[ sched_algo_ulmu_grouping.c : 1014 ] UL_MUMIMO_DBG: max_mu_grp_sz: %d +2215,iii,[ sched_algo_ulmu_grouping.c : 490 ] UL_MUMIMO_DBG: sched_algo_construct_ulmu_candidate_table. group size %d, max_intf_nss %d, rc_mode_max %d +2214,i,[ sched_algo_ulmu_grouping.c : 584 ] UL_MUMIMO_DBG: sched_algo_construct_ulmu_candidate_table. number of entries added %d +2222,iiiii,[ sched_algo_qos_result.c : 761 ] ofdma_user_cap: tx_mode: %d, num_users: %d, sta_count_having_short_payload: %d, ul_sta_count_having_low_mcs: %d, truncate_candidate_list: %d +2221,IiIii,[ sched_algo_qos_result.c : 1411 ] ul_dbg_passed_ru_alloc: peer=0x%x, tid_num=%d, pat_mask=0x%x, ru_size_20=%d, ru_index_20=%d +2220,iiii,[ sched_algo_qos_result.c : 1420 ] ul_dbg_passed_ru_alloc_2: ru_size_40=%d, ru_index_40=%d, ru_size_80=%d, ru_index_80=%d +2219,ii,[ sched_algo_qos_result.c : 1694 ] Per user txtime user%d : %d +2218,i,[ sched_algo_qos_result.c : 1617 ] ul_ppdu_count %d + +2227,Ii,[ sched_algo_txbf.c : 788 ] cv_upload_dma invalid SW peer ID cv_buf->sw_peer_id 0x%x pdev_id %d +2226,III,[ sched_algo_txbf.c : 493 ] cbf_mimo_ctrl SW Peer ID %x, Preamble %x, BUF_IDX %x. +2225,IIIIIIII,[ sched_algo_txbf.c : 504 ] cbf_mimo_ctrl NR %x, NC %x, FB %x, BW_FP %x, NG %x, CB %x, BUF_IDX %u, ASNR %x. +2224,IIII,[ sched_algo_txbf.c : 531 ] cbf_mimo_ctrl NC index mismatch. SW_PEER_ID: %u, PEER_NC: %u, CV_NC: %u, Total Mismatch: %u. +2223,Ii,[ sched_algo_txbf.c : 3400 ] cv_upload_dma invalid SW peer ID cv_buf->sw_peer_id 0x%x pdev_id %d +2241,i,[ sched_algo_txbf_ofdma.c : 565 ] ru_to_start_and_end_tone (bw > BW_CNT) bw = %d +2240,ii,[ sched_algo_txbf_ofdma.c : 570 ] ru_to_start_and_end_tone invalid ru_end (ru_end > MAX_RU_PER_BW[%d]) ru_end =%d +2239,ii,[ sched_algo_txbf_ofdma.c : 575 ] ru_to_start_and_end_tone invalid ru_start (ru_start > MAX_RU_PER_BW[%d]) ru_start =%d +2238,ii,[ sched_algo_txbf_ofdma.c : 581 ] ru_to_start_and_end_tone invalid ru_start/ru_end (ru_end < ru_start) ru_start = %d, ru_end = %d +2237,i,[ sched_algo_txbf_ofdma.c : 586 ] ru_to_start_and_end_tone invalid (NG > WAL_TXBF_HE_NG_MAX) ng = %d +2236,,[ sched_algo_txbf_ofdma.c : 591 ] ru_to_start_and_end_tone start_tone is NULL +2235,,[ sched_algo_txbf_ofdma.c : 596 ] ru_to_start_and_end_tone end_tone is NULL +2234,i,[ sched_algo_txbf_ofdma.c : 496 ] ru_to_tone_offset_size (bw > BW_CNT) bw = %d +2233,ii,[ sched_algo_txbf_ofdma.c : 501 ] ru_to_tone_offset_size invalid ru_end (ru_end > MAX_RU_PER_BW[%d]) ru_end =%d +2232,ii,[ sched_algo_txbf_ofdma.c : 506 ] ru_to_tone_offset_size invalid ru_start (ru_start > MAX_RU_PER_BW[%d]) ru_start =%d +2231,ii,[ sched_algo_txbf_ofdma.c : 512 ] ru_to_tone_offset_size invalid ru_start/ru_end (ru_end < ru_start) ru_start = %d, ru_end = %d +2230,i,[ sched_algo_txbf_ofdma.c : 517 ] ru_to_tone_offset_size invalid ng ( ng >= WAL_TXBF_HE_NG_MAX ), ng = %d +2229,,[ sched_algo_txbf_ofdma.c : 522 ] ru_to_tone_offset_size tone_offset is NULL +2228,,[ sched_algo_txbf_ofdma.c : 527 ] ru_to_tone_offset_size num_tones is NULL +2254,iiiiiiii,[ sched_algo_muedca.c : 401 ] MU_EDCA_DEBUG: compute_mu_edca_params: ac: %d, trig_capable_user_count: %d, non_trig_capable_user_count: %d, num_ulmu_non_cap_ax_sta: %d, rx_loading_pct: %d, num_mumimo_txop %d, ul_ppdu: %d, ul_tcp_ppdu: %d +2253,II,[ sched_algo_muedca.c : 434 ] MU_EDCA_DEBUG: OFDMA case MU-EDCA tuning - Trigger Status = %u for AC = %u +2252,IIII,[ sched_algo_muedca.c : 95 ] MU_EDCA_DEBUG: AIFS for BE = %u, CWMIN = %u, num_ax_sta: %u, num_legacy_sta: %u +2251,II,[ sched_algo_muedca.c : 112 ] MU_EDCA_DEBUG: AIFS for VI = %u, CWMIN = %u +2250,IIIII,[ sched_algo_muedca.c : 49 ] MU_EDCA_DEBUG: ULMU- AIFS for BE = %u, CWMIN = %u, num_ax_sta: %u, num_legacy_sta: %u, num_non_ulmu_cap_sta: %u +2249,II,[ sched_algo_muedca.c : 66 ] MU_EDCA_DEBUG: ULMU- AIFS for VI = %u, CWMIN = %u +2248,iiii,[ sched_algo_muedca.c : 604 ] MU_EDCA_DEBUG: ac: %d, aifs_n: %d, cw_min: %d, cw_max: %d +2247,,[ sched_algo_muedca.c : 755 ] MU_EDCA_DEBUG: Running Dynamic MU EDCA update +2246,iiiiii,[ sched_algo_muedca.c : 196 ] MU_EDCA_DEBUG: tune_edca_parameters: trig_capable_user_count: %d, non_trig_capable_user_count: %d, non_ulmu_trig_capable_user_count: %d, rx_loading_pct: %d, curr_state: %d, new_state: %d +2245,iiiii,[ sched_algo_muedca.c : 228 ] MU_EDCA_DEBUG: tune_edca_parameters: applying config to ac %d, old aifs: %d, new aifs: %d, old cwmin: %d, new cwmin: %d +2244,II,[ sched_algo_muedca.c : 674 ] MU_EDCA_DEBUG: Current OFDMA Trigger Status = %u for AC = %u +2243,,[ sched_algo_muedca.c : 570 ] MU_EDCA_DEBUG: Sending WMI MESSAGE +2242,IIII,[ sched_algo_muedca.c : 572 ] MU_EDCA_DEBUG: aifsn be = %u, bk = %u, vi = %u, vo = %u +2269,iiiiiii,[ sched_algo_tx_mode.c : 2156 ] Duration based tx_mode %d, total_psdu_time %d, avg_su_psdu_dur %d, adj_avg_psdu_dur %d, txop_duration %d, max_avg_psdu_dur %d, total_psdu %d + +2268,iiiii,[ sched_algo_tx_mode.c : 2168 ] Duration based num_txop %d, over_head %d, avg_chan_acc_lat_us %d, gain %d, total_latency %d + +2267,iiiiiii,[ sched_algo_tx_mode.c : 2224 ] Duration based tx_mode %d, total_psdu_time %d, avg_su_psdu_dur %d, adj_avg_psdu_dur %d, txop_duration %d, max_avg_psdu_dur %d, total_psdu %d + +2266,iiiii,[ sched_algo_tx_mode.c : 2236 ] Duration based num_txop %d, over_head %d, avg_chan_acc_lat_us %d, gain %d, total_latency %d + +2265,iiiii,[ sched_algo_tx_mode.c : 2264 ] Duration based selected tx mode %d => tx latency %d : Max users %d candidate_list->num_entries %d chan_access_let %d + +2264,iiiiii,[ sched_algo_tx_mode.c : 833 ] OFDMA_SCHED_DECISION: aid: %d, cur_time_ms: %d, use_ul_su_phy_rate: %d, avg_ul_su_phy_rate: %d, rix: %d, phy_rate_kbps: %d +2263,iiii,[ sched_algo_tx_mode.c : 836 ] OFDMA_SCHED_DECISION: aid: %d, cur_time_ms: %d, ul_su_update_time: %d, ul_ofdma_trig_time: %d +2262,iiii,[ sched_algo_tx_mode.c : 876 ] OFDMA_SCHED_DECISION: aid: %d, psd_boost_ref_phy_rate: %d, ul_max_nss: %d, ul_max_bw: %d +2261,iIiiii,[ sched_algo_tx_mode.c : 1809 ] ul_dbg_populate_bsr_CTL: tid_num=%d, tidq=0x%x, sch_inp_lsb=%d,%d last_bsr_lsb=%d, trigger_timeout_ms=%d +2260,i,[ sched_algo_tx_mode.c : 915 ] OFDMA_SCHED_DECISION: num_entries: %d +2259,iiiiI,[ sched_algo_tx_mode.c : 956 ] OFDMA_SCHED_DECISION: aid: %d, avg_txtime_us: %d, avg_ul_qdepth_bytes: %d, txtime_us: %d, qdepth_bytes: %lu +2258,iii,[ sched_algo_tx_mode.c : 973 ] OFDMA_SCHED_DECISION: num_entries: %d, lowq_users: %d, highq_low_mcs_users: %d +2257,ii,[ sched_algo_tx_mode.c : 364 ] Candidate list: Num entries = %d, TX_MODE = %d +2256,ii,[ sched_algo_tx_mode.c : 1631 ] UL_MUMIMO_DBG: select UL MU-MIMO candidate list. num_frms %d, txtime_us %d +2255,iii,[ sched_algo_tx_mode.c : 893 ] OFDMA_SCHED_DECISION: aid: %d, psd_boost_phy_rate_max: %d, phy_rate_estimate %d +2273,IIII,[ sched_algo_tones_li.c : 256 ] tone out of index: preamble:%x, cbf_bw:%x,pkt_bw:%x, ng:%x +2272,IIII,[ sched_algo_tones_li.c : 276 ] tone out of index: preamble:%x,cbf_bw:%x,pkt_bw:%x, ng:%x +2271,IIII,[ sched_algo_tones_li.c : 338 ] tone out of index: preamble:%x,cbf_bw:%x,pkt_bw:%x, ng:%x +2270,IIII,[ sched_algo_tones_li.c : 358 ] tone out of index: preamble:%x, cbf_bw:%x,pkt_bw:%x, ng:%x +2280,,[ wlan_atf.c : 265 ] ATF_DBG:WMI_VDEV_ATF_REQUEST_CMDID is obsolete. Use WMI_PEER_ATF_REQUEST_CMDID instead +2279,IIi,[ wlan_atf.c : 298 ] ATF_DBG:ATF WAL PEER NOT FOUND FOR MAC: 0x%08x 0x%08x ATF-UNITS: %d + +2278,ii,[ wlan_atf.c : 319 ] ATF_DBG:WMI Entry: %d ATF-UNITS: %d + +2277,II,[ wlan_atf.c : 430 ] ATF_DBG:ATF PEER MAC: 0x%08x 0x%08x + +2276,,[ wlan_atf.c : 458 ] ATF_DBG:Invalid WMI command + +2275,i,[ wlan_atf.c : 281 ] ATF_DBG:ATF PEER REQ: NUM-PEERS: %d + +2274,IIi,[ wlan_atf.c : 291 ] ATF_DBG:ATF PEER MAC: 0x%08x 0x%08x NOT FOUND!!! ATF-UNITS: %d + +2283,,[ hca_HwComponentBbLithium_debug.cpp : 230 ] PHYDBG::Dump::Capture enable clear-Timeout + +2282,,[ hca_HwComponentBbLithium_debug.cpp : 941 ] PHYDBG DISABLE: HcaHwComponentBbLithium_debug::PHYDBG_disable +2281,,[ hca_HwComponentBbLithium_debug.cpp : 943 ] PHYDBG disabled + +2297,I,[ hca_HwComponentBbLithium_debug_core.cpp : 559 ] PHYDBG LWod 0x%lx + +2296,I,[ hca_HwComponentBbLithium_debug_core.cpp : 560 ] PHYDBG UWod 0x%lx + +2295,Ii,[ hca_HwComponentBbLithium_debug_core.cpp : 300 ] %s skipping bank %d + +2294,I,[ hca_HwComponentBbLithium_debug_core.cpp : 510 ] PHYDBG_CAPTURE_U 0x%lx + +2293,I,[ hca_HwComponentBbLithium_debug_core.cpp : 511 ] PHYDBG_CAPTURE_L 0x%lx + +2292,I,[ hca_HwComponentBbLithium_debug_core.cpp : 512 ] PHYDBG_PLAYBACK_U 0x%lx + +2291,I,[ hca_HwComponentBbLithium_debug_core.cpp : 513 ] PHYDBG_PLAYBACK_L 0x%lx + +2290,I,[ hca_HwComponentBbLithium_debug_core.cpp : 514 ] PHYDBG_PHYRF_TX_PRE_DESC_WR_1_L 0x%lx + +2289,I,[ hca_HwComponentBbLithium_debug_core.cpp : 515 ] PHYDBG_WFAX_PHYRF_PHYRF_ACTIVATION_CTRL_L 0x%lx + +2288,I,[ hca_HwComponentBbLithium_debug_core.cpp : 516 ] PHYDBG_MODE_L 0x%lx + +2287,I,[ hca_HwComponentBbLithium_debug_core.cpp : 517 ] PHYDBG_TRIGGER_0_L 0x%lx + +2286,I,[ hca_HwComponentBbLithium_debug_core.cpp : 518 ] PHYDBG_TRIGGER_0_U 0x%lx + +2285,I,[ hca_HwComponentBbLithium_debug_core.cpp : 519 ] PHYDBG_TRIGGER_1_L 0x%lx + +2284,Ii,[ hca_HwComponentBbLithium_debug_core.cpp : 404 ] %s skipping bank %d + +2301,iiIiiiiii,[ hca_HwComponentBbLithium_dfs_phyerr_tlv.cpp : 295 ] DFS_DUMPS ts=%d diff_ts=%d sidx=%i dur=%d chirp=%d det=%d radar_check=%d agc_event=%d rssi=%d +2300,iiiii,[ hca_HwComponentBbLithium_dfs_phyerr_tlv.cpp : 301 ] DFS_DUMPS ts=%d delta_peak=%d delta_diff=%d total_gain=%d is_max_pw=%d +2299,iiiii,[ hca_HwComponentBbLithium_dfs_phyerr_tlv.cpp : 325 ] DFS_DUMP radar summary detection_mode=%d timestamp=%d pulse_rssi=%d is_chirp=%d sidx=%d + +2298,iiiiiIiii,[ hca_HwComponentBbLithium_dfs_phyerr_tlv.cpp : 192 ] DFS_DUMPS ts=%d fft_num=%d radar_check=%d total_gain=%d base_pwr=%d peak_sidx=%i relpwr=%d peak_mag=%d num_str_bins_ib=%d + +2311,ii,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 477 ] DFS_DUMP Dfs0Sighandler pHandle=%d ipc_ring_id=%d + +2310,ii,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 485 ] DFS_DUMP Dfs1Sighandler pHandle=%d ipc_ring_id=%d + +2309,ii,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 495 ] DFS_DUMP Dfs2Sighandler pHandle=%d ipc_ring_id=%d + +2308,,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 268 ] FFT_RAW START + +2307,II,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 272 ] FFT_RAW %p 0x%x + +2306,II,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 276 ] FFT_RAW %p 0x%x + +2305,II,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 278 ] FFT_RAW %p 0x%x + +2304,II,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 279 ] FFT_RAW %p 0x%x + +2303,,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 284 ] FFT_RAW END + +2302,iii,[ hca_HwComponentBbLithium_dfs_process_phyerr.cpp : 458 ] DFS_DUMP pcss_ipc_sig_handler_process_multiple_ring_element pHandle=%d ipc_ring_id=%d num_bufs=%d + +2339,III,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 322 ] DFS_DUMPS Rejecting Radar since delta peak values are invalid : dl_delta_peak_match_count=%lu, dl_psidx_diff_match_count=%lu, rf_threshold=%lu + +2338,IIi,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 327 ] DFS_DUMPS %s: Rejecting Radar since duration diff %ld is more than %d + +2337,i,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 469 ] [%d]: dfs is NULL +2336,i,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 566 ] [%d]: event is NULL +2335,i,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 583 ] DFS_DUMPS Rejecteing as radar injected in non-DFS channel, freq offset=%d +2334,iiIIII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 808 ] +[%d]:PHYERR# = %d ts = %u diff_ts = %u ppdu_rssi = %u dur = %u + +2333,iiiiii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 812 ] +[%d]: is_hw_chirp = %d segid = %d sidx = %d peak_mag = %d delta_peak = %d + +2332,iiiiIi,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 816 ] +[%d]: delta_diff = %d agc_total_gain = %d agc_mb_gain = %d radar_subchan_mask = 0x%x pulse_height = %d + +2331,iiiii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 821 ] +[%d]: triggering_agc_event = %d rs_pulse_rssi = %d pri80_inband_power = %d ext80_inband_power = %d + +2330,iIIIII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 825 ] [%d]:xxxxx ts =%u re.re_dur=%u re.re_rssi =%u diff =%u pl->pl_lastelem.p_time=%llu xxxxx +2329,Ii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 904 ] :chan->ic_flags=0x%x, MHz separation=%d + +2328,iii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 908 ] : Peak Idx =%d,re.re_dur =%d,diff_ts =%d + +2327,,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 911 ] +: Modify pulse dur to fit valid range + +2326,Ii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 940 ] +:chan->ic_flags=0x%x,MHz Separation=%d + +2325,iii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 944 ] :Peak Index =%d,re.re_dur =%d,diff_ts =%d + +2324,,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 947 ] :Modify ETSI pulse dur to valid range + +2323,,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1005 ] DFS_DUMPS found bin5 radar + +2322,iII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1045 ] [%d]: Rejecting on rssi rssi=%u thresh=%u +2321,ii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1046 ] DFS_DUMPS Rejecting pulses on rssi rssi=%d, thresh=%d + +2320,iII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1077 ] [%d]:Rejecting on pri pri=%lld minpri=%u +2319,iiII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1110 ] [%d]:filterID= %d::Rejecting on individual filter min PRI deltaT=%lld rf->rf_minpri=%u +2318,iiII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1133 ] [%d]:filterID= %d :: Rejecting on individual filter max PRI deltaT=%lld rf->rf_minpri=%u +2317,iiII,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1178 ] [%d]:filterID= %d :: Rejecting on individual filter max PRI deltaT=%lld rf->rf_minpri=%u +2316,iiii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1252 ] [%d]:### Found on channel minDur = %d, filterId = %d seg_id = %d ### +2315,iiii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1300 ] DFS_DUMPS Radar Found with Filter Id = %d min dur=%d sidx=%d freq_offset=%d + +2314,ii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1307 ] CHANNEL_CLOSE radarevent g_dfs_test_mode=%d event_data.detection_mode=%d + +2313,iiii,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1338 ] [%d]:### RADAR FOUND ON CHANNEL %d (%d MHz),seg_id=%d ### +2312,i,[ hca_HwComponentBbLithium_dfs_process_radarevent.cpp : 1408 ] DFS_DEBUGS false_radar dfs->dfs_seq_num =%d + +2340,i,[ hca_HwComponentBbLithium_pcss_ipc.cpp : 534 ] PcssIpcRingIRQHandler: PS Mode, ignoring IPC Ring IRQ! phyId:%d +2341,I,[ hca_HwComponentBbLithium_phy.cpp : 141 ] %s + +2348,iI,[ hca_HwComponentBbQcn9000_ani.cpp : 282 ] ANI_EDCCA_PHYID%d MAX_ED_CCA=0x%x + +2347,iIII,[ hca_HwComponentBbQcn9000_ani.cpp : 300 ] ANI_EDCCA_PHYID%d ED_A_VAL=0x%x ED_B_VAL=0x%x ED_C_VAL=0x%x + +2346,iII,[ hca_HwComponentBbQcn9000_ani.cpp : 177 ] ANI_DUMP_PHYID%d DISABLED ANI rxtd_rssi_thr_l=%x rxtd_rssi_thr_u=%x + +2345,iI,[ hca_HwComponentBbQcn9000_ani.cpp : 118 ] ANI_DUMP OFDM DL=%d RSSI_THR_L =%x + +2344,iii,[ hca_HwComponentBbQcn9000_ani.cpp : 202 ] STR_DET_WAR ERROR RATE %d < %d THR %d + +2343,iii,[ hca_HwComponentBbQcn9000_ani.cpp : 238 ] STR_DET_WAR ERROR RATE %d > %d THR %d + +2342,i,[ hca_HwComponentBbQcn9000_ani.cpp : 258 ] STR_DET_WAR ERROR RATE CONSECUTIVE LESS ERROR Reset Regs THR %d + +2367,,[ hca_HwComponentBbQcn9000_debug.cpp : 212 ] DumpPerfReg: Name, BitMask, BitShift, Value(Hex), Value(Dec) +2366,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 218 ] DumpPerfReg: PHYRF_TPC_GEN_CTRL_L->TARGET_PWR_CLPC_THR_CORR, 0x%x, 0x%x, 0x%x, %d +2365,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 222 ] DumpPerfReg: PHYRF_TPC_GEN_CTRL_L->OLPC_MODE, 0x%x, 0x%x, 0x%x, %d +2364,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 227 ] DumpPerfReg: PHYRF_TPC_GLUT_SETTINGS_L->GLUT_DAC_GAIN_CAL, 0x%x, 0x%x, 0x%x, %d +2363,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 233 ] DumpPerfReg: PHYRF_TPC_GLUT_IDX_8_L->TPC_GLUT_LAST_IDX_DPDTRAIN, 0x%x, 0x%x, 0x%x, %d +2362,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 239 ] DumpPerfReg: PHYRF_TPC_GLUT_IDX_8_L->TPC_GLUT_INIT_IDX_DPDTRAIN, 0x%x, 0x%x, 0x%x, %d +2361,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 244 ] DumpPerfReg: PHYRF_TPC_OLPC_CTRL_L->TPC_SPARE, 0x%x, 0x%x, 0x%x, %d +2360,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 250 ] DumpPerfReg: PHYRF_TPC_CLPC_CTRL_0_L->MASK_OUT_CLPC_ERR_UPDATE, 0x%x, 0x%x, 0x%x, %d +2359,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 255 ] DumpPerfReg: PHYRF_TPC_CLPC_CTRL_0_L->CLPC_ERR_UPDATE_DIS, 0x%x, 0x%x, 0x%x, %d +2358,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 259 ] DumpPerfReg: WFAX_PCSS_VR_OP_PARAMS_3_L->PHYOFF_RCVD, 0x%x, 0x%x, 0x%x, %d +2357,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 263 ] DumpPerfReg: WFAX_PCSS_VR_OP_PARAMS_3_L->PHYON_RCVD, 0x%x, 0x%x, 0x%x, %d +2356,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 267 ] DumpPerfReg: WFAX_PCSS_GLOBAL_CONFIG_L->CF_ACTIVE, 0x%x, 0x%x, 0x%x, %d +2355,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 271 ] DumpPerfReg: WFAX_PCSS_VR_OP_PARAMS_3_U->CHANNEL_NUM, 0x%x, 0x%x, 0x%x, %d +2354,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 275 ] DumpPerfReg: WFAX_PCSS_VR_OP_PARAMS_3_U->RX_DISABLE, 0x%x, 0x%x, 0x%x, %d +2353,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 280 ] DumpPerfReg: WFAX_PCSS_VR_RX_CONFIG_PARAMS_0_L->DCN_COMP_EN, 0x%x, 0x%x, 0x%x, %d +2352,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 285 ] DumpPerfReg: WFAX_PCSS_VR_OP_PARAMS_5_U, 0x%x, 0x%x, 0x%x, %d +2351,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 289 ] DumpPerfReg: RXTD_RSSI_THR_L, 0x%x, 0x%x, 0x%x, %d +2350,IIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 293 ] DumpPerfReg: RXTD_AGC_CCA_THRA_L, 0x%x, 0x%x, 0x%x, %d +2349,iIIIi,[ hca_HwComponentBbQcn9000_debug.cpp : 301 ] DumpPerfReg: PHYRF_PAPRD_CTRL_L_CH%d->PAPRD_ENABLE, 0x%x, 0x%x, 0x%x, %d +2368,I,[ hca_HwComponentBbQcn9000_dfs.cpp : 68 ] DFS_DUMPS: Radar Sub band mask =%x +2369,iiiII,[ hca_HwComponentBbQcn9000_dfs_phyerr_tlv.cpp : 83 ] DFS_DUMP pcss_ipc_sig_handler_process_multiple_ring_element pHandle=%d ipc_ring_id=%d num_bufs=%d read_address=%p readaddressvalue=%p + +2370,ii,[ hca_HwComponentBbQcn9000_pcss.cpp : 133 ] PCSS Version : Branch = %d, Build ID = %d +2372,,[ hca_HwComponentBbQcn9000_preInit.cpp : 236 ] No BDF merge since one of the pointer is NULL or invalid length +2371,i,[ hca_HwComponentBbQcn9000_preInit.cpp : 241 ] golden bdf_calversion : %d +2394,I,[ hca_HwComponentBbQcn9000_reset.cpp : 511 ] PCSS_VR: Indicate ucode on channel/band change UCODE_MODE_MAP writen value %x + +2393,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 360 ] DFS_DUMPS Post Prog Init phyDfsEnMask=%d, synthSelMask=%d + +2392,iii,[ hca_HwComponentBbQcn9000_reset.cpp : 364 ] ASSCAN: Post Prog Init phySscanEnMask=%d, synthSelMask=%d aDfsSynthFreq=%d +2391,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 779 ] PerformPhyOff::BuildId=%d BranchId=%d is not supported + +2390,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 785 ] PerformPhyOff::BuildId=%d BranchId=%d is supported + +2389,Ii,[ hca_HwComponentBbQcn9000_reset.cpp : 797 ] PerformPhyOff:: q6_to_m3_ipc_address=0x%x q6_to_m3_ipc=%d + +2388,Ii,[ hca_HwComponentBbQcn9000_reset.cpp : 809 ] PerformPhyOff::(VR_Q6_TO_M3_10_L) failure status : 0x%x, loopCount=%d + +2387,i,[ hca_HwComponentBbQcn9000_reset.cpp : 832 ] M3_SSR::CheckIfPhyIsOff CF_active: %d +2386,,[ hca_HwComponentBbQcn9000_reset.cpp : 837 ] M3_SSR::CheckIfPhyIsOff:: Forcing CF_ACTIVE LOW +2385,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 842 ] M3_SSR::CheckIfPhyIsOff CF_active: %d readStatus: %d +2384,,[ hca_HwComponentBbQcn9000_reset.cpp : 858 ] CheckIfPhyIsOff::phyOff was not received by uCode, forcing phyOff via Interrupt + +2383,,[ hca_HwComponentBbQcn9000_reset.cpp : 863 ] CheckIfPhyIsOff::phyOff was received by uCode via TLV + +2382,i,[ hca_HwComponentBbQcn9000_reset.cpp : 602 ] ANI_DUMP_PHYID%d SAVE ANI DEFAULTS + +2381,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 186 ] ADFS_DUMPS / ASSCAN SetHwChainMasks phyDfsEnMask=%d phySscanEnMask=%d +2380,iiiIi,[ hca_HwComponentBbQcn9000_reset.cpp : 951 ] ADFS_DUMPS / ASSCAN PostSetChannelAgile phyDfsEnMask=%d, phySscanEnMask=%d, synthSelMask=%d, rxchainmsk=%, txchainmsk=%d +2379,i,[ hca_HwComponentBbQcn9000_reset.cpp : 221 ] Tx_Gain Overrided - %d + +2378,,[ hca_HwComponentBbQcn9000_reset.cpp : 239 ] Tx_Gain Removed + +2377,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 1512 ] Before ShiftChainMask: tx:%d rx:%d +2376,ii,[ hca_HwComponentBbQcn9000_reset.cpp : 1540 ] After ShiftChainMask: tx:%d rx:%d +2375,,[ hca_HwComponentBbQcn9000_reset.cpp : 592 ] CV_UPLOAD_SIGNED Enabled + +2374,,[ hca_HwComponentBbQcn9000_reset.cpp : 595 ] uCode does not advertised CV_UPLOAD_SIGNED Enabled + +2373,,[ hca_HwComponentBbQcn9000_reset.cpp : 732 ] M3_SSR::WarmReset calling CheckIfPhyIsOff +2395,ii,[ hca_HwComponentBbQcn9000_spectral.cpp : 483 ] SSCAN: BinIndices scanMode %d isChan165 %d +2400,,[ hca_HwComponentBbQcn9000_spurMit.cpp : 134 ] SpurMitigation: No 2G Spur freq available + +2399,,[ hca_HwComponentBbQcn9000_spurMit.cpp : 141 ] SpurMitigation: No 6G spur freq available + +2398,,[ hca_HwComponentBbQcn9000_spurMit.cpp : 143 ] SpurMitigation: No 5G spur freq available + +2397,IIII,[ hca_HwComponentBbQcn9000_spurMit.cpp : 498 ] %s PriCount : 0x%lx , 1stPriSpur : 0x%lx , 2ndPriSpur : 0x%lx + +2396,IIII,[ hca_HwComponentBbQcn9000_spurMit.cpp : 499 ] %s ExtCount : 0x%lx , 1stExtSpur : 0x%lx , 2ndExtSpur : 0x%lx + +2428,II,[ phyDevLib.c : 371 ] PDL_CAL_FUNC: func=phyADCCal calCmdId=0x%x RC=0x%x + +2427,I,[ phyDevLib.c : 371 ] PDL_CAL_FUNC: func=phyADCCal calCmdId=NULL RC=0x%x + +2426,II,[ phyDevLib.c : 431 ] PDL_CAL_FUNC: func=phyAdcCal calCmdId=0x%x RC=0x%x + +2425,I,[ phyDevLib.c : 431 ] PDL_CAL_FUNC: func=phyAdcCal calCmdId=NULL RC=0x%x + +2424,II,[ phyDevLib.c : 166 ] PDL_CAL_FUNC: func=phyCombinedCal calCmdId=0x%x RC=0x%x + +2423,I,[ phyDevLib.c : 166 ] PDL_CAL_FUNC: func=phyCombinedCal calCmdId=NULL RC=0x%x + +2422,II,[ phyDevLib.c : 321 ] PDL_CAL_FUNC: func=phyDACCal calCmdId=0x%x RC=0x%x + +2421,I,[ phyDevLib.c : 321 ] PDL_CAL_FUNC: func=phyDACCal calCmdId=NULL RC=0x%x + +2420,II,[ phyDevLib.c : 326 ] PDL_CAL_FUNC: func=phyIM2Cal calCmdId=0x%x RC=0x%x + +2419,I,[ phyDevLib.c : 326 ] PDL_CAL_FUNC: func=phyIM2Cal calCmdId=NULL RC=0x%x + +2418,II,[ phyDevLib.c : 386 ] PDL_CAL_FUNC: func=phyPALCal calCmdId=0x%x RC=0x%x + +2417,I,[ phyDevLib.c : 386 ] PDL_CAL_FUNC: func=phyPALCal calCmdId=NULL RC=0x%x + +2416,II,[ phyDevLib.c : 171 ] PDL_CAL_FUNC: func=phyPDCCal calCmdId=0x%x RC=0x%x + +2415,I,[ phyDevLib.c : 171 ] PDL_CAL_FUNC: func=phyPDCCal calCmdId=NULL RC=0x%x + +2414,II,[ phyDevLib.c : 186 ] PDL_CAL_FUNC: func=phyPkDetCal calCmdId=0x%x RC=0x%x + +2413,I,[ phyDevLib.c : 186 ] PDL_CAL_FUNC: func=phyPkDetCal calCmdId=NULL RC=0x%x + +2412,II,[ phyDevLib.c : 915 ] PDL_CAL_FUNC: func=phyRSTCal calCmdId=0x%x RC=0x%x + +2411,I,[ phyDevLib.c : 915 ] PDL_CAL_FUNC: func=phyRSTCal calCmdId=NULL RC=0x%x + +2410,II,[ phyDevLib.c : 296 ] PDL_CAL_FUNC: func=phyRxBBFCal calCmdId=0x%x RC=0x%x + +2409,I,[ phyDevLib.c : 296 ] PDL_CAL_FUNC: func=phyRxBBFCal calCmdId=NULL RC=0x%x + +2408,II,[ phyDevLib.c : 156 ] PDL_CAL_FUNC: func=phyRxDCOCal calCmdId=0x%x RC=0x%x + +2407,I,[ phyDevLib.c : 156 ] PDL_CAL_FUNC: func=phyRxDCOCal calCmdId=NULL RC=0x%x + +2406,II,[ phyDevLib.c : 391 ] PDL_CAL_FUNC: func=phySetTPC calCmdId=0x%x RC=0x%x + +2405,I,[ phyDevLib.c : 391 ] PDL_CAL_FUNC: func=phySetTPC calCmdId=NULL RC=0x%x + +2404,II,[ phyDevLib.c : 376 ] PDL_CAL_FUNC: func=phyTIAdcCal calCmdId=0x%x RC=0x%x + +2403,I,[ phyDevLib.c : 376 ] PDL_CAL_FUNC: func=phyTIAdcCal calCmdId=NULL RC=0x%x + +2402,II,[ phyDevLib.c : 301 ] PDL_CAL_FUNC: func=phyTxBBFCal calCmdId=0x%x RC=0x%x + +2401,I,[ phyDevLib.c : 301 ] PDL_CAL_FUNC: func=phyTxBBFCal calCmdId=NULL RC=0x%x + +2433,i,[ phyDevLibCommon.c : 71 ] Error: Invalid PHY ID [=%d] +2432,II,[ phyDevLibCommon.c : 129 ] Dumping PDMEM: [0x%08lx : 0x%08lx] +2431,,[ phyDevLibCommon.c : 134 ] Dumping PDMEM Done +2430,I,[ phyDevLibCommon.c : 92 ] Switch WCSS ENV to %s +2429,,[ phyDevLibCommon.c : 46 ] register polling disabled +2435,,[ phyIniAg.c : 411 ] Error: cannot commit NULL table! +2434,iI,[ phyIniAg.c : 438 ] Note: table filtered out. table[%d].filter = %c +2438,I,[ phy_dev_init.c : 281 ] Fatal Error! Invalid PHY ID[=%lu]. +2437,I,[ phy_dev_init.c : 89 ] wlan base: 0x%x +2436,III,[ phy_dev_init.c : 99 ] CHIP: %s ENV: %s VER: %s +2451,Ii,[ m3_init.c : 98 ] %s: phy%d +2450,,[ m3_init.c : 119 ] M3 Reset de-asserted [Running @640MHz] +2449,i,[ m3_init.c : 120 ] Polling for boot completion ... [max_poll_count = %d] +2448,,[ m3_init.c : 136 ] Warning: Max Poll Count Exceeded +2447,,[ m3_init.c : 143 ] M3 is idle +2446,,[ m3_init.c : 148 ] Alert: M3 has reported boot failure +2445,,[ m3_init.c : 156 ] Error: Could not detect M3 Boot completion +2444,,[ m3_init.c : 105 ] M3 is already Running. Asserting Reset +2443,,[ m3_init.c : 230 ] Recipe Complete +2442,,[ m3_init.c : 197 ] invalid phym3 binary, skip loading +2441,,[ m3_init.c : 201 ] Loading PDMEM (may take few minutes)... +2440,iIIII,[ m3_init.c : 207 ] seg%d: buf: %p dsize: %x msize: %x offset: %x +2439,,[ m3_init.c : 211 ] Loading PDMEM done +2458,ii,[ m3Config.c : 353 ] [uCode] Branch=%d Ver=%d +2457,i,[ m3Config.c : 357 ] Warning: uCode version mismatch detected [Expected Ver >= %d] +2456,i,[ m3Config.c : 114 ] Fatal Error: Invalid PHYID[=%d] +2455,I,[ m3Config.c : 239 ] forceCrashMask=0x%0.08x +2454,,[ m3Config.c : 269 ] DFS INI programmed +2453,i,[ m3Config.c : 126 ] phyM3Ini: phyId = %d +2452,,[ m3Config.c : 293 ] SPECTRAL SCAN INI programmed +2462,i,[ phy_dev_setChainMask.c : 130 ] phySetChainMask: setting chain mask for phyId = %d ... +2461,,[ phy_dev_setChainMask.c : 134 ] RXCHMASK will be forced to 0x1 +2460,i,[ phy_dev_setChainMask.c : 188 ] phySetChainMask: chain mask for phyId = %d completed +2459,iiI,[ phy_dev_setChainMask.c : 133 ] Warning: [PHYID=%d isSBS=%d RXCHMASK=0x%X] is not supported. +2464,i,[ phy_dev_setXbar.c : 75 ] phySetXbar: setting xbar for phyId = %d ... +2463,i,[ phy_dev_setXbar.c : 88 ] phySetXbar: xbar for phyId = %d completed +2466,iiii,[ phyHeavyClip.c : 219 ] isHcEn_qcn90xx : mcs[%d] nss[%d] pktType[%d] hcEn [%d] +2465,iii,[ phyHeavyClip.c : 259 ] heavyClipPerMcs:%d, heavyClipEnablePktType:%d, heavyClipNssThreshold:%d +2469,IIII,[ phyInitCfoCsr.c : 114 ] fc=%f fcPri20=%f shft_pri80in160=%f cfoCorrFracFloat=%f +2468,III,[ phyInitCfoCsr.c : 147 ] cfoCorrFracPri80=%hhd cfoCorrFracSec80=%hhd cfoCorrFrac_80in160=%hhd +2467,II,[ phyInitCfoCsr.c : 159 ] vsrc_ppm_fc_factor(%uMHz) = %u +2471,,[ phyRegIni.c : 336 ] DFS INI programmed +2470,,[ phyRegIni.c : 383 ] Sscan INI programmed +2491,,[ phyReset.c : 867 ] RxDco Cal complete. + +2490,i,[ phyReset.c : 93 ] [phyId=%d] +2489,i,[ phyReset.c : 96 ] [bandCode=%d] +2488,I,[ phyReset.c : 97 ] [rxChMask=0x%x] +2487,i,[ phyReset.c : 98 ] [dynPriChn=%d] +2486,i,[ phyReset.c : 99 ] [band_center_freq1=%dMHz] +2485,i,[ phyReset.c : 100 ] [band_center_freq2=%dMHz] +2484,I,[ phyReset.c : 101 ] [loadIniMask=0x%x] +2483,I,[ phyReset.c : 94 ] [phyBase=0x%0.08x] +2482,i,[ phyReset.c : 95 ] [bwCode=%d] +2481,,[ phyReset.c : 822 ] Recipe Complete phyChannelSwitch_qcn90xx +2480,,[ phyReset.c : 136 ] (Start) +2479,,[ phyReset.c : 153 ] (End) +2478,,[ phyReset.c : 848 ] Recipe Complete +2477,,[ phyReset.c : 111 ] phyRegAccessPass +2476,,[ phyReset.c : 707 ] Error: Skipping phyReset since reset_input is NULL!! +2475,I,[ phyReset.c : 712 ] [phyResetCtrl=0x%x] +2474,,[ phyReset.c : 717 ] Error: phyRegAccess Failed +2473,I,[ phyReset.c : 718 ] Skipping phyReset for [phyBase = 0x%0.08X] +2472,,[ phyReset.c : 781 ] Recipe Complete phyReset_qcn90xx +2493,i,[ phySetRx11bDetThr.c : 67 ] phySetRx11bDetCorrThr: Warning: numRxChain = %d was unexpected! +2492,,[ phySetRx11bDetThr.c : 78 ] Recipe Complete +2494,I,[ phySetRxfePerNrx.c : 139 ] numChains = %lu +2498,i,[ phyCfrCirCap.c : 41 ] Enable CFR ini programming phyId=%d +2497,i,[ phyCfrCirCap.c : 52 ] Restoring Enable CFR ini programed phyId=%d +2496,i,[ phyCfrCirCap.c : 63 ] Enable CFR ini programming phyId=%d +2495,i,[ phyCfrCirCap.c : 74 ] Restoring Enable CFR ini programed phyId=%d +2500,i,[ phyRtt.c : 41 ] RTT per busrt ini programming phyId=%d +2499,i,[ phyRtt.c : 53 ] Restoring RTT per burst ini programed phyId=%d +2502,iii,[ phySpurMitigation.c : 147 ] numberOfSpurs = %d + spur1Offset = %d + spur2Offset = %d +2501,I,[ phySpurMitigation.c : 248 ] WFAX_RXTD_NOTCH_CNTL_1_L = 0x%lx +2504,,[ phyWarmRst.c : 43 ] Executing Warm Reset on PHYA +2503,,[ phyWarmRst.c : 49 ] RECIPE COMPLETE +2505,iiiI,[ phyVersion.c : 18 ] HDL Version %d.%d.%d (Released On %s) +2581,iiiiii,[ phyrf_ani.c : 141 ] ANI NFREAD%d PHYID=%d NFInDBr=%d NFToDBm=%d maxNumChain=%d maxNFInDBm=%d +2580,iii,[ phyrf_ani.c : 151 ] ANI_LOG: PHY Id %d ETSI Domain - maxNFInDBm=%d, DL_MAX value =%d +2579,ii,[ phyrf_ani.c : 156 ] ANI_LOG PHY Id %d DL_MAX value =%d +2578,iiii,[ phyrf_ani.c : 186 ] ANI_EDCCA_PHYID%d CHAIN%d NFBDF=%d NFRUNTIME=%d +2577,iiiiII,[ phyrf_ani.c : 197 ] ANI_EDCCA_PHYID%d NFBDF=%d NFRUNTIME=%d DELTA=%d txChainMask=0x%x rxChainMask=0x%x +2576,i,[ phyrf_ani.c : 216 ] ANI_API_PHYID%d API: ANI CONFIGURE +2575,iiiii,[ phyrf_ani.c : 272 ] ANI_DUMP_PHYID%d DL_OFDM %d DL_CCK %d DL_MIN %d DL_MAX %d + +2574,iiii,[ phyrf_ani.c : 274 ] ANI_DUMP_PHYID%d DL_OFDM %d DL_MIN %d DL_MAX %d + +2573,iiiiiiii,[ phyrf_ani.c : 462 ] ANI_LOG PHYB POLL %dms LISTEN %dms: OFDM %d LSIG %d CCK %d SIZ1 %d M %d OFDM_DL -%d + +2572,iiiiiiii,[ phyrf_ani.c : 464 ] ANI_LOG PHYB POLL %dms LISTEN %dms: OFDM %d LSIG %d CCK %d SIZ1 %d M %d OFDM_DL %d + +2571,iiiiiiii,[ phyrf_ani.c : 466 ] ANI_LOG PHYB POLL %dms LISTEN %dms: OFDM %d LSIG %d CCK %d SIZ1 %d M %d OFDM_DL -%d + +2570,iiiiiiii,[ phyrf_ani.c : 468 ] ANI_LOG PHYB POLL %dms LISTEN %dms: OFDM %d LSIG %d CCK %d SIZ1 %d M %d OFDM_DL %d + +2569,iiiiiii,[ phyrf_ani.c : 478 ] ANI_LOG PHYA1 POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL -%d + +2568,iiiiiii,[ phyrf_ani.c : 480 ] ANI_LOG PHYA1 POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL %d + +2567,iiiiiii,[ phyrf_ani.c : 485 ] ANI_LOG PHYA0 POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL -%d + +2566,iiiiiii,[ phyrf_ani.c : 487 ] ANI_LOG PHYA0 POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL %d + +2565,iiiiiii,[ phyrf_ani.c : 493 ] ANI_LOG PHYA POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL -%d + +2564,iiiiiii,[ phyrf_ani.c : 495 ] ANI_LOG PHYA POLL %dms LISTEN %dms: OFDM %d LSIG %d SIZ1 %d M %d OFDM_DL %d + +2563,iiii,[ phyrf_ani.c : 828 ] ANI_TIME_PHYID%d CUR_TIME=%d PREV_TIME=%d DIFF_TIME=%d +2562,,[ phyrf_ani.c : 397 ] Error: phyrf_ani_AniReset: pHandle is NULL +2561,i,[ phyrf_ani.c : 401 ] Error: phyrf_ani_AniReset: phyId %d is INVALID +2560,i,[ phyrf_ani.c : 404 ] ANI_LOG PHY%d ANI_RESET +2559,I,[ phyrf_ani.c : 410 ] ANI_CHANNEL_CHANGE - resetCause=%x +2558,ii,[ phyrf_ani.c : 416 ] ANI_CHANNEL_CHANGE - clear ANI histogram counters phyID=%d ,size=%d +2557,iiiii,[ phyrf_ani.c : 598 ] ANI_DUMP_PHYID%d ofdmPhyErrCnt %d lsigPhyErrCnt %d cckPhyErrCnt %d sizing1 %d +2556,iiii,[ phyrf_ani.c : 604 ] ANI_LOW_POWER_CNTR_PHYID%d rxClearCnt %d ccaCntr0 %d time %d + +2555,iii,[ phyrf_ani.c : 605 ] ANI_DUMP_PHYID%d CYCLE_CNT %d time %d + +2554,iii,[ phyrf_ani.c : 613 ] ANI_DUMP_PHYID%d listen time %d retflag %d +2553,ii,[ phyrf_ani.c : 673 ] ANI_DUMP LISTEN_TIME=%d, log_cnt=%d +2552,ii,[ phyrf_ani.c : 693 ] ANI_DUMP_PHYID%d ERROR RATE < %d PERCENT +2551,ii,[ phyrf_ani.c : 708 ] ANI_DUMP_PHYID%d ERROR RATE > %d PERCENT +2550,i,[ phyrf_ani.c : 715 ] ANI_DUMP_PHYID%d CONSECUTIVE ERROR, INCREMENTING DESENSE LEVEL +2549,i,[ phyrf_ani.c : 732 ] ANI_DUMP_PHYID%d CONSECUTIVE LESS ERROR, DECREMENTING DESENSE LEVEL +2548,i,[ phyrf_ani.c : 884 ] ANI_LOG - phyrf_ani_EnableAni - g_ani_enable=%d +2547,ii,[ phyrf_ani.c : 925 ] ANI_DUMP_PHYID%d ENABLED %d +2546,ii,[ phyrf_ani.c : 940 ] ANI_DUMP_PHYID%d DISABLED %d +2545,ii,[ phyrf_ani.c : 1041 ] ANI_DUMP_PHYID%d GET ANI STATE %d +2544,i,[ phyrf_ani.c : 1685 ] phyrf_ani_GetCckLevel (Invalid PHY_ID) phyID=%d +2543,iii,[ phyrf_ani.c : 1697 ] phyrf_ani_GetCckLevel (ANI not enabled) phyID=%d, g_ani_enable[%d]=%d +2542,i,[ phyrf_ani.c : 382 ] ANI_LOG GetListenTime=%d +2541,i,[ phyrf_ani.c : 1661 ] phyrf_ani_GetOfdmLevel (Invalid PHY_ID) phyID=%d +2540,iii,[ phyrf_ani.c : 1673 ] phyrf_ani_GetOfdmLevel (ANI not enabled) phyID=%d, g_ani_enable[%d]=%d +2539,iii,[ phyrf_ani.c : 1248 ] ANI_LOG - OverrideAniDlMinMax aniMode=%d, DL_min=%d, DL_max=%d +2538,I,[ phyrf_ani.c : 1720 ] ANI_LOG- phyrf_ani_SendWmiStatus -ani_wmi_evt_cb=%p +2537,iii,[ phyrf_ani.c : 1176 ] ANI_LOG PHY Id %d SetAniCckImmunLevel g_ani_trigger=%d, pAniParam->dl_cck=%d +2536,ii,[ phyrf_ani.c : 1034 ] ANI_LOG PHYID%d SetAniListenPeriod %d +2535,i,[ phyrf_ani.c : 1122 ] ANI_LOG PHYID%d SetAniOfdmImmunLevel error : ANI Disabled.Cannot set OFDM level +2534,iii,[ phyrf_ani.c : 1149 ] ANI_LOG PHY Id %d SetAniOfdmImmunLevel g_ani_trigger=%d, pAniParam->dl_ofdm=%d +2533,iiii,[ phyrf_ani.c : 1386 ] ANI_LOG - SetAniPollListenDesenseStepSize - PHYID=%d aniMode=%d SetAniPollPeriod=%d SetAniListenPeriod=%d +2532,ii,[ phyrf_ani.c : 1026 ] ANI_LOG PHYID%d SetAniPollPeriod %d +2531,iii,[ phyrf_ani.c : 1337 ] ANI_LOG - SetMinAniDl -MinAniDl_input=%d, DL_min=%d, DL_max=%d +2530,i,[ phyrf_ani.c : 1758 ] ANI_LOG- phyrf_ani_SetWmiTimestamp- Invalid cmd_evt value =%d +2529,iiiiii,[ phyrf_ani.c : 511 ] ANI_LOW_POWER_CNTR_PHYID%d cycleCnt %d txFrameCnt %d rxframecnt %d rxClearCnt %d time %d + +2528,iii,[ phyrf_ani.c : 513 ] ANI_EDCCA_PHYID%d raw_nfdelta=%d pedccaParam->curr_delta=%d + +2527,ii,[ phyrf_ani.c : 544 ] ANI_DUMP PHYID%d ramp_up_time %dms + +2526,ii,[ phyrf_ani.c : 560 ] ANI_DUMP PHYID%d ramp_down_time %dms + +2525,i,[ phyrf_ani.c : 1512 ] ANI-VREG-ERR Invalid ANI hist types =%d +2524,i,[ phyrf_ani.c : 1530 ] ANI-VREG-ERR Channel-frequency (Mhz) =%d +2523,,[ phyrf_ani.c : 1536 ] ANI-VREG-ERR |rx_ofdma_timing_err | rx_cck_fail |mac_tx_abort | mac_rx_abort |phy_tx_abort | phy_rx_abort | phyrf_defer_abort| sizing1_evt | sizing2_evt + +2522,IIIIIIIII,[ phyrf_ani.c : 1551 ] ANI-VREG-ERR |%20u|%13u|%13u|%14u|%13u|%14u|%18u|%13u|%13u + +2521,,[ phyrf_ani.c : 1560 ] ANI-VREG-ERR |RX_PKT_CNT_11A |RX_PKT_CNT_11B |RX_PKT_CNT_11N |RX_PKT_CNT_11AC |RX_PKT_CNT_11AX |RX_PKT_CNT_GF + +2520,IIIIII,[ phyrf_ani.c : 1572 ] ANI-VREG-ERR |%15u|%15u|%15u|%16u|%16u|%14u + +2519,,[ phyrf_ani.c : 1581 ] ANI-VREG-ERR |RX_PKT_CRC_PASS_CNT_11A |RX_PKT_CRC_PASS_CNT_11B |RX_PKT_CRC_PASS_CNT_11N |RX_PKT_CRC_PASS_CNT_11AC |RX_PKT_CRC_PASS_CNT_11AX |RX_PKT_CRC_PASS_CNT_GF + +2518,IIIIII,[ phyrf_ani.c : 1593 ] ANI-VREG-ERR |%24u|%24u|%24u|%25u|%25u|%23u + +2517,,[ phyrf_ani.c : 1602 ] ANI-VREG-ERR |LSIG_ERROR | HTSIG_ERROR |VHTSIG_ERROR |HESIG_ERROR |RXTD_OTA |RXTD_FATAL |TXFD |TXTD |PHYRF + +2516,IIIIIIIII,[ phyrf_ani.c : 1617 ] ANI-VREG-ERR |%11u|%13u|%13u|%12u|%9u|%11u|%5u|%5u|%5u + +2515,,[ phyrf_ani.c : 1626 ] ANI-VREG-ERR |VOTING_FAIL |WEAK_DET_FAIL |STRONG_SIG_FAIL |CCK_FAIL |POWER_SURGE |BTCF_TIMING |BTCF_PACKET_DETECT |COARSE_TIMEOUT + +2514,IIIIIIII,[ phyrf_ani.c : 1640 ] ANI-VREG-ERR |%12u|%14u|%16u|%9u|%12u|%12u|%19u|%14u + +2513,I,[ phyrf_ani.c : 1649 ] ANI-VREG-ERR - Invalid Error TYPE = %x +2512,,[ phyrf_ani.c : 1521 ] ANI-VREG-ERR LIST +2511,i,[ phyrf_ani.c : 1522 ] ANI-VREG-ERR phyId=%d +2510,i,[ phyrf_ani.c : 1523 ] ANI-VREG-ERR Latest index in histogram =%d +2509,i,[ phyrf_ani.c : 1526 ] ANI-VREG-ERR collection_interval = %d ms +2508,,[ phyrf_ani.c : 1528 ] ANI-VREG-ERR collection_interval = 1second +2507,i,[ phyrf_ani.c : 426 ] ANI_DUMP_PHYID%d READ AND CACHE VREG VALUES +2506,iiiii,[ phyrf_ani.c : 319 ] ANI_DUMP_PHYID%d RESTORE DL to %d, prev DL OFDM %d, difftime %d, ANI trigger %d +2660,,[ phyrf_bdf.c : 4963 ] Functionality unavailable now +2659,ii,[ phyrf_bdf.c : 4969 ] phyrf_Get_BDFVersion: SW major : %d , SW minor: %d +2658,I,[ phyrf_bdf.c : 4975 ] phyrf_Get_BDFVersion: setting meta no.: %u +2657,I,[ phyrf_bdf.c : 4987 ] phyrf_Get_BDFVersion: ProjectID: 0x%x +2656,,[ phyrf_bdf.c : 4992 ] phyrf_Get_BDFVersion:OPERATION UNALLOWED +2655,,[ phyrf_bdf.c : 4999 ] phyrf_Set_BDFVersion: Feature support unavailable +2654,,[ phyrf_bdf.c : 4910 ] phyrf_Set_BDFVersion: setting BDF tpl ver. +2653,I,[ phyrf_bdf.c : 4937 ] phyrf_Set_BDFVersion: ProjectID: 0x%x +2652,,[ phyrf_bdf.c : 4939 ] phyrf_Get_BDFVersion: ProjectID:ERROR! OTP WRITE UNALLOWED +2651,I,[ phyrf_bdf.c : 4942 ] phyrf_Set_BDFVersion:WARNING: OTP fused: projectID: 0x%x +2650,,[ phyrf_bdf.c : 4950 ] phyrf_Set_BDFVersion: Feature support unavailable +2649,ii,[ phyrf_bdf.c : 4917 ] phyrf_Set_BDFVersion: major: %d, minor : %d +2648,I,[ phyrf_bdf.c : 4922 ] phyrf_Set_BDFVersion: meta: %u +2647,I,[ phyrf_bdf.c : 4933 ] phyrf_Set_BDFVersion: projectID: 0x%x +2646,iii,[ phyrf_bdf.c : 2518 ] phyrf_bdf_ActivateSARLimitSet enable = %d, Index = %d, chainNum = %d + +2645,iii,[ phyrf_bdf.c : 2548 ] phyrf_bdf_ActivateSARLimitSet SAR version = %d, isDbsMode = %d, SARLimitIdx[chainNum] = %d + +2644,iiii,[ phyrf_bdf.c : 5953 ] [POL_DIV_CTL] NTx:%d cMaxTrue=%d, cMax=%d, NSS:%d +2643,,[ phyrf_bdf.c : 5958 ] [POL_DIV_CTL] NO HALPHY ADJUSTMENTS OF ARRAY GAIN +2642,iii,[ phyrf_bdf.c : 5961 ] [POL_DIV_CTL] Pctl:%d PctlNew:%d AG:%d +2641,IIiii,[ phyrf_bdf.c : 5808 ] [POL_DIV] DeriveXYZmaskandPolDivTxChainMask antennaChainsToAxisMapping: 0x%x CM:0x%x xyzMask[0]:%d [1]:%d [2]:%d +2640,,[ phyrf_bdf.c : 5837 ] [POL_DIV] DeriveXYZmaskperNTxandCmaxperNTx +2639,ii,[ phyrf_bdf.c : 5852 ] [POL_DIV] CTL_DOF: %d ctlDofIndex: %d +2638,iiii,[ phyrf_bdf.c : 5891 ] [POL_DIV] g_xyzMaskperNtx[%d]: %d %d %d +2637,ii,[ phyrf_bdf.c : 5892 ] [POL_DIV] g_cMaxperNTx[%d]: %d +2636,ii,[ phyrf_bdf.c : 5893 ] [POL_DIV] LookupCmaxTrueFlag[%d]: %d +2635,II,[ phyrf_bdf.c : 4614 ] %s:EEPROM i2cResult - %ld +2634,I,[ phyrf_bdf.c : 4619 ] %s:EEPROM Init failed +2633,,[ phyrf_bdf.c : 2884 ] TPC: isFbin is TRUE +2632,i,[ phyrf_bdf.c : 2898 ] TPC: pTpcCalFreq=%d +2631,i,[ phyrf_bdf.c : 2906 ] TPC: chans5G=%d +2630,i,[ phyrf_bdf.c : 2918 ] TPC: chans5G=%d +2629,i,[ phyrf_bdf.c : 2951 ] TPC: chans6G=%d +2628,i,[ phyrf_bdf.c : 1158 ] GetCurrentTempInDegC ::: phyId = %d phy reset in progress +2627,i,[ phyrf_bdf.c : 1163 ] GetCurrentTempInDegC ::: phyId = %d Updating Temperature +2626,,[ phyrf_bdf.c : 5693 ] [LPI_CM_LIMIT] [POL_DIV]: Overridden with debug values +2625,ii,[ phyrf_bdf.c : 5708 ] [LPI_CM_LIMIT] : isPolDiv:%d, NSS:%d +2624,I,[ phyrf_bdf.c : 5713 ] [LPI_CM_LIMIT]: Final LPI CM:0x%x +2623,I,[ phyrf_bdf.c : 5719 ] [LPI_CM_LIMIT]: txBF TRUE Final LPI CM:0x%x +2622,I,[ phyrf_bdf.c : 5732 ] [LPI_CM_LIMIT]: TxBF FALSE Final LPI CM:0x%x +2621,iIii,[ phyrf_bdf.c : 5739 ] [LPI_CM_LIMIT] [POL_DIV]: isPolDiv:%d, poldiv-TxCM:0x%x, NTx:%d NSS:%d +2620,I,[ phyrf_bdf.c : 5745 ] [LPI_CM_LIMIT] [POL_DIV]: TxBF TRUE Final LPI CM:0x%x +2619,I,[ phyrf_bdf.c : 5760 ] [LPI_CM_LIMIT] [POL_DIV]: NTx3 Mode Final LPI CM:0x%x +2618,i,[ phyrf_bdf.c : 1384 ] TPC_DLOFDMA: Target power is %d + +2617,iiii,[ phyrf_bdf.c : 1524 ] DumpTpcPerPacket: rtIdx = %d numStreams %d numChains %d rateCode %d + +2616,iii,[ phyrf_bdf.c : 1569 ] DumpTpcPerPacket: Get Rate target pwr TPC pwr = ch0=%d ch1=%d phy: %d + +2615,iii,[ phyrf_bdf.c : 1579 ] DumpTpcPerPacket: Get Rate CTL pwr TPC pwr = ch0=%d ch1=%d phy: %d + +2614,iii,[ phyrf_bdf.c : 1632 ] DumpTpcPerPacket: Get Rate regulatory pwr TPC pwr = ch0=%d ch1=%d phy: %d + +2613,iii,[ phyrf_bdf.c : 1727 ] DumpTpcPerPacket: Get Rate Miscellaneous pwr TPC pwr = ch0=%d ch1=%d phy: %d + +2612,i,[ phyrf_bdf.c : 5394 ] DumpTpcPerPacket: maxRegAllowedPower:%d + +2611,i,[ phyrf_bdf.c : 5396 ] DumpTpcPerPacket: maxRegAllowedPower:%d + +2610,i,[ phyrf_bdf.c : 5407 ] DumpTpcPerPacket: maxRegAllowedPower:%d + +2609,iii,[ phyrf_bdf.c : 5437 ] DumpTpcPerPacket: Get max tx pwr from regulatory Info Hal-phy call BW:%d , Max_tx_pwr: %d, tx_power:%d + +2608,iii,[ phyrf_bdf.c : 5448 ] DumpTpcPerPacket: Get max tx pwr from regulatory Info Hal-phy call BW:%d , Max_tx_pwr: %d, tx_power:%d + +2607,iii,[ phyrf_bdf.c : 5459 ] DumpTpcPerPacket: Get max tx pwr from regulatory Info Hal-phy call BW:%d , Max_tx_pwr: %d, tx_power:%d + +2606,iii,[ phyrf_bdf.c : 5470 ] DumpTpcPerPacket: Get max tx pwr from regulatory Info Hal-phy call BW:%d , Max_tx_pwr: %d, tx_power:%d + +2605,iiiii,[ phyrf_bdf.c : 5501 ] DumpTpcPerPacket: Get max tx pwr from regulatory Info Hal-phy call %d , isPSD:%d, Max_tx_pwr: %d, curr_BW: %d, adj_BW:%d + +2604,,[ phyrf_bdf.c : 1971 ] phyrf_bdf_GetTpcMaxTxPwr :: Invalid Channel Frequency +2603,iiIi,[ phyrf_bdf.c : 1992 ] GetTpcMaxTxPwr: phyId %d txCM %d rcFlags 0x%x tpc_max_tx_power %d +2602,i,[ phyrf_bdf.c : 2003 ] MaxPwr tpc_max_tx %d + +2601,iiii,[ phyrf_bdf.c : 2505 ] phyrf_bdf_IsDBSMode: isDbsMode %d dbsCheck %d SARLimitIdx[0] %d SARLimitIdx[1] %d +2600,i,[ phyrf_bdf.c : 2289 ] Invalid SAR Version set : %d +2599,i,[ phyrf_bdf.c : 2295 ] Invalid SAR Index set Index: %d +2598,i,[ phyrf_bdf.c : 2310 ] Invalid SAR Index set Index: %d +2597,i,[ phyrf_bdf.c : 2316 ] Invalid SAR Index Index: %d +2596,i,[ phyrf_bdf.c : 2327 ] Invalid SAR Index set for extended SAR for DBS_SAR Index: %d +2595,i,[ phyrf_bdf.c : 2333 ] Invalid SAR Index set for DBS_SAR Index: %d +2594,i,[ phyrf_bdf.c : 2340 ] Invalid SAR Index set for DBS_SAR Index: %d +2593,II,[ phyrf_bdf.c : 4754 ] %s: eeprom addr - %lx +2592,III,[ phyrf_bdf.c : 4755 ] %s: read failed expected - %ld retrived - %ld +2591,i,[ phyrf_bdf.c : 3180 ] phyrf_bdf_SetBoardCalVersion: New CalVersion %d is programmed +2590,,[ phyrf_bdf.c : 3183 ] phyrf_bdf_SetBoardCalVersion: SwCalVersion is zero, if MergeBDF() not executed due to NO-caldata in the board. +2589,II,[ phyrf_bdf.c : 4821 ] %s: eeprom addr - %lx +2588,III,[ phyrf_bdf.c : 4822 ] %s: write failed expected - %ld retrived - %ld +2587,,[ phyrf_bdf.c : 5171 ] DumpTpcPerPacket: Set regulatory Info Hal-phy call + +2586,iiii,[ phyrf_bdf.c : 5172 ] Eirp %d psd %d pwr type %d num_pwr_level %d + +2585,iiii,[ phyrf_bdf.c : 5173 ] Tx_pwr %d %d %d %d + +2584,i,[ phyrf_bdf.c : 5236 ] Final Reg Tx pwr %d + +2583,iiI,[ phyrf_bdf.c : 5327 ] phyrf_bdf_setRegPwrInfo 1 => g_tpc_change[%d][%d] = [%08x] +2582,iiI,[ phyrf_bdf.c : 5332 ] phyrf_bdf_setRegPwrInfo 2 => g_tpc_change[%d][%d] = [%08x] +2681,II,[ phyrf_cal.c : 472 ] NFCAL at reset for phyId %u, start time(ms) : %u +2680,II,[ phyrf_cal.c : 482 ] NFCAL at reset for phyId %u, cal time(ms) : %u +2679,IIIIIII,[ phyrf_cal.c : 884 ] phyid %u, mhz %4u, f1 %4u, f2 %4u, phyMode %2u, calType %2u, calResult %3u +2678,II,[ phyrf_cal.c : 312 ] Periodic NFCAL timer started for phyId %u at time(ms) : %u +2677,II,[ phyrf_cal.c : 322 ] Periodic NFCAL timer stopped for phyId %u at time(ms) : %u +2676,i,[ phyrf_cal.c : 904 ] WAL_CHAN_CHANGE DPDCAL 10ms timer expired for channel %d +2675,IIi,[ phyrf_cal.c : 923 ] WAL_CHAN_CHANGE DPDCAL STATE MC for phyId %u, cal time(ms) : %u cal channel %d +2674,iiiii,[ phyrf_cal.c : 943 ] WAL_CHAN_CHANGE DPDCAL:progress - bHomeChan %d channel %d calChannel %d timerActive %d dpd cal State %d +2673,ii,[ phyrf_cal.c : 946 ] WAL_CHAN_CHANGE DPDCAL: globalCallingContext %d paprd.calValid %d +2672,iIii,[ phyrf_cal.c : 955 ] WAL_CHAN_CHANGE DPDCAL cannot do cal - BDF disabled for phyID %d, currTime(ms) %u, channel %d, home %d +2671,IIi,[ phyrf_cal.c : 987 ] WAL_CHAN_CHANGE DPDCAL timer stopped for phyId %u at time(ms) : %u, channel %d +2670,IIii,[ phyrf_cal.c : 1006 ] WAL_CHAN_CHANGE DPDCAL timer started for phyId %u at time(ms) : %u cal channel %d, tot time by Timer API %d +2669,i,[ phyrf_cal.c : 112 ] Skip Periodic NFCAL for phyId %d +2668,III,[ phyrf_cal.c : 121 ] Periodic NFCAL for phyId %u, with phyoffPhyOn %u, start time(ms) : %u +2667,IIIi,[ phyrf_cal.c : 142 ] Periodic NFCAL for phyId %u, with phyoffPhyOn %u, cal time(ms) : %u reset_done %d +2666,i,[ phyrf_cal.c : 774 ] in phyrf_cal_RunDPDCalibration : %d + +2665,iiiI,[ phyrf_cal.c : 1314 ] cp_stats : total_num_cals %d num_pdev_ids_processed %d buf_length %d buf_ptr 0x%x +2664,iii,[ phyrf_cal.c : 1323 ] cp_stats param_tlv->pdev_ids %d mac_id %d phy_id %d +2663,iiiiii,[ phyrf_cal.c : 1136 ] phyrf_cal_log_calibration_stats : CAL_STATS calProfile %d calType %d cal_triggered_cnt: %d cal_fail_cnt: %d cal_fcs_cnt: %d cal_fcs_fail_cnt: %d +2662,iii,[ phyrf_cal.c : 1176 ] phyrf_cal_log_calibration_stats : CAL_STATS periodicCalType %d cal_triggered_cnt: %d cal_fail_cnt: %d +2661,IIiI,[ phyrf_cal.c : 1228 ] cp_stats cal_type 0x%x cal_profile 0x%x isPeriodic %d cal_info 0x%x +2695,IIII,[ phyrf_cal_sm.c : 943 ] CC::: inside cal_SM_Main, 0x%x, (pHandle=0x%x, smInput=0x%x, pCalSmTable=0x%x) +2694,iIII,[ phyrf_cal_sm.c : 1034 ] CAL SM::: cal type idx=%d, ptrStandalone=%x, pIn=%x, pOut=%x +2693,Iii,[ phyrf_cal_sm.c : 604 ] CC::: generateCalSmTable=0x%x, callingContext=%d, curCalTypeIdx=%d +2692,iiiiiIIi,[ phyrf_cal_sm.c : 651 ] CALSM: globalCallingContext[%d]=%d, mhz=%d, freq1=%d, freq2=%d, phy_mode=%3d, txCM=%2X, Total_cal_time=%d us +2691,ii,[ phyrf_cal_sm.c : 653 ] Summary starts: calibration with globalCallingContext[%d]=%d +2690,iiiii,[ phyrf_cal_sm.c : 669 ] :::::::: %d %d %d %d %d +2689,iI,[ phyrf_cal_sm.c : 717 ] CAL SM::: genCalTable calType=%d hwCalMask 0x%x +2688,iii,[ phyrf_cal_sm.c : 758 ] ADC=%d: calType=%d, ptr_phyrf_cal_sm_table->calTypeVarianceId=%d +2687,iii,[ phyrf_cal_sm.c : 771 ] TIADC_80=%d: calType=%d, ptr_phyrf_cal_sm_table->calTypeVarianceId=%d +2686,iii,[ phyrf_cal_sm.c : 1132 ] CAL SM::: Phy mode=%d, IsTrue160supported=%d, bwcode=%d +2685,Iiii,[ phyrf_cal_sm.c : 198 ] CALSM: %x, callingContext=%d, masterCalDbExist()=%d, isSBS=%d +2684,iiiii,[ phyrf_cal_sm.c : 503 ] :::: shortenPhyId=%d, callingContext = %d, Final doCalFlag = %d, docalFlagRxDCO = %d doCalFlagCombIQ = %d +2683,iiii,[ phyrf_cal_sm.c : 205 ] CALSM: final calDBEnableSetting=%d, final CalTimeOutSetting = %d, final PersistentEnable = %d, ColdBootDfsCalEnable=%d +2682,iiii,[ phyrf_cal_sm.c : 360 ] :::: shortenPhyId=%d, callingContext = %d, Final doCalFlag = %d, doCalFlagCombIQ = %d +2771,,[ phyrf_caldb.c : 4684 ] CALDB ::: CheckCombCalForFCS [PREVIOUS_RECORD == PRESENT_RECORD] +2770,,[ phyrf_caldb.c : 4689 ] CALDB ::: CheckCombCalForFCS [PREVIOUS_RECORD != PRESENT_RECORD] +2769,,[ phyrf_caldb.c : 4694 ] CALDB ::: CheckCombCalForFCS [PRESENT_RECORD = INVALID] +2768,iiiiii,[ phyrf_caldb.c : 4753 ] CheckDpdMemForFCS() : maxChainIdx %d rfChainMask %d cur_tbl_idx %d subModeIndxFor80p80 %d phyId %d, chainIdx %d +2767,IIii,[ phyrf_caldb.c : 4758 ] previous hw tracking table %x , curremt tracking table %x tableValid %d CALDB_STATUS_VALID %d +2766,I,[ phyrf_caldb.c : 4770 ] CB::: CheckDpdMemForFCS() : %x, +2765,,[ phyrf_caldb.c : 4599 ] CALDB ::: CheckRXDCOForFCS [PREVIOUS_RECORD == PRESENT_RECORD] +2764,,[ phyrf_caldb.c : 4604 ] CALDB ::: CheckRXDCOForFCS [PREVIOUS_RECORD != PRESENT_RECORD] +2763,,[ phyrf_caldb.c : 4609 ] CALDB ::: CheckRXDCOForFCS [PRESENT_RECORD = INVALID] +2762,iiiiiIii,[ phyrf_caldb.c : 6138 ] TEMPSEN::: phyId = %d, chainIdx = %d, CBNormalizedOffset=%d, CBTempInC=%d, LastTempInC=%d, getTime=%u, curTempID=%d, CBtempeID=%d +2761,,[ phyrf_caldb.c : 2557 ] Error: pHandle is NULL +2760,i,[ phyrf_caldb.c : 2561 ] Error: phyId %d is INVALID +2759,,[ phyrf_caldb.c : 5018 ] error: pHandle is NULL +2758,i,[ phyrf_caldb.c : 5022 ] error: phyId %d is INVALID +2757,iiii,[ phyrf_caldb.c : 7353 ] chain %d MemDPDValidateCurChSwForFCS %d channel %d rssult %d +2756,,[ phyrf_caldb.c : 3191 ] error: pHandle is NULL +2755,i,[ phyrf_caldb.c : 3195 ] error: phyId %d is INVALID +2754,iiiiii,[ phyrf_caldb.c : 2497 ] CALDB TEMPSEN::: phyId=%d, calType=%d rfChainMask = %d, chainIdx=%d, globalCallingContext=%d, UseAltTableAllowed=%d +2753,I,[ phyrf_caldb.c : 4813 ] CALDB::: IS_FTM_MODE() : %x, DISALBE_RESTORE_FOR_FTM is defined +2752,i,[ phyrf_caldb.c : 6814 ] dualband_enable_phyb = %d + +2751,i,[ phyrf_caldb.c : 1343 ] dual_lo_needed = %d + +2750,IIIII,[ phyrf_caldb.c : 6793 ] CALDB_DEBUG: Frequency table dump Start Freq %u | End freq %u | Sequential Index %u | Master Index %u | TPC mapped freq %u +2749,iiiiiii,[ phyrf_caldb.c : 6530 ] caldB_synopsis: [%d], phyID=%d, mHz=%d, f1=%d, f2=%d, phyMode=%d, fullResetTime(us)=%d +2748,IIII,[ phyrf_caldb.c : 6568 ] caldB_synopsis: RXDCO Valid: 0x%08x 0x%08x, 0x%08x, 0x%08x +2747,II,[ phyrf_caldb.c : 6573 ] caldB_synopsis: RXDCO Addr : 0x%08x 0x%08x +2746,II,[ phyrf_caldb.c : 6575 ] caldB_synopsis: RXDCO Valid: 0x%08x 0x%08x +2745,IIII,[ phyrf_caldb.c : 6600 ] caldB_synopsis: COMIQ Addr : 0x%08x 0x%08x, 0x%08x, 0x%08x +2744,IIII,[ phyrf_caldb.c : 6603 ] caldB_synopsis: COMIQ Valid: 0x%08x 0x%08x, 0x%08x, 0x%08x +2743,IIII,[ phyrf_caldb.c : 6611 ] caldB_synopsis: COMIQ Addr : 0x%08x 0x%08x, 0x%08x, 0x%08x +2742,IIII,[ phyrf_caldb.c : 6614 ] caldB_synopsis: COMIQ Valid: 0x%08x 0x%08x, 0x%08x, 0x%08x +2741,II,[ phyrf_caldb.c : 6619 ] caldB_synopsis: COMIQ Addr : 0x%08x 0x%08x +2740,II,[ phyrf_caldb.c : 6621 ] caldB_synopsis: COMIQ Valid: 0x%08x 0x%08x +2739,i,[ phyrf_caldb.c : 6626 ] caldB_synopsis: No of coldboot channels : %d +2738,IIII,[ phyrf_caldb.c : 6554 ] caldB_synopsis: RXDCO Addr : 0x%08x 0x%08x, 0x%08x, 0x%08x +2737,IIII,[ phyrf_caldb.c : 6557 ] caldB_synopsis: RXDCO Valid: 0x%08x 0x%08x, ;0x%08x, 0x%08x +2736,IIII,[ phyrf_caldb.c : 6565 ] caldB_synopsis: RXDCO Addr : 0x%08x 0x%08x, 0x%08x, 0x%08x +2735,iII,[ phyrf_caldb.c : 6732 ] caldB_synopsis: phyId=%d calFileVersionID=0x%08x calFileRevisionID=0x%08x +2734,,[ phyrf_caldb.c : 277 ] Secondary effrfchnmask: Invalid chainmask config!!! +2733,,[ phyrf_caldb.c : 315 ] Listen effrfchnmask- Invalid chainmask config!!! +2732,i,[ phyrf_caldb.c : 1898 ] CALDB ERROR: invalid band of %d + +2731,,[ phyrf_caldb.c : 1915 ] CALDB ERROR: illegal band access detected! asserting here + +2730,iiiiii,[ phyrf_caldb.c : 2059 ] CALDB :::: frequency=%d, bandw:%d calTypeIdx=%d, *mapToCalGroupIdx=%d, *rfsub =%d, *sequentialSubBandIdx=%d +2729,,[ phyrf_caldb.c : 2081 ] CALDB ERROR: illegal channel access detected! asserting here + +2728,,[ phyrf_caldb.c : 1701 ] error: pHandle is NULL +2727,i,[ phyrf_caldb.c : 1705 ] error: phyId %d is INVALID +2726,III,[ phyrf_caldb.c : 3714 ] CC::: rxiqStart: %x, txiqStart: %x, txloStart: %x +2725,iiIi,[ phyrf_caldb.c : 3904 ] dpdStart address for cur_tbl_idx [%d] chainIdx %d is 0x%x channel %d +2724,,[ phyrf_caldb.c : 3788 ] Error: pHandle is NULL +2723,i,[ phyrf_caldb.c : 3792 ] Error: phyId %d is INVALID +2722,,[ phyrf_caldb.c : 3465 ] error: phyId not matched to system supported number of PHYs. +2721,I,[ phyrf_caldb.c : 7572 ] Error: %s Invalid halphy_update_caldb_cal_channel DPD table address +2720,,[ phyrf_caldb.c : 6926 ] Error: pHandle is NULL +2719,i,[ phyrf_caldb.c : 6930 ] Error: phyId %d is INVALID +2718,iii,[ phyrf_caldb.c : 6958 ] invalid Cal attemps %d chain index %d freq %d +2717,I,[ phyrf_caldb.c : 7542 ] Error: %s Invalid halphy_update_caldb_cal_channel DPD table address +2716,,[ phyrf_caldb.c : 7105 ] Error: pHandle is NULL +2715,i,[ phyrf_caldb.c : 7109 ] Error: phyId %d is INVALID +2714,iii,[ phyrf_caldb.c : 6919 ] update Cal attemps %d chain index %d freq %d +2713,,[ phyrf_caldb.c : 2305 ] error: phyId not matched to system supported number of PHYs. +2712,iii,[ phyrf_caldb.c : 1508 ] Wow mode status operation : %d wow_mode_status (0: master calDB can be access) %d, wow entry cnt=%d +2711,,[ phyrf_caldb.c : 5607 ] ERROR: CalDB checksum failure +2710,,[ phyrf_caldb.c : 5415 ] error: phyId not matched to system supported number of PHYs. +2709,,[ phyrf_caldb.c : 162 ] ERROR: supported phy not match to phyId +2708,I,[ phyrf_caldb.c : 6779 ] eDPD ptr %p +2707,i,[ phyrf_caldb.c : 1418 ] isDFS = %d +2706,iiiiiii,[ phyrf_caldb.c : 6458 ] updating_caldB_synopsis: [%d], phyID=%d, mHz=%d, f1=%d, f2=%d, phyMode=%d, fullResetTime(us)=%d +2705,iII,[ phyrf_caldb.c : 6471 ] updating_caldB_synopsis: RXDCO, chainIdx=%d, Addr=0x%08x, Valid=0x%08x +2704,iiII,[ phyrf_caldb.c : 6486 ] updating_caldB_synopsis: COMBIQ, tableIdx=%d, chainIdx=%d, Addr=0x%08x, Valid=0x%08x +2703,,[ phyrf_caldb.c : 4527 ] Error: pHandle is NULL +2702,i,[ phyrf_caldb.c : 4531 ] Error: phyId %d is INVALID +2701,II,[ phyrf_caldb.c : 7372 ] in fn updateCurChSwMemDpdCal address1 %x = address0 %x + +2700,,[ phyrf_caldb.c : 3558 ] error: pHandle is NULL +2699,i,[ phyrf_caldb.c : 3562 ] error: phyId %d is INVALID +2698,,[ phyrf_caldb.c : 3588 ] error: phyId not matched to system supported number of PHYs. +2697,,[ phyrf_caldb.c : 4300 ] Error: pHandle is NULL +2696,i,[ phyrf_caldb.c : 4304 ] Error: phyId %d is INVALID +2773,i,[ phyrf_cbc.c : 894 ] cbc: ENABLE_CHANNEL_LIST_IN_BDF not defined: repeatLimit=%d +2772,i,[ phyrf_cbc.c : 318 ] CALDB_DEBUG: skipping the wrong channel for the radio : %d + +2791,,[ phyrf_caldb_aging.c : 186 ] REGEN_CALDB: starting +2790,,[ phyrf_caldb_aging.c : 191 ] REGEN_CALDB: Invalid phy Handle. Exiting Caldb regen +2789,,[ phyrf_caldb_aging.c : 197 ] REGEN_CALDB: Invalid phyId. Exiting Caldb regen +2788,,[ phyrf_caldb_aging.c : 204 ] REGEN_CALDB: Software configuration to skip CalDb Regen +2787,,[ phyrf_caldb_aging.c : 220 ] REGEN_CALDB: Invalid Mac Handle. Exiting Caldb regen +2786,,[ phyrf_caldb_aging.c : 232 ] REGEN_CALDB: CALBD CLEARED: +2785,,[ phyrf_caldb_aging.c : 235 ] REGEN_CALDB: INVALID PHYID OR CALDB NOT CLEARED +2784,,[ phyrf_caldb_aging.c : 239 ] REGEN_CALDB: Save the pre regen channel +2783,,[ phyrf_caldb_aging.c : 256 ] REGEN_CALDB: Turning off phy pre regen +2782,II,[ phyrf_caldb_aging.c : 323 ] REGEN_CALDB: Skipping due to invalid PHYID groupMapping[%u][1] is %u +2781,iiii,[ phyrf_caldb_aging.c : 418 ] gurug REGEN_CALDB: calChEntry[%d][%d] %d chIdx %d +2780,,[ phyrf_caldb_aging.c : 469 ] REGEN_CALDB: Restore pre regen channel +2779,,[ phyrf_caldb_aging.c : 480 ] REGEN_CALDB: Turning on phy post regen +2778,I,[ phyrf_caldb_aging.c : 488 ] REGEN_CALDB: completed in %u uSec +2777,,[ phyrf_caldb_aging.c : 95 ] REGEN_CALDB: Invalid Phy Handle +2776,I,[ phyrf_caldb_aging.c : 117 ] REGEN_CALDB: Skipping cal as freq %u is not supported +2775,,[ phyrf_caldb_aging.c : 103 ] REGEN_CALDB: Invalid pdev Handle +2774,,[ phyrf_caldb_aging.c : 109 ] REGEN_CALDB: Invalid Mac Handle +2793,i,[ phyrf_debug.c : 762 ] HALPHY DUMP: WIFITOOL issued with subcommand ID %d +2792,i,[ phyrf_debug.c : 773 ] Invalid or Unsupported halphy debug sub command: %d +2804,ii,[ phyrf_debug_prdd.c : 559 ] PRDD - Invalid number of args (should be %d..%d) +2803,i,[ phyrf_debug_prdd.c : 730 ] PRDD - Invalid PRDD command (should be 0..%d) +2802,,[ phyrf_debug_prdd.c : 735 ] PRDD - Invalid number of args in PRDD command (should be >= 2 args) +2801,I,[ phyrf_debug_prdd.c : 742 ] PRDD - Invalid phyId - should be 0..%lu +2800,,[ phyrf_debug_prdd.c : 701 ] PRDD - Not enough memory to support fixed mode +2799,II,[ phyrf_debug_prdd.c : 454 ] PRDD - No report for phy%u at %u MHz +2798,iii,[ phyrf_debug_prdd.c : 311 ] PRDD - %d MHz, phy%d, 1swT %d ms +2797,iI,[ phyrf_debug_prdd.c : 400 ] PRDD - module%d 0x%08lx +2796,,[ phyrf_debug_prdd.c : 469 ] No PRDD report +2795,i,[ phyrf_debug_prdd.c : 121 ] PRDD - Could not find idx for freq %d +2794,ii,[ phyrf_debug_prdd.c : 964 ] PRDD - channel %d is not found in phy%d +3075,I,[ phyrf_debug_cmd.c : 3039 ] CAL_STATS: CAL PROFILE - COLD_BOOT_CAL (0x%x) +3074,I,[ phyrf_debug_cmd.c : 3042 ] CAL_STATS: CAL PROFILE - FULL_CHAN_SWITCH (0x%x) +3073,I,[ phyrf_debug_cmd.c : 3045 ] CAL_STATS: CAL PROFILE - SCAN_CHAN_SWITCH (0x%x) +3072,I,[ phyrf_debug_cmd.c : 3048 ] CAL_STATS: CAL PROFILE - DPD_SPLIT_CAL (0x%x) +3071,I,[ phyrf_debug_cmd.c : 3051 ] CAL_STATS: CAL PROFILE - TEMP_TRIGEER_CAL (0x%x) +3070,I,[ phyrf_debug_cmd.c : 3054 ] CAL_STATS: CAL PROFILE - POWER_SAVE_WAKE_UP (0x%x) +3069,I,[ phyrf_debug_cmd.c : 3057 ] CAL_STATS: CAL PROFILE - TIMER_TRIGGER_CAL (0x%x) +3068,I,[ phyrf_debug_cmd.c : 3060 ] CAL_STATS: CAL PROFILE - FTM_TRIGGER_CAL (0x%x) +3067,I,[ phyrf_debug_cmd.c : 3063 ] CAL_STATS: CAL PROFILE - POWER_DOWN_DTIM (0x%x) +3066,I,[ phyrf_debug_cmd.c : 3066 ] CAL_STATS: CAL PROFILE - NOISY_ENV_RXDO (0x%x) +3065,I,[ phyrf_debug_cmd.c : 3069 ] CAL_STATS: CAL PROFILE - UNKNOWN_PROFILE (0x%x) +3064,I,[ phyrf_debug_cmd.c : 3079 ] CAL_STATS: CAL TYPE - ADC (0x%x) +3063,I,[ phyrf_debug_cmd.c : 3082 ] CAL_STATS: CAL TYPE - DAC (0x%x) +3062,I,[ phyrf_debug_cmd.c : 3085 ] CAL_STATS: CAL TYPE - NOISE_FLOOR (0x%x) +3061,I,[ phyrf_debug_cmd.c : 3088 ] CAL_STATS: CAL TYPE - RXDCO (0x%x) +3060,I,[ phyrf_debug_cmd.c : 3091 ] CAL_STATS: CAL TYPE - COMB_TXLO_TXIQ_RXIQ (0x%x) +3059,I,[ phyrf_debug_cmd.c : 3094 ] CAL_STATS: CAL TYPE - DPD_MEMORYLESS (0x%x) +3058,I,[ phyrf_debug_cmd.c : 3097 ] CAL_STATS: CAL TYPE - DPD_MEMORY (0x%x) +3057,I,[ phyrf_debug_cmd.c : 3100 ] CAL_STATS: CAL TYPE - IBF (0x%x) +3056,I,[ phyrf_debug_cmd.c : 3103 ] CAL_STATS: CAL TYPE - PDET_AND_PAL (0x%x) +3055,I,[ phyrf_debug_cmd.c : 3106 ] CAL_STATS: CAL TYPE - RXDCO_DTIM (0x%x) +3054,I,[ phyrf_debug_cmd.c : 3109 ] CAL_STATS: CAL TYPE - RXDCO_IQ (0x%x) +3053,I,[ phyrf_debug_cmd.c : 3112 ] CAL_STATS: CAL TYPE - BWFILTER (0x%x) +3052,I,[ phyrf_debug_cmd.c : 3115 ] CAL_STATS: CAL TYPE - PADROOP (0x%x) +3051,I,[ phyrf_debug_cmd.c : 3118 ] CAL_STATS: CAL TYPE - INVALID_CAL_ID (0x%x) +3050,I,[ phyrf_debug_cmd.c : 3128 ] CAL_STATS: CAL TYPE - PERIODIC_NOISE_FLOOR (0x%x) +3049,I,[ phyrf_debug_cmd.c : 3131 ] CAL_STATS: CAL TYPE - PERIODIC_DPD_MEMORYLESS (0x%x) +3048,I,[ phyrf_debug_cmd.c : 3134 ] CAL_STATS: CAL TYPE - PERIODIC_INVALID_CAL (0x%x) +3047,,[ phyrf_debug_cmd.c : 3871 ] AFC: GraceTimeOverride: Invalid number of test arguments +3046,i,[ phyrf_debug_cmd.c : 3877 ] ANI: Invalid PHY ID = %d + +3045,,[ phyrf_debug_cmd.c : 3883 ] AFC: GraceTimeOverride: Invalid of test arguments, grace count should be between 1 - 288 +3044,ii,[ phyrf_debug_cmd.c : 3889 ] AFC: GraceTimeOverride: Updated value is %d, current value is %d +3043,ii,[ phyrf_debug_cmd.c : 3893 ] AFC: GraceTimeOverride: Cannot increase time beyond 24hrs. Updated value is %d, current value is %d +3042,,[ phyrf_debug_cmd.c : 984 ] WIFITOOL: PHYID is not active + +3041,iiii,[ phyrf_debug_cmd.c : 1026 ] ANI_LOG PHYID%d ani_dl_min %d, ani_dl_max %d, error_threshold %d +3040,ii,[ phyrf_debug_cmd.c : 1038 ] ANI_LOG PHYID%d ani_ramp_down %d + +3039,i,[ phyrf_debug_cmd.c : 1047 ] ANI_LOG_ERR - Before- value of ANI histogram=%d +3038,i,[ phyrf_debug_cmd.c : 1049 ] ANI_LOG_ERR - After - value of ANI histogram=%d +3037,,[ phyrf_debug_cmd.c : 1052 ] ANI_LOG_ERR VREG ERR COUNTER VALUES +3036,iiii,[ phyrf_debug_cmd.c : 3431 ] MMHostCmdAvgCFO : num_args %d cmd_id %d phy_id %d sub_cmd_id %d +3035,I,[ phyrf_debug_cmd.c : 3438 ] MMHostCmdAvgCFO : Invalid phyId %u +3034,I,[ phyrf_debug_cmd.c : 3446 ] MMHostCmdAvgCFO : Invalid pHandle for phyId %u +3033,i,[ phyrf_debug_cmd.c : 2228 ] BT_CLOCK_ENABLE: %d +3032,iii,[ phyrf_debug_cmd.c : 3483 ] [cjwu]num_args=%d, args[%d]=%d +3031,,[ phyrf_debug_cmd.c : 3490 ] CTL_SETTING::6G CTL POWER MODE::Invalid test arguments +3030,iiI,[ phyrf_debug_cmd.c : 3501 ] phyId=%d, ctl6g_pwermode=%d, debugFlag0=0x%x +3029,I,[ phyrf_debug_cmd.c : 3153 ] MMHostCmdCalStats : Invalid phyId %u +3028,I,[ phyrf_debug_cmd.c : 3161 ] MMHostCmdCalStats : Invalid pHandle for phyId %u +3027,iiii,[ phyrf_debug_cmd.c : 3172 ] MMHostCmdCalStats : num_args %d cmd_id %d phy_id %d sub_cmd_id %d +3026,,[ phyrf_debug_cmd.c : 3182 ] CAL_STATS : Reset calibration stats +3025,,[ phyrf_debug_cmd.c : 3188 ] CAL_STATS : Valid Cal profiles and cal types +3024,I,[ phyrf_debug_cmd.c : 3196 ] CAL_STATS : Number of cal types in this profile = %u +3023,,[ phyrf_debug_cmd.c : 3211 ] CAL_STATS : Calibration stats for valid Cal profiles and cal types +3022,,[ phyrf_debug_cmd.c : 3219 ] ************************************************ +3021,IIIII,[ phyrf_debug_cmd.c : 3233 ] CAL_STATS : cal_type = %u | cal_triggered_cnt = %u | cal_fail_cnt = %u | cal_fcs_cnt = %u | cal_fcs_fail_cnt = %u +3020,,[ phyrf_debug_cmd.c : 3237 ] ************************************************** +3019,,[ phyrf_debug_cmd.c : 3244 ] CAL_STATS : Calibration stats for valid Periodic Cal profiles and cal types +3018,I,[ phyrf_debug_cmd.c : 3248 ] CAL_STATS : PERIODIC CAL cal_profile = %u +3017,III,[ phyrf_debug_cmd.c : 3258 ] CAL_STATS : cal_type = %u | cal_triggered_cnt = %u | cal_fail_cnt = %u +3016,,[ phyrf_debug_cmd.c : 2726 ] Coldboot Calibration Feature Not Supported +3015,,[ phyrf_debug_cmd.c : 2731 ] Coldboot Calibration Feature: Invalid test arguments +3014,i,[ phyrf_debug_cmd.c : 1790 ] WIFITOOL: PHYID %d is not active + +3013,ii,[ phyrf_debug_cmd.c : 1795 ] EnableDssWarCFO: enable=%d FOR PHYID %d + +3012,iiII,[ phyrf_debug_cmd.c : 2291 ] CHAINMASKOVERRIDE %d - phy[%d]: txChMask 0x%x; rxChMask 0x%x +3011,,[ phyrf_debug_cmd.c : 3627 ] [POL_DIV_DEBUG] Wrong usage of debug command +3010,i,[ phyrf_debug_cmd.c : 3632 ] [POL_DIV_DEBUG] Invalid PHY ID = %d +3009,,[ phyrf_debug_cmd.c : 3641 ] [POL_DIV_DEBUG] CrossPolarization not enabled in BDF. Debug-commands not applicable +3008,i,[ phyrf_debug_cmd.c : 3686 ] [POL_DIV_DEBUG] CrossPolar Disabled isPolDiv:%d +3007,I,[ phyrf_debug_cmd.c : 3690 ] [POL_DIV_DEBUG] Input XYZmask: 0x%x +3006,i,[ phyrf_debug_cmd.c : 3699 ] [POL_DIV_DEBUG] Settings are invalid, please set XYZmask as per CTL_DOF:%d +3005,Ii,[ phyrf_debug_cmd.c : 3702 ] [POL_DIV_DEBUG] Settings are valid polDiv-Tx-Chainmask:0x%x numChains:%d +3004,iiIi,[ phyrf_debug_cmd.c : 3719 ] [POL_DIV_DEBUG] DOF: %d, num-chains: %d BDF-antAxisMap: 0x%x BDF-polDivEN: %d +3003,,[ phyrf_debug_cmd.c : 3722 ] [POL_DIV_DEBUG] Cached values dump +3002,iIi,[ phyrf_debug_cmd.c : 3724 ] [POL_DIV_DEBUG] polDivEn:%d CM:0x%x numChains:%d +3001,i,[ phyrf_debug_cmd.c : 3727 ] [POL_DIV_DEBUG] Cross-polar params dump isPolDiv:%d +3000,iiiiii,[ phyrf_debug_cmd.c : 3741 ] [POL_DIV_DEBUG] g_xyzMaskperNtx[%d]:: Ntx:%d :: %d %d %d CTLxyzMask:%d +2999,,[ phyrf_debug_cmd.c : 3746 ] [POL_DIV_DEBUG] CTL_TOOL_CMax BDF-CMAXtrue lookupCMaxTrueFlag +2998,iiii,[ phyrf_debug_cmd.c : 3748 ] [POL_DIV_DEBUG] [Ntx=%d]: %d %d %d +2997,,[ phyrf_debug_cmd.c : 3755 ] [POL_DIV_DEBUG] Wrong command usage +2996,i,[ phyrf_debug_cmd.c : 3759 ] [POL_DIV_DEBUG] g_dbg_lpi_chain_limit = %d +2995,iii,[ phyrf_debug_cmd.c : 3761 ] [POL_DIV_DEBUG] Phy ID %d | polDiv-debug-Enable: %d | polDiv-TxChainMask: %d +2994,,[ phyrf_debug_cmd.c : 660 ] CTL_DISABLE: Invalid test arguments +2993,,[ phyrf_debug_cmd.c : 666 ] CTL_DISABLE: Invalid phyId +2992,,[ phyrf_debug_cmd.c : 678 ] CTL_DISABLE: Disabling CTL power limits! +2991,,[ phyrf_debug_cmd.c : 683 ] CTL_DISABLE: Enabling back CTL power limits! +2990,,[ phyrf_debug_cmd.c : 2447 ] DFS_ENABLE: Invalid test arguments +2989,,[ phyrf_debug_cmd.c : 2453 ] DFS_ENABLE: Invalid phyId +2988,,[ phyrf_debug_cmd.c : 2669 ] PHYRF_DEBUG_MM_HOST_CMD_SET_DPD_EDPD_ENABLE Invalid Command +2987,Ii,[ phyrf_debug_cmd.c : 2676 ] PHYRF_DEBUG_MM_HOST_CMD_SET_DPD_EDPD_ENABLE: Invalid PHY ID = %u, phyrf_init_GetNumPhys()=%d +2986,i,[ phyrf_debug_cmd.c : 2684 ] PHYRF_DEBUG_MM_HOST_CMD_SET_DPD_EDPD_ENABLE: Invalid pHandle for phyId=%d +2985,iI,[ phyrf_debug_cmd.c : 2691 ] Set g_halphy_dpd_enable[%d] =0x%x + +2984,,[ phyrf_debug_cmd.c : 901 ] DO_NFCAL_ACTION Invalid Command +2983,I,[ phyrf_debug_cmd.c : 908 ] DO_NFCAL_ACTION: Invalid PHY ID = %u +2982,II,[ phyrf_debug_cmd.c : 927 ] DO_NFCAL_ACTION: Setting NF home channl IterCount to %u for phyId = %u +2981,II,[ phyrf_debug_cmd.c : 934 ] DO_NFCAL_ACTION: Setting pResetStruct->nfPeriodicCalControl to %u for phyId %u +2980,II,[ phyrf_debug_cmd.c : 941 ] DO_NFCAL_ACTION: Setting pResetStruct->nfPeriodicCalWithPhyOffPhyOnControl to %u for phyId %u +2979,II,[ phyrf_debug_cmd.c : 948 ] DO_NFCAL_ACTION: Setting pResetStruct->nfResetCalControl to %u for phyId %u +2978,II,[ phyrf_debug_cmd.c : 958 ] DO_NFCAL_ACTION: Triggering NFCAL with flags %x for phyId %u +2977,i,[ phyrf_debug_cmd.c : 1557 ] DSS: WIFITOOL ISSUED TO ENABLE/DISABLE DSS %d + +2976,i,[ phyrf_debug_cmd.c : 1568 ] DSS: G_SYNTH_CONTROL_FTM=%d FOR PHYID 0 + +2975,i,[ phyrf_debug_cmd.c : 1580 ] DSS: G_SYNTH_CONTROL=%d FOR PHYID 0 + +2974,i,[ phyrf_debug_cmd.c : 1770 ] WIFITOOL: PHYID %d is not active + +2973,ii,[ phyrf_debug_cmd.c : 1775 ] SetDssWarCFODeltaThreshold: cfo_threshold=%d FOR PHYID %d + +2972,i,[ phyrf_debug_cmd.c : 2766 ] DUMP_TPC_GLUT_WAKEUP_SLEEP: WIFITOOL ISSUED TO ENABLE TPC GLUT DUMP %d + +2971,,[ phyrf_debug_cmd.c : 2770 ] DUMP_TPC_GLUT_WAKEUP_SLEEP: wifitool : Invalid test arguments +2970,i,[ phyrf_debug_cmd.c : 2775 ] DUMP_TPC_GLUT_WAKEUP_SLEEP: WIFITOOL ISSUED TO DISABLE TPC GLUT DUMP %d + +2969,i,[ phyrf_debug_cmd.c : 2749 ] DUMP_TPC_REGS_ENABLE: WIFITOOL ISSUED TO ENABLE TPC REG DUMP %d + +2968,,[ phyrf_debug_cmd.c : 2753 ] DUMP_TPC_REGS_ENABLE: wifitool : Invalid test arguments +2967,,[ phyrf_debug_cmd.c : 3842 ] ANI: Command arguments Invalid +2966,i,[ phyrf_debug_cmd.c : 3848 ] ANI: Invalid PHY ID = %d + +2965,iii,[ phyrf_debug_cmd.c : 3854 ] ANI: PHYID = %d , value of g_enable_10ms_ani_histogram[%d] = %d + +2964,i,[ phyrf_debug_cmd.c : 3014 ] ENABLE_CHAN_CHANGE_BREAKDOWN: WIFITOOL ISSUED TO ENABLE CHAN CHANGE BREAKDOWN %d + +2963,,[ phyrf_debug_cmd.c : 3018 ] ENABLE_CHAN_CHANGE_BREAKDOWN: wifitool : Invalid test arguments +2962,i,[ phyrf_debug_cmd.c : 3023 ] ENABLE_CHAN_CHANGE_BREAKDOWN: WIFITOOL ISSUED TO DISABLE CHAN CHANGE BREAKDOWN %d + +2961,I,[ phyrf_debug_cmd.c : 1108 ] pResetStruct->enable_ldocal_otp = %u +2960,i,[ phyrf_debug_cmd.c : 1195 ] PAPRD: Invalid PHY ID = %d +2959,ii,[ phyrf_debug_cmd.c : 1199 ] PAPRD: Phy ID %d | Enable for MM = %d +2958,i,[ phyrf_debug_cmd.c : 3516 ] PAPRD: Invalid PHY ID = %d +2957,ii,[ phyrf_debug_cmd.c : 3520 ] PAPRD: Phy ID %d | PAPRD FCS Enable = %d +2956,ii,[ phyrf_debug_cmd.c : 1182 ] ANI_LOG PHYID%d error_threshold %d + +2955,,[ phyrf_debug_cmd.c : 2954 ] wrong no of arguments from unit test command +2954,ii,[ phyrf_debug_cmd.c : 1937 ] DSS: WIFITOOL ISSUED TO FORCED SYNTH phyId %d, Synth %d + +2953,i,[ phyrf_debug_cmd.c : 1940 ] FORCED_SYNTH: Invalid PHY ID = %d +2952,ii,[ phyrf_debug_cmd.c : 1959 ] FORCED SYNTH: G_SYNTH_CONTROL=%d FOR PHYID %d + +2951,ii,[ phyrf_debug_cmd.c : 1964 ] FORCED SYNTH: G_SYNTH_CONTROL=%d FOR PHYID %d + +2950,,[ phyrf_debug_cmd.c : 2913 ] CWOFFSET : wifitool : Invalid test arguments +2949,Ii,[ phyrf_debug_cmd.c : 2919 ] phyrf_debug_MMHostCmdGenerateCWToneAtOffset: Invalid PHY ID = %u, phyrf_init_GetNumPhys()=%d +2948,i,[ phyrf_debug_cmd.c : 2925 ] phyrf_debug_MMHostCmdGenerateCWToneAtOffset: Invalid pHandle for phyId=%d +2947,,[ phyrf_debug_cmd.c : 2941 ] phyrf_debug_MMHostCmdGenerateCWToneAtOffset: Invalid command +2946,,[ phyrf_debug_cmd.c : 3324 ] GET_BDF_FEATURE_FLAGS: wifitool : Invalid test arguments +2945,I,[ phyrf_debug_cmd.c : 3332 ] GET_BDF_FEATURE_FLAGS: Invalid PHY ID = %u +2944,iiII,[ phyrf_debug_cmd.c : 3361 ] GET_BDF_FEATURE_FLAGS: wifitool : nvCaldbEnable=%d calDbPersistentEnable=%d tpc_flag=0x%x commonBoardFlags=0x%x +2943,Iiii,[ phyrf_debug_cmd.c : 3362 ] GET_BDF_FEATURE_FLAGS: wifitool : projectId = 0x%x boardCalVersion=%d, bdfVersion=%d, iniVersion=%d +2942,ii,[ phyrf_debug_cmd.c : 3363 ] GET_BDF_FEATURE_FLAGS: wifitool :templateVersionMajor=%d templateVersionMinor=%d +2941,iii,[ phyrf_debug_cmd.c : 3366 ] GET_BDF_FEATURE_FLAGS: wifitool : dpdEnable =%d regMismatchFeatureEnable=%d antenna_gain_feature_enabled=%d +2940,,[ phyrf_debug_cmd.c : 2786 ] GET BOARD CAL DETAILS : wifitool : Invalid test arguments +2939,ii,[ phyrf_debug_cmd.c : 2790 ] GET BOARD CAL DETAILS : wifitool : SW version : %d.%d +2938,i,[ phyrf_debug_cmd.c : 2792 ] GET BOARD CAL DETAILS : wifitool : Meta version : %d +2937,I,[ phyrf_debug_cmd.c : 2795 ] GET BOARD CAL DETAILS : wifitool : ProjectID in OTP : 0x%x +2936,II,[ phyrf_debug_cmd.c : 1345 ] Unit Test ID %u :: phyrf_bdf_GetAllChanGradeInfo returns A_STATUS :: %u ( Internal Error ) +2935,II,[ phyrf_debug_cmd.c : 1349 ] Unit Test ID %u :: phyrf_bdf_GetAllChanGradeInfo returns A_STATUS :: %u ( No Entry ) +2934,II,[ phyrf_debug_cmd.c : 1353 ] Unit Test ID %u :: phyrf_bdf_GetAllChanGradeInfo returns A_STATUS :: %u ( No Memory) +2933,III,[ phyrf_debug_cmd.c : 1357 ] Unit Test ID %u :: phyrf_bdf_GetAllChanGradeInfo returns A_STATUS :: %u ( Success ), chanGradeInfoCount %u +2932,IIIi,[ phyrf_debug_cmd.c : 1366 ] %u. Freq %u, BW %u, ChanPerfMetric %d +2931,II,[ phyrf_debug_cmd.c : 1371 ] Unit Test ID %u :: phyrf_bdf_GetAllChanGradeInfo returns A_STATUS :: %u ( Unknown Error ) +2930,i,[ phyrf_debug_cmd.c : 1292 ] PCSS: Invalid PHY ID = %d +2929,iiii,[ phyrf_debug_cmd.c : 1279 ] PDL Version : %d.%d - RDL Version : %d.%d +2928,,[ phyrf_debug_cmd.c : 1383 ] GetSignalLevel : Invalid test arguments +2927,,[ phyrf_debug_cmd.c : 1399 ] GetSignalLevel : pHandle not found +2926,IIIII,[ phyrf_debug_cmd.c : 1407 ] GetSignalLevel phyId %u, snrInput %u, chainMask %x, bandwidth %u, combRssi %u +2925,I,[ phyrf_debug_cmd.c : 1411 ] GetSignalLevel : SNR Input %u +2924,III,[ phyrf_debug_cmd.c : 1426 ] GetSignalLevel : SNR BW Segment Input %8x%8x for Chain %u +2923,I,[ phyrf_debug_cmd.c : 1434 ] GetSignalLevel : Returns %u (WHAL_EINVAL) +2922,Ii,[ phyrf_debug_cmd.c : 1443 ] GetSignalLevel : SNR=%u RSSI=%d +2921,IIIIIi,[ phyrf_debug_cmd.c : 1457 ] GetSignalLevel : SNR[%u][%u]=%u RSSI[%u][%u]=%d +2920,I,[ phyrf_debug_cmd.c : 3278 ] GET_START_END_FREQ: Invalid PHY ID = %u +2919,,[ phyrf_debug_cmd.c : 3291 ] GET_START_END_FREQ: wifitool : Invalid test arguments +2918,iiii,[ phyrf_debug_cmd.c : 3295 ] GET_START_END_FREQ : wifitool : low_2ghz_chan = %d high_2ghz_chan=%d low_5ghz_chan=%d high_5ghz_chan=%d +2917,i,[ phyrf_debug_cmd.c : 2365 ] GTXENABLE: Invalid PHY ID = %d +2916,ii,[ phyrf_debug_cmd.c : 2371 ] GreenTx Enable[%d]=%d +2915,i,[ phyrf_debug_cmd.c : 2384 ] ImpsBmpsControl: Invalid PHY ID = %d +2914,ii,[ phyrf_debug_cmd.c : 2395 ] ImpsBmpsControl: enable=%d, phyId=%d +2913,iii,[ phyrf_debug_cmd.c : 2409 ] ImpsBmpsControl: imps=%d, enable=%d, phyId=%d +2912,iiii,[ phyrf_debug_cmd.c : 2428 ] ImpsBmpsControl: imps=%d, w2s=%d, enable=%d, phyId=%d +2911,I,[ phyrf_debug_cmd.c : 3383 ] MMHostCmdLMConfig :: LM_DBG: Invalid phyId %u +2910,I,[ phyrf_debug_cmd.c : 3391 ] MMHostCmdLMConfig :: LM_DBG: Invalid pHandle for phyId %u +2909,,[ phyrf_debug_cmd.c : 2197 ] LP_SYNTH: Invalid test arguments +2908,ii,[ phyrf_debug_cmd.c : 2214 ] LPSYNTHFORLEGACY: WIFITOOL ISSUED TO ENABLE LP SYNTH: legacy rate: %d, dtim: %d + +2907,I,[ phyrf_debug_cmd.c : 1127 ] ANI_LOG g_max_edcca=%x +2906,ii,[ phyrf_debug_cmd.c : 1141 ] ANI_LOG PHYID%d g_ani_cca %d + +2905,iii,[ phyrf_debug_cmd.c : 1161 ] ANI_LOG PHYID%d ani_dl_min %d, ani_dl_max %d + +2904,I,[ phyrf_debug_cmd.c : 1893 ] NFCAL_READ_TEST : phyId %u not available for test +2903,IIIIIi,[ phyrf_debug_cmd.c : 1911 ] NFCAL_READ_TEST : phyId %u, nfType 0x%x, bufferSize %u, validBuffer %u, bufferPointer 0x%x, returns %d +2902,IIIi,[ phyrf_debug_cmd.c : 1919 ] NFCAL_READ_TEST : phyId %u, nfType 0x%x, Chain %u, NFValue %d +2901,,[ phyrf_debug_cmd.c : 3804 ] PaprdTimerOverride: Invalid test arguments +2900,,[ phyrf_debug_cmd.c : 3810 ] PaprdTimerOverride: Invalid phy ID +2899,iii,[ phyrf_debug_cmd.c : 3831 ] PAPRD: Phy ID %d | PAPRDTIMEROVERRIDE %d | Duration ms = %d +2898,,[ phyrf_debug_cmd.c : 2493 ] IpcHandler_Enable: Invalid test arguments +2897,,[ phyrf_debug_cmd.c : 2499 ] IpcHandler_Enable: Invalid phyId +2896,ii,[ phyrf_debug_cmd.c : 2506 ] IpcHandler_Enable: enable=%d, phyId=%d +2895,ii,[ phyrf_debug_cmd.c : 1480 ] PHYDBG: g_phydbg_phy_disable[%d] = %d +2894,,[ phyrf_debug_cmd.c : 1497 ] phydbg_reconfigure : Invalid test arguments +2893,i,[ phyrf_debug_cmd.c : 1505 ] phydbg_reconfigure : Invalid PHY ID = %d + +2892,ii,[ phyrf_debug_cmd.c : 1509 ] phydbg_reconfigure : PHYID = %d ,Event = %d + +2891,,[ phyrf_debug_cmd.c : 2814 ] DebugCmdPhyOnOffSeq : Invalid test arguments +2890,I,[ phyrf_debug_cmd.c : 2821 ] DebugCmdPhyOnOffSeq : Invalid phyId %u +2889,I,[ phyrf_debug_cmd.c : 2829 ] DebugCmdPhyOnOffSeq : Invalid pHandle for phyId %u +2888,I,[ phyrf_debug_cmd.c : 2837 ] DebugCmdPhyOnOffSeq : Invalid pResetStruct for phyId %u +2887,IIII,[ phyrf_debug_cmd.c : 2846 ] DebugCmdPhyOnOffSeq : Pretest Counter phyId %u, cfActiveLow_Fail_cnt %04u, cfActiveLow_Pass_cnt %04u, phyOffThroughVregCnt %04u +2886,I,[ phyrf_debug_cmd.c : 2857 ] DebugCmdPhyOnOffSeq : Validating vreg based phyOff for phyId %u +2885,I,[ phyrf_debug_cmd.c : 2861 ] DebugCmdPhyOnOffSeq : Validating tlv based phyOff followed by vreg based phyOff for phyId %u +2884,I,[ phyrf_debug_cmd.c : 2866 ] DebugCmdPhyOnOffSeq : Validating calling vreg based phyOff twice for phyId %u +2883,I,[ phyrf_debug_cmd.c : 2872 ] DebugCmdPhyOnOffSeq : Validating tlv based phyOff for phyId %u +2882,IIII,[ phyrf_debug_cmd.c : 2885 ] DebugCmdPhyOnOffSeq : Posttest Counter phyId %u, cfActiveLow_Fail_cnt %04u, cfActiveLow_Pass_cnt %04u, phyOffThroughVregCnt %04u +2881,i,[ phyrf_debug_cmd.c : 731 ] BDF DUMP: Invalid NV Section %d +2880,i,[ phyrf_debug_cmd.c : 736 ] BDF DUMP: NV Section Size: %d +2879,ii,[ phyrf_debug_cmd.c : 747 ] BDF DUMP: sub-section size: %d sub-section id: 0x%d +2878,iI,[ phyrf_debug_cmd.c : 753 ] BDF DUMP: index: %d d: 0x%x +2877,iI,[ phyrf_debug_cmd.c : 762 ] BDF DUMP: index: %d d:0x%x +2876,I,[ phyrf_debug_cmd.c : 263 ] RegDumpId %u :: NFCAL_BDF_PER_CHAIN :: Exceptions :: Value = 1 : Chain Unsupported +2875,,[ phyrf_debug_cmd.c : 535 ] REGEN_CALDB: wal_pdev is NULL. Skipping +2874,ii,[ phyrf_debug_cmd.c : 603 ] TT-Chain=%d, Temperature=%d + +2873,II,[ phyrf_debug_cmd.c : 611 ] Avg temp across %u chains=%u +2872,i,[ phyrf_debug_cmd.c : 620 ] DumpPerfReg: PHY ID = %d +2871,,[ phyrf_debug_cmd.c : 624 ] DumpPerfReg: Invalid phyId +2870,IIIii,[ phyrf_debug_cmd.c : 299 ] RegDumpId %u :: NFCAL_RUNTIME_PER_CHAIN :: phyId %u :: Chain %u :: %d dBr :: %d dBm +2869,,[ phyrf_debug_cmd.c : 632 ] DumpPerfReg: PHY HANDLE Invalid +2868,,[ phyrf_debug_cmd.c : 638 ] DumpPerfReg: PHY HANDLE not initialized +2867,III,[ phyrf_debug_cmd.c : 309 ] RegDumpId %u :: XTAL CAPIN=%u CAPOUT=%u + +2866,IIi,[ phyrf_debug_cmd.c : 313 ] BdfDump :: XTAL CAPIN=%u CAPOUT=%u PPM=%d + +2865,IIi,[ phyrf_debug_cmd.c : 316 ] BdfDump :: XTAL CAPIN=%u CAPOUT=%u PPM=-%d + +2864,II,[ phyrf_debug_cmd.c : 338 ] RegDumpId %u :: TPC_DUMP MASK %u +2863,iii,[ phyrf_debug_cmd.c : 361 ] RxGainCalResult phyId:%d channel_idx:%d, channel_freq:%d +2862,iiiii,[ phyrf_debug_cmd.c : 367 ] RxGainCalResult phyId:%d channel_idx:%d, chain_idx:%d, DBr_value:%d, DBm_value:%d +2861,IIIii,[ phyrf_debug_cmd.c : 270 ] RegDumpId %u :: NFCAL_BDF_PER_CHAIN :: phyId %u :: Chain %u :: %d dBr :: %d dBm +2860,iI,[ phyrf_debug_cmd.c : 385 ] FTM_DEBUG: g_ftm_ctxt[%d] addr = %p +2859,iIIII,[ phyrf_debug_cmd.c : 396 ] FTM_DEBUG: g_ftm_ctxt[%d]: pdev = %p, vdev = %p, peer = %p, ftm_mode = 0x%x +2858,iIIII,[ phyrf_debug_cmd.c : 398 ] FTM_DEBUG: g_ftm_ctxt[%d]: send_mgmt = 0x%x, send_data = 0x%x, encap_cfg = %p, ctrl = %p +2857,,[ phyrf_debug_cmd.c : 402 ] FTM_DEBUG: encap_cfg pointer is NULL in g_ftm_ctxt !! +2856,iiiI,[ phyrf_debug_cmd.c : 410 ] FTM_DEBUG: g_ftm_ctxt[%d].encap_cfg: pkt_len = %d, pkt_type = %d, vdev = %p +2855,iIIIIII,[ phyrf_debug_cmd.c : 417 ] FTM_DEBUG: g_ftm_ctxt[%d].encap_cfg->sa_addr = 0x%02x:%02x:%02x:%02x:%02x:%02x +2854,iIIIIII,[ phyrf_debug_cmd.c : 425 ] FTM_DEBUG: g_ftm_ctxt[%d].encap_cfg->da_addr = 0x%02x:%02x:%02x:%02x:%02x:%02x +2853,iIIIIII,[ phyrf_debug_cmd.c : 433 ] FTM_DEBUG: g_ftm_ctxt[%d].encap_cfg->bss_addr = 0x%02x:%02x:%02x:%02x:%02x:%02x +2852,,[ phyrf_debug_cmd.c : 438 ] FTM_DEBUG: ctrl pointer is NULL in g_ftm_ctxt !! +2851,iii,[ phyrf_debug_cmd.c : 445 ] FTM_DEBUG: g_ftm_ctxt[%d].ctrl: num_pkts_to_send = %d, is_aggr_ok = %d +2850,I,[ phyrf_debug_cmd.c : 292 ] RegDumpId %u :: NFCAL_RUNTIME_PER_CHAIN :: Exceptions :: Value = 1 : Chain Unsupported, Value = 0 : NFCAL Convergence Failed +2849,iii,[ phyrf_debug_cmd.c : 452 ] FTM_DEBUG: g_dbg_overwrite_ppdu_dur_us = %d, g_dbg_gi_override = %d, g_dbg_he_ltf_override = %d +2848,iiii,[ phyrf_debug_cmd.c : 483 ] CALDB_DEBUG: calDBEnableSetting=%d, CalTimeOutSetting = %d, PersistentEnable = %d, masterCalDbExist()=%d +2847,Ii,[ phyrf_debug_cmd.c : 484 ] CALDB_DEBUG: CALDB_ADDRE= %x dB size = %d +2846,,[ phyrf_debug_cmd.c : 485 ] CALDB_DEBUG: Version info and CALDB Synopsis follows: +2845,,[ phyrf_debug_cmd.c : 519 ] REGEN_CALDB: Re-generating cold boot calibration over debug - Command - wait for 60seconds ... + +2844,iIIi,[ phyrf_debug_cmd.c : 1237 ] ADDRVAL: indx = %d addr = 0x%X val = 0x%X en=%d +2843,iIIi,[ phyrf_debug_cmd.c : 1247 ] ADDRVAL: indx = %d addr = 0x%X val = 0x%X en=%d +2842,iIIi,[ phyrf_debug_cmd.c : 1253 ] ADDRVAL: indx = %d addr = 0x%X val = 0x%X en=%d +2841,,[ phyrf_debug_cmd.c : 3772 ] PAPRD: Command arguments Invalid +2840,i,[ phyrf_debug_cmd.c : 3777 ] PAPRD: Invalid PHY ID = %d + +2839,ii,[ phyrf_debug_cmd.c : 3781 ] PAPRD: PHYID = %d ,Event Val = %d + +2838,,[ phyrf_debug_cmd.c : 2634 ] phyrf_debug_MMHostCmdSetCalMask Invalid Command +2837,Ii,[ phyrf_debug_cmd.c : 2641 ] phyrf_debug_MMHostCmdSetCalMask: Invalid PHY ID = %u, phyrf_init_GetNumPhys()=%d +2836,i,[ phyrf_debug_cmd.c : 2649 ] phyrf_debug_MMHostCmdSetCalMask: Invalid pHandle for phyId=%d +2835,I,[ phyrf_debug_cmd.c : 2656 ] Set g_halphy_debug_cal_mask =0x%x + +2834,,[ phyrf_debug_cmd.c : 2514 ] SetCcaThreshold: Invalid test arguments +2833,,[ phyrf_debug_cmd.c : 2520 ] SetCcaThreshold: Invalid phyId +2832,I,[ phyrf_debug_cmd.c : 2175 ] Set g_halphy_debug_mask =0x%x + +2831,I,[ phyrf_debug_cmd.c : 2181 ] Set phyDebugMask =0x%x + +2830,,[ phyrf_debug_cmd.c : 1978 ] PAPRD: Invalid test arguments +2829,i,[ phyrf_debug_cmd.c : 1986 ] PAPRD: Invalid PHY ID = %d + +2828,ii,[ phyrf_debug_cmd.c : 1990 ] PAPRD: PHYID = %d ,Event = %d + +2827,i,[ phyrf_debug_cmd.c : 2097 ] Setting PBS Mode to %d + +2826,,[ phyrf_debug_cmd.c : 2895 ] FUSE BOARD ID VALUE TO OTP : wifitool : Invalid test arguments +2825,,[ phyrf_debug_cmd.c : 2901 ] FUSE BOARD ID VALUE TO OTP : wifitool :Completed +2824,,[ phyrf_debug_cmd.c : 2599 ] phyrf_debug_MMHostCmdSetTpcFlag: Invalid test arguments +2823,Ii,[ phyrf_debug_cmd.c : 2605 ] phyrf_debug_MMHostCmdSetTpcFlag: Invalid phyId %u, phyrf_init_GetNumPhys()=%d +2822,i,[ phyrf_debug_cmd.c : 2616 ] phyrf_debug_MMHostCmdSetTpcFlag: Invalid pHandle for phyId=%d +2821,,[ phyrf_debug_cmd.c : 2315 ] SPECTRAL_ENABLE: Invalid test arguments +2820,,[ phyrf_debug_cmd.c : 2321 ] SPECTRAL_ENABLE: Invalid phyId +2819,,[ phyrf_debug_cmd.c : 2327 ] SPECTRAL_ENABLE: Invalid scanMode +2818,i,[ phyrf_debug_cmd.c : 2974 ] phyrf_debug_MMHostCmdTPCDebug g_clpc_corr_thr %d +2817,ii,[ phyrf_debug_cmd.c : 2990 ] phyrf_debug_MMHostCmdTPCDebug pdadc_read %d meas_pwr %d +2816,ii,[ phyrf_debug_cmd.c : 2995 ] phyrf_debug_MMHostCmdTPCDebug PLUT[%d] = %d +2815,,[ phyrf_debug_cmd.c : 3003 ] phyrf_debug_MMHostCmdTPCDebug Invalid commands +2814,i,[ phyrf_debug_cmd.c : 1085 ] THERMAL: Invalid PHY ID = %d +2813,ii,[ phyrf_debug_cmd.c : 1092 ] g_ThermalEnable[%d]=%d +2812,,[ phyrf_debug_cmd.c : 2552 ] TpcPowerOverride: Invalid test arguments +2811,,[ phyrf_debug_cmd.c : 2558 ] TpcPowerOverride: Invalid phy ID +2810,,[ phyrf_debug_cmd.c : 2576 ] TpcPowerOverride: Invalid test arguments +2809,ii,[ phyrf_debug_cmd.c : 2584 ] TpcPowerOverride: chain %d: power: %d +2808,i,[ phyrf_debug_cmd.c : 1066 ] XTAL: Invalid PHY ID = %d +2807,ii,[ phyrf_debug_cmd.c : 1071 ] g_XtalCalPPM[%d]=%d +2806,i,[ phyrf_debug_cmd.c : 3415 ] WIFITOOL ISSUED TO ENABLE/DISABLE PER-PACKET CHAINMASK SUPPORT = %d + +2805,i,[ phyrf_debug_cmd.c : 3419 ] ENABLE/DISABLE PER-PACKET CHAINMASK SUPPORT: INVALID INPUT %d + +3076,i,[ dfs_fcc_bin5.c : 110 ] DFS_DUMPS Rejecting pulses as they are not chirp %d + +3109,,[ phyrf_dfs.c : 683 ] Invalid Channel Number +3108,i,[ phyrf_dfs.c : 716 ] Invalid frequency : %d +3107,I,[ phyrf_dfs.c : 766 ] %s: DFS ic is Invalid +3106,II,[ phyrf_dfs.c : 773 ] %s: allocation of dfs_ic->ic_curchan failed %zu +3105,iiiii,[ phyrf_dfs.c : 793 ] ADFS_DUMPS : req_chan=%d, ic_ieee_chan=%d, center_freq1=%d, center_freq2=%d, chan_wodth=%d + +3104,I,[ phyrf_dfs.c : 809 ] %s: ADFS- CHANNEL CONFIGURED +3103,iii,[ phyrf_dfs.c : 411 ] DFS_DUMPS regdomain %d phyId=%d g_DfsConfiguration=%d + +3102,,[ phyrf_dfs.c : 237 ] DFS_DUMPS set 0x8000 + +3101,,[ phyrf_dfs.c : 260 ] DFS_DUMP set g_dfs_test_mode + +3100,,[ phyrf_dfs.c : 265 ] DFS_DUMP clear g_dfs_test_mode + +3099,,[ phyrf_dfs.c : 270 ] DFS_DUMP Send Radar summary pulse to host + +3098,,[ phyrf_dfs.c : 274 ] DFS_DUMP stop Sending Radar summary pulse to host + +3097,,[ phyrf_dfs.c : 279 ] DFS_DUMPS Print all the pulse information + +3096,,[ phyrf_dfs.c : 284 ] DFS_DUMPS Stop printing pulse information + +3095,i,[ phyrf_dfs.c : 289 ] DFS_DUMPS RAW_FFT Data Dump set to %d + +3094,iiiiiiiii,[ phyrf_dfs.c : 250 ] DFS_DUMPS timestamp=%d diff_ts=%d pulse_rssi=%d pulse_duration=%d is_chirp=%d sidx=%d detector_id=%d + false_radar=%d radar_check=%d +3093,,[ phyrf_dfs.c : 255 ] DFS_DUMPS set 0x8001 + +3092,II,[ phyrf_dfs.c : 982 ] %s:Allocation of g_dfs_ic[dfs_detector_id] failed %zu +3091,I,[ phyrf_dfs.c : 529 ] %s: DFS ic is Invalid +3090,I,[ phyrf_dfs.c : 546 ] %s: DFS-FCC domain +3089,I,[ phyrf_dfs.c : 554 ] %s: DFS-ETSI domain +3088,I,[ phyrf_dfs.c : 569 ] %s:DFS-MKKN domain +3087,I,[ phyrf_dfs.c : 587 ] %s: DFS-MKK domain +3086,I,[ phyrf_dfs.c : 603 ] %s: DFS_CN_DOMAIN +3085,I,[ phyrf_dfs.c : 617 ] %s: DFS_KR_DOMAIN +3084,I,[ phyrf_dfs.c : 635 ] %s: DFS-UNINT domain +3083,,[ phyrf_dfs.c : 658 ] PRDD_Test_Radar_Enable +3082,Ii,[ phyrf_dfs.c : 661 ] %s[%d]: DFS- Radar Detection Enabling Failed +3081,I,[ phyrf_dfs.c : 858 ] %s: DFS ic is Invalid +3080,I,[ phyrf_dfs.c : 963 ] %s: DFS- CHANNEL CONFIGURED +3079,II,[ phyrf_dfs.c : 869 ] %s: allocation of dfs_ic->ic_curchan failed %zu +3078,iiiii,[ phyrf_dfs.c : 891 ] DFS_DUMPS : req_chan=%d, ic_ieee_chan=%d, center_freq1=%d, center_freq2=%d, chan_wodth=%d + +3077,Ii,[ phyrf_dfs.c : 941 ] %s: Recieved a wrong channel width %d +3110,III,[ wma_dfs_interface.c : 63 ] %s: called; ptr=%p, radar_info=%p + +3112,,[ hca_rf_ftmIf_api.cpp : 140 ] ftmIf_SetRxDeaf +3111,,[ hca_rf_ftmIf_api.cpp : 154 ] ftmIf_SetRxListen +3113,i,[ hca_HwComponentTrx.cpp : 78 ] Error: processCmd ID of %d, unknown state. +3114,i,[ hca_config.cpp : 85 ] Invalid HW component type %d + +3190,i,[ phyrf_mc_paprd.c : 2303 ] PAPRD:Tx stats : hw_queued %d +3189,i,[ phyrf_mc_paprd.c : 2304 ] PAPRD:Tx stats : hw_reaped %d +3188,i,[ phyrf_mc_paprd.c : 2305 ] PAPRD:Tx stats : tx_done %d +3187,i,[ phyrf_mc_paprd.c : 2306 ] PAPRD:Tx stats : tx_abort %d +3186,i,[ phyrf_mc_paprd.c : 2307 ] PAPRD:Tx stats : tx_abort_compl_err_status %d +3185,i,[ phyrf_mc_paprd.c : 2308 ] PAPRD:Tx stats : tx_abort_pdev_suspend %d +3184,i,[ phyrf_mc_paprd.c : 2309 ] PAPRD:Tx stats : tx_async_enqueue %d +3183,i,[ phyrf_mc_paprd.c : 2310 ] PAPRD:Tx stats : tx_async_dequeue %d +3182,i,[ phyrf_mc_paprd.c : 2311 ] PAPRD:Tx stats : tx_fail %d +3181,i,[ phyrf_mc_paprd.c : 879 ] PAPRD: Start Calibration : %d ms Timer expired +3180,,[ phyrf_mc_paprd.c : 2842 ] PAPRD: dpd_cal_sync_handler_0 pHandle NULL +3179,i,[ phyrf_mc_paprd.c : 2850 ] PAPRD: PhyId %d dpd_cal_sync_timer_handler_0, releasing the wal_lock +3178,i,[ phyrf_mc_paprd.c : 2063 ] Calibration is in progress on other phy, cur phyId %d +3177,iiiiii,[ phyrf_mc_paprd.c : 2115 ] PAPRD: Abort TempRecal phy %d, curr time %d, currTemp %d, last calTemp %d curr Channel %d thermal channel %d +3176,iiii,[ phyrf_mc_paprd.c : 2144 ] PAPRD : FTM PHY id %d currTemp %d cal temp %d tempDiff_scale %d +3175,iiiiii,[ phyrf_mc_paprd.c : 2155 ] PAPRD : TempRecal triggered phy %d, curr time %d, currTemp %d, last calTemp %d channel %d tempDiff %d +3174,iiii,[ phyrf_mc_paprd.c : 2176 ] PAPRD : PHY id %d currTemp %d cal temp %d tempDiff_scale %d +3173,iiiiii,[ phyrf_mc_paprd.c : 2673 ] (chan %d ,cm %d halphyMemDPDValidateCalDB , result [%d %d], cal_attempts[%d %d] +3172,iiiii,[ phyrf_mc_paprd.c : 2677 ] (chan %d ,cm %d halphyMemDPDValidateCalDB , max attemps %d temp [%d %d] +3171,iiii,[ phyrf_mc_paprd.c : 2643 ] halphyPaprdValidateMemCalibration calattempts %d %d, validBits %d %d +3170,,[ phyrf_mc_paprd.c : 2648 ] CALIBRATION COMPLETE chain 0, result 1 +3169,,[ phyrf_mc_paprd.c : 2652 ] CALIBRATION COMPLETE chain 1, result 1 +3168,,[ phyrf_mc_paprd.c : 2750 ] Do not have access to masterCalDb or localCalDb, failed to restore DPD +3167,ii,[ phyrf_mc_paprd.c : 2754 ] DPD Memory : paprd_restore : finalCase %d channel %d +3166,iii,[ phyrf_mc_paprd.c : 838 ] phyrf_mc_CancelPaprdTimer bHomeChan %d timerActive %d, channel %d +3165,iii,[ phyrf_mc_paprd.c : 846 ] PAPRD: Cancel Timer : %d ms Timer on curChan %d home %d +3164,iiii,[ phyrf_mc_paprd.c : 1700 ] PAPRD: cur_channel %d, wal_channel %d, scan_channel %d, phyReset %d +3163,iiiii,[ phyrf_mc_paprd.c : 1266 ] PAPRD: DPD calibration aborted on chain %d, tableIdx %d, channel %d, state %d, new_channel_change_request %d +3162,i,[ phyrf_mc_paprd.c : 1284 ] PAPRD: DPD calibration aborted on channel %d +3161,i,[ phyrf_mc_paprd.c : 282 ] PAPRD:SM state %d +3160,,[ phyrf_mc_paprd.c : 365 ] PAPRD: Enabling DPD because eDPD failed +3159,ii,[ phyrf_mc_paprd.c : 368 ] PAPRD: Aborting Excess Retries. retry_dpd %d, Tx_Err %d +3158,ii,[ phyrf_mc_paprd.c : 489 ] PAPRD: incrementing retry_dpd %d, Tx_Err %d +3157,ii,[ phyrf_mc_paprd.c : 497 ] 2: PAPRD: incrementing retry_dpd %d, Tx_Err %d +3156,i,[ phyrf_mc_paprd.c : 501 ] PAPRD: PAPRD_CAL_SM_DPD_TRAINING_PROCESS_DATA hwPaPrdStatus(fail) retry_dpd %d +3155,iii,[ phyrf_mc_paprd.c : 565 ] PAPRD: TRAINING_PROCESS_DATA chain %d tableIdx %d processing_time %d +3154,i,[ phyrf_mc_paprd.c : 598 ] DPD Aborted due to BG thread activated in FTM mode : smState %d +3153,iiii,[ phyrf_mc_paprd.c : 325 ] PAPRD: State m/c : channel %d, txchain %d, table %d, state %d +3152,,[ phyrf_mc_paprd.c : 636 ] PAPRD: PAPRD_CAL_SM_TEARDOWN_TRAINING : DPD ABORT +3151,,[ phyrf_mc_paprd.c : 670 ] PAPRD: PAPRD_CAL_SM_TEARDOWN_TRAINING : DPD ABORT +3150,iii,[ phyrf_mc_paprd.c : 693 ] PAPRD: is160mode %d secondary %d primary_done %d +3149,iii,[ phyrf_mc_paprd.c : 711 ] PAPRD: phy_a0_done %d phy_a1_done %d phy_a1_secondary_done %d +3148,ii,[ phyrf_mc_paprd.c : 723 ] PAPRD: PAPRDTUNING DONE. total_caltime %d, phyOff_cnt %d +3147,,[ phyrf_mc_paprd.c : 733 ] ----- PAPRDTUNING SECONDARY started----- +3146,ii,[ phyrf_mc_paprd.c : 743 ] PAPRD: PAPRDTUNING DONE. total_caltime %d, phyOff_cnt %d +3145,iii,[ phyrf_mc_paprd.c : 748 ] PAPRD: is160mode %d, secondary %d, isExtn %d +3144,ii,[ phyrf_mc_paprd.c : 749 ] PAPRD: lastcalTime %d, current_time %d +3143,ii,[ phyrf_mc_paprd.c : 364 ] PAPRD: MEM DPD Aborting Excess Retries. retry_dpd %d, Tx_Err %d +3142,ii,[ phyrf_mc_paprd.c : 1213 ] PAPRD: Channel = %d, dpd_enable = %d +3141,iii,[ phyrf_mc_paprd.c : 1232 ] PAPRD: Chain = %d, txgainIdx = %d, dacgain = %d +3140,i,[ phyrf_mc_paprd.c : 1008 ] PAPRD : phyrf_mc_PaprdStartTimer: %d ms +3139,iiiiiii,[ phyrf_mc_paprd.c : 1825 ] PAPRD: phyrf_mc_SendTxCompletion : channel %d, txchain %d, table %d, new_channel_change_request %d, cal abort_ppdu %d, status %d, retry_cnt %d +3138,iiiiiii,[ phyrf_mc_paprd.c : 1854 ] PAPRD: new_channel_change_request : channel %d, txchain %d, table %d, new_channel_change_request %d, cal abort_ppdu %d, status %d, retry_cnt %d +3137,iiiii,[ phyrf_mc_paprd.c : 1878 ] PAPRD: Status %d, whal_tx_err_status_t %d, Flush_req_reason %d, tx_ctxt_flags %d, pdev_paused %d +3136,i,[ phyrf_mc_paprd.c : 1892 ] PAPRD: HALPHY_TX_TBTT_FLUSH : condition hit , flush_req_reason = %d +3135,iiii,[ phyrf_mc_paprd.c : 1910 ] PAPRD: Tx Completion Status(HALPHY_TX_ERROR) %d, whal_tx_err_status_t = %d , retrying (chain %d table %d) +3134,iiiiii,[ phyrf_mc_paprd.c : 1748 ] PAPRD: TxChain %d, tableIdx %d, channel %d, state %d, new_channel_change_request %d, startEvtLatency %d +3133,,[ phyrf_mc_paprd.c : 1757 ] PAPRD: PPDU Start Event Delayed - skip further processing and retry DPD +3132,iii,[ phyrf_mc_paprd.c : 1769 ] PAPRD: Aborted. Status %d abort_ppdu %d cur_tbl_idx %d +3131,,[ phyrf_mc_paprd.c : 1776 ] PAPRD: phyrf_paprd_TrainingStatus success +3130,,[ phyrf_mc_paprd.c : 1780 ] PAPRD: phyrf_paprd_TrainingStatus fail +3129,i,[ phyrf_mc_paprd.c : 176 ] PAPRD: Paprd Done status is %d +3128,iiii,[ phyrf_mc_paprd.c : 1968 ] PAPRD: phyId %d, txchainmask %d chain %d, degC %d +3127,iiii,[ phyrf_mc_paprd.c : 1973 ] PAPRD: phyId %d, txchainmask %d currtime %d, degC %d +3126,iiii,[ phyrf_mc_paprd.c : 2334 ] PAPRD ApplyTempScaling: PhyId %d slope %d temp delta %d scaling %d +3125,,[ phyrf_mc_paprd.c : 2918 ] PAPRD: UCODE VREG WAR enabled +3124,iiii,[ phyrf_mc_paprd.c : 2956 ] PAPRD: last_valid_chain_idx %d last_valid_table_index %d pPaprdStruct->txChain %d pPaprdStruct->tableIndex %d + +3123,ii,[ phyrf_mc_paprd.c : 2966 ] PAPRD: phyrf_paprd_HandleMaxRetry pPaprdStruct->training_fail_table %d and calAttempts %d + +3122,i,[ phyrf_mc_paprd.c : 2035 ] Calibration is in progress on phyId %d +3121,iiiiiii,[ phyrf_mc_paprd.c : 2593 ] phyId %d thread context : workingChannel %d txChainMask %d bHomeChan %d phyrfMode %d WoW Mode %d curr Channel %d +3120,ii,[ phyrf_mc_paprd.c : 2611 ] MEM_DPD THREAD (START the new table) : UPDATING CALDB POST PROCESSING DATA : %d %d +3119,iiii,[ phyrf_mc_paprd.c : 2624 ] BG THREAD CONTEXT is DIFFERENT : %d %d, curr channel %d bChannelContext %d +3118,ii,[ phyrf_mc_paprd.c : 2273 ] thermal scaling value is %d and thermal slope is %d +3117,iiiii,[ phyrf_mc_paprd.c : 2290 ] PAPRD: temp_recal_timer started. tempRecalcount %d, phyId %d, calTemp %d, calDb temp chain0 %d, calDb temp chain1 %d +3116,iii,[ phyrf_mc_paprd.c : 2996 ] PAPRD: Calibration triggered for a pending request on PhyId %d Channel %d , home %d +3115,iiiiii,[ phyrf_mc_paprd.c : 2807 ] phyId %d thread context : workingChannel %d txChainMask %d bHomeChan %d phyrfMode %d WoW Mode %d +3191,I,[ phyrf_phy.c : 79 ] MAC FW Vreg update RU26 Tx disable = %x +3249,iii,[ phyrf_regulatory.c : 271 ] RegDB-6G MaxBW AP SP - %d, LPI - %d, VLP - %d + +3248,iii,[ phyrf_regulatory.c : 277 ] RegDB-6G MaxBW CLIENT SP - %d, LPI - %d, VLP - %d + +3247,,[ phyrf_regulatory.c : 284 ] RegDB - phyrf_regulatory_FillMinBW_6g + +3246,iii,[ phyrf_regulatory.c : 288 ] RegDB-6G MinBW AP SP - %d, LPI - %d, VLP - %d + +3245,iii,[ phyrf_regulatory.c : 294 ] RegDB-6G MinBW CLIENT SP - %d, LPI - %d, VLP - %d + +3244,iii,[ phyrf_regulatory.c : 304 ] RegDB-6G NumRules AP SP - %d, LPI - %d, VLP - %d + +3243,iii,[ phyrf_regulatory.c : 310 ] RegDB-6G NumRules CLIENT SP - %d, LPI - %d, VLP - %d + +3242,i,[ phyrf_regulatory.c : 2131 ] AFC RegDB- num sp reg rules: %d + +3241,Ii,[ phyrf_regulatory.c : 2165 ] RegDB-Test_Super Domain 6G %x %d + +3240,i,[ phyrf_regulatory.c : 949 ] RegDB-Version %d + +3239,i,[ phyrf_regulatory.c : 1001 ] get valid country_code/domain_code from OTP %d. +3238,,[ phyrf_regulatory.c : 1073 ] RegDB-Has a 6G domain ID + +3237,,[ phyrf_regulatory.c : 1078 ] RegDB-Valid 6G super dmn and 5G2G reg pair Combo + +3236,,[ phyrf_regulatory.c : 1091 ] RegDB-Invlid Combo + +3235,ii,[ phyrf_regulatory.c : 1096 ] Valid superdomain but not mapped to any country RegDB-Super Dmn Id %d Idx %d + +3234,ii,[ phyrf_regulatory.c : 1132 ] RegDB-6G Super Dmn %d Max BW %d + +3233,ii,[ phyrf_regulatory.c : 1214 ] RegDB-6G Super Dmn %d Max BW %d + +3232,ii,[ phyrf_regulatory.c : 1219 ] RegDB-Valid country ID %d Correspondig RegDmn %d + +3231,ii,[ phyrf_regulatory.c : 1255 ] RegDB-6G Super Dmn %d Max BW %d + +3230,ii,[ phyrf_regulatory.c : 1285 ] RegDB-6G Super Dmn %d Max BW %d + +3229,ii,[ phyrf_regulatory.c : 1290 ] RegDB-Valid country ID %d Correspondig RegDmn %d + +3228,i,[ phyrf_regulatory.c : 1301 ] RegDB-Status %d + +3227,iiiiiiii,[ phyrf_regulatory.c : 1302 ] RegDB-Final Result alpha0 %d alpha1 %d alpha_size %d max_rules %d get_type %d cc_type %d ctryID %d dmnCode %d + +3226,iiiiiiii,[ phyrf_regulatory.c : 1303 ] RegDB-Final Result num_2g_rules %d num_5g_rules %d phybitmap %d dfsregion %d min_bw_2g %d min_bw_5g %d max_bw_2g %d max_bw_5g %d + +3225,i,[ phyrf_regulatory.c : 1011 ] get valid country_code/domain_code from BDF %d. +3224,,[ phyrf_regulatory.c : 1014 ] neither OTP nor BDF valid value for country_code/domain_code. +3223,iii,[ phyrf_regulatory.c : 1033 ] RegDB-BDF CC %d OTP RD %d CC Type %d + +3222,iii,[ phyrf_regulatory.c : 1035 ] RegDB-BDF CC %d BDF RD %d CC Type %d + +3221,i,[ phyrf_regulatory.c : 1067 ] RegDB-No Reg_Dmn diff with BDF %d + +3220,i,[ phyrf_regulatory.c : 676 ] RegDB-Version %d + +3219,,[ phyrf_regulatory.c : 677 ] RegDB-New Extended Event Invoked + +3218,iii,[ phyrf_regulatory.c : 723 ] RegDB-Super Dmn Id %d validity %d Idx %d + +3217,iii,[ phyrf_regulatory.c : 771 ] RegDB-Super Dmn Id %d validity %d Idx %d + +3216,iii,[ phyrf_regulatory.c : 830 ] RegDB - Ext Event Status - 2G5G %d 6G %d Overall %d + +3215,iiiiiiii,[ phyrf_regulatory.c : 831 ] RegDB-Final Result_Ext alpha0 %d alpha1 %d alpha_size %d max_rules %d get_type %d cc_type %d ctryID %d dmnCode %d + +3214,iiiiiiii,[ phyrf_regulatory.c : 832 ] RegDB-Final Result_Ext num_2g_rules %d num_5g_rules %d phybitmap %d dfsregion %d min_bw_2g %d min_bw_5g %d max_bw_2g %d max_bw_5g %d + +3213,Ii,[ phyrf_regulatory.c : 2011 ] RegDB-Test_Super Domain 6G %x %d + +3212,i,[ phyrf_regulatory.c : 1397 ] get valid country_code/domain_code from OTP %d. +3211,i,[ phyrf_regulatory.c : 1409 ] get valid country_code/domain_code from BDF %d. +3210,,[ phyrf_regulatory.c : 1412 ] neither OTP nor BDF valid value for country_code/domain_code. +3209,i,[ phyrf_regulatory.c : 587 ] get valid country_code/domain_code from OTP %d. +3208,i,[ phyrf_regulatory.c : 599 ] get valid country_code/domain_code from BDF %d. +3207,,[ phyrf_regulatory.c : 602 ] neither OTP nor BDF valid value for country_code/domain_code. +3206,ii,[ phyrf_regulatory.c : 487 ] RegDB-Getting 6G_AP_LPI Rules dmn_id %d num_rules %d + +3205,ii,[ phyrf_regulatory.c : 490 ] RegDB-Getting 6G_AP_SP Rules dmn_id %d num_rules %d + +3204,ii,[ phyrf_regulatory.c : 493 ] RegDB-Getting 6G_AP_VLP Rules dmn_id %d num_rules %d + +3203,ii,[ phyrf_regulatory.c : 504 ] RegDB-Getting 6G_CLIENT_LPI Rules dmn_id %d num_rules %d + +3202,ii,[ phyrf_regulatory.c : 511 ] RegDB-Getting 6G_CLIENT_SP Rules dmn_id %d num_rules %d + +3201,ii,[ phyrf_regulatory.c : 518 ] RegDB-Getting 6G_CLIENT_VLP Rules dmn_id %d num_rules %d + +3200,i,[ phyrf_regulatory.c : 1327 ] RegDB-Valid reg dmn pair id %d + +3199,ii,[ phyrf_regulatory.c : 1341 ] RegDB-Valid domain 2g rules %d 5g rules %d + +3198,,[ phyrf_regulatory.c : 1466 ] Invalid country code. Setting to "US". +3197,,[ phyrf_regulatory.c : 1551 ] Invalid country_code/domain_code. No currentRD or ctl value change. +3196,,[ phyrf_regulatory.c : 1574 ] neither OTP nor BDF valid value for country_code/domain_code. +3195,iiiiii,[ phyrf_regulatory.c : 216 ] RegDB 2G-Rule%d start %d end %d max_bw %d reg_power %d flags %d + +3194,iiiiii,[ phyrf_regulatory.c : 244 ] RegDB 5G-Rule%d start %d end %d max_bw %d reg_power %d flags %d + +3193,ii,[ phyrf_regulatory.c : 317 ] RegDB 6G Getting Rules dmn_id %d num_rules %d + +3192,iiiiiii,[ phyrf_regulatory.c : 328 ] RegDB 6G-Rule%d start %d end %d max_bw %d tx_power_eirp %d max_psd_eirp %d flags %d + +3281,i,[ phyrf_afc.c : 245 ] AFC: read_status:%d +3280,i,[ phyrf_afc.c : 269 ] AFC: max_eirp_pwr: %d +3279,i,[ phyrf_afc.c : 277 ] AFC: num_eirp: %d +3278,ii,[ phyrf_afc.c : 293 ] AFC - Bin parse, ini timer disabled: %d, ini reqId check disabled: %d +3277,i,[ phyrf_afc.c : 308 ] AFC Request Id mismatch: fw_status_code %d +3276,i,[ phyrf_afc.c : 246 ] AFC: time_to_live Info:%d +3275,i,[ phyrf_afc.c : 247 ] AFC: payload_length Info:%d +3274,i,[ phyrf_afc.c : 248 ] AFC: payload_format Info:%d +3273,i,[ phyrf_afc.c : 249 ] AFC: local_error_code Info:%d +3272,i,[ phyrf_afc.c : 250 ] AFC: version Info:%d +3271,i,[ phyrf_afc.c : 251 ] AFC: afc_wfa_version Info:%d +3270,ii,[ phyrf_afc.c : 252 ] AFC: response_id Info:%d, Request Id: %d: +3269,i,[ phyrf_afc.c : 253 ] AFC: avail_exp_time_d Info:%d +3268,i,[ phyrf_afc.c : 254 ] AFC: avail_exp_time_t Info:%d +3267,i,[ phyrf_afc.c : 255 ] AFC: afc_serv_resp_code Info:%d +3266,i,[ phyrf_afc.c : 256 ] AFC: num_frequency Info:%d +3265,i,[ phyrf_afc.c : 257 ] AFC: num_channel Info:%d +3264,I,[ phyrf_afc.c : 260 ] AFC: Freq Info: 0x%x +3263,I,[ phyrf_afc.c : 261 ] AFC: Max PSD: %u +3262,i,[ phyrf_afc.c : 262 ] AFC: global_operating_class: %d +3261,i,[ phyrf_afc.c : 263 ] AFC: num_channels: %d +3260,i,[ phyrf_afc.c : 268 ] AFC: channel_cfi: %d +3259,I,[ phyrf_afc.c : 58 ] AFC: request_id: %u +3258,i,[ phyrf_afc.c : 176 ] AFC, disable query: count:%d +3257,i,[ phyrf_afc.c : 118 ] AFC ini timer disabled - AFC Start: %d, +3256,i,[ phyrf_afc.c : 138 ] AFC: count:%d +3255,i,[ phyrf_afc.c : 144 ] AFC: count:%d +3254,,[ phyrf_afc.c : 147 ] AFC: grace period has ended. Switching power mode to LPI +3253,,[ phyrf_afc.c : 152 ] AFC: grace period has ended. Since power mode was already LPI, not updating +3252,i,[ phyrf_afc.c : 160 ] AFC: count:%d +3251,i,[ phyrf_afc.c : 127 ] AFC: Grace count is:%d +3250,i,[ phyrf_afc.c : 132 ] AFC: count:%d +3310,iii,[ phyrf_reset.c : 654 ] DumpTpc-3: set trasmit chan power: %d, forced: %d, max tx: %d +3309,i,[ phyrf_reset.c : 655 ] phyrf_reset_ForceTxPower: homeChanFlag: %d +3308,i,[ phyrf_reset.c : 3419 ] Invalid number of chains %d. Resetting PPET to all 0s +3307,iI,[ phyrf_reset.c : 3462 ] ppet16_8ru0_3[%d] = 0x%x +3306,iI,[ phyrf_reset.c : 3464 ] update_ppet->numNss_m1 %d, update_ppet->ruMask 0x%x +3305,i,[ phyrf_reset.c : 3386 ] Invalid ChainIndex %d. Returning the input chainIndex without translating +3304,i,[ phyrf_reset.c : 3393 ] Invalid ChainIndex %d. Returning the input chainIndex without translating +3303,i,[ phyrf_reset.c : 3398 ] Translated ChainIndex %d +3302,I,[ phyrf_reset.c : 3343 ] Translated chainmask 0x%x +3301,iIii,[ phyrf_reset.c : 1204 ] [phyId=%d]HALPHY_RESET_SETUP: Reset cause is 0x%x, bHomeChan=%d, ScanTPC channel=%d +3300,I,[ phyrf_reset.c : 1221 ] HALPHY_RESET_SETUP: SCAN-HOME: Scan to home channel change & reset cause is %lu + +3299,I,[ phyrf_reset.c : 1226 ] HALPHY_RESET_SETUP: SCAN-HOME: New Home Chan or New Scan Chan or Reset and resetCause is %lu + +3298,,[ phyrf_reset.c : 1230 ] HALPHY_RESET_SETUP: SCAN-HOME: Home to scan channel change! + +3297,,[ phyrf_reset.c : 1234 ] HALPHY_RESET_SETUP: SCAN-HOME: Home channel change! + +3296,iiiii,[ phyrf_reset.c : 1270 ] DumpTpc-5: set trasmit chan power: %d, reset struct power: %d, 2g limit: %d, 5g limit: %d, max tx: %d +3295,II,[ phyrf_reset.c : 3243 ] PowerMode setting for phyId : 0x%x, value : 0x%x +3294,ii,[ phyrf_reset.c : 1685 ] SetChainMasks: tx:%d rx:%d +3293,ii,[ phyrf_reset.c : 727 ] Not a 160 channel chan->band_center_freq1 %d, chan->band_center_freq2 %d +3292,iiiii,[ phyrf_reset.c : 492 ] DumpTpc-1: set trasmit chan power: %d, 2g limit: %d, 5g limit: %d, max tx: %d limit %d +3291,i,[ phyrf_reset.c : 511 ] halphySetTxChannelPowerLimit homeChanFlag: %d +3290,iiii,[ phyrf_reset.c : 510 ] halphySetTxChannelPowerLimit phyId %d limit %d maxTxPower %d curChan->mhz %d +3289,iiii,[ phyrf_reset.c : 448 ] DumpTpc-4: set trasmit chan power: %d, 2g limit: %d, 5g limit: %d, max tx: %d +3288,i,[ phyrf_reset.c : 449 ] phyrf_reset_SetTxPowerLimit: homeChanFlag: %d +3287,iiii,[ phyrf_reset.c : 919 ] DumpTpc-4: set trasmit chan power: %d, 2g limit: %d, 5g limit: %d, max tx: %d +3286,i,[ phyrf_reset.c : 920 ] phyrf_reset_SetTxPowerScale: homeChanFlag: %d +3285,iiii,[ phyrf_reset.c : 1128 ] UpdateResetParms : homeChannel[0] %d homeChannel[1] %d curChan freq1 %d curChan freq2 %d +3284,iiIi,[ phyrf_reset.c : 3486 ] PPET numNss_m1 %d, nss_2g %d, chainmask %x, numchains %d +3283,iiIi,[ phyrf_reset.c : 3502 ] PPET numNss_m1 %d, nss_5g %d, chainmask %x, numchains %d +3282,iii,[ phyrf_reset.c : 3512 ] PPET updated = %d (1=YES,0=NO) phyId %d rf_mode %d +3315,,[ phyrf_spectral.c : 312 ] SSCAN: Activating spectral scan +3314,,[ phyrf_spectral.c : 332 ] SSCAN: Deactivating spectral scan +3313,,[ phyrf_spectral.c : 463 ] SSCAN: Disabling spectral scan +3312,,[ phyrf_spectral.c : 229 ] SSCAN: Enabling spectral scan +3311,,[ phyrf_spectral.c : 356 ] SSCAN: Resetting spectral scan +3317,III,[ phyrf_tpc.c : 363 ] %s:chan 0x%x flag:0x%x + +3316,ii,[ phyrf_tpc.c : 509 ] setting plut and alut for 160 chan1 %d chan2 %d +3324,iii,[ phyrf_bdf_tpc.c : 1185 ] phyrf_tpc_device_ClpcPlutAlutUpdate tpcPowerOffset[%d] %d twoPtOffset[cmask] %d +3323,iiiii,[ phyrf_bdf_tpc.c : 237 ] return from phyrf_tpc_device_AlutGeneration as pdadc meas seems to be zero %d %d %d %d %d +3322,ii,[ phyrf_bdf_tpc.c : 814 ] ##TPC_DBG: GVC Chan %d CalDB %d + +3321,i,[ phyrf_bdf_tpc.c : 919 ] GLUT_PROG_ERROR: pRawCalPerPointOlpcGtxExt was unexpectedly NULL, last 2 entries of GLUT NOT BEING PROGRAMMED maxGlutIdx = %d +3320,Iiiiii,[ phyrf_bdf_tpc.c : 1014 ] ##GVC0 chIDX %lu, pwr %d, dGain %d, gIdx %d, paCfg %d, maxGlutIdx %d + +3319,ii,[ phyrf_bdf_tpc.c : 819 ] ##TPC_DBG: sec80 Chan %d sec80 CalDB %d + +3318,i,[ phyrf_bdf_tpc.c : 832 ] Zero TPC FreqPiers for the band %d + +3334,i,[ wlan_swbmiss_offload.c : 535 ] wlan_bmiss_update_hwbmiss = %d +3333,iiiiiiii,[ wlan_swbmiss_offload.c : 685 ] SWBMISS_NULL_SEND_CMPLT: vdev_id=%d, isQosNullSuccess=%d, isFinalBmiss=%d, first_bmiss_detected=%d, final_bmiss_detected=%d, fbmiss_evnt_posted=%d, vbmiss->connected = %d, cons_bmiss_count = %d +3332,ii,[ wlan_swbmiss_offload.c : 554 ] SWBMISS_BCON_RECVED: vdev_id=%d, IS_HWBMISS=%d +3331,iiiiiii,[ wlan_swbmiss_offload.c : 994 ] SWBMISS_TIMER_FN: vdev_id=%d, curr_bmiss_bcnt=%d, pre_bmiss_detected=%d, first_bmiss_detected=%d, final_bmiss_detected=%d, b_timeout=%d, cons_bmiss_count = %d +3330,i,[ wlan_swbmiss_offload.c : 423 ] wlan_swbmiss_check_if_bmiss_enabled: vdev id=%d, bmiss timer isn't armed, restart it. +3329,iIii,[ wlan_swbmiss_offload.c : 1180 ] SWBMISS_DELIVER_EVT: vdev_id=%d, evt_type=0x%x, bcn_rssi_avg=%d, bcn_rssi_last=%d +3328,iiIiI,[ wlan_swbmiss_offload.c : 503 ] SWBMISS_DISABLED: vdev_id=%d, swbmiss_module_id=%d, bmiss_disable_bitmap=0x%x, curr_bmiss_bcnt=%d, cur_disable_bitmask=0x%x +3327,iiIii,[ wlan_swbmiss_offload.c : 459 ] SWBMISS_ENABLED: vdev_id=%d, swbmiss_module_id=%d, bmiss_disable_bitmap=0x%x, curr_bmiss_bcnt=%d, final_bmiss_detected=%d +3326,ii,[ wlan_swbmiss_offload.c : 615 ] SWBMISS_TIMER_SET: vdev_id=%d, timeout_val=%d +3325,iiii,[ wlan_swbmiss_offload.c : 1249 ] SWBMISS_VDEV_EVT: vdev_id=%d, mac id %d notif=%d , HBMISS %d +3420,,[ wlan_dev.c : 8360 ] WMI_PDEV_SET_WMM_PARAMS_CMDID DEPRECATED - use VDEV level command instead +3419,i,[ wlan_dev.c : 9152 ] ANI_WMI: WMI_PDEV_GET_HALPHY_CAL_STATUS_CMDID - pdev_id=%d + +3418,i,[ wlan_dev.c : 9199 ] WMI_PDEV_SMART_ANT_ENABLE_CMDID gpio_handler_num : %d +3417,i,[ wlan_dev.c : 9229 ] WMI_PDEV_SMART_ANT_ENABLE_CMDID loop number : %d +3416,i,[ wlan_dev.c : 9440 ] BSS_CHAN_INFO_CMD_RCVD mac_id:%d +3415,IIII,[ wlan_dev.c : 9621 ] WMI_GPIO_CONFIG_CMDID: %x %x %x %x +3414,II,[ wlan_dev.c : 9692 ] WMI_GPIO_OUTPUT_CMDID: %x %x +3413,,[ wlan_dev.c : 9696 ] WMI_GPIO_OUTPUT_CMDID: set output value with tx/rx suspend. +3412,,[ wlan_dev.c : 9700 ] WMI_GPIO_OUTPUT_CMDID: set output value only. +3411,,[ wlan_dev.c : 8566 ] wlan_pdev_resume_cmd: NOT expected to receive during wifi on +3410,i,[ wlan_dev.c : 8579 ] wlan_pdev_resume_cmd: NOT expected to receive during wifi on, mac id=%d +3409,,[ wlan_dev.c : 8812 ] WMI_REQUEST_LINK_STATS_CMDID, ftm mode +3408,iII,[ wlan_dev.c : 8942 ] WMI_LRO_CONFIG_CMDID 1 mac=%d en=%x flags=%x +3407,II,[ wlan_dev.c : 7957 ] smart_ant_gpio_handler smart_gpio_cfg.gpio_num :%x, smart_gpio_cfg.func: %x +3406,iiii,[ wlan_dev.c : 3176 ] To serve %d peers %d TIDs is enough (TQM TIDs = %d, TQM BYPASS TIDs = %d) +3405,iiii,[ wlan_dev.c : 3183 ] To serve %d peers %d TIDs required (TQM TIDs = %d, TQM BYPASS TIDs = %d) +3404,ii,[ wlan_dev.c : 7131 ] wlan_dev_set_pcl not match pcl_cnt=%d,supp_chan_cnt=%d +3403,iii,[ wlan_dev.c : 7157 ] wlan_dev_set_pcl: cur_category %d: num_chans_in_category %d -> cur_idx %d +3402,i,[ wlan_dev.c : 7165 ] wlan_dev_set_pcl: num_chans=%d +3401,i,[ wlan_dev.c : 10092 ] unit_test: sleep for %d ms +3400,I,[ wlan_dev.c : 10101 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_ABG_MODE_TX_CHAIN_NUM, value = 0x%x +3399,I,[ wlan_dev.c : 10114 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_TX_CHAIN_MASK, value=0x%x +3398,I,[ wlan_dev.c : 10123 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_RX_CHAIN_MASK, value=0x%x +3397,I,[ wlan_dev.c : 10133 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, value=0x%x +3396,I,[ wlan_dev.c : 10143 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, value=0x%x +3395,I,[ wlan_dev.c : 10153 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, value=0x%x +3394,I,[ wlan_dev.c : 10163 ] wlan_dev_unit_test: cmd = WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, value=0x%x +3393,ii,[ wlan_dev.c : 10173 ] wlan_dev_unit_test: cca_busy_detector_config time_diff_threshold = %d us, cca_busy_percent_threshold = %d +3392,I,[ wlan_dev.c : 10242 ] wlan_dev_unit_test: obss_pd_th = %x +3391,I,[ wlan_dev.c : 10263 ] error on wlan_log_save_module_level: mod_id=%u +3390,IIII,[ wlan_dev.c : 10285 ] PDEV_configs atf_config 0x%x, tx_chain_mask 0x%x, rx_chain_mask 0x%x, num_peers 0x%x +3389,IIII,[ wlan_dev.c : 10287 ] PDEV_configs cur_channel_mhz 0x%x, home_channel_mhz 0x%x vdev_active_count 0x%x, vow_config 0x%x +3388,III,[ wlan_dev.c : 10289 ] PDEV_configs rx_decap_count 0x%x, max_nss 0x%x dynamic_bw 0x%x +3387,iiii,[ wlan_dev.c : 473 ] GreenAP Curr Chainmask: %d/%d, Phy_mode: %d, bw[20/40/80/160]: %d +3386,iiiii,[ wlan_dev.c : 475 ] GreenAP saved tx/rx chainmask: %d/%d, phymode: %d, freq1: %d, valid flag: %d +3385,iii,[ wlan_dev.c : 477 ] GreenAP cur_channel mhz: %d, freq1: %d, freq2: %d +3384,,[ wlan_dev.c : 3739 ] phymode_param Received multi-vdev command +3383,iii,[ wlan_dev.c : 3819 ] Update Stream: vdev_id=%d preferred_tx_stream = %d preferred_rx_stream = %d +3382,ii,[ wlan_dev.c : 3827 ] phymode_param: applying phymode=%d for vdev at index %d +3381,IIi,[ wlan_dev.c : 10737 ] wlan_pdev_get_hw_mode_transition_event: old_hw_idx=0x%x, new_hw_idx=0x%x, vdev_num=%d +3380,ii,[ wlan_dev.c : 11309 ] wlan_pdev_handle_get_channel_ani_cmd max_channel_limit %d, received_count %d +3379,i,[ wlan_dev.c : 11321 ] wlan_pdev_handle_get_channel_ani_cmd memory allocation failed, %d +3378,iii,[ wlan_dev.c : 11353 ] wlan_pdev_handle_get_channel_ani_cmd freq:%d, mac_id:%d, ani:%d +3377,i,[ wlan_dev.c : 11357 ] wlan_pdev_handle_get_channel_ani_cmd unsupported freq:%d +3376,iiiI,[ wlan_dev.c : 7565 ] pdev_id = %d: DMA %d push config status %d event %p +3375,i,[ wlan_dev.c : 2762 ] BSS_CHAN_INFO_EVENT_SENT mac_id:%d +3374,ii,[ wlan_dev.c : 500 ] GreenAP wlan_pdev_set_greenap_cmd enable: %d, zero_client:%d +3373,,[ wlan_dev.c : 512 ] GreenAP GAP_ENABLE AWGN_INT_DBG AWGN Timer Disabled +3372,,[ wlan_dev.c : 542 ] GreenAP GAP_ENABLE AWGN_INT_DBG AWGN Timer Enabled +3371,,[ wlan_dev.c : 554 ] GreenAP GAP_ENABLE AWGN_INT_DBG AWGN Timer Disabled +3370,,[ wlan_dev.c : 575 ] GreenAP GAP_ENABLE AWGN_INT_DBG AWGN Timer Enabled +3369,I,[ wlan_dev.c : 7212 ] wlan_pdev_set_hw_mode: HW_Mode_Idx = 0x%x +3368,I,[ wlan_dev.c : 7244 ] wlan_pdev_set_hw_mode: DBSMGR_Ret_Status = 0x%x +3367,,[ wlan_dev.c : 7389 ] wlan_pdev_set_hw_mode_resp_event: WMI Event Alloc Failed!!! +3366,II,[ wlan_dev.c : 7429 ] wlan_pdev_set_hw_mode_resp_event: status=0x%x, cfg_hw_mode_idx=0x%x +3365,,[ wlan_dev.c : 7298 ] WMI_PDEV_SET_MAC_CONFIG_RESP_EVENT: WMI Event Alloc Failed!!! +3364,I,[ wlan_dev.c : 7315 ] WMI_PDEV_SET_MAC_CONFIG_RESP_EVENT: status=0x%x +3363,I,[ wlan_dev.c : 4248 ] wlan_pdev_set_param: WMI_PDEV_PARAM_TX_CHAIN_MASK 0x%x +3362,I,[ wlan_dev.c : 4290 ] wlan_pdev_set_param: WMI_PDEV_PARAM_TX_CHAIN_MASK 0x%x not valid +3361,I,[ wlan_dev.c : 4323 ] wlan_pdev_set_param: WMI_PDEV_PARAM_RX_CHAIN_MASK 0x%x +3360,I,[ wlan_dev.c : 4345 ] wlan_pdev_set_param: WMI_PDEV_PARAM_RX_CHAIN_MASK 0x%x not valid +3359,,[ wlan_dev.c : 5232 ] PDEV_PARAM_RX_FILTER not supported +3358,I,[ wlan_dev.c : 5404 ] PDEV_PARAM_IOT_PATTERN=%08x +3357,,[ wlan_dev.c : 5519 ] PDEV_PARAM_GCMP_SUPPORT_ENABLE not handled in FW +3356,III,[ wlan_dev.c : 11916 ] wlan_pdev_tsf_auto_report return detla too small, pdev_%x, delta(%x/%x) +3355,III,[ wlan_dev.c : 11927 ] wlan_pdev_tsf_auto_report return in wow, pdev_%x, delta(%x/%x) +3354,,[ wlan_dev.c : 11948 ] wlan_pdev_tsf_auto_report: no memory +3353,iiIIIIII,[ wlan_dev.c : 11981 ] wlan_pdev_tsf_auto_report: vdev_id = %d, mac_id = %d, tsf_low = 0x%x(%u), qtimer_low=0x%x(%u),cur_delta_0x%x(%u) +3352,,[ wlan_dev.c : 7776 ] WMI_PDEV_UPDATE_PKT_ROUTING_CMDID SOC level command not valid + +3351,II,[ wlan_dev.c : 4193 ] wlan_pdev_set_param: soft_tx_chain_mask pdev-id = 0x%x vdev_id = 0x%x +3350,IIII,[ wlan_dev.c : 4207 ] wlan_pdev_set_param: WMI_PDEV_PARAM_TX_CHAIN_MASK soft_tx_chain_mask enabled = 0x%x tx_chain_mask_strem = 0x%x preferred_tx_stream = 0x%x vdev_id = 0x%x +3349,ii,[ wlan_dev.c : 3641 ] wlan_resync_imps: IMPS_ENABLED=%d, VDEV_UP_COUNT=%d +3348,,[ wlan_dev.c : 11127 ] DISPLAY_TPC_STATS: Alloc tpc_configs_reg_event_buf failed + +3347,,[ wlan_dev.c : 11151 ] DISPLAY_TPC_STATS: Alloc tgt_pwrs_event_buf failed + +3346,,[ wlan_dev.c : 11179 ] DISPLAY_TPC_STATS: Alloc tgt_pwrs_set2_event_buf failed + +3345,,[ wlan_dev.c : 11208 ] DISPLAY_TPC_STATS: Alloc ctl_event_buf failed + +3344,,[ wlan_dev.c : 11217 ] DISPLAY_TPC_STATS: Allocation complete! +3343,,[ wlan_dev.c : 11770 ] ANI - Memory Allocation fail +3342,,[ wlan_dev.c : 11792 ] ANI - Invalid PDEV_ID +3341,i,[ wlan_dev.c : 11794 ] ANI - CCK_level=%d +3340,,[ wlan_dev.c : 11720 ] ANI - Memory Allocation fail +3339,,[ wlan_dev.c : 11742 ] ANI - Invalid PDEV_ID +3338,i,[ wlan_dev.c : 11744 ] ANI - OFDM_level=%d +3337,IiiI,[ wlan_dev.c : 6899 ] WMI: WMI_PDEV_AOA_PHASEDELTA_EVENTID pdev_id %ld freq %d Len %d chainInfo %x +3336,II,[ wlan_dev.c : 6866 ] WMI: WMI_PDEV_GET_DPD_STATUS_EVENTID pdev_id %ld ev->dpd_status %ld +3335,III,[ wlan_dev.c : 12133 ] ANI_WMI: WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID ev->pdev_id=%ld cal_bmap=%ld cal_status=%ld +3509,,[ wlan_peer.c : 6366 ] Invalid sta_fixed_rate: Found CCK rate in 5G + +3508,,[ wlan_peer.c : 6383 ] Invalid sta_fixed_rate: Found CCK rate in 5G + +3507,IIIIIIII,[ wlan_peer.c : 6465 ] WMI_PEER_PARAM_DISABLE_AGGRESSIVE_TX:peer %x value %x mac_address %x:%x:%x:%x:%x:%x +3506,,[ wlan_peer.c : 6908 ] PEER_CHAN_WIDTH null vdev +3505,IIi,[ wlan_peer.c : 6933 ] Invalid CHAN_WIDTH_SWITCH: mac_addr31to0 = 0x%x, mac_addr47to32 = 0x%x, phy_mode %d +3504,iIiiI,[ wlan_peer.c : 6945 ] Invalid CHAN_WIDTH_SWITCH:peer_id = %d chan_width =0x%X, new_phy_mode= %d old_phy_mode = %d he_mcs_nss_160=0x%x +3503,iIiiI,[ wlan_peer.c : 6951 ] Invalid CHAN_WIDTH_SWITCH:peer_id = %d chan_width =0x%X, new_phy_mode= %d old_phy_mode = %d he_mcs_nss_80_80=0x%x +3502,iIIiiI,[ wlan_peer.c : 583 ] RESOURCE_PEER_ALLOC duplicate PEER_TYPE_BSS vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x mac_id = %d/%d peer=0x%x +3501,iIIIi,[ wlan_peer.c : 719 ] wal peer allocaton status = %d vdev_id_8/mac_id_8 = 0x%x mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x peer_type = %d +3500,iIIiiIi,[ wlan_peer.c : 594 ] RESOURCE_PEER_ALLOC duplicate PEER_TYPE_BSS vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x mac_id = %d/%d peer=0x%x peer_del_in_prog %d +3499,iIIIi,[ wlan_peer.c : 696 ] wal peer allocaton status = %d vdev_id_8/mac_id_8 = 0x%x mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x peer_type = %d +3498,,[ wlan_peer.c : 279 ] wlan_find_peer: NULL vdev +3497,iIIi,[ wlan_peer.c : 924 ] VDEV EVT:RESOURCE_PEER_FREE vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x usage_count = %d +3496,IiII,[ wlan_peer.c : 950 ] CP-WARN DUP PEER-DELETE: wlan_free_peer wal_peer:0x%x PEER_ID:%d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x +3495,iI,[ wlan_peer.c : 1022 ] VDEV EVT PEER: wlan_free_peer del_resp=%d, wal_peer:0x%x +3494,iI,[ wlan_peer.c : 2765 ] HE160NSS : 160_mcs_nss_set %d, 160_mcs_nss_map %x +3493,II,[ wlan_peer.c : 7474 ] Deauth frame is not sent because of different RT thread addr1 0x%x addr2 = 0x%x +3492,,[ wlan_peer.c : 3136 ] rc_node_update: ABORT +3491,iiIIiiII,[ wlan_peer.c : 5595 ] WLAN_PEER_ASSOC_REQ peer %d peer_assoc_evt %d, ni_flags 0x%x, valid_tx_chainmask 0x%x, peer_nss %d, phymode %d, ni_vht_mcs_set 0x%x, ni_legacy_rate_set 0x%x, +3490,ii,[ wlan_peer.c : 5615 ] WLAN_PEER_CHANGE_BW: peerid=%d bw=%d +3489,iii,[ wlan_peer.c : 5665 ] WLAN_PEER_CHANGE_NSS peer %d peer_nss %d ul_nss %d +3488,ii,[ wlan_peer.c : 5698 ] WLAN_PEER_CHANGE_PHY_MODE: peerid=%d phymode=%d +3487,iIIiiII,[ wlan_peer.c : 5726 ] WLAN_PEER_CHANGE_CHAN_WIDTH peer %d ni_flags 0x%x, valid_tx_chainmask 0x%x, peer_nss %d, phymode %d, ni_vht_mcs_set 0x%x, ni_legacy_rate_set 0x%x, +3486,II,[ wlan_peer.c : 2658 ] OMI: wlan_peer_set_11ax_omi_param: disable mu :ulmu_disable: 0x%lx, ulmu_data_disable: 0x%lx, + +3485,II,[ wlan_peer.c : 2666 ] OMI: wlan_peer_set_11ax_omi_param: enable mu :ulmu_disable: 0x%lx, ulmu_data_disable: 0x%lx, + +3484,III,[ wlan_peer.c : 2682 ] Assoc OMI: NSS=0x%x BW=0x%x er_su_disable=0x%x +3483,iIIi,[ wlan_peer.c : 5913 ] PEER_TID_DEBUG: vdev_id:%d mac addr:0x%08x 0x%08x tid_num:%d +3482,iiiiiIiii,[ wlan_peer.c : 5924 ] PEER_TID_DEBUG: ack:%d aggr:%d rate:%d rcode:%d sw_retry:%d bitmap:0x%x rts_cts:%d ampdu:%d amsdu:%d +3481,iiIIii,[ wlan_peer.c : 1777 ] peer_update status=%d,vdevid=%d,macaddr=0x%8x0x%4x peer_type=%d,req_peer_type=%d + +3480,IIII,[ wlan_peer.c : 5212 ] wal_vdev non_data_rc:0x%x bcast_data_rc:0x%x mcast_data_rc:0x%x beacon_rc:0x%x + +3479,I,[ wlan_peer.c : 5234 ] wal_peer: %x, wlan_peer_vdev_restart_done: tearing down tx_ba and rx_ba +3478,II,[ wlan_peer.c : 5250 ] update non data1, peer:0x%x, rc:0x%x +3477,II,[ wlan_peer.c : 5281 ] update rts_rix, peer:0x%x, rts_rix:0x%x +3476,i,[ wlan_peer.c : 5803 ] WMI_PEER_UNMAP_RESPONSE_CMDID: %d +3475,ii,[ wlan_peer.c : 5810 ] peer_id[%d]: %d +3474,I,[ wlan_peer.c : 2363 ] wlan_set_peer_he_txbf_cap:ax_txbf_caps.suax_max_nc=%x +3473,I,[ wlan_peer.c : 1484 ] wlan_set_peer_vht_txbf_cap vht_caps: %x +3472,III,[ wlan_peer.c : 1515 ] Nr=%x Nrx=%x, Nc=%x + +3471,IIII,[ wlan_peer.c : 1597 ] Nr=%x Nc=%x peer_nss=%x Ntx=%x +3470,iIIiii,[ wlan_peer.c : 488 ] RESOURCE_PEER_ALLOC error vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x usage_count = %d, peer_type = %d, delete_in_process:%d +3469,iIIiii,[ wlan_peer.c : 499 ] RESOURCE_PEER_ALLOC error return as peer delete is in progress vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x usage_count = %d, peer_type = %d, delete_in_process:%d +3468,ii,[ wlan_peer.c : 3051 ] Invalid PEER_CAP: mismatch of phymode pream(%d) vs ni_flags pream(%d) + +3467,ii,[ wlan_peer.c : 3060 ] Invalid PEER_CAP: ni_flags bw(%d) is greater than peer phymode(%d) + +3466,I,[ wlan_peer.c : 3075 ] Invalid PEER_CAP: phymode is 160Mhz but no valid rates are set %x + +3465,I,[ wlan_peer.c : 3084 ] Invalid PEER_CAP: phymode is 80Mhz but no valid rates are set %x + +3464,,[ wlan_peer.c : 3094 ] Invalid PEER_CAP: LDPC not set in 11AXA for bw 40/80/160 + +3463,Iii,[ wlan_peer.c : 7247 ] wlan_vdev_delete_all_peer_conf_msg_hdlr: wal_vdev=%p, delete_all_peer_in_progress=%d, WLAN_FW_THREAD_IS_RT=%d + +3462,i,[ wlan_peer.c : 7252 ] wlan_vdev_delete_all_peer_conf_msg_hdlr: vdev_id=%d + +3461,ii,[ wlan_peer.c : 7322 ] wlan_vdev_delete_all_peer_conf_msg_hdlr: vdev_id=%d dbg_conf_del_all_peer_num = %d + +3460,i,[ wlan_peer.c : 2176 ] delete_all_peer: WMI_VDEV_DELETE_ALL_PEER_CMDID command for vdev_id %d + +3459,,[ wlan_peer.c : 2179 ] DELETE_ALL_PEER max vdev +3458,,[ wlan_peer.c : 2186 ] DELETE_ALL_PEER null vdev +3457,,[ wlan_peer.c : 2203 ] DELETE_ALL_PEER alredy in progress +3456,,[ wlan_peer.c : 2252 ] DELETE_ALL_PEER No active peer +3455,,[ wlan_peer.c : 3497 ] PEER_ASSOC null vdev +3454,,[ wlan_peer.c : 3513 ] PEER_ASSOC null peer +3453,,[ wlan_peer.c : 3515 ] PEER_ASSOC null wal_peer +3452,iiIIi,[ wlan_peer.c : 3640 ] PEER_ASSOC Overridding phymode. Orig phy %d, new phy %d. Orig flag 0x%x, new flag 0x%x. Error:%d +3451,IIiIIIii,[ wlan_peer.c : 3732 ] PEER_ASSOC cmd for mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x, num_peer_ht_rates=%d, ni_flags=0x%x phymode=0x%x nss=0x%x mpdudensity=%d max_mpdu=%d +3450,,[ wlan_peer.c : 4151 ] PEER_ASSOC Sending KO for STA as invalid phymode config +3449,,[ wlan_peer.c : 3502 ] PEER_ASSOC null vdev->bss +3448,IIIII,[ wlan_peer.c : 3394 ] PEER_ASSOC ni_legacy_rate_set= 0x%x ht_caps=0x%x vht_caps=0x%x vht_mcs_set=0x%x ht_mcs_set= 0x%x +3447,I,[ wlan_peer.c : 3413 ] Peer_assoc:peer_he_cap_phy = 0x%x +3446,II,[ wlan_peer.c : 3419 ] Peer_assoc: he_ops=0x%x he_cap_info_internal=0x%x +3445,iIIIII,[ wlan_peer.c : 4718 ] wlan_vdev_dispatch_peer_change_bw: peerid=%d prev_ni_flags=%x new_ni_flags=%x new_bw=%x ht_caps=%x vht_caps=%x +3444,iII,[ wlan_peer.c : 1830 ] peer create cmd ingored vdev_id =%d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x + +3443,iII,[ wlan_peer.c : 1840 ] peer create cmd ingored as delete all peer is in progress vdev_id =%d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x + +3442,II,[ wlan_peer.c : 1940 ] DFS nol protection peer create cmd ingored mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x + +3441,II,[ wlan_peer.c : 1951 ] peer create command for mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x + +3440,iII,[ wlan_peer.c : 2094 ] peer delete command for vdev_id %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x +3439,,[ wlan_peer.c : 2107 ] PEER_DELETE null vdev +3438,,[ wlan_peer.c : 2114 ] PEER_DELETE parent vdev delete_all_peer_in_progress +3437,,[ wlan_peer.c : 2139 ] PEER_DELETE peer not exist, still generating PEER_DELETE_RESP_EVENTID +3436,Ii,[ wlan_peer.c : 5147 ] wlan_vdev_dispatch_peer_mask_cck_rates is-2g=0x%x id=%d +3435,i,[ wlan_peer.c : 4427 ] RATE_DBG wlan_vdev_migrate_rate_reset peer_params NULL: peer_id %d +3434,i,[ wlan_peer.c : 4432 ] RATE_DBG wlan_vdev_migrate_rate_reset: peer_id %d +3433,I,[ wlan_peer.c : 4392 ] wlan_vdev_peer_autorate_reset: user_start_rate 0x=%x +3432,I,[ wlan_peer.c : 4583 ] wlan_vdev_peer_change_bw_internal: new_bw = %x +3431,ii,[ wlan_peer.c : 4523 ] wlan_vdev_peer_change_phymode_internal: peerid=%d phymode=%d +3430,IIIIi,[ wlan_peer.c : 5549 ] MASK_CCK_RATES: wlan_peer=0x%x rc_node=0x%x legacy_rate=0x%x is_cck_rate_mask=0x%x msg_id=%d +3429,I,[ wlan_peer.c : 5523 ] wlan_vdev_peer_mimo_ps_internal: valid_tx_chainmask 0x=%x +3428,II,[ wlan_peer.c : 4794 ] TXBF_UPDATE_PEER_PARAMS peer_nss = %u, nc_idx = %u. +3427,II,[ wlan_peer.c : 4803 ] TXBF_UPDATE_PEER_PARAMS peer_nss_160 = %u, nc_idx_160 = %u. +3426,iii,[ wlan_peer.c : 882 ] delete_all_peer: VDEV EVT:WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID vdevId=%d status=%d time=%d +3425,iiIIi,[ wlan_peer.c : 1755 ] VDEV EVT:WMI_PEER_CREATE_RESP_EVENTID send vdevId=%d time=%d peer_macaddr31to0 =0x%x peer_macaddr47to32 =0x%x status = %d +3424,,[ wlan_peer.c : 834 ] WMI_EVENT_ALLOC_FAILURE: WMI_PEER_DELETE_RESP_EVENTID buffer failure +3423,iiII,[ wlan_peer.c : 850 ] VDEV EVT:WMI_PEER_DELETE_RESP_EVENTID send vdevId=%d time=%d peer_macaddr31to0 =0x%x peer_macaddr47to32 =0x%x +3422,,[ wlan_peer.c : 5835 ] WMI_PEER_TX_PN_REQUEST : Invalid Peer +3421,ii,[ wlan_peer.c : 5844 ] WMI_PEER_TX_PN_REQUEST : vdev_id = %d, key_type = %d +3530,IIIII,[ wlan_mgmt_local_txrx.c : 2269 ] _wlan_local_send_peer_change_omi()invalid rx=0x%x bw=0x%x ulmu=0x%x tx=0x%x ulmu_data=0x%x + +3529,I,[ wlan_mgmt_local_txrx.c : 2284 ] _wlan_local_send_peer_change_omi()newOMI=0x%x +3528,III,[ wlan_mgmt_local_txrx.c : 1619 ] mac id mismatch:rx:%x vdev:%x, frame: %x + +3527,III,[ wlan_mgmt_local_txrx.c : 1763 ] mac id mismatch:rx:%x vdev:%x, frame: %x + +3526,,[ wlan_mgmt_local_txrx.c : 1826 ] IEEE80211_FC0_SUBTYPE_NDPA +3525,,[ wlan_mgmt_local_txrx.c : 419 ] SCAN_RADIO_SUPPORT_DBUG _wlan_mgmt_local_send cur_channel NULL +3524,ii,[ wlan_mgmt_local_txrx.c : 648 ] MGMT_TXRX_SENT_FROM_LOCAL: send failure:%d, flags:%d +3523,i,[ wlan_mgmt_local_txrx.c : 428 ] SCAN_RADIO_SUPPORT_DBUG: _wlan_mgmt_local_send DFS channel = %d Detected Skipping... + +3522,IIIIIiII,[ wlan_mgmt_local_txrx.c : 541 ] MGMT_TXRX_SENT_FROM_LOCAL: macidh8/tid8/ptype16:0x%08x, cbflags=0x%08x, peerflag=0x%x,addr=0x%08x 0x%04x cur_chan=%d ppdu_H32=0x%x ppdu_L32=0x%x +3521,I,[ wlan_mgmt_local_txrx.c : 2124 ] LOCAL MGMT DEAUTH-DISASSOC tx compl. status 0x%x +3520,IiI,[ wlan_mgmt_local_txrx.c : 923 ] _wlan_mgmt_local_send_nullfunc() get nullfunc failed: peer = %p peer_type = %d cb_flags: 0x%x +3519,IIIII,[ wlan_mgmt_local_txrx.c : 684 ] OMI: wlan_mgmt_txrx_send_omi rx_nss: 0x%lx, bw: 0x%lx, ulmu_disable: 0x%lx, ulmu_data_disable: 0x%lx, tx_nss: 0x%lx + +3518,IIIIIIIi,[ wlan_mgmt_local_txrx.c : 1436 ] FORWARD_TO_HOST: mgmt pkt, Ch_VdevActCnt_ToHost=0x%08x MacId_Type_Subtype=0x%06x Seq=%04d(0x%03x) Addr2=0x%04x 0x%08x RssiComb_Ch0_Ch1=0x%06x , sta_mon_mode=%d +3517,IIiIIi,[ wlan_mgmt_local_txrx.c : 1465 ] FORWARD_TO_HOST: not mgmt pkt, Ch_VdevActCnt_ToHost=0x%08x MacId_Type_Subtype=0x%06x Seq=%d(0x%x) RssiComb_Ch0_Ch1=0x%06x ,sta_mon_mode=%d +3516,i,[ wlan_mgmt_local_txrx.c : 672 ] wlan_mgmt_txrx_omi_req_completion: set mu as %d + +3515,II,[ wlan_mgmt_local_txrx.c : 730 ] setUnitTestCmd 13 9 1 %x %x - couldn't find peer! +3514,IIIIiI,[ wlan_mgmt_local_txrx.c : 741 ] OMI: Unit test with rx_nss = 0x%lx, bw = 0x%lx, ulmu disable = 0x%lx, tx_nss = 0x%lx, er_su disable %d, ulmu_data_disable = 0x%lx + +3513,,[ wlan_mgmt_local_txrx.c : 745 ] Invalid input for OMI unit test. + +3512,,[ wlan_mgmt_local_txrx.c : 799 ] Invalid input for muedca unit test to set mu wmm params. + +3511,,[ wlan_mgmt_local_txrx.c : 831 ] Invalid input for muedca unit test to emulate trigger frm. + +3510,I,[ wlan_mgmt_local_txrx.c : 841 ] Unit test: mu edca enable = %lu + +3560,I,[ wlan_mgmt_txrx.c : 1403 ] QOS_NULL_TX_WMI_FROM_HOST: Host is not expected to use this command other than QoS null, frame subtype = 0x%X +3559,IIIi,[ wlan_mgmt_txrx.c : 1452 ] QOS_NULL_TX_WMI_FROM_HOST subtype=0x%02x addr=0x%04x%08x chanfreq=%d +3558,iiIiI,[ wlan_mgmt_txrx.c : 1457 ] QOS_NULL_TX_WMI_FROM_HOST tx_param_valid=%d frame_len=%d desc_id=0x%x tid_num=%d ppdu_info=0x%x +3557,iIiI,[ wlan_mgmt_txrx.c : 1505 ] QOS_NULL_TX_WMI_FROM_HOST FAIL invalid input param vdev_id=%d, vdev_opmode=%x, desc_id=%d peer =0x%X +3556,I,[ wlan_mgmt_txrx.c : 1411 ] QOS_NULL_TX_WMI_FROM_HOST: Command is expected only for AP VDEV wlan_vdev->ic_opmode= 0x%X +3555,I,[ wlan_mgmt_txrx.c : 1420 ] QOS_NULL_TX_WMI_FROM_HOST: Expected wlan peer value = 0x%X +3554,IIi,[ wlan_mgmt_txrx.c : 374 ] _wlan_mgmt_rx_frame_handler Droping frame from non associated Peer type=0x%x subtype=0x%x bNull=%d +3553,,[ wlan_mgmt_txrx.c : 2384 ] SCAN_RADIO_SUPPORT_DBUG WMI_SCAN_EVENT_FOREIGN_CHANNEL_ENTRY pmac NULL +3552,,[ wlan_mgmt_txrx.c : 2390 ] SCAN_RADIO_SUPPORT_DBUG WMI_SCAN_EVENT_FOREIGN_CHANNEL_ENTRY cur_channel NULL +3551,ii,[ wlan_mgmt_txrx.c : 2417 ] SCAN_RADIO_SUPPORT_DBUG WMI_SCAN_EVENT_FOREIGN_CHANNEL_ENTRY DFS_Flag = %d channel = %d +3550,IIii,[ wlan_mgmt_txrx.c : 1642 ] MGMT_TX_WMI_FROM_HOST is_home_8/is_curr_8=0x%x mode_8/submode_8=0x%x pmac->mac_id=%d e_mac_id=%d +3549,IIIii,[ wlan_mgmt_txrx.c : 1734 ] MGMT_TX_WMI_FROM_HOST subtype=0x%02x addr=0x%04x%08x chanfreq=%d peer_rssi=%d +3548,iiIiIIiI,[ wlan_mgmt_txrx.c : 1739 ] MGMT_TX_WMI_FROM_HOST check_tag=%d tx_param_valid=%d cmd_ch=0x%x frame_len=%d tx_flags=0x%x desc_id=0x%x tid_num=%d ppdu_info=0x%x +3547,,[ wlan_mgmt_txrx.c : 1823 ] Dropping CFR capture +3546,ii,[ wlan_mgmt_txrx.c : 2534 ] MGMT_TX_WMI_FROM_HOST register %d %d +3545,ii,[ wlan_mgmt_txrx.c : 2539 ] MGMT_TX_WMI_FROM_HOST register %d %d +3544,ii,[ wlan_mgmt_txrx.c : 2545 ] MGMT_TX_WMI_FROM_HOST register %d %d +3543,iiIi,[ wlan_mgmt_txrx.c : 2261 ] WMI TX comp hold, idx:%d, desc id=%d, frame_type_subtype=0x%x, comp=%d +3542,I,[ wlan_mgmt_txrx.c : 1898 ] WMI TX comp send bundle: bundle_evt_size:0x%x +3541,iii,[ wlan_mgmt_txrx.c : 1963 ] WMI TX comp send bundle, num:%d, desc id=%d comp=%d +3540,,[ wlan_mgmt_txrx.c : 2069 ] MGMT_TX_WMI_TXCOMP_SEND_EVT PKT NULL +3539,,[ wlan_mgmt_txrx.c : 2075 ] MGMT_TX_WMI_TXCOMP_SEND_EVT PKT NULL +3538,IIii,[ wlan_mgmt_txrx.c : 2119 ] MGMT_TX_WMI_FROM_HOST_COMP desc_id=0x%x tx_status=0x%x ppdu_id:%d ack_rssi=%d +3537,I,[ wlan_mgmt_txrx.c : 964 ] WMI_SEND_EVENT_WRONG_TLV CmdId/EventId = 0x%x +3536,I,[ wlan_mgmt_txrx.c : 877 ] WMI_SEND_EVENT_WRONG_TLV CmdId/EventId = 0x%x +3535,,[ wlan_mgmt_txrx.c : 1978 ] OFFCHAN_DATA_TX_WMI_TXCOMP_SEND_EVT PKT NULL +3534,II,[ wlan_mgmt_txrx.c : 1994 ] MGMT_TX_WMI_FROM_HOST_COMP desc_id=0x%x tx_status=0x%x +3533,,[ wlan_mgmt_txrx.c : 2013 ] QOS_NULL_TX_WMI_FROM_HOST PKT NULL +3532,IIIII,[ wlan_mgmt_txrx.c : 2032 ] QOS_NULL_TX_WMI_FROM_HOST Send Evt: desc_id = 0x%x comp_type=0x%x,pdev_id =0x%X, ppdu_id=0x%X ack_rssi =0x%X +3531,IIIII,[ wlan_mgmt_txrx.c : 1317 ] MGMT_TX_WMI_FROM_HOST: dword0=0x%x dword1=0x%x, subtype:%x, ppdu_info:0x%x multiplier:0x%x +3599,iii,[ offload_mgr.c : 1763 ] OFLD drop wmi evt, id=%d, len:%d status:%d +3598,iii,[ offload_mgr.c : 332 ] OFLD dereg data name=%d vdev id=%d,vdev mask=%d +3597,ii,[ offload_mgr.c : 434 ] OFLD dereg htt name=%d ref_cnt=%d +3596,ii,[ offload_mgr.c : 312 ] OFLD dereg nondata name=%d ref_cnt=%d +3595,ii,[ offload_mgr.c : 413 ] OFLD dereg wmi name=%d ref_cnt=%d +3594,,[ offload_mgr.c : 961 ] drop data in wow awake +3593,I,[ offload_mgr.c : 980 ] OFLD remote data hdlr dropping frame as L2_valid :%x +3592,II,[ offload_mgr.c : 996 ] OFLD remote data hdlr ds2ds, id:%x, mode:%x +3591,II,[ offload_mgr.c : 1003 ] OFLD remote data hdlr nonds, id:%x, mode:%x +3590,iiii,[ offload_mgr.c : 1012 ] OFLD remote data hdlr pktlen=%d, dataT=%d addrT=%d vdevId=%d +3589,iii,[ offload_mgr.c : 1077 ] OFLD enhanced data hdlr ofld id=%d status=%d, wow data state:%d +3588,I,[ offload_mgr.c : 1815 ] evt store:%x +3587,III,[ offload_mgr.c : 1437 ] offldmgr_non_data_handler: Received rx buf as null for peer = 0x%x mac_id =0x%X rxbuf =0x%X +3586,III,[ offload_mgr.c : 1530 ] _ofld_non_data_hdlr: peer = 0x%x addr1 0x%x addr2 = 0x%x +3585,II,[ offload_mgr.c : 1628 ] _ofld_nondata_hdlr: status_h8/sub_sts_8/ofld_id_16:0x%x frmtyp = 0x%x +3584,II,[ offload_mgr.c : 1733 ] _ofld_nondata_hdlr: status = 0x%x frmtyp = 0x%x +3583,ii,[ offload_mgr.c : 1127 ] OFLD proto data hdlr ret_Status=%d curr_wow=%d +3582,III,[ offload_mgr.c : 201 ] OFLD reg data name=0x%x, vdevid:0x%x, vdev_bitmap:0x%x +3581,ii,[ offload_mgr.c : 220 ] OFLD reg data vdev id=%d, max_len =%d +3580,II,[ offload_mgr.c : 276 ] OFLD reg HTT name=0x%x, refcnt:0x%x +3579,II,[ offload_mgr.c : 160 ] OFLD reg nondata name=0x%x, refcnt:0x%x +3578,II,[ offload_mgr.c : 238 ] OFLD reg wmi name=0x%x, refcnt:0x%x +3577,ii,[ offload_mgr.c : 1936 ] OFLD wmi evt flush evt_id=%d, evt_len=%d +3576,ii,[ offload_mgr.c : 1905 ] OFLD wmi evt store evt_id=%d, evt_len=%d +3575,,[ offload_mgr.c : 1910 ] ofld wmi evt store failure - no memory +3574,Iiiii,[ offload_mgr.c : 700 ] OFLD data parse 11c_snap_hdr_t exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d,dsDir:%d +3573,Iiii,[ offload_mgr.c : 747 ] OFLD data parse llc_snap_hdr_t exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3572,i,[ offload_mgr.c : 763 ] Unknown RX Decap mode %d +3571,IIIIII,[ offload_mgr.c : 789 ] OFLD data parse DA %x %x %x %x %x %x +3570,iiI,[ offload_mgr.c : 792 ] OFLD data parse rx_mode:%d, L3 offset=%d, L2 ethType=%x +3569,Iiii,[ offload_mgr.c : 817 ] OFLD data parse IP_HDR exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3568,Iiii,[ offload_mgr.c : 833 ] OFLD data parse IP6_HDR exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3567,Iiii,[ offload_mgr.c : 865 ] OFLD data parse TCP_HDR exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3566,Iiii,[ offload_mgr.c : 878 ] OFLD data parse UDP_HDR exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3565,Iiii,[ offload_mgr.c : 890 ] OFLD data parse ICMPV6_HDR exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3564,Iiii,[ offload_mgr.c : 730 ] OFLD data parse ether_header exceeds frame length pktbuf:%x,rx_mode:%d,buf_len:%d,offset:%d +3563,ii,[ offload_mgr.c : 1353 ] scan_radio_allow_tx_on_dfs_ofld_nondata_hdlr Vdev is not Up/Active vdev_id = %d vdev_active = %d + +3562,iiiii,[ offload_mgr.c : 1365 ] scan_radio_allow_tx_on_dfs_ofld_nondata_hdlr Vdev_Unpause not done is_vdev_paused = %d is_DFS_channel = %d pdv_id = %d cur_mhz = %d hom_mhz = %d + +3561,iiiii,[ offload_mgr.c : 1377 ] scan_radio_allow_tx_on_dfs_ofld_nondata_hdlr Vdev_Unpause done is_vdev_paused = %d is_DFS_channel = %d pdv_id = %d cur_mhz = %d hom_mhz = %d + +3607,iII,[ channel_mgr.c : 58 ] CHAN_MGR_PAUSE_COMPLETE: curr_chan = %d link = 0x%x link_flgs = 0x%x +3606,,[ channel_mgr.c : 100 ] chan mgr pause complete timeout +3605,II,[ channel_mgr.c : 260 ] CHAN_MGR_CTS2S_TX_COMP: status = 0x%x ch_handle = 0x%x +3604,II,[ channel_mgr.c : 227 ] CHAN_MGR_PAUSE_CMPL_CB: status = 0x%x curr_time = 0x%x +3603,iIIiI,[ channel_mgr.c : 164 ] CHAN_MGR_VDEV_PAUSE: chan = %d link = 0x%x flg = 0x%x max_sw_time = %d curr_time = 0x%x +3602,III,[ channel_mgr.c : 131 ] CHAN_MANAGER_SM_EVENT_DATA: chan = 0x%x sec_chan = 0x%x sw_time = 0x%x +3601,iiIIIIi,[ channel_mgr.c : 434 ] CHAN_MGR_TRIGGER_CHANNEL_CHANGE: pri_ch = %d, chan_change_dur = %d,is_chm_valid = 0x%x tx_chm = 0x%x, rx_chm = 0x%x, selfgen_chm = 0x%x, pf_cnt = %d +3600,iII,[ channel_mgr.c : 198 ] CHAN_MGR_VDEV_UNPAUSE:chan =%d link =0x%x curr_time = 0x%x +3611,ii,[ channel_mgr_sm.c : 338 ] CHAN_MANAGER_SM: %d => %d +3610,III,[ channel_mgr_sm.c : 123 ] RESMGR_CHMGR_SEND_CTS2SELF: cur_vc = 0x%x link = 0x%x status = 0x%x +3609,ii,[ channel_mgr_sm.c : 320 ] CHAN_MANAGER_SM_EVENT: %d < %d + +3608,ii,[ channel_mgr_sm.c : 252 ] CHAN_MGR_UNPAUSE: PF %d, time %d +3613,II,[ resmgr_wmi.c : 83 ] RESMGR_OCS_INVALID_QUOTA Different MAC: chan0 = 0x%x chan1 = 0x%x +3612,II,[ resmgr_wmi.c : 136 ] RESMGR_OCS_INVALID_LATENCY Different MAC: chan0 = 0x%x chan1 = 0x%x +3621,II,[ resmgr.c : 349 ] RESMGR_DEREG_EVT_HDLR: handler = 0x%x arg = 0x%x not found!!! +3620,II,[ resmgr.c : 355 ] RESMGR_DEREG_EVT_HDLR: handler = 0x%x arg = 0x%x deregistered +3619,II,[ resmgr.c : 313 ] RESMGR_REG_EVT_HDLR: handler = 0x%x arg = 0x%x exists!!! +3618,II,[ resmgr.c : 321 ] RESMGR_REG_EVT_HDLR: handler = 0x%x arg = 0x%x no memory!!! +3617,II,[ resmgr.c : 331 ] RESMGR_REG_EVT_HDLR: handler = 0x%x arg = 0x%x registered +3616,III,[ resmgr.c : 145 ] RESMGR_OCS_REQ_QUOTA_STATS arg = 0x%x chan_mhz = 0x%x req_chan_time/latency = 0x%x +3615,III,[ resmgr.c : 153 ] RESMGR_OCS_REQ_QUOTA_STATS arg = 0x%x chan_mhz = 0x%x req_chan_time/latency = 0x%x +3614,III,[ resmgr.c : 167 ] RESMGR_OCS_REQ_QUOTA_STATS arg = 0x%x chan_mhz = 0x%x req_chan_time/latency = 0x%x +3622,i,[ resmgr_ocm_init.c : 42 ] RESMGR_OCS_ALLOCRAM_SIZE size_in_bytes = %d +3627,I,[ resmgr_ocm.c : 645 ] OCM_Migrate: migrate_mode = 0x%x +3626,II,[ resmgr_ocm.c : 702 ] OCM_Resume: ocs_cfg = 0x%x, Pause_OCS = 0x%x +3625,II,[ resmgr_ocm.c : 492 ] OCM_Suspend: Pause_Pending = 0x%x, Pause_OCS = 0x%x +3624,ii,[ resmgr_ocm.c : 783 ] resmgr_ocm_update_ocs_min_cat_dur: ocs_ins = %d, min_cat_dur = %d +3623,,[ resmgr_ocm.c : 383 ] RESMGR_OCS_CHAN_CHANGE_PROGRESS FAILURE +3628,i,[ resmgr_dyn_sch_init.c : 30 ] RESMGR_DYN_SCH_ALLOCRAM_SIZE size = %d +3636,iIII,[ resmgr_dyn_sch.c : 169 ] RESMGR_DYN_SCH_CH_SX_STATS chan_mhz = %d accu_tx_rx_dur_us = 0x%x accu_free_dur_us = 0x%x accu_sampling_dur_us = 0x%x +3635,iiii,[ resmgr_dyn_sch.c : 258 ] RESMGR_DYN_SCH_HOME_CH_QUOTA chan0_mhz = %d ch0_new_quota = %d chan1_mhz = %d ch1_new_quota = %d +3634,iIII,[ resmgr_dyn_sch.c : 176 ] RESMGR_DYN_SCH_CH_SX_STATS chan_mhz = %d accu_tx_rx_dur_us = 0x%x accu_free_dur_us = 0x%x accu_sampling_dur_us = 0x%x +3633,iiii,[ resmgr_dyn_sch.c : 190 ] RESMGR_DYN_SCH_TOT_UTIL_PER chan0_mhz = %d chan0_util_percentage = %d chan1_mhz = %d chan1_util_percentage = %d +3632,iiiii,[ resmgr_dyn_sch.c : 448 ] RESMGR_DYN_SCH_CH_STATS_END chan_mhz = %d rx_clear_cnt = %d tx_frame_cnt = %d rx_frame_cnt_us = %d sampling_dur_us = %d +3631,iiiii,[ resmgr_dyn_sch.c : 518 ] RESMGR_DYN_SCH_CH_STATS_START chan_mhz = %d start_rx_clear_cnt = %d start_tx_frame_cnt = %d start_rx_frame_cnt_us = %d start_time_us = %d +3630,II,[ resmgr_dyn_sch.c : 328 ] RESMGR_DYN_SCH_ENABLE enable = 0x%x fw_disable_bmap = 0x%x +3629,i,[ resmgr_dyn_sch.c : 90 ] RESMGR_DYN_SCH_ACTIVE is_active = %d +3637,i,[ resmgr_ocs_init.c : 93 ] RESMGR_OCS_ALLOCRAM_SIZE size_in_bytes = %d +3698,IIiii,[ resmgr_ocs.c : 4636 ] RESMGR_OCS_CHREQ_CREATE: req_id = 0x%x chan_req_addr = 0x%x chan_mhz = %d, sec_chan_mhz = %d prioirty = %d +3697,IiiIiI,[ resmgr_ocs.c : 4642 ] RESMGR_OCS_CHREQ_CREATE: start_tsf = 0x%x duration_usec = %d interval = %d dtim_start_tsf = 0x%x dtim_period = %d end_tsf = 0x%x +3696,IiI,[ resmgr_ocs.c : 4667 ] CHREQ_DELETE: chreq=0x%x chan=%d req_id(1)|state(1)|sec_chan(2)=0x%08x +3695,III,[ resmgr_ocs.c : 5042 ] CHREQ_START: chreq=0x%x chan(2)|sec_chan(2)=0x%08x req_id(1)|prio(1)|freq2(2)=0x%08x +3694,IiiIiI,[ resmgr_ocs.c : 5047 ] CHREQ_START: start_tsf=0x%x dur_usec=%d interval=%d dtim_start_tsf=0x%x dtim_period=%d end_tsf=0x%x +3693,IiI,[ resmgr_ocs.c : 5109 ] CHREQ_STOP: chreq=0x%x chan=%d req_id(1)|state(1)|sec_chan(2)=0x%08x +3692,I,[ resmgr_ocs.c : 4719 ] RESMGR_OCS_CHREQ_UPDATE: start_tsf/req_id = 0x%x +3691,IIIiiIII,[ resmgr_ocs.c : 4856 ] CHREQ_UPDATE: chreq=0x%x chan(2)|sec_chan(2)=0x%08x start_tsf=0x%x dur_usec=%d interval=%d req_id(1)|prio(1)|dtim_period(2)=0x%08x dtim_start_tsf=0x%x end_tsf=0x%x +3690,ii,[ resmgr_ocs.c : 2912 ] RESMGR_OCS_WIN_CAT_DUR duration = %d, chan_mhz = %d +3689,IIIIiIII,[ resmgr_ocs.c : 531 ] CHREQ_UPDATE chreq=0x%x chan(2)|sec_chan(2)=0x%08x start_tsf=0x%x dur_usec=0x%x interval=%d req_id(1)|prio(1)|purge(1)|dtim_period(1)=0x%08x dtim_start_tsf=0x%x, end_tsf=0x%x +3688,IIIi,[ resmgr_ocs.c : 611 ] RESMGR_OCS_CHREQ_RESTART start_tsf = 0x%x stop_tsf = 0x%x dtim_start_tsf = 0x%x dtim_period = %d +3687,,[ resmgr_ocs.c : 4473 ] RESMGR_OCS_CH_SWITCH_REQ +3686,II,[ resmgr_ocs.c : 1938 ] RESMGR_OCS_LATENCY_STRICT_TIME_SLOT slot1_start_tsf = 0x%x slot2_start_tsf = 0x%x +3685,I,[ resmgr_ocs.c : 1957 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3684,I,[ resmgr_ocs.c : 2128 ] RESMGR_OCS_CURR_TSF current_tsf = 0x%x +3683,II,[ resmgr_ocs.c : 2130 ] RESMGR_OCS_QUOTA_REM cat1_quota_remain = 0x%x cat2_quota_remain = 0x%x +3682,I,[ resmgr_ocs.c : 2175 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3681,I,[ resmgr_ocs.c : 2179 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3680,I,[ resmgr_ocs.c : 2203 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3679,I,[ resmgr_ocs.c : 2253 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3678,I,[ resmgr_ocs.c : 2257 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3677,I,[ resmgr_ocs.c : 2272 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3676,I,[ resmgr_ocs.c : 2301 ] RESMGR_OCS_LATENCY_CASE_NO arg = 0x%x +3675,I,[ resmgr_ocs.c : 3518 ] RESMGR_OCS_CLEANUP_CH_ALLOCATORS cur_ch_alloc_addr = 0x%x +3674,I,[ resmgr_ocs.c : 3537 ] RESMGR_OCS_CH_ALLOCATOR_FREE cur_ch_alloc_addr = 0x%x +3673,I,[ resmgr_ocs.c : 3588 ] RESMGR_OCS_CLEANUP_STALE_REQS cur_ch_alloc_addr = 0x%x +3672,II,[ resmgr_ocs.c : 3609 ] RESMGR_OCS_CHREQ_COMPLETE curr_time = 0x%x ch_req_addr = 0x%x +3671,II,[ resmgr_ocs.c : 3633 ] RESMGR_OCS_CHREQ_COMPLETE curr_time = 0x%x ch_req_addr = 0x%x +3670,IIi,[ resmgr_ocs.c : 3674 ] RESMGR_OCS_CHREQ_TERMINATE: req_id = 0x%x cur_ch_req = 0x%x state = %d +3669,Iii,[ resmgr_ocs.c : 1488 ] RESMGR_OCS_CONSTRUCT_CAT_WIN chan_alloc_addr=0x%x chan_mhz=%d sec_ch_mhz=%d +3668,Ii,[ resmgr_ocs.c : 1527 ] RESMGR_OCS_NEW_CAT_WINDOW_REQ ch_req_addr = 0x%x state = %d +3667,II,[ resmgr_ocs.c : 1530 ] RESMGR_OCS_NEW_CAT_WINDOW_TIMESLOT start_tsf = 0x%x stop_tsf = 0x%x +3666,IIIII,[ resmgr_ocs.c : 4385 ] RESMGR_OCS_RESOURCES req_id = 0x%x ch_req_addr = 0x%x ch_alloc_addr = 0x%x state = 0x%x priority = 0x%x +3665,iii,[ resmgr_ocs.c : 4388 ] RESMGR_OCS_RESOURCES chan_mhz = %d sec_chan_mhz = %d, band_center_freq2 = %d +3664,II,[ resmgr_ocs.c : 91 ] CHREQ_GRANT cur_time=0x%x chreq=0x%x +3663,II,[ resmgr_ocs.c : 678 ] RESMGR_OCS_CHREQ_COMPLETE curr_time = 0x%x ch_req_addr = 0x%x +3662,i,[ resmgr_ocs.c : 5145 ] RESMGR_OCS_CHANNEL_SWITCHED status = %d +3661,II,[ resmgr_ocs.c : 1853 ] RESMGR_OCS_MISS_TOLERANCE miss_tolerance_cnt_timeslot1 = 0x%x miss_tolerance_cnt_timeslot2 = 0x%x +3660,i,[ resmgr_ocs.c : 5294 ] RESMGR_OCS_NEXT_SCH_INTERVAL = %d +3659,Ii,[ resmgr_ocs.c : 3405 ] RESMGR_OCS_PURGE_CHREQ cur_ch_alloc_addr = 0x%x chan_mhz = %d +3658,I,[ resmgr_ocs.c : 3456 ] RESMGR_OCS_PURGE_CHREQ cur_ch_req_addr = 0x%x +3657,ii,[ resmgr_ocs.c : 4949 ] RESMGR_OCS_RECAL_QUOTAS num_home_chans = %d tracking_interval = %d +3656,ii,[ resmgr_ocs.c : 4996 ] RESMGR_OCS_RECAL_QUOTAS chan_mhz = %d latency = %d +3655,iii,[ resmgr_ocs.c : 5003 ] RESMGR_OCS_ALLOCATED_QUOTA_STATS chan_mhz = %d req_chan_time_percentage = %d chan_time_quota = %d +3654,i,[ resmgr_ocs.c : 3030 ] RESMGR_OCS_RECOMPUTE_SCHEDULE: ocs_ins = %d +3653,i,[ resmgr_ocs.c : 3036 ] RESMGR_OCS %d has been paused +3652,,[ resmgr_ocs.c : 305 ] RESMGR_OCS_CURR_CAT_WINDOW +3651,I,[ resmgr_ocs.c : 341 ] RESMGR_OCS_CURR_CAT_WINDOW: Channel change pending, flags = 0x%x +3650,IIi,[ resmgr_ocs.c : 323 ] RESMGR_OCS_CURR_CAT_WINDOW_REQ req_id = 0x%x ch_req_addr = 0x%x state = %d +3649,II,[ resmgr_ocs.c : 326 ] RESMGR_OCS_CURR_CAT_WINDOW_TIMESLOT start_tsf = 0x%x stop_tsf = 0x%x +3648,Iii,[ resmgr_ocs.c : 2982 ] RESMGR_OCS_CUR_CH_ALLOC curr_chan_alloc_addr = 0x%x chan_mhz = %d sec_ch_mhz = %d +3647,Iii,[ resmgr_ocs.c : 2992 ] RESMGR_OCS_WINNING_CH_ALLOC curr_chan_alloc_addr = 0x%x chan_mhz = %d sec_ch_mhz = %d +3646,iII,[ resmgr_ocs.c : 3857 ] OCS_INVOKED: ins=%d last_entry=0x%x cur_time=0x%x +3645,i,[ resmgr_ocs.c : 4010 ] RESMGR_OCS_SCHED_CH_CHANGE: ocs_ins = %d +3644,I,[ resmgr_ocs.c : 4063 ] RESMGR_OCS_TSF_TIMEOUT_US next_tsftime = %x +3643,I,[ resmgr_ocs.c : 4075 ] RESMGR_OCS_NEXT_TSFTIME next_tsf_time = 0x%x +3642,iii,[ resmgr_ocs.c : 4106 ] RESMGR_OCS_TSF_TIMEOUT_US wake up latency = %d, wlan_chan_num = %d, wlan_cb_num = %d +3641,i,[ resmgr_ocs.c : 4119 ] TSF_TIMEOUT_US timeout_us=%d +3640,iII,[ resmgr_ocs.c : 4192 ] RESMGR_OCS_INVOKED: ocs_ins = %d ocs_entry_time = 0x%x ocs_exit_time = 0x%x +3639,III,[ resmgr_ocs.c : 3861 ] RESMGR_OCS_INVOKED: Cur_Ch_Alloc = 0x%x Flags = 0x%x Resched_Req = 0x%x +3638,I,[ resmgr_ocs.c : 3994 ] RESMGR_OCS_TSF_TIMEOUT_US defer_sch_time = %x +3699,I,[ resmgr_vcm_init.c : 76 ] VCM_Init: VC Pool Size = 0x%x +3703,,[ resmgr_vcm.c : 56 ] RESMGR_CREATE_LINK failed due to invalid channel param +3702,IIiiii,[ resmgr_vcm.c : 163 ] RESMGR_LINK_CREATE link_pointer = 0x%x link_flags = 0x%x ch_mhz = %d phy_mode = %d band_center_freq1 = %d band_center_freq2 = %d +3701,I,[ resmgr_vcm.c : 176 ] RESMGR_LINK_DELETE Link Pointer = 0x%x +3700,,[ resmgr_vcm.c : 300 ] RESMGR_UPDATE_LINK failed due to invalid channel param +3716,iII,[ virtual_channel.c : 411 ] RESMGR_VC_UPDATE_HOME_CHAN_INFO: mac_id = %d virtual_chan_count = 0x%x home_chan_count = 0x%x +3715,iiIIiiII,[ virtual_channel.c : 499 ] RESMGR_ADD_LINK ch_mhz = %d phy_mode = %d link_flags = 0x%x link_valid_attr = 0x%x no_160_link_cnt = %d 160_link_cnt = %d vc = 0x%x link = 0x%x +3714,i,[ virtual_channel.c : 455 ] RESMGR_VC_INIT_ROAM_CHAN: chan_mhz = %d +3713,iIIIIi,[ virtual_channel.c : 290 ] RESMGR_VC_INIT_VIR_CHAN: chan_mhz = %d, mac_id = 0x%x, band = 0x%x, tx_chm = 0x%x, rx_chm = 0x%x, rx_nss = %d +3712,IIIIIII,[ virtual_channel.c : 300 ] RESMGR_VC_INIT_VIR_CHAN: nss1_tx_chm = 0x%x, nss2_tx_chm = 0x%x, selfgen_chm = 0x%x, nss_tx_11b_chainmask = 0x%x, selfgen_11b_chainmask = 0x%x, nss_tx_ofdm_chainmask = 0x%x, selfgen_ofdm_chainmask = 0x%x +3711,i,[ virtual_channel.c : 328 ] RESMGR_VC_INIT_HOME_CHAN: chan_mhz = %d +3710,iI,[ virtual_channel.c : 638 ] RESMGR_OCS_REQ_QUOTA_STATS chan_mhz = %d req_chan_time/latency = 0x%x +3709,II,[ virtual_channel.c : 644 ] RESMGR_OCS_REQ_QUOTA_STATS arg = 0x%x req_chan_time/latency = 0x%x +3708,iiiiII,[ virtual_channel.c : 820 ] RESMGR_VC_REGISTER_LINK: chan_mhz = %d link_count = %d ephemeral_link_count = %d is_home_chan = %d link_flags = 0x%x link_valid_attr = 0x%x +3707,iiIIii,[ virtual_channel.c : 536 ] RESMGR_RMV_LINK ch_mhz = %d phy_mode = %d link_flags = 0x%x link_valid_attr = 0x%x no_160_link_cnt = %d 160_link_cnt = %d +3706,III,[ virtual_channel.c : 998 ] !cts2s_sent: 0x%x 0x%x 0x%x +3705,iiii,[ virtual_channel.c : 842 ] RESMGR_VC_UNREGISTER_LINK: chan_mhz = %d link_count = %d ephemeral_link_count = %d is_home_chan = %d +3704,i,[ virtual_channel.c : 699 ] RESMGR_VC_UPDATE_CUR_VC chan_mhz = %d +3724,iii,[ virtual_channel_arbiter.c : 1252 ] wlan_virtual_chan_apply_chan_num rx = %d tx = %d org = %d +3723,IiiIii,[ virtual_channel_arbiter.c : 843 ] RESMGR_VC_ARBITRATE_CHAN_PARAM arbit_chan = 0x%x arbit_chan_mhz=%d arbit_chan_phy_mode=%d link_chan=0x%x link_chan_mhz=%d link_chan->phy_mode=%d +3722,iii,[ virtual_channel_arbiter.c : 1450 ] RESMGR_VC_ARBITRATE_ATTRIBUTES link_count = %d chain_number = %d per_link_chain_num = %d +3721,ii,[ virtual_channel_arbiter.c : 1543 ] RESMGR_VC_ARBITRATE_ATTRIBUTES chan_mhz = %d phy_mode/vc_prog_latency = %d +3720,iiii,[ virtual_channel_arbiter.c : 1564 ] RESMGR_VC_ARBITRATE_ATTRIBUTES chan_mhz = %d current_chan_mhz = %d per link tx_chainmask = %d, rx_chainmask = %d +3719,iII,[ virtual_channel_arbiter.c : 1472 ] RESMGR_VC_ARBITRATE_ATTRIBUTES num = %d, tx_mask = %x rx_mask = %x +3718,iiiII,[ virtual_channel_arbiter.c : 1516 ] RESMGR_VC_ARBITRATE_ATTRIBUTES chan_mhz = %d phy_mode/vc_prog_latency = %d band_center_freq = %d virtual_chan_ctxt = 0x%x virtual_chan = 0x%x +3717,iii,[ virtual_channel_arbiter.c : 1615 ] VC_ARB_SMPS: mhz = %d, smps_supp = %d, dyn_smps = %d +3725,iiIi,[ resmgr_chainmask_mgr.c : 3147 ] RESMGR_CHMMGR_GET_MAX_BANDWIDTH: band = %d, mac = %d, max_bw_supported = 0x%x, hw_mode = %d +3731,II,[ resmgr_concurrency_mgr.c : 162 ] RESMGR_CONCURRENCY_DEREG_EVT_HDLR: handler = 0x%x arg = 0x%x deregistered +3730,IIIi,[ resmgr_concurrency_mgr.c : 272 ] _resmgr_concurrency_mgr_is_low_freq_vdev_chreq_apply: active_sta_vdev_num = 0x%x, active_vdev_num = 0x%x, resmgr_nan_discovery_enable = 0x%x, result = %d +3729,I,[ resmgr_concurrency_mgr.c : 351 ] resmgr_concurrency_mgr_notify: module = 0x%x +3728,II,[ resmgr_concurrency_mgr.c : 106 ] RESMGR_CONCURRENCY_REG_EVT_HDLR: handler = 0x%x arg = 0x%x exists!!! +3727,II,[ resmgr_concurrency_mgr.c : 114 ] RESMGR_CONCURRENCY_REG_EVT_HDLR: handler = 0x%x arg = 0x%x no memory!!! +3726,II,[ resmgr_concurrency_mgr.c : 124 ] RESMGR_CONCURRENCY_REG_EVT_HDLR: handler = 0x%x arg = 0x%x registered +3743,I,[ wlan_scan_wmi.c : 192 ] SCAN_SCH_WMI_START_SCAN vdev_id = 0x%x is FREE +3742,IIIIII,[ wlan_scan_wmi.c : 277 ] SCAN_SCH_WMI_START_SCAN bssid = %02x:%02x:%02x:%02x:%02x:%02x +3741,Iiiiii,[ wlan_scan_wmi.c : 326 ] SCAN_SCH_WMI_START_SCAN s_ssid_bssid_cache = 0x%x num_hint_freq_short_ssid_list = %d num_hint_freq_bssid_list = %d dtime_act = %d dtime_pas = %d min_dtime = %d +3740,iiiii,[ wlan_scan_wmi.c : 378 ] CheckNOL status = %d, p_cmd->num_chan = %d, numOfChans = %d, scan_id = %d, req_id = %d +3739,iI,[ wlan_scan_wmi.c : 409 ] SCAN_START_COMMAND_FAILED err_ret_code = %d(1:normal 2:NOL) status = 0x%x +3738,IIIIIIII,[ wlan_scan_wmi.c : 242 ] SCAN_SCH_WMI_START_SCAN 6ghz_ch 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x +3737,iiiiii,[ wlan_scan_wmi.c : 270 ] SCAN_SCH_WMI_START_SCAN num_ssid from %d to %d, num_bssid from %d to %d, num_chan = %d ie_len = %d +3736,I,[ wlan_scan_wmi.c : 434 ] SCAN_SCH_STOP_COMMAND_FAILED status = 0x%x +3735,I,[ wlan_scan_wmi.c : 73 ] %s: Invalid params +3734,I,[ wlan_scan_wmi.c : 50 ] %s: Invalid params +3733,ii,[ wlan_scan_wmi.c : 479 ] SCAN_SET_CHANLIST_FAILED support_chan %d num_scan_chans %d +3732,iiiIIii,[ wlan_scan_wmi.c : 585 ] SCAN_SET_CHAN_LIST idx = %d, mhz = %d, is_passive = %d ch_info = 0x%x reg_info_1 = 0x%x max_bd = %d is_nan_disabled = %d +3767,I,[ wlan_scan_sch.c : 2135 ] SCAN_SCH_CSA_FAILED status = 0x%x +3766,III,[ wlan_scan_sch.c : 2400 ] SCAN_SCH_RESUME requestor_id = 0x%x suspend_bitmap_63_32 = 0x%x, suspend_bitmap_31_0 = 0x%x +3765,iIIi,[ wlan_scan_sch.c : 104 ] SCAN_SCH_SUPPRESS_REQ req_mod_id=%d sch_class = 0x%x id = 0x%x is_disable_scan = %d +3764,III,[ wlan_scan_sch.c : 2374 ] SCAN_SCH_SUSPEND requestor_id = 0x%x suspend_bitmap_63_32 = 0x%x, suspend_bitmap_31_0 = 0x%x +3763,IIiiIIii,[ wlan_scan_sch.c : 1333 ] SCAN_INTERN_EVT evt_type=%x(1:start 2:compl 4:bss 8:frn_ch 10:deq 20:preempt 40:start_fail 80:restart 100:frn_ch_exit 200:susp 400:resume) scan_id=0x%x vdev_id=%d freq=%d req_sub_id=0x%x to_host(8b)|reason(8b)=0x%x abs_pri=%d dwell=%d +3762,Iiiii,[ wlan_scan_sch.c : 1387 ] SCAN_INTERN_EVT (FOREIGN_CHANNEL) scan_id = 0x%x ch_freq = %d bss_ch_freq = %d passive/active = %d dwell_time = %d +3761,IIi,[ wlan_scan_sch.c : 1400 ] SCAN_INTERN_EVT (PREEMPTED) scan_id = 0x%x preempted_by (scan_id) = 0x%x reason = %d +3760,II,[ wlan_scan_sch.c : 576 ] SCAN_SCH_SUSPENDED suspend_bitmap_63_32 = 0x%x, suspend_bitmap_31_0 = 0x%x +3759,i,[ wlan_scan_sch.c : 603 ] SCAN_SCH_START_NEW_REQ_FAILED error_code=%d +3758,,[ wlan_scan_sch.c : 606 ] SCAN_DETERM_HIGH_PRI cur scan not completed +3757,iI,[ wlan_scan_sch.c : 1060 ] SCAN_SCH_START_PARAM_INVALID scan_id=0x%d param=0x%x +3756,IIIiiiii,[ wlan_scan_sch.c : 1131 ] SCAN_SCH_START scan_id = 0x%x requestor_id = 0x%x req_sub_id = 0x%x requested_priority = %d absolute_priority = %d actv_time_5g = %d actv_time_2g = %d pass_time = %d +3755,iiIii,[ wlan_scan_sch.c : 1161 ] SCAN_SCH_START_INFO monitoring_interval = %d ie_len = %d ie_chunk_bitmap = 0x%x opmode = %d subopmode = %d +3754,iiIIii,[ wlan_scan_sch.c : 1178 ] SCAN_SCH_START_FAIL err_code = %d(1:misc 2:vdev_invalid 3:no_mem_new_req 4:chunk_copy_fail) scan_id = 0x%d requestor_id = 0x%x req_sub_id = 0x%x requested_priority = %d ie_len = %d +3753,I,[ wlan_scan_sch.c : 1760 ] SCAN_EVENT_SEND_FAILED 0x%x +3752,IiiIi,[ wlan_scan_sch.c : 1490 ] SCAN_EVENT_SEND_FAILED scan_id = 0x%x vdev_id = %d ch_freq = %d req_sub_id = 0x%x reason = %d +3751,IIii,[ wlan_scan_sch.c : 235 ] SCAN_SCH_CANCEL scan_id = 0x%x requestor_id = 0x%x vdev_id = %d req_type = %d +3750,,[ wlan_scan_sch.c : 287 ] SCAN_SCH_CANCEL already in progress +3749,,[ wlan_scan_sch.c : 293 ] SCAN_SCH_CANCEL no match found +3748,II,[ wlan_scan_sch.c : 502 ] SCAN_SCH_SUSPEND_NEXT_SCAN suspend_bitmap_63_32 = 0x%x, suspend_bitmap_31_0 = 0x%x +3747,IIIIIII,[ wlan_scan_sch.c : 535 ] SCAN_SCH_SUPPRESS_MATCH scan_id = 0x%x, requestor = 0x%x, vdev_id = 0x%x, suppress_vdev_id_bitmap = 0x%x suppress_mod_bitmap[0:2] 0x%x 0x%x 0x%x +3746,II,[ wlan_scan_sch.c : 1224 ] SCAN_SCH_ENGINE_STOP_DUE_TO_TIMEOUT evt_scan_id = 0x%x evt_reason = 0x%x +3745,i,[ wlan_scan_sch.c : 1607 ] SCAN_SCH_NEXT_SCAN_FAILED error_code=%d +3744,i,[ wlan_scan_sch.c : 1290 ] SCAN_EVENT_COMPLETED really cancelled scan_id %d +3782,iiiiiii,[ wlan_scan_eng.c : 945 ] SCAN_ENG_CALC_CHAN num_2g = %d num_5g_active = %d (num_5g_low_act_ch = %d) num_5g_passive = %d double_passive_chan_scan = %d num_6g_ch = %d num_extra_6g_ch = %d +3781,IIII,[ wlan_scan_eng.c : 973 ] SCAN_ENG_SPOOFED_MAC_ADDR full_mac_addr = %08x%04x partial_mac_addr = %08x%04x +3780,IIIIIiii,[ wlan_scan_eng.c : 376 ] SCAN_ENG_START scan_id = 0x%x eng_id(3)|req_type(3) = %06d num_chans_[req(3)|granted_2g(3)|granted_5g(3)] = %09d num_[ssid(3)|bssid(3)] = %06d flags = 0x%x vdev_freq = %d cur_ch_idx_2g|5g = %d %d +3779,iiiiii,[ wlan_scan_eng.c : 388 ] SCAN_ENG_PARAM_1 dwell_time_active = %d dwell_time_active_2g = %d msec dwell_time_passive = %d msec min_rest_time = %d msec max_rest_time = %d msec max_scan_time = %d msec +3778,iiiiiii,[ wlan_scan_eng.c : 399 ] SCAN_ENG_PARAM_2 idle_time = %d msec repeat_probe_time = %d msec probe_spacing_time = %d msec probe_delay = %d msec burst_duration = %d msec max_num_probes(2g|5g) = %d cancel_probe_req_defer = %d +3777,iiii,[ wlan_scan_eng.c : 1106 ] SCAN_ADJUST_PARAM active=%d active_2g=%d passive=%d rest=%d +3776,IIIIIii,[ wlan_scan_eng.c : 214 ] CHANNEL_CONGESTION_PRINTS cycle_cnt = %10u, busy = %10u, tx = %10u, rx = %10u, mr_rx = %10u, chan_freq= %d send_stats:%d +3775,iiiiiiii,[ wlan_scan_eng.c : 594 ] SCAN_ENG_CALC_CHAN num_6g_active = %d num_6g_passive = %d num_items_in_cache = %d scan_all_psc_chan = %d scan_all_non_psc_chan = %d match_hint = %d skip_non_rnr_chan = %d client_priority = %d +3774,iIIiii,[ wlan_scan_eng.c : 1312 ] SCAN_ENG_CANCEL scanhandler_id = %d scan_id = 0x%x requestor= 0x%x stop_mode = %d scan_in_progress = %d cancel_in_progress = %d +3773,iiiII,[ wlan_scan_eng.c : 89 ] AUTO_CHAN_EVT_HDNLR CURR_CHAN_STATS_ERROR error_code = %d (1:scan_handle NULL, 2:chan_freq 0) scan_id = %d evt_mac_id = %d type = 0x%x freq = 0x%x +3772,iIii,[ wlan_scan_eng.c : 1488 ] SCAN_BCN_RECVD mhz=%d at %08x is_scan_in_progress=%d (0 ignored) send_probe_req_on_DFS_ch=%d (1 ignored) +3771,ii,[ wlan_scan_eng.c : 1852 ] SCAN_SM_SKIP_NON_RNR_CH freq = %d chan_index = %d +3770,IIIi,[ wlan_scan_eng.c : 1145 ] SCAN_ENG_START_IN_PROGRESS = 1 scan_id = 0x%x requestor = 0x%x req_sub_id = 0x%x priority = %d -> return EBUSY +3769,I,[ wlan_scan_eng.c : 1267 ] SCAN_SM_START_COMMAND_FAILED cur_sch_scan_req = NULL handle = 0x%x +3768,iI,[ wlan_scan_eng.c : 318 ] SCAN_ENG_MAX_SCAN_TIMEOUT scanhandle_id = %d scan_id = 0x%x +3802,iii,[ wlan_scan_sm.c : 70 ] SCAN_SM_TRANSITIONS_MAC_%d %d => %d +3801,iii,[ wlan_scan_sm.c : 55 ] SCAN_SM_DISPATCH_MAC_%d %d < %d +3800,Iiii,[ wlan_scan_sm.c : 6366 ] SCAN_SM_OCS_TIMEOUT scan_id 0x%x, requestor = %d, curr_index = %d, curr_policy = %d +3799,IIIIiiii,[ wlan_scan_sm.c : 945 ] SCAN_SM_REQ_NEXT_CHAN scan_id=0x%x cur_policy(8)|hdl_id(8)=0x%x 2g_idx(16)|tot(16)=0x%x 5g_idx(8)|tot(E8_H8_L8)=0x%x dwell=%dms dur=%dus freq_pri=%d freq_sec=%d +3798,IiiiiiiIi,[ wlan_scan_sm.c : 4626 ] SCAN_SEND_PROBE_REQ scan_id = 0x%x mac_id = %d freq = %d cur_index = %d max_num_probe = %d probe_timer_count = %d chainmask = %d ppdu_info = 0x%x max_tx_power = %d +3797,Ii,[ wlan_scan_sm.c : 6427 ] SCAN_SM_CANCEL scan_stop = 0x%x scan_timeout = %d +3796,i,[ wlan_scan_sm.c : 3344 ] SCAN_SM_REQ_NEXT_CHAN !error! not implemented scan policy: %d +3795,ii,[ wlan_scan_sm.c : 4713 ] SCAN_SM_PROBE_REQ_FRAME_GEN_FAILED scanhandler_id = %d 6g_freq = %d +3794,iIiIIII,[ wlan_scan_sm.c : 4751 ] SEND_PROBE_ON_6GHZ_CH freq = %d short_ssid = 0x%x (cur_20TU_idx = %d add_flags_save = 0x%x add_flags = 0x%x chainmask = 0x%x ppdu_info = 0x%x) +3793,iIIiIIII,[ wlan_scan_sm.c : 4761 ] SEND_PROBE_ON_6GHZ_CH freq = %d bssid = %08x%04x (cur_20TU_idx = %d add_flags_save = 0x%x add_flags = 0x%x chainmask = 0x%x ppdu_info = 0x%x) +3792,i,[ wlan_scan_sm.c : 4841 ] SCAN_SEND_PROBE_REQ_6G_MGR err_ret = %d +3791,IIIiiiii,[ wlan_scan_sm.c : 5733 ] SCAN_SEND_PROBE_REQ_INFO scan_id = 0x%x band_2G_info = 0x%x band_5G_info = 0x%x probe_time = %d last_ssid_idx = %d last_bssid_idx = %d last_sent_probes = %d increase_probe_cnt:%d +3790,iI,[ wlan_scan_sm.c : 5739 ] SCAN_SEND_PROBE_REQ_RET err_ret = %d scan_id = 0x%x +3789,IiiI,[ wlan_scan_sm.c : 5383 ] SCAN_SEND_PROBE_REQ_2G_RET scan_id = 0x%x freq = %d cur_index = %d flags = 0x%02x +3788,IiiI,[ wlan_scan_sm.c : 5394 ] SCAN_SEND_PROBE_REQ_5G_RET scan_id = 0x%x freq = %d cur_index = %d flags = 0x%02x +3787,i,[ wlan_scan_sm.c : 5289 ] SCAN_SM_PROBE_REQ_FRAME_GEN_FAILED scanhandler_id = %d +3786,iii,[ wlan_scan_sm.c : 5167 ] SCAN_SM_PROBE_REQ_FRAME_GEN_FAILED scanhandler_id = %d 5g_freq = %d 2g_freq = %d +3785,iii,[ wlan_scan_sm.c : 4268 ] SCAN_SM_FOREIGN_CH actual_probe_delay = %d, scan_sch_handle->cancel_probe_req_defer = %d, params.cancel_probe_req_defer = %d +3784,iiii,[ wlan_scan_sm.c : 4182 ] SCAN_SM_LEGACY_MAC_CHANGE scanhandler_id = %d, last_legacy_macid = %d req_mac_id = %d, index = %d +3783,i,[ wlan_scan_sm.c : 6124 ] SCAN_SM_FOREIGN_CHAN_EVENT !error! not implemented scan policy: %d +3824,Iiiii,[ wlan_scan_mgr.c : 102 ] SCAN_MGR_STATE_CHANGE scan_id = 0x%x num_ssid = %d num_bssid = %d num_chan = %d new_scan_state = %d (0:completed 1:legacy 2:sync_DBS 3:async_DBS 4:agile 5:agile_DFS_2g 6:agile_DFS_5g) +3823,iiiii,[ wlan_scan_mgr.c : 1352 ] SCAN_MGR_BCN_RECV_WRONG_CH mac_id = %d freq = %d ch_freq = %d cur_freq = %d get_ch_freq_code = %d +3822,ii,[ wlan_scan_mgr.c : 1402 ] SCAN_MGR_BCN_RECV_FAIL err_code = %d(1:macid_invalid 2:cur_sch_scan_req_null) mac_id = %d +3821,,[ wlan_scan_mgr.c : 1569 ] SCAN_MGR_CH_MODE_CHANGE scan cancelled +3820,iiiii,[ wlan_scan_mgr.c : 1635 ] SCAN_MGR_CHECK_PARAMS_CHANNELS params->num_chan=%d params->chan_list[0]=%d has_2g_chan=%d has_5g_chan_active=%d has_5g_chan_passive=%d +3819,iii,[ wlan_scan_mgr.c : 1421 ] SCAN_MGR_DS_PARAM mac_id = %d, chan = %d len = %d +3818,iI,[ wlan_scan_mgr.c : 400 ] SCAN_MGR_EVENT_FAIL: Invalid input - scan_handler_id = %d, current_scan_sch_req = 0x%x +3817,Iiiii,[ wlan_scan_mgr.c : 496 ] SCAN_MGR_EVENT_COMPLETED scan_id = 0x%x num_ssid = %d num_bssid = %d num_chan = %d is_drop = %d +3816,IIIiiii,[ wlan_scan_mgr.c : 348 ] SCAN_MGR_EVENT_PREEMP_SUSP engid_policy_susp_preempt = 0x%08x 2g_idx(8)|tot(8)|5g_idx(8) = 0x%x 5g_E8_H8_L8_LA8 = 0x%x cancel_pending_bitmask = %d comp_pending_bitmask = %d comp_pending_5g_LB = %d comp_pending_5g_LB_act_ch = %d +3815,i,[ wlan_scan_mgr.c : 377 ] SCAN_MGR_EVENT_PREEMPTED or SCAN_MGR_EVENT_SUSPENDED drop_event = %d +3814,IIiiiiiIi,[ wlan_scan_mgr.c : 365 ] SCAN_MGR_EVENT_PREEMPTED scan_id = 0x%x cur_chan_index = 0x%x mac_id = %d 2g_next_idx = %d 2g_curr = %d 5g_next_idx = %d 5g_curr = %d reason = 0x%x cur_scan_policy = %d +3813,IIIi,[ wlan_scan_mgr.c : 371 ] SCAN_MGR_EVENT_SUSPENDED scan_id = 0x%x cur_chan_index = 0x%x reason = 0x%x cur_scan_policy = %d +3812,Ii,[ wlan_scan_mgr.c : 1736 ] SCAN_MGR_SCAN_POLICY_RECOMPUTE_START suppress mode bitmap = 0x%x is_scan_start = %d +3811,iiii,[ wlan_scan_mgr.c : 1790 ] SCAN_MGR_SCAN_POLICY_RECOMPUTE invalid chan index vdev_index=%d has_2g_chan=%d passive_5g=%d has_5g_chan_active=%d +3810,iiiiiiI,[ wlan_scan_mgr.c : 1845 ] SCAN_MGR_SCAN_POLICY_RECOMPUTE_END vdev_index = %d, chan_index = %d, policy_sel = %d, new_scan_policy = %d, cur_scan_policy = %d, scan_policy_max = %d, suppress mode bitmap = 0x%x +3809,IIii,[ wlan_scan_mgr.c : 1096 ] SCAN_MGR_CANCEL scan_id = 0x%x requstor = 0x%x stop_mode = %d scan_eng_start_pending = %d +3808,II,[ wlan_scan_mgr.c : 1203 ] SCAN_MGR_CANCEL comp_pending=0x%x cancel_pending=0x%x +3807,IIII,[ wlan_scan_mgr.c : 540 ] SCAN_POLICY_EVENT current_allowed_policy = 0x%x new_allowed_policy = 0x%x current_scan_req = 0x%x suppress_mode_bitmap = 0x%x +3806,Ii,[ wlan_scan_mgr.c : 1061 ] SCAN_MGR_SCAN_START_NON_DBS scan_id = 0x%x cur_scan_policy = %d +3805,i,[ wlan_scan_mgr.c : 1263 ] SCAN_SCH_NEXT_SCAN_FAILED after setting new channel lists, error_code=%d +3804,iiiiiiii,[ wlan_scan_mgr.c : 690 ] SCAN_MGR_RESUME_EVENT 2g cur_chan = %d, 2g next_chan = %d, 5g cur_chan = %d, 5g next_chan = %d, band_5g_low(high)_num_chan_indices = %d(%d), band_5g_low(high)_num_chan_indices = %d(%d) +3803,iiii,[ wlan_scan_mgr.c : 569 ] SCAN_MGR_PDEV_SUSPEND_RESUME_CHANGE_EVT pdev_id = %d requestor = %d reason %d state = %d +3836,I,[ wlan_dcs.c : 556 ] WLAN_DCS_DBGID_TIMER 0x%x +3835,I,[ wlan_dcs.c : 754 ] Init = 0x%x +3834,I,[ wlan_dcs.c : 56 ] WMI_EVENT_ALLOC_FAILURE EventId = 0x%x +3833,iiiII,[ wlan_dcs.c : 88 ] AWGN_INT_DBG ATH_CAP_DCS_AGWNIM sent chan_freq = %d center_freq0 = %d center_freq1 = %d channel_width = 0x%x bitmap = 0x%x + +3832,I,[ wlan_dcs.c : 163 ] WMI_EVENT_ALLOC_FAILURE EventId = 0x%x +3831,I,[ wlan_dcs.c : 193 ] WLAN_DCS_DBGID_WMI_CWINT 0x%x +3830,I,[ wlan_dcs.c : 252 ] WMI_EVENT_ALLOC_FAILURE EventId = 0x%x +3829,I,[ wlan_dcs.c : 280 ] WLAN_DCS_DBGID_WMI_WLAN_INT 0x%x +3828,I,[ wlan_dcs.c : 537 ] WLAN_DCS_DBGID_TIMER 0x%x +3827,iiiii,[ wlan_dcs.c : 125 ] AWGN_INT_DBG unit_test command invoked num_args = %d vdev_id = %d e_mac_id = %d pmac_id = %d g_chan_bw_interference_bitmap = %d + +3826,ii,[ wlan_dcs.c : 131 ] AWGN_INT_DBG unit_test wrong param num_args = %d args[0] = %d + +3825,iIii,[ wlan_dcs.c : 101 ] AWGN_INT_DBG pdev_id = %d seg = 0x%x bw_drop = %d pkt_drop = %d + +3837,i,[ wlan_scan_unit_test.c : 64 ] SCAN_NUM_SUPP_CHAN_LIST %d +3841,i,[ wlan_scan_6g_discv.c : 762 ] SCAN_FILSD_HANDLER_ERROR err_code = %d +3840,iiI,[ wlan_scan_6g_discv.c : 801 ] SCAN_FILSD_PARSER_ERROR rx_freq = %d len = %d ret = 0x%x +3839,IiiIII,[ wlan_scan_6g_discv.c : 162 ] SCAN_RNR_CACHE_TBL_ACT act_target_reason_attrib = 0x%08x num_items_in_cache = %d freq = %d s_ssid = 0x%08x bssid = %08x%04x +3838,i,[ wlan_scan_6g_discv.c : 402 ] SCAN_RNR_HANDLER ret_code = %d +3866,,[ wlan_stats.c : 2173 ] PS_STA_AVG_CHANNEL_CONGESTION(ERROR0):total_awake_period == 0 +3865,II,[ wlan_stats.c : 2192 ] PS_STA_AVG_CHANNEL_CONGESTION(ERROR1):diff_all(%u) < diff_tx(%u) +3864,I,[ wlan_stats.c : 2210 ] PS_STA_AVG_CHANNEL_CONGESTION(ERROR2): chan_activity(%u) > 100 +3863,IIIIIII,[ wlan_stats.c : 2233 ] PS_STA_AVG_CHANNEL_CONGESTION: vdev_id=%u, running_avg=%u, chan_activity=%u, total_period=%u, busy_activity=%u, diff_all=%u, diff_tx=%u +3862,,[ wlan_stats.c : 1988 ] chan_init POOL ALLOC FAILURE +3861,iii,[ wlan_stats.c : 543 ] wlan_stats_processor:vdev_id:%d ch%d_snr:%d +3860,,[ wlan_stats.c : 4585 ] _wlan_iface_link_stats_process: vdev is NULL +3859,iii,[ wlan_stats.c : 4695 ] total_num_peers:%d num_peer_stats_events:%d num_peer_in_event: %d +3858,,[ wlan_stats.c : 4528 ] radio_link_stats_process no buffer +3857,ii,[ wlan_stats.c : 4555 ] radio_link_stats_process cur_pwr_state:%d next_pwr_state:%d +3856,,[ wlan_stats.c : 5402 ] BIGDATA ERR: mem alloc failed +3855,iiiiiii,[ wlan_stats.c : 5443 ] BIGDATA STATS: vdev_id=%d tsf_out_of_sync=%d ani=%d data_tx_pwr=%d tx_pwr[dss,ofdm]=%d,%d kbps=%d +3854,ii,[ wlan_stats.c : 438 ] PS_STA_AVG_CHANNEL_CONGESTION BusyChanRunningAvg = %d %d +3853,I,[ wlan_stats.c : 1029 ] vdev_id=%u is NULL +3852,ii,[ wlan_stats.c : 1237 ] wlan_stats_processor:vdev_id:%d mac_snr:%d +3851,ii,[ wlan_stats.c : 1264 ] wlan_stats_processor:vdev_id:%d invalid_snr:%d +3850,ii,[ wlan_stats.c : 1278 ] wlan_stats_processor:vdev_id:%d bcn_snr:%d +3849,iii,[ wlan_stats.c : 1419 ] wlan_stats_processor: peer_stats->peer_tx_rate = %d rx_rate = %d rssi = %d +3848,IIII,[ wlan_stats.c : 1665 ] wlan_stats_processor: bcn_protect stats igtk_mic_fail_cnt = %x igtk_replay_cnt = %x bcn_mic_fail_cnt = %x bcn_replay_cnt = %x +3847,,[ wlan_stats.c : 1769 ] wlan_stats_processor: Ran out of buffers; Aborting Report generation; Sending Report to Host +3846,iI,[ wlan_stats.c : 1033 ] vdev free=%d, pmf_vdev_ctxt=%u +3845,,[ wlan_stats.c : 1119 ] Event not getting allocated evh = NULL +3844,,[ wlan_stats.c : 5229 ] _wlan_wlm_stats_process: vdev is NULL +3843,,[ wlan_stats.c : 5237 ] _wlan_wlm_stats_process: wal_vdev is NULL +3842,i,[ wlan_stats.c : 5242 ] _wlan_wlm_stats_process: cmd->vdev_id:%d is not up or sta +3872,I,[ wlan_wmi_ctrl_path_stats.c : 482 ] cp_stats print stats for pdev_id =0x%X +3871,I,[ wlan_wmi_ctrl_path_stats.c : 128 ] cp_stats event_send_complete & released buffer= 0x%X +3870,IIi,[ wlan_wmi_ctrl_path_stats.c : 982 ] cp_stats Reeived cp stats_req with stats_id_mask =0x%X action =0x%X req_id %d +3869,,[ wlan_wmi_ctrl_path_stats.c : 161 ] cp_stats calling send event +3868,II,[ wlan_wmi_ctrl_path_stats.c : 191 ] cp_stats send wmi event with more data = 0x%X event_status = 0x%X +3867,I,[ wlan_wmi_ctrl_path_stats.c : 959 ] cp_stats call send event with more data = 0x%X +3891,iIIiiII,[ wlan_rssi_monitor.c : 264 ] RSSI_MONITOR_ARBITER: vdevid=%d, client=%u, rssi_threshold_type=%u, low_rssi_threshold=%d, high_rssi_threshold=%d, configure_low_rssi_thresh=%u, configure_high_rssi_thresh=%u +3890,iIiIiIii,[ wlan_rssi_monitor.c : 325 ] RSSI_MONITOR_ARBITER_CONFIG_HW: vdevid=%d, configure_low_rssi_thresh=%u, final_low_rssi_thresh=%d, configure_high_rssi_thresh=%u, final_high_rssi_thresh=%d, rssi_weight=%u low client:%d high client:%d +3889,ii,[ wlan_rssi_monitor.c : 176 ] RSSI_MONITOR_CHECK_AND_DELIVER_EVENT: vdevid=%d, current_rssi=%d +3888,iIII,[ wlan_rssi_monitor.c : 158 ] RSSI_MONITOR_DELIVER_EVENT: vdevid=%d, client=%u, evt_type=%u, cb_fn=%#x +3887,iII,[ wlan_rssi_monitor.c : 433 ] RSSI_MONITOR_DISABLE_THRESHOLDS_CLIENT_REQ: vdevid=%d, client=%u, rssi_threshold_type=%u +3886,iI,[ wlan_rssi_monitor.c : 438 ] RSSI_MONITOR_DISABLE_THRESHOLDS_CLIENT_REQ_ERR(!vdev_rssi_monitor): vdevid=%d, client=%u +3885,iIIii,[ wlan_rssi_monitor.c : 357 ] RSSI_MONITOR_ENABLE_THRESHOLDS_CLIENT_REQ: vdevid=%d, client=%u, rssi_threshold_type=%u, low_rssi_threshold=%d, high_rssi_threshold=%d +3884,iI,[ wlan_rssi_monitor.c : 362 ] RSSI_MONITOR_ENABLE_THRESHOLDS_CLIENT_REQ_ERR(!vdev_rssi_monitor): vdevid=%d, client=%u +3883,iI,[ wlan_rssi_monitor.c : 405 ] RSSI_MONITOR_ENABLE_THRESHOLDS_CLIENT_REQ_ERR(!client_data): vdevid=%d, client=%u +3882,iii,[ wlan_rssi_monitor.c : 52 ] RSSI_MONITOR_GET_BEACON_RSSI_AVG: vdevid=%d, rssi_avg=%d, mac_id=%d +3881,iI,[ wlan_rssi_monitor.c : 475 ] RSSI_MONITOR_HW_EVENT: vdevid=%d, event_type=%x +3880,i,[ wlan_rssi_monitor.c : 489 ] RSSI_MONITOR_HW_EVENT(!low_rssi_threshold_configured): vdevid=%d +3879,i,[ wlan_rssi_monitor.c : 506 ] RSSI_MONITOR_HW_EVENT(!high_rssi_threshold_configured): vdevid=%d +3878,iIIiii,[ wlan_rssi_monitor.c : 119 ] RSSI_MONITOR_UPDATE_BEACON_RSSI: vdevid=%d, mac_id=%u, rssi_last=%u, rssi_avg_last=%d rssi_new=%d rssi_avg_new=%d +3877,iIIiii,[ wlan_rssi_monitor.c : 123 ] RSSI_MONITOR_UPDATE_BEACON_RSSI: vdevid=%d, mac_id=%u, rssi_last=%u, rssi_avg_last=%d rssi_new=%d rssi_avg_new=%d +3876,iI,[ wlan_rssi_monitor.c : 530 ] RSSI_MONITOR_VDEV_EVENT: vdevid=%d, notif=%u +3875,i,[ wlan_rssi_monitor.c : 615 ] RSSI_MONITOR_VDEV_FREE: vdevid=%d +3874,i,[ wlan_rssi_monitor.c : 603 ] RSSI_MONITOR_VDEV_INIT: vdevid=%d +3873,ii,[ wlan_rssi_monitor.c : 142 ] wlan_set_avg_rssi old_val = %d, vdev_rssi_monitor->rssi_avg = %d +3899,iii,[ wlan_thermal_unit_test.c : 87 ] WLAN_THERMAL_TSENS_TEMP_1 temp_req = %d, sensor_id = %d, temp = %d +3898,iiiiiiii,[ wlan_thermal_unit_test.c : 97 ] WLAN_THERMAL_TSENS_TEMP_2 sensor[1-8] %d %d %d %d %d %d %d %d +3897,ii,[ wlan_thermal_unit_test.c : 451 ] wlan_thermal_unit_test %d %d +3896,ii,[ wlan_thermal_unit_test.c : 49 ] WLAN_THERMAL_TSENS_INVALID_CONFIG vdev_id = %d, num_args = %d +3895,iiiiii,[ wlan_thermal_unit_test.c : 53 ] WLAN_THERMAL_TSENS_RECONFIG num_args = %d, Temp1|2 degC = %d %d, kp|ki|kd = %d %d %d +3894,iiiii,[ wlan_thermal_unit_test.c : 381 ] tt enabled. pdev_id(%d) dc:%d, dc_per_event:%d, hwm:%d, throt_levels:%d +3893,i,[ wlan_thermal_unit_test.c : 396 ] tt disabled for pdev_id: (%d) +3892,iiii,[ wlan_thermal_unit_test.c : 440 ] level configured. level:%d, lwm:%d, hwm:%d, dcoff:%d +3993,,[ wlan_vdev.c : 529 ] vdev connecting client is registered in non wow mode +3992,I,[ wlan_vdev.c : 553 ] allow during connecting, subtype:%x +3991,iiI,[ wlan_vdev.c : 627 ] set_restore_mac_addr status = %d, freq = %d, evh = 0x%x +3990,ii,[ wlan_vdev.c : 7406 ] VDEV_MGR_STA_PS_EVENT: vdev_id=%d, event_type=%d +3989,ii,[ wlan_vdev.c : 1721 ] VDEV EVT:RT thread handle vdev_stop_down_del cmd:%d, vdev_id:%d +3988,iii,[ wlan_vdev.c : 1648 ] VDEV EVT:DATA offload thread handle vdev_stop_down_del msg cmd = %d, vdev_id = %d, vdev_mode = %d +3987,iii,[ wlan_vdev.c : 1544 ] VDEV EVT:RT thread handle vdev_stop_down_del msg cmd = %d, vdev_id = %d, vdev_mode = %d +3986,i,[ wlan_vdev.c : 12056 ] wmi vdev send event %d +3985,II,[ wlan_vdev.c : 7985 ] VDEV_STOP_ABORT_TX try_to_abort, hwq=0x%x, swq=0x%x +3984,II,[ wlan_vdev.c : 7992 ] VDEV_STOP_ABORT_TX abort_fails, hwq=0x%x, swq=0x%x +3983,II,[ wlan_vdev.c : 7996 ] VDEV_STOP_ABORT_TX abort_succeeds, hwq=0x%x, swq=0x%x +3982,II,[ wlan_vdev.c : 8003 ] VDEV_STOP_ABORT_TX after_abort, hwq=0x%x, swq=0x%x +3981,iii,[ wlan_vdev.c : 8023 ] VDEV_STOP_EVT VDEV ID = %d HW Q depth= %d, SW Q depth = %d +3980,ii,[ wlan_vdev.c : 8119 ] WMI_CMD_PARAMS VdevId/AC/Arg1 = %d Cmd/Med-Time/Action/Arg2 = %d +3979,iii,[ wlan_vdev.c : 1168 ] VDEV EVT: vdev create id=%d, mode=%d submode=%d +3978,ii,[ wlan_vdev.c : 2160 ] VDEV EVT: vdev delete id=%d, mode=%d +3977,i,[ wlan_vdev.c : 1763 ] wlan_beacon_tx: vdev id = %d vdev delete return becasue bcn ctxt is not free yet +3976,iii,[ wlan_vdev.c : 1837 ] VDEV EVT: WMI_VDEV_DELETE_RESP_EVENTID vdevId=%d vdev_type: %d vdev_subtype: %d +3975,iiIIi,[ wlan_vdev.c : 1794 ] VDEV EVT peer not cleared idx=%d vdev_id = %d mac_addr31to0 = 0x%x mac_addr47to32 = 0x%x usage_count = %d +3974,,[ wlan_vdev.c : 10368 ] Failed to allocate memory for DISA event!!! +3973,i,[ wlan_vdev.c : 10398 ] DISA event sent to HOST: frame_len=%d +3972,iiiii,[ wlan_vdev.c : 10902 ] Error: vdev id %d, aggregation type %d, ac %d, max num frames %d, enable_bitmap %d + +3971,iiiiii,[ wlan_vdev.c : 10909 ] vdev id %d, aggregation type %d, ac %d, max num frames %d, enable_bitmap %d rx_size %d + +3970,iiiiii,[ wlan_vdev.c : 10991 ] vdev id %d, ac %d, software retry type %d, software retry threshold %d, pdev->agg_retry_th %d, pdev->non_agg_retry_th %d +3969,i,[ wlan_vdev.c : 10420 ] WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID invalid vdev_id %d +3968,i,[ wlan_vdev.c : 10429 ] WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID invalid data_len %d +3967,i,[ wlan_vdev.c : 10449 ] VDEV_DISPATCH_DISA_FRAME_TX failed status=%d +3966,i,[ wlan_vdev.c : 9709 ] WMI_VDEV_GET_ARP_STAT_CMDID: vdev_id = %d event alloc failed +3965,,[ wlan_vdev.c : 9357 ] BIGDATA ERR: vdev NULL or FREE +3964,i,[ wlan_vdev.c : 9508 ] WMI_VDEV_GET_KEEPALIVE_CMDID: vdev_id = %d event alloc failed +3963,iiiii,[ wlan_vdev.c : 8723 ] 11w PMF vdevId=%d key_ix=%d cipher=%d is_group_key_valid %d group_key_ix %d +3962,,[ wlan_vdev.c : 8806 ] key cache POOL ALLOC FAILURE +3961,iIIi,[ wlan_vdev.c : 8844 ] VDEV_INSTALL_KEY_FAIL vdev_id %d mac_addr %04x:%08x status %d +3960,iIIi,[ wlan_vdev.c : 8892 ] VDEV_INSTALL_KEY_FAIL_MESH vdev_id %d mac_addr %04x:%08x status %d +3959,iI,[ wlan_vdev.c : 8930 ] WAL_DBGID_SET_M4_SENT_MANUALLY VDEV ID = %d, peer = 0x%x +3958,i,[ wlan_vdev.c : 10631 ] LIMIT_OFFCHAN_ERROR client_id=%d +3957,i,[ wlan_vdev.c : 10641 ] LIMIT_OFFCHAN_ERROR vdev_id=%d +3956,Iiii,[ wlan_vdev.c : 10294 ] dispatch_set_ie_cmd: ie_id = 0x%x, id_len = %d, source=%d, band=%d +3955,Iii,[ wlan_vdev.c : 10312 ] vdev_set_scan_default_ie status = 0x%x vdev_id=%d prunned_ie_len=%d +3954,iII,[ wlan_vdev.c : 9464 ] KA: cmd handler() -> start timer vdev_id = %d keepalive_interval = 0x%x keepalive_method = 0x%x +3953,i,[ wlan_vdev.c : 8551 ] Invalid VDEV in WMI_VDEV_SET_WMM_PARAMS_CMDID, VDEV ID = %d +3952,i,[ wlan_vdev.c : 8558 ] Invalid WAL VDEV in WMI_VDEV_SET_WMM_PARAMS_CMDID, VDEV ID = %d +3951,i,[ wlan_vdev.c : 8574 ] WMI_VDEV_SET_WMM_PARAMS_CMDID type=%d +3950,IIII,[ wlan_vdev.c : 8587 ] WMI_VDEV_SET_WMM_PARAMS_CMDID ac[31-16]/acm[15-0] = 0x%x cw_min = 0x%x cw_max = 0x%x txop_limit[31-16]/aifs[15-0] = 0x%x +3949,Iiii,[ wlan_vdev.c : 8326 ] Rejecting vdev_start Invalid Regdomain vdev_id= 0x%x, host_regdomain = %d regdomain = %d isDFSSTA=%d +3948,I,[ wlan_vdev.c : 8338 ] Rejecting vdev_start Roaming in progress vdev_id= 0x%x +3947,I,[ wlan_vdev.c : 8347 ] Rejecting vdev_start BSS Peer not created vdev_id= 0x%x +3946,I,[ wlan_vdev.c : 8355 ] Rejecting vdev_start Home channel not in supported band vdev_id= 0x%x +3945,III,[ wlan_vdev.c : 8376 ] Rejecting vdev_start request from requestor_id = 0x%x. start_delay_us = 0x%x, max_start_delay_us=0x%x +3944,iI,[ wlan_vdev.c : 8389 ] Rejecting vdev_start request for vdev_id = %d from requestor_id = 0x%x. STA + STA not supported +3943,i,[ wlan_vdev.c : 8453 ] STA-DFS flag SET in wmi_channel for vdev %d +3942,IIIIIii,[ wlan_vdev.c : 9238 ] WLAN_DISPATCH_VDEV_UP vdev_flags:0x%x vdev_bssid:%x_%x trans_bssid:%x_%x profile_idx:%d profile_num:%d +3941,,[ wlan_vdev.c : 9274 ] WLAN_DISPATCH_VDEV_UP !!!host sends wrong MBSSID param!!! +3940,iii,[ wlan_vdev.c : 9001 ] WMI_CMD_PARAMS AC = %d Med-Time usec = %d DwnGrd_Type = %d +3939,ii,[ wlan_vdev.c : 9774 ] dispatch_wmm_delts_cmd: ac = %d vdev id = %d +3938,,[ wlan_vdev.c : 9794 ] dispatch_wmm_delts_cmd: end +3937,ii,[ wlan_vdev.c : 5151 ] VDEV EVT: vdev down id=%d, mode=%d +3936,ii,[ wlan_vdev.c : 10251 ] vdev_extract_mandatory_ies: id=%d, len=%d +3935,Ii,[ wlan_vdev.c : 10165 ] vdev_extract_optional_vendor_ies: oui=0x%x, len=%d +3934,III,[ wlan_vdev.c : 7686 ] VDEV free error, peer addr:0x%x, mac:0x%x 0x%x +3933,iii,[ wlan_vdev.c : 11511 ] VDEV_SET_PARAM_TPC_POWER psd_power=%d, eirp_power=%d, num_pwr_levels=%d +3932,iiiii,[ wlan_vdev.c : 11480 ] wlan_vdev_handle_wfa_config_cmd override_rsnxe=%d, ignore_csa=%d, deauth_on_saquery_timeout=%d override_oci_chan frame_types=%d, override_oci_chan=%d +3931,iIii,[ wlan_vdev.c : 10592 ] LIMIT_OFFCHAN_ARBITER client=%d flag=0x%x max_offchan_time=%d rest_time=%d +3930,Iii,[ wlan_vdev.c : 10614 ] LIMIT_OFFCHAN_ARBITER_RESULT flag=0x%x max_offchan_time=%d rest_time=%d +3929,II,[ wlan_vdev.c : 2669 ] wlan_vdev_migrate vdev_id[31-16]/from_mac[15-8]/to_mac[7-0] 0x%x, is_up[24]/is_active[16]/mode[15-8]/submode[7-0] 0x%x +3928,,[ wlan_vdev.c : 8218 ] WMI_EVENT_ALLOC_FAILURE: VDEV_REJECT_VDEV_START_REQ_RESP_EVENTID buffer failure +3927,ii,[ wlan_vdev.c : 10008 ] vdev_set_mandatory_ie: ie_id=%d, id_len=%d +3926,i,[ wlan_vdev.c : 10116 ] vdev_set_mandatory_ie: not handled ie_id=%d +3925,iii,[ wlan_vdev.c : 9904 ] vdev_set_mandatory_ie_by_band: ie_id=%d, band=%d, id_len=%d +3924,iI,[ wlan_vdev.c : 12301 ] wlan_vdev_set_max_pause_delay_us vdev_id=%d max_pause_delay_us = 0x%x +3923,ii,[ wlan_vdev.c : 6074 ] WMI_CMD_PARAMS VdevId/AC/Arg1 = %d Cmd/Med-Time/Action/Arg2 = %d +3922,iII,[ wlan_vdev.c : 6079 ] vdev_id: %d vdev_set_param: id: 0x%x param_value: 0x%x +3921,iII,[ wlan_vdev.c : 6665 ] WLAN_VDEV_SET_PARAM_FAIL3 paramid:%d vdevp:0x%x vdevp->bss:0x%x +3920,iii,[ wlan_vdev.c : 6888 ] WMI_VDEV_PARAM_DISABLE_NOA_P2P_GO ic_mode:%d ic_subopmode:%d param:%d +3919,ii,[ wlan_vdev.c : 6909 ] WMI_VDEV_PARAM_SMPS_INTOLERANT: vdev_id:%d, param:%d +3918,I,[ wlan_vdev.c : 7153 ] Setting CABQ to %x +3917,,[ wlan_vdev.c : 7224 ] Err: WMI_VDEV_PARAM_NTH_BEACON_TO_HOST command came for non STA vdev +3916,IiiiiiI,[ wlan_vdev.c : 3710 ] VDEV_START: vdev_id[31-24]/mode[23-16]/mode[15-8]/mac_id[7-0] = 0x%x chan_mhz = %d phy_mode=%d band_center_freq1=%d band_center_freq2=%d ldpc_rx_enabled=%d vdev_flags:0x%x +3915,IiI,[ wlan_vdev.c : 3934 ] VDEV_MGR_HP_START_TIME vdev_id = 0x%x chan_mhz = %d start_tsf = 0x%x +3914,Ii,[ wlan_vdev.c : 659 ] resmgr link already exist: 0x%X vdev_id = %d +3913,iIIII,[ wlan_vdev.c : 9042 ] wlan_vdev_tsf_report: vdev_id = %d, tsf_low = 0x%x, tsf_high = 0x%x, qtimer_low=0x%x, qtimer_high=0x%x +3912,iI,[ wlan_vdev.c : 9063 ] wlan_vdev_tsf_tstamp_action:vdev_id = %d, action = 0x%x +3911,ii,[ wlan_vdev.c : 9071 ] wlan_vdev_tsf_tstamp_action: vdev_id = %d, vdev_ifUp = %d +3910,iI,[ wlan_vdev.c : 12080 ] wlan_vdev_unit_test: vdev_id = %d, cmd = WMI_VDEV_PARAM_ABG_MODE_TX_CHAIN_NUM, value = 0x%x +3909,iI,[ wlan_vdev.c : 12089 ] wlan_vdev_unit_test: vdev_id = %d, set_ctrl_path_sw_event_bitmap: value = 0x%x +3908,ii,[ wlan_vdev.c : 4633 ] VDEV_MGR_VDEV_UP id=%d, mode=%d +3907,III,[ wlan_vdev.c : 4684 ] WMI_VDEV_UP_CMDID soft_tx_chain_mask Disabled tx_chainmask_preferred_tx_stream = 0x%x stream = 0x%x vdev_id = 0x%x +3906,i,[ wlan_vdev.c : 4892 ] VDEV RESMGR_LINK_ATTR_SMPS_VALID Peer_flags:%d +3905,i,[ wlan_vdev.c : 4944 ] VDEV RESMGR_LINK_ATTR_SMPS_VALID VHT mode:%d +3904,iII,[ wlan_vdev.c : 5023 ] KA: wlan_vdev_up() -> start timer vdev_id = %d keepalive_interval = 0x%x keepalive_method = 0x%x +3903,i,[ wlan_vdev.c : 2982 ] wlan_vdevs_migrate, vdevs_migrate_duration = %d us +3902,iiii,[ wlan_vdev.c : 840 ] WMI NRP Config : addr1=%d, idx=%d, type=%d, action=%d +3901,iii,[ wlan_vdev.c : 7720 ] WAL Peer event vdevp %d is_free %d, is_vdev_stopping %d +3900,iii,[ wlan_vdev.c : 7728 ] WAL Peer event Vdev ID = %d HW Q depth= %d, SW Q depth = %d +4013,iii,[ wlan_vdev_misc.c : 1286 ] VDEV_MGR_MY_BEACON_PARSED malformed id = %d len=%d remain_len=%d +4012,iiI,[ wlan_vdev_misc.c : 1334 ] VDEV_MGR_MY_BEACON_BAD_IE id=%d,len=%d,status=0x%x +4011,IIIIII,[ wlan_vdev_misc.c : 1068 ] VENDOR SPECIFIC IE :%u, %u, %02x, %02x, %02x, %02x +4010,ii,[ wlan_vdev_misc.c : 3459 ] User configured fils discovery period (%d) is more than max supported value (%d). Capping fd period to max supported +4009,ii,[ wlan_vdev_misc.c : 3015 ] wlan_vdev_fill_vdev_mac_entry: vdev_id=%d, pdev_id=%d +4008,,[ wlan_vdev_misc.c : 3385 ] FD_TMPL_CMD: buf_len is greater than max len +4007,,[ wlan_vdev_misc.c : 3393 ] FD_TMPL_CMD: invalid vdev_id +4006,,[ wlan_vdev_misc.c : 3402 ] failed to allocate buffer for FD TMPL CMD +4005,,[ wlan_vdev_misc.c : 1028 ] 2xLTF not supported +4004,I,[ wlan_vdev_misc.c : 3165 ] wlan_vdev_get_migrate_active_vdev_list vdev_id_list=0x%x +4003,Ii,[ wlan_vdev_misc.c : 1898 ] Received IBSS Beacon peer = 0x%x send_to_host = %d +4002,iIIIiii,[ wlan_vdev_misc.c : 1616 ] VDEV_MGR_MY_BEACON_RECEIVED: vdev_id = %d curr_time = 0x%x curr_vdev_tsf = 0x%x seq = %u rssi = %d bss_ch = %d recv_ch = %d +4001,iii,[ wlan_vdev_misc.c : 1726 ] VDEV_MGR_HANDLE_OWN_BEACON fail freq:%d len:%d err_code:%d(1:NULL_wal_peer 2:ch_0 3:NULL_wlan_peer 4:short_len) +4000,i,[ wlan_vdev_misc.c : 3974 ] wlan_vdev_is_mcc_vdev_connect_in_progress result %d +3999,IIIIi,[ wlan_vdev_misc.c : 2245 ] OMI: Error peernss = 0x%lx OMI nss = 0x%lx bssBw= %1x OMI Bw= %1x peerMaxBw = %d + +3998,i,[ wlan_vdev_misc.c : 2454 ] wlan_vdev_reconfig: wlan_vdev vdev_id = %d is not up +3997,IIIII,[ wlan_vdev_misc.c : 1183 ] set_ignore_check_for_OUI :: VENDOR SPECIFIC IE :%u, %u, %02x, %02x, %02x +3996,IIII,[ wlan_vdev_misc.c : 1489 ] MU EDCA BEACON UPDATE FROM AP ac = 0x%x cw_min = 0x%x cw_max = 0x%x mu_edca_timer[31-16]/aifs[15-0] = 0x%x +3995,iiii,[ wlan_vdev_misc.c : 1509 ] MU EDCA BEACON: ignoring edca update qos_present=%d mu_edca_present=%d bcn_update_cnt=%d vdev_update_cnt=%d +3994,i,[ wlan_vdev_misc.c : 333 ] STA_KICKOUT: Reason=%d +4023,iIIII,[ wlan_vdev_keepalive.c : 805 ] KA: VDEV_MGR_AP_KEEPALIVE_INACTIVE vdev_id = %d cur_txrx_ref_time = 0x%x last_txrx_time = 0x%xlast_tx_time = 0x%x last_rx_time = 0x%x +4022,IIi,[ wlan_vdev_keepalive.c : 816 ] KA: wlan_vdev_keepalive_ready_to_send cur_txrx_ref_time = 0x%x last_txrx_time = 0x%x inactive_time_ms = %d +4021,iIII,[ wlan_vdev_keepalive.c : 397 ] VDEV_MGR_AP_KEEPALIVE_IDLE vdev_id = %d assoc_id = 0x%x inact_gen = 0x%x n_buffered_mpdu = 0x%x +4020,iiIIIIIi,[ wlan_vdev_keepalive.c : 472 ] VDEV_MGR_AP_KEEPALIVE KICKOUT: vdevid:%d, aid:%d, max_inactivity:0x%x last_txrx_activity:0x%x curr_time:0x%x, data_act:0x%x, mgmt_ctrl_act:0x%x, IdleOption:%d +4019,III,[ wlan_vdev_keepalive.c : 515 ] IBSS Keep Alive rx_last_activity = 0x%x ibss_max_bcn_lost_uses = 0x%x current time = 0x%x +4018,IIII,[ wlan_vdev_keepalive.c : 403 ] VDEV_MGR_AP_KEEPALIVE_INACTIVE vdev_id = 0x%x assoc_id = 0x%x inact_gen = 0x%x n_buffered_mpdu = 0x%x +4017,iIII,[ wlan_vdev_keepalive.c : 409 ] VDEV_MGR_AP_KEEPALIVE_UNRESPONSIVE vdev_id = %d assoc_id = 0x%x inact_gen = 0x%x n_buffered_mpdu = 0x%x +4016,i,[ wlan_vdev_keepalive.c : 909 ] VDEV_MGR_FIRST_BMISS_DETECTED: vdev_id = %d +4015,i,[ wlan_vdev_keepalive.c : 919 ] VDEV_MGR_FINAL_BMISS_DETECTED: vdev_id = %d +4014,i,[ wlan_vdev_keepalive.c : 956 ] VDEV_MGR_BCN_IN_SYNC: vdev_id = %d +4051,iIIII,[ wlan_vdev_schedule.c : 621 ] VDEV_MGR_AP_TBTT_CONFIG: vdev_id =%d, chan_mhz = 0x%x, tbtt_link_type = 0x%x, ni_intval = 0x%x, tbtt_offset = 0x%x +4050,iII,[ wlan_vdev_schedule.c : 693 ] Corr_sta_tbtt_drift: vdev_id = %d, chan_mhz = 0x%x, start_tsf = 0x%x +4049,iIIi,[ wlan_vdev_schedule.c : 3211 ] VDEV_MGR AP Connection protection critical channel request: vdev_id = %d, chan_mhz = 0x%x, start_tsf = 0x%x, duration = %d +4048,iIIi,[ wlan_vdev_schedule.c : 3146 ] VDEV_MGR SWBA protection critical channel request: vdev_id = %d, chan_mhz = 0x%x, start_tsf = 0x%x, duration = %d +4047,,[ wlan_vdev_schedule.c : 1804 ] vdev_bmiss_crit_ch_req_cb: ch_req granted +4046,,[ wlan_vdev_schedule.c : 1844 ] vdev_bmiss_crit_ch_req_cb: ch_req completed without receiving beacon +4045,i,[ wlan_vdev_schedule.c : 2515 ] VDEV_MGR_VDEV_START_OCS_HP_REQ_STOP: vdev_id = %d +4044,i,[ wlan_vdev_schedule.c : 2550 ] VDEV_MGR_FIRST_BCN_RECEIVED: vdev_id = %d +4043,i,[ wlan_vdev_schedule.c : 2555 ] VDEV_MGR_PEER_AUTHORIZED: vdev_id = %d +4042,i,[ wlan_vdev_schedule.c : 2573 ] VDEV_MGR_VDEV_START_OCS_HP_REQ_STOP: vdev_id = %d +4041,i,[ wlan_vdev_schedule.c : 2585 ] WLAN_VDEV_DPD_CAL_START vdev_id:%d +4040,iI,[ wlan_vdev_schedule.c : 2398 ] VDEV_MGR_VDEV_START_OCS_HP_REQ_COMPLETE without VDEV UP: vdev_id = %d, ch_req_flag = 0x%x +4039,i,[ wlan_vdev_schedule.c : 2437 ] VDEV_MGR_VDEV_START_OCS_HP_REQ_COMPLETE: vdev_id = %d +4038,ii,[ wlan_vdev_schedule.c : 2121 ] WLAN_VDEV_DPD_CAL_DONE vdev_id:%d ch:%d +4037,iiI,[ wlan_vdev_schedule.c : 2255 ] multi_vdev response: vdev_id=%d, num_multi_vdev_restart_compl=%d, multi_vdev_restart_bitmap=0x%x +4036,ii,[ wlan_vdev_schedule.c : 2070 ] WMI_EVENT_ALLOC_FAILURE: vdev_id = %d, opmode = %d, evt_id = WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID +4035,i,[ wlan_vdev_schedule.c : 2095 ] multi_vdev WMI_EVENT_SEND: pdev_id = %d, event = WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID +4034,ii,[ wlan_vdev_schedule.c : 1989 ] WMI_EVENT_ALLOC_FAILURE: vdev_id = %d, opmode = %d, evt_id = WMI_VDEV_START_RESP_EVENTID +4033,ii,[ wlan_vdev_schedule.c : 2044 ] WMI_EVENT_SEND: vdev_id = %d, opmode = %d, event = WMI_VDEV_START_RESP_EVENTID +4032,iII,[ wlan_vdev_schedule.c : 3484 ] wlan_vdev_sta_concurrency_event_handler: vdev_id = %d, next_state = 0x%x, cur_state = 0x%x +4031,Ii,[ wlan_vdev_schedule.c : 1969 ] SCAN_RADIO_SUPPORT_DBUG scan_radio_lpri_req setup lp_ch_req created = %p channel = %d + +4030,,[ wlan_vdev_schedule.c : 3078 ] VDEV_MGR_FIRST_BMISS_DETECTED: Post Critical ch_req +4029,iIIII,[ wlan_vdev_schedule.c : 1429 ] VDEV_MGR_AP_TBTT_CONFIG: vdev_id = %d, chan_mhz = 0x%x, tbtt_link_type = 0x%x, ni_intval = 0x%x, ap_tbtt_offset = 0x%x +4028,iI,[ wlan_vdev_schedule.c : 2861 ] VDEV_MGR_LOWPOWER_HP_CHREQ_ENABLED: vdev_id = %d, chan_mhz = 0x%x +4027,iII,[ wlan_vdev_schedule.c : 2944 ] VDEV_MGR_HP_START_TIME: vdev_id = %d, chan_mhz = 0x%x, start_tsf = 0x%x +4026,iI,[ wlan_vdev_schedule.c : 2979 ] VDEV_MGR_LOWPOWER_LP_CHREQ_ENABLED: vdev_id = %d, factor = 0x%x +4025,iI,[ wlan_vdev_schedule.c : 2985 ] VDEV_MGR_LOWPOWER_LP_CHREQ_ENABLED: vdev_id = %d, factor = 0x%x +4024,iII,[ wlan_vdev_schedule.c : 3003 ] VDEV_MGR_OCS_HP_LP_REQ_POSTED: vdev_id = %d, hp_ch_req = 0x%x, lp_ch_req = 0x%x +4065,iI,[ wlan_vdev_pause.c : 499 ] VDEV Unpause Failure: VDEV ID = %d pause_bitmap = 0x%x in Unpause complete +4064,ii,[ wlan_vdev_pause.c : 1365 ] Disable leaky AP CTS2S: vdev_id = %d pause_delay_us = %d +4063,I,[ wlan_vdev_pause.c : 1368 ] enable_null_leaky_ap_pause=0x%x +4062,I,[ wlan_vdev_pause.c : 609 ] vdev->bcn_tx_paused_wlan_vdev_pause_1=0x%x +4061,,[ wlan_vdev_pause.c : 628 ] VDEV_PAUSE_FAIL ifPaused set with pause_bitmap = 0 in _wlan_vdev_pause +4060,IiiiI,[ wlan_vdev_pause.c : 696 ] VDEV_MGR_VDEV_PAUSE: enable_null_leaky_ap_pause=0x%x no_null_to_ap_for_roaming=%d leakyAp_cts2s_enable=%d pause_delay_us=%d req from mod_id = %x +4059,iiiii,[ wlan_vdev_pause.c : 266 ] VDEV_MGR_VDEV_PAUSE_COMP: vdev_id = %d pause_status = LEAKY AP DETECTED data_null_tx_delay = %d actual_leak_window = %d pause_delay_us = %d consec_detect_leaky_ap_cnt = %d +4058,iiiii,[ wlan_vdev_pause.c : 401 ] VDEV_MGR_VDEV_PAUSE_DELAY_UPDATE: vdev_id = %d avg_data_null_tx_delay = %d avg_rx_leak_window = %d pause_delay_us = %d is_bt_connected = %d +4057,iiiii,[ wlan_vdev_pause.c : 321 ] VDEV_MGR_VDEV_PAUSE_COMP: vdev_id = %d pause_status = FAILURE data_null_tx_delay = %d avg_data_null_tx_delay = %d actual_leak_window = %d avg_rx_leak_window = %d +4056,iiiii,[ wlan_vdev_pause.c : 344 ] VDEV_MGR_VDEV_PAUSE_COMP: vdev_id = %d pause_status = SUCCESS data_null_tx_delay = %d avg_data_null_tx_delay = %d actual_leak_window = %d avg_rx_leak_window = %d +4055,i,[ wlan_vdev_pause.c : 1376 ] no_null_to_ap_for_roaming=%d +4054,I,[ wlan_vdev_pause.c : 926 ] VDEV_UNPAUSE_FAIL: ifPaused not set with pause_bitmap = 0x%x in _wlan_vdev_unpause +4053,,[ wlan_vdev_pause.c : 967 ] VDEV_MGR_VDEV_PAUSE unpause non_protocol_unpaused +4052,,[ wlan_vdev_pause.c : 1045 ] VDEV_MGR_VDEV_PAUSE csa_roaming_ongoing and no host unpause +4071,,[ wlan_vdev_unit_test.c : 91 ] wlan_vdev_config_test: vdev is NULL +4070,iiii,[ wlan_vdev_unit_test.c : 162 ] wlan_vdev_unit_test: vdev_id = %d, custom_sw_retry_th_cmd, ac %d sw_retry_type = %d sw_retry_th = %d +4069,,[ wlan_vdev_unit_test.c : 193 ] wlan_vdev_unit_test: disable QoS per peer per tid configuration +4068,I,[ wlan_vdev_unit_test.c : 238 ] wlan_vdev_unit_test: g_wmi_cmd_enable_pf_log = 0x%x +4067,iiiii,[ wlan_vdev_unit_test.c : 105 ] wlan_vdev_config_test: vdev_id = %d, test_cmd = %d, args[1] = %d, args[2] = %d, num_args = %d +4066,iii,[ wlan_vdev_unit_test.c : 140 ] wlan_vdev_unit_test: vdev_id = %d, custom_aggr_size_cmd, subfram %d ac = %d +4074,,[ wlan_coex_main.c : 243 ] WLAN_COEX_LEAKYAP: Enable NULL for Leaky Ap for scan + a2dp/ble scan! +4073,,[ wlan_coex_main.c : 275 ] WLAN_COEX_LEAKYAP: Disable NULL for Leaky AP Pause due to Scan Stop ! +4072,ii,[ wlan_coex_main.c : 319 ] WLAN_COEX_VDEV_EVENT: vdev_id(%d), mac_id(%d) +4084,I,[ wlan_coex_ps.c : 197 ] COEX_PSP_ERROR: COEX_PSP_ERROR_VDEV_NULL Stimulus(%u) +4083,iiIiI,[ wlan_coex_ps.c : 339 ] COEX_PSP_RX_STATUS_STATE_1: ExpTS(%d) ActTS(%d) IsOverRun(%u) RespOverUnderRunTime(%d) ApResponseRxDuration(%u) +4082,,[ wlan_coex_ps.c : 382 ] COEX_PSP_SEND_PSPOLL: 0 +4081,IIII,[ wlan_coex_ps.c : 408 ] COEX_PSP_NONWLAN_INTERVAL: BaseIntrvl(%u) NonWlanIdleTime(%u) PsPollSpecInterval(%u) ApResponseTimeout(%u) +4080,IIIIIII,[ wlan_coex_ps.c : 443 ] COEX_PSP_MGR: Error(0x%x) Stimulus (%u) State(0x%x), Avg(%u) EstimationOverun(%u) SpecCount(%u) MoreData(%u) +4079,II,[ wlan_coex_ps.c : 110 ] COEX_PSP_SEND_PSPOLL: State(0x%x) PSPNum(%u) +4078,IiIiI,[ wlan_coex_ps.c : 161 ] COEX_PSP_READY_STATE: T2NonWlan(%u) EndTS(%d) MoreData(%u) ExpTS(%d) NonWlanIdleTime(%u) +4077,,[ wlan_coex_ps.c : 164 ] COEX_PSP_SEND_PSPOLL: 0 +4076,IIIIII,[ wlan_coex_ps.c : 146 ] COEX_PSP_SPEC_POLL: En(%u) Count(%u) TS(%u) AllowSpecPsPollTx(%u) Delta(%u) Intrvl(%u) +4075,,[ wlan_coex_ps.c : 156 ] COEX_PSP_SEND_PSPOLL: 0 +4094,,[ wlan_coex_ocs.c : 898 ] COEX_GENERIC_ERROR: Defer the Disable NULL for Leaky AP Pause due to A2DP Stop during Scan to SCAN_COMPLETE ! +4093,,[ wlan_coex_ocs.c : 942 ] COEX_GENERIC_ERROR: Enable NULL for Leaky AP Pause due to A2DP Start during Scan ! +4092,IIIiIi,[ wlan_coex_ocs.c : 1005 ] WLAN_COEX_OCS_MGR: Stimulus(%u) Status(%u) State(0x%x) ExpBtStartTime(%d) now(%u) delta(%d) +4091,IIIIIii,[ wlan_coex_ocs.c : 1213 ] WLAN_COEX_OCS_RECOMP: State(0x%x) A2dpCrit(%u), ExpBtStartTime(%u), ExpBtStartTimeUT(%u), now (%u) delta(%d) delta_ut(%d) +4090,iI,[ wlan_coex_ocs.c : 256 ] WLAN_OCS_RESTART: rc(%d) vdev_id(%u) +4089,IiIIi,[ wlan_coex_ocs.c : 393 ] WLAN_OCS_REQ: Error(0x%x), status(%d) ocs_req_state(0x%x) bt_req(0x%x) priority(%d) +4088,IIIi,[ wlan_coex_ocs.c : 539 ] WLAN_OCS_REQ: OCS Start: COEX_OCS_START_ERROR (0x%x), ocs_req_state(0x%x) bt_req(0x%x) priority(%d) +4087,III,[ wlan_coex_ocs.c : 438 ] WLAN_OCS_REQ: OCS Start: COEX_OCS_START_ERROR (0x%x), ocs_cal_req_state(0x%x) bt_cal_req(0x%x) +4086,IiIIi,[ wlan_coex_ocs.c : 835 ] WLAN_OCS_UPDATE: Error(0x%x) status(%d) ocs_req_state(0x%x) bt_req(0x%x) priority(%d) +4085,IIi,[ wlan_coex_ocs.c : 604 ] WLAN_COEX_BTREQ: One Shot 0x%x 0x%x priority(%d) +4102,i,[ wlan_coex_test.c : 332 ] PTA Cont info delay time %d +4101,i,[ wlan_coex_test.c : 336 ] PTA Cont info nack time %d +4100,,[ wlan_coex_test.c : 339 ] COEX_GET_PTA_TIMERS_INTERVALS: invalid argument +4099,i,[ wlan_coex_test.c : 371 ] Automation Code %d +4098,ii,[ wlan_coex_test.c : 308 ] PTA set cont info delay pta_num : %d, time:%d +4097,ii,[ wlan_coex_test.c : 312 ] PTA set cont nack pta_num:%d, time:%d +4096,,[ wlan_coex_test.c : 315 ] COEX_SET_PTA_TIMERS_INTERVALS: invalid argument +4095,i,[ wlan_coex_test.c : 245 ] WAL_COEX_FORCED_ALGO: forced_algo(%d) +4104,II,[ wlan_coex_cts2s.c : 248 ] WLAN_COEX_CTS2S_TIMEOUT: Now : %u, WbPrepare: %u +4103,I,[ wlan_coex_cts2s.c : 345 ] COEX_GENERIC_ERROR: COEX_ERROR_UNKNOWN_NULLPTR Status(%u) +4105,,[ wlan_coex_wmi.c : 81 ] COEX_CONFIG_CMD: Either Invalid 2G vdev ID or 2G Mac is not Enabled +4111,IIIII,[ wlan_coex_ps_handler.c : 179 ] COEX_PSP_STAT_1: Resp0(%u) Resp1(%u) Resp2(%u) Resp3(%u) Resp4(%u) +4110,IIIII,[ wlan_coex_ps_handler.c : 182 ] COEX_PSP_STAT_2: DP(%u) Max(%u) RespIdx(%u) ValidDps(%u) PsPAvg(%u) +4109,,[ wlan_coex_ps_handler.c : 261 ] COEX_PSP_MGR: Reset late data frame count +4108,iI,[ wlan_coex_ps_handler.c : 567 ] COEX_GENERIC_ERROR: Set TDM Guard Period to %d, Error (0x%x) +4107,III,[ wlan_coex_ps_handler.c : 134 ] COEX_PSP_SEND_PSPOLL: status(0x%x) PsPollState(0x%x) PsPollNum(%u) +4106,IIII,[ wlan_coex_ps_handler.c : 104 ] WLAN_COEX_SLEEP: status(%u) enable(%u) mac(%u) reason(%u) +4120,II,[ wlan_coex_utils.c : 1186 ] COEX_BT_ACTIVITY: prof_bitmap(0x%x), scan_bitmap(0x%x) +4119,Iii,[ wlan_coex_utils.c : 370 ] WLAN_COEX_LEAKYAP_NULL: found(%u) vdev_id = %d, enable_null_pause = %d +4118,iI,[ wlan_coex_utils.c : 521 ] WLAN_COEX_MCS_RATE: status(%d) mcs(%u) +4117,I,[ wlan_coex_utils.c : 476 ] WLAN_COEX_SET_SWBMISS: wlan_vdev_t is NULL, enable: %u +4116,I,[ wlan_coex_utils.c : 600 ] WLAN_COEX_VDEV_CREATE: Error(0x%x) +4115,i,[ wlan_coex_utils.c : 1472 ] COEX_VDEV_AUTH_MODE: coex_vdev_get_auth_mode: isEnterprise(%d) +4114,iIIII,[ wlan_coex_utils.c : 315 ] WLAN_COEX_VDEV_PAUSE: status(%d) max_time(%u) pause(%u) softAp(%u) opmode(%u) +4113,IiIii,[ wlan_coex_utils.c : 213 ] WLAN_COEX_TXRX_CB: frameType 0x%x vdev %d txSt 0x%x flush %d consFlshCnt %d +4112,ii,[ wlan_coex_utils.c : 1200 ] WLAN_COEX_SLEEP: Received WOW Entered/Exit event from OffloadMgr %d, coex_struct_ptr->is_wow_entered = %d +4154,,[ wlan_pmf_offload.c : 958 ] 11w PMF: PN Replay attack detected +4153,,[ wlan_pmf_offload.c : 225 ] 11W PMF: Beacon add MMIE No pmf_info or PMF is disabled +4152,i,[ wlan_pmf_offload.c : 251 ] 11W PMF: Beacon add MMIE can not handle frame size: %d +4151,i,[ wlan_pmf_offload.c : 232 ] 11W PMF: Beacon add MMIE No BIGTK installed key length: %d +4150,iiii,[ wlan_pmf_offload.c : 849 ] 11w PMF KEY ID MISMATCH MMIE is_bcn = %d key_id = %d, bigtk_key_id = %d igtk_key_id = %d +4149,IIIIIIIi,[ wlan_pmf_offload.c : 863 ] EVENT_WLAN_FW_MMIE_MIC_VALIDATION type = 0x%x sub_type = 0x%x bip_protocol = 0x%x wh->i_addr2 = %08x%04x wh->i_addr1 = %08x%04x mic_validate_status = %d +4148,i,[ wlan_pmf_offload.c : 136 ] 11W PMF : Beacon protection already enabled on vdev %d +4147,i,[ wlan_pmf_offload.c : 575 ] 11w PMF: can not handle frame size: %d +4146,,[ wlan_pmf_offload.c : 594 ] 11w PMF: IE is not Mgmt MIC IE or Invalid length +4145,,[ wlan_pmf_offload.c : 616 ] 11w PMF: BC/MC/Beacon MGMT IPN check Failed +4144,,[ wlan_pmf_offload.c : 680 ] 11w PMF: BC/MC/Beacon CMAC MGMT frame MMIE MIC check Failed +4143,,[ wlan_pmf_offload.c : 749 ] 11w PMF: BC/MC/Beacon GMAC MGMT frame MMIE MIC check Failed +4142,,[ wlan_pmf_offload.c : 798 ] 11W PMF: MMIE valid +4141,iiIII,[ wlan_pmf_offload.c : 1024 ] 11W PMF mgmt hdlr subtype=%d len=%d wal_peer: %p vdev: %p wlan_peer:%p +4140,,[ wlan_pmf_offload.c : 1034 ] 11W PMF mgmt hdlr pmf not enabled +4139,,[ wlan_pmf_offload.c : 1048 ] 11W PMF mgmt hdlr Beacon Protection not enabled +4138,,[ wlan_pmf_offload.c : 1053 ] 11W PMF mgmt hdlr pmf not enabled +4137,,[ wlan_pmf_offload.c : 1068 ] 11W PMF mgmt hdlr frame not from Associated AP +4136,,[ wlan_pmf_offload.c : 1101 ] 11w PMF BIP check failed +4135,I,[ wlan_pmf_offload.c : 1116 ] 11w PMF decrypt error, rx status 0x%x +4134,,[ wlan_pmf_offload.c : 1139 ] 11w PMF drop unenryp robust action category +4133,IIII,[ wlan_pmf_offload.c : 1148 ] 11w PMF action frm %x %x %x %x +4132,ii,[ wlan_pmf_offload.c : 1191 ] 11w PMF current transId=%d startTransId=%d +4131,,[ wlan_pmf_offload.c : 1196 ] 11w PMF SA query rsp with valid transId rcvd +4130,Ii,[ wlan_pmf_offload.c : 1213 ] 11w PMF deauth/disassoc reason_code %x frmType=%d +4129,i,[ wlan_pmf_offload.c : 1216 ] 11w PMF send SA query state=%d +4128,ii,[ wlan_pmf_offload.c : 443 ] 11W PMF: SA query timeout hdlr vdevId=%d, query_state=%d +4127,ii,[ wlan_pmf_offload.c : 448 ] 11W PMF: SA query timeout hdlr cur retry cnt=%d, max retry cnt=%d +4126,iiii,[ wlan_pmf_offload.c : 895 ] 11W PMF: Send SA query vdevId=%d, transId=%d query_type=%d tx_status=%d +4125,iii,[ wlan_pmf_offload.c : 160 ] 11W PMF: Update BiGTK vdevId=%d, keyIdx=%d, KeyLen=%d +4124,,[ wlan_pmf_offload.c : 184 ] igtk: Same key reinstalled +4123,iii,[ wlan_pmf_offload.c : 506 ] 11W PMF: Update iGTK vdevId=%d, keyIdx=%d, KeyLen=%d +4122,,[ wlan_pmf_offload.c : 527 ] igtk: Same key reinstalled +4121,,[ wlan_pmf_offload.c : 1275 ] 11w PMF is not enabled +4157,iI,[ wlan_pmf_offload_init.c : 188 ] 11w PMF: is_bcn=%d,mic_fail_cnt=%x +4156,iI,[ wlan_pmf_offload_init.c : 169 ] 11w PMF: is_bcn=%d, replay_err_cnt=%x +4155,iii,[ wlan_pmf_offload_init.c : 122 ] 11W PMF Offload CMD hdlr: WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID vdevId=%d, interval=%d, retry_count=%d +4163,iIIii,[ wlan_dsm_filter.c : 329 ] DSM_RSSI_REJECTED_AP_ALLOW_UPDATE new_list = %d, bssid %08x%04x exp_delay = %d msec, exp_rssi = %ddBm +4162,i,[ wlan_dsm_filter.c : 378 ] valid_entries=%d +4161,iII,[ wlan_dsm_filter.c : 213 ] DSM_LIST_UPDATE bssid_type = %d bssid removed is %08x%04x +4160,iIIiiiii,[ wlan_dsm_filter.c : 104 ] i | bssid_type = %d, bssid_disallow_ap = %08x%04x retry_delay = %d msec, rssi = %d dbm source|reason = %d original_timestamp = %d original_timeout = %d +4159,iIIiiiii,[ wlan_dsm_filter.c : 196 ] FW added: i | bssid_type = %d, bssid_disallow_ap = %08x%04x retry_delay = %d msec, rssi = %d dbm source|reason = %d original_timestamp = %d original_timeout = %d +4158,iIIii,[ wlan_dsm_filter.c : 526 ] AP Blacklisted: bssid_type = %d, bssid %08x%04x exp_delay = %d msec, exp_rssi = %ddBm +4173,I,[ wlan_framegen.c : 2226 ] WLAN_FRMGEN_GET_ACTION_SMPS incorrect sm_power_control:0x%x +4172,iIiIiIiI,[ wlan_framegen.c : 1903 ] WLAN_FRMGEN_GET_ACTION_TM lci_ie_len:%d lci_ie:0x%x civ_ie_len:%d civ_ie:0x%x ftm_ie_len:%d ftm_ie:0x%x vendor_ie_len:%d vendor_ie:0x%x +4171,iIiIiIiI,[ wlan_framegen.c : 1730 ] WLAN_FRMGEN_GET_ACTION_TMR lci_ie_len:%d lci_ie:0x%x civ_ie_len:%d civ_ie:0x%x ftm_ie_len:%d ftm_ie:0x%x vendor_ie_len:%d vendor_ie:0x%x +4170,iiii,[ wlan_framegen.c : 5806 ] bss color gen evt rpt ie_len=%d evt_token=%d evt_type=%d evt_status=%d +4169,iIi,[ wlan_framegen.c : 6208 ] frmgen_get_default_ie vdev_id=%d fc_type=0x%x length=%d +4168,III,[ wlan_framegen.c : 265 ] WLAN_FRMGEN_GET_NULLFUNC_WITH_HTCTRL FAIL! peer:0x%x addr1:0x%x addr3:0x%x +4167,i,[ wlan_framegen.c : 1559 ] SKIPPED inserting some IE's error_code:%d +4166,iIIi,[ wlan_framegen.c : 6174 ] frmgen_insert_default_ie vdev_id=%d frm_type=0x%x sub_type=0x%x ies_len=%d +4165,IIIi,[ wlan_framegen.c : 6305 ] frmgen_set_default_ie: vdev=0x%x,frm_type=0x%x,buf=0x%x,len=%d +4164,iIiii,[ wlan_framegen.c : 6352 ] frmgen_set_default_ie vdev_id=%d frm_type=0x%x ies_len=%d status=%d i=%d +4241,ii,[ wlan_frameparse.c : 5137 ] FRAME_PARSER frm_len=%d fils_d_size=%d +4240,iiii,[ wlan_frameparse.c : 4776 ] bss color parse evt rpt ie_len=%d evt_token=%d evt_type=%d evt_status=%d +4239,iii,[ wlan_frameparse.c : 589 ] FRMPARSE_WARN ie->ie_len %d (exp %d) remaining_len %d. ignore this IE +4238,ii,[ wlan_frameparse.c : 3669 ] MLME_FRMPARSE_WARN_EXT_CAP ie->ie_len %d (remaining %d) ignore this IE +4237,i,[ wlan_frameparse.c : 3675 ] MLME_FRMPARSE_WARN_EXT_CAP ie->ie_len %d ignore this IE +4236,ii,[ wlan_frameparse.c : 1538 ] MLME_FRMPARSE_WARN_EXT_SUPP_RATE ie->ie_len %d remaining_len %d. ignore this IE +4235,iii,[ wlan_frameparse.c : 1547 ] MLME_FRMPARSE_WARN_EXT_SUPP_RATE rate_index %d (> %d)-> trimmed to %d +4234,I,[ wlan_frameparse.c : 1558 ] MLME_FRMPARSE_WARN_EXT_SUPP_RATE skipped unknown rate 0x%x +4233,,[ wlan_frameparse.c : 1565 ] MLME_FRMPARSE_WARN_EXT_SUPP_RATE no known rate value +4232,iiiI,[ wlan_frameparse.c : 4882 ] wlan_frmparse_get_mgmt_payload frm_len=%d iv_len=%d ivmic_len=%d htctrl_len=%u +4231,ii,[ wlan_frameparse.c : 741 ] MLME_FRMPARSE_WARN_HE_6GHZ_BAND_CAP ie->ie_len %d (exp %d) ignore this IE +4230,ii,[ wlan_frameparse.c : 748 ] MLME_FRMPARSE_WARN_HE_6GHZ_BAND_CAP remaining_len %d (exp %d) ignore this IE +4229,ii,[ wlan_frameparse.c : 646 ] MLME_FRMPARSE_HE_CAP remaining_len %d (exp %d) ignore this IE +4228,ii,[ wlan_frameparse.c : 653 ] MLME_FRMPARSE_HE_CAP remaining_len %d (exp %d) ignore this IE +4227,ii,[ wlan_frameparse.c : 686 ] MLME_FRMPARSE_HE_CAP_MSC remaining_len %d (exp %d) ignore this IE +4226,ii,[ wlan_frameparse.c : 716 ] MLME_FRMPARSE_HE_PPET remaining_len %d (exp %d) ignore this IE +4225,ii,[ wlan_frameparse.c : 494 ] MLME_FRMPARSE_HE_OP remaining_len %d (exp %d) ignore this IE +4224,ii,[ wlan_frameparse.c : 501 ] MLME_FRMPARSE_HE_OP remaining_len %d (exp %d) ignore this IE +4223,iiii,[ wlan_frameparse.c : 565 ] FRMPARSE he op ie heop_present=%d vht_op_present=%d 6ghz_op=%d max_co_loc_bssid_present=%d. +4222,ii,[ wlan_frameparse.c : 263 ] MLME_FRMPARSE_WARN_HT_CAP ie->ie_len %d (exp %d) ignore this IE +4221,ii,[ wlan_frameparse.c : 269 ] MLME_FRMPARSE_WARN_HT_CAP remaining_len %d (exp %d) ignore this IE +4220,ii,[ wlan_frameparse.c : 326 ] MLME_FRMPARSE_WARN_HT_OPER ie->ie_len %d (exp %d) ignore this IE +4219,ii,[ wlan_frameparse.c : 332 ] MLME_FRMPARSE_WARN_HT_OPER remaining_len %d (exp %d) ignore this IE +4218,,[ wlan_frameparse.c : 4710 ] FRM_PARSE_IE_ITERATOR ie_buffer_start is NULL +4217,ii,[ wlan_frameparse.c : 4717 ] FRM_PARSE_IE_ITERATOR ERROR remaining_length(%d) < ie_hdr_size(%d) +4216,ii,[ wlan_frameparse.c : 4724 ] FRM_PARSE_IE_ITERATOR ERROR remaining_length(%d) < ie_len(%d) +4215,ii,[ wlan_frameparse.c : 1817 ] FRMPARSE_WARN_MU_EDCA_PARAM ie->ie_len %d (exp %d). ignore this IE +4214,ii,[ wlan_frameparse.c : 1824 ] FRMPARSE_WARN_MU_EDCA_PARAM ie->ie_len %d remaining_len %d. ignore this IE +4213,ii,[ wlan_frameparse.c : 81 ] MLME_FRMPARSE_WARN_QBSS ie->ie_len %d remaining_len %d. ignore this IE +4212,ii,[ wlan_frameparse.c : 86 ] MLME_FRMPARSE_WARN_QBSS ie->ie_len %d (!= %d) +4211,ii,[ wlan_frameparse.c : 1435 ] MLME_FRMPARSE_WARN_SSID ie->ie_len %d (> %d) +4210,ii,[ wlan_frameparse.c : 1442 ] MLME_FRMPARSE_WARN_SSID ie->ie_len %d remaining_len %d. ignore this IE +4209,ii,[ wlan_frameparse.c : 1476 ] MLME_FRMPARSE_WARN_SUPP_RATE ie->len %d (> %d)-> ignore this IE +4208,ii,[ wlan_frameparse.c : 1484 ] MLME_FRMPARSE_WARN_SUPP_RATE ie->ie_len %d remaining_len %d. ignore this IE +4207,I,[ wlan_frameparse.c : 1499 ] MLME_FRMPARSE_WARN_SUPP_RATE skipped unknown rate 0x%x +4206,,[ wlan_frameparse.c : 1508 ] MLME_FRMPARSE_WARN_SUPP_RATE no known rate value +4205,i,[ wlan_frameparse.c : 4418 ] MLME_FRMPARSE_VENDOR_VHT unknown type %d +4204,ii,[ wlan_frameparse.c : 4435 ] MLME_FRMPARSE_WARN_VENDOR_VHT remaining_len %d (exp %d) ignore this IE +4203,I,[ wlan_frameparse.c : 4448 ] MLME_FRMPARSE_WARN_VENDOR_VHT ERROR vht_caps. status %x + +4202,I,[ wlan_frameparse.c : 4462 ] MLME_FRMPARSE_WARN_VENDOR_VHT ERROR vht_oper. status %x + +4201,ii,[ wlan_frameparse.c : 424 ] MLME_FRMPARSE_WARN_VHT_CAP ie->ie_len %d (exp %d) ignore this IE +4200,ii,[ wlan_frameparse.c : 431 ] MLME_FRMPARSE_WARN_VHT_CAP remaining_len %d (exp %d) ignore this IE +4199,ii,[ wlan_frameparse.c : 371 ] MLME_FRMPARSE_WARN_VHT_OPER ie->ie_len %d (exp %d) ignore this IE +4198,ii,[ wlan_frameparse.c : 378 ] MLME_FRMPARSE_WARN_VHT_OPER remaining_len %d (exp %d) ignore this IE +4197,i,[ wlan_frameparse.c : 2246 ] MLME_FRMPARSE_WPA_IE skip parsing as rsn_ie_len (%d) is present +4196,iIII,[ wlan_frameparse.c : 1963 ] MLME_FRMPARSE_WPA_RSN_CIPHER index %d unknown vendor oui 0x%08x 0x%08x 0x%08x +4195,I,[ wlan_frameparse.c : 1990 ] MLME_FRMPARSE_WPA_RSN_CIPHER_ERR can't use_group for suite type 0x%x +4194,iIi,[ wlan_frameparse.c : 2006 ] MLME_FRMPARSE_WPA_RSN_CIPHER index %d unknown suite type 0x%08x cipher_suite_type = %d +4193,iiiII,[ wlan_frameparse.c : 2019 ] MLME_FRMPARSE_WPA_RSN_CIPHER cipher_suite_count %d is_rsn %d suite_type %d (0=group,1=pair,2=group_mgmt) cipher_type 0x%08x ie_status 0x%x +4192,i,[ wlan_frameparse.c : 2057 ] MLME_FRMPARSE_ERROR_WPA_RSN missing version field. remaining_len %d +4191,ii,[ wlan_frameparse.c : 2064 ] MLME_FRMPARSE_ERROR_WPA_RSN version (%d) is not 1. remaining ie_len %d +4190,i,[ wlan_frameparse.c : 2074 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete group cipher suite. remaining_len = %d (< 4) +4189,i,[ wlan_frameparse.c : 2088 ] MLME_FRMPARSE_WARN_WPA_RSN pairwise suite count remaining_len %d (< 2) +4188,ii,[ wlan_frameparse.c : 2096 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete pairwise cipher suite. remaining_len = %d (< %d) +4187,i,[ wlan_frameparse.c : 2110 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete akm suite count remaining_len %d (< 2) +4186,ii,[ wlan_frameparse.c : 2120 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete akm suite. remaining_len = %d (< %d) +4185,i,[ wlan_frameparse.c : 2131 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete rsn caps. remaining_len = %d (< 2) +4184,II,[ wlan_frameparse.c : 2142 ] MLME_FRMPARSE_WARN_WPA_RSN rsn_caps.pre_auth set in WPA rem_ie_len=%x, ie_status=%x +4183,i,[ wlan_frameparse.c : 2159 ] MLME_FRMPARSE_WARN_WPA_RSN pmkid. remaining_len = %d (< 2) +4182,ii,[ wlan_frameparse.c : 2169 ] MLME_FRMPARSE_WARN_WPA_RSN pmkid. remaining_len = %d (< %d) +4181,i,[ wlan_frameparse.c : 2185 ] MLME_FRMPARSE_WARN_WPA_RSN incomplete group mgmt cipher suite. remaining_len = %d (< 4) +4180,iIII,[ wlan_frameparse.c : 1878 ] MLME_FRMPARSE_WPA_RSN_AKM index %d unknown vendor oui 0x%08x 0x%08x 0x%08x +4179,iI,[ wlan_frameparse.c : 1924 ] MLME_FRMPARSE_WPA_RSN_AKM index %d unknown suite type 0x%08x + +4178,iiIII,[ wlan_frameparse.c : 1930 ] MLME_FRMPARSE_WPA_RSN_AKM akm_suite_count %d is_rsn %d proto 0x%08x key_mgmt 0x%08x ie_status 0x%x +4177,i,[ wlan_frameparse.c : 1260 ] MLME_PHYMODE invaild center freq0 phymode=%d +4176,i,[ wlan_frameparse.c : 1356 ] MLME_PHYMODE invaild center freq0 phymode=%d +4175,iiiii,[ wlan_frameparse.c : 1025 ] wlan_get_rx_nss nss=%d,%d,%d,%d,%d +4174,iiiii,[ wlan_frameparse.c : 1080 ] wlan_get_tx_nss nss=%d,%d,%d,%d,%d +4260,iii,[ wlan_key_mgmt.c : 40 ] KEYMGMT_ADD_PEER_ENTRY key_ciper:%d key_len:%d is_mcast:%d +4259,iIi,[ wlan_key_mgmt.c : 77 ] KEYMGMT_ADD_KEY_ENTRY_REINSTALLATION ERROR id=%d flags=0x%x len=%d +4258,i,[ wlan_key_mgmt.c : 104 ] KEYMGMT_ADD_PEER_ENTRY WEP ERROR key_len:%d +4257,i,[ wlan_key_mgmt.c : 120 ] KEYMGMT_ADD_PEER_ENTRY AES CCM ERROR key_len:%d +4256,i,[ wlan_key_mgmt.c : 137 ] KEYMGMT_ADD_PEER_ENTRY AES GCM ERROR key_len:%d +4255,i,[ wlan_key_mgmt.c : 172 ] KEYMGMT_ADD_PEER_ENTRY ERROR key_ciper:%d +4254,iii,[ wlan_key_mgmt.c : 195 ] wal_peer_set_key type=%d, keyid=%d,pairwise=%d failed + +4253,i,[ wlan_key_mgmt.c : 43 ] KEYMGMT_ADD_PEER_ENTRY open key_ciper:%d +4252,,[ wlan_key_mgmt.c : 57 ] KEYMGMT_ADD_PEER_ENTRY ERROR! wal_peer is NULL +4251,i,[ wlan_key_mgmt.c : 416 ] KEYMGMT_CLR_KEY_ENTRY id=%d +4250,i,[ wlan_key_mgmt.c : 433 ] KEYMGMT_CLR_KEY_ENTRY id=%d +4249,,[ wlan_key_mgmt.c : 244 ] KEYMGMT_ADD_GROUP_KEY ERROR! wal_peer is NULL +4248,i,[ wlan_key_mgmt.c : 270 ] KEYMGMT_ADD_GROUP_KEY WEP ERROR key_len:%d +4247,i,[ wlan_key_mgmt.c : 327 ] KEYMGMT_ADD_GROUP_KEY ERROR key_ciper:%d +4246,iII,[ wlan_key_mgmt.c : 527 ] KEYMGMT_RESET_KEY id=%d peer_addr=%08x%04x +4245,iiIi,[ wlan_key_mgmt.c : 367 ] KEYMGMT_ADD_KEY_ENTRY id=%d key_idx=%d flags=0x%x len=%d +4244,iIi,[ wlan_key_mgmt.c : 382 ] KEYMGMT_ADD_KEY_ENTRY_EXISTING key_idx=%d flags=0x%x len=%d +4243,ii,[ wlan_key_mgmt.c : 394 ] KEYMGMT_ADD_KEY_ENTRY_NO_MEM id=%d key_idx=%d +4242,iiIiII,[ wlan_key_mgmt.c : 479 ] KEYMGMT_INSTALL_KEY_ENTRY id=%d idx=%d key_flags_bitmap=0x%x len=%d peer_addr=0x04%x08%x +4283,ii,[ wlan_beacon.c : 1163 ] WLAN_BEACON_CANCEL_RESYNC: vdev_id=%d, resyncBeacon=%d +4282,II,[ wlan_beacon.c : 1866 ] nextdtim: 0x%08x%08x +4281,II,[ wlan_beacon.c : 654 ] tsf_beacon: 0x%08x%08x +4280,ii,[ wlan_beacon.c : 1135 ] WLAN_BEACON_RESYNC: vdev_id=%d, resyncBeacon=%d +4279,ii,[ wlan_beacon.c : 2343 ] BEACON_RESYNC_ARBITER_ADD_CLIENT: vdev_id=%d, client_id=%d +4278,i,[ wlan_beacon.c : 2326 ] BEACON_RESYNC_ARBITER_CANCEL_ALL_REQUESTS: vdev_id=%d +4277,ii,[ wlan_beacon.c : 2301 ] BEACON_RESYNC_ARBITER_CANCEL_REQUEST: vdev_id=%d, client_id=%d +4276,ii,[ wlan_beacon.c : 2357 ] BEACON_RESYNC_ARBITER_REMOVE_CLIENT: vdev_id=%d, client_id=%d +4275,ii,[ wlan_beacon.c : 2270 ] BEACON_RESYNC_ARBITER_REQUEST: vdev_id=%d, client_id=%d +4274,iii,[ wlan_beacon.c : 2373 ] BEACON_RESYNC_ARBITER_RESOLVE: vdev_id=%d, is_vdev_holding=%d, SLIST_EMPTY(hold_list)=%d +4273,i,[ wlan_beacon.c : 2399 ] BEACON_RESYNC_ARBITER_VDEV_INIT: vdev_id=%d +4272,,[ wlan_beacon.c : 2417 ] arbiter_clinet POOL ALLOC FAILURE +4271,,[ wlan_beacon.c : 2404 ] arbiter_clinet POOL ALLOC FAILURE +4270,i,[ wlan_beacon.c : 2439 ] BEACON_RESYNC_ARBITER_VDEV_DEINIT: vdev_id=%d +4269,,[ wlan_beacon.c : 1060 ] WLAN_BEACON_TBTTOFFSET_UPDATE_HANDLER ERROR! pmac is NULL +4268,iIII,[ wlan_beacon.c : 1097 ] WLAN_BEACON_TBTTOFFSET_UPDATE_HANDLER vdev_map mismatch i:%d vdev_map:0x%x vdev_id_map:0x%x max_diff:0x%x +4267,,[ wlan_beacon.c : 207 ] beacon_init POOL ALLOC FAILURE +4266,iI,[ wlan_beacon.c : 1470 ] _wlan_tsfoor_handler: vdev_id = %d, tesf = 0x%x +4265,iiii,[ wlan_beacon.c : 756 ] QUIET IE STA: period=%d dur=%d, offset=%d, tbtt cnt=%d +4264,ii,[ wlan_beacon.c : 166 ] wlan_beacon_unit_test_module %d %d +4263,,[ wlan_beacon.c : 980 ] WLAN_BEACON_WAL_TBTTOFFSET_UPDATE_HANDLER ERROR! pmac is NULL +4262,ii,[ wlan_beacon.c : 131 ] wlan_beacon_unit_test_beacon_start_stop %d %d +4261,i,[ wlan_beacon.c : 157 ] wlan_beacon_unit_test_slot_time %d +4300,iI,[ wlan_mbssid.c : 659 ] MBSS: NONTRAN_BSSID_CAP IE length: %d, NontxBssidCap: 0x%x +4299,iI,[ wlan_mbssid.c : 664 ] MBSS: SSID IE length:%d ssid:%s +4298,iIIIIIIii,[ wlan_mbssid.c : 680 ] MBSS: Couldn't find (mbssid_ind %d) %x:%x:%x:%x:%x:%x, DP: %d, DC:%d +4297,iiii,[ wlan_mbssid.c : 689 ] MBSS: UPDATE: mbssid_idx:%d, period:%d, *dtim_cnt:%d, vdev_dtim_intval:%d +4296,iiiiii,[ wlan_mbssid.c : 698 ] MBSS: SET: mbssid_idx: %d, dtimperiod:%d, frm_dtimcnt:%d, vdev_dtim_cnt %d, recvd_dtim:%d, settingdtm:%d +4295,i,[ wlan_mbssid.c : 716 ] MBSS: Unhandled wlan_mbss_index_update_type: %d +4294,ii,[ wlan_mbssid.c : 723 ] MBSS: ELEMENT ID: %d, IE length: %d +4293,ii,[ wlan_mbssid.c : 534 ] WLAN_MBSSID_GET_MAX_INDICATOR mismatch cur = %d previous = %d +4292,ii,[ wlan_mbssid.c : 539 ] WLAN_MBSSID_GET_MAX_INDICATOR Big max_bssid_ind = %d (max = %d) +4291,iiIIIIII,[ wlan_mbssid.c : 598 ] MBSSID_GET_NONTRANS_BSSID profile_id = %d bssid_index = %d mac addr = %02x:%02x:%02x:%02x:%02x:%02x +4290,ii,[ wlan_mbssid.c : 437 ] MBSSID_GET_NONTRANS_BSSID_PROF_NUM profile_num = %d max_mbssid_indicator = %d +4289,ii,[ wlan_mbssid.c : 828 ] WLAN_MBSSID_GET_MAX_INDICATOR mismatch cur = %d previous = %d +4288,ii,[ wlan_mbssid.c : 833 ] WLAN_MBSSID_GET_MAX_INDICATOR Big max_bssid_ind = %d (max = %d) +4287,ii,[ wlan_mbssid.c : 301 ] MBSSID_IS_BSSID_MATCHED fail, len:%d err_code:%d (5:invalid_idx, 6:invalid_prof_id) +4286,,[ wlan_mbssid.c : 326 ] MBSSID_IS_SSID_MATCHED legacy case +4285,ii,[ wlan_mbssid.c : 360 ] MBSSID_IS_SSID_MATCHED profile_id = %d ssid_len = %d +4284,i,[ wlan_mbssid.c : 779 ] MBSS: MBSSID_GET_NONTRANS_BSSID_PROF_NUM profile_num = %d +4303,ii,[ wlan_phyerr_internal.c : 121 ] phyerr event err: buf_len:%d>%d +4302,,[ wlan_phyerr_internal.c : 208 ] phyerr event: alloc event failure +4301,iiiii,[ wlan_phyerr_internal.c : 223 ] phyerr event, lo:%d, now_mac:%d, now_os:%d, phy0:%d, phy1:%d +4316,i,[ wlan_dfs_phyerr_offload.c : 393 ] PHYERR offload enable pdev_id=%d +4315,,[ wlan_dfs_phyerr_offload.c : 429 ] PHYERR unexpected offload disable command for HKv2! +4314,iiiiiii,[ wlan_dfs_phyerr_offload.c : 481 ] ADFS_DUMPS WMI_VDEV_ADFS_CH_CFG_CMD center_freq1=%d, center_freq2=%d, chan_width=%d, cac_duration_ms=%d, ocac_mode=%d, flags=%d, vdev_id=%d +4313,ii,[ wlan_dfs_phyerr_offload.c : 519 ] ADFS_DUMPS PROTOCOL-Starting timer for cac_duration_ms:%d, current_time:%d + +4312,i,[ wlan_dfs_phyerr_offload.c : 74 ] ADFS_DUMPS PROTOCOL-Inside wlan_adfs_cac_timer_handler, current_time = %d +4311,iiiii,[ wlan_dfs_phyerr_offload.c : 57 ] ADFS_DUMPS PROTOCOL-Sending WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID center_freq1=%d, center_freq2=%d, bandwidth=%d, status=%d, vdev_id=%d +4310,,[ wlan_dfs_phyerr_offload.c : 260 ] PHYERR offload cac check not DFS chan +4309,ii,[ wlan_dfs_phyerr_offload.c : 265 ] PHYERR offload not enabled, mac_id=%d vdev_id=%d +4308,i,[ wlan_dfs_phyerr_offload.c : 96 ] PHYERR offload cac timeout vdevId=%d +4307,ii,[ wlan_dfs_phyerr_offload.c : 240 ] PHYERR offload mac_id=%d enabled=%d +4306,,[ wlan_dfs_phyerr_offload.c : 594 ] register - WMI_SERVICE_DFS_PHYERR_OFFLOAD +4305,i,[ wlan_dfs_phyerr_offload.c : 355 ] PHYERR offload send radar detection evt WMI pdevId=%d +4304,iiii,[ wlan_dfs_phyerr_offload.c : 357 ] PHYERR offload det mode=%d, chan_freq=%d det_id=%d seg_id=%d +4319,iii,[ wlan_dfs_phyerr_unit_test.c : 44 ] wlan_dfs_phyerr_offload_unit_test input: vdevId=%d testId=%d num_args=%d +4318,ii,[ wlan_dfs_phyerr_unit_test.c : 60 ] wlan_dfs_phyerr_offload_unit_test input: set radar mac_id=%d cmd=%d +4317,ii,[ wlan_dfs_phyerr_unit_test.c : 107 ] wlan_dfs_phyerr_offload_unit_test input: mac_id=%d enable radar det offload=%d +4327,II,[ wlan_txbf.c : 355 ] TXBFEE_DBGID_HOST_CONFIG_CMDID ID=0x%x Value=0x%x +4326,IIIIi,[ wlan_txbf.c : 121 ] TXBF: SUBFee=0x%x MUBFee=0x%x SUBFer=0x%x MUBFer=0x%x chan->phy_mode=%d +4325,iI,[ wlan_txbf.c : 249 ] TXBFEE_DBGID_BRPOLL_RECEIVED vdev_id = %d fbSegBmap=0x%x +4324,,[ wlan_txbf.c : 271 ] Non-directed GID frame + +4323,iII,[ wlan_txbf.c : 323 ] TXBFEE_DBGID_GID_RECEIVED vdev_id = %d gid=0x%x userpos=0x%x +4322,iI,[ wlan_txbf.c : 297 ] i=%d, membership=0x%x + +4321,i,[ wlan_txbf.c : 314 ] Gid=%d + +4320,iiIi,[ wlan_txbf.c : 228 ] TXBFEE_DBGID_NDPA_RECEIVED vdev_id=%d vht_he=%d staInfo=0x%x token_num=%d +4328,I,[ wlan_txbf_unit_test.c : 78 ] WLAN_TXBF_CONFIG param = 0x%x +4331,II,[ unit_test.c : 416 ] UNIT_TEST_GEN 0x%x 0x%x +4330,IIIII,[ unit_test.c : 424 ] UNIT_TEST_GEN 0x%x 0x%x 0x%x 0x%x, 0x%x +4329,,[ unit_test.c : 175 ] DTF Disabled +4393,ii,[ wlan_regdb_offload.c : 192 ] AFC: Compile time flag is NOT set. Timer check disable =%d Request Id check disable= %d +4392,iiI,[ wlan_regdb_offload.c : 305 ] REGDB set init country command pdev_id=%d, cc_type=%d, cc_value=%x +4391,i,[ wlan_regdb_offload.c : 315 ] AFC num AP SP rules=%d, +4390,i,[ wlan_regdb_offload.c : 317 ] AFC Host wmi/ini disabled: %d, +4389,i,[ wlan_regdb_offload.c : 323 ] AFC ini timer disabled: %d, +4388,,[ wlan_regdb_offload.c : 328 ] AFC event sent +4387,i,[ wlan_regdb_offload.c : 358 ] AFC num AP SP rules=%d, +4386,i,[ wlan_regdb_offload.c : 360 ] AFC Host wmi/ini disabled: %d, +4385,i,[ wlan_regdb_offload.c : 366 ] AFC ini timer disabled: %d, +4384,,[ wlan_regdb_offload.c : 371 ] AFC event sent +4383,,[ wlan_regdb_offload.c : 405 ] REGDB AFC HOST RX INDICATION RECEIVED +4382,iIii,[ wlan_regdb_offload.c : 409 ] REGDB AFC host event received cmd pdev_id=%d,tlv_header= 0%x, tlv_tag_id_enum = %d,tag_id_rec = %d +4381,I,[ wlan_regdb_offload.c : 430 ] AFC : buffer: 0x%x + +4380,i,[ wlan_regdb_offload.c : 442 ] AFC TTL set to %d: +4379,,[ wlan_regdb_offload.c : 453 ] AFC bin parsed +4378,,[ wlan_regdb_offload.c : 474 ] register - WMI_SERVICE_REGULATORY_DB +4377,i,[ wlan_regdb_offload.c : 806 ] REGDB send afc expiry reg rules for mac_id=%d +4376,i,[ wlan_regdb_offload.c : 815 ] REGDB send wmi afc expiry reg rules failed - status=%d +4375,Iiii,[ wlan_regdb_offload.c : 820 ] REGDB AFC send wmi afc expiry reg rules for request_id= %u, mac_id= %d, event_type= %d, event_subtype= %d +4374,i,[ wlan_regdb_offload.c : 842 ] REGDB send afc power reg rules for mac_id=%d +4373,i,[ wlan_regdb_offload.c : 861 ] REGDB send afc power reg rules failed - status=%d +4372,iiii,[ wlan_regdb_offload.c : 866 ] REGDB send afc power reg rules for response_id=%d, event_type =%d, fw_status_code=%d, afc_serv_resp_code=%d +4371,i,[ wlan_regdb_offload.c : 782 ] REGDB EXT send reg rules failed - status=%d +4370,i,[ wlan_regdb_offload.c : 722 ] REGDB send reg rules failed - status=%d +4369,ii,[ wlan_regdb_offload.c : 728 ] REGDB rdCtl: %d %d +4368,II,[ wlan_regdb_offload.c : 732 ] REGDB send default reg rules for alpha2: %c %c +4367,iiiiii,[ wlan_regdb_offload.c : 734 ] REGDB send def reg rules phy_id=%d status_code=%d, ctry_id=%d dom_code=%d, num_2g_rules=%d, num_5g_rules=%d +4366,IIiiii,[ wlan_regdb_offload.c : 737 ] REGDB dfs_reg=%x, phybitmap=%x minbw2g=%d maxbw2g=%d minbw5g=%d maxbw5g=%d +4365,,[ wlan_regdb_offload.c : 629 ] REGDB EXT fail - invalid country code input +4364,,[ wlan_regdb_offload.c : 633 ] REGDB EXT fail - invalid get type +4363,iiiI,[ wlan_regdb_offload.c : 516 ] REGDB send reg rules for mac_id=%d get_type=%d cc_type=%d cc_value=%x +4362,i,[ wlan_regdb_offload.c : 585 ] REGDB send reg rules failed - status=%d +4361,II,[ wlan_regdb_offload.c : 589 ] REGDB send reg rules for alpha2: %c %c +4360,iiiiii,[ wlan_regdb_offload.c : 591 ] REGDB phy_id=%d status_code=%d, ctry_id=%d dom_code=%d, num_2g_rules=%d, num_5g_rules=%d +4359,IIiiii,[ wlan_regdb_offload.c : 594 ] REGDB dfs_reg=%x, phybitmap=%x minbw2g=%d maxbw2g=%d minbw5g=%d maxbw5g=%d +4358,,[ wlan_regdb_offload.c : 531 ] REGDB fail - invalid country code input +4357,,[ wlan_regdb_offload.c : 535 ] REGDB fail - invalid get type +4356,,[ wlan_regdb_offload.c : 1149 ] RegDB AFC expiry wmi buf alloc fail +4355,,[ wlan_regdb_offload.c : 1187 ] AFC - INIT WMI_AFC_EXP_REG_RULES + +4354,,[ wlan_regdb_offload.c : 1189 ] AFC - Sent WMI_AFC_EXP_REG_RULES + +4353,ii,[ wlan_regdb_offload.c : 1244 ] AFC NUM_EIRP:%d, length: %d +4352,iiiiii,[ wlan_regdb_offload.c : 1290 ] AFC - fw_status_code:%d response_id:%d afc_serv_resp_code:%d afc_wfa_version:%d avail_exp_time_d:%d avail_exp_time_t:%d + +4351,iiii,[ wlan_regdb_offload.c : 1310 ] AFC - High Freq WMI:%d Low Freq WMI:%d High Freq:%d Low Freq:%d + +4350,i,[ wlan_regdb_offload.c : 1314 ] AFC - Payload ERROR, Low Freq is:%d which is lower than operable frequency for 6 GHz + +4349,i,[ wlan_regdb_offload.c : 1318 ] AFC - Payload ERROR, High Freq is:%d which is higher than operable frequency for 6 GHz + +4348,iii,[ wlan_regdb_offload.c : 1320 ] AFC - freq_info:%d psd_power_info:%d num_frequency:%d + +4347,ii,[ wlan_regdb_offload.c : 1343 ] AFC - global_operating_class:%d num_channels:%d + +4346,ii,[ wlan_regdb_offload.c : 1372 ] AFC - channel_cfi:%d max_eirp_pwr:%d + +4345,i,[ wlan_regdb_offload.c : 1375 ] AFC - Paylod ERROR, max_eirp_pwr is :%d which is greater than defaul max + +4344,I,[ wlan_regdb_offload.c : 1394 ] AFC : PWR EVT buffer: 0x%x + +4343,,[ wlan_regdb_offload.c : 1397 ] RegDB - AFC PWR EVT TRIGGERED + +4342,,[ wlan_regdb_offload.c : 1399 ] RegDB - AFC PWR EVT SENT + +4341,,[ wlan_regdb_offload.c : 1249 ] RegDB AFC pwr wmi buf alloc fail +4340,i,[ wlan_regdb_offload.c : 1025 ] RegDB EXT Rules Assert - %d + +4339,,[ wlan_regdb_offload.c : 1034 ] RegDB EXT wmi buf alloc fail +4338,,[ wlan_regdb_offload.c : 1119 ] RegDB - Sent WMI_REG_CHAN_LIST_CC_EXT_EVENT + +4337,II,[ wlan_regdb_offload.c : 896 ] REGDB read reg rules alpha2 %c %c +4336,iiii,[ wlan_regdb_offload.c : 907 ] REGDB max_rules=%d 2g_rules=%d 5g_rules=%d, evt_len=%d +4335,,[ wlan_regdb_offload.c : 910 ] REGDB wmi buf alloc fail +4334,iIII,[ wlan_regdb_offload.c : 973 ] REGDB ruleIdx=%d freq info=%x bw_pwr=%x flag=%x +4333,,[ wlan_regdb_offload.c : 983 ] REGDB send WMI_REG_CHAN_LIST_CC_EVENTID +4332,ii,[ wlan_regdb_offload.c : 133 ] REGDB test command num_args=%d testId=%d +4417,iiiIIIiii,[ wlan_beacon_tx_offload.c : 783 ] BEACON_DIAG: TX_OK pdev:%d vdev:%d seq_num:%d TBTT:%luus compl_TS:%luus delay_from_TBTT:%luus bcn_delta:%d.%dms consec_bcn_fail:%d +4416,iiIIiiiii,[ wlan_beacon_tx_offload.c : 799 ] BEACON_DIAG: TX_FAIL pdev|vdev:%d seq_num:%d TBTT:%luus compl_TS:%luus last_tx_ok_seq_num:%d cons_fail:%d err_st:%d tx_attm:%d flush_rc:%d +4415,i,[ wlan_beacon_tx_offload.c : 1746 ] WOW_PROBE_RESP_TX: tx done cb, compl status=%d +4414,I,[ wlan_beacon_tx_offload.c : 1346 ] HE_RTS_THRESHOLD_DBG: enter: he_op_ie rts_thresh: %lu +4413,iiii,[ wlan_beacon_tx_offload.c : 1370 ] HE_RTS_THRESHOLD_DBG: middle: he_rts_load_enable_threshold: %d, load_metric: %d, active_user_count: %d, rx_load_pct: %d +4412,I,[ wlan_beacon_tx_offload.c : 1384 ] HE_RTS_THRESHOLD_DBG: exit: he_op_ie rts_thresh: %lu +4411,IIIIiiI,[ wlan_beacon_tx_offload.c : 957 ] BEACON TX ignored, vdev id:%x, mac_id:%x, bcn_tx_paused:%x, pdev_id:%x, swba_delay:%d consec_beacon_skip:%d, on_chan = %x +4410,IIIii,[ wlan_beacon_tx_offload.c : 1070 ] BEACON TX bcn_ctxt->do_not_send_bcn_h8/bcn_ctxt->csa_in_progress_8/send_evt_to_host_16 : 0x%x ,update_switch_count:%x, bcn_ctxt->current_csa_count:%x, bcn_ctxt->csa_event_bitmap:%d pmac->csa_cur_sw_count:%d +4409,I,[ wlan_beacon_tx_offload.c : 1088 ] WOW_RECV_MGMT frame_type = 0x%x +4408,ii,[ wlan_beacon_tx_offload.c : 1401 ] MU_EDCA_DEBUG: id: %d, update_cnt: %d +4407,iiiii,[ wlan_beacon_tx_offload.c : 1406 ] MU_EDCA_DEBUG: id: %d, BK: cwmin: %d, cwmax: %d, aifsn: %d, edca_timer: %d +4406,iiiii,[ wlan_beacon_tx_offload.c : 1411 ] MU_EDCA_DEBUG: id: %d, BE: cwmin: %d, cwmax: %d, aifsn: %d, edca_timer: %d +4405,iiiii,[ wlan_beacon_tx_offload.c : 1416 ] MU_EDCA_DEBUG: id: %d, VI: cwmin: %d, cwmax: %d, aifsn: %d, edca_timer: %d +4404,iiiii,[ wlan_beacon_tx_offload.c : 1421 ] MU_EDCA_DEBUG: id: %d, VO: cwmin: %d, cwmax: %d, aifsn: %d, edca_timer: %d +4403,iiiiii,[ wlan_beacon_tx_offload.c : 303 ] OPTDBG: vdevid:%d, vdev chan_idx:%d, vdev opclass:%d, regdomain:%d, rnr opclass: %d, rnr_chidx:%d +4402,iIIi,[ wlan_beacon_tx_offload.c : 629 ] BCN_TMPL_CMDID: dtim_count_tmpl0:%d, nonTxVdevMap: 0x%x 0x%x Cur_idx:%d +4401,iiii,[ wlan_beacon_tx_offload.c : 666 ] MBSS : BCN_TMPL_CMDID: TMPL0: %d DTIM: %d Cur_pp_index: %d PP:%d + +4400,iii,[ wlan_beacon_tx_offload.c : 692 ] BCN_TMPL_CMDID: dtim_count:%d, pp:%d new_pp_eff_in_bcn:%d +4399,,[ wlan_beacon_tx_offload.c : 2275 ] WOW_PROBE_RESP_TX: wps ie recv, wakeup host +4398,,[ wlan_beacon_tx_offload.c : 227 ] QUIET IE AP_swba: BCN_CTXT Null +4397,I,[ wlan_beacon_tx_offload.c : 232 ] QUIET IE AP_swba: SWBA Enable value = %x +4396,I,[ wlan_beacon_tx_offload.c : 237 ] QUIET IE AP_swba: SWBA disable value = %x +4395,ii,[ wlan_beacon_tx_offload.c : 1841 ] WOW_PROBE_RESP_TX: Err sending probe response not on home channel vdev home channel = %d, mac cahnnel = %d +4394,,[ wlan_beacon_tx_offload.c : 2034 ] WOW_PROBE_RESP_TX: send probe resp +4430,IIIII,[ wlan_beacon_tx_offload_wmi.c : 588 ] QUIET IE AP: vdev_id= %x period = %x duration = %x off = %x flag = %x +4429,,[ wlan_beacon_tx_offload_wmi.c : 657 ] buf POOL ALLOC FAILURE +4428,I,[ wlan_beacon_tx_offload_wmi.c : 695 ] QUIET IE AP_swba: TIM Disable value = %x +4427,I,[ wlan_beacon_tx_offload_wmi.c : 705 ] QUIET IE AP_swba: TIM Enable value = %x +4426,,[ wlan_beacon_tx_offload_wmi.c : 650 ] offload_ctxt POOL ALLOC FAILURE +4425,,[ wlan_beacon_tx_offload_wmi.c : 96 ] bcn_ctxt POOL ALLOC FAILURE +4424,I,[ wlan_beacon_tx_offload_wmi.c : 1229 ] QUIET IE AP: num_args= %x failed +4423,IIIII,[ wlan_beacon_tx_offload_wmi.c : 1241 ] QUIET IE AP: vdev_id= %x period = %x duration = %x off = %x flag = %x +4422,,[ wlan_beacon_tx_offload_wmi.c : 1323 ] 11w Bcn prot test : CSA IE not added by host +4421,Ii,[ wlan_beacon_tx_offload_wmi.c : 1132 ] WOW_PROBE_RESP_TX offload flags = 0x%x enabled = %d +4420,iiiiiiI,[ wlan_beacon_tx_offload_wmi.c : 336 ] BCN_TMPL_CMDID: vdevid:%d, tmplt_idx:%d, first:%d, last:%d, pp:%d, maxpp:%d, vdev_flags:0x%x +4419,ii,[ wlan_beacon_tx_offload_wmi.c : 369 ] tmplt_idx %d >= profile_period %d +4418,iI,[ wlan_beacon_tx_offload_wmi.c : 515 ] WOW_PROBE_RESP_TX: PRB TMPL CMDID, probe_resp_len=%d flags=%x +4433,iii,[ wlan_nth_beacon_offload.c : 88 ] wlan_nth_bcn_ofld_run_timer error can't start timer nvalue = %d, ifup = %d, active = %d +4432,iiiiiIII,[ wlan_nth_beacon_offload.c : 141 ] wlan_nth_bcn_ofld_run_timer timeout_val_ms = %d, nvalue = %d, status = %d, is_nth_beacon_enable = %d, drift_ms = %d, next_tbtt = 0x%x, cur_tsf =0x%x bi_us = 0x%x +4431,iiiii,[ wlan_nth_beacon_offload.c : 211 ] wlan_nth_beacon_ofld_handler bcn received n_value = %d, nth_ctx->tmr_status = %d, is_nth_beacon_enable = %d, WOW_STATE = %d , host_wake_alwd = %d +4437,iii,[ wlan_nth_beacon_offload_wmi.c : 54 ] wlan_nth_bcn_ctx_deint nth_value = %d, timer_status = %d, is_nth_beacon_enable = %d +4436,,[ wlan_nth_beacon_offload_wmi.c : 93 ] nth beacon vdev notification registration failed +4435,iii,[ wlan_nth_beacon_offload_wmi.c : 104 ] wlan_nth_beacon_to_host_ofld_init nth_value = %d, timer_status = %d, is_ofld_active = %d +4434,iii,[ wlan_nth_beacon_offload_wmi.c : 142 ] wlan_update_value_nth_bcn_ofld nth_value = %d, timer_ststus = %d, is_ofld_active = %d +4438,iiiii,[ wlan_nth_beacon_offload_unit_test.c : 26 ] wlan_nth_bcn_offload_unit_test num_args = %d, args[0] = %d, args[1] = %d, vdev_id = %d, ifUp = %d +4447,Ii,[ csa_offload_main.c : 175 ] _csa_action_frame_handler: wbw_ie 0x%x len: %d +4446,,[ csa_offload_main.c : 389 ] pause disable +4445,II,[ csa_offload_main.c : 40 ] CSA_OFFLOAD_CSA_TIMER_ERROR vdev_id=0x%x state=0x%x +4444,iII,[ csa_offload_main.c : 52 ] CSA_OFFLOAD_CSA_TIMER_ERROR vdev_id = %d csa_proc/bcn_tsf=0x%x curr_tsf=0x%x +4443,iII,[ csa_offload_main.c : 62 ] CSA_OFFLOAD_CSA_TIMER_EXP vdev_id = %d csa_proc=0x%x curr_tsf=0x%x +4442,IIII,[ csa_offload_main.c : 425 ] _csa_vdev_notif_handler: enable:%x pause_until_beacon:%x, csa state:%x, notify:%x + +4441,II,[ csa_offload_main.c : 438 ] csa vdev_start notif,csa ch freq:0x%x, prev csa ch freq:0x%x +4440,iii,[ csa_offload_main.c : 105 ] csa_check_ies_valid chan_valid = %d, tbtt_valid = %d pcl = %d +4439,ii,[ csa_offload_main.c : 297 ] SSID MATCH fail len:%d err_code:%d +4456,II,[ csa_offload_main_wmi.c : 59 ] CSA_OFFLOAD_WMI_CHANSWITCH_RECV cur_ch_freq=0x%x new_ch_freq=0x%x +4455,III,[ csa_offload_main_wmi.c : 210 ] csa handle ie: enable:%x pause_until_beacon:%x, csa state:%x + +4454,iI,[ csa_offload_main_wmi.c : 268 ] CSA_OFFLOAD_CSA_RECV_ERROR_IE vdev_id = %d tbtt_cnt=0x%x +4453,iIi,[ csa_offload_main_wmi.c : 321 ] CSA_OFFLOAD_CSA_RECV_ERROR_IE vdev_id = %d tbtt_cnt=0x%x csa_ies_valid = %d +4452,i,[ csa_offload_main_wmi.c : 352 ] CSA_OFFLOAD_CSA_RECV_ERROR_IE: CSWRAP IE len: %d +4451,I,[ csa_offload_main_wmi.c : 374 ] pause vdev, csa:%x +4450,iIIiII,[ csa_offload_main_wmi.c : 243 ] CSA_OFFLOAD_BEACON_CSA_RECV, XCSA_IE vdev_id = %d tbtt_cnt=0x%x, curr_chan_freq :0x%x, csa_chan %d csa_freq:0x%x, prev csa ch freq:0x%x +4449,iIIiII,[ csa_offload_main_wmi.c : 259 ] CSA_OFFLOAD_BEACON_CSA_RECV, CSA_IE vdev_id = %d tbtt_cnt=0x%x, curr_chan_freq :0x%x, csa_chan %d csa_freq:0x%x, prev csa ch freq:0x%x +4448,iI,[ csa_offload_main_wmi.c : 120 ] CSA_OFFLOAD_WMI_EVENT_ERROR vdev_id = %d csa_proc=0x%x +4457,i,[ obss_offload_api.c : 104 ] bss color: SCAN_SCH_START_ALLOC_FAIL, %d +4480,i,[ bss_color_offload_int.c : 717 ] bss color offload: not support: vdev id:%d +4479,ii,[ bss_color_offload_int.c : 746 ] bss color offload: vdev id:%d, enable=%d +4478,iii,[ bss_color_offload_int.c : 86 ] bss color chg ie: new_bss_color=%d countdown=%d remain_time_us=%d +4477,ii,[ bss_color_offload_int.c : 119 ] bss color he op ie: new_rts_thres=%d curr_rts_thres=%d +4476,i,[ bss_color_offload_int.c : 671 ] bss color: bss clr chg timeout hdlr vdev_id=%d +4475,iii,[ bss_color_offload_int.c : 271 ] bss color he op ie: bcn_bss_color=%d bss_color_disabled=%d curr_bss_color=%d +4474,iii,[ bss_color_offload_int.c : 311 ] bss color: collission detected for different color vdevId=%d cur color=%d last reported color=%d +4473,i,[ bss_color_offload_int.c : 524 ] bss color: scan_evt_handler evt->type = %d +4472,,[ bss_color_offload_int.c : 578 ] BSS COLOR: SCAN_START_COMMAND_FAILED, vdev bss NULL +4471,i,[ bss_color_offload_int.c : 625 ] BSS COLOR: SCAN_START_COMMAND_FAILED, %d +4470,i,[ bss_color_offload_int.c : 646 ] 11d: STOP_COMMAND_FAILED, %d +4469,iii,[ bss_color_offload_int.c : 475 ] bss color: check color collision detection vdev_id=%d vdev_mode=%d col_detect=%d +4468,iii,[ bss_color_offload_int.c : 504 ] bss color: check color collision detection evt_type=%d free_slot_timer=%d det_period=%d +4467,iii,[ bss_color_offload_int.c : 159 ] bss color action: iv_len=%d, category=%d, code=%d +4466,i,[ bss_color_offload_int.c : 764 ] bss color offload: not support: vdev id:%d +4465,ii,[ bss_color_offload_int.c : 821 ] bss color offload: collision det cmd: vdev id:%d, evt_type=%d +4464,iii,[ bss_color_offload_int.c : 827 ] bss color vdev cfg: det_per=%d scan_per=%d expiry_per=%d +4463,i,[ bss_color_offload_int.c : 690 ] bss color: obss clr colli det timeout hdlr vdev_id=%d +4462,ii,[ bss_color_offload_int.c : 373 ] bss color: Send evt report vdevId=%d, tx_status=%d +4461,ii,[ bss_color_offload_int.c : 398 ] bss color: event report fails in wow, vdev id:%d, evt_type:%d +4460,iiII,[ bss_color_offload_int.c : 423 ] bss color: event report,vdev id:%d, evt_type:%d, color bitmap:32to63 0x%x 0to31 0x%x +4459,i,[ bss_color_offload_int.c : 456 ] bss color: restart color collision detection vdev_id=%d +4458,i,[ bss_color_offload_int.c : 434 ] bss color: stop color collision detection vdev_id=%d +4482,i,[ bss_color_offload_unit_test.c : 94 ] bss_color ofld unit test fails: bss_color vdev not exist id:%d +4481,iiii,[ bss_color_offload_unit_test.c : 105 ] bss color ofld unit test: args %d %d %d %d +4484,i,[ obss_offload_priv.c : 64 ] bss color: len wrong:%d +4483,ii,[ obss_offload_priv.c : 73 ] bss color: wrong type:%d, sub:%d +4499,iii,[ wlan_quiet_ie_ap.c : 108 ] QUIET IE AP: timer cb-next evt:%d, cac:%d, paused:%d +4498,I,[ wlan_quiet_ie_ap.c : 132 ] QUIET IE AP: quiet duration time-usec:0x%x +4497,i,[ wlan_quiet_ie_ap.c : 60 ] QUIET IE AP: vdev init vdevId=%d +4496,II,[ wlan_quiet_ie_ap.c : 233 ] QUIET IE AP: not appending quiet IE. time_to_quite_period_start = 0x%x, time_to_bcn_tx = 0x%x +4495,iIIi,[ wlan_quiet_ie_ap.c : 277 ] QUIET IE AP: append quiet IE, tbtt cnt=%d dur=0x%x offset=0x%x len=%d +4494,iiI,[ wlan_quiet_ie_ap.c : 189 ] QUIET IE AP: bi_us=%d diff=%d curr_wal_time=0x%x +4493,iiii,[ wlan_quiet_ie_ap.c : 315 ] QUIET IE AP: start quiet IE: module id=%d, vdev id=%d, dur=%d, beaconing_cnt=%d +4492,i,[ wlan_quiet_ie_ap.c : 326 ] QUIET IE AP: start quiet IE: input duration out of range, duration_us = %d +4491,,[ wlan_quiet_ie_ap.c : 337 ] QUIET IE AP: cancel current quiet IE config +4490,III,[ wlan_quiet_ie_ap.c : 382 ] QUIET IE AP: quiet IE Start time=0x%x Curr_time=0x%x timeout=0x%x +4489,iiii,[ wlan_quiet_ie_ap.c : 456 ] QUIET IE AP: test input num_args=%d vdevId=%d dur=%d cnt=%d +4488,,[ wlan_quiet_ie_ap.c : 465 ] QUIET IE AP: test cfg fail +4487,I,[ wlan_quiet_ie_ap.c : 468 ] QUIET IE AP: test cfg success start_time=0x%x +4486,i,[ wlan_quiet_ie_ap.c : 446 ] QUIET IE AP: test cb status=%d +4485,iii,[ wlan_quiet_ie_ap.c : 425 ] QUIET IE AP: post migration,vdevId:%d, cac:%d, vdevPaused:%d +4512,IiiiiI,[ wlan_quiet_ie_sta.c : 141 ] QUIET IE STA, time-usec:0x%x, vdevId=%d, evt:%d, all_tids_tx_blocked:%d, supend_alwd:%d, period:0x%x +4511,iiiii,[ wlan_quiet_ie_sta.c : 233 ] QUIET IE STA: vdevId=%d, next_start=%d, period=%d, duration=%d, quiet_enabled=%d +4510,,[ wlan_quiet_ie_sta.c : 238 ] QUIET IE STA: cancel current quiet IE config +4509,Ii,[ wlan_quiet_ie_sta.c : 274 ] QUIET IE STA: Quiet period starts in=0x%x, vdevId=%d +4508,iiii,[ wlan_quiet_ie_sta.c : 328 ] QUIET IE STA: test input num_args=%d vdevId=%d dur=%d per=%d +4507,,[ wlan_quiet_ie_sta.c : 333 ] QUIET IE STA: test cfg, vdev is NULL +4506,,[ wlan_quiet_ie_sta.c : 338 ] QUIET IE STA: test cfg, vdev not up or incorrect mode +4505,,[ wlan_quiet_ie_sta.c : 355 ] QUIET IE STA: test cfg fail +4504,,[ wlan_quiet_ie_sta.c : 358 ] QUIET IE STA: test cfg success +4503,IiiiiIi,[ wlan_quiet_ie_sta.c : 397 ] QUIET IE STA: PS SM callback , time-usec:0x%x, vdevId=%d, next_evt:%d, all_tids_tx_blocked:%d, supend_alwd:%d, period:0x%x, sleep = %d +4502,IIIII,[ wlan_quiet_ie_sta.c : 438 ] QUIET IE STA: time_diff_us = 0x%x , current_quite_ie = 0x%x, sum =0x%x, ref_time = 0x%x, curr_ts=0x%x +4501,Ii,[ wlan_quiet_ie_sta.c : 462 ] QUIET IE STA: wake recved in ON period timer:0x%x, nxt_evnt:%d +4500,Ii,[ wlan_quiet_ie_sta.c : 476 ] QUIET IE STA: wake recved in OFF period timer:0x%x, nxt_evnt:%d +4516,,[ wlan_hw_data_filtering.c : 55 ] Add NON ARP BC CCE filter +4515,,[ wlan_hw_data_filtering.c : 59 ] Delete NON ARP BC CCE filter +4514,,[ wlan_hw_data_filtering.c : 111 ] Add NON ICMPv6 MC CCE filter +4513,,[ wlan_hw_data_filtering.c : 115 ] Delete NON ICMPv6 MC CCE filter +4518,iiiiiiii,[ wlan_hw_data_filtering_wmi.c : 66 ] OFFLOAD HDLR CCE UNIT TEST CMD: num_args=%d vdevId=%d args =%d %d %d %d %d %d +4517,iiiiiiiii,[ wlan_hw_data_filtering_wmi.c : 243 ] OFLD CMD: num_params=%d proto=%d proto_type =%d data_len = %d off=%d data[0]=%d data[1]=%d %d %d +4520,i,[ offload_unit_test.c : 135 ] OFFLOAD HDLR UNIT TEST: status = %d +4519,iii,[ offload_unit_test.c : 180 ] Offload unit test input: vdevid:%d, group=%d, type=%d +4528,ii,[ wlan_opmode.c : 76 ] WLAN_OPMODE_SET_PMAC_LATENCY: mac_id=%d, opmode_latency=%d +4527,ii,[ wlan_opmode.c : 85 ] WLAN_OPMODE_SET_PMAC_LATENCY: mac_id=%d, opmode_latency=%d [!WAL_EOK returned] +4526,iiii,[ wlan_opmode.c : 142 ] WLAN_OPMODE_UPDATE_PMAC_LATENCY: mac_id=%d, final_latency=%d, power_state=%d, is_pmac_idle=%d +4525,i,[ wlan_opmode.c : 259 ] WLAN_OPMODE_VDEV_FREE: vdev_id=%d +4524,i,[ wlan_opmode.c : 243 ] WLAN_OPMODE_VDEV_INIT: vdev_id=%d +4523,i,[ wlan_opmode.c : 250 ] WLAN_OPMODE_VDEV_INIT: vdev_id=%d [!A_OK returned] +4522,iI,[ wlan_opmode.c : 157 ] WLAN_OPMODE_WAL_PDEV_EVT: pmac_id=%d, event=0x%x +4521,ii,[ wlan_opmode.c : 182 ] WLAN_OPMODE_VDEV_EVT: vdev_id=%d, event=%d +4535,ii,[ wlan_pm_arbiter.c : 363 ] wlan_pm_arbiter_dump_wake_stats: mac_id=%d, ModuleID=%d +4534,iii,[ wlan_pm_arbiter.c : 348 ] wlan_pm_arbiter_req_migration: vdevid=%d, old_mac_id=%d, new_mac_id=%d +4533,IIIII,[ wlan_pm_arbiter.c : 209 ] PS_STA_PM_ARB_RESOLVE: mac/power_state/request/mod_id = 0x%x bitmask[0]=0x%x, bitmask[1]=0x%x, bitmask[2]=0x%x, bitmask[3]=0x%x +4532,ii,[ wlan_pm_arbiter.c : 518 ] wake_monitor mac:%d win_len:%dms +4531,iiiiii,[ wlan_pm_arbiter.c : 541 ] wake_monitor mac:%d w_list mod:%d vdev:%d total_time:%dms total_cnt:%d max_time:%dms +4530,iiiiii,[ wlan_pm_arbiter.c : 562 ] wake_monitor mac:%d s_list mod:%d vdev:%d total_time:%dms total_cnt:%d max_time:%dms +4529,iii,[ wlan_pm_arbiter.c : 299 ] wlan_pm_arbiter_vdev_migration: vdevid=%d, old_mac_id=%d, new_mac_id=%d +4542,iiiIi,[ wlan_powersave_ap.c : 2370 ] AP_PS_DBGID_DELIVER_CAB vdev_id = %d Tid = %d NumMPDU = %d Flags = 0x%x RetryOther = %d +4541,i,[ wlan_powersave_ap.c : 2321 ] AP_PS_DBGID_CAB_FINISH vdev_id = %d +4540,i,[ wlan_powersave_ap.c : 2464 ] AP_PS_DBGID_START_CAB vdev_id = %d +4539,i,[ wlan_powersave_ap.c : 3055 ] AP_PS_DBGID_VDEV_CREATION_FAILURE AP PS:vdev_id = %d vdev alloc failed +4538,Ii,[ wlan_powersave_ap.c : 3185 ] AP_PS_DBGID_HOST_TX_PAUSE vdev_map = %0x, pause: %d +4537,ii,[ wlan_powersave_ap.c : 2232 ] wlan_ps_ap_send_message: is_vdev_valid:%d, is_command_data_valid:%d +4536,,[ wlan_powersave_ap.c : 2243 ] wlan_ps_ap_send_message: null cmd_data +4562,Iii,[ wlan_powersave_sta.c : 964 ] wlan_ps_sta_check_data_stall_detected: current_index=%0x, notxrx_count=%d, notxrx_max_count=%d +4561,ii,[ wlan_powersave_sta.c : 3349 ] wlan_ps_sta_check_long_inactive_duration: is_enabled=%d, duration_ms=%d +4560,IIIIII,[ wlan_powersave_sta.c : 3230 ] wlan_ps_sta_check_vendor_specific_ie: AP: specific_code=%x:%x:%x:%x:%x:%x +4559,iiiiiI,[ wlan_powersave_sta.c : 2660 ] PS_STA_PSPOLL_SEQ_DONE vdev_id = %d QueueTime = %d CompleteTime = %d ResponseTime = %d ResponseDuration = %d ResponseFrameCtrl/QosCtrl = 0x%x +4558,,[ wlan_powersave_sta.c : 1516 ] sta_handle POOL ALLOC FAILURE +4557,iii,[ wlan_powersave_sta.c : 1970 ] PS_STA_DELIVER_EVENT vdev_id = %d EventType = %d Statue = %d +4556,ii,[ wlan_powersave_sta.c : 3408 ] wlan_ps_sta_enable_disable_dbg_logs vdev_id = %d, enable = %d +4555,I,[ wlan_powersave_sta.c : 3387 ] wlan_ps_sta_force_data_stall_event: flags_3=0x%x +4554,iI,[ wlan_powersave_sta.c : 2923 ] STA PS: wlan_ps_sta_health_monitor_timeout: vdev_id=%d sta_flags=0x%X +4553,,[ wlan_powersave_sta.c : 3324 ] wlan_ps_sta_long_inactive_monitor_timeout: start timer again +4552,iI,[ wlan_powersave_sta.c : 1803 ] wlan_ps_sta_pause: vdev_id=%d, timeout_us=%u +4551,iiIi,[ wlan_powersave_sta.c : 1881 ] PS_STA_PSPOLL_ALLOW vdev_id = %d Allow = %d Flags = 0x%x Time = %d +4550,iiIIII,[ wlan_powersave_sta.c : 1089 ] PS_STA_RESYNC vdev_id = %d VDevUpCnt = %d IsBTConnected = 0x%x Flags = 0x%x VDevSubMode = 0x%x BitMap = 0x%x +4549,ii,[ wlan_powersave_sta.c : 2530 ] PS_STA_COEX_MODE vdev_id = %d Enable = %d +4548,ii,[ wlan_powersave_sta.c : 2541 ] PS_STA_WOW_MODE vdev_id = %d Enable = %d +4547,iII,[ wlan_powersave_sta.c : 2063 ] PS_STA_SET_PARAM vdev_id = %d param = 0x%x value = 0x%x +4546,i,[ wlan_powersave_sta.c : 777 ] STA PS vdev_id = %d, No buffers available for null frames +4545,ii,[ wlan_powersave_sta.c : 909 ] PS_STA_INACTIVITY_INFO ITO picked = %d us, current ITO = %d, +4544,i,[ wlan_powersave_sta.c : 1851 ] wlan_ps_sta_unpause: vdev_id=%d +4543,Iiii,[ wlan_powersave_sta.c : 2845 ] STA PS: VOWiFi: voip_notify: vdev_id=%u, vo_call_start=%d, intvl_ms=%d media_quality=%d +4573,ii,[ wlan_powersave_sta_sm.c : 1133 ] wlan_ps_sta_data_activity_pending: vdev_id=%d, inactive_time_us=%d +4572,,[ wlan_powersave_sta_sm.c : 1365 ] wlan_ps_sta_state_active_entry: cancel long_inactive_monitor_timer +4571,ii,[ wlan_powersave_sta_sm.c : 1889 ] wlan_ps_sta_state_pause_event: vdev id = %d, pause_stat_rx_frms_leaked = %d +4570,iii,[ wlan_powersave_sta_sm.c : 4008 ] SPEC_PSPOLL_TIMEOUT: vdevid=%d, spec=%d, timeout=%d +4569,iiii,[ wlan_powersave_sta_sm.c : 3453 ] sleep_awake_event_rx: MD=%d, pspoll_count=%d, is_qos_null:%d, nodata_count=%d +4568,iiiiIi,[ wlan_powersave_sta_sm.c : 3462 ] sleep_awake_event_rx: is_qos_null:%d, wakeup_dur=%d, nodata_cnt=%d, nodata_max_cnt=%d, flags=0x%x, pspoll_cnt=%d +4567,,[ wlan_powersave_sta_sm.c : 3706 ] total_spec_pspoll_count reaches MAX: reset it +4566,,[ wlan_powersave_sta_sm.c : 2631 ] wlan_ps_sta_state_active_entry: start long_inactive_monitor_timer +4565,iIIiI,[ wlan_powersave_sta_sm.c : 789 ] wlan_ps_sta_tx_sent_send_nullfunc: vdevid=%d, force_ps=0X%x, sta_handle=%p, peer_type=%d, blocked_tids=0X%x +4564,ii,[ wlan_powersave_sta_sm.c : 2385 ] PS_STA_SPECPOLL_TIMER_STARTED vdev_id = %d SpecPsPollNoDataCnt = %d +4563,i,[ wlan_powersave_sta_sm.c : 2398 ] PS_STA_SPECPOLL_TIMER_STOPPED: vdev_id = %d +4626,iiiiiii,[ wlan_smps.c : 2417 ] STA_SMPS_VHT_OP_MODE_NOTIF_PEER_COMPLETE : vdevid = %d peerid = %d completion_status = %d peer_smps_frames_sent_mask = %d vedevNotif = %dsm_power_control = %d, vcLastSMpwrCntrl = %d +4625,i,[ wlan_smps.c : 2486 ] SMPS Action TX frame not sent, attemps:%d +4624,ii,[ wlan_smps.c : 2493 ] SMPS action frame attempt mask %d smps_power_control %d +4623,,[ wlan_smps.c : 2659 ] SMPS_AP Action frame could not send BW OMN notification connection is not VHT +4622,i,[ wlan_smps.c : 2700 ] SMPS Action TX frame not sent, attemps:%d +4621,iii,[ wlan_smps.c : 2547 ] STA_SMPS_SEND_VHT_OPMODE_NOTIF_FRAME_TO_PEER vdevid = %d peerid = %d ret_value = %d +4620,i,[ wlan_smps.c : 4362 ] SMPS Build Operation mode notification IE: enable = %d +4619,,[ wlan_smps.c : 3501 ] wlan_smps_cfg_change_timeout + +4618,iii,[ wlan_smps.c : 3643 ] wlan_smps_cfg_notify_done: status:%d, stage:%d->0 smps_cfg_notify_compl_args.ctxt=%d +4617,iiiIi,[ wlan_smps.c : 3677 ] wlan_smps_chainmask_change_handle_done: status:%d, stage:%d->0,smps_cfg_notify_compl_args.ctxt=%d cur_chain_h16/next_chain=0x%x,smstate:%d +4616,,[ wlan_smps.c : 3332 ] wlan_smps_vc_cfg_notify queued cfg + +4615,iI,[ wlan_smps.c : 4386 ] SMPS get Operation mode notification IE length %d %p +4614,ii,[ wlan_smps.c : 1299 ] wlan_smps_get_peer_bandwidth channel_width = %d, peer_bw = %d +4613,ii,[ wlan_smps.c : 2788 ] STA_SMPS_CREATE_NON_STA_INSTANCE vdevid = %d smps_handle = %d +4612,ii,[ wlan_smps.c : 2799 ] STA_SMPS_DELETE_NON_STA_INSTANCE : vdevid = %d smps_handle = %d +4611,iii,[ wlan_smps.c : 2052 ] STA_SMPS_DTIM_CHMASK_UPDATE_AWAKE : tx_chainmask = %d rx_chainmask = %d orig_rx_chainmask = %d +4610,ii,[ wlan_smps.c : 2057 ] DTIM_UPDATE_CHAIN_ON_AWAKE: update chain in single chain, hwchain=%d, new=%d +4609,i,[ wlan_smps.c : 2024 ] wlan_smps_pdev_update_dtim_chmask_on_sleep RSSI_INDICATION = %d +4608,I,[ wlan_smps.c : 3602 ] wlan_smps_set_current_cfg vdev level notification hence no update vdev_map = 0x%x +4607,i,[ wlan_smps.c : 2317 ] STA_SMPS_CREATE_STA_INSTANCE : sta_handle = %d +4606,i,[ wlan_smps.c : 2340 ] STA_SMPS_DELETE_STA_INSTANCE : sta_handle = %d +4605,,[ wlan_smps.c : 1451 ] SMPS_STA Action frame could not send BW OMN/OMI notification connection is not VHT +4604,,[ wlan_smps.c : 1496 ] SMPS_STA Action frame could not send BW OMN/OMI notification wrong rx NSS +4603,,[ wlan_smps.c : 1506 ] SMPS_STA Action frame could not send BW OMN/OMI notification wrong tx NSS +4602,,[ wlan_smps.c : 1511 ] wlan_smps_sta_send_action_frame IEEE80211_NODE_HE +4601,ii,[ wlan_smps.c : 1549 ] SMPS_STA Action frame send power_control: %d ret_value:%d +4600,iIIiIi,[ wlan_smps.c : 4088 ] wlan_smps_vc_cfg_notify : arg %d req rx_chainmask = 0x%x currVCrxnss = 0x%xnew_channel_width = %d , updatecfg= 0x%x, is_vdev_notif = %d +4599,I,[ wlan_smps.c : 4102 ] SMPS not supported on current channel 0x%x +4598,iIi,[ wlan_smps.c : 4110 ] wlan_smps_vc_cfg_notify vc_handle->cfg_change_stage=%d, new_cfg.update_cf=%x, new_cfg.vdev_map = %d +4597,,[ wlan_smps.c : 4124 ] wlan_smps_rejecting_queuing, something is already queued + +4596,Ii,[ wlan_smps.c : 4147 ] wlan_smps_vc_cfg_notify queued cb = 0x%x, ret = %d +4595,i,[ wlan_smps.c : 4157 ] invalid smps cfg notification value new_cfg.channel_width = %d +4594,,[ wlan_smps.c : 4197 ] SMPS_CFG_CHANGE_NOTIFY: rejected due to duplicate request +4593,IiI,[ wlan_smps.c : 4282 ] SMPS_CFG_CHANGE_NOTIFY: ONLY CFG PARAM CHANGE mhz: 0x%x, ret = %d, Notification mask = 0x%x +4592,Iiiii,[ wlan_smps.c : 4293 ] SMPS_CFG_CHANGE_NOTIFY: mhz: 0x%x, ret = %d, prev_vc_rx_chain_mode: %d, next_vc_rx_chain_mode: %d, chain_mask_change_stage: %d +4591,I,[ wlan_smps.c : 4295 ] SMPS_CFG_CHANGE_NOTIFY: Invalid VC handle %p +4590,iiIIII,[ wlan_smps.c : 3933 ] invalid smps cfg notification requested ul_disablemu = %d, channel_width = %d rx_chainmask = 0x%x, tx_chainmask = 0x%x, update cfg = %x, vdev map = %x +4589,I,[ wlan_smps.c : 4012 ] vdev level notification is requested = 0x%x +4588,iiiii,[ wlan_smps.c : 891 ] STA_SMPS_VC_ACTION_FRAME_TX_COMPL_OLD_DBG : power control = %d vc_handle->last_frame_sm_pwr_ctrl = %d completion status = %d current_state = %d vc_handle->cfg_change_stage = %d +4587,iI,[ wlan_smps.c : 895 ] STA_SMPS_VC_ACTION_FRAME_TX_COMPL Additional params: prev_forced_mode = %d channel mhz = 0x%x +4586,,[ wlan_smps.c : 993 ] STA_SMPS_VC_ACTION_FRAME_TX_COMPL : incorrect state readjustment + +4585,,[ wlan_smps.c : 1024 ] STA_SMPS_VC_ACTION_FRAME_TX_COMPL : fallback on legacy SMPS configuration + +4584,i,[ wlan_smps.c : 1086 ] STA_SMPS_VC_ACTION_FRAME_TX_COMPL : action_valid = %d + +4583,,[ wlan_smps.c : 1098 ] wlan_smps_vc_cfg_notify queued cfg + +4582,i,[ wlan_smps.c : 2882 ] STA_SMPS_CREATE_VIRTUAL_CHAN_INSTANCE : vc_handle = %d +4581,i,[ wlan_smps.c : 2958 ] STA_SMPS_DELETE_VIRTUAL_CHAN_INSTANCE : vc_handle = %d +4580,ii,[ wlan_smps.c : 340 ] STA_SMPS_VIRTUAL_CHAN_SMPS_START : vc_handle = %d, vc_handle->enabled = %d +4579,ii,[ wlan_smps.c : 357 ] SMPSVC CHNL START : STA_SMPS_INVALID_SM_EVENT event = %d dynamicSMPSSupported = %d +4578,ii,[ wlan_smps.c : 387 ] STA_SMPS_VIRTUAL_CHAN_SMPS_STOP : vc_handle = %d, vc_handle->enabled = %d +4577,iiiiii,[ wlan_smps.c : 415 ] wlan_smps_virtual_chan_update : vc_handle = %d, vc_handle->enabled = %d,vc_handle->cfg_notification_mode = %d, vc_handle->fw_forced_mode =%d , vc_handle->host_forced_mode = %d, smps_cur_state = %d +4576,,[ wlan_smps.c : 449 ] wlan_smps_virtual_chan_update : smps action frame sent +4575,,[ wlan_smps.c : 444 ] wlan_smps_virtual_chan_update : smps restarted +4574,i,[ wlan_smps.c : 1704 ] wlan_smps_virtual_chan_update_dtim_chmask WAL_PM_MAC_PARAM_RSSI_INDICATION = %d +4627,ii,[ wlan_smps_sm.c : 186 ] SMPS_STATE_STATIC_EVENT: chain: %d, dropped ev:%d +4629,ii,[ wlan_powersave_sta_wmi.c : 209 ] PS_STA_UAPSD_AUTO_TRIG VdevID = %d NumAC = %d +4628,iiiiii,[ wlan_powersave_sta_wmi.c : 230 ] PS_STA_UAPSD_AUTO_TRIG_PER_AC vdev_id = %d WMM_AC = %d UserPriority = %d SrvIntl = %d SuspIntl = %d DelayIntl = %d +4651,ii,[ wlan_twt.c : 683 ] wlan_twt_wmi_add_dialog: vdev_id=%d, id=%d +4650,iii,[ wlan_twt.c : 814 ] wlan_twt_wmi_add_dialog_complete_event: vdev=%d, id=%d, status=%d +4649,ii,[ wlan_twt.c : 1454 ] wmi_twt_btwt_invite_sta: vdev_id=%d, id=%d +4648,III,[ wlan_twt.c : 1461 ] AP TWT: Cant find peer: lsb_mac=%x:%x:%x +4647,III,[ wlan_twt.c : 1469 ] wlan_twt_wmi_btwt_invite_sta: WMI_PEER_TYPE_SELF: lsb_mac=%x:%x:%x +4646,iii,[ wlan_twt.c : 1494 ] wlan_twt_wmi_btwt_invite_sta_complete_event: vdev=%d, id=%d, status=%d +4645,ii,[ wlan_twt.c : 1537 ] wmi_twt_btwt_remove_sta: vdev_id=%d, id=%d +4644,III,[ wlan_twt.c : 1544 ] AP TWT: Cant find peer: lsb_mac=%x:%x:%x +4643,III,[ wlan_twt.c : 1552 ] wlan_twt_wmi_btwt_remove_sta: WMI_PEER_TYPE_SELF: lsb_mac=%x:%x:%x +4642,iii,[ wlan_twt.c : 1577 ] wlan_twt_wmi_btwt_remove_sta_complete_event: vdev=%d, id=%d, status=%d +4641,iii,[ wlan_twt.c : 900 ] wlan_twt_wmi_del_dialog: vdev_id=%d, id=%d, b_twt_persistence=%d +4640,iii,[ wlan_twt.c : 963 ] wlan_twt_wmi_del_dialog_complete_event: vdev=%d, id=%d, status=%d +4639,iI,[ wlan_twt.c : 360 ] wlan_twt_wmi_disable: pdev_id=%d, flags=0x%x +4638,i,[ wlan_twt.c : 473 ] wlan_twt_wmi_disable_complete_event: pdev_id=%d +4637,iiI,[ wlan_twt.c : 210 ] wlan_twt_wmi_enable: pdev_id=%d, sta_cong_timer_ms=%d, pdev-flags=0x%x +4636,ii,[ wlan_twt.c : 266 ] wlan_twt_wmi_enable_complete_event: pdev_id=%d, status=%d +4635,iiii,[ wlan_twt.c : 1320 ] wlan_twt_wmi_nudge_dialog: vdev_id=%d, id=%d, suspend_duration_ms=%d, next_twt_size=%d +4634,iiiI,[ wlan_twt.c : 1394 ] wlan_twt_wmi_nudge_dialog_complete_event: vdev=%d, id=%d, status=%d, next_twt=0x%x +4633,ii,[ wlan_twt.c : 1019 ] wlan_twt_wmi_pause_dialog: vdev_id=%d, id=%d +4632,iii,[ wlan_twt.c : 1079 ] wlan_twt_wmi_pause_dialog_complete_event: vdev=%d, id=%d, status=%d +4631,iii,[ wlan_twt.c : 1143 ] wlan_twt_wmi_resume_dialog: vdev_id=%d, id=%d, next_twt_size=%d +4630,iii,[ wlan_twt.c : 1215 ] wlan_twt_wmi_resume_dialog_complete_event: vdev=%d, id=%d, status=%d +4652,iii,[ wlan_twt_protocol.c : 240 ] wlan_twt_action_frame_handler: cat=%d, act=%d, len=%d +4657,III,[ wlan_twt_ap.c : 279 ] AP TWT: Cant find peer lsb_mac=%x:%x:%x +4656,i,[ wlan_twt_ap.c : 580 ] AP TWT: Vdev id = %d not TWT enabled +4655,i,[ wlan_twt_ap.c : 996 ] AP TWT: Vdev id = %d not TWT enabled +4654,i,[ wlan_twt_ap.c : 747 ] AP TWT: peer id = %d not TWT enabled +4653,i,[ wlan_twt_ap.c : 955 ] AP TWT: Vdev id = %d not TWT enabled +4659,iii,[ wlan_powersave_sta_unit_test.c : 272 ] STA PS ITO pattern %d ito %d ms specWakeup %d ms +4658,ii,[ wlan_powersave_sta_unit_test.c : 303 ] STA PS ITO config ito=%d ms specWakeup=%d ms +4664,iiiiiiii,[ wlan_twt_unit_test.c : 862 ] wlan_twt_unit_test: vdev_id=%d, num_args=%d, type=%d, args:%d-%d-%d-%d-%d +4663,i,[ wlan_twt_unit_test.c : 918 ] wlan_twt_unit_test: wrong num_args==%d, for WLAN_TWT_TEST_TYPE_ADD +4662,i,[ wlan_twt_unit_test.c : 865 ] vdev == NULL: %d +4661,i,[ wlan_twt_unit_test.c : 866 ] !vdev->ifUp, %d +4660,III,[ wlan_twt_unit_test.c : 533 ] AP TWT: Cant find peer: lsb_mac=%x:%x:%x +4665,II,[ wlan_pps.c : 124 ] PPS wmi_set_vdev_pkt_pwr_save: old:0x%x, new:0x%x +4810,,[ wlan_rtt.c : 11240 ] wlan_internal_disable_responder +4809,,[ wlan_rtt.c : 726 ] Event buffer allocation for cancel measurement response failed +4808,iii,[ wlan_rtt.c : 4695 ] wlan_oem_rtt_measreq_hdl: client %d running. cannot new req from client: %d. So Dropping req_id: %d +4807,i,[ wlan_rtt.c : 4718 ] wlan_oem_rtt_measreq_hdl: Request with id %d won't be served because of an error +4806,i,[ wlan_rtt.c : 4750 ] wlan_oem_rtt_measreq_hdl: asm_req status %d would be served from call back due to NACK +4805,IIII,[ wlan_rtt.c : 11016 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4804,IIII,[ wlan_rtt.c : 11076 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4803,IIII,[ wlan_rtt.c : 11087 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4802,iIi,[ wlan_rtt.c : 1081 ] wlan_rtt_band_change_req_init_cb: event: %d init_ctxt: 0x%08x rtt_2g: %d +4801,IIII,[ wlan_rtt.c : 1117 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4800,,[ wlan_rtt.c : 3302 ] RTT_CALL_FLOW: WLAN_RTT_BEACON_RX +4799,iiiiiiii,[ wlan_rtt.c : 4972 ] wlan_rtt_burst_instance_done: num_burst_done:%d total_bursts:%d curr_state:%d burst_duration:%d, index:%d ftm1_done:%d num_meas:%d ftm_per_burst:%d +4798,,[ wlan_rtt.c : 5079 ] Wait for NAN module to finish sending NAN ranging termination frame +4797,iI,[ wlan_rtt.c : 11359 ] wlan_rtt_cancel_all_rtt_operation attached to vdev_id: %d p_pdev_rtt_ctxt: 0x%08x +4796,iiiiii,[ wlan_rtt.c : 3892 ] wlan_rtt_cap_msg_req_hdl: client_id: %d Req:%d Reqid:%d Major:%d Minor:%d Revision:%d +4795,,[ wlan_rtt.c : 3907 ] Event buffer allocation for wlan_rtt_cap_msg_req response failed +4794,iIII,[ wlan_rtt.c : 7526 ] RTT_CHANNEL_SWITCH_GRANT ev_id = %d p_chnl_switch_ctxt = 0x%x p_owner = 0x%x p_rtt_ctxt = 0x%x +4793,,[ wlan_rtt.c : 3254 ] RTT_CALL_FLOW: WLAN_RTT_DFS_EXIT +4792,IIII,[ wlan_rtt.c : 10708 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4791,ii,[ wlan_rtt.c : 3420 ] wlan_rtt_dfs_chan_init_handler rtt_ctxt->chnl_switch_ctxt.cb_fn %d rtt_ctxt->chnl_switch_ctxt.owner%d +4790,iII,[ wlan_rtt.c : 3447 ] RTT_CHANNEL_DFS_SWITCH_HDL ev = %d sw_ctxt->arg = 0x%08x sw_ctxt->cb_fn 0x%08x +4789,,[ wlan_rtt.c : 3236 ] RTT_CALL_FLOW: WLAN_RTT_DFS_TIMEOUT_HANDLER +4788,iiii,[ wlan_rtt.c : 7750 ] RTT_CHANNEL_SWITCH_REQ module_id %d duration = %d channel = %d priority = %d +4787,I,[ wlan_rtt.c : 1991 ] wlan_rtt_free_init_ctxt() usage flags = 0x%x +4786,II,[ wlan_rtt.c : 2028 ] Unregistered wlan_rtt_vdev_notify_handler() for init context vdev = 0x%08x status = 0x%x +4785,I,[ wlan_rtt.c : 6659 ] wlan_rtt_ftm_delta_timeout() Ignore ctxt freed %p +4784,IIiiiii,[ wlan_rtt.c : 6511 ] wlan_rtt_ftm_init_burst_periodic_timeout: dest_mac:%x%x is_multiburst(%d) is_repetitive_ss(%d) current_burst:%d total_bursts:%d curr_state: %d +4783,iII,[ wlan_rtt.c : 6567 ] wlan_rtt_ftm_init_burst_periodic_timeout: ERR: Some other request is in progress; skip current burst %d for dest_mac:%x%x +4782,II,[ wlan_rtt.c : 6599 ] Init PTSF fired resp_tsf_h = 0x%x resp_tsf_l = 0x%x +4781,iii,[ wlan_rtt.c : 6483 ] wlan_rtt_ftm_resp_burst_timeout: ftm_state: %d num_burst_exp: %d no_burst_count: %d +4780,II,[ wlan_rtt.c : 11322 ] wlan_rtt_get_clear_stats ranging_dur: %x resp_dur: %x +4779,iii,[ wlan_rtt.c : 5323 ] wlan_rtt_get_ftm_chnl_code bw:%d preamble:%d phy_mode:%d +4778,,[ wlan_rtt.c : 5776 ] RTT_ERROR_REPORT :RTT_RESP_CTXT_EXIST +4777,,[ wlan_rtt.c : 5807 ] RTT_ERROR_REPORT :RTT_RESP_REQ_ACCEPT +4776,,[ wlan_rtt.c : 5817 ] RTT_ERROR_REPORT :RTT_RESP_BUSY +4775,iiiIii,[ wlan_rtt.c : 2516 ] wlan_rtt_init_update_channel mhz=%d bw=%d preamble=%d rate_info=0x%x chnl_format=%d error_code=%d +4774,IIiIIiII,[ wlan_rtt.c : 3705 ] wlan_rtt_init_handler: Starting initiator with mac_addr = %08x%02x init_idx = %d init_ctxt_usage_flags = 0x%x pmac: 0x%08x mac_id: %d vdev: 0x%08x rate_info: 0x%x +4773,,[ wlan_rtt.c : 3710 ] RTT request on a different vdev than the one set during channel change +4772,IiI,[ wlan_rtt.c : 3732 ] Registered wlan_rtt_vdev_notify_handler() for init context : vdev = 0x%08x vdevid = %d status = 0x%x +4771,iii,[ wlan_rtt.c : 7429 ] vdev mac id(%d) not same as pmac mac id(%d): change PM lock & set mac address: %d +4770,iiiiI,[ wlan_rtt.c : 7450 ] Channel Granted(Initiator): RTT requested freq: %d phymode: %d Grant came on freq: %d phymode: %d chan_flags: 0x%04x +4769,iII,[ wlan_rtt.c : 7483 ] Downgraded the BW: New bw: %d chnl_format: %u rate_info: %u +4768,II,[ wlan_rtt.c : 2129 ] wlan_rtt_init_scheduler => curr_init:0x%x init_ctxt_usage_flags:0x%x +4767,ii,[ wlan_rtt.c : 2164 ] wlan_rtt_init_scheduler => diff1:%d diff2:%d +4766,i,[ wlan_rtt.c : 2194 ] wlan_rtt_init_scheduler => next_mb_slot_index:%d +4765,i,[ wlan_rtt.c : 2239 ] wlan_rtt_init_scheduler: Skipping initiator with index %d as it may creep into next multiburst start time +4764,iiii,[ wlan_rtt.c : 2256 ] wlan_rtt_init_scheduler => index:%d curr_index:%d schedule_timeout:%d next_mb_slot_index: %d +4763,iiiiiiiI,[ wlan_rtt.c : 2838 ] RTT_MEAS_REQ_HEAD ch_mhz = %d, center_freq1 = %d ch_mode = %d sta_num:%d, max_reg_power: %d antenna_max: %d, max_tx_power: %d, ch_flags: 0x%04x +4762,IIIII,[ wlan_rtt.c : 10387 ] Received FTMR resp_tsf_h = 0x%x resp_tsf_l = 0x%x curslot_slot_idx: 0x%x cur_diff: 0x%x resp_ref_tsf: 0x%x +4761,III,[ wlan_rtt.c : 10404 ] wlan_rtt_is_burst_in_slot: diff_tesf: %u next_burst_tsf: %u cur_tsf: %u +4760,i,[ wlan_rtt.c : 774 ] wlan_rtt_is_wmi_event_to_send: invalid client_id (%d) +4759,IIII,[ wlan_rtt.c : 7810 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4758,iiiIIii,[ wlan_rtt.c : 7865 ] wlan_rtt_local_send()status: %d pmac_mac_id: %d vdev_mac_id: %d selfgen_chm: 0x%x abf: 0x%08x peer_type: %d vdev_id: %d +4757,IIIII,[ wlan_rtt.c : 5299 ] RTT_FTM_PARAM_INFO arg1 = 0x%x arg2 = 0x%x arg3 = 0x%x arg4 = 0x%x arg5 = 0x%x +4756,iiii,[ wlan_rtt.c : 2983 ] RTT_MEAS_REQ_HEAD req_id = %d num_chan = %d sps = %d client: %d +4755,iIii,[ wlan_rtt.c : 7173 ] wlan_rtt_measurement_report: client_id: %d curr_init_ctxt:0x%08x size: %d freq: %d +4754,iII,[ wlan_rtt.c : 10551 ] nan_ranging_terminate_completion_handler: req_id: %d init_ctxt: 0x%08x wait_status: %x +4753,i,[ wlan_rtt.c : 10574 ] nan_ranging_terminate_completion_handler for req_id: %d is not processed !!! +4752,iiii,[ wlan_rtt.c : 8926 ] RTT Null frame Tx status: %d tx_fail_count: %d num_meas: %d terminate: %d +4751,iii,[ wlan_rtt.c : 8945 ] Null frame ack handler: tx_fail_count: %d, num_meas:%d, Tx fail thresold:%d +4750,I,[ wlan_rtt.c : 8670 ] RTT add_random_mac_addr failed. status: 0x%x +4749,i,[ wlan_rtt.c : 4182 ] _wlan_wmi_oem_req: Non TLV format msg received; tlv_head: %d +4748,iii,[ wlan_rtt.c : 4199 ] wlan_wmi_oem_req: INFO: OEM Req received with sub_type:%d, req_id:%d client: %d +4747,ii,[ wlan_rtt.c : 3195 ] wlan_rtt_pm_arb_req(): mac_id: %d state: %d +4746,IIIIII,[ wlan_rtt.c : 5670 ] wlan_rtt_populate_resp_ftm_param: next_sched_tsf: %u resp_ref_tsf: %u partial_tsf: %u diff_tsf: %u current_resp_tsf64: 0x%08x%08x +4745,IIIIII,[ wlan_rtt.c : 5699 ] wlan_rtt_populate_resp_ftm_param: next_sched_tsf: %u diff_tsf: %u nearest_tsf: %u resp_partial_tsf: %u next_burst_tsf: 0x%08x%08x +4744,II,[ wlan_rtt.c : 5754 ] wlan_rtt_populate_resp_ftm_param: ftm_param.burst_period: %u resp_param_info.burst_period: %u +4743,Iii,[ wlan_rtt.c : 522 ] wlan_rtt_proceed: init_ctxt: 0x%08x wait_status: %d wait_nan_module: %d +4742,iIIIIIIII,[ wlan_rtt.c : 2784 ] RTT_MEAS_REQ_BODY idx = %d dest_mac_0to31 = 0x%x dest_mac_32to47 = 0x%x sppof_bssid_0to31 = 0x%x spoof_bssid_32to47 = 0x%x control_inf = 0x%x meas_inf = 0x%x meas_params1 = 0x%x meas_params2 = 0x%x +4741,IIIII,[ wlan_rtt.c : 10655 ] wlan_rtt_ranging_negotiation_status_notif_handler: timeout_us:%u burst_start_time_h:%u burst_start_time_l:%u StartTsf:%u curr_time%u +4740,iIi,[ wlan_rtt.c : 10682 ] wlan_rtt_ranging_negotiation_status_notif_handler: ranging_ind_data->RangingParams.ReqId %d init_ctxt 0x%08x event_handled %d +4739,IIII,[ wlan_rtt.c : 10832 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4738,iii,[ wlan_rtt.c : 7350 ] wlan_rtt_resp_chan_switch_hdl() ev_id = %d ftm_state:%d is_ftmr_pending:%d +4737,II,[ wlan_rtt.c : 3161 ] Unregistered wlan_rtt_vdev_notify_handler() for resp context vdev = 0x%08x status = 0x%x +4736,IIIII,[ wlan_rtt.c : 10344 ] wlan_rtt_resp_free_existing_slot 0x%x 0x%x 0x%x dest_mac:%08x%02x +4735,iiI,[ wlan_rtt.c : 6410 ] wlan_rtt_resp_ftm1_timeout: ftm_state: %d asap: %d resp_ctxt: 0x%08x +4734,IIIIIIII,[ wlan_rtt.c : 10330 ] wlan_rtt_resp_get_free_slot 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x dest_mac:%08x%02x +4733,ii,[ wlan_rtt.c : 6256 ] wlan_rtt_resp_init:current session is active: session_index: %d slot: %d +4732,ii,[ wlan_rtt.c : 6267 ] wlan_rtt_resp_init: Received a frame which we are not in slot send FTM stop frame. session_index: %d slot: %d +4731,iii,[ wlan_rtt.c : 6138 ] wlan_rtt_resp_init_body: session_active: %d init_new_session: %d ftm_state: %d +4730,iii,[ wlan_rtt.c : 6142 ] wlan_rtt_resp_init_body: asap: %d ftm_state: %d session_active: %d +4729,iiI,[ wlan_rtt.c : 6176 ] wlan_rtt_resp_init_body:ftm_state: %d asap: %d resp_ctxt: 0x%08x +4728,III,[ wlan_rtt.c : 6196 ] wlan_rtt_resp_init_body: ftm_state: %u asap: %u resp_ctxt: 0x%08x +4727,IiII,[ wlan_rtt.c : 5947 ] Registered wlan_rtt_vdev_notify_handler() for resp context vdev: 0x%08x vdev_type: %d pmac: 0x%08x status: 0x%x +4726,IIII,[ wlan_rtt.c : 6073 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4725,ii,[ wlan_rtt.c : 6088 ] wlan_rtt_resp_init_new_session: slot: %d param_info.status: %d +4724,iiI,[ wlan_rtt.c : 6097 ] END_FTM_INVALID_REQUEST: ftm_state: %d asap: %d resp_ctxt: 0x%08x +4723,iiiiiiii,[ wlan_rtt.c : 5558 ] wlan_rtt_resp_init_rate: vdev_id: %d phy_mode: %d mhz: %d ftm_chnl_format: %d param_ie_valid: %d tx_bw: %d tx_preamble: %d mcs: %d +4722,IIIi,[ wlan_rtt.c : 7333 ] Channel Granted(Responder): Responder operating freq = 0x%x pmac = 0x%08x Granted on freq: 0x%x phymode: %d +4721,ii,[ wlan_rtt.c : 10490 ] wlan_rtt_resp_house_keeping: channel_mhz: %d nearest_sched_resp_tsf_ctxt_index: %d +4720,,[ wlan_rtt.c : 2339 ] All requests done nothing to schedule +4719,IIII,[ wlan_rtt.c : 1760 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4718,iiiI,[ wlan_rtt.c : 7022 ] RTT_ERROR_WMI_EVENT: ERROR: client_id: %d req_id:%d reason:%d init_ctxt: 0x%08x +4717,,[ wlan_rtt.c : 7066 ] Event buffer allocation for send_rtt_error_report failed +4716,iIiiiIi,[ wlan_rtt.c : 7223 ] wlan_rtt_send_measurement_report_hdl: client_id: %d curr_init_ctxt: 0x%08x token_id:%d frag_idx:%d more_frag: %d buf:0x%08x buf_len:%d +4715,IIIi,[ wlan_rtt.c : 7930 ] wlan_rtt_send_null_frame: abf: 0x%08x channel: %x pmac = 0x%08x spoofed_seqno = %d +4714,Ii,[ wlan_rtt.c : 7948 ] RTT NULL frame Tx failed: abf: 0x%08x ret: %d +4713,,[ wlan_rtt.c : 8453 ] wlan_rtt_send_tm_frame: vdev is seen as NULL in resp_ctxt +4712,,[ wlan_rtt.c : 8607 ] RTT_ERROR_REPORT :ALLOCATE_FRAME_BUFFER_ERROR +4711,IiIIiiiiI,[ wlan_rtt.c : 8616 ] wlan_rtt_send_tm_frame: abf: 0x%08x freq: %d pmac = 0x%08x resp_ctxt: 0x%08x tkn = %d follow_tkn = %d tx_bw = %d resp_ctxt ftm state = %d chan_flags = 0x%04x +4710,II,[ wlan_rtt.c : 8291 ] Sending RTT Trigger frame resp_tsf_h = 0x%x resp_tsf_l = 0x%x +4709,,[ wlan_rtt.c : 8322 ] RTT_ERROR_REPORT :ALLOCATE_FRAME_BUFFER_ERROR +4708,IIi,[ wlan_rtt.c : 8346 ] wlan_rtt_send_tmr_frame: channel: %x pmac = 0x%08x spoofed_seqno = %d +4707,,[ wlan_rtt.c : 8387 ] RTT_TIMER_STOP +4706,I,[ wlan_rtt.c : 8136 ] RTT_CALL_FLOW: WLAN_RTT_SET_VENDOR_IE_HT_VHT_ACK ts = %u +4705,iii,[ wlan_rtt.c : 11202 ] wlan_rtt_sta_resp_chan_switch: channel.mhz: %d band_center_freq1: %d phy_mode: %d +4704,IIII,[ wlan_rtt.c : 11129 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4703,i,[ wlan_rtt.c : 1576 ] wlan_rtt_start_burst_periodic_timer: timeout_ms:%dms +4702,iIIi,[ wlan_rtt.c : 1306 ] wlan_rtt_terminate_all_ftm_resp_context() idx: %d resp_ctxt = 0x%08x vdev = 0x%08x ftm_state = %d +4701,iiiii,[ wlan_rtt.c : 1399 ] cancel_measurement_req: vdev_type: %d, req_id: %d, free_curr_init: %d, is_cancelled: %d frame_type_handler_called %d +4700,iIII,[ wlan_rtt.c : 2097 ] wlan_rtt_terminate_repetitive_ss_request: red_id:%d init_ctxt_usage_flags:0x%x dest_mac :%x %x +4699,iii,[ wlan_rtt.c : 1258 ] wlan_rtt_terminate_resp_context() state: %d busrt_exp: %d burst_count: %d +4698,iii,[ wlan_rtt.c : 9251 ] wlan_rtt_tm_ack_handle_completion: ftm_state: %d num_burst_exp: %d no_burst_count: %d +4697,IiIII,[ wlan_rtt.c : 9283 ] wlan_rtt_tm_ack_handle_completion: init_ftmr_rx_ts: %10u completion_status: %d ftm_tx_ts: %10u init_ftmr_offset: %6u delta_ftm_act: %6u +4696,i,[ wlan_rtt.c : 9365 ] RTT TM frame Tx status: %d +4695,i,[ wlan_rtt.c : 9312 ] RTT_TWOSIDED_RESP_CNT number = %d +4694,iii,[ wlan_rtt.c : 9332 ] wlan_rtt_tm_ack_success: ftm_state: %d num_burst_exp: %d no_burst_count: %d +4693,iii,[ wlan_rtt.c : 9337 ] wlan_rtt_tm_ack_success:Don't continue burst: ftm_state: %d num_burst_exp: %d no_burst_count: %d +4692,iIIiIII,[ wlan_rtt.c : 9721 ] state = %d tsf_sync_info = 0x%x resp_tsf = 0x%x Diff: %d ftm_req_start_time = 0x%x ftm_req_complete_time = 0x%x current_tsf = 0x%x +4691,II,[ wlan_rtt.c : 9732 ] RTT TM FTM curr_tsf_delta = 0x%x new_tsf_delta = 0x%x +4690,IIII,[ wlan_rtt.c : 9811 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4689,,[ wlan_rtt.c : 9922 ] RTT_ERROR_REPORT :TM_TOKEN_MISMATCH +4688,,[ wlan_rtt.c : 9925 ] RTT_ERROR_REPORT :TM_CFR_CAPTURE_ERROR +4687,,[ wlan_rtt.c : 9927 ] RTT_ERROR_REPORT :TM_SEQUENCE_RESTART +4686,,[ wlan_rtt.c : 9992 ] RTT_ERROR_REPORT :RTT_GET_TM_NOTWAIT_TM +4685,,[ wlan_rtt.c : 10010 ] RTT_ERROR_REPORT :RTT_GET_TM_NOTWAIT_TM +4684,IIiIIII,[ wlan_rtt.c : 10093 ] wlan_rtt_tm_rx_hdl: status: 0x%x RTT_TWOSIDED_RESP_CNT number = %2d recv_state: %d init_ftmr_tx_ts: %10u ftm_rx_ts: %10u init_ftmr_offset: %6u delta_ftm_act: %6u +4683,IIII,[ wlan_rtt.c : 8035 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4682,IIII,[ wlan_rtt.c : 8042 ] RTT_REPORT arg1 = 0x%x arg2 = 0x%x arg3 = x%x arg4 = 0x%x +4681,I,[ wlan_rtt.c : 8768 ] RTT add_random_mac_addr failed. status: 0x%x +4680,,[ wlan_rtt.c : 9591 ] rtt_tmr_rx_hdl() vdev not found +4679,,[ wlan_rtt.c : 9597 ] rtt_tmr_rx_hdl() wal_vdev not found +4678,II,[ wlan_rtt.c : 9639 ] rtt_tmr_rx_hdl() ftmr_rx_ts: %10u begin_tsf_sap_resp: %10u +4677,,[ wlan_rtt.c : 9658 ] RTT_ERROR_REPORT :RTT_GET_INVALID_TMR_STOP +4676,,[ wlan_rtt.c : 9678 ] RTT_ERROR_REPORT :RTT_GET_INVALID_TMR_STOP +4675,iiI,[ wlan_rtt.c : 8998 ] RTT TMR frame Tx status: %d curr_state: %d ftmr_tx_ts: %u +4674,iiii,[ wlan_rtt.c : 4348 ] RTT_UNIT_TEST_CMD 1 num_args = %d arg0 = %d vdev_id = %d mac_id = %d +4673,iiiiii,[ wlan_rtt.c : 4411 ] RTT_UNIT_TEST_CMD numFrms= %d ChnlFrmt= %d frmType= %d reportType= %d burstDr= %d asap_mode= %d +4672,i,[ wlan_rtt.c : 4640 ] RTT_UNIT_TEST_CMD 2 status = %d +4671,,[ wlan_rtt.c : 4388 ] MAC address not configured +4670,,[ wlan_rtt.c : 4399 ] Channel not configured +4669,Iii,[ wlan_rtt.c : 1493 ] wlan_rtt_vdev_notify_handler() vdev = 0x%08x vdev_id = %d notification type = %d +4668,,[ wlan_rtt.c : 10887 ] Event buffer allocation for send_responder_cfg_info response failed +4667,iIIi,[ wlan_rtt.c : 11539 ] wlan_rtt_terminate_all_ftm_resp_context() idx: %d resp_ctxt = 0x%08x vdev = 0x%08x ftm_state = %d +4666,iiIii,[ wlan_rtt.c : 7127 ] wmi_send_rtt_error_report_event: req_id: %d reason: %d init_ctxt: 0x%08x vdev_type: %d nan_req_active: %d +4836,iIii,[ wlan_rtt_tlv_helper.c : 190 ] RTTTLV_CHECK_AND_PAD_TLVS is_req = %d buf_ptr = 0x%x buf_len = %d sub_type = %d +4835,i,[ wlan_rtt_tlv_helper.c : 194 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Couldn't get expected number of TLVs for sub_type=%d + +4834,iiiiii,[ wlan_rtt_tlv_helper.c : 214 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Invalid TLV length for sub_type=%d Tag_order=%d buf_idx=%d Tag:%d Len:%d TotalLen:%d + +4833,ii,[ wlan_rtt_tlv_helper.c : 223 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: No TLV attributes found for sub_type=%d Tag_order=%d + +4832,iii,[ wlan_rtt_tlv_helper.c : 228 ] RTTTLV_CHECK_AND_PAD_TLVS: VERBOSE: [tlv %d]: tag=%d, len=%d + +4831,iii,[ wlan_rtt_tlv_helper.c : 241 ] RTTTLV_CHECK_AND_PAD_TLVS: VERBOSE: Tag ID expecting is Loop end for loop started at index %d but received tag %d.num_active_loops: %d +4830,iii,[ wlan_rtt_tlv_helper.c : 247 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Can't get the first TLV Tag ID (tlv_index:%d) for last entered loop start (cnt=%d) for sub_type=%d + +4829,iiii,[ wlan_rtt_tlv_helper.c : 255 ] RTTTLV_CHECK_AND_PAD_TLVS: WARN: First TLV Tag ID (%d) for last entered loop start (index=%d) doesn't match; skipping this tlv with tag:%d for sub_type=%d +4828,iiiii,[ wlan_rtt_tlv_helper.c : 262 ] RTTTLV_CHECK_AND_PAD_TLVS: VERBOSE: First TLV Tag ID (tlv_index:%d) for last entered loop start (total_active_loops=%d) matched (looping loop_cnt:%d) with tag:%d for sub_type=%d +4827,iii,[ wlan_rtt_tlv_helper.c : 278 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: TLV has wrong tag in order for sub_type=%d. Given=%d, Expected=%d. + +4826,iii,[ wlan_rtt_tlv_helper.c : 284 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: TLV has wrong tag in order for sub_type=%d. Given=%d, Expected=%d. + +4825,ii,[ wlan_rtt_tlv_helper.c : 292 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Wrong TLV length %d for loop end for sub_type:%d +4824,i,[ wlan_rtt_tlv_helper.c : 297 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Loop start and End mismatch for sub_type:%d +4823,iiii,[ wlan_rtt_tlv_helper.c : 305 ] RTTTLV_CHECK_AND_PAD_TLVS: VERBOSE: Processing of loop %d done for sub_type:%d; left out loop instances:%d TLVs per loop:%d +4822,iii,[ wlan_rtt_tlv_helper.c : 320 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Exceeded given max loop count %d, for sub_type:%d tlv_index:%d +4821,ii,[ wlan_rtt_tlv_helper.c : 329 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Wrong TLV length %d for loop start for sub_type:%d +4820,i,[ wlan_rtt_tlv_helper.c : 334 ] RTTTLV_CHECK_AND_PAD_TLVS: ERROR: Maximum inner loops reached for sub_type:%d +4819,i,[ wlan_rtt_tlv_helper.c : 367 ] RTTTLV_CHECK_AND_PAD_TLVS: WARN: ERROR Need to handle this tag ID %d for variable length + +4818,ii,[ wlan_rtt_tlv_helper.c : 378 ] RTTTLV_CHECK_AND_PAD_TLVS: WARN: TLV truncated. tlv_size_diff=%d, curr_tlv_len=%d + +4817,i,[ wlan_rtt_tlv_helper.c : 393 ] RTTTLV_CHECK_AND_PAD_TLVS: WARN: TLV needs padding. tlv_size_diff=-%d + +4816,ii,[ wlan_rtt_tlv_helper.c : 458 ] RTTTLV_CHECK_AND_PAD_TLVS: Some loop(cnt = %d) didn't ended properly for sub_type:%d +4815,i,[ wlan_rtt_tlv_helper.c : 464 ] RTTTLV_CHECK_AND_PAD_TLVS: Successfully processed TLVs for sub_type:%d + +4814,iii,[ wlan_rtt_tlv_helper.c : 90 ] WMI TLV attribute definitions for is_req:%d found; rtt_cmd_event_id: %d num_of_tlvs:%d +4813,ii,[ wlan_rtt_tlv_helper.c : 119 ] ERROR: Didn't found WMI TLV attribute definitions for is_req:%d rtt_cmd_event_id: %d +4812,iiii,[ wlan_rtt_tlv_helper.c : 99 ] ERROR: TLV order %d greater than num_of_tlvs:%d for is_req:%d rtt_cmd_event_id: %d +4811,iiii,[ wlan_rtt_tlv_helper.c : 106 ] WMI TLV attributes for is_req:%d rtt_cmd_event_id: %d TLV order %d [tlv %d] +4862,,[ wlan_cfr.c : 1473 ] No free unassociated CFR pool +4861,ii,[ wlan_cfr.c : 1822 ] wlan_cfr_pm_arb_req(): mac_id: %d state: %d +4860,iiii,[ wlan_cfr.c : 1624 ] <<< CFR_UNIT_TEST_CMD, num_args = %d arg0 = %d vdev_id = %d mac_id = %d +4859,,[ wlan_cfr.c : 1657 ] CFR_UNIT_TEST_CMD_SET_TA_AND_MASK, there's some missing argument, cannot set here +4858,,[ wlan_cfr.c : 1677 ] CFR_UNIT_TEST_CMD_SET_RA_AND_MASK, there's some missing argument, cannot set here +4857,,[ wlan_cfr.c : 1699 ] CFR_UNIT_TEST_CMD_SET_EXTRA_PARAMS_CAPTURE_GROUP, there's some missing argument, cannot set here +4856,,[ wlan_cfr.c : 1722 ] CFR_UNIT_TEST_CMD_SET_EXTRA_FIXED_PARAM, there's some missing argument, cannot set here +4855,,[ wlan_cfr.c : 1742 ] CFR_UNIT_TEST_CMD_WMI_CFR_CAPTURE_FILTER_CMDID, there's some missing argument, cannot set here +4854,IIIII,[ wlan_cfr.c : 1767 ] wmi_pdev_id = 0x%x filter_type = 0x%x capture_interval = 0x%x capture_duration = 0x%x filter_group_bitmap = 0x%x +4853,IIIIII,[ wlan_cfr.c : 1776 ] filter_group_id = 0x%x filter_set_valid_mask = 0x%x bw_nss_filter = 0x%x mgmt_subtype_filter = 0x%x ctrl_subtype_filter = 0x%x data_subtype_filter = 0x%x +4852,IIII,[ wlan_cfr.c : 1783 ] ta_addr.mac_addr31to0 = 0x%x ta_addr.mac_addr47to32 = 0x%x ta_addr_mask.mac_addr31to0 = 0x%x ta_addr_mask.mac_addr47to32 = 0x%x +4851,IIII,[ wlan_cfr.c : 1790 ] ra_addr.mac_addr31to0 = 0x%x ra_addr.mac_addr47to32 = 0x%x ra_addr_mask.mac_addr31to0 = 0x%x ra_addr_mask.mac_addr47to32 = 0x%x +4850,i,[ wlan_cfr.c : 1810 ] >>> CFR_UNIT_TEST_CMD, status = %d +4849,I,[ wlan_cfr.c : 1549 ] wlan_next_cfr_capture_handler: no capture requests in 0x%08x +4848,III,[ wlan_cfr.c : 933 ] Space not available read_index = %x,write_index = %x, max_write_index = %x +4847,i,[ wlan_cfr.c : 1154 ] gain table index is non zero for chain: %d +4846,,[ wlan_cfr.c : 1176 ] Invalid gain info. No AoA phase data got captured. +4845,IIIii,[ wlan_cfr.c : 1202 ] wlan_null_frame_cfr_wmi_ack_hdl: status 0x%08x correlation_info 0x%08x%08x cap_bw %d tx_bw %d +4844,i,[ wlan_cfr.c : 1161 ] Capping gain to 62, Current gain = %d +4843,IIIIIIII,[ wlan_cfr.c : 1171 ] gainDB values: %u %u %u %u %u %u %u %u +4842,I,[ wlan_cfr.c : 1340 ] Invalid operating BW for CFR %x +4841,I,[ wlan_cfr.c : 1389 ] Invalid CFR capture method %x +4840,iiIIIi,[ wlan_cfr.c : 755 ] wlan_peer_cfr_capture_cmd_handler: request %d periodicity %d peer MAC 0x%08x%02x context 0x%08x status %d +4839,iIIiI,[ wlan_cfr.c : 55 ] wlan_peer_cfr_capture_done: vdev %d peer MAC 0x%08x%02x status %d at %p +4838,,[ wlan_cfr.c : 100 ] WMI_PEER_CFR_CAPTURE_EVENTID evt alloc failed +4837,I,[ wlan_cfr.c : 1587 ] wlan_periodic_cfr_capture_handler: no capture requests in 0x%08x +4872,II,[ wlan_obss_scan_offload.c : 192 ] obss send: num_of_scans:%x,send cnt:%x +4871,II,[ wlan_obss_scan_offload.c : 219 ] obss merge: num_of_scans:%x, idx:%x +4870,ii,[ wlan_obss_scan_offload.c : 322 ] Beacon parser invoked, mac_id:%d, ch:%d +4869,ii,[ wlan_obss_scan_offload.c : 353 ] obss scan TE-A type=%d, index:%d +4868,,[ wlan_obss_scan_offload.c : 358 ] obss scan TE-A rec null +4867,Iiii,[ wlan_obss_scan_offload.c : 394 ] obss scan TE-A found_dup=%x, index:%d, op:%d,ch_id:%d +4866,iI,[ wlan_obss_scan_offload.c : 350 ] obss scan HT cap present=%d, teb:0x%x +4865,Ii,[ wlan_obss_scan_offload.c : 117 ] obss scan send action, add ch id:%x, op class:%d +4864,IiIi,[ wlan_obss_scan_offload.c : 123 ] OBSS_SCAN_SEND_ACTION idx:%x, op class:%d, intolerent len:%x, frame len:%d +4863,I,[ wlan_obss_scan_offload.c : 153 ] obss coex action frame buf null, vdev id:%x +4877,i,[ wlan_obss_scan_offload_wmi.c : 330 ] obss scan stop, refer cnt:%d, status +4876,i,[ wlan_obss_scan_offload_wmi.c : 201 ] obss scan start vdev id =%d +4875,,[ wlan_obss_scan_offload_wmi.c : 265 ] Channel not in 2.4 GHz sent +4874,i,[ wlan_obss_scan_offload_wmi.c : 206 ] obss scan vdev pool alloc failed=%d +4873,,[ wlan_obss_scan_offload_wmi.c : 253 ] Channel not in 2.4 GHz sent +4885,II,[ umac_wmi_events.c : 600 ] WMI_CHAN_INFO_EVENT_ALLOC_FAILURE EventId = 0x%x chan_freq = 0x%x +4884,iiiiiii,[ umac_wmi_events.c : 608 ] WMI_CHAN_INFO_EVT err_code = %d, freq = %d, cmd_flags = %d, nf = %d, rx_clr_cnt = %d, cycle_cnt = %d, chan_tx_pwr_range = %d +4883,iiiiii,[ umac_wmi_events.c : 610 ] WMI_CHAN_INFO_EVT chan_tx_pwr_tp = %d, rx_frm_cnt = %d, my_bss_rx_cycle_cnt = %d, rx_11b_mode_data_dur = %d, tx_frm_cnt = %d, mac_clk_mhz = %d +4882,iII,[ umac_wmi_events.c : 649 ] WMI_EVENT_ALLOC_FAILURE vdev_id = %d EventId = 0x%x AssocId/VdevMap = 0x%x +4881,iII,[ umac_wmi_events.c : 750 ] WMI_EVENT_ALLOC_FAILURE vdev_id = %d EventId = 0x%x AssocId/VdevMap = 0x%x +4880,ii,[ umac_wmi_events.c : 114 ] drop mgmt as size:%d,limit:%d +4879,,[ umac_wmi_events.c : 279 ] BEACON_EVENT_SWBA_SEND_FAILED +4878,II,[ umac_wmi_events.c : 710 ] WMI_EVENT_ALLOC_FAILURE EventId = 0x%x AssocId/VdevMap = 0x%x +4891,,[ wlan_wmi.c : 299 ] wlan_wmi_read_tlv: p_in_tlv is NULL +4890,,[ wlan_wmi.c : 305 ] wlan_wmi_read_tlv: p_out_tlv is NULL +4889,III,[ wlan_wmi.c : 328 ] wlan_wmi_read_tlv: type=%u, length=%u, read_len=%u +4888,,[ wlan_wmi.c : 259 ] wlan_wmi_write_tlv: p_in_tlv is NULL +4887,,[ wlan_wmi.c : 265 ] wlan_wmi_write_tlv: p_out_tlv is NULL +4886,III,[ wlan_wmi.c : 285 ] wlan_wmi_write_tlv: type=%u, length=%u, write_len=%u +4917,iiii,[ wlan_wmi_events.c : 592 ] wlan_debug_mesg_flush_compete stall_type:%d vdev_bmap:%d reason_code1:%d reason_code2:%d +4916,II,[ wlan_wmi_events.c : 642 ] WMI handle send WMI evt msg fail, evt_id:0x%x, evt_len:0x%x + +4915,II,[ wlan_wmi_events.c : 646 ] WMI handle send WMI evt msg, evt_id:0x%x, evt_len:0x%x + +4914,IIIII,[ wlan_wmi_events.c : 266 ] bdf_version = %x ref_design_id=%x, customer_id=%x, project_id=%x, board_data_rev=%x +4913,iiiii,[ wlan_wmi_events.c : 1741 ] wmi_service_ready_ext_event: pdev_id %d mod_id %d ring_elems_min %d min_buf_align %d min_buf_size %d +4912,ii,[ wlan_wmi_events.c : 1810 ] SCAN_RADIO_SUPPORT_DBUG WMI_SERVICE_READY_EXT2 san_radio_flag = %d phy_id = %d + +4911,ii,[ wlan_wmi_events.c : 1843 ] cust_bdf_ver_major =%d cust_bdf_ver_minor=%d +4910,iiiii,[ wlan_wmi_events.c : 1544 ] wmi_service_ready_ext_event: pdev_id %d mod_id %d ring_elems_min %d min_buf_align %d min_buf_size %d +4909,IIIIIIII,[ wlan_wmi_events.c : 1567 ] WMI Service Ready Ext: wmi_svc_bitmap(ext) = 0x%08x %08x %08x %08x (%08x %08x %08x %08x) +4908,III,[ wlan_wmi_events.c : 691 ] DISPLAY_TPC_STATS: 1st event tpcEvSize is %lu wal_pdev_get_reg_array_len is %lu reg_mask is %u +4907,,[ wlan_wmi_events.c : 695 ] DISPLAY_TPC_STATS: Event size exceeds WMI_SVC_MSG_SIZE!! +4906,,[ wlan_wmi_events.c : 703 ] DISPLAY_TPC_STATS: WMI tpc stats evt, allocation failed! +4905,I,[ wlan_wmi_events.c : 930 ] DISPLAY_TPC_STATS: 4th event tpcEvSize is %lu +4904,I,[ wlan_wmi_events.c : 932 ] DISPLAY_TPC_STATS: wal_pdev_get_ctl_array_len is %lu +4903,,[ wlan_wmi_events.c : 939 ] DISPLAY_TPC_STATS: Event size exceeds WMI_SVC_MSG_SIZE!! +4902,,[ wlan_wmi_events.c : 946 ] DISPLAY_TPC_STATS: WMI tpc stats evt, allocation failed! +4901,I,[ wlan_wmi_events.c : 952 ] DISPLAY_TPC_STATS: event starting ptr is %lu +4900,,[ wlan_wmi_events.c : 667 ] DISPLAY_TPC_STATS: wmi_tpc_stats_event_complete +4899,II,[ wlan_wmi_events.c : 766 ] DISPLAY_TPC_STATS: 2nd event tpcEvSize is %lu wal_pdev_get_rates_array_len is %lu +4898,,[ wlan_wmi_events.c : 770 ] DISPLAY_TPC_STATS: Event size exceeds WMI_SVC_MSG_SIZE!! +4897,,[ wlan_wmi_events.c : 777 ] DISPLAY_TPC_STATS: WMI tpc stats evt, allocation failed! +4896,I,[ wlan_wmi_events.c : 783 ] DISPLAY_TPC_STATS: event starting ptr is %lu +4895,I,[ wlan_wmi_events.c : 842 ] DISPLAY_TPC_STATS: 3rd event tpcEvSize is %lu +4894,,[ wlan_wmi_events.c : 849 ] DISPLAY_TPC_STATS: Event size exceeds WMI_SVC_MSG_SIZE!! +4893,,[ wlan_wmi_events.c : 856 ] DISPLAY_TPC_STATS: WMI tpc stats evt, allocation failed! +4892,,[ wlan_wmi_events.c : 611 ] WOW send initial wakeup wmi cmd +5036,I,[ hca_HwComponentRf_bdf_v1.cpp : 88 ] %s NOT available + +5035,I,[ hca_HwComponentRf_bdf_v1.cpp : 38 ] %s NOT available + +5034,I,[ hca_HwComponentRf_bdf_v1.cpp : 96 ] %s NOT available + +5033,I,[ hca_HwComponentRf_bdf_v1.cpp : 79 ] %s NOT available + +5032,I,[ hca_HwComponentRf_bdf_v1.cpp : 115 ] %s NOT available + +5031,I,[ hca_HwComponentRf_bdf_v1.cpp : 70 ] %s NOT available + +5030,I,[ hca_HwComponentRf_bdf_v1.cpp : 60 ] %s NOT available + +5029,I,[ hca_HwComponentRf_bdf_v1.cpp : 77 ] %s NOT available + +5028,I,[ hca_HwComponentRf_bdf_v1.cpp : 64 ] %s NOT available + +5027,I,[ hca_HwComponentRf_bdf_v1.cpp : 71 ] %s NOT available + +5026,I,[ hca_HwComponentRf_bdf_v1.cpp : 89 ] %s NOT available + +5025,I,[ hca_HwComponentRf_bdf_v1.cpp : 76 ] %s NOT available + +5024,I,[ hca_HwComponentRf_bdf_v1.cpp : 105 ] %s NOT available + +5023,I,[ hca_HwComponentRf_bdf_v1.cpp : 135 ] %s NOT available + +5022,I,[ hca_HwComponentRf_bdf_v1.cpp : 91 ] %s NOT available + +5021,I,[ hca_HwComponentRf_bdf_v1.cpp : 75 ] %s NOT available + +5020,I,[ hca_HwComponentRf_bdf_v1.cpp : 45 ] %s NOT available + +5019,I,[ hca_HwComponentRf_bdf_v1.cpp : 95 ] %s NOT available + +5018,I,[ hca_HwComponentRf_bdf_v1.cpp : 51 ] %s NOT available + +5017,I,[ hca_HwComponentRf_bdf_v1.cpp : 40 ] %s NOT available + +5016,I,[ hca_HwComponentRf_bdf_v1.cpp : 65 ] %s NOT available + +5015,I,[ hca_HwComponentRf_bdf_v1.cpp : 81 ] %s NOT available + +5014,I,[ hca_HwComponentRf_bdf_v1.cpp : 78 ] %s NOT available + +5013,I,[ hca_HwComponentRf_bdf_v1.cpp : 92 ] %s NOT available + +5012,I,[ hca_HwComponentRf_bdf_v1.cpp : 101 ] %s NOT available + +5011,I,[ hca_HwComponentRf_bdf_v1.cpp : 69 ] %s NOT available + +5010,I,[ hca_HwComponentRf_bdf_v1.cpp : 100 ] %s NOT available + +5009,I,[ hca_HwComponentRf_bdf_v1.cpp : 99 ] %s NOT available + +5008,I,[ hca_HwComponentRf_bdf_v1.cpp : 116 ] %s NOT available + +5007,I,[ hca_HwComponentRf_bdf_v1.cpp : 134 ] %s NOT available + +5006,I,[ hca_HwComponentRf_bdf_v1.cpp : 73 ] %s NOT available + +5005,I,[ hca_HwComponentRf_bdf_v1.cpp : 39 ] %s NOT available + +5004,I,[ hca_HwComponentRf_bdf_v1.cpp : 50 ] %s NOT available + +5003,I,[ hca_HwComponentRf_bdf_v1.cpp : 80 ] %s NOT available + +5002,I,[ hca_HwComponentRf_bdf_v1.cpp : 63 ] %s NOT available + +5001,I,[ hca_HwComponentRf_bdf_v1.cpp : 55 ] %s NOT available + +5000,I,[ hca_HwComponentRf_bdf_v1.cpp : 46 ] %s NOT available + +4999,I,[ hca_HwComponentRf_bdf_v1.cpp : 67 ] %s NOT available + +4998,I,[ hca_HwComponentRf_bdf_v1.cpp : 74 ] %s NOT available + +4997,I,[ hca_HwComponentRf_bdf_v1.cpp : 44 ] %s NOT available + +4996,I,[ hca_HwComponentRf_bdf_v1.cpp : 68 ] %s NOT available + +4995,I,[ hca_HwComponentRf_bdf_v1.cpp : 42 ] %s NOT available + +4994,I,[ hca_HwComponentRf_bdf_v1.cpp : 58 ] %s NOT available + +4993,I,[ hca_HwComponentRf_bdf_v1.cpp : 102 ] %s NOT available + +4992,I,[ hca_HwComponentRf_bdf_v1.cpp : 41 ] %s NOT available + +4991,I,[ hca_HwComponentRf_bdf_v1.cpp : 90 ] %s NOT available + +4990,I,[ hca_HwComponentRf_bdf_v1.cpp : 57 ] %s NOT available + +4989,I,[ hca_HwComponentRf_bdf_v1.cpp : 56 ] %s NOT available + +4988,I,[ hca_HwComponentRf_bdf_v1.cpp : 110 ] %s NOT available + +4987,I,[ hca_HwComponentRf_bdf_v1.cpp : 103 ] %s NOT available + +4986,I,[ hca_HwComponentRf_bdf_v1.cpp : 61 ] %s NOT available + +4985,I,[ hca_HwComponentRf_bdf_v1.cpp : 93 ] %s NOT available + +4984,I,[ hca_HwComponentRf_bdf_v1.cpp : 43 ] %s NOT available + +4983,I,[ hca_HwComponentRf_bdf_v1.cpp : 107 ] %s NOT available + +4982,I,[ hca_HwComponentRf_bdf_v1.cpp : 114 ] %s NOT available + +4981,I,[ hca_HwComponentRf_bdf_v1.cpp : 111 ] %s NOT available + +4980,I,[ hca_HwComponentRf_bdf_v1.cpp : 106 ] %s NOT available + +4979,I,[ hca_HwComponentRf_bdf_v1.cpp : 47 ] %s NOT available + +4978,I,[ hca_HwComponentRf_bdf_v1.cpp : 48 ] %s NOT available + +4977,I,[ hca_HwComponentRf_bdf_v1.cpp : 109 ] %s NOT available + +4976,I,[ hca_HwComponentRf_bdf_v1.cpp : 82 ] %s NOT available + +4975,I,[ hca_HwComponentRf_bdf_v1.cpp : 83 ] %s NOT available + +4974,I,[ hca_HwComponentRf_bdf_v1.cpp : 123 ] %s NOT available + +4973,I,[ hca_HwComponentRf_bdf_v1.cpp : 132 ] %s NOT available + +4972,I,[ hca_HwComponentRf_bdf_v1.cpp : 72 ] %s NOT available + +4971,I,[ hca_HwComponentRf_bdf_v1.cpp : 104 ] %s NOT available + +4970,I,[ hca_HwComponentRf_bdf_v1.cpp : 124 ] %s NOT available + +4969,I,[ hca_HwComponentRf_bdf_v1.cpp : 85 ] %s NOT available + +4968,I,[ hca_HwComponentRf_bdf_v1.cpp : 112 ] %s NOT available + +4967,I,[ hca_HwComponentRf_bdf_v1.cpp : 113 ] %s NOT available + +4966,I,[ hca_HwComponentRf_bdf_v1.cpp : 66 ] %s NOT available + +4965,I,[ hca_HwComponentRf_bdf_v1.cpp : 62 ] %s NOT available + +4964,I,[ hca_HwComponentRf_bdf_v1.cpp : 84 ] %s NOT available + +4963,I,[ hca_HwComponentRf_bdf_v1.cpp : 94 ] %s NOT available + +4962,I,[ hca_HwComponentRf_bdf_v1.cpp : 108 ] %s NOT available + +4961,I,[ hca_HwComponentRf_bdf_v1.cpp : 52 ] %s NOT available + +4960,I,[ hca_HwComponentRf_bdf_v1.cpp : 86 ] %s NOT available + +4959,I,[ hca_HwComponentRf_bdf_v1.cpp : 59 ] %s NOT available + +4958,I,[ hca_HwComponentRf_bdf_v1.cpp : 37 ] %s NOT available + +4954,i,[ hca_HwComponentRf_bdf_v1.cpp : 2614 ] RTT - Invalid preamble: %d; return 0 delays +4953,iiiiiiii,[ hca_HwComponentRf_bdf_v1.cpp : 2627 ] RTT - phy%d chainNum: %d txRxIdx: %d, dynBw: %d, preamble: %d, heLtf: %d, pktBw: %d, whalRate: %d +4952,i,[ hca_HwComponentRf_bdf_v1.cpp : 2638 ] RTT - base=%d +4951,ii,[ hca_HwComponentRf_bdf_v1.cpp : 2642 ] RTT - freq %d, delta=%d +4950,i,[ hca_HwComponentRf_bdf_v1.cpp : 2648 ] RTT - pri20, delta=%d +4949,ii,[ hca_HwComponentRf_bdf_v1.cpp : 2657 ] RTT - chain %d delta=%d +4948,i,[ hca_HwComponentRf_bdf_v1.cpp : 2664 ] RTT - IQ, delta=%d +4947,i,[ hca_HwComponentRf_bdf_v1.cpp : 2669 ] RTT - LCP, delta=%d +4946,i,[ hca_HwComponentRf_bdf_v1.cpp : 2680 ] RTT - heavyclip, delta=%d +4945,i,[ hca_HwComponentRf_bdf_v1.cpp : 2685 ] RTT - DPD PEF, delta=%d +4944,i,[ hca_HwComponentRf_bdf_v1.cpp : 2690 ] RTT - Tx DAC, delta=%d +4943,i,[ hca_HwComponentRf_bdf_v1.cpp : 2699 ] RTT - Ti ADC, delta=%d +4942,i,[ hca_HwComponentRf_bdf_v1.cpp : 2704 ] RTT - VSRC, delta=%d +4941,i,[ hca_HwComponentRf_bdf_v1.cpp : 2709 ] RTT - spur mit, delta=%d +4940,I,[ hca_HwComponentRf_bdf_v1.cpp : 2722 ] RTT - apply 2G 6us offset, delayVal=0x%x +4939,i,[ hca_HwComponentRf_bdf_v1.cpp : 2727 ] RTT - delayPs=%d ps +4938,,[ hca_HwComponentRf_bdf_v1.cpp : 2808 ] NEED to implement GetTpcCalFreq in chip specific class +4937,iiI,[ hca_HwComponentRf_bdf_v1.cpp : 582 ] ccaThresh:%d deltaNF:%d reg:%x +4936,,[ hca_HwComponentRf_bdf_v1.cpp : 2511 ] xTal : Skipped programming CapIn and capOut values +4935,,[ hca_HwComponentRf_bdf_v1.cpp : 3785 ] FTM CALDB: Skipping regeneration of CALDB: + +4934,,[ hca_HwComponentRf_bdf_v1.cpp : 3787 ] FTM CALDB: NOT Skipping regeneration of CALDB: + +4933,i,[ hca_HwComponentRf_bdf_v1.cpp : 1112 ] SCAN-HOME: Calling EnableCLPC Scan-Home SetOlpcforScan=%d +4932,iiIi,[ hca_HwComponentRf_bdf_v1.cpp : 1118 ] HomeChan = %d doTpcFlag = %d, resetCause = 0x%x, tpscale = %d +4931,iIIiii,[ hca_HwComponentRf_bdf_v1.cpp : 2878 ] DumpTpcPerPacket: GetCtlPwrPerChain NSS %d rcFlags 0x%x CM 0x%x scaledPower %d beamforming %d phyID %d +4930,,[ hca_HwComponentRf_bdf_v1.cpp : 2895 ] TPC_CTL: FTM STBC type and NSS is limited to 1 for NTx = 1 +4929,,[ hca_HwComponentRf_bdf_v1.cpp : 2900 ] TPC_CTL: STBC type and NSS was 1 for NTx >= 2 so setting NSS 2 +4928,ii,[ hca_HwComponentRf_bdf_v1.cpp : 2584 ] RTT - pktBw %d is not valid in dynamicBw %d +4927,III,[ hca_HwComponentRf_bdf_v1.cpp : 2003 ] sticky - add 0x%08lx, flag 0x%08lx, val 0x%08lx +4926,,[ hca_HwComponentRf_bdf_v1.cpp : 1380 ] Incorrect array length for MIMO gain table +4925,iii,[ hca_HwComponentRf_bdf_v1.cpp : 2459 ] GetCalVersionDetails:: SWCAL DEBUG swCalVersion =%d, boardCalVersion=%d, calStatus=%d +4924,i,[ hca_HwComponentRf_bdf_v1.cpp : 2170 ] returning from phyrf_bdf_GetRxGainCalCfgLocalByBand:%d +4923,,[ hca_HwComponentRf_bdf_v1.cpp : 930 ] Rate to power table generated +4922,Ii,[ hca_HwComponentRf_bdf_v1.cpp : 611 ] xTal : Error returning ptr = 0x%x, maxXtalTempCompNum %d +4921,I,[ hca_HwComponentRf_bdf_v1.cpp : 358 ] WHAL_ERROR_EEPROM_MACADDR - sum = %lx + +4920,iiii,[ hca_HwComponentRf_bdf_v1.cpp : 2557 ] tempCode ch%d = %d, calTemp %d, tempSlope %d + +4919,ii,[ hca_HwComponentRf_bdf_v1.cpp : 2561 ] bdf thermCode %d, calTemp %d + +4918,i,[ hca_HwComponentRf_bdf_v1.cpp : 2565 ] bdf temp slope %d + +4957,I,[ hca_HwComponentRf_bdf_v1.cpp : 121 ] %s NOT available + +4956,I,[ hca_HwComponentRf_bdf_v1.cpp : 120 ] %s NOT available + +4955,I,[ hca_HwComponentRf_bdf_v1.cpp : 149 ] %s NOT available + +5040,I,[ phy_dev_calUtils.c : 259 ] otpRead: otp_read_en = 0x%08x +5039,i,[ phy_dev_calUtils.c : 264 ] Invalid OTP_WORD[=%d]. +5038,,[ phy_dev_calUtils.c : 319 ] Recipe failure +5037,I,[ phy_dev_calUtils.c : 320 ] [trigger_cal Recipe failure=%x] +5054,i,[ phy_dev_fdmtCombCal.c : 958 ] FDMT: CAL_INFO_MEM_0: RUN %d: START +5053,i,[ phy_dev_fdmtCombCal.c : 961 ] FDMT: CAL_INFO_MEM_0: RUN %d: END +5052,i,[ phy_dev_fdmtCombCal.c : 963 ] FDMT: CAL_INFO_MEM_1: RUN %d: START +5051,i,[ phy_dev_fdmtCombCal.c : 966 ] FDMT: CAL_INFO_MEM_1: RUN %d: END +5050,II,[ phy_dev_fdmtCombCal.c : 82 ] FDMT: ADDR: 0x%08x VAL: 0x%08x +5049,i,[ phy_dev_fdmtCombCal.c : 168 ] FDMT: RXIQ: CHAIN%d-PRI: +5048,i,[ phy_dev_fdmtCombCal.c : 171 ] FDMT: RXIQ: CHAIN%d-SEC: +5047,i,[ phy_dev_fdmtCombCal.c : 174 ] FDMT: RXIQ: CHAIN%d-FCS: +5046,i,[ phy_dev_fdmtCombCal.c : 132 ] FDMT: TXCL: CHAIN%d-PRI: +5045,i,[ phy_dev_fdmtCombCal.c : 135 ] FDMT: TXCL: CHAIN%d-FCS: +5044,i,[ phy_dev_fdmtCombCal.c : 105 ] FDMT: TXDCOC: CHAIN%d-PRI-PRISYN: +5043,i,[ phy_dev_fdmtCombCal.c : 108 ] FDMT: TXDCOC: CHAIN%d-FCS-PRISYN: +5042,i,[ phy_dev_fdmtCombCal.c : 150 ] FDMT: TXIQ: CHAIN%d-PRI: +5041,i,[ phy_dev_fdmtCombCal.c : 153 ] FDMT: TXIQ: CHAIN%d-FCS: +5061,,[ phy_dev_NFCal.c : 753 ] NFCAL: Enter NFCAL Mode +5060,,[ phy_dev_NFCal.c : 767 ] NFCAL: Exit NFCAL Mode +5059,ii,[ phy_dev_NFCal.c : 741 ] NFCAL: Forcing Chain%d MINCCAPWR_PRI80_DB2 with %ddBm +5058,ii,[ phy_dev_NFCal.c : 742 ] NFCAL: Forcing Chain%d MINCCAPWR_SEC80_DB2 with %ddBm +5057,ii,[ phy_dev_NFCal.c : 579 ] NFCAL: Converged value for Chain%d MINCCAPWR_OUT_DB2 is %ddBm +5056,,[ phy_dev_NFCal.c : 68 ] NFCAL: Running Noise Floor CAL +5055,,[ phy_dev_NFCal.c : 72 ] NFCAL: Noise Floor CAL completed +5152,,[ phy_dev_paprd_device.c : 129 ] eDPD SendDpdTrainPktFtpg: Invaild PHY BW!!!! + +5151,III,[ phy_dev_paprd_device.c : 140 ] DPD SendDpdTrainPktFtpg: mcs %u, mpduLen, %u, pktBWCode, %u + +5150,i,[ phy_dev_paprd_device.c : 3953 ] -Q5-PAPRD-:channel freq %d + +5149,ii,[ phy_dev_paprd_device.c : 3954 ] -Q5-PAPRD-:txChain %d tableIndex %d + +5148,i,[ phy_dev_paprd_device.c : 3955 ] -Q5-PAPRD-:forced_sq_idx %d +5147,ii,[ phy_dev_paprd_device.c : 3956 ] -Q5-PAPRD-:sq_idx_sw %d sq_idx_hw %d + +5146,,[ phy_dev_paprd_device.c : 1449 ] Stopping phyDBG capture enable +5145,I,[ phy_dev_paprd_device.c : 1471 ] -Q5-PAPRDTUNING-:DPD training AGC2 size %lx + +5144,I,[ phy_dev_paprd_device.c : 1474 ] -Q5-PAPRDTUNING-:DPD training AGC2 pwr 0x%8lx + +5143,I,[ phy_dev_paprd_device.c : 1478 ] -Q5-PAPRDTUNING-:DPD training rx gain idx 0x%lx + +5142,I,[ phy_dev_paprd_device.c : 1482 ] -Q5-PAPRD-:DPD training active %lu + +5141,I,[ phy_dev_paprd_device.c : 1485 ] -Q5-PAPRD-:DPD training incomplete %lu + +5140,I,[ phy_dev_paprd_device.c : 1488 ] -Q5-PAPRDTUNING-:SQ index HW is %lu + +5139,i,[ phy_dev_paprd_device.c : 1500 ] -Q5-PAPRD-:DC estimate I %d + +5138,i,[ phy_dev_paprd_device.c : 1501 ] -Q5-PAPRD-:DC estimate Q %d + +5137,I,[ phy_dev_paprd_device.c : 1507 ] -Q5-PAPRD-:HW calculated stage2 min dispersion = %lu + +5136,I,[ phy_dev_paprd_device.c : 1508 ] -Q5-PAPRD-:Dispersion value at SQ Stage2 (minimum index - 1) = %lu + +5135,I,[ phy_dev_paprd_device.c : 1509 ] -Q5-PAPRD-:Dispersion value at SQ Stage2 (minimum index + 1) = %lu + +5134,II,[ phy_dev_paprd_device.c : 4039 ] --Q5--PAPRD: validmask 0x%lx phyInput->validChainMask 0x%x + +5133,,[ phy_dev_paprd_device.c : 524 ] PAPRD: HWDISABLE ALL + +5132,i,[ phy_dev_paprd_device.c : 511 ] PAPRD: HWDISABLE CHAIN : %d + +5131,i,[ phy_dev_paprd_device.c : 292 ] --Q5-PAPRD : For DPD Cal - Choosing GLUT %d + +5130,i,[ phy_dev_paprd_device.c : 302 ] --Q5-PAPRD : txMaskImprFlag %d + +5129,i,[ phy_dev_paprd_device.c : 449 ] eDPD SendDpdTrainPkt: %d + +5128,i,[ phy_dev_paprd_device.c : 807 ] -Q5-PAPRDTUNING-:DynBW = %d + +5127,,[ phy_dev_paprd_device.c : 979 ] force SQ + +5126,iI,[ phy_dev_paprd_device.c : 982 ] -Q5-PAPRDTUNING-:Forcing sq index hw for table %d with %lu + +5125,iii,[ phy_dev_paprd_device.c : 829 ] TxCount = %d table index = %d, txChina = %d + +5124,iiii,[ phy_dev_paprd_device.c : 861 ] -Q5-PAPRD : TxCount = %d table index = %d, txChina = %d, dacGain = %d + +5123,i,[ phy_dev_paprd_device.c : 876 ] -Q5 - PAPRDTUNING - :min loopback delay = %d + +5122,ii,[ phy_dev_paprd_device.c : 886 ] ADC OVRD VAL is %d with j as %d +5121,ii,[ phy_dev_paprd_device.c : 892 ] ADC OVRD VAL is %d with j as %d +5120,,[ phy_dev_paprd_device.c : 952 ] Enabling PHY DBG capture +5119,,[ phy_dev_paprd_device.c : 960 ] force SQ + +5118,,[ phy_dev_paprd_device.c : 967 ] NOT force SQ + +5117,ii,[ phy_dev_paprd_device.c : 974 ] Table Index = %d TxCount = %d + +5116,iI,[ phy_dev_paprd_device.c : 598 ] -Q5-PAPRD-:Chain = %d, Tx Cal Sub Mode = %lu + +5115,iiI,[ phy_dev_paprd_device.c : 603 ] -Q5-PAPRD-:Chain = %d, dpd Rx loop chian %d Rx Cal Sub Mode = %lu + +5114,ii,[ phy_dev_paprd_device.c : 607 ] -Q5-PAPRD-: HWIO : Tx Chain %d Attenuation value %d + +5113,ii,[ phy_dev_paprd_device.c : 612 ] -Q5-PAPRD-: HWIO : Rx Chain %d Attenuation value %d + +5112,,[ phy_dev_paprd_device.c : 749 ] -Q5-PAPRD-: phy_paprd_device_Iron_programming + +5111,II,[ phy_dev_paprd_device.c : 3333 ] Populate DPD LUT of Chain %hhu at table_idx %hhu + +5110,,[ phy_dev_paprd_device.c : 3387 ] Invalid tableOffset + +5109,,[ phy_dev_paprd_device.c : 3440 ] Invalid tableOffset + +5108,,[ phy_dev_paprd_device.c : 3446 ] Invalid tableType + +5107,iiiI,[ phy_dev_paprd_device.c : 3459 ] PAPRD:tableType: %d tableIdx: %d at even entry: %d from is : %lx + +5106,iiiI,[ phy_dev_paprd_device.c : 3461 ] PAPRD:tableType: %d tableIdx: %d at odd entry: %d from is : %lx + +5105,,[ phy_dev_paprd_device.c : 3469 ] Start Populated MemoryDPD Table! + +5104,i,[ phy_dev_paprd_device.c : 3474 ] int delay ddr x1 = %d + +5103,i,[ phy_dev_paprd_device.c : 3475 ] int delay ddr x2 = %d + +5102,i,[ phy_dev_paprd_device.c : 3476 ] int delay ddr x3 = %d + +5101,i,[ phy_dev_paprd_device.c : 3477 ] int delay ddr x4 = %d + +5100,i,[ phy_dev_paprd_device.c : 3478 ] int delay ddr x5 = %d + +5099,i,[ phy_dev_paprd_device.c : 3479 ] int delay ddr x6 = %d + +5098,,[ phy_dev_paprd_device.c : 3663 ] Invalid tableOffset + +5097,,[ phy_dev_paprd_device.c : 3687 ] Invalid tableOffset + +5096,,[ phy_dev_paprd_device.c : 3696 ] Finished populating DPD LUT into memory! +5095,,[ phy_dev_paprd_device.c : 1676 ] -Q5-PAPRD-:Read back DPD training data from memory: + +5094,ii,[ phy_dev_paprd_device.c : 1677 ] -Q5-PAPRD-:Raw Data: chain %d table %d + +5093,,[ phy_dev_paprd_device.c : 1678 ] -Q5-PAPRD-:DpdTrainData0 DpdTrainData1 DpdTrainData2 DpdTrainData3 + +5092,IIII,[ phy_dev_paprd_device.c : 1681 ] -Q5-PAPRD-:%lu %lu %lu %lu + +5091,iii,[ phy_dev_paprd_device.c : 473 ] PAPRD: Current Temp is %d Temp Threshold is %d dynGlutEn %d + +5090,iiIIii,[ phy_dev_paprd_device.c : 501 ] PAPRD:Chain = %d, tpc_index = %d, table_offset = %lu, glut_idx_offset = %lx, txgain_index = %d Power=%d + +5089,IIIII,[ phy_dev_paprd_device.c : 3887 ] -Q5-PAPRD- : RestorePreCalSettings savePreCalSettings[0] 0x%x [1] 0x%x [3] 0x%x [4] 0x%x [2] 0x%x +5088,IIIIi,[ phy_dev_paprd_device.c : 3894 ] -Q5-PAPRD- : RestorePreCalSettings TPC_FORCE_CTRL 0x%x PHYDBG_MODE 0x%x PHYDBG_CAPTURE_L 0x%x PHYDBG_CAPTURE_U 0x%x PHYDBG_TRIGGER_1_L 0x%d +5087,iI,[ phy_dev_paprd_device.c : 3898 ] -Q5-PAPRD- : RestorePreCalSettings RXBB-EN0 for Chain %d 0x%x +5086,ii,[ phy_dev_paprd_device.c : 3901 ] -Q5-PAPRD- : RestorePreCalSettings PHYRF_CAL_SEQ_CTRL_19_L %d PHYRF_CAL_MEAS_CTRL_4_U %d +5085,IIIIi,[ phy_dev_paprd_device.c : 3837 ] -Q5-PAPRD- : SavePreCalSettings TPC_FORCE_CTRL 0x%x PHYDBG_MODE 0x%x PHYDBG_CAPTURE_L 0x%x PHYDBG_CAPTURE_U 0x%x PHYDBG_TRIGGER_1_L 0x%d +5084,iI,[ phy_dev_paprd_device.c : 3841 ] -Q5-PAPRD- : SavePreCalSettings RXBB-EN0 for Chain %d 0x%x +5083,ii,[ phy_dev_paprd_device.c : 3845 ] -Q5-PAPRD- : savePreCalSettings PHYRF_CAL_SEQ_CTRL_19_L %d PHYRF_CAL_MEAS_CTRL_4_U %d +5082,i,[ phy_dev_paprd_device.c : 1039 ] agc2pwr = %d +5081,i,[ phy_dev_paprd_device.c : 1193 ] -Q5-PAPRD : StopTraining for Chain = %d + +5080,iiii,[ phy_dev_paprd_device.c : 1598 ] -Q5-PAPRD-: In training signal quality --- Bin idx %d -- accum count = %d, X value = %d, Average X = %d + +5079,i,[ phy_dev_paprd_device.c : 1606 ] -Q5-PAPRD-:Max value of Averaged X = %d + +5078,iiii,[ phy_dev_paprd_device.c : 1624 ] -Q5-PAPRD-:Bin %d chk_acc = %d, cnt = %d, diffn = %d +5077,i,[ phy_dev_paprd_device.c : 1638 ] -Q5-PAPRD-: Averaged SQ value is %d + +5076,i,[ phy_dev_paprd_device.c : 1324 ] -Q5-PAPRD : TRAINING DONE value is %d + +5075,i,[ phy_dev_paprd_device.c : 1332 ] SQ value is %d + +5074,I,[ phy_dev_paprd_device.c : 1356 ] -Q5-PAPRDTUNING-:TABLE 0 1 SQ index HW is %lu + +5073,iIi,[ phy_dev_paprd_device.c : 1372 ] -Q5-PAPRDTUNING-:sq PASS: sq_idx_sw %d sq_idx_hw %ld force_sq_idx %d + +5072,iiIi,[ phy_dev_paprd_device.c : 1380 ] -Q5-PAPRDTUNING-:sq FAIL : %d sq_idx_sw %d sq_idx_hw %ld force_sq_idx %d + +5071,,[ phy_dev_paprd_device.c : 1387 ] -Q5-PAPRD-:DPD training Failed. Paprd Done bit is not set in HW! + +5070,,[ phy_dev_paprd_device.c : 1127 ] -Q5-PAPRD-: phy_paprd_device_XmitTrainningFrame + +5069,iI,[ phy_dev_paprd_device.c : 3768 ] -Q5-PAPRD-:Exit Cal function - Chain = %d, Tx Cal Sub Mode = %lu + +5068,iiI,[ phy_dev_paprd_device.c : 3773 ] -Q5-PAPRD-:Exit Cal function - Chain = %d, dpd Rx loop chain %d Rx Cal Sub Mode = %lu + +5067,,[ phy_dev_paprd_device.c : 536 ] PAPRD: Force enable tlv + +5066,i,[ phy_dev_paprd_device.c : 768 ] PAPRD: txgain_index = %d + +5065,i,[ phy_dev_paprd_device.c : 781 ] PAPRD: dpdDacGain = %d + +5064,I,[ phy_dev_paprd_device.c : 1208 ] --Q5--PAPRDPHYDBG Base = 0x%lx + +5063,iIIII,[ phy_dev_paprd_device.c : 1245 ] --Q5--PAPRDPHYDBG-IQ %d %05d %05d %05d %05d + +5062,,[ phy_dev_paprd_device.c : 1249 ] --Q5--PAPRDPHYDBG-IQ delay 1ms +5178,ii,[ phy_dev_paprd_core.c : 906 ] PAPRD:UpdateLoopBackInfo wrong chain or GlutIdx: txChain %d tableIndex %d +5177,ii,[ phy_dev_paprd_core.c : 919 ] PAPRD:UpdateLoopBackInfo: txChain %d tableIndex %d +5176,ii,[ phy_dev_paprd_core.c : 927 ] PAPRD:phy_core_GetLoopbackInfo wrong chain or table index: txChain %d tableIndex %d +5175,ii,[ phy_dev_paprd_core.c : 941 ] PAPRD:phy_core_GetLoopbackInfo: txChain %d tableIndex %d +5174,iI,[ phy_dev_paprd_core.c : 651 ] phy_core_PaprdCalcGainFxp : max bins %d X[GfxpIdx] %lu + +5173,Ii,[ phy_dev_paprd_core.c : 656 ] -Q5-PAPRD : small signal gain is %ld, max_bins %d + +5172,ii,[ phy_dev_paprd_core.c : 53 ] phy_core_PaprdChangeTrainingIndex(): Change training position to chain index %d and dpd table index %d + +5171,ii,[ phy_dev_paprd_core.c : 450 ] -Q5-PAPRD : Max_index = %d, lssCount = %d +5170,I,[ phy_dev_paprd_core.c : 621 ] small signal gain is %ld + +5169,iI,[ phy_dev_paprd_core.c : 628 ] -Q5-PAPRD : PA_in[%d] = 0x%lx + +5168,i,[ phy_dev_paprd_core.c : 105 ] Channel %d is not in valid range + +5167,i,[ phy_dev_paprd_core.c : 76 ] Invalid channel %d + +5166,ii,[ phy_dev_paprd_core.c : 152 ] pPaprdStruct->tableIndex = %d, pPaprdStruct->txChain = %d + +5165,,[ phy_dev_paprd_core.c : 167 ] ******Memless DPD +5164,I,[ phy_dev_paprd_core.c : 204 ] SQ is %lu and update DPD table + +5163,ii,[ phy_dev_paprd_core.c : 217 ] SQ > SQ limit, DPD cal failed at chain %d and table index %d + +5162,I,[ phy_dev_paprd_core.c : 218 ] SQ = %lu + +5161,i,[ phy_dev_paprd_core.c : 155 ] training_done_for_curr_table_idx %d + +5160,i,[ phy_dev_paprd_core.c : 344 ] -Q5-PAPRD-:max_idx = %d (before adding bin#1) + +5159,,[ phy_dev_paprd_core.c : 349 ] -Q5-PAPRD-:X Y theta accCount + +5158,IIii,[ phy_dev_paprd_core.c : 353 ] -Q5-PAPRD-:%lu %lu %d %d + +5157,i,[ phy_dev_paprd_core.c : 264 ] Channel %d is not in valid range + +5156,ii,[ phy_dev_paprd_core.c : 896 ] PARPD:DPD Failed for txChain %d tableIndex %d +5155,i,[ phy_dev_paprd_core.c : 848 ] -Q5-PAPRDTUNING-: max_bin %d +5154,i,[ phy_dev_paprd_core.c : 849 ] -Q5-PAPRDTUNING-: base_bin %d +5153,i,[ phy_dev_paprd_core.c : 876 ] -Q5-PAPRD : Compression Ratio is %d +5194,i,[ phy_dev_DPDCal.c : 85 ] phyId : %d + +5193,i,[ phy_dev_DPDCal.c : 87 ] txmask = %d + +5192,i,[ phy_dev_DPDCal.c : 88 ] rxmask = %d + +5191,i,[ phy_dev_DPDCal.c : 89 ] gi = %d + +5190,,[ phy_dev_DPDCal.c : 102 ] Start to setup DPD cal: phy_DPDCal_InitTrainingData() + +5189,i,[ phy_dev_DPDCal.c : 103 ] phyId = %d + +5188,i,[ phy_dev_DPDCal.c : 104 ] txmask = %d + +5187,i,[ phy_dev_DPDCal.c : 105 ] gi = %d + +5186,,[ phy_dev_DPDCal.c : 115 ] Start to transmit training packet: phy_paprd_device_TransmitTrainingPacket() +5185,iIII,[ phy_dev_DPDCal.c : 131 ] %d 0x%08x 0x%05x%08x +5184,,[ phy_dev_DPDCal.c : 139 ] Training Done, Start post-processing + +5183,,[ phy_dev_DPDCal.c : 146 ] Finished post-processing + +5182,I,[ phy_dev_DPDCal.c : 86 ] phyBase = 0x%lx + +5181,,[ phy_dev_DPDCal.c : 151 ] Training data not valid poor SQ + +5180,,[ phy_dev_DPDCal.c : 157 ] train_done flag cannot be set by HW, DPD Cal hits an critical error and abort + +5179,,[ phy_dev_DPDCal.c : 301 ] DPDCal Recipe Start!!! + +5203,iI,[ phy_dev_DACCal.c : 139 ] Q5-DACcal: calibration completed for chain%d, result = 0x%x +5202,iI,[ phy_dev_DACCal.c : 144 ] Q5-DACcal: calibration failed for chain%d, result = 0x%x +5201,,[ phy_dev_DACCal.c : 166 ] Disabling TxBBF before DAC Cal for every chain +5200,i,[ phy_dev_DACCal.c : 192 ] DAC Cal time: = %d us + +5199,,[ phy_dev_DACCal.c : 182 ] Restoring TxBBF settings +5198,,[ phy_dev_DACCal.c : 230 ] DAC Cal Restore +5197,,[ phy_dev_DACCal.c : 205 ] DAC Cal Save +5196,i,[ phy_dev_DACCal.c : 70 ] running dac_cal_setup for chain%d +5195,ii,[ phy_dev_DACCal.c : 94 ] running enable_dac_cal for chain%d in mode %d +5214,,[ phy_dev_PkDetCal.c : 100 ] Enter Peak Detector CAL +5213,Iii,[ phy_dev_PkDetCal.c : 189 ] remainingChains = %x DCOC_RES_Chain%d= 'd%d +5212,Iii,[ phy_dev_PkDetCal.c : 193 ] calStatus check failed, remainingChains = %x chain = %d calStatus=%d +5211,I,[ phy_dev_PkDetCal.c : 216 ] D_AGC_PKDET_GAIN is set to %x +5210,iiii,[ phy_dev_PkDetCal.c : 218 ] PKDET_DCOC_RES_OVD for chain %d is = 'd%d is_sbs=%d PKDET_THRES_5G = %d +5209,I,[ phy_dev_PkDetCal.c : 224 ] D_AGC_PKDET_GAIN is set to %x +5208,iiii,[ phy_dev_PkDetCal.c : 226 ] PKDET_DCOC_RES_OVD for chain %d is = 'd%d is_sbs=%d PKDET_THRES_2G = %d +5207,II,[ phy_dev_PkDetCal.c : 113 ] rxChMask=%x,counter:%x +5206,IIII,[ phy_dev_PkDetCal.c : 182 ] PKdet cal check result, RO_AGC_CAL=%x , current chain=%x , remain chain=%x , counter=%x +5205,IIIii,[ phy_dev_PkDetCal.c : 345 ] pkdet_restore :: regCalResult = 0x%x regParameters[0] = 0x%x regParameters[1] = 0x%x chain = %d is_sbs=%d +5204,IIIii,[ phy_dev_PkDetCal.c : 302 ] pkdet_save :: regCalResult = 0x%x regParameters[0] = 0x%x regParameters[1] = 0x%x chain = %d is_sbs=%d +5260,i,[ phy_dev_RxDCOCal.c : 1841 ] RxDCO: Cal failed on chain%d! Writing zeros to DCO LUT... +5259,iii,[ phy_dev_RxDCOCal.c : 1847 ] RXDCO: Using forced value:Ch[%d] (I,Q)=(%d, %d) +5258,,[ phy_dev_RxDCOCal.c : 2049 ] phyRxDCOCal_qcn90xx +5257,,[ phy_dev_RxDCOCal.c : 1871 ] restore_rxdco_calResult +5256,,[ phy_dev_RxDCOCal.c : 1887 ] RXDCO: Allocating memory for DcoLut +5255,I,[ phy_dev_RxDCOCal.c : 1410 ] RXDCO: A_DELAY_USECS cal_done time out calDoneCount=%u +5254,i,[ phy_dev_RxDCOCal.c : 1414 ] RXDCO: A_DELAY_USECS cal_done early calDoneCount=%d +5253,I,[ phy_dev_RxDCOCal.c : 1417 ] do cal after triggered=0x%X +5252,,[ phy_dev_RxDCOCal.c : 1423 ] RXDCO: cal_done failure and reset DO_CALIBRATE bit and CF_RESET_CORE !!!!! +5251,I,[ phy_dev_RxDCOCal.c : 1426 ] WFAX_PHYRF_CAL_SEQ_CTRL_16_L.DO_CALIBRATE= %lu +5250,,[ phy_dev_RxDCOCal.c : 2034 ] rxdco_disable +5249,,[ phy_dev_RxDCOCal.c : 155 ] rxdco_docal +5248,,[ phy_dev_RxDCOCal.c : 271 ] RXDCO: Allocating memory for DcoLut +5247,i,[ phy_dev_RxDCOCal.c : 278 ] rxdco_docal, RXDCO TIMER1: %d + +5246,i,[ phy_dev_RxDCOCal.c : 290 ] rxdco_docal, RXDCO TIMER2: %d +5245,,[ phy_dev_RxDCOCal.c : 298 ] RXDCO: Allocating memory for CalResult +5244,I,[ phy_dev_RxDCOCal.c : 156 ] RxDCO CAL DEBUG VERSION - 0x%x + +5243,i,[ phy_dev_RxDCOCal.c : 263 ] rxdco_docal, RXDCO TIMER0: %d +5242,,[ phy_dev_RxDCOCal.c : 2024 ] rxdco_enable +5241,,[ phy_dev_RxDCOCal.c : 1598 ] index out of range +5240,I,[ phy_dev_RxDCOCal.c : 1285 ] xfem_gpo_cfg= 0x%x +5239,,[ phy_dev_RxDCOCal.c : 999 ] RESULT>>> ch_idx, odac_range, cal_gain, Success, ODAC_I, ODAC_Q, Res_I, Res_Q, interf_pwr, interf_var +5238,II,[ phy_dev_RxDCOCal.c : 1002 ] ch_idx = [0x%x] rxChMask = 0x%x +5237,,[ phy_dev_RxDCOCal.c : 2000 ] rxdco_restore +5236,,[ phy_dev_RxDCOCal.c : 528 ] RXDCO: Cal for MIn Gain +5235,i,[ phy_dev_RxDCOCal.c : 567 ] RxDCO: Cal failed on chain%d! Writing zeros to DCO LUT... +5234,iii,[ phy_dev_RxDCOCal.c : 573 ] RXDCO: Using forced value:Ch[%d] (I,Q)=(%d, %d) +5233,,[ phy_dev_RxDCOCal.c : 533 ] RXDCO: Cal for MAx Gain +5232,,[ phy_dev_RxDCOCal.c : 556 ] RXDCO: Cal for MIn Gain +5231,,[ phy_dev_RxDCOCal.c : 362 ] RXDCO: *************************************** HW cal timeout +5230,i,[ phy_dev_RxDCOCal.c : 371 ] RXDCO: cal done successful, range_iter=%d +5229,i,[ phy_dev_RxDCOCal.c : 390 ] Condition for Cal Success: cal_success= %d +5228,i,[ phy_dev_RxDCOCal.c : 396 ] rxdco_run_rxdco_hw_cal: range_iter= %d +5227,,[ phy_dev_RxDCOCal.c : 444 ] RXDCO: Failed in all tries! +5226,,[ phy_dev_RxDCOCal.c : 1976 ] rxdco_save +5225,,[ phy_dev_RxDCOCal.c : 1991 ] RxDCO: Invalid selection. CAL_SAVE is not supported for raw Cal Results +5224,,[ phy_dev_RxDCOCal.c : 1179 ] RXDCO Cal: rxdco_validate_hw_results +5223,iiiii,[ phy_dev_RxDCOCal.c : 1224 ] ch_idx=%d i=%d Overall_Success=%d RangeOK=%d ResidualOK=%d +5222,ii,[ phy_dev_RxDCOCal.c : 1225 ] RC_CH[%d]= %d +5221,i,[ phy_dev_RxDCOCal.c : 1230 ] RXDCO Cal: rxdco_validate_hw_results: dcoc_range= %d +5220,i,[ phy_dev_RxDCOCal.c : 1242 ] skip_forceTRSW= %d +5219,i,[ phy_dev_RxDCOCal.c : 1253 ] forceTRSW= %d +5218,II,[ phy_dev_RxDCOCal.c : 761 ] mode = [0x%x] rxChMask = 0x%x +5217,i,[ phy_dev_RxDCOCal.c : 771 ] Def_GainTbl_Max = %d +5216,,[ phy_dev_RxDCOCal.c : 1638 ] save_restore_rxdco_DcoLut +5215,I,[ phy_dev_RxDCOCal.c : 1680 ] save_restore_rxdco_DcoLut:::Override mode is not restored for table mode: Value = %x +5266,,[ phy_dev_RxDCOCal_SWPP.c : 540 ] 2G 20MHz + +5265,,[ phy_dev_RxDCOCal_SWPP.c : 586 ] 5G Set0 + +5264,,[ phy_dev_RxDCOCal_SWPP.c : 608 ] 5G Set1 + +5263,,[ phy_dev_RxDCOCal_SWPP.c : 635 ] 6G Set0 + +5262,,[ phy_dev_RxDCOCal_SWPP.c : 657 ] 6G Set1 + +5261,,[ phy_dev_RxDCOCal_SWPP.c : 560 ] 2G 40MHz + +5348,I,[ phy_dev_TPCcal.c : 1074 ] GLUT - Chain %u + +5347,I,[ phy_dev_TPCcal.c : 2587 ] In CLPCModeICOUPLER_IS: txChainMask = 0x%x + +5346,I,[ phy_dev_TPCcal.c : 2640 ] In CLPCModeICOUPLER_PO: txChainMask = 0x%x + +5345,I,[ phy_dev_TPCcal.c : 2705 ] In CLPCModePdet: txChainMask = 0x%x + +5344,I,[ phy_dev_TPCcal.c : 2685 ] In CLPCModeVdet: txChainMask = 0x%x + +5343,,[ phy_dev_TPCcal.c : 1032 ] In clearalut routine, Clearing ALUT indices +5342,,[ phy_dev_TPCcal.c : 999 ] In clearglut routine, Clearing GLUT indices +5341,i,[ phy_dev_TPCcal.c : 2055 ] Q5-TPC: HW_PDET_CAL: Count is %d + +5340,,[ phy_dev_TPCcal.c : 2059 ] Q5-TPC: HW_PDET_CAL: LG CAL PAILED !!!!!!!!! + +5339,i,[ phy_dev_TPCcal.c : 2083 ] Q5-TPC: HW_PDET_CAL: Count is %d + +5338,,[ phy_dev_TPCcal.c : 2087 ] Q5-TPC: HW_PDET_CAL: HG CAL PAILED !!!!!!!!! + +5337,II,[ phy_dev_TPCcal.c : 752 ] PDL_TPC: EnableTPCMode input->tgtPwrClpcThrDb4 %x with shift %x +5336,,[ phy_dev_TPCcal.c : 1228 ] Invalid GLUT numEntries! + +5335,I,[ phy_dev_TPCcal.c : 1248 ] GLUT - Chain %u + +5334,i,[ phy_dev_TPCcal.c : 176 ] HeavyClippingOffsetSetup %d +5333,,[ phy_dev_TPCcal.c : 2296 ] OverrideHwPdetCalValues +5332,I,[ phy_dev_TPCcal.c : 1148 ] PLUT - Chain %u + +5331,IIIIIII,[ phy_dev_TPCcal.c : 502 ] TPC_PHYDEVLIB maxQAM[0..6] %x %x %x %x %x %x %x +5330,IIIIIII,[ phy_dev_TPCcal.c : 504 ] TPC_PHYDEVLIB minQAM[0..6] %x %x %x %x %x %x %x +5329,IIIIIII,[ phy_dev_TPCcal.c : 506 ] TPC_PHYDEVLIB maxQAM MU[0..6] %x %x %x %x %x %x %x +5328,IIIIIII,[ phy_dev_TPCcal.c : 508 ] TPC_PHYDEVLIB minQAM MU[0..6] %x %x %x %x %x %x %x +5327,i,[ phy_dev_TPCcal.c : 389 ] In ProgramGLUTIndicesByRange: powerRange = %d + +5326,,[ phy_dev_TPCcal.c : 393 ] Programming GLUT Indices Range 0 + +5325,,[ phy_dev_TPCcal.c : 411 ] Programming GLUT Indices Range 1 + +5324,,[ phy_dev_TPCcal.c : 424 ] Programming GLUT Indices Range 2 + +5323,,[ phy_dev_TPCcal.c : 437 ] Programming GLUT Indices Range 3 + +5322,i,[ phy_dev_TPCcal.c : 326 ] pktMCSType = %d + +5321,IiI,[ phy_dev_TPCcal.c : 961 ] programGLUT: Address of the GLUt base = 0x%x: GLUT_Idx = %d; Measured power = %hx + +5320,I,[ phy_dev_TPCcal.c : 600 ] TPC_PHYDEVLIB: TPC_GLUT_TARGET_PWR_LEVEL %x +5319,I,[ phy_dev_TPCcal.c : 608 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_4_L %x +5318,I,[ phy_dev_TPCcal.c : 616 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_5_L %x +5317,I,[ phy_dev_TPCcal.c : 624 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_2_L %x +5316,I,[ phy_dev_TPCcal.c : 632 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_3_L %x +5315,I,[ phy_dev_TPCcal.c : 640 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_0_L %x +5314,I,[ phy_dev_TPCcal.c : 648 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_1_L %x +5313,I,[ phy_dev_TPCcal.c : 656 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_6_L %x +5312,I,[ phy_dev_TPCcal.c : 664 ] TPC_PHYDEVLIB: TPC_GLUT_IDX_7_L %x +5311,IIII,[ phy_dev_TPCcal.c : 3203 ] tpcOnepointCal:: thermCalValue %u alphaTherm %u thermGainErrMax %u for chain %u +5310,ii,[ phy_dev_TPCcal.c : 1615 ] TX_CONV: Invalid chain_idx:%d for phy_idx:%d +5309,iii,[ phy_dev_TPCcal.c : 1658 ] TX_CONV: TxConvergenceRegRead phy_idx:%d for chain_idx:%d state:%d +5308,i,[ phy_dev_TPCcal.c : 1659 ] TX_CONV: txgain_count:%d +5307,i,[ phy_dev_TPCcal.c : 1660 ] TX_CONV: stat_latest_fwd:%d +5306,i,[ phy_dev_TPCcal.c : 1661 ] TX_CONV: stat_latest_lb:%d +5305,iii,[ phy_dev_TPCcal.c : 1704 ] TX_CONV: TX_CONVERGENCE_VALIDATION_RETRY_SUCCESS phy_idx:%d chain_idx:%d retry_cnt:%d +5304,iii,[ phy_dev_TPCcal.c : 1709 ] TX_CONV: TX_CONVERGENCE_VALIDATION_RETRY phy_idx:%d chain_idx:%d retry_cnt:%d +5303,iii,[ phy_dev_TPCcal.c : 1712 ] TX_CONV: TX_CONVERGENCE_VALIDATION_FAILURE phy_idx:%d chain_idx:%d retry_cnt:%d +5302,iiii,[ phy_dev_TPCcal.c : 1721 ] TX_CONV: mhz:%d phy_idx:%d chain_idx:%d state:%d +5301,,[ phy_dev_TPCcal.c : 1726 ] TX_CONV: TX_CONVERGENCE_CLEAR +5300,,[ phy_dev_TPCcal.c : 1732 ] TX_CONV: TX_CONVERGENCE_INIT +5299,,[ phy_dev_TPCcal.c : 1737 ] TX_CONV: TX_CONVERGENCE_UPDATE +5298,,[ phy_dev_TPCcal.c : 1745 ] TX_CONV: TX_CONVERGENCE_UPDATE_RETRY +5297,i,[ phy_dev_TPCcal.c : 1758 ] TX_CONV: Invalid state: %d +5296,iiii,[ phy_dev_TPCcal.c : 1683 ] TX_CONV: phy_idx:%d chain_idx:%d txgain_count_delta:%d latest_pwr_delta:%d +5295,,[ phy_dev_TPCcal.c : 1687 ] TX_CONV: TX_CONVERGENCE_VALIDATION_SUCCESS +5294,i,[ phy_dev_TPCcal.c : 2527 ] ov_rel1:%d +5293,,[ phy_dev_TPCcal.c : 1421 ] Printing all the input paramters + +5292,iI,[ phy_dev_TPCcal.c : 1429 ] ForcedDacGain[%d] = 0x%x + +5291,iI,[ phy_dev_TPCcal.c : 1430 ] ForcedTxGainIdx[%d] = 0x%x + +5290,iI,[ phy_dev_TPCcal.c : 1431 ] ForcedGLUTIdx[%d] = 0x%x + +5289,I,[ phy_dev_TPCcal.c : 1439 ] Force target Power = 0x%x + +5288,i,[ phy_dev_TPCcal.c : 1422 ] bandCode - %d + +5287,I,[ phy_dev_TPCcal.c : 1423 ] ForcedTargetPower - 0x%x + +5286,I,[ phy_dev_TPCcal.c : 1424 ] ForceDacGain - 0x%x + +5285,I,[ phy_dev_TPCcal.c : 1425 ] ForceTxGainIdx - 0x%x + +5284,,[ phy_dev_TPCcal.c : 1833 ] -Q5-TPC:- phyLatestAccumulatedCLPCError_qcn90xx was passed NULL Ptr +5283,iII,[ phy_dev_TPCcal.c : 1847 ] -Q5-TPC:- tpcOnepointCal::bandCode %d Chain %u latestAccumulatedClpcError %u +5282,ii,[ phy_dev_TPCcal.c : 1878 ] temp %d = %d +5281,,[ phy_dev_TPCcal.c : 1886 ] phyLatestThermValue_qcn90xx was passed NULL Ptr +5280,iII,[ phy_dev_TPCcal.c : 1892 ] -Q5-TPC :- tpcOnepointCal::phyId %d Chain %u thermalVal %u +5279,,[ phy_dev_TPCcal.c : 3219 ] phyOLPCTempComp_qcn90xx +5278,,[ phy_dev_TPCcal.c : 3232 ] phyOLPCTempUpdate_qcn90xx +5277,IIII,[ phy_dev_TPCcal.c : 100 ] Get the Modes - CLPCMode - 0x%x readTPCStatus - 0x%x Force Mode - 0x%x Forced gain - 0x%x +5276,,[ phy_dev_TPCcal.c : 127 ] Incorrect Test Selection ... +5275,II,[ phy_dev_TPCcal.c : 161 ] set ch %x TPC_OVERRIDE_3 to %x + +5274,iii,[ phy_dev_TPCcal.c : 1799 ] TX_CONV: TX_CONVERGENCE_VALIDATION_FAILURE invalid phy_base_addr:%d phy_idx:%d chain_idx:%d +5273,iii,[ phy_dev_TPCcal.c : 1804 ] TX_CONV: phyInput->bandCode:%d, phyInput->txChMask:%d, tx_active_chain_mask:%d +5272,i,[ phy_dev_TPCcal.c : 1816 ] TX_CONV: End: tx_converged:%d +5271,i,[ phy_dev_TPCcal.c : 229 ] -Q5-TPC : In setupTPC: fcsEnabled = %d + +5270,i,[ phy_dev_TPCcal.c : 235 ] -Q5-TPC : Configuring TPC Mode on PHY with BandCode - %d + +5269,,[ phy_dev_TPCcal.c : 275 ] -Q5-TPC : Completed the Setup TPC settings... +5268,I,[ phy_dev_TPCcal.c : 3305 ] xfem_gpo_cfg= 0x%x +5267,iiii,[ phy_dev_TPCcal.c : 2478 ] PDL_TPC_DBG: pdadc[0] %d dcVal[0] %d pdadc[1] %d dcVal[1] %d +5357,II,[ phy_dev_TxBBFCal.c : 167 ] beol: 0x%x pw: 0x%x + +5356,,[ phy_dev_TxBBFCal.c : 189 ] Beol and/or pw came back as zero - OTP is likely not programmed +5355,iii,[ phy_dev_TxBBFCal.c : 203 ] rSkew: %d rc3Skew: %d rc4Skew: %d +5354,iiiii,[ phy_dev_TxBBFCal.c : 204 ] beol40: %d beol75: %d beol120: %d beol150: %d beol270: %d +5353,IIIII,[ phy_dev_TxBBFCal.c : 238 ] tiaRtuneTarget: %u lvlRtuneTarget: %u bqRtune1Target: %u bqRtune2Target: %u bqRtune3Target: %u +5352,IIIII,[ phy_dev_TxBBFCal.c : 239 ] tiaCcompTarget: %u tiaCfwrdTarget: %u tiaCtuneTarget: %u bqC1CtuneTarget: %u bqC2CtuneTarget: %u +5351,IIIII,[ phy_dev_TxBBFCal.c : 292 ] tiaRtuneTarget: %u lvlRtuneTarget: %u bqRtune1Target: %u bqRtune2Target: %u bqRtune3Target: %u +5350,IIIII,[ phy_dev_TxBBFCal.c : 293 ] tiaCcompTarget: %u tiaCfwrdTarget: %u tiaCtuneTarget: %u bqC1CtuneTarget: %u bqC2CtuneTarget: %u +5349,II,[ phy_dev_TxBBFCal.c : 181 ] beol_1.25: 0x%x pw_1.25: 0x%x + +5370,I,[ phy_dev_RxBBFCal.c : 247 ] rfa_otp_address_base= 0x%08x +5369,,[ phy_dev_RxBBFCal.c : 267 ] Beol came back as Zero - OTP is likely not programmed +5368,,[ phy_dev_RxBBFCal.c : 268 ] no action taken +5367,ii,[ phy_dev_RxBBFCal.c : 273 ] rTune: %d rInt: %d +5366,,[ phy_dev_RxBBFCal.c : 288 ] RXBBFCAL: bw code too large!!! Defaulting to 0 +5365,,[ phy_dev_RxBBFCal.c : 294 ] RXBBFCAL: bw code 80P80 or 160 or 165 +5364,III,[ phy_dev_RxBBFCal.c : 303 ] rc_corner_scale : %u r_corner_scale: %u c_corner_scale: %u +5363,IIII,[ phy_dev_RxBBFCal.c : 392 ] Reg_TIA_Gain: %u tia_Gain_Factor[Reg_TIA_Gain]: %u chainIdx: %u ch_factor[chainIdx] = %u +5362,I,[ phy_dev_RxBBFCal.c : 251 ] hirc 0x%x + +5361,III,[ phy_dev_RxBBFCal.c : 401 ] bq_cfb_total_ref: %u bq_cfb_fixed: %u bq_cfb_tuned = %u +5360,II,[ phy_dev_RxBBFCal.c : 405 ] chainIdx: %u ch_factor_BQ_2G[chainIdx] = %u +5359,II,[ phy_dev_RxBBFCal.c : 410 ] chainIdx: %u ch_factor_BQ_5G[chainIdx] = %u +5358,I,[ phy_dev_RxBBFCal.c : 263 ] hirc_1.25 0x%x + +5391,I,[ rfaConfig.c : 199 ] INVALID FREQUENCY1 %u +5390,III,[ rfaConfig.c : 229 ] NfNbna: LOFrequency=%0.2fMHz NBNA=0x%x NF=0x%x +5389,,[ rfaConfig.c : 1079 ] ironInit +5388,,[ rfaConfig.c : 1101 ] +5387,,[ rfaConfig.c : 798 ] phyRfaIni +5386,,[ rfaConfig.c : 803 ] ERROR! UNKNOWN WCSS ENVIRONMENT +5385,,[ rfaConfig.c : 870 ] RfaIni Done +5384,,[ rfaConfig.c : 1056 ] set channel Agile Recipe Start +5383,,[ rfaConfig.c : 1068 ] set channel Agile Recipe Complete +5382,,[ rfaConfig.c : 1034 ] set channel Recipe Start +5381,,[ rfaConfig.c : 1046 ] set channel Recipe Complete +5380,,[ rfaConfig.c : 1114 ] phySetlowerTxGainIdxWAR_qcn90xx +5379,,[ rfaConfig.c : 369 ] Error! : Synth frequency is out of range from defined list +5378,iii,[ rfaConfig.c : 961 ] freq=%dMHz chanIdx=%d sBandCode=%d +5377,,[ rfaConfig.c : 919 ] aDFS Configuration not supported +5376,,[ rfaConfig.c : 323 ] Error! : Synth frequency is out of range from defined list +5375,I,[ rfaConfig.c : 326 ] da_ctune = 0x%x +5374,I,[ rfaConfig.c : 329 ] da_ctune = 0x%x +5373,,[ rfaConfig.c : 283 ] Error! : Synth frequency is out of range from defined list +5372,III,[ rfaConfig.c : 286 ] ctune[1, 3, 5] = [0x%x, 0x%x, 0x%x] +5371,III,[ rfaConfig.c : 289 ] ctune[1, 3, 5] = [0x%x, 0x%x, 0x%x] +5403,II,[ hca_HwComponentTrxPine_cal.cpp : 172 ] RY: RestoreSetHwChainMasks: forceTxChainMask=%x, forceRxChainMask=%x +5402,i,[ hca_HwComponentTrxPine_cal.cpp : 852 ] VK_NF minNfLimit=%d +5401,Iii,[ hca_HwComponentTrxPine_cal.cpp : 894 ] DBG_NF per chain : rxChainMask 0x%x nfPerChain[%d] = %d +5400,i,[ hca_HwComponentTrxPine_cal.cpp : 278 ] NFCAL, itercount : %d +5399,ii,[ hca_HwComponentTrxPine_cal.cpp : 309 ] NFCAL, Cached value for chain %d NF : %d +5398,ii,[ hca_HwComponentTrxPine_cal.cpp : 324 ] NFCAL, Override Cached value for chain %d NF : %d +5397,iii,[ hca_HwComponentTrxPine_cal.cpp : 797 ] AoA - phy%d, numChains %d, freq %d +5396,iiiiii,[ hca_HwComponentTrxPine_cal.cpp : 809 ] AoA - ch%d, gnIdx %d, dataSz %d, bdfVal %d calVal %d, AoAphase %d +5395,IIIII,[ hca_HwComponentTrxPine_cal.cpp : 609 ] NFCAL backed up phyId %u, rssiThr1aDb %x, rssiThr1bDb %x, rssiThr1cDb %x, rssiThr1dDb %x +5394,IIIII,[ hca_HwComponentTrxPine_cal.cpp : 765 ] NFCAL phyId %u, Result %u, ccaCountMax %u, firPwrThrdB2 %u, relPwrThrdB2 %u +5393,IIIIIIIi,[ hca_HwComponentTrxPine_cal.cpp : 769 ] NFCAL phyId %u, Chan %u, Chain %u, curCCaCnt %u, firpwrCnt %u, relPwrCnt %u, nf_cal_gtc_mask %u, nf %d +5392,i,[ hca_HwComponentTrxPine_cal.cpp : 695 ] VK_NF minNfLimit=%d +5410,I,[ hca_HwComponentTrxPine_calDb.cpp : 890 ] CALDB_DEBUG: channel list table dump 2G 20 %u +5409,I,[ hca_HwComponentTrxPine_calDb.cpp : 894 ] CALDB_DEBUG: channel list table dump 2G 40 %u +5408,I,[ hca_HwComponentTrxPine_calDb.cpp : 898 ] CALDB_DEBUG: channel list table dump 5G 20 %u +5407,I,[ hca_HwComponentTrxPine_calDb.cpp : 902 ] CALDB_DEBUG: channel list table dump 5G 40 %u +5406,I,[ hca_HwComponentTrxPine_calDb.cpp : 906 ] CALDB_DEBUG: channel list table dump 5G 80 %u +5405,I,[ hca_HwComponentTrxPine_calDb.cpp : 910 ] CALDB_DEBUG: channel list table dump 5G 160 %u +5404,i,[ hca_HwComponentTrxPine_calDb.cpp : 914 ] CALDB_DEBUG: groupMapping[i][1]=%d +5413,i,[ hca_HwComponentTrxPine_config.cpp : 198 ] PRDD-DFS ADFS SynthFreq - %d +5412,,[ hca_HwComponentTrxPine_config.cpp : 272 ] Agile DFS Channel in Secondary 80 of 165 MHz +5411,,[ hca_HwComponentTrxPine_config.cpp : 279 ] Agile Non DFS Channel in Secondary 80 of 165 MHz +5423,,[ hca_HwComponentTrxPine_efuse.cpp : 290 ] HcaHwComponentTrxPine_efuse::ReadPerRfa apply_xo_param bit is enabled +5422,ii,[ hca_HwComponentTrxPine_efuse.cpp : 295 ] HcaHwComponentTrxPine_efuse::ReadPerRfa %d, %d +5421,iii,[ hca_HwComponentTrxPine_efuse.cpp : 331 ] HcaHwComponentTrxPine_efuse::WritePerRfa::XO cdacin %d, cdacout %d rc %d +5420,II,[ hca_HwComponentTrxPine_efuse.cpp : 37 ] Error: buffer is out of bounds. offset = %lu, numBytes = %lu + +5419,iII,[ hca_HwComponentTrxPine_efuse.cpp : 44 ] efuseR[%d] ->address [%lu] Value 0x%lx + +5418,II,[ hca_HwComponentTrxPine_efuse.cpp : 58 ] Error: buffer is out of bounds. offset = %lu, numBytes = %lu + +5417,I,[ hca_HwComponentTrxPine_efuse.cpp : 64 ] Error; numBytes not a mulpile of 4, numBytes = %lu + +5416,iII,[ hca_HwComponentTrxPine_efuse.cpp : 88 ] efuseW[%d] ->address [%lu] Value 0x%lx + +5415,III,[ hca_HwComponentTrxPine_efuse.cpp : 111 ] efuseR[%lu] = 0x%lx != 0x%lx + +5414,II,[ hca_HwComponentTrxPine_efuse.cpp : 117 ] Error: %lu/%lu bytes were not written to eFuse correctly. + +5437,ii,[ hca_HwComponentTrxPine_paprd.cpp : 670 ] PAPRD HcaHwComponentTrxPine_paprd::FtmControl : channel %d dpd_enable %d +5436,iii,[ hca_HwComponentTrxPine_paprd.cpp : 695 ] PAPRD ResetParams phyExtn = %d phyId %d enable %d +5435,i,[ hca_HwComponentTrxPine_paprd.cpp : 785 ] PAPRD: Unknown PHY Id %d +5434,I,[ hca_HwComponentTrxPine_paprd.cpp : 83 ] PAPRD: Debugflag entered %x +5433,iii,[ hca_HwComponentTrxPine_paprd.cpp : 657 ] PAPRD SetPaprdEnable : enable %d paprdEnable2G %d paprdEnable5G %d +5432,iiiiii,[ hca_HwComponentTrxPine_paprd.cpp : 740 ] PAPRD: GetDPDChannelRange PHY ID %d isG %d start %d end %d chan start %d chan end %d +5431,iiII,[ hca_HwComponentTrxPine_paprd.cpp : 320 ] PAPRD PDL secondary %d cur cal Temperature %d phyInput->txChMask 0x%x tx mask 0x%x +5430,ii,[ hca_HwComponentTrxPine_paprd.cpp : 153 ] PAPRDTUNING: SETTING - LoopBack Attn | Glut %d Value %d +5429,ii,[ hca_HwComponentTrxPine_paprd.cpp : 158 ] PAPRDTUNING: SETTING - Timing Delay | Glut %d Value %d +5428,iiii,[ hca_HwComponentTrxPine_paprd.cpp : 561 ] PAPRDTUNING: Channel %d chainIdx %d glutIdx %d gainIdx %d + +5427,iiii,[ hca_HwComponentTrxPine_paprd.cpp : 563 ] PAPRDTUNING: Channel %d chainIdx %d glutIdx %d gainIdx %d + +5426,i,[ hca_HwComponentTrxPine_paprd.cpp : 387 ] PAPRD: XmitTrainingFrame failed. Status %d + +5425,iIi,[ hca_HwComponentTrxPine_paprd.cpp : 389 ] PAPRD: XmitTrainingFrame tx_count %d, tx_ctxt_flags 0x%x cal type %d +5424,Ii,[ hca_HwComponentTrxPine_paprd.cpp : 47 ] PAPRD:HcaHwComponentTrxPine_paprd::HwDisable all : PhyBase %8x channel %d +5466,i,[ hca_HwComponentTrxPine_tpc.cpp : 141 ] TPC_DBG:Incorrect tpcFlag value: %d +5465,III,[ hca_HwComponentTrxPine_tpc.cpp : 151 ] TPC_DBG:EnableCLPC clpc thresh from BDF %x clpc thresh in alutGen %x out %x +5464,i,[ hca_HwComponentTrxPine_tpc.cpp : 266 ] HcaHwComponentTrxPine_tpc::EnableCLPC=%d PDET Cal executed +5463,i,[ hca_HwComponentTrxPine_tpc.cpp : 394 ] ov_rel0:%d +5462,iii,[ hca_HwComponentTrxPine_tpc.cpp : 341 ] force glut: chain%d, gainindex%d: dacgain=%d + +5461,i,[ hca_HwComponentTrxPine_tpc.cpp : 410 ] OPC: phyId:%d state +5460,,[ hca_HwComponentTrxPine_tpc.cpp : 655 ] OLPC_TEMP_COMP: Invalid latestThermValue! + +5459,I,[ hca_HwComponentTrxPine_tpc.cpp : 666 ] OLPC_TEMP_COMP: latestThermValue = %u + +5458,II,[ hca_HwComponentTrxPine_tpc.cpp : 732 ] TPC_DUMP: PrimaryChan %u, SecondaryChan %u + +5457,IIIIIIII,[ hca_HwComponentTrxPine_tpc.cpp : 754 ] TPC_DUMP_GLUT: tpcTblIdx %3u | tpcChainIdx %3u | tpcGainIdx %3u | pwrMeas %3d | minDacGain %3d | txGainIdx %3d | clpcError %4d | tpcClPktCnt %3d +5456,IIIIIIIII,[ hca_HwComponentTrxPine_tpc.cpp : 777 ] TPC_DUMP_PLUT: tpcTblIdx %3u | tpcChainIdx %3u | tpcPlutIdx %3u | pdadc[%3u-%3u] 0x%08x | pdadc[%3u-%3u] 0x%08x | +5455,IIIIIIIII,[ hca_HwComponentTrxPine_tpc.cpp : 800 ] TPC_DUMP_ALUT: tpcTblIdx %3u | tpcChainIdx %3u | tpcAlutIdx %3u | Alut tgtPwr Step [%3u-%3u] 0x%08x | Alut tgtPwr Step [%3u-%3u] 0x%08x +5454,IIII,[ hca_HwComponentTrxPine_tpc.cpp : 827 ] TPC_DUMP_COMMON: phyBase 0x%3x | TARGET_PWR_CLPC_THR_CORR %3u | OLPC_MODE %3u | GLUT_DAC_GAIN_CAL %3u | +5453,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 847 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | LATEST_GLUT_IDX %3u | LATEST_TXGAIN_IDX %3u | LATEST_DAC_GAIN %3u | LATEST_TARGET_PWR %3u | +5452,IIII,[ hca_HwComponentTrxPine_tpc.cpp : 850 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | LATEST_ACCUMULATED_CLPC_ERR %4u | LATEST_CLPC_ERR %4u | LATEST_MEAS_PWR_OUT %3u | +5451,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 853 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | LATEST_WSI_TX_GAIN_IDX %3u | LATEST_WSI_CLPC_PKT_TYPE %3u | LATEST_WSI_TPC_PDET_GAIN_IDX %3u | LATEST_WSI_TPC_ATTEN %3u | +5450,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 890 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | txgainIdx %3u | meas_pwr %10d | +5449,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 915 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | txgainIdx %3u | meas_pwr %10d | +5448,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 941 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | txgainIdx %3u | meas_pwr %10d | +5447,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 972 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | pdadc_read %3u | meas_pwr %10d | +5446,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 998 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | pdadc_read %3u | meas_pwr %10d | +5445,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 1024 ] TPC_DUMP_BDF : tpcchan %3u | tpcChainIdx %3u | gainIdx %3u | pdadc_read %3u | meas_pwr %10d | +5444,III,[ hca_HwComponentTrxPine_tpc.cpp : 1043 ] TPC_DUMP_RATEARRAY : index %u ratesArray 0x%x ratesArray2 0x%x +5443,IIIIIi,[ hca_HwComponentTrxPine_tpc.cpp : 1070 ] TPC_DUMP_CTLARRAY: ctlEdgePwrBF[phyId=%u][numChains=%u][bf=%u][rate=%u][numStreams=%u] = %d +5442,IIIIIi,[ hca_HwComponentTrxPine_tpc.cpp : 1095 ] TPC_DUMP_CTLARRAY: ctlEdgePwr160[phyId=%u][numChains=%u][rate=%u][bf=%u][numStreams=%u] = %d +5441,IIIII,[ hca_HwComponentTrxPine_tpc.cpp : 1139 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | RO_PDADC_CLIP_1_CNT_0 %3u | RO_PDADC_CLIP_2_CNT_0 %3u | RO_PDADC_CLIP_3_CNT_0 %3u | RO_PDADC_CLIP_4_CNT_0 %3u | +5440,IIII,[ hca_HwComponentTrxPine_tpc.cpp : 1143 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | RO_LATEST_ATB_VALUE_0 %3u | RO_LATEST_VOLT_VALUE_0 %3u | RO_LATEST_THERM_VAL_0 %2u | +5439,IIII,[ hca_HwComponentTrxPine_tpc.cpp : 1147 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | RO_FULL_PKT_AVG_OUT_0 %3u | RO_LATEST_DC_VALUE_0 %7u | RO_PDACC_AVG_OUT_0 %4u | +5438,IIII,[ hca_HwComponentTrxPine_tpc.cpp : 1151 ] TPC_DUMP_CHAIN: tpcChainIdx %3u | TX_DCOC_OV_0 %14u | TX_GAIN_OV_0 %15u | TX_GAIN_OV_1 %12u | +5471,I,[ hca_HwComponentTrxPine_xtalCal.cpp : 165 ] XTAL_CAL_PINE - Enable flag =0x%x + +5470,i,[ hca_HwComponentTrxPine_xtalCal.cpp : 183 ] XTAL_CAL- CWgain_index=%d +5469,i,[ hca_HwComponentTrxPine_xtalCal.cpp : 189 ] XTAL_CAL clear - gainIdx4XtalCal=%d +5468,iiI,[ hca_HwComponentTrxPine_xtalCal.cpp : 240 ] XTAL_CAL_PINE :SET -Reg_values, chain=%d, idx=%d , value=0x%x + +5467,iiI,[ hca_HwComponentTrxPine_xtalCal.cpp : 304 ] XTAL_CAL_PINE :Clear - Reg_values, chain=%d, idx=%d , value=0x%x + +5549,,[ hca_HwComponentTrxPine_bdf.cpp : 2679 ] TPC_DBG: using 2G data +5548,,[ hca_HwComponentTrxPine_bdf.cpp : 2694 ] TPC_DBG: using 6G data +5547,,[ hca_HwComponentTrxPine_bdf.cpp : 2707 ] TPC_DBG: using 5G2 data +5546,i,[ hca_HwComponentTrxPine_bdf.cpp : 6528 ] TLMM:::: GPIO config Success for freq: %d +5545,,[ hca_HwComponentTrxPine_bdf.cpp : 2857 ] SetCtlTable halphy api called. Access to BDF CTL data temporarily disabled. +5544,,[ hca_HwComponentTrxPine_bdf.cpp : 2862 ] CTL DATA push failed. +5543,iiiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 2873 ] Variables: isG: %d, seq: %d, endflag: %d, totalLen: %d, ctl_ptr: %d, beginning actual address: %d, BDF beginning: %d +5542,i,[ hca_HwComponentTrxPine_bdf.cpp : 2875 ] CTL 2G DATA push under process at seq %d +5541,i,[ hca_HwComponentTrxPine_bdf.cpp : 2876 ] Size being copied in this iteration: %d +5540,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2877 ] Value at address %d before copy: %d +5539,,[ hca_HwComponentTrxPine_bdf.cpp : 2880 ] Invalid CTL data size. Access denied to copy this fragment. Please copy CTL blob from beginning with right size. +5538,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2886 ] Value at address %d after copy: %d +5537,i,[ hca_HwComponentTrxPine_bdf.cpp : 2887 ] Size copied: %d +5536,iiiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 2895 ] Variables: isG: %d, seq: %d, endflag: %d, totalLen: %d, ctl_ptr: %d, beginning actual address: %d, BDF beginning: %d +5535,i,[ hca_HwComponentTrxPine_bdf.cpp : 2897 ] CTL 6G DATA push under process at seq %d +5534,i,[ hca_HwComponentTrxPine_bdf.cpp : 2898 ] Size being copied in this iteration: %d +5533,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2899 ] Value at address %d before copy: %d +5532,,[ hca_HwComponentTrxPine_bdf.cpp : 2902 ] Invalid CTL data size. Access denied to copy this fragment. Please copy CTL blob from beginning with right size. +5531,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2908 ] Value at address %d after copy: %d +5530,i,[ hca_HwComponentTrxPine_bdf.cpp : 2909 ] Size copied: %d +5529,iiiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 2918 ] Variables: isG: %d, seq: %d, endflag: %d, totalLen: %d, ctl_ptr: %d, beginning actual address: %d, BDF beginning: %d +5528,i,[ hca_HwComponentTrxPine_bdf.cpp : 2920 ] CTL 5G DATA push under process at seq %d +5527,i,[ hca_HwComponentTrxPine_bdf.cpp : 2921 ] Size being copied in this iteration: %d +5526,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2922 ] Value at address %d before copy: %d +5525,,[ hca_HwComponentTrxPine_bdf.cpp : 2925 ] Invalid CTL data size. Access denied to copy this fragment. Please copy CTL blob from beginning with right size. +5524,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2931 ] Value at address %d after copy: %d +5523,i,[ hca_HwComponentTrxPine_bdf.cpp : 2932 ] Size copied: %d +5522,,[ hca_HwComponentTrxPine_bdf.cpp : 2937 ] CTL DATA push successful. CTL parsing will be allowed. +5521,i,[ hca_HwComponentTrxPine_bdf.cpp : 6543 ] TLMM:::: DAL_DeviceAttach TLMM: Failed due to Dal result %d + +5520,,[ hca_HwComponentTrxPine_bdf.cpp : 6551 ] TLMM:::: Null pointer exception on gpiointConfig +5519,i,[ hca_HwComponentTrxPine_bdf.cpp : 6557 ] TLMM:::: DalTlmm_ConfigGpio: Failed due to Dal result %d + +5518,i,[ hca_HwComponentTrxPine_bdf.cpp : 6564 ] TLMM:::: DalTlmm_GpioOut: Failed due to Dal result %d + +5517,iii,[ hca_HwComponentTrxPine_bdf.cpp : 5552 ] ACR : cfgCtl2G=%d, isG[2G=1,5G=0,6G=2]=%d, acrSetting=%d + +5516,IIIIIII,[ hca_HwComponentTrxPine_bdf.cpp : 4688 ] tpcOnepointCal:: chosen phyId %u alphaThermFreq[%u] %u curChan %u curChain %u tempIdx %u alphaThermValue %u +5515,i,[ hca_HwComponentTrxPine_bdf.cpp : 2723 ] TPC_DBG: precaldata band %d +5514,,[ hca_HwComponentTrxPine_bdf.cpp : 1200 ] TPC_CTL: Unable to find channel and power index for RD!!!Hence setting max power + +5513,iiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 7016 ] perPacketCMFeatureEnable rcFlag=%d ctlFromBDF=%d ctlPlusComp=%d MaxPwr=%d chain=%d ChMsk=%d +5512,iiiiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 2947 ] RegModeFlags part1 %d %d %d %d %d %d %d %d +5511,iiiiiiii,[ hca_HwComponentTrxPine_bdf.cpp : 2948 ] RegModeFlags part2 %d %d %d %d %d %d %d %d +5510,,[ hca_HwComponentTrxPine_bdf.cpp : 2811 ] Board data address pointer is NULL !! +5509,,[ hca_HwComponentTrxPine_bdf.cpp : 7060 ] DFS_DUMP :: radar det thresh programming +5508,,[ hca_HwComponentTrxPine_bdf.cpp : 7129 ] DFS_DUMP :: radar det thresh programming +5507,ii,[ hca_HwComponentTrxPine_bdf.cpp : 3320 ] phyrf_tpc_device_GetOnePointTpcOffset channel %d chosen_chanid = %d +5506,iiii,[ hca_HwComponentTrxPine_bdf.cpp : 3342 ] tpcOnepointCal::channel:%d cmask:%d is2GHz:%d tpcPowerOffset:%d + +5505,ii,[ hca_HwComponentTrxPine_bdf.cpp : 263 ] RTT - pri20 %d is not valid in dynamicBw %d +5504,i,[ hca_HwComponentTrxPine_bdf.cpp : 298 ] RTT - Invalid dynamicBw %d +5503,i,[ hca_HwComponentTrxPine_bdf.cpp : 112 ] RTT - Error: unsupported pktBw %d +5502,,[ hca_HwComponentTrxPine_bdf.cpp : 2980 ] Board data address pointer is NULL !! +5501,,[ hca_HwComponentTrxPine_bdf.cpp : 1479 ] CTL table under update process. CTL table will not be parsed/updated at this time. +5500,i,[ hca_HwComponentTrxPine_bdf.cpp : 1537 ] CTL6G Value %d + +5499,i,[ hca_HwComponentTrxPine_bdf.cpp : 173 ] RTT - Error: unsupported pktBw %d +5498,ii,[ hca_HwComponentTrxPine_bdf.cpp : 2526 ] ProgramGIcorrGICCAThr is6Ghz:%d and is6gFCC:%d GICorr and GI CCA Thr settings +5497,iii,[ hca_HwComponentTrxPine_bdf.cpp : 5399 ] HC: band: %d, chan %d, hcliteThr %d +5496,IIIIIi,[ hca_HwComponentTrxPine_bdf.cpp : 4475 ] tpcOnepointCal:: chosen phyId %u calFreq[%u] %u curChan %u curChain %u onePointThermOffset %d +5495,i,[ hca_HwComponentTrxPine_bdf.cpp : 217 ] RTT - Invalid dynamicBw %d for 2G +5494,iI,[ hca_HwComponentTrxPine_bdf.cpp : 2556 ] wmi ccaThres programming for phyId:%d reg:0x%x +5493,IIiIIii,[ hca_HwComponentTrxPine_bdf.cpp : 7317 ] GetRssiBypassXlnaOffset : phyId %u, Band %u, rssi %d, rssiByPassXlnaFreqPierIdx %u, rssiByPassXlnaFreqPier2G %u, rssiByPassXlnaSnrThresh2G %d,pRssiByPassXlnaOffset %d +5492,IIiIIii,[ hca_HwComponentTrxPine_bdf.cpp : 7338 ] GetRssiBypassXlnaOffset : phyId %u, Band %u, rssi %d, rssiByPassXlnaFreqPierIdx %u, rssiByPassXlnaFreqPier5G %u, rssiByPassXlnaSnrThresh5G %d,pRssiByPassXlnaOffset %d +5491,IIiIIii,[ hca_HwComponentTrxPine_bdf.cpp : 7360 ] GetRssiBypassXlnaOffset : phyId %u, Band %u, rssi %d, rssiByPassXlnaFreqPierIdx %u, rssiByPassXlnaFreqPier6G %u, rssiByPassXlnaSnrThresh6G %d,pRssiByPassXlnaOffset %d +5490,i,[ hca_HwComponentTrxPine_bdf.cpp : 198 ] RTT - Invalid dynamicBw %d for 5G +5489,IIII,[ hca_HwComponentTrxPine_bdf.cpp : 5891 ] PhyId: %lu, Mode : %lu, Rate : %lu, Target Power: %lu +5488,IIIIIi,[ hca_HwComponentTrxPine_bdf.cpp : 4363 ] tpcOnepointCal:: chosen phyId %u calFreq[%u] %u curChan %u curChain %u onePointTpcGLUTOffset %d +5487,,[ hca_HwComponentTrxPine_bdf.cpp : 3020 ] Board data address pointer is NULL !! +5486,,[ hca_HwComponentTrxPine_bdf.cpp : 3071 ] Board data address pointer is NULL !! +5485,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3110 ] tpcOnepointCal::Saving to BDF txPwrOffset_db8 %d for Band %u, Chain %u,Chan %u, calAttempts %u +5484,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3119 ] tpcOnepointCal::Saving to BDF glutOffset %d for Band %u, Chain %u,Chan %u, calAttempts %u +5483,IIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3129 ] tpcOnepointCal:: Saving to BDF thermalOffset %u for Band %u, Chain %u,Chan %u, calAttempts %u +5482,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3141 ] tpcOnepointCal::Saving to BDF txPwrOffset_db8 %d for Band %u, Chain %u,Chan %u, calAttempts %u +5481,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3150 ] tpcOnepointCal::Saving to BDF glutOffset %d for Band %u, Chain %u,Chan %u, calAttempts %u +5480,IIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3160 ] tpcOnepointCal:: Saving to BDF thermalOffset %u for Band %u, Chain %u,Chan %u, calAttempts %u +5479,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3174 ] tpcOnepointCal::Saving to BDF txPwrOffset_db8 %d for Band %u, Chain %u,Chan %u, calAttempts %u +5478,iIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3183 ] tpcOnepointCal::Saving to BDF glutOffset %d for Band %u, Chain %u,Chan %u, calAttempts %u +5477,IIIII,[ hca_HwComponentTrxPine_bdf.cpp : 3193 ] tpcOnepointCal:: Saving to BDF thermalOffset %u for Band %u, Chain %u,Chan %u, calAttempts %u +5476,i,[ hca_HwComponentTrxPine_bdf.cpp : 7031 ] Per-Packet Chainmask support is Disabled. perPacketCMFeatureEnable = %d +5475,i,[ hca_HwComponentTrxPine_bdf.cpp : 7034 ] Per-Packet Chainmask support is Enabled. perPacketCMFeatureEnable = %d +5474,ii,[ hca_HwComponentTrxPine_bdf.cpp : 7036 ] Per-Packet Chainmask support: perPacketCMFeatureEnable = %d, Debug Log = %d +5473,ii,[ hca_HwComponentTrxPine_bdf.cpp : 7039 ] Per-Packet Chainmask support: perPacketCMFeatureEnable = %d, DebugLogEnabled = %d +5472,ii,[ hca_HwComponentTrxPine_bdf.cpp : 7042 ] Per-Packet Chainmask support: perPacketCMFeatureEnable = %d, DebugLogDisabled = %d +5556,iiIII,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 78 ] phyInput->homeCh %d + phyInput->bandCode %d + phyInput->phyBase 0x%x + phyInput->txChMask 0x%x + phyInput->rxChMask 0x%x + +5555,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 79 ] phyInput->bwCode %d + +5554,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 80 ] ACR : rx_bbf_cal_input->acrSetting %d + +5553,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 128 ] TxBBF and RxBBF cals loadIniMask %d +5552,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 131 ] Skipping TxBBF and RxBBF cals. Reason: No BW/Band change loadIniMask %d +5551,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 145 ] TxBBF cal completed result=%d + +5550,i,[ hca_HwComponentTrxPine_calSmBwFilter.cpp : 155 ] RxBBF cal completed result=%d + +5670,iI,[ hca_HwComponentTrxPine_calSmComb.cpp : 972 ] combCal_SM_save: RXIQ: chainIdx=%d, pStartRxIq=%x +5669,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1020 ] cannot update RxIq table in caldb for chainIdx = %d! +5668,iI,[ hca_HwComponentTrxPine_calSmComb.cpp : 1070 ] combCal_SM_save: TXIQ: chainIdx=%d, pStartTxIq=%x +5667,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1090 ] cannot update TxIq table in caldb for chainIdx = %d! +5666,iIi,[ hca_HwComponentTrxPine_calSmComb.cpp : 1134 ] combCal_SM_save: TXLO: chainIdx=%d, pStartTxLo=%x, 4 * NUM_GAINS_PER_MODE_DIG_ANA_CL=%d +5665,Iii,[ hca_HwComponentTrxPine_calSmComb.cpp : 1143 ] #### SAVE rxChainMask=%x, maxChain=%d, fdmtCombCalInput->chainIdx = %d +5664,ii,[ hca_HwComponentTrxPine_calSmComb.cpp : 1144 ] #### SAVE fdmtCombCalInput->combCalType = %d (COMB_CAL_TYPE_CL=%d) +5663,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1145 ] #### SAVE fdmtCombCalInput->calCmdId=%d +5662,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1146 ] #### ADDR SAVE:pStartTxLo=%x +5661,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1207 ] cannot update txlo table in caldb for chainIdx = %d! +5660,,[ hca_HwComponentTrxPine_calSmComb.cpp : 288 ] APPLICALBE_RESUBMISSION_ONLY:: failure on not getting pStart (= NULL) from caldb! +5659,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1619 ] CAL_COMMON_PARAM pHandle =%x +5658,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1620 ] CAL_COMMON_PARAM calType =%d +5657,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1621 ] CAL_COMMON_PARAM cmdGroupId =%d +5656,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1622 ] CAL_COMMON_PARAM isRestoreOnly =%d +5655,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1623 ] CAL_COMMON_PARAM calTypeVarianceId =%d +5654,iii,[ hca_HwComponentTrxPine_calSmComb.cpp : 1624 ] CAL_COMMON_PARAM reserved =%d %d %d +5653,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1625 ] CAL_COMMON_PARAM (pIn->pHandle).phyId =%x +5652,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1626 ] CAL_COMMON_PARAM halphyBW =%x +5651,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1627 ] PHYDEVLIB_PHY_INPUT phyId =%d +5650,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1628 ] PHYDEVLIB_PHY_INPUT bandCode =%d +5649,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1629 ] PHYDEVLIB_PHY_INPUT bwCode =%d +5648,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1630 ] PHYDEVLIB_PHY_INPUT phyMode =%d +5647,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1631 ] PHYDEVLIB_PHY_INPUT band_center_freq1 =%d +5646,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1632 ] PHYDEVLIB_PHY_INPUT band_center_freq2 =%d +5645,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1633 ] PHYDEVLIB_PHY_INPUT txChMask =%x +5644,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1634 ] PHYDEVLIB_PHY_INPUT rxChMask =%x +5643,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1635 ] PHYDEVLIB_PHY_INPUT phyBase =%x +5642,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1636 ] PHYDEVLIB_PHY_INPUT phyBaseExt =%x +5641,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1637 ] PHYDEVLIB_PHY_INPUT concMode =%d +5640,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1638 ] PHYDEVLIB_PHY_INPUT dynPriChan =%d +5639,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1639 ] PHYDEVLIB_PHY_INPUT homeCh =%d +5638,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1640 ] PHYDEVLIB_PHY_INPUT dtim =%d +5637,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1641 ] PHYDEVLIB_PHY_INPUT extLNA =%d +5636,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1642 ] PHYDEVLIB_PHY_INPUT extPA =%d +5635,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1643 ] PHYDEVLIB_PHY_INPUT phyrf_init_GetPhyRfMode =%x +5634,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1644 ] PHYDEVLIB_PHY_INPUT isSBSmode =%d +5633,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1645 ] PHYDEVLIB_PHY_INPUT loType =%d +5632,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1646 ] PHYDEVLIB_PHY_INPUT dpdMode =%d +5631,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1647 ] PHYDEVLIB_PHY_INPUT loadIniMask =%d +5630,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1648 ] PHYDEVLIB_PHY_INPUT calMask =%d +5629,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1649 ] PHYDEVLIB_PHY_INPUT cal_mode_ctrl =%d +5628,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1651 ] CCAL_INPUT calCmdId =%d +5627,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1652 ] CCAL_INPUT cal_chain_mask =%x +5626,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1653 ] CCAL_INPUT cal_mode =%d +5625,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1654 ] CCAL_INPUT mode (80p80 mode) =%d +5624,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1655 ] CCAL_INPUT fixed_gain =%d +5623,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1656 ] CCAL_INPUT engineSharing =%d +5622,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1657 ] CCAL_INPUT driveTxGLUTIdx =%d +5621,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1658 ] CCAL_INPUT enableBlockAccAvg =%d +5620,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1659 ] CCAL_INPUT blockSize =%d +5619,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1660 ] CCAL_INPUT dcEstWindowSize =%d +5618,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1661 ] CCAL_INPUT numOfBlocks =%d +5617,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1662 ] CCAL_INPUT numSamplesToReadback[0] =%d +5616,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1663 ] CCAL_INPUT numSamplesToReadback[1] =%d +5615,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1664 ] CCAL_INPUT numSamplesToReadback[2] =%d +5614,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1665 ] CCAL_INPUT rxGainSettlingTime =%d +5613,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1666 ] CCAL_INPUT txGainSettlingTime =%d +5612,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1667 ] CCAL_INPUT txShiftSettlingTime =%d +5611,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1668 ] CCAL_INPUT calModeSettlingTime =%d +5610,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1669 ] CCAL_INPUT loopbackSettlingTime =%d +5609,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1670 ] CCAL_INPUT txResidueSettlingTime =%d +5608,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1671 ] CCAL_INPUT numTaps[0] =%d +5607,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1672 ] CCAL_INPUT numTaps[1] =%d +5606,iI,[ hca_HwComponentTrxPine_calSmComb.cpp : 679 ] combCal_SM_restore: RXIQ: chainIdx=%d, pStartRxIq=%x +5605,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 723 ] cannot update RxIq table in caldb for chainIdx = %d! +5604,iI,[ hca_HwComponentTrxPine_calSmComb.cpp : 802 ] combCal_SM_restore: TXIQ: chainIdx=%d, pStartTxIq=%x +5603,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 816 ] cannot update TxIq table in caldb for chainIdx = %d! +5602,iI,[ hca_HwComponentTrxPine_calSmComb.cpp : 868 ] combCal_SM_restore: TXLO: chainIdx=%d, pStartTxLo=%x +5601,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 887 ] cannot update txlo table in caldb for chainIdx = %d! +5600,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1313 ] MODE2CALID in *calMode =%d +5599,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1314 ] MODE2CALID in *calId =%d +5598,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1315 ] MODE2CALID in retValue =%d +5597,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1373 ] OVERRIDE FINALCASE pHandle =%x +5596,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1374 ] OVERRIDE FINALCASE callingContext =%d +5595,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1375 ] OVERRIDE FINALCASE calId =%d +5594,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1376 ] OVERRIDE FINALCASE in finalCase =%d +5593,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1392 ] OVERRIDE FINALCASE out finalCase =%d +5592,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1472 ] FC_HANDLE pHandle =%x +5591,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1473 ] FC_HANDLE phyInput =%x +5590,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1474 ] FC_HANDLE fdmtCombCalInput =%x +5589,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1475 ] FC_HANDLE fdmtCombCalOutput =%x +5588,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1476 ] FC_HANDLE finalCase =%d +5587,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1477 ] FC_HANDLE rfChainMask =%x +5586,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1553 ] #### reset current associated table only +5585,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1564 ] path to call docal due to NEED_TO_DO_CAL, calCmdId =%d +5584,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1400 ] ITER2CMDIDX iterIdx =%d +5583,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1425 ] ITER2CMDIDX cmdIdx =%d +5582,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1437 ] UPDATE_COMBC_TRACKING pHandle =%x +5581,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1438 ] UPDATE_COMBC_TRACKING calMode =%d +5580,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1439 ] UPDATE_COMBC_TRACKING rfChainMask =%x +5579,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1440 ] UPDATE_COMBC_TRACKING subMode80p80 =%d +5578,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1445 ] UPDATE_COMBC_TRACKING COMB_TXLO_TXIQ_RXIQ +5577,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1450 ] UPDATE_COMBC_TRACKING COMB_CAL_MODE_DPD_LP_RXIQ +5576,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1227 ] COMPOSE CMBIQ INPUT pIn =%x +5575,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1228 ] COMPOSE CMBIQ INPUT phyInput =%x +5574,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1229 ] COMPOSE CMBIQ INPUT rxdcoInput =%x +5573,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1230 ] COMPOSE CMBIQ INPUT in *calId =%x +5572,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1289 ] COMPOSE CMBIQ INPUT out *calId =%x +5571,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1331 ] FINALCASE pHandle =%x +5570,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1332 ] FINALCASE callingContext =%d +5569,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1333 ] FINALCASE calMode =%x +5568,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1334 ] FINALCASE calId =%d +5567,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1335 ] FINALCASE rfChainMask =%x +5566,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1336 ] FINALCASE in finalCase =%x +5565,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1337 ] FINALCASE statusChainMask =%x +5564,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1338 ] FINALCASE subMode80p80 =%x +5563,I,[ hca_HwComponentTrxPine_calSmComb.cpp : 1361 ] FINALCASE out finalCase =%x +5562,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1732 ] skipping comb I and Q on DFS channel in cold boot time +5561,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1823 ] CalSM: scan cal end phyId=%d +5560,i,[ hca_HwComponentTrxPine_calSmComb.cpp : 1859 ] CalSM: cal end phyId=%d +5559,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1868 ] :::: phyrf_turn_on is called +5558,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1870 ] :::: phyrf_turn_off is called +5557,,[ hca_HwComponentTrxPine_calSmComb.cpp : 1682 ] Welcome, cal SM for Comb Cal will be created.. + +5678,,[ hca_HwComponentTrxPine_calSmDac.cpp : 162 ] DACCAL_SM ::: SKIP for Scan Radio +5677,I,[ hca_HwComponentTrxPine_calSmDac.cpp : 166 ] DACCAL_SM ::: START resetCause: %x +5676,i,[ hca_HwComponentTrxPine_calSmDac.cpp : 193 ] DACCAL_SM: RECIPE : %d +5675,iiI,[ hca_HwComponentTrxPine_calSmDac.cpp : 206 ] DACCAL_SM: save invoked on chainIdx = %d bandcode= %d pDACData:0x%x +5674,iiI,[ hca_HwComponentTrxPine_calSmDac.cpp : 228 ] DACCAL_SM: restore invoked cal on chainIdx = %d bandcode=%d pDACData:0x%x +5673,,[ hca_HwComponentTrxPine_calSmDac.cpp : 242 ] CalSM: DAC cal end +5672,,[ hca_HwComponentTrxPine_calSmDac.cpp : 250 ] :::: phyrf_turn_on is called +5671,,[ hca_HwComponentTrxPine_calSmDac.cpp : 252 ] :::: phyrf_turn_off is called +5684,iiii,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 86 ] PAPRD : dynGlutEn %d glutTempThrhld %d prevTemp %d currTemp %d +5683,ii,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 126 ] DPD Cal State m/c ::: new_channel_change_request(%d) on channel %d +5682,,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 157 ] PAPRD: DPD disabled for this range of frequency +5681,Iiiiiii,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 184 ] Run DPD Calibration ::: pHdl=%x, phyMode=%d, phyID=%d, channel %d, bwCode %d, txCM=%d, rxCM=%d +5680,iiii,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 188 ] DPD Cal State m/c ::: Channel %d= State %d, DPD Queue %d, tx pkt cnt %d +5679,ii,[ hca_HwComponentTrxPine_calSmDpdMemoryLess.cpp : 198 ] PAPRD: DPD not triggered. phy_mode %d workingChannel %d +5688,,[ hca_HwComponentTrxPine_calSmIbf.cpp : 115 ] HcaHwComponentTrxPine_calSmIbf enter + +5687,,[ hca_HwComponentTrxPine_calSmIbf.cpp : 137 ] :::: phyrf_turn_on is called +5686,,[ hca_HwComponentTrxPine_calSmIbf.cpp : 139 ] :::: phyrf_turn_off is called +5685,,[ hca_HwComponentTrxPine_calSmIbf.cpp : 34 ] Welcome, cal SM for IBF will be created.. + +5689,,[ hca_HwComponentTrxPine_calSmPadroop.cpp : 32 ] Welcome, cal SM for Dadroop Cal will be created.. + +5711,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 428 ] PALCAL STARTED +5710,i,[ hca_HwComponentTrxPine_calSmPdet.cpp : 439 ] PALCAL CONF final pal_cal_input->pcalMethod=%d +5709,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 440 ] PALCAL COMPLETED +5708,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 447 ] :::: phyrf_turn_on is called +5707,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 449 ] :::: phyrf_turn_off is called +5706,i,[ hca_HwComponentTrxPine_calSmPdet.cpp : 213 ] PALCAL_INPUT calCmdId =%d +5705,I,[ hca_HwComponentTrxPine_calSmPdet.cpp : 214 ] PALCAL_INPUT pPalDlyVals =%x +5704,i,[ hca_HwComponentTrxPine_calSmPdet.cpp : 215 ] PALCAL_INPUT pcalMethod =%d +5703,i,[ hca_HwComponentTrxPine_calSmPdet.cpp : 216 ] PALCAL_INPUT pcalOptDoSetEDandDM =%d +5702,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 219 ] PALCAL CONF ModeStatus[phyId=%d][ConfMode=%d][0] =%d +5701,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 220 ] PALCAL CONF ModeStatus[phyId=%d][ConfMode=%d][1] =%d +5700,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 221 ] PALCAL CONF ModeStatus[phyId=%d][ConfMode=%d][2] =%d +5699,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 222 ] PALCAL STORE palCalDlyVals[phyId=%d][%d][0] =%d +5698,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 223 ] PALCAL STORE palCalDlyVals[phyId=%d]{%d][1] =%d +5697,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 224 ] PALCAL STORE palCalDlyVals[phyId=%d][%d][2] =%d +5696,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 225 ] PALCAL STORE palCalDlyVals[phyId=%d][%d][3] =%d +5695,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 226 ] PALCAL STORE palCalDlyVals[phyId=%d][%d][4] =%d +5694,iii,[ hca_HwComponentTrxPine_calSmPdet.cpp : 227 ] PALCAL STORE palCalDlyVals[phyId=%d][%d][5] =%d +5693,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 494 ] PAL cal is disabled by BDF cal mask flag +5692,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 499 ] PAL cal is disabled for HW SBS specific board for now +5691,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 505 ] PAL cal Option control parameter is not equal to desired PAL CAL OPTION, PAL is skipped +5690,,[ hca_HwComponentTrxPine_calSmPdet.cpp : 348 ] Welcome, cal SM for Pdet Cal will be created +5813,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 347 ] CAL_COMMON_PARAM pHandle =%x +5812,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 348 ] CAL_COMMON_PARAM calType =%d +5811,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 349 ] CAL_COMMON_PARAM cmdGroupId =%d +5810,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 350 ] CAL_COMMON_PARAM isRestoreOnly =%d +5809,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 351 ] CAL_COMMON_PARAM calTypeVarianceId =%d +5808,iii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 352 ] CAL_COMMON_PARAM reserved =%d %d %d +5807,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 353 ] CAL_COMMON_PARAM (pIn->pHandle).phyId =%x +5806,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 354 ] CAL_COMMON_PARAM halphyBW =%x +5805,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 355 ] PHYDEVLIB_PHY_INPUT phyId =%d +5804,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 356 ] PHYDEVLIB_PHY_INPUT bandCode =%d +5803,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 357 ] PHYDEVLIB_PHY_INPUT bwCode =%d +5802,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 358 ] PHYDEVLIB_PHY_INPUT phyMode =%d +5801,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 359 ] PHYDEVLIB_PHY_INPUT band_center_freq1 =%d +5800,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 360 ] PHYDEVLIB_PHY_INPUT band_center_freq2 =%d +5799,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 361 ] PHYDEVLIB_PHY_INPUT txChMask =%x +5798,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 362 ] PHYDEVLIB_PHY_INPUT rxChMask =%x +5797,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 363 ] PHYDEVLIB_PHY_INPUT phyBase =%x +5796,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 364 ] PHYDEVLIB_PHY_INPUT phyBaseExt =%x +5795,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 365 ] PHYDEVLIB_PHY_INPUT concMode =%d +5794,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 366 ] PHYDEVLIB_PHY_INPUT dynPriChan =%d +5793,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 367 ] PHYDEVLIB_PHY_INPUT homeCh =%d +5792,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 368 ] PHYDEVLIB_PHY_INPUT dtim =%d +5791,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 369 ] PHYDEVLIB_PHY_INPUT extLNA =%d +5790,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 370 ] PHYDEVLIB_PHY_INPUT extPA =%d +5789,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 371 ] PHYDEVLIB_PHY_INPUT phyrf_init_GetPhyRfMode =%x +5788,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 372 ] PHYDEVLIB_PHY_INPUT isSBSmode =%d +5787,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 373 ] PHYDEVLIB_PHY_INPUT loType =%d +5786,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 374 ] PHYDEVLIB_PHY_INPUT dpdMode =%d +5785,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 375 ] PHYDEVLIB_PHY_INPUT loadIniMask =%d +5784,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 376 ] PHYDEVLIB_PHY_INPUT calMask =%x +5783,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 377 ] PHYDEVLIB_PHY_INPUT cal_mode_ctrl =%d +5782,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 378 ] PHYDEVLIB_PHY_INPUT boardId =%d +5781,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 379 ] PHYDEVLIB_PHY_INPUT phySscanEnMask =0x%x +5780,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 380 ] PHYDEVLIB_PHY_INPUT phyDfsEnMask =0x%x +5779,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 698 ] ITER2CMDIDX iterIdx =%d +5778,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 724 ] ITER2CMDIDX cmdIdx =%d +5777,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 271 ] MODE2CALID in *calMode =%d +5776,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 272 ] MODE2CALID in *calId =%d +5775,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 273 ] MODE2CALID in retValue =%d +5774,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 493 ] FC_HANDLE pHandle =%x +5773,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 494 ] FC_HANDLE phyInput =%x +5772,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 495 ] FC_HANDLE rxdcoInput =%x +5771,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 497 ] FC_HANDLE finalCase =%d +5770,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 498 ] FC_HANDLE rfChainMask =%x +5769,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 499 ] FC_HANDLE subMode80p80 =%d +5768,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 538 ] RXDCO ****** invokes rxdco RESTORE ***** +5767,iii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 596 ] RXDCO ::: BF CAL_RESTORE bwCode=%d, chainIdx=%d homech=%d +5766,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 599 ] RXDCO restore ::: pDcoLut chain 0: img:%d real:%d +5765,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 602 ] RXDCO restore ::: pDcoLut chain 1: img:%d real:%d +5764,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 605 ] RXDCO restore ::: pDcoLut chain 2: img:%d real:%d +5763,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 609 ] RXDCO restore ::: pDcoLut chain 3: img:%d real:%d +5762,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 631 ] FC_HANDLE autoIterativeIdx =%d +5761,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 632 ] FC_HANDLE rxdcoInput->calCmdId =%d +5760,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 633 ] FC_HANDLE iterIdx =%d +5759,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 634 ] RXDCO ****** invokes rxdco cal ***** +5758,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 638 ] RXDCO ::: recipe : %d , cal_mode : %d +5757,iii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 653 ] RXDCO ::: BF CAL_SAVE bwCode=%d, chainIdx=%d homeCh=%d +5756,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 656 ] RXDCO save ::: pDcoLut chain 0: img:%d real:%d +5755,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 659 ] RXDCO save ::: pDcoLut chain 1: img:%d real:%d +5754,ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 662 ] RXDCO save ::: pDcoLut chain 2: img:%d real:%d +5753,iii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 666 ] RXDCO save ::: pDcoLut chain 3: img:%d real:%d range:%d +5752,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 671 ] RXDCO ::: AFTER:CAL_SAVE convertNewRxdcoLutfromCalDb failed + +5751,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 469 ] OVERRIDE FINALCASE out finalCase =%d +5750,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 734 ] UPDATE_RXDCO_TRACKING pHandle =%x +5749,iii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 735 ] UPDATE_RXDCO_TRACKING calMode =%d (RXDCO_CAL_MODE_NORMAL=%d,RXDCO_CAL_MODE_DTIM=%d +5748,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 736 ] UPDATE_RXDCO_TRACKING rfChainMask =%x +5747,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 737 ] UPDATE_RXDCO_TRACKING subMode80p80 =%d +5746,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 742 ] UPDATE_RXDCO_TRACKING RXDCO_CAL_MODE_NORMAL +5745,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 747 ] UPDATE_RXDCO_TRACKING RXDCO_CAL_MODE_NORMAL +5744,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 293 ] COMPOSE RXDCO INPUT pIn =%x +5743,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 294 ] COMPOSE RXDCO INPUT phyInput =%x +5742,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 295 ] COMPOSE RXDCO INPUT rxdcoInput =%x +5741,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 296 ] COMPOSE RXDCO INPUT pUnionDcoLut =%x +5740,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 297 ] COMPOSE RXDCO INPUT in *calId =%x +5739,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 315 ] COMPOSE RXDCO INPUT override bwCode =%x +5738,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 339 ] COMPOSE RXDCO INPUT out *calId =%x +5737,iI,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 805 ] RXDCO ::: save TablePtr chain:%d = %p +5736,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 830 ] NEED_TO_DO_CAL:: cannot update rxdco caldb for chainIdx = %d! +5735,iI,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 764 ] RXDCO ::: restore TablePtr chain:%d = %p +5734,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 785 ] APPLICALBE_RESUBMISSION_ONLY:: failure on not getting pStart (= NULL) from caldb! +5733,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 396 ] FINALCASE pHandle =%x +5732,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 397 ] FINALCASE callingContext =%d +5731,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 398 ] FINALCASE calMode =%x +5730,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 399 ] FINALCASE calId =%d +5729,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 400 ] FINALCASE rfChainMask =%x +5728,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 401 ] FINALCASE in finalCase =%x +5727,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 402 ] FINALCASE statusChainMask =%x +5726,I,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 403 ] FINALCASE subMode80p80 =%x +5725,Ii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 436 ] FINALCASE out finalCase =%x for calMode=%d +5724,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 899 ] RXDCO SM COLDBOOT SUPPORT VERSION ************** +5723,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 912 ] RXDCO SM FINAL VERSION bandw=%d>>>>>>>>>>>>>>>>>> +5722,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 931 ] RXDCO callingContext = %d --> AFS_CAL_PROFILE +5721,iiii,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 961 ] RXDCO SM::bwCode=%d, bandCode=%d, calCmdId=%d, cal_mode=%d +5720,IiiiI,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 962 ] RXDCO SM::rxChainMask=%x, homech=%d, phyMode=%d, dtim=%d boardId=0x%x +5719,iiIi,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 967 ] RXDCO SM SKIPPED:::finalCase = %d, doCalFlag = %d, skipMask = %x, previousCalResultAtHomeCh=%d +5718,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 972 ] RXDCO SM::FCS mode, so for home channel noCal +5717,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 974 ] RXDCO SM::FCS calflag is wrong, should be doCal +5716,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 998 ] RXDCO SM FINALCASE BASED +5715,i,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 1003 ] RXDCO callingContext = %d restore doCalFlag--> AFS_CAL_PROFILE +5714,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 1013 ] :::: phyrf_turn_on is called +5713,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 1015 ] :::: phyrf_turn_off is called +5712,,[ hca_HwComponentTrxPine_calSmRxDco.cpp : 1018 ] RXDCO SM FINAL VERSION <<<<<<<<<<<<<<<<<< +5838,IIIIIIII,[ wmi_svc.c : 362 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x +5837,III,[ wmi_svc.c : 373 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x +5836,IIII,[ wmi_svc.c : 376 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x 0x%08x +5835,IIIII,[ wmi_svc.c : 379 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x +5834,IIIIII,[ wmi_svc.c : 382 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x +5833,IIIIIII,[ wmi_svc.c : 385 ] WMI_CMD_PARAMS 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x +5832,Ii,[ wmi_svc.c : 555 ] WMI_CMD_RX CmdId=0x%x Len=%d +5831,III,[ wmi_svc.c : 562 ] WMI Logging debug stats total_drops = 0x%x resume_cnts = 0x%x, suspend_cnts = 0x%x +5830,I,[ wmi_svc.c : 367 ] WMI_CMD_PARAMS 0x%08x +5829,I,[ wmi_svc.c : 576 ] WMI_SEND_EVENT_WRONG_TLV CmdId/EventId = 0x%x +5828,iiiI,[ wmi_svc.c : 601 ] WMI_CMD_RX process inline cmd=%d length=%d endPt=%d, pHTCbuf=%x +5827,I,[ wmi_svc.c : 604 ] start page log CmdId = 0x%x +5826,I,[ wmi_svc.c : 611 ] stop page log CmdId = 0x%x +5825,iiiIi,[ wmi_svc.c : 642 ] WMI_CMD_RX send dispatch msg to threads, cmd=%d length=%d endPt=%d, pHTCbuf=%x msg_size=%d +5824,II,[ wmi_svc.c : 370 ] WMI_CMD_PARAMS 0x%08x 0x%08x +5823,Ii,[ wmi_svc.c : 878 ] WMI_EVT completion msg to RT pEvt=%p, thread_id=%d +5822,iiI,[ wmi_svc.c : 1834 ] WMI_EVT msg to HIF EventId=%d length=%d pEvt=%p +5821,Ii,[ wmi_svc.c : 1980 ] WMI_EVT_SEND EvtId=0x%x ep=%d +5820,iiIi,[ wmi_svc.c : 2023 ] RT WMI_EVT EventId=%d length=%d pEvt=%p filterAction:%d +5819,I,[ wmi_svc.c : 2075 ] pending EventId = 0x%x +5818,II,[ wmi_svc.c : 2087 ] WMI_EVENT_SEND drop EventId = 0x%x, action:0x%x +5817,iiiI,[ wmi_svc.c : 836 ] WMI_CMD_RX cmd comp. handle in hif --free buf cmd=%d length=%d endPt=%d, pHTCbuf=%x +5816,iiiI,[ wmi_svc.c : 773 ] WMI_CMD_RX handle in BE cmd=%d length=%d endPt=%d, pHTCbuf=%x +5815,iiiI,[ wmi_svc.c : 739 ] WMI_CMD_RX handle in data offload cmd=%d length=%d endPt=%d, pHTCbuf=%x +5814,iiiI,[ wmi_svc.c : 807 ] WMI_CMD_RX handle in RT cmd=%d length=%d endPt=%d, pHTCbuf=%x +5839,iii,[ evt_tracer.c : 1023 ] suspend_en:%d, module %d, evt_trace_in_suspend %d +5841,Iii,[ platform_page_log.c : 485 ] PF ADDR:0x%X, THREAD:%d, DSR:%d +5840,Iii,[ platform_page_log.c : 492 ] PF ADDR:0x%X, THREAD:%d, DSR:%d +5842,,[ platform_ce.c : 112 ] platform_ce_send_use_hif: Sending msg to HIF thread to do SYNC CE copy +5848,i,[ platform_gpio.c : 291 ] ERR: setting output for input GPIO %d +5847,,[ platform_gpio.c : 315 ] TLMM unit test: wrong num of args. +5846,I,[ platform_gpio.c : 320 ] TLMM unit test: reg addr (0x%x) is out of range of TLMM. +5845,II,[ platform_gpio.c : 330 ] TLMM unit test: Op: Read, Reg: 0x%x, Value: 0x%x. +5844,II,[ platform_gpio.c : 338 ] TLMM unit test: Op: Write, Reg: 0x%x, Value: 0x%x. +5843,,[ platform_gpio.c : 341 ] TLMM unit test: wrong operation: read: 0, write: 1. +5862,I,[ platform_bdf_and_cal.c : 1143 ] Initiating cal download (halphy)...temp_bin = 0x%x +5861,i,[ platform_bdf_and_cal.c : 1163 ] Cal download complete...cal file size = %d +5860,Ii,[ platform_bdf_and_cal.c : 1213 ] Initiating cal update (halphy)...temp_bin = 0x%x | file_size = %d +5859,,[ platform_bdf_and_cal.c : 1351 ] QMI Platform: Cold Cal done signal received +5858,,[ platform_bdf_and_cal.c : 1403 ] QMI Platform: Sending FW READY ind... +5857,,[ platform_bdf_and_cal.c : 1417 ] QMI Platform: Sending FW READY ind... +5856,i,[ platform_bdf_and_cal.c : 691 ] platorm_idx__download_req= %d, +5855,i,[ platform_bdf_and_cal.c : 526 ] platorm_idx= %d, +5854,i,[ platform_bdf_and_cal.c : 655 ] platform_proc_bdf_download_req: BDF download done, current_size = %d, +5853,i,[ platform_bdf_and_cal.c : 615 ] platform_proc_bdf_download_req: BDF download curr_size = %d, +5852,I,[ platform_bdf_and_cal.c : 294 ] QMI Platform: Cal download REQ received, seg_id 0x%x +5851,i,[ platform_bdf_and_cal.c : 201 ] QMI Platform: Cal Update remaining bytes = %d, +5850,,[ platform_bdf_and_cal.c : 1297 ] sending cal_done indication before changing state +5849,,[ platform_bdf_and_cal.c : 1339 ] QMI Platform: Sending FW READY ind... +5863,II,[ platform_m3.c : 1787 ] M3 DDR address = %ull, size = 0x%x +5864,ii,[ platform.c : 3316 ] AFC MEM Alloc size (%d) != Req Size (%d) +5874,,[ platform_tsens.c : 1586 ] TSENS_MEMORY_ALLOC_FAILED +5873,iiiiiiii,[ platform_tsens.c : 1604 ] TSENS_PID_GET_CONFIG temp_thresh_1|2|3 %d %d %d kp = %d, ki = %d, kd = %d, max_temp = %d sensor = %d +5872,iiiiii,[ platform_tsens.c : 1633 ] TSENS_PID_SET_CONFIG algo = %d, temp_thresh_1|2 %d %d, kp = %d, ki = %d, kd = %d +5871,iiIIiii,[ platform_tsens.c : 1435 ] TSENS_PID_DATA temp_thresh_1|2 %d %d kp|ki = 0x%x, hyst|slope_dc = 0x%x, param_id = %d, val1 = %d, val2 = %d +5870,,[ platform_tsens.c : 1460 ] TSENS_MEMORY_ALLOC_FAILED +5869,iIIIIIIi,[ platform_tsens.c : 1504 ] TSENS_TEMP_INFO algo = %d, err_info = 0x%x 0x%x 0x%x, num_client|num_sensor = 0x%x, temp_zone|sensor_id = 0x%x, flags = 0x%x last_dc = %d +5868,iiiiiiii,[ platform_tsens.c : 1514 ] TSENS_TEMP_OFFSET [0-7] %d %d %d %d %d %d %d %d +5867,iiiiiiii,[ platform_tsens.c : 1480 ] TSENS_PID_DATA temp_thresh_1|2|3 %d %d %d kp = %d, ki = %d, kd = %d, max_temp = %d sensor = %d +5866,iiiiiiii,[ platform_tsens.c : 1490 ] TSENS_TEMP_DATA_DEGC [0-7] %d %d %d %d %d %d %d %d +5865,iiiiii,[ platform_tsens.c : 1543 ] TSENS_PID_UPDATE_PARAM algo = %d, temp_thresh_1|2 %d %d, kp = %d, ki = %d, kd = %d +5879,iIIIIIIII,[ txde_thread.c : 109 ] %d [RING_STATS:RING_EMPTY]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +5878,iIIIIIIII,[ txde_thread.c : 148 ] %d [RING_STATS:RING_50_75_PER]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +5877,iIIIIIIII,[ txde_thread.c : 161 ] %d [RING_STATS:(RINGSZ - 12)]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +5876,iIIIIIIII,[ txde_thread.c : 122 ] %d [RING_STATS:RING_FULL]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +5875,iIIIIIIII,[ txde_thread.c : 135 ] %d [RING_STATS:RING_0_50_PER]==> 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x + +5880,,[ aes_gcm.c : 318 ] GCM: Tag mismatch +5881,III,[ cmnos_intmux.c : 97 ] cmnos_intmux_dsr_attach error: handler = %p, pinum = %p, pparg=%p +5889,IIII,[ cmnos_allocram.c : 552 ] unknown proxy_flag:0x%x, ret:0x%x, ret1:0x%x,ret2:0x%x +5888,IiII,[ cmnos_allocram.c : 266 ] arena_flags: 0x%x, bytes:%d, call1:0x%x, call2:0x%x + +5887,,[ cmnos_allocram.c : 723 ] Dumping allocram info into buffer... +5886,i,[ cmnos_allocram.c : 784 ] Wrote: %d bytes +5885,,[ cmnos_allocram.c : 803 ] Creating file... +5884,,[ cmnos_allocram.c : 656 ] BEGIN: cmnos_allocram_info_dump() +5883,iIIiii,[ cmnos_allocram.c : 659 ] arena: %d, start: 0x%p, current: 0x%p, used = %d, remaining: %d, num_allocs: %d + +5882,,[ cmnos_allocram.c : 701 ] END: cmnos_allocram_info_dump() +5902,II,[ cmnos_thread.c : 4831 ] assert:r0=0x%x, r1=0x%x + +5901,III,[ cmnos_thread.c : 5026 ] assert:r0=0x%x, r1=0x%x, line:0x%x + +5900,III,[ cmnos_thread.c : 3148 ] thread exit exception:r0=0x%x, r1=0x%x, line:0x%x + +5899,ii,[ cmnos_thread.c : 4038 ] CMNOS_Buf_Alloc_Failure Buffer_Full_thread_id = %d Current_thread_id = %d + +5898,Iiiii,[ cmnos_thread.c : 3939 ] LACK ROOM IN %s THREAD'S MSG QUEUE FIFO (need %d, have %d); readIndex=%d writeIndex=%d +5897,iii,[ cmnos_thread.c : 1966 ] APP THREAD ID %d thread stack: %dB used, %dB unused + +5896,,[ cmnos_thread.c : 1793 ] cmnos_threads_delete + +5895,I,[ cmnos_thread.c : 1813 ] cmnos_threads_delete: wait for thread app id 0x%x to exit + +5894,I,[ cmnos_thread.c : 1816 ] cmnos_threads_delete: thread app id 0x%x is done + +5893,,[ cmnos_thread.c : 1875 ] cmnos_threads_delete: clean up mutex locks + +5892,,[ cmnos_thread.c : 1884 ] cmnos_threads_delete: clean up thread barriers + +5891,,[ cmnos_thread.c : 1895 ] cmnos_threads_delete: do global cleanups + +5890,I,[ cmnos_thread.c : 1800 ] cmnos_threads_delete: send exit to 0x%x thread app id + +5906,,[ platform_init.c : 62 ] WLAN Platform: Starting wlan tasks... +5905,,[ platform_init.c : 270 ] QMI Platform: Sending msg to RT thread to do cold cal init... +5904,i,[ platform_init.c : 91 ] WLAN Adrastea/MSL HW init, enable_hw_debug =%d +5903,,[ platform_init.c : 151 ] QMI Platform: Starting wlan tasks... +5908,,[ platform_deinit.c : 40 ] QMI Platform: Deinit started... +5907,,[ platform_deinit.c : 90 ] QMI Platform: Threads killed... +5909,ii,[ platform_common.c : 148 ] plat_set_one_ce_service_map_cfg: ERROR - idx %d > PIPE_TO_CE_MAP_CNT %d +5913,,[ platform_athdiag.c : 239 ] plat_athdiag_proc_read_req: Sending msg to RT thread to do athdiag read +5912,,[ platform_athdiag.c : 182 ] plat_athdiag_white_list_add: only support limited security area +5911,IIi,[ platform_athdiag.c : 380 ] QMI Platform: Athdiag read REQ received...offset = 0x%x | mem_type = 0x%x | data_len = %d +5910,IIi,[ platform_athdiag.c : 468 ] QMI Platform: Athdiag write REQ received...offset = 0x%x | mem_type = 0x%x | data_len = %d +5914,II,[ platform_thread.c : 609 ] M3SSR recipe complete mac_id:%x ts:%x +5982,II,[ qmi_platform.c : 926 ] Error code 0x%x in msg_id 0x%x +5981,,[ qmi_platform.c : 2829 ] QDSS mem info REQ received +5980,i,[ qmi_platform.c : 2627 ] qmi_plat_check_state: error - received CFG download REQ at wrong state %d +5979,i,[ qmi_platform.c : 2592 ] platform_proc_qdss_cfg_download_req: QDSS cfg download curr_size = %d, +5978,i,[ qmi_platform.c : 2608 ] platform_proc_qdss_cfg_download_req: QDSS cfg download done, current_size = %d, +5977,IIII,[ qmi_platform.c : 560 ] qmi_event_history_log: msg_id = 0x%x, client_handle = 0x%x, event = 0x%x, tick = 0x%x +5976,i,[ qmi_platform.c : 190 ] qmi_plat_check_state: error - received HOST_CAP_REQ at wrong state %d +5975,iI,[ qmi_platform.c : 219 ] qmi_plat_check_state: ERROR: wrong state %d to receive msg_id 0x%x +5974,i,[ qmi_platform.c : 230 ] qmi_plat_check_state: error - received MSA INFO REQ at wrong state %d +5973,i,[ qmi_platform.c : 239 ] qmi_plat_check_state: error - received MSA READY REQ at wrong state %d +5972,i,[ qmi_platform.c : 248 ] qmi_plat_check_state: error - sending MSA READY IND at wrong state %d +5971,i,[ qmi_platform.c : 258 ] qmi_plat_check_state: error - received CAPABILITY REQ at wrong state %d +5970,i,[ qmi_platform.c : 282 ] qmi_plat_check_state: error - received CAPABILITY REQ at wrong state %d +5969,i,[ qmi_platform.c : 315 ] qmi_plat_check_state: error - received BDF DOWNLOAD REQ at wrong state %d +5968,i,[ qmi_platform.c : 201 ] qmi_plat_check_state: WARNING: wrong state to send remote ddr mem cfg indication, state = %d +5967,i,[ qmi_platform.c : 327 ] qmi_plat_check_state: error - received CAL_REPORT REQ at wrong state %d +5966,i,[ qmi_platform.c : 340 ] qmi_plat_check_state: error - received M3_INFO REQ at wrong state %d +5965,i,[ qmi_platform.c : 382 ] qmi_plat_check_state: error - send FW INIT Done at wrong state %d +5964,Ii,[ qmi_platform.c : 419 ] qmi_plat_check_state: error - Try to send FW Ready ind at wrong mode 0x%x and wrong state %d +5963,i,[ qmi_platform.c : 429 ] qmi_plat_check_state: error - received CFG REQ at wrong state %d +5962,Ii,[ qmi_platform.c : 447 ] qmi_plat_check_state: error - received MODE REQ w/ mode = 0x%x at wrong state %d +5961,Ii,[ qmi_platform.c : 461 ] qmi_plat_check_state: error - received MODE REQ w/ mode = 0x%x at wrong state %d +5960,Ii,[ qmi_platform.c : 484 ] qmi_plat_check_state: error - received MODE REQ w/ mode = 0x%x at wrong state %d +5959,i,[ qmi_platform.c : 498 ] qmi_plat_check_state: error - Try to send CAL Done Ind at wrong state %d +5958,Ii,[ qmi_platform.c : 506 ] qmi_plat_check_state: error - Try to send Cal Done Ind at wrong mode 0x%x and wrong state %d +5957,iI,[ qmi_platform.c : 210 ] qmi_plat_check_state: ERROR: wrong state %d to receive msg_id 0x%x +5956,i,[ qmi_platform.c : 518 ] qmi_plat_check_state: error - Try to send SOC WAKE at wrong state %d +5955,i,[ qmi_platform.c : 532 ] qmi_plat_check_state: error - Try to send SOC WAKE at wrong state %d +5954,I,[ qmi_platform.c : 762 ] Client with handle 0x%x connected +5953,I,[ qmi_platform.c : 793 ] Client with handle 0x%x disconnected +5952,,[ qmi_platform.c : 2029 ] QMI Platform: sending QMI_WLFW_FILE_SAVE_IND_V01 +5951,I,[ qmi_platform.c : 1993 ] QMI Platform: BDF download REQ received, seg_id 0x%x +5950,,[ qmi_platform.c : 2365 ] QMI Platform: Cal report REQ received +5949,,[ qmi_platform.c : 2336 ] QMI Platform: Cap REQ received +5948,ii,[ qmi_platform.c : 2056 ] QMI Platform: QMI_WLFW_FILE_DATA_REQ_V01 received, invalid parameter, req_id %d, cur_seg_id %d +5947,i,[ qmi_platform.c : 2066 ] QMI Platform: QMI_WLFW_FILE_DATA_REQ_V01 received, cur_seg_id %d +5946,,[ qmi_platform.c : 2070 ] QMI Platform: QMI_WLFW_FILE_DATA_REQ_V01 received, cur_seg_id +5945,ii,[ qmi_platform.c : 2098 ] QMI Platform: QMI_WLFW_FILE_DATA_RESP_V01 sent, data %d, end %d +5944,II,[ qmi_platform.c : 1139 ] wlfw_handle_host_cap_req: num_clients=%x, nm_modem=%x +5943,,[ qmi_platform.c : 1292 ] QMI Platform: Ind register REQ received +5942,I,[ qmi_platform.c : 1326 ] Client with unique ID 0x%x registering +5941,I,[ qmi_platform.c : 1331 ] Client with unique ID 0x%x found in client_list +5940,i,[ qmi_platform.c : 1874 ] QMI Platform: INI REQ received, debug mode = %d +5939,ii,[ qmi_platform.c : 1892 ] QMI Platform: recieved INI REQ, enablefwlog_valid = %d, enablefwlog = %d +5938,ii,[ qmi_platform.c : 1896 ] QMI Platform: recieved INI REQ, enablefwlog_valid = %d, enablefwlog = %d +5937,ii,[ qmi_platform.c : 1903 ] QMI Platform: recieved INI REQ, enablefwlog_valid = %d, enablefwlog = %d +5936,ii,[ qmi_platform.c : 1907 ] QMI Platform: Did not recieve INI REQ, enablefwlog_valid = %d, enablefwlog = %d +5935,Ii,[ qmi_platform.c : 2318 ] QMI Platform: M3 download REQ received, paddr = %ul, size = %d +5934,,[ qmi_platform.c : 2386 ] QMI Platform: MAC addr REQ received +5933,IIIIII,[ qmi_platform.c : 2433 ] Valid mac addr received from modem NV: %x : %x : %x : %x : %x : %x +5932,,[ qmi_platform.c : 2106 ] I shouldn't have been called F +5931,I,[ qmi_platform.c : 2713 ] QDSS mode REQ received, mode = 0x%x +5930,i,[ qmi_platform.c : 1399 ] wlfw_handle_remote_ddr_mem_req: INFO: num_mem_cfg = %d +5929,,[ qmi_platform.c : 2510 ] QMI Platform: Shutdown req recvd +5928,i,[ qmi_platform.c : 2530 ] QMI Platform: platform state %d +5927,,[ qmi_platform.c : 1732 ] QMI Platform: Wlan Cfg REQ received +5926,i,[ qmi_platform.c : 1819 ] wlfw_handle_wlan_cfg_req: svc_cfg_len - %d +5925,I,[ qmi_platform.c : 1466 ] QMI Platform: Wlan mode REQ received, mode = 0x%x +5924,,[ qmi_platform.c : 1493 ] wlfw_handle_wlan_mode_req: hw_debug_valid = d, hw_debug = d +5923,,[ qmi_platform.c : 2163 ] WHY DID YOU CALL ME +5922,,[ qmi_platform.c : 1043 ] QMI Platform: sending QMI_WLFW_RESPOND_GET_INFO_IND_V01 +5921,II,[ qmi_platform.c : 653 ] Ind with id 0x%x sent to client handle 0x%x +5920,II,[ qmi_platform.c : 682 ] Ind with id 0x%x not sent to client handle 0x%x +5919,II,[ qmi_platform.c : 664 ] Setting fw_status_mask in handle 0x%x with FW READY; new value = 0x%x +5918,II,[ qmi_platform.c : 671 ] Handle 0x%x, fw_status_mask = 0x%x +5917,II,[ qmi_platform.c : 677 ] Indication sent failed. Err code = 0x%x id = 0x%x +5916,,[ qmi_platform.c : 1013 ] QMI Platform: sending QMI_WLFW_QDSS_TRACE_FREE_IND_V01 +5915,,[ qmi_platform.c : 988 ] QMI Platform: sending QMI_WLFW_QDSS_TRACE_SAVE_IND_V01 +5983,I,[ pool_mgr_api.c : 408 ] product resulting in buffer overflow: num_of_elem * elem_sz = 0x%x +5985,i,[ latency_profile.c : 452 ] profile_report: #profiles enabled > WMI limit (=%d) +5984,i,[ latency_profile.c : 488 ] profile_report: could not alloc, size=%d +5991,IIIi,[ sm.c : 345 ] SM: %x:%x:%p : allocation from event pool failed for event %d +5990,IIIi,[ sm.c : 232 ] SM: %x:%x:%p : invalid event %d +5989,IIIiIII,[ sm.c : 253 ] [SM:RcvEvt] CurS:%x<-Evt:%x mod_id/inst/evt_q=%x vapid =%d ext1/2/3=0x%x/0x%x/0x%x +5988,IIIii,[ sm.c : 262 ] SM: %x :%x :%p : event %d not handled in state %d +5987,iiIIiIIII,[ sm.c : 278 ] [SM:RcvEvt] Evt:%d not handled in CurS:%d mod_id=%x instance=%x vapid =%d make_sm = 0x%x extra = 0x%x extra2 = 0x%x extra3 = 0x%x +5986,IIIiIII,[ sm.c : 396 ] [SM:ChgSta] CurS:%x->NxtS:%x mod_id/inst/evt_q=%x vapid=%d ext1/2/3=0x%x/0x%x/0x%x diff --git a/qca/ath11k-firmware/files/QCN9000/Notice.txt b/qca/ath11k-firmware/files/QCN9000/Notice.txt new file mode 100644 index 000000000..1c77b82f5 --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/Notice.txt @@ -0,0 +1,786 @@ +This Notice.txt file contains certain notices of software components included with the software that Qualcomm Atheros, Inc. ("Qualcomm Atheros") is required to provide you. Except where prohibited by the open source license, the content of this notices file is only provided to satisfy Qualcomm Atheros's attribution and notice requirement; your use of these software components together with the Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as "Software") is subject to the terms of your agreement from Qualcomm Atheros. Compliance with all copyright laws and software license agreements included in the notice section of this file are the responsibility of the user. Except as may be granted by separate express written agreement, this file provides no license to any patents, trademarks, copyrights, or other intellectual property of Qualcomm Incorporated or any of its subsidiaries. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated trademarks are used with permission. Other products and brand names may be trademarks or registered trademarks of their respective owners. + +-------------------- + + /* + * WPA definitions shared between hostapd and wpa_supplicant + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + + /* WPA/RSN - Shared functions for supplicant and authenticator + * EAP common peer/server definitions + * EAP peer state machines (RFC 4137) + * Copyright (c) 2002-2018, Jouni Malinen + * + * This software may be distributed under the terms of the BSD license. + * See README for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * AES-based functions + * + * + * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394) + * - One-Key CBC MAC (OMAC1) hash with AES-128 + * - AES-128 CTR mode encryption + * - AES-128 EAX mode encryption/decryption + * - AES-128 CBC + * + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * SHA1 hash implementation and interface functions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * Notifications and licenses are retained for attribution purposes only. + */ +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / wrapper functions for crypto libraries + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + * + * This file defines the cryptographic functions that need to be implemented + * for wpa_supplicant and hostapd. When TLS is not used, internal + * implementation of MD5, SHA1, and AES is used and no external libraries are + * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the + * crypto library used by the TLS implementation is expected to be used for + * non-TLS needs, too, in order to save space by not implementing these + * functions twice. + * + * Wrapper code for using each crypto library is in its own file (crypto*.c) + * and one of these files is build and linked in to provide the functions + * defined here. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - Common definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant - WPA state machine and EAPOL-Key processing + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * WPA Supplicant / Configuration file structures + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + /* + * Copyright (c) 2008, Atheros Communications Inc. + * + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * Qualcomm Atheros, Inc. has chosen to take madwifi subject to the BSD license and terms. + * + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - Internal WPA state machine definitions + * Copyright (c) 2004-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant - WPA definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +/* + * wpa_supplicant/hostapd / common helper functions, etc. + * Copyright (c) 2002-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +-------------------- + + * Australian Public Licence B (OZPLB) + * + * Version 1-0 + * + * Copyright (c) 2004, National ICT Australia + * Copyright (c) 2007, Open Kernel Labs, Inc. + * + * All rights reserved. + * + * Developed by: Embedded, Real-time and Operating Systems Program (ERTOS) + * National ICT Australia + * http://www.ertos.nicta.com.au + * + * Permission is granted by National ICT Australia, free of charge, to + * any person obtaining a copy of this software and any associated + * documentation files (the "Software") to deal with the Software without + * restriction, including (without limitation) the rights to use, copy, + * modify, adapt, merge, publish, distribute, communicate to the public, + * sublicense, and/or sell, lend or rent out copies of the Software, and + * to permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimers. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimers in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of National ICT Australia, nor the names of its + * contributors, may be used to endorse or promote products derived + * from this Software without specific prior written permission. + * + * EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT + * PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND + * NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS, + * WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS + * REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE, + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, + * THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF + * ERRORS, WHETHER OR NOT DISCOVERABLE. + * + * TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL + * NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL + * THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER + * LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR + * OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS + * OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR + * OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT, + * CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN + * CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER + * DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS + * CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS, + * DAMAGES OR OTHER LIABILITY. + * + * If applicable legislation implies representations, warranties, or + * conditions, or imposes obligations or liability on National ICT + * Australia or one of its contributors in respect of the Software that + * cannot be wholly or partly excluded, restricted or modified, the + * liability of National ICT Australia or the contributor is limited, to + * the full extent permitted by the applicable legislation, at its + * option, to: + * a. in the case of goods, any one or more of the following: + * i. the replacement of the goods or the supply of equivalent goods; + * ii. the repair of the goods; + * iii. the payment of the cost of replacing the goods or of acquiring + * equivalent goods; + * iv. the payment of the cost of having the goods repaired; or + * b. in the case of services: + * i. the supplying of the services again; or + * ii. the payment of the cost of having the services supplied again. + * + * The construction, validity and performance of this licence is governed + * by the laws in force in New South Wales, Australia. + +-------------------- + + * Copyright (c) 2002-2004, Karlsruhe University + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + /* + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + * + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +-------------------- + + * AUTHOR: Aaron D. Gifford - http://www.aarongifford.com/ + * + * Copyright (c) 2000-2001, Aaron D. Gifford + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTOR(S) ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTOR(S) BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1982, 1986, 1990, 1991, 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +# Copyright (c) 2012-2015 Qualcomm Atheros, Inc. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + +-------------------- + +/* $OpenBSD: string.h,v 1.17 2006/01/06 18:53:04 millert Exp $ */ +/* $NetBSD: string.h,v 1.6 1994/10/26 00:56:30 cgd Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 5.10 (Berkeley) 3/9/91 + */ + +-------------------- + + // Copyright (c) 1991, 1993 + // The Regents of the University of California. All rights reserved. + // $ATH_LICENSE_NULL$ + // + // Redistribution and use in source and binary forms, with or without + // modification, are permitted provided that the following conditions + // are met: + // 1. Redistributions of source code must retain the above copyright + // notice, this list of conditions and the following disclaimer. + // 2. Redistributions in binary form must reproduce the above copyright + // notice, this list of conditions and the following disclaimer in the + // documentation and/or other materials provided with the distribution. + // 3. All advertising materials mentioning features or use of this software + // must display the following acknowledgement: + // This product includes software developed by the University of + // California, Berkeley and its contributors. + // 4. Neither the name of the University nor the names of its contributors + // may be used to endorse or promote products derived from this software + // without specific prior written permission. + // + // THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + // ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + // SUCH DAMAGE. + +-------------------- + + * Copyright (c) 1998, 2010 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +-------------------- + +/* + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +-------------------- + +** Copyright (c) 2004-2010, Atheros Communications Inc. +** +** Permission to use, copy, modify, and/or distribute this software for any +** purpose with or without fee is hereby granted, provided that the above +** copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +** WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +** ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +** WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +** ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +** OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +** +** This module is the Atheros specific ioctl/iwconfig/iwpriv interface +** to the ATH object, normally instantiated as wifiX, where X is the +** instance number (e.g. wifi0, wifi1). +** +** This provides a mechanism to configure the ATH object within the +** Linux OS enviornment. This file is OS specific. + +-------------------- + +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + */ + +/* + * For this file, which was received with alternative licensing options for + * distribution, Qualcomm Atheros, Inc. has selected the BSD license. + */ + +//- +// Copyright (c) 2002-2004 Sam Leffler, Errno Consulting +// All rights reserved. +// $ATH_LICENSE_NULL$ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer, +// without modification. +// 2. Redistributions in binary form must reproduce at minimum a disclaimer +// similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +// redistribution must be conditioned upon including a substantially +// similar Disclaimer requirement for further binary redistribution. +// 3. Neither the names of the above-listed copyright holders nor the names +// of any contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// Alternatively, this software may be distributed under the terms of the +// GNU General Public License ("GPL") version 2 as published by the Free +// Software Foundation. +// +// NO WARRANTY +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +// THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +// IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGES. + +-------------------- + + /* + * AES SIV (RFC 5297) + * Copyright (c) 2013 Cozybit, Inc. + * + * This software may be distributed under the terms of the BSD license. + */ + +-------------------- + + * Copyright 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + +-------------------- + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +-------------------- + +// This code implements the MD5 message-digest algorithm. +// The algorithm is due to Ron Rivest. This code was +// written by Colin Plumb in 1993, no copyright is claimed. +// This code is in the public domain; do with it what you wish. +// +// Equivalent code is available from RSA Data Security, Inc. +// This code has been tested against that, and is equivalent, +// except that you don't need to include two pages of legalese +// with every copy. +// + +-------------------- diff --git a/qca/ath11k-firmware/files/QCN9000/amss.bin b/qca/ath11k-firmware/files/QCN9000/amss.bin new file mode 100644 index 000000000..24060b813 Binary files /dev/null and b/qca/ath11k-firmware/files/QCN9000/amss.bin differ diff --git a/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature.ini b/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature.ini new file mode 100644 index 000000000..9b87b0cf9 --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature.ini @@ -0,0 +1,108 @@ +# +# Copyright (c) 2018-2021 Qualcomm Technologies, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# + +#Host firstly will be looking for board specific macros, if not available default macros for that specific chip is to be used. +#So add all the default strings at the end of each board type. +#Format for HK V1/V2 chipsets with same boardnames : +# boardname_v_default_ +#Format for other boards : +# boardname_default_ + +#IMPORTANT NOTE: +# 1. Duplicate entries for same board name should not be added. Please modify only the values and not add new lines for same board +# 2. Do not add boardname search strings in comments. As the host script search patterns are for boardnames in the file and does not ignore comments +############################################################################################################# +#CYP+Pine RDP's +#Cypress+Pine RDP, For Pine PCIE radio +ap-cp01-c3_qcn9000_pci0_enable_daemon_support=1 +ap-cp01-c3_qcn9000_pci0_enable_cold_boot_support=1 +ap-cp01-c3_qcn9000_pci0_enable_qdss_tracing=1 + +#Cypress+Pine+Pine(Scan) RDP, For Pine PCIE0 +ap-cp01-c5_qcn9000_pci0_enable_daemon_support=1 +ap-cp01-c5_qcn9000_pci0_enable_cold_boot_support=1 +ap-cp01-c5_qcn9000_pci0_enable_qdss_tracing=1 + +#Cypress+Pine+Pine(Scan) RDP, For Pine PCIE1(Scan) +ap-cp01-c5_qcn9000_pci1_enable_daemon_support=1 +ap-cp01-c5_qcn9000_pci1_enable_cold_boot_support=1 +ap-cp01-c5_qcn9000_pci1_enable_qdss_tracing=1 + +############################################################################################################# +#HK+Pine -RDPs +#HK10 - Pine RDPs +#For HK10-C1 board - Pine PCIE 0 +ap-hk10-c1_qcn9000_pci0_enable_daemon_support=1 +ap-hk10-c1_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk10-c1_qcn9000_pci0_enable_qdss_tracing=1 + +#For HK10-C1 board - Pine PCIE 1 +ap-hk10-c1_qcn9000_pci1_enable_daemon_support=1 +ap-hk10-c1_qcn9000_pci1_enable_cold_boot_support=1 +ap-hk10-c1_qcn9000_pci1_enable_qdss_tracing=1 + +#For HK10-C2 board - Pine PCIE 0 +ap-hk10-c2_qcn9000_pci0_enable_daemon_support=1 +ap-hk10-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk10-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#For HK10-C2 board - Pine PCIE 1 +ap-hk10-c2_qcn9000_pci1_enable_daemon_support=1 +ap-hk10-c2_qcn9000_pci1_enable_cold_boot_support=1 +ap-hk10-c2_qcn9000_pci1_enable_qdss_tracing=1 + +#HK14 - Pine RDPs : Pine6G + HK(2G+5G) in HK09 platform +#For HK14 board - Pine PCIE 0 +ap-hk14_qcn9000_pci0_enable_daemon_support=1 +ap-hk14_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk14_qcn9000_pci0_enable_qdss_tracing=1 + +#HK01-C6 - Pine RDPs : Pine6G + HK(2G+5G) in HK01 platform +#For HK01-C6 board - Pine PCIE 0 +ap-hk01-c6_qcn9000_pci0_enable_daemon_support=1 +ap-hk01-c6_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk01-c6_qcn9000_pci0_enable_qdss_tracing=1 +#No explicit defualt tags for HK10/HK14 board as of now. All Combinations of HK10/HK14 are explicitily addressed above. +############################################################################################################# +#Maple+Pine RDP's +ap-mp03.1_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.1_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.1_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine emmc +ap-mp03.1-c2_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.1-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.1-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine+Spruce +ap-mp03.3_qcn9000_pci1_enable_daemon_support=1 +ap-mp03.3_qcn9000_pci1_enable_cold_boot_support=1 +ap-mp03.3_qcn9000_pci1_enable_qdss_tracing=1 + +#Maple+Pine+Spruce emmc +ap-mp03.3-c2_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.3-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.3-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine+Pine +ap-mp03.4-c1_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.4-c1_qcn9000_pci0_enable_cold_boot_support=0 +ap-mp03.4-c1_qcn9000_pci0_enable_qdss_tracing=1 + +ap-mp03.4-c1_qcn9000_pci1_enable_daemon_support=1 +ap-mp03.4-c1_qcn9000_pci1_enable_cold_boot_support=0 +ap-mp03.4-c1_qcn9000_pci1_enable_qdss_tracing=1 + +#Alder Silicon RDPs +ap-al02-c1_qcn9000_pci0_enable_daemon_support=1 +ap-al02-c1_qcn9000_pci0_enable_cold_boot_support=1 +ap-al02-c1_qcn9000_pci0_enable_qdss_tracing=1 + +ap-al02-c1_qcn9000_pci1_enable_daemon_support=1 +ap-al02-c1_qcn9000_pci1_enable_cold_boot_support=1 +ap-al02-c1_qcn9000_pci1_enable_qdss_tracing=1 +############################################################################################################# + diff --git a/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature_512P.ini b/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature_512P.ini new file mode 100644 index 000000000..24c25eb59 --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/firmware_rdp_feature_512P.ini @@ -0,0 +1,108 @@ +# +# Copyright (c) 2018-2021 Qualcomm Technologies, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# + +#Host firstly will be looking for board specific macros, if not available default macros for that specific chip is to be used. +#So add all the default strings at the end of each board type. +#Format for HK V1/V2 chipsets with same boardnames : +# boardname_v_default_ +#Format for other boards : +# boardname_default_ + +#IMPORTANT NOTE: +# 1. Duplicate entries for same board name should not be added. Please modify only the values and not add new lines for same board +# 2. Do not add boardname search strings in comments. As the host script search patterns are for boardnames in the file and does not ignore comments +############################################################################################################# +#CYP+Pine -RDPs +#Cypress+Pine RDP, For Pine PCIE radio +ap-cp01-c3_qcn9000_pci0_enable_daemon_support=1 +ap-cp01-c3_qcn9000_pci0_enable_cold_boot_support=1 +ap-cp01-c3_qcn9000_pci0_enable_qdss_tracing=1 + +#Cypress+Pine+Pine(Scan) RDP, For Pine PCIE0 +ap-cp01-c5_qcn9000_pci0_enable_daemon_support=1 +ap-cp01-c5_qcn9000_pci0_enable_cold_boot_support=1 +ap-cp01-c5_qcn9000_pci0_enable_qdss_tracing=1 + +#Cypress+Pine+Pine(Scan) RDP, For Pine PCIE1(Scan) +ap-cp01-c5_qcn9000_pci1_enable_daemon_support=1 +ap-cp01-c5_qcn9000_pci1_enable_cold_boot_support=1 +ap-cp01-c5_qcn9000_pci1_enable_qdss_tracing=1 +############################################################################################################# +#HAWKEYE + pine -RDPs +#For HK10-C1 board - Pine PCIE 0 +ap-hk10-c1_qcn9000_pci0_enable_daemon_support=1 +ap-hk10-c1_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk10-c1_qcn9000_pci0_enable_qdss_tracing=1 + +#For HK10-C1 board - Pine PCIE 1 +ap-hk10-c1_qcn9000_pci1_enable_daemon_support=1 +ap-hk10-c1_qcn9000_pci1_enable_cold_boot_support=1 +ap-hk10-c1_qcn9000_pci1_enable_qdss_tracing=1 + +#For HK10-C2 board - Pine PCIE 0 +ap-hk10-c2_qcn9000_pci0_enable_daemon_support=1 +ap-hk10-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk10-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#For HK10-C2 board - Pine PCIE 1 +ap-hk10-c2_qcn9000_pci1_enable_daemon_support=1 +ap-hk10-c2_qcn9000_pci1_enable_cold_boot_support=1 +ap-hk10-c2_qcn9000_pci1_enable_qdss_tracing=1 + +#HK14 - Pine RDPs : Pine6G + HK(2G+5G) in HK09 platform +#For HK14 board - Pine PCIE 0 +ap-hk14_qcn9000_pci0_enable_daemon_support=1 +ap-hk14_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk14_qcn9000_pci0_enable_qdss_tracing=1 + +#HK01-C6 - Pine RDPs : Pine6G + HK(2G+5G) in HK01 platform +#For HK01-C6 board - Pine PCIE 0 +ap-hk01-c6_qcn9000_pci0_enable_daemon_support=1 +ap-hk01-c6_qcn9000_pci0_enable_cold_boot_support=1 +ap-hk01-c6_qcn9000_pci0_enable_qdss_tracing=1 +#No explicit defualt tags for HK10/HK14 board as of now. All Combinations of HK10/HK14 are explicitily addressed above. +############################################################################################################# +#MAPLE+Pine-RDPS +#Maple+Pine +ap-mp03.1_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.1_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.1_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine emmc +ap-mp03.1-c2_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.1-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.1-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine+Spruce +ap-mp03.3_qcn9000_pci1_enable_daemon_support=1 +ap-mp03.3_qcn9000_pci1_enable_cold_boot_support=1 +ap-mp03.3_qcn9000_pci1_enable_qdss_tracing=1 + +#Maple+Pine+Spruce emmc +ap-mp03.3-c2_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.3-c2_qcn9000_pci0_enable_cold_boot_support=1 +ap-mp03.3-c2_qcn9000_pci0_enable_qdss_tracing=1 + +#Maple+Pine+Pine +ap-mp03.4-c1_qcn9000_pci0_enable_daemon_support=1 +ap-mp03.4-c1_qcn9000_pci0_enable_cold_boot_support=0 +ap-mp03.4-c1_qcn9000_pci0_enable_qdss_tracing=1 + +ap-mp03.4-c1_qcn9000_pci1_enable_daemon_support=1 +ap-mp03.4-c1_qcn9000_pci1_enable_cold_boot_support=0 +ap-mp03.4-c1_qcn9000_pci1_enable_qdss_tracing=1 + +#Alder Silicon RDPs +ap-al02-c1_qcn9000_pci0_enable_daemon_support=1 +ap-al02-c1_qcn9000_pci0_enable_cold_boot_support=1 +ap-al02-c1_qcn9000_pci0_enable_qdss_tracing=1 + +ap-al02-c1_qcn9000_pci1_enable_daemon_support=1 +ap-al02-c1_qcn9000_pci1_enable_cold_boot_support=1 +ap-al02-c1_qcn9000_pci1_enable_qdss_tracing=1 + +############################################################################################################# + diff --git a/qca/ath11k-firmware/files/QCN9000/fw_version.txt b/qca/ath11k-firmware/files/QCN9000/fw_version.txt new file mode 100644 index 000000000..e6f36bb9e --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/fw_version.txt @@ -0,0 +1 @@ +WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 v1 diff --git a/qca/ath11k-firmware/files/QCN9000/m3.bin b/qca/ath11k-firmware/files/QCN9000/m3.bin new file mode 100644 index 000000000..6ec907b5b Binary files /dev/null and b/qca/ath11k-firmware/files/QCN9000/m3.bin differ diff --git a/qca/ath11k-firmware/files/QCN9000/qdss_trace_config.bin b/qca/ath11k-firmware/files/QCN9000/qdss_trace_config.bin new file mode 100644 index 000000000..98dd6d642 --- /dev/null +++ b/qca/ath11k-firmware/files/QCN9000/qdss_trace_config.bin @@ -0,0 +1,105 @@ +//This comment and parser will ignore +//Tracer scenario(or commands) always +//starts with start keyword +//Below commands to enable Event traces on UMAC,MAC0,MAC1 +seq_start; +seq_type:mem_req; +//memory size always given in KB. beow example reserves 3 buffers segments of 16 KB. +sink:etr_ddr,0x1,0x400; +seq_end; +//Below commands to enable Event traces on UMAC,MAC0,MAC1 +seq_start; +seq_type:mac_event_trace; +sink:etr_ddr; +subsys_cfg_start:mac0; +swevt:0x0, 0xFFFFFFFF,0xFFFFFFFF,0x0,0x0; +hwsch:0x1, 0x6FFFF3, 0x60000, 0x00000000, 0x00000000; +rxdma:0x2, 0x3F37FE7F, 0x00017F04, 0x00000000, 0x00000000; +crypto:0x3, 0xF7DB3770, 0x00000000, 0x00000000, 0x00000000; +txpcu:0x4, 0xD6C7F4E7, 0x200801D2, 0x00000000, 0x00000000; +rxole:0x5, 0x00000000, 0xFFC00000, 0x00000000, 0x00000000; +txole:0x6, 0x641F0FF4, 0x6FF0F000, 0x00000000, 0x00000000; +mxi:0x7, 0x00122234, 0x00000000, 0x00000000, 0x00000000; +txdma:0x8, 0x39800064, 0x00000084, 0x00000000, 0x00000000; +sfm:0x9, 0xC03C0F03, 0xE, 0x00000000, 0x00000000; +subsys_cfg_end:mac0; +//subsys_cfg_start:mac1; +//swevt:0x0, 0xFFFFFFFF,0xFFFFFFFF,0x0,0x0; +//hwsch:0x8, 0xEFFF1, 0x1036052C, 0x00000000, 0x00000000; +//rxdma:0x9, 0x00003400, 0x00008000, 0x00000000, 0x00000000; +//crypto:0xa, 0xf79B3770, 0x00000000, 0x00000000, 0x00000000; +//txpcu:0xb, 0xD6C7B447, 0x000000D2, 0x00000000, 0x00000000; +//txdma:0xc, 0x00001734, 0x00000084, 0x00000000, 0x00000000; +//txole:0xd, 0x7C0FFE26, 0x00000000, 0x00000000, 0x00000000; +//pdg:0xe, 0x00C00002, 0x00000000, 0x00000000, 0x00000000; +//subsys_cfg_end:mac1; +swap:0xFFFFFFFF; +trigger_start:trc; +wfi:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +ts0:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +ts1:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +ts2:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +ts3:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +ts4:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +trigger_end:trc; +memw:0xFFFFFFFF,0xFFFFFFFF; +seq_end; +// Below commands to enable obo trace on the mac0 +//seq_start; +//seq_type:mac_obo_trace; +//sink:etb_wcss; +//subsys_cfg_start:mac0; +//hwsch:0x1,0xABCDABCD; +//subsys_cfg_end:mac0; +//swap:0xABCDABCD; +//trigger_start:trc; +//wfi:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//ts0:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//ts1:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//ts2:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//ts3:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//ts4:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; +//trigger_end:trc; +//memw:0xFFFFFFFF,0xFFFFFFFF; +//seq_end; +// Below commands to enable TLV trace on the mac0 +//seq_start; +//seq_type:mac_tlv_trace; +//sink:etb_wcss; +//subsys_cfg_start:mac0; +//tlv_port:PDG_TXDMA_TLV; +//subsys_cfg_end:mac0; +//seq_end; +// Below commands to enable q6 etm +//seq_start; +//seq_type:q6_etm_trace; +//sink:etr_ddr; +//seq_end; +// Below commands to enable umac noc traces +//seq_start; +//seq_type:umac_noc_trace; +//sink:etb_wcss; +//ctrl:0x12; +//port_sel:0x4; +//lut:0xA; +//routeid_base:0x01000000; +//routeid_mask:0x01c00000; +//addr_lo:0x0; +//addr_hi:0x0; +//win_size:0x25; +//req_opcode:0x3; +//res_status:0x3; +//fltr_len:0xF; +//async_period:0xC; +//seq_end; +// Below commands to enable umac noc traces +//seq_start; +//seq_type:phy_tlv_trace; +//sink:etr_ddr; +//seq_end; +//seq_start; +//seq_type:phy_event_trace; +//sink:etr_ddr; +//phya:0x1,0x1; +//phyb:0x1,0x1; +//seq_end; diff --git a/qca/ath11k-fwtest/Makefile b/qca/ath11k-fwtest/Makefile new file mode 100644 index 000000000..1fc7d167a --- /dev/null +++ b/qca/ath11k-fwtest/Makefile @@ -0,0 +1,45 @@ +include $(TOPDIR)/rules.mk + +PKG:=ath11k-fwtest +PKG_NAME:=$(PKG) +PKG_VERSION:=1.0 + +PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG) + +include $(INCLUDE_DIR)/package.mk + +define Package/ath11k-fwtest + SECTION:=QCA + CATEGORY:=QCA + URL:=http://www.qca.qualcomm.com + MAINTAINER:=Qualcomm Atheros, Inc. + TITLE:=QCA ath11k fwtest utility + DEPENDS:= +libnl +endef + +define Package/ath11k-fwtest/description + This Package contains ath11k fwtest utility +endef + +TARGET_CFLAGS += -O1 -Wall -fpie -I. -I$(STAGING_DIR)/usr/include/ -I $(STAGING_DIR)/usr/include/mac80211/uapi -I $(STAGING_DIR)/usr/include/libnl3 +TARGET_LDFLAGS += -lnl-3 -lnl-genl-3 + +define Build/Compile + mkdir -p $(PKG_BUILD_DIR)/install/sbin + $(MAKE) -C $(PKG_BUILD_DIR)/ \ + CC="$(TARGET_CC)" \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/ath11k-fwtest $(1)/usr/sbin +endef + +define Package/$(PKG_NAME)/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/ath11k-fwtest $(1)/usr/sbin +endef + +$(eval $(call BuildPackage,$(PKG_NAME))) diff --git a/qca/ath11k-fwtest/src/Makefile b/qca/ath11k-fwtest/src/Makefile new file mode 100644 index 000000000..b30c1c404 --- /dev/null +++ b/qca/ath11k-fwtest/src/Makefile @@ -0,0 +1,29 @@ +# Makefile for ath11k-fwtest + +ALL=ath11k-fwtest + +OBJS = fwtest.o + +# Making default targets: +all: local install + @echo All done in `pwd` + +local : $(ALL) + @echo Made outputs in `pwd` + +install: local + @cp -a -f ath11k-fwtest ./install/sbin + @echo Installed outputs from `pwd` + +fwtest.o : fwtest.c + $(CC) -c $(CFLAGS) fwtest.c + +ath11k-fwtest: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) -o $@ + +# Remove all generated files +clean: + @rm -f *.o + +.PHONY: all clean install + diff --git a/qca/ath11k-fwtest/src/fwtest.c b/qca/ath11k-fwtest/src/fwtest.c new file mode 100644 index 000000000..40b5c5fe9 --- /dev/null +++ b/qca/ath11k-fwtest/src/fwtest.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2014, 2019 Qualcomm Technologies, Inc. + * + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#define ATH11K_TM_DATA_MAX_LEN 5000 +#define ATH11K_WMI_UNIT_TEST_MAX_NUM_ARGS 100 + +#define WMI_TAG_ARRAY_UINT32 16 +#define WMI_TAG_VDEV_SET_PARAM_CMD 95 +#define WMI_TAG_PDEV_SET_PARAM_CMD 82 +#define WMI_TAG_UNIT_TEST_CMD 327 + +#define WMI_TLV_HDR_SIZE (sizeof(unsigned int)) + +#define WMI_TLV_LEN_SHIFT 0 +#define WMI_TLV_LEN_MASK 0x0000ffff + +#define WMI_TLV_TAG_SHIFT 16 +#define WMI_TLV_TAG_MASK 0xffff0000 + +#define FIELD_PREP(a, b) (((a) << (b##_SHIFT)) & (b##_MASK)) + +#define WMI_GRP_FWTEST 0x1f +#define WMI_GRP_PDEV 0x04 +#define WMI_GRP_VDEV 0x05 +#define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) +#define WMI_UNIT_TEST_CMDID (WMI_TLV_CMD(WMI_GRP_FWTEST) + 2) +#define WMI_VDEV_SET_PARAM_CMDID (WMI_TLV_CMD(WMI_GRP_VDEV) + 7) +#define WMI_PDEV_SET_PARAM_CMDID (WMI_TLV_CMD(WMI_GRP_PDEV) + 2) + +enum ath11k_tm_attr { + __ATH11K_TM_ATTR_INVALID = 0, + ATH11K_TM_ATTR_CMD = 1, + ATH11K_TM_ATTR_DATA = 2, + ATH11K_TM_ATTR_WMI_CMDID = 3, + ATH11K_TM_ATTR_VERSION_MAJOR = 4, + ATH11K_TM_ATTR_VERSION_MINOR = 5, + ATH11K_TM_ATTR_WMI_OP_VERSION = 6, + + /* keep last */ + __ATH11K_TM_ATTR_AFTER_LAST, + ATH11K_TM_ATTR_MAX = __ATH11K_TM_ATTR_AFTER_LAST - 1, +}; + +/* All ath11k testmode interface commands specified in + * ATH11K_TM_ATTR_CMD + */ +enum ath11k_tm_cmd { + /* Returns the supported ath11k testmode interface version in + * ATH11K_TM_ATTR_VERSION. Always guaranteed to work. User space + * uses this to verify it's using the correct version of the + * testmode interface + */ + ATH11K_TM_CMD_GET_VERSION = 0, + + /* Boots the UTF firmware, the netdev interface must be down at the + * time. + */ + ATH11K_TM_CMD_TESTMODE_START = 1, + + /* Shuts down the UTF firmware and puts the driver back into OFF + * state. + */ + ATH11K_TM_CMD_TESTMODE_STOP = 2, + + /* The command used to transmit a FW test WMI command to the firmware + * and the event to receive WMI events from the firmware. Without + * struct wmi_cmd_hdr header, only the WMI payload. Command id is + * provided with ATH11K_TM_ATTR_WMI_CMDID and payload in + * ATH11K_TM_ATTR_DATA. + */ + ATH11K_TM_CMD_WMI_FW_TEST = 3, + + /* The command used to transmit a FTM WMI command to the firmware + * and the event to receive WMI events from the firmware.The data + * received only contain the payload, Need to add the tlv + * header and send the cmd to fw with commandid WMI_PDEV_UTF_CMDID. + */ + ATH11K_TM_CMD_WMI_FTM = 4, + +}; + +struct nl80211_socket_info { + struct nl_sock *nl_sock; + int genl_family_id; +}; + +struct wmi_unit_test_cmd { + unsigned int tlv_header; + unsigned int vdev_id; + unsigned int module_id; + unsigned int num_args; + unsigned int diag_token; +}; + +struct wmi_vdev_pdev_set_param_cmd { + unsigned int tlv_header; + unsigned int vdev_pdev_id; + unsigned int param_id; + unsigned int param_value; +}; + +enum wmi_unit_test_cmd_type { + ATH11K_WMI_FW_UNIT_TEST_CMD, + ATH11K_WMI_VDEV_SET_PARAM_CMD, + ATH11K_WMI_PDEV_SET_PARAM_CMD, +}; + +int init_nl_sock(struct nl80211_socket_info *sock) +{ + int ret; + + sock->nl_sock = nl_socket_alloc(); + if (!sock->nl_sock) { + fprintf(stderr, "Failed to create nl socket\n"); + return -ENOMEM; + } + + if (genl_connect(sock->nl_sock)) { + fprintf(stderr, "Failed to connect to nl socket\n"); + ret = -ENOLINK; + goto free_nl_sock; + } + + nl_socket_set_buffer_size(sock->nl_sock, 0, ATH11K_TM_DATA_MAX_LEN); + + sock->genl_family_id = genl_ctrl_resolve(sock->nl_sock, "nl80211"); + if (sock->genl_family_id < 0) { + fprintf(stderr, "genl family not found!!\n"); + ret = -ENOENT; + goto free_nl_sock; + } + + return 0; +free_nl_sock: + nl_socket_free(sock->nl_sock); + return ret; +} + +void usage(char *argv[]) +{ + fprintf(stderr, "Usage: %s -t -i -m -v \n", + argv[0]); +} + +static int nl_cb_error_handler(struct sockaddr_nl *nla, struct nlmsgerr *err, void *arg) +{ + int *ret = arg; + *ret = err->error; + return NL_STOP; +} + +static int nl_cb_finish_handler(struct nl_msg *msg, void *arg) +{ + int *ret = arg; + *ret = 0; + return NL_SKIP; +} + +static int nl_cb_ack_handler(struct nl_msg *msg, void *arg) +{ + int *ret = arg; + *ret = 0; + return NL_STOP; +} + +void *ath11k_fwtest_fill_cmd_buf(unsigned int module_id, unsigned int vdev_id, + int num_args, char *argv[], int optind, int *buf_sz) +{ + struct wmi_unit_test_cmd *cmd; + unsigned int *buf; + int buf_size, i; + + buf_size = sizeof(struct wmi_unit_test_cmd) + WMI_TLV_HDR_SIZE + num_args * sizeof(unsigned int); + *buf_sz = buf_size; + + buf = (unsigned int *) malloc(buf_size); + if (!buf) { + fprintf(stderr, "Failed to allocate memory\n"); + return NULL; + } + + memset((void *)buf, 0, buf_size); + cmd = (struct wmi_unit_test_cmd *) buf; + + cmd->tlv_header = FIELD_PREP(WMI_TAG_UNIT_TEST_CMD, WMI_TLV_TAG) | + FIELD_PREP(sizeof(struct wmi_unit_test_cmd) - WMI_TLV_HDR_SIZE, WMI_TLV_LEN); + + cmd->module_id = module_id; + cmd->vdev_id = vdev_id; + cmd->num_args = num_args; + cmd->diag_token = 0; + + buf = (unsigned int *)((char *)buf + sizeof(struct wmi_unit_test_cmd)); + *buf = FIELD_PREP(WMI_TAG_ARRAY_UINT32, WMI_TLV_TAG) | + FIELD_PREP(num_args * sizeof(unsigned int), WMI_TLV_LEN); + buf++; + + for (i = 0; i < num_args; i++, buf++) + *buf = strtoul(argv[optind + i], NULL, 0); + + return cmd; +} + +void *ath11k_wmi_vdev_pdev_set_cmd_fill_buf(unsigned int type, unsigned int vdev_pdev_id, + char *argv[], int optind, int *buf_sz) +{ + struct wmi_vdev_pdev_set_param_cmd *cmd; + unsigned int *buf; + int buf_size; + int tag; + + buf_size = sizeof(struct wmi_vdev_pdev_set_param_cmd); + *buf_sz = buf_size; + + buf = (unsigned int *) malloc(buf_size); + if (!buf) { + fprintf(stderr, "Failed to allocate memory\n"); + return NULL; + } + + memset((void *)buf, 0, buf_size); + cmd = (struct wmi_vdev_pdev_set_param_cmd *) buf; + + if (type == ATH11K_WMI_VDEV_SET_PARAM_CMD) + tag = WMI_TAG_VDEV_SET_PARAM_CMD; + else + tag = WMI_TAG_PDEV_SET_PARAM_CMD; + + cmd->tlv_header = FIELD_PREP(tag, WMI_TLV_TAG) | + FIELD_PREP(sizeof(struct wmi_vdev_pdev_set_param_cmd) - WMI_TLV_HDR_SIZE, WMI_TLV_LEN); + + cmd->vdev_pdev_id = vdev_pdev_id; + cmd->param_id = strtoul(argv[optind], NULL, 0); + cmd->param_value = strtoul(argv[optind + 1], NULL, 0); + + return cmd; +} + +int main(int argc, char *argv[]) +{ + struct nl80211_socket_info sock; + void *cmd = NULL; + struct nl_msg *msg; + struct nlattr *nest; + struct nl_cb *cb; + unsigned int cmd_id; + char *ifname = NULL; + int netdev_idx; + unsigned int module_id = UINT_MAX; + unsigned int vdev_id = UINT_MAX; + unsigned int pdev_id = UINT_MAX; + unsigned int type = ATH11K_WMI_FW_UNIT_TEST_CMD; + int num_args; + int buf_size; + int opt; + int ret = 1; + + while (1) { + opt = getopt(argc, argv, "t:i:m:v:p:h"); + if (opt < 0) + break; + + switch (opt) { + case 'i': + ifname = optarg; + break; + case 't': + type = strtoul(optarg, NULL, 0); + break; + case 'm': + module_id = strtoul(optarg, NULL, 0); + break; + case 'v': + vdev_id = strtoul(optarg, NULL, 0); + break; + case 'p': + pdev_id = strtoul(optarg, NULL, 0); + break; + case 'h': + /* fall through */ + default: + usage(argv); + return ret; + } + } + + if (!ifname || module_id == UINT_MAX || + (type != ATH11K_WMI_PDEV_SET_PARAM_CMD && vdev_id == UINT_MAX)) { + fprintf(stderr, "Mandatory options are missing!!\n"); + usage(argv); + return -EINVAL; + } + + if (optind >= argc) { + fprintf(stderr, "Argument list missing!!\n"); + usage(argv); + return ret; + } + + num_args = argc - optind; + if (num_args > ATH11K_WMI_UNIT_TEST_MAX_NUM_ARGS) { + fprintf(stderr, "Arguments exceeded max limit, limit:%d\n", + ATH11K_WMI_UNIT_TEST_MAX_NUM_ARGS); + return ret; + } + + + netdev_idx = if_nametoindex(ifname); + if (!netdev_idx) { + fprintf(stderr, "%s not found\n", ifname); + return -ENOENT; + } + + ret = init_nl_sock(&sock); + if (ret < 0) { + fprintf(stderr, "Failed to initialize nl socket\n"); + return ret; + } + + msg = nlmsg_alloc(); + if (!msg) { + fprintf(stderr, "Failed to allocate nl message\n"); + ret = -ENOMEM; + goto free_nl_sock; + } + + cb = nl_cb_alloc(NL_CB_DEFAULT); + if (!cb) { + fprintf(stderr, "failed to allocate netlink callback\n"); + ret = -ENOMEM; + goto free_nl_msg; + } + + switch (type) { + case ATH11K_WMI_FW_UNIT_TEST_CMD: + cmd = ath11k_fwtest_fill_cmd_buf(module_id, vdev_id, num_args, argv, optind, &buf_size); + cmd_id = WMI_UNIT_TEST_CMDID; + break; + case ATH11K_WMI_VDEV_SET_PARAM_CMD: + cmd = ath11k_wmi_vdev_pdev_set_cmd_fill_buf(type, vdev_id, argv, optind, &buf_size); + cmd_id = WMI_VDEV_SET_PARAM_CMDID; + break; + case ATH11K_WMI_PDEV_SET_PARAM_CMD: + if (pdev_id == 0 || pdev_id == UINT_MAX) + break; + cmd = ath11k_wmi_vdev_pdev_set_cmd_fill_buf(type, pdev_id, argv, optind, &buf_size); + cmd_id = WMI_PDEV_SET_PARAM_CMDID; + break; + default: + fprintf(stderr, "Unknown fw unittest type\n"); + ret = -EINVAL; + goto free_nl_msg; + } + + if (!cmd) { + fprintf(stderr, "failed to fill cmd buffer, please check inputs\n"); + ret = -EINVAL; + goto free_nl_msg; + } + + genlmsg_put(msg, 0, 0, sock.genl_family_id, 0, 0, + NL80211_CMD_TESTMODE, 0); + + NLA_PUT_U32(msg, NL80211_ATTR_IFINDEX, netdev_idx); + + nest = nla_nest_start(msg, NL80211_ATTR_TESTDATA); + if (!nest) { + fprintf(stderr, "Failed to nest test input\n"); + ret = -ENOMEM; + goto free_cmd_buf; + } + + NLA_PUT_U32(msg, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI_FW_TEST); + NLA_PUT_U32(msg, ATH11K_TM_ATTR_WMI_CMDID, cmd_id); + NLA_PUT(msg, ATH11K_TM_ATTR_DATA, buf_size, cmd); + + nla_nest_end(msg, nest); + + ret = nl_send_auto_complete(sock.nl_sock, msg); + if (ret < 0) { + fprintf(stderr, "Failed to send nl msg: %d\n", ret); + goto free_cmd_buf; + } + + ret = 1; + + nl_cb_err(cb, NL_CB_CUSTOM, nl_cb_error_handler, &ret); + nl_cb_set(cb, NL_CB_FINISH, NL_CB_CUSTOM, nl_cb_finish_handler, &ret); + nl_cb_set(cb, NL_CB_ACK, NL_CB_CUSTOM, nl_cb_ack_handler, &ret); + + while (ret > 0) + nl_recvmsgs(sock.nl_sock, cb); + if (ret < 0) + fprintf(stderr, "command failed: %s (%d)\n", strerror(-ret), ret); + + goto free_cmd_buf; + +nla_put_failure: + fprintf(stderr, "nl put operation failed!!\n"); +free_cmd_buf: + free(cmd); + nl_cb_put(cb); +free_nl_msg: + nlmsg_free(msg); +free_nl_sock: + nl_socket_free(sock.nl_sock); + return ret; +} diff --git a/qca/ath11k-wifi/Makefile b/qca/ath11k-wifi/Makefile new file mode 100644 index 000000000..6741d057d --- /dev/null +++ b/qca/ath11k-wifi/Makefile @@ -0,0 +1,198 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/version.mk + +PKG_NAME:=ath11k-wifi +PKG_RELEASE:=1 +PKG_FLAGS:=nonshared + +include $(INCLUDE_DIR)/package.mk + +define Build/Prepare + mkdir -p $(PKG_BUILD_DIR) +endef + +define Build/Compile +endef + +# +# This is intended to be used on an interim basis until device-specific +# board data for new devices is available through the upstream compilation +# +# Please send a mail with your device-specific board files upstream. +# You can find instructions and examples on the linux-wireless wiki: +# +# + +ALLWIFIBOARDS:= \ + cig-wf188 \ + cig-wf188n \ + cig-wf194c \ + cig-wf194c4 \ + cig-wf196 \ + cybertan-eww622-a1 \ + edgecore-eap101 \ + gl-ax1800 \ + sercomm-wallaby \ + edgecore-eap102 \ + edgecore-eap104 \ + wallys-dr6018 \ + wallys-dr6018-v4 \ + tplink-ex227 \ + tplink-ex447 \ + yuncore-ax840 + +ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ath11k-wifi-$(BOARD)) + +define Package/ath11k-wifi-default + SUBMENU:=ath11k Board-Specific Overrides + SECTION:=firmware + CATEGORY:=Firmware + DEPENDS:=@TARGET_ipq807x||TARGET_ipq60xx + TITLE:=Custom Board +endef + +define Package/ath11k-wifi-qcom-ipq8074 +$(call Package/ath11k-wifi-default) + TITLE:=board-2.bin for QCOM IPQ807x eval kits +endef + +define Package/ath11k-wifi-qcom-ipq6018 +$(call Package/ath11k-wifi-default) + TITLE:=board-2.bin for QCOM IPQ60xx eval kits +endef + +define Package/ath11k-wifi-qcom-ipq5018 +$(call Package/ath11k-wifi-default) + TITLE:=board-2.bin for QCOM IPQ50xx eval kits +endef + +define Package/ath11k-wifi-qcom-qcn9000 +$(call Package/ath11k-wifi-default) + TITLE:=board-2.bin for QCOM QCN9000 eval kits +endef + +define Package/ath11k-wifi-qcom-ipq6122 +$(call Package/ath11k-wifi-default) + TITLE:=board-2.bin for QCOM IPQ6122 eval kits +endef + +define Package/ath11k-wifi-cig-wf196_6g +$(call Package/ath11k-wifi-default) + TITLE:=cig-wf196 6G bdf +endef + +define Package/ath11k-wifi-gl-ax1800 +$(call Package/ath11k-wifi-default) + TITLE:=gl-ax1800 bdf +endef + +define ath11k-wifi-install-one-to + $(INSTALL_DIR) $(2)/lib/firmware/$(3)/ + $(INSTALL_DATA) $(1) $(2)/lib/firmware/$(3)/board.bin +endef + +define ath11k-wifi-install-one + $(if $(filter $(suffix $(1)),.IPQ5018),\ + $(call ath11k-wifi-install-one-to,$(1),$(2),ath11k/IPQ5018/hw1.0/),\ + ) + $(if $(filter $(suffix $(1)),.IPQ6018),\ + $(call ath11k-wifi-install-one-to,$(1),$(2),ath11k/IPQ6018/hw1.0/),\ + ) + $(if $(filter $(suffix $(1)),.IPQ8074),\ + $(call ath11k-wifi-install-one-to,$(1),$(2),ath11k/IPQ8074/hw2.0/),\ + ) + $(if $(filter $(suffix $(1)),.QCN9074),\ + $(call ath11k-wifi-install-one-to,$(1),$(2),ath11k/QCN9074/hw1.0/),\ + ) + $(if $(filter $(suffix $(1)),.QCN6122),\ + $(call ath11k-wifi-install-one-to,$(1),$(2),ath11k/qcn6122/hw1.0/),\ + ) + +endef +# Blank line required at end of above define due to foreach context + +define generate-ath11k-wifi-package + define Package/ath11k-wifi-$(1) + $(call Package/ath11k-wifi-default) + TITLE:=bdwlan.bin Overrides for $(2) + CONFLICTS:=$(PREV_BOARD) + endef + + define Package/ath11k-wifi-$(1)/description +The $(2) requires board-specific, reference ("cal") data +that is not yet present in the upstream wireless firmware distribution. + +This package supplies bdwlan.bin file(s) that, in the interim, +overwrite those supplied by the ath11k-firmware-* packages. + +This is package is only necessary for the $(2). + +Do not install it for any other device! + endef + + define Package/ath11k-wifi-$(1)/install-overlay + $$$$(foreach ATH11K_WIFI_BOARD_FILE,$$$$(wildcard board-$(1).*),\ + $$$$(call ath11k-wifi-install-one,$$$$(ATH11K_WIFI_BOARD_FILE),$$(1))) + endef + + PREV_BOARD+=ath11k-wifi-$(1) +endef + +define Package/ath11k-wifi-qcom-ipq8074/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ8074/hw2.0/ + $(INSTALL_DATA) ./board-2.bin.IPQ8074 $(1)/lib/firmware/ath11k/IPQ8074/hw2.0/board-2.bin +endef + +define Package/ath11k-wifi-qcom-ipq6018/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/ + $(INSTALL_DATA) ./board-2.bin.IPQ6018 $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/board-2.bin +endef + +define Package/ath11k-wifi-qcom-ipq5018/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/ + $(INSTALL_DATA) ./board-2.bin.IPQ5018 $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/board-2.bin +endef + +define Package/ath11k-wifi-qcom-ipq6122/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ6122/hw1.0/ + $(INSTALL_DATA) ./board-2.bin.IPQ6122 $(1)/lib/firmware/ath11k/IPQ6122/hw1.0/board-2.bin +endef + +define Package/ath11k-wifi-qcom-qcn9000/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ + $(INSTALL_DATA) ./board-2.bin.QCN9000 $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin +endef + +define Package/ath11k-wifi-cig-wf196_6g/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ + $(INSTALL_DATA) ./board-cig-wf196_6g.bin.QCN9074 $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board.bin +endef + +define Package/ath11k-wifi-gl-ax1800/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/ + $(INSTALL_DATA) ./board-gl-ax1800.bin.IPQ6018 $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/board-2.bin +endef + +$(eval $(call generate-ath11k-wifi-package,cig-wf188,Cigtech WF188)) +$(eval $(call generate-ath11k-wifi-package,cig-wf188n,Cigtech WF188n)) +$(eval $(call generate-ath11k-wifi-package,cig-wf194c,Cigtech WF194c)) +$(eval $(call generate-ath11k-wifi-package,cig-wf194c4,Cigtech WF194c4)) +$(eval $(call generate-ath11k-wifi-package,cig-wf196,Cigtech WF196)) +$(eval $(call generate-ath11k-wifi-package,cybertan-eww622-a1,CyberTan EWW622 A1)) +$(eval $(call generate-ath11k-wifi-package,sercomm-wallaby,Sercomm Kiwi)) +$(eval $(call generate-ath11k-wifi-package,wallys-dr6018,Wallys DR6018)) +$(eval $(call generate-ath11k-wifi-package,wallys-dr6018-v4,Wallys DR6018 V4)) +$(eval $(call generate-ath11k-wifi-package,edgecore-eap101,EdgeCore EAP101)) +$(eval $(call generate-ath11k-wifi-package,edgecore-eap102,Edgecore EAP102)) +$(eval $(call generate-ath11k-wifi-package,edgecore-eap104,Edgecore EAP104)) +$(eval $(call generate-ath11k-wifi-package,tplink-ex227,TP-Link EX227)) +$(eval $(call generate-ath11k-wifi-package,tplink-ex447,TP-Link EX447)) +$(eval $(call generate-ath11k-wifi-package,yuncore-ax840,YunCore AX840)) + +$(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE)))) +$(eval $(call BuildPackage,ath11k-wifi-qcom-ipq5018)) +$(eval $(call BuildPackage,ath11k-wifi-qcom-ipq6122)) +$(eval $(call BuildPackage,ath11k-wifi-qcom-ipq8074)) +$(eval $(call BuildPackage,ath11k-wifi-qcom-ipq6018)) +$(eval $(call BuildPackage,ath11k-wifi-qcom-qcn9000)) +$(eval $(call BuildPackage,ath11k-wifi-cig-wf196_6g)) diff --git a/qca/ath11k-wifi/board-2.bin.IPQ5018 b/qca/ath11k-wifi/board-2.bin.IPQ5018 new file mode 100644 index 000000000..da412c85b Binary files /dev/null and b/qca/ath11k-wifi/board-2.bin.IPQ5018 differ diff --git a/qca/ath11k-wifi/board-2.bin.IPQ6018 b/qca/ath11k-wifi/board-2.bin.IPQ6018 new file mode 100644 index 000000000..8c384dc89 Binary files /dev/null and b/qca/ath11k-wifi/board-2.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-2.bin.IPQ6122 b/qca/ath11k-wifi/board-2.bin.IPQ6122 new file mode 100644 index 000000000..a5edfbefb Binary files /dev/null and b/qca/ath11k-wifi/board-2.bin.IPQ6122 differ diff --git a/qca/ath11k-wifi/board-2.bin.IPQ8074 b/qca/ath11k-wifi/board-2.bin.IPQ8074 new file mode 100644 index 000000000..aa4991bdc Binary files /dev/null and b/qca/ath11k-wifi/board-2.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-2.bin.QCN9000 b/qca/ath11k-wifi/board-2.bin.QCN9000 new file mode 100644 index 000000000..24fa37548 Binary files /dev/null and b/qca/ath11k-wifi/board-2.bin.QCN9000 differ diff --git a/qca/ath11k-wifi/board-cig-wf188.bin.IPQ6018 b/qca/ath11k-wifi/board-cig-wf188.bin.IPQ6018 new file mode 100644 index 000000000..19a15b41d Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf188.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-cig-wf188n.bin.IPQ6018 b/qca/ath11k-wifi/board-cig-wf188n.bin.IPQ6018 new file mode 100644 index 000000000..3d81cfa92 Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf188n.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-cig-wf194c.bin.IPQ8074 b/qca/ath11k-wifi/board-cig-wf194c.bin.IPQ8074 new file mode 100644 index 000000000..fc545e57c Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf194c.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-cig-wf194c4.bin.IPQ8074 b/qca/ath11k-wifi/board-cig-wf194c4.bin.IPQ8074 new file mode 100644 index 000000000..d235d2ec6 Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf194c4.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-cig-wf196.bin.IPQ8074 b/qca/ath11k-wifi/board-cig-wf196.bin.IPQ8074 new file mode 100644 index 000000000..c1427834f Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf196.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-cig-wf196_6g.bin.QCN9074 b/qca/ath11k-wifi/board-cig-wf196_6g.bin.QCN9074 new file mode 100644 index 000000000..051c2b050 Binary files /dev/null and b/qca/ath11k-wifi/board-cig-wf196_6g.bin.QCN9074 differ diff --git a/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.IPQ5018 b/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.IPQ5018 new file mode 100644 index 000000000..ec97bdaf4 Binary files /dev/null and b/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.IPQ5018 differ diff --git a/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.QCN9074 b/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.QCN9074 new file mode 100644 index 000000000..f3638227e Binary files /dev/null and b/qca/ath11k-wifi/board-cybertan-eww622-a1.bin.QCN9074 differ diff --git a/qca/ath11k-wifi/board-edgecore-eap101.bin.IPQ6018 b/qca/ath11k-wifi/board-edgecore-eap101.bin.IPQ6018 new file mode 100644 index 000000000..4b26af3a4 Binary files /dev/null and b/qca/ath11k-wifi/board-edgecore-eap101.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-edgecore-eap102.bin.IPQ8074 b/qca/ath11k-wifi/board-edgecore-eap102.bin.IPQ8074 new file mode 100644 index 000000000..211b99535 Binary files /dev/null and b/qca/ath11k-wifi/board-edgecore-eap102.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-edgecore-eap104.bin.IPQ5018 b/qca/ath11k-wifi/board-edgecore-eap104.bin.IPQ5018 new file mode 100644 index 000000000..688674d95 Binary files /dev/null and b/qca/ath11k-wifi/board-edgecore-eap104.bin.IPQ5018 differ diff --git a/qca/ath11k-wifi/board-edgecore-eap104.bin.QCN6122 b/qca/ath11k-wifi/board-edgecore-eap104.bin.QCN6122 new file mode 100644 index 000000000..c14f10f44 Binary files /dev/null and b/qca/ath11k-wifi/board-edgecore-eap104.bin.QCN6122 differ diff --git a/qca/ath11k-wifi/board-gl-ax1800.bin.IPQ6018 b/qca/ath11k-wifi/board-gl-ax1800.bin.IPQ6018 new file mode 100644 index 000000000..9ee8d0a75 Binary files /dev/null and b/qca/ath11k-wifi/board-gl-ax1800.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-tplink-ex227.bin.IPQ8074 b/qca/ath11k-wifi/board-tplink-ex227.bin.IPQ8074 new file mode 100644 index 000000000..7a11f38a9 Binary files /dev/null and b/qca/ath11k-wifi/board-tplink-ex227.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-tplink-ex447.bin.IPQ8074 b/qca/ath11k-wifi/board-tplink-ex447.bin.IPQ8074 new file mode 100644 index 000000000..f0a5c56f1 Binary files /dev/null and b/qca/ath11k-wifi/board-tplink-ex447.bin.IPQ8074 differ diff --git a/qca/ath11k-wifi/board-wallys-dr6018-v4.bin.IPQ6018 b/qca/ath11k-wifi/board-wallys-dr6018-v4.bin.IPQ6018 new file mode 100644 index 000000000..6c89a8822 Binary files /dev/null and b/qca/ath11k-wifi/board-wallys-dr6018-v4.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-wallys-dr6018.bin.IPQ6018 b/qca/ath11k-wifi/board-wallys-dr6018.bin.IPQ6018 new file mode 100644 index 000000000..4b26af3a4 Binary files /dev/null and b/qca/ath11k-wifi/board-wallys-dr6018.bin.IPQ6018 differ diff --git a/qca/ath11k-wifi/board-yuncore-ax840.bin.IPQ6018 b/qca/ath11k-wifi/board-yuncore-ax840.bin.IPQ6018 new file mode 100644 index 000000000..349d35304 Binary files /dev/null and b/qca/ath11k-wifi/board-yuncore-ax840.bin.IPQ6018 differ diff --git a/qca/ftm/Makefile b/qca/ftm/Makefile new file mode 100644 index 000000000..66c37f46f --- /dev/null +++ b/qca/ftm/Makefile @@ -0,0 +1,69 @@ +include $(TOPDIR)/rules.mk + +PKG:=ftm +PKG_NAME:=$(PKG) +PKG_RELEASE:=1 +PKG_VERSION:=11.4-csu1 + +#PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG) + +include $(INCLUDE_DIR)/package.mk + +define Package/$(PKG_NAME) + SECTION:=QCA + CATEGORY:=QCA + URL:=http://www.qca.qualcomm.com + MAINTAINER:=Qualcomm Atheros + TITLE:= QCA ftm utils + DEPENDS:= @TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64||TARGET_ipq807x||TARGET_ipq60xx||TARGET_ipq50xx +libnl +libtcmd +qca-diag +librt +kmod-diag-char +endef + +define Package/$(PKG_NAME)/description/Default + FTM Package Support for QCA WIFI 11 drivers +endef + +TARGET_CFLAGS += -DCONFIG_FTM_WLAN -DDEBUG -DFTM_DEBUG -DWIN_AP_HOST +TARGET_CFLAGS += -I$(STAGING_DIR)/usr/include/qca-diag +TARGET_CFLAGS += -MMD -O2 -Wall -g +TARGET_CFLAGS += -I$(STAGING_DIR)/usr/include +TARGET_CFLAGS += -fpie +TARGET_LDFLAGS += -ldiag -lnl-3 -lnl-genl-3 -lrt -ltcmd +TARGET_CSRCS := ftm_main.c ftm_wlan.c ftm_write_to_flash.c +TARGET_LDFLAGS += -pie + +ifneq ($(CONFIG_PACKAGE_kmod-ath11k),) + TARGET_CFLAGS+=-DWIN_AP_HOST_OPEN=1 +endif + +ifeq ($(CONFIG_FEATURE_QCA_IOT),y) +TARGET_CFLAGS += -DIPQ_AP_HOST_IOT -DIPQ_AP_HOST_IOT_QCA402X -ggdb3 -DCONFIG_DAEMON_MODE +TARGET_CSRCS += ftm_iot.c +TARGET_LDFLAGS += -lpthread +TARGET_CFLAGS += -I$(STAGING_DIR)/usr/include/qca-iot +TARGET_LDFLAGS += -ldiag_demo +endif + +ifeq ($(CONFIG_FEATURE_QCA_IOT_IPQ50XX_SUPPORT),y) +TARGET_CFLAGS += -DIPQ_AP_HOST_IOT -DIPQ_AP_HOST_IOT_IPQ50XX -ggdb3 -I$(STAGING_DIR)/usr/include/btdaemon +TARGET_CSRCS += ftm_iot.c +TARGET_LDFLAGS += -lpthread -lbtdaemon +endif + +define Build/Compile +$(MAKE) -C $(PKG_BUILD_DIR) \ + CC="$(TARGET_CC)" \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + CSRCS="$(TARGET_CSRCS)" +endef + +define Package/$(PKG_NAME)/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) $(PKG_BUILD_DIR)/ftm $(1)/usr/sbin/ + $(INSTALL_BIN) ./files/ftm.init $(1)/etc/init.d/ftm + $(INSTALL_DIR) $(1)/lib/wifi + $(INSTALL_BIN) ./files/compress_vart.sh $(1)/lib/compress_vart.sh +endef + +$(eval $(call BuildPackage,ftm)) diff --git a/qca/ftm/files/compress_vart.sh b/qca/ftm/files/compress_vart.sh new file mode 100644 index 000000000..ba9f53f7a --- /dev/null +++ b/qca/ftm/files/compress_vart.sh @@ -0,0 +1,74 @@ +#!/bin/sh +# +# Copyright (c) 2020 Qualcomm Technologies, Inc. +# +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# + +[ -e /lib/ipq806x.sh ] && . /lib/ipq806x.sh +. /lib/functions.sh + +low_mem_compress_art() +{ + local mtdblock=$(find_mtd_part 0:ART) + + if [ -z "$mtdblock" ]; then + # read from mmc + mtdblock=$(find_mmc_part 0:ART) + fi + + [ -n "$mtdblock" ] || return + + local apmp="/tmp" + + lzma -zvfk -4 ${apmp}/virtual_art.bin 2> /dev/null || { + echo "Error Compressing Virtual ART" > /dev/console + return + } + + dd if=${apmp}/virtual_art.bin.lzma of=${mtdblock} + echo "Success compressing Virtual ART(${mtdblock})" > /dev/console + return +} + +normal_art() +{ + local mtdblock=$(find_mtd_part 0:ART) + + if [ -z "$mtdblock" ]; then + # read from mmc + mtdblock=$(find_mmc_part 0:ART) + fi + + [ -n "$mtdblock" ] || return + + local apmp="/tmp" + + dd if=${apmp}/virtual_art.bin of=${mtdblock} + echo "Success writing to ART(${mtdblock})" > /dev/console + return +} + +write_caldata() +{ + local board + [ -f /tmp/sysinfo/board_name ] && { + board=ap$(cat /tmp/sysinfo/board_name | awk -F 'ap' '{print$2}') + } + + if [ -e /sys/firmware/devicetree/base/compressed_art ] + then + echo "Compressed ART Supported Platform $board " > /dev/console + low_mem_compress_art + else + echo "Non Compressed ART Platform $board " > /dev/console + normal_art + fi +} + +if [ "$1" = "write_caldata" ] +then + write_caldata +fi diff --git a/qca/ftm/files/ftm.init b/qca/ftm/files/ftm.init new file mode 100644 index 000000000..b526b54dc --- /dev/null +++ b/qca/ftm/files/ftm.init @@ -0,0 +1,97 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2013, 2017, 2020 Qualcomm Technologies, Inc. +# +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# +# 2013 Qualcomm Atheros, Inc. +# +# All Rights Reserved. +# Qualcomm Atheros Confidential and Proprietary +# + +. /lib/functions.sh +[ -e /lib/ipq806x.sh ] && . /lib/ipq806x.sh + +START=97 +SERVICE_DAEMONIZE=1 +SERVICE_WRITE_PID=1 + +MTD_ART_PART_NAME="art" + +compressed_art_read() { + local mtdblock=$(find_mtd_part 0:ART) + + if [ -z "$mtdblock" ]; then + #read from mmc + mtdblock=$(find_mmc_part 0:ART) + fi + + [ -n "$mtdblock" ] || return + + local apmp="/tmp" + + dd if=${mtdblock} of=${apmp}/virtual_art.bin.lzma + lzma -fdv --single-stream ${apmp}/virtual_art.bin.lzma || { + # Create dummy virtual_art.bin file of size 512K + dd if=/dev/zero of=${apmp}/virtual_art.bin bs=1024 count=512 + } + echo "Uncompressed and Copied ART content from ${mtdblock} to /tmp/virtual_art.bin" > /dev/console +} + +raw_art_read() { + local mtdblock=$(find_mtd_part 0:ART) + + if [ -z "$mtdblock" ]; then + #read from mmc + mtdblock=$(find_mmc_part 0:ART) + fi + + [ -n "$mtdblock" ] || return + + local apmp="/tmp" + + dd if=${mtdblock} of=${apmp}/virtual_art.bin + echo "Copy ART caldata from ${mtdblock} to /tmp/virtual_art.bin" > /dev/console +} + +retrieve_caldata() { + local board + [ -f /tmp/sysinfo/board_name ] && { + board=ap$(cat /tmp/sysinfo/board_name | awk -F 'ap' '{print$2}') + } + echo "**** Platform Name: $board *****" > /dev/console + + if [ -e /sys/firmware/devicetree/base/compressed_art ] + then + compressed_art_read + else + raw_art_read + fi +} + +start() { + local emmc_flash="" + local nor_flash="" + + emmc_flash=$(find_mmc_part 0:ART 2> /dev/null) + mtd_name=$(grep -i -w ${MTD_ART_PART_NAME} /proc/mtd | cut -f1 -d:) + nor_flash=`find /sys/bus/spi/devices/*/mtd -name ${mtd_name} 2> /dev/null` + + if [ -n "$emmc_flash" ]; then + [ -L /dev/caldata ] || \ + ln -s $emmc_flash /dev/caldata + elif [ -n "$nor_flash" ]; then + [ -L /dev/caldata ] || \ + ln -s /dev/${mtd_name//mtd/mtdblock} /dev/caldata + elif [ -n "$mtd_name" ]; then + [ -L /dev/caldata ] || \ + ln -s /dev/${mtd_name//mtd/mtdblock} /dev/caldata + fi + retrieve_caldata +} + +stop() { + [ -L /dev/caldata ] && rm /dev/caldata +} diff --git a/qca/ftm/src/Android.mk b/qca/ftm/src/Android.mk new file mode 100644 index 000000000..6d1349939 --- /dev/null +++ b/qca/ftm/src/Android.mk @@ -0,0 +1,133 @@ +ifeq ($(call is-vendor-board-platform,QCOM),true) + +# Build only if board has BT/FM/WLAN +ifeq ($(findstring true, $(BOARD_HAVE_QCOM_FM) $(BOARD_HAVE_BLUETOOTH) $(BOARD_HAS_ATH_WLAN_AR6320)),true) + +LOCAL_PATH:= $(call my-dir) + +BDROID_DIR:= system/bt +ifeq ($(TARGET_SUPPORTS_WEARABLES),true) +QTI_DIR := hardware/qcom/bt/msm8909/libbt-vendor +else +QTI_DIR := hardware/qcom/bt/libbt-vendor +endif + + +include $(CLEAR_VARS) + +LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/diag/include \ +LOCAL_C_INCLUDES += vendor/qcom/proprietary/diag/src \ +LOCAL_C_INCLUDES += $(TARGET_OUT_HEADERS)/common/inc \ +LOCAL_C_INCLUDES += vendor/qcom/proprietary/bt/hci_qcomm_init \ +LOCAL_C_INCLUDES += vendor/qcom/opensource/fm/helium \ +LOCAL_C_INCLUDES += $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ/usr/include \ +LOCAL_C_INCLUDES += $(BDROID_DIR)/hci/include \ +LOCAL_C_INCLUDES += $(QTI_DIR)/include +ifeq ($(TARGET_SUPPORTS_WEARABLES),true) +LOCAL_C_INCLUDES += device/qcom/msm8909w/opensource/bluetooth/tools/hidl_client/inc +else +LOCAL_C_INCLUDES += vendor/qcom/opensource/bluetooth/tools/hidl_client/inc +endif + +LOCAL_ADDITIONAL_DEPENDENCIES := $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ/usr + +LOCAL_CFLAGS:= \ + -DANDROID \ + -DDEBUG + +#LOCAL_CFLAGS += -include bionic/libc/include/sys/socket.h +#LOCAL_CFLAGS += -include bionic/libc/include/netinet/in.h + +ifneq ($(DISABLE_BT_FTM),true) +LOCAL_CFLAGS += -DCONFIG_FTM_BT +endif + +ifeq ($(BOARD_HAVE_QCOM_FM),true) +LOCAL_CFLAGS += -DCONFIG_FTM_FM +endif + +ifeq ($(BOARD_HAS_QCA_FM_SOC), "cherokee") +LOCAL_CFLAGS += -DFM_SOC_TYPE_CHEROKEE +endif + +ifneq ($(BOARD_ANT_WIRELESS_DEVICE), ) +LOCAL_CFLAGS += -DCONFIG_FTM_ANT +endif +LOCAL_CFLAGS += -DCONFIG_FTM_NFC + +ifeq ($(BOARD_HAVE_BLUETOOTH_BLUEZ), true) + LOCAL_CFLAGS += -DHAS_BLUEZ_BUILDCFG +endif # BOARD_HAVE_BLUETOOTH_BLUEZ + +LOCAL_SRC_FILES:= \ + ftm_main.c \ + ftm_nfc.c \ + ftm_nfcnq.c \ + ftm_nfcqti.c \ + ftm_nfcnq_fwdl.c \ + ftm_nfcnq_test.c + +ifneq ($(DISABLE_BT_FTM),true) +LOCAL_SRC_FILES += \ + ftm_bt.c \ + ftm_bt_power_pfal_linux.c \ + ftm_bt_hci_pfal_linux.c \ + ftm_bt_persist.cpp +endif + +ifeq ($(call is-platform-sdk-version-at-least,23),true) +LOCAL_CFLAGS += -DANDROID_M +endif + +ifeq ($(BOARD_HAVE_QCOM_FM),true) +ifeq ($(BOARD_HAS_QCA_FM_SOC), "cherokee") +LOCAL_SRC_FILES += ftm_fm.c ftm_fm_pfal_linux_3990.c +else +LOCAL_SRC_FILES += ftm_fm.c ftm_fm_pfal_linux.c +endif +endif + +ifneq ($(BOARD_ANT_WIRELESS_DEVICE), ) +LOCAL_SRC_FILES += ftm_ant.c +endif + +ifeq ($(findstring true, $(BOARD_HAS_ATH_WLAN) $(BOARD_HAS_ATH_WLAN_AR6320)),true) +LOCAL_CFLAGS += -DBOARD_HAS_ATH_WLAN_AR6320 +LOCAL_CFLAGS += -DCONFIG_FTM_WLAN +LOCAL_CFLAGS += -DCONFIG_FTM_WLAN_AUTOLOAD +LOCAL_STATIC_LIBRARIES += libtcmd +LOCAL_SHARED_LIBRARIES += libnl +LOCAL_C_INCLUDES += $(TARGET_OUT_HEADERS)/libtcmd +LOCAL_SRC_FILES += ftm_wlan.c +endif + +LOCAL_SHARED_LIBRARIES += libdl + +ifneq ($(DISABLE_BT_FTM),true) +LOCAL_SHARED_LIBRARIES += libbt-hidlclient +endif + +LOCAL_MODULE_PATH := $(TARGET_OUT_VENDOR_EXECUTABLES) +LOCAL_MODULE:= ftmdaemon +LOCAL_CLANG := true +ifeq ($(PRODUCT_VENDOR_MOVE_ENABLED),true) +LOCAL_PROPRIETARY_MODULE := true +endif +LOCAL_MODULE_TAGS := optional +LOCAL_SHARED_LIBRARIES += libdiag +LOCAL_SHARED_LIBRARIES += libcutils liblog libhardware + +ifneq ($(DISABLE_BT_FTM),true) +LOCAL_SHARED_LIBRARIES += libbtnv +endif + +# By default NV persist gets used +LOCAL_CFLAGS += -DBT_NV_SUPPORT + +LDFLAGS += -ldl + +include $(BUILD_EXECUTABLE) +include $(call all-makefiles-under,$(LOCAL_PATH)) + +endif # filter +endif # is-vendor-board-platform diff --git a/qca/ftm/src/LICENSE b/qca/ftm/src/LICENSE new file mode 100644 index 000000000..53f3da5eb --- /dev/null +++ b/qca/ftm/src/LICENSE @@ -0,0 +1,181 @@ +This text file is provided to comply with the attribution requirements of +the licenses herein, but see NOTICE for license terms of this software. +The Apache 2.0 license can be found at +http://www.apache.org/licenses/LICENSE-2.0.html + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS diff --git a/qca/ftm/src/Makefile b/qca/ftm/src/Makefile new file mode 100644 index 000000000..54e2ec30b --- /dev/null +++ b/qca/ftm/src/Makefile @@ -0,0 +1,12 @@ +#CC := $(ATH_CROSS_COMPILE_TYPE)gcc +TARGET_TYPE ?= AR9888 +TARGET_VERS ?= v2 + +#Sources to compile +CSRCS := ftm_main.c ftm_wlan.c ftm_write_to_flash.c + +all: + $(CC) $(CFLAGS) $(LDFLAGS) -g3 -Wall \ + $(CSRCS) -o ftm +clean: + rm -f ftm diff --git a/qca/ftm/src/Makefile.am b/qca/ftm/src/Makefile.am new file mode 100644 index 000000000..6a100c571 --- /dev/null +++ b/qca/ftm/src/Makefile.am @@ -0,0 +1,86 @@ +AM_CFLAGS = -Wall \ + -g -O0 \ + $(DIAG_CFLAGS) + +AM_CPPFLAGS = -Wall \ + -g -O0 \ + $(DIAG_CFLAGS) + +AM_CFLAGS += -I${WORKSPACE}/system/bt/hci/include +AM_CFLAGS += -I${WORKSPACE}/vendor/qcom/proprietary/bt/hci_qcomm_init/ + +AM_CPPFLAGS += -I${WORKSPACE}/system/bt/hci/include +AM_CPPFLAGS += -I${WORKSPACE}/vendor/qcom/proprietary/bt/hci_qcomm_init/ + +if DEBUG +AM_CFLAGS += -DDEBUG +AM_CPPFLAGS += -DDEBUG +endif + +requiredlibs = -lrt $(DIAG_LIBS) + +if USE_GLIB +AM_CFLAGS += -DUSE_GLIB $(GLIB_CFLAGS) +AM_CPPFLAGS += -DUSE_GLIB $(GLIB_CFLAGS) +requiredlibs += $(GLIB_LIBS) +endif + +#By default build for MDM_LE +AM_CFLAGS += -DMDM_LE +AM_CPPFLAGS += -DMDM_LE + +if MDM_ROME +AM_CFLAGS += -DBT_SOC_TYPE_ROME +AM_CPPFLAGS += -DBT_SOC_TYPE_ROME +else +if MDM_PRONTO +AM_CFLAGS += -DHCI_USE_MCT +AM_CPPFLAGS += -DHCI_USE_MCT +endif +endif + +c_sources = ftm_main.c + +if CONFIG_FTM_BT +AM_CFLAGS += -DCONFIG_FTM_BT -DBT_NV_SUPPORT +AM_CPPFLAGS += -DCONFIG_FTM_BT -DBT_NV_SUPPORT +c_sources += ftm_bt.c +c_sources += ftm_bt_power_pfal_linux.c +c_sources += ftm_bt_hci_pfal_linux.c +c_sources += ftm_bt_persist.cpp +endif + +if CONFIG_FTM_FM +AM_CFLAGS += -DCONFIG_FTM_FM +c_sources += ftm_fm.c +c_sources += ftm_fm_pfal_linux.c +endif + +if CONFIG_FTM_ANT +AM_CFLAGS += -DCONFIG_FTM_ANT +c_sources += ftm_ant.c +endif + +if CONFIG_FTM_NFC +AM_CFLAGS += -DCONFIG_FTM_NFC +c_sources += ftm_nfc.c +c_sources += ftm_nfcnq.c +c_sources += ftm_nfcqti.c +c_sources += ftm_nfcnq_fwdl.c +c_sources += ftm_nfcnq_test.c +endif + +if CONFIG_FTM_WLAN + +AM_CFLAGS += -DCONFIG_FTM_WLAN -DCONFIG_FTM_WLAN_AUTOLOAD +AM_CFLAGS += $(LIBNL_CFLAGS) $(ATH6KL_UTILS_CFLAGS) +AM_CPPFLAGS += $(LIBNL_CFLAGS) $(ATH6KL_UTILS_CFLAGS) + +requiredlibs += $(ATH6KL_UTILS_LIBS) $(LIBNL_LIBS) + +c_sources += ftm_wlan.c +endif + +ftmdaemon_SOURCES = $(c_sources) +ftmdaemon_LDADD = -ldl $(requiredlibs) -lbtnv +bin_PROGRAMS = ftmdaemon diff --git a/qca/ftm/src/NOTICE b/qca/ftm/src/NOTICE new file mode 100644 index 000000000..a74fbfab1 --- /dev/null +++ b/qca/ftm/src/NOTICE @@ -0,0 +1,72 @@ +This NOTICE file contains certain notices of software components included +with the software that Qualcomm Technologies, Inc. ("Qualcomm Technologies") +is required to provide you. Notwithstanding anything in the notices in this +file, your use of these software components together with the +Qualcomm Technologies software (Qualcomm Technologies software hereinafter +referred to as "Software") is subject to the terms of your license from +Qualcomm Technologies. Compliance with all copyright laws and software +license agreements included in the notice section of this file are the +responsibility of the user. Except as may be granted by separate express +written agreement, this file provides no license to any patents, +trademarks, copyrights, or other intellectual property. + +Copyright (c) 2016 Qualcomm Technologies, Inc. +All rights reserved. +Qualcomm is a registered trademark and registered service mark of +QUALCOMM Incorporated. All other trademarks and service marks are the +property of their respective owners. +________________________________________ +NOTICES +________________________________________ + +Copyright (C) 2010 The Android Open Source Project + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +________________________________________ + +Copyright (C) 2015 NXP Semiconductors +The original Work has been changed by NXP Semiconductors. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +________________________________________ + +Copyright (C) 2015 The Android Open Source Project + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +________________________________________ + +Note: Any files for which the above Apache License notices are required +to be provided are not contributions. + +A copy of the Apache 2.0 license is included in the file LICENSE +for attribution purposes only. diff --git a/qca/ftm/src/configure.ac b/qca/ftm/src/configure.ac new file mode 100644 index 000000000..9dc5973f3 --- /dev/null +++ b/qca/ftm/src/configure.ac @@ -0,0 +1,149 @@ +# -*- Autoconf -*- + +# configure.ac -- Autoconf script for ftm. +# + +# Process this file with autoconf to produce a configure script + +# Requires autoconf tool later than 2.61 +AC_PREREQ(2.61) +# Initialize the ftm package version 1.0.0 +AC_INIT([ftm],1.0.0) +# Does not strictly follow GNU Coding standards +AM_INIT_AUTOMAKE([foreign]) +# Disables auto rebuilding of configure, Makefile.ins +AM_MAINTAINER_MODE +# defines some macros variable to be included by source +AC_CONFIG_HEADERS([config.h]) +AC_CONFIG_MACRO_DIR([m4]) + +# Checks for programs. +AC_PROG_CC +AC_PROG_CXX +AM_PROG_CC_C_O +AC_PROG_LIBTOOL +AC_PROG_AWK +AC_PROG_CPP +AC_PROG_INSTALL +AC_PROG_LN_S +AC_PROG_MAKE_SET + +# Checks for libraries. +PKG_CHECK_MODULES([DIAG], [diag]) +AC_SUBST([DIAG_CFLAGS]) +AC_SUBST([DIAG_LIBS]) + +has_libnl_ver=0 +# libnl-2 provides only libnl-2.0.pc file, so we check for separate libnl-genl-3.0.pc +# pkg-config file just for libnl-3.0 case. +# +PKG_CHECK_MODULES([LIBNL], [libnl-3.0 >= 3.0 libnl-genl-3.0 >= 3.0], [has_libnl_ver=3], [ + PKG_CHECK_MODULES([LIBNL], [libnl-2.0 >= 2.0], [has_libnl_ver=2], [ + PKG_CHECK_MODULES([LIBNL], [libnl-1], [has_libnl_ver=1], [has_libnl_ver=0])])]) + +if (test "$has_libnl_ver" -eq 0); then + AC_MSG_ERROR(libnl and libnl-genl are required but were not found) +fi + +if (test "$has_libnl_ver" -gt 1); then + AC_DEFINE([HAVE_LIBNL20], [1], [Define if you have libnl-2.0 or higher]) +fi + +AC_SUBST([LIBNL_CFLAGS]) +AC_SUBST([LIBNL_LIBS]) + +PKG_CHECK_MODULES([ATH6KL_UTILS], [ath6kl-utils]) +AC_SUBST([ATH6KL_UTILS_CFLAGS]) +AC_SUBST([ATH6KL_UTILS_LIBS]) + +AC_ARG_WITH([glib], + AC_HELP_STRING([--with-glib], + [enable glib, building FTM Daemon which use glib])) + +if (test "x${with_glib}" = "xyes"); then + PKG_CHECK_MODULES(GTHREAD, gthread-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GThread >= 2.16 is required)) + PKG_CHECK_MODULES(GLIB, glib-2.0 >= 2.16, dummy=yes, + AC_MSG_ERROR(GLib >= 2.16 is required)) + GLIB_CFLAGS="$GLIB_CFLAGS $GTHREAD_CFLAGS" + GLIB_LIBS="$GLIB_LIBS $GTHREAD_LIBS" + + AC_SUBST(GLIB_CFLAGS) + AC_SUBST(GLIB_LIBS) +fi +AM_CONDITIONAL(USE_GLIB, test "x${with_glib}" = "xyes") + +AC_ARG_ENABLE([debug], + [ --enable-debug Turn on debugging], + [case "${enableval}" in + yes) debug=true ;; + no) debug=false ;; + *) AC_MSG_ERROR([bad value ${enableval} for --enable-debug]) ;; + esac],[debug=false]) + +AM_CONDITIONAL([DEBUG], [test x$debug = xtrue]) + +AC_ARG_ENABLE([all], + [ --enable-all Enable all FTM functionality], + [case "${enableval}" in + yes) all=true ;; + no) all=false ;; + *) AC_MSG_ERROR([bad value ${enableval} for --enable-all]) ;; + esac],[all=false]) + +AM_CONDITIONAL([CONFIG_FTM_BT], [test x$all = xtrue]) +AM_CONDITIONAL([CONFIG_FTM_FM], [test x$all = xtrue]) +AM_CONDITIONAL([CONFIG_FTM_ANT], [test x$all = xtrue]) +AM_CONDITIONAL([CONFIG_FTM_NFC], [test x$all = xtrue]) + +AC_ARG_ENABLE([wlan], + [ --enable-wlan Enable WLAN FTM functionality], + [case "${enableval}" in + yes) wlan=true ;; + no) wlan=false ;; + *) AC_MSG_ERROR([bad value ${enableval} for --enable-wlan]) ;; + esac],[wlan=false]) + +AM_CONDITIONAL([CONFIG_FTM_WLAN], [test x$wlan = xtrue -o x$all = xtrue]) + +AC_ARG_ENABLE([bt], + [ --enable-bt Enable BT FTM functionality], + [case "${enableval}" in + yes) bt=true ;; + no) bt=false ;; + *) AC_MSG_ERROR([bad value ${enableval} for --enable-bt]) ;; + esac],[bt=false]) + +AM_CONDITIONAL([CONFIG_FTM_BT], [test x$bt = xtrue -o x$all = xtrue]) + + +AC_ARG_ENABLE(target, + [AS_HELP_STRING([--enable-target=TARGET], [Specify the target product to build])], + [TARGET=$enableval], + [TARGET=none] +) +AM_CONDITIONAL([MDM_ROME], [test "x$TARGET" = "xmdm9607" -o "x$TARGET" = "xmdm9635" -o "x$TARGET" = "xmdm9640" -o "x$TARGET" = "xmdmcalifornium"]) +AM_CONDITIONAL([MDM_PRONTO], [test "x$TARGET" = "xapq8009" -o "x$TARGET" = "xapq8017" -o "x$TARGET" = "xapq8053"]) + +# Checks for typedefs, structures, and compiler characteristics. +AC_HEADER_STDBOOL +AC_HEADER_STDC +AC_C_INLINE +AC_TYPE_INT64_T +AC_TYPE_PID_T +AC_TYPE_SIZE_T +AC_TYPE_SSIZE_T +AC_TYPE_UINT16_T +AC_TYPE_UINT32_T +AC_TYPE_UINT8_T + +# Checks for library functions. +AC_FUNC_ERROR_AT_LINE +AC_FUNC_FORK +AC_FUNC_MALLOC + +AC_CONFIG_FILES([ \ + Makefile \ + ]) +AC_OUTPUT + diff --git a/qca/ftm/src/ftm_ant.c b/qca/ftm/src/ftm_ant.c new file mode 100644 index 000000000..5adb48ba1 --- /dev/null +++ b/qca/ftm/src/ftm_ant.c @@ -0,0 +1,585 @@ +/*========================================================================== + + FTM ANT Source File + +Description + FTM platform independent processing of packet data + +# Copyright (c) 2010-2012 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/16/12 ankurn Adding support for ANT commands +11/28/12 c_ssugas implements efficent method for Ant cmd transfer + and implements Rx thread for event handling. +===========================================================================*/ +#include "event.h" +#include "msg.h" +#include "log.h" + +#include "diag_lsm.h" +#include "diagpkt.h" +#include "diagcmd.h" +#include "diag.h" +#include "termios.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bt_vendor_qcom.h" +#include "ftm_ant_common.h" +#include "ftm_bt.h" +#include +#include "hidl_client.h" + +#ifdef ANDROID +#include +#endif + +#ifdef ANDROID +extern int soc_type; +#endif + +#define ANT_CTRL_PACKET_TYPE 0x0c +#define ANT_DATA_PACKET_TYPE 0x0e + +#define UNUSED(x) (void)(x) + +int init_transport_ant(int on); +// The following functions are dummy implementations of the callbacks required by libbt-vendor. +static void vendor_fwcfg_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_scocfg_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_lpm_vnd_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_audio_state_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void* vendor_alloc(int size) { + UNUSED(size); + return NULL; +} +static void vendor_dealloc(void *p_buf) { + UNUSED(p_buf); +} +static uint8_t vendor_xmit_cb(uint16_t opcode, void *p_buf, tINT_CMD_CBACK p_cback) { + UNUSED(opcode); + UNUSED(p_buf); + UNUSED(p_cback); + return 0; +} +static void vendor_epilog_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_a2dp_offload_cb(bt_vendor_op_result_t result, bt_vendor_opcode_t op, unsigned char handle) { + UNUSED(result); + UNUSED(op); + UNUSED(handle); +} + +// This struct is used to regsiter the dummy callbacks with libbt-vendor +static bt_vendor_interface_t *vendor_interface=NULL; +static const bt_vendor_callbacks_t vendor_callbacks = { + sizeof(bt_vendor_callbacks_t), + vendor_fwcfg_cb, + vendor_scocfg_cb, + vendor_lpm_vnd_cb, + vendor_audio_state_cb, + vendor_alloc, + vendor_dealloc, + vendor_xmit_cb, + vendor_epilog_cb, + vendor_a2dp_offload_cb +}; + +/* Transport file descriptor */ +int fd_transport_ant_cmd; +extern int first_ant_command; +/* Reader thread handle */ +pthread_t ant_cmd_thread_hdl; +/* Pipe file descriptors for cancelling read operation */ +int ant_pipefd[2]; + +/* Enable FTM_DEBUG to turn on Debug messages */ +//#define FTM_DEBUG + +/*=========================================================================== +FUNCTION ftm_ant_readerthread + +DESCRIPTION + Thread Routine to perfom asynchrounous handling of events coming on Smd + descriptor. It invokes a callback to the FTM ANT layer to intiate a request + to read event bytes. + +DEPENDENCIES + The LifeTime of ReaderThraad is dependent on the status returned by the + call to ftm_ant_qcomm_handle_event + +RETURN VALUE + RETURN NULL + +SIDE EFFECTS + None + +===========================================================================*/ +void *ftm_ant_readerthread(void *ptr) +{ + boolean status = FALSE; + int retval; + fd_set readfds; + int buf; + + UNUSED(ptr); +#ifdef FTM_DEBUG + printf("ftm_ant_readerthread --> \n"); +#endif + do + { + FD_ZERO(&readfds); + FD_SET(fd_transport_ant_cmd, &readfds); + FD_SET(ant_pipefd[0],&readfds); + retval = select((fd_transport_ant_cmd>ant_pipefd[0]?fd_transport_ant_cmd + :ant_pipefd[0]) + 1, &readfds, NULL, NULL, NULL); + if(retval == -1) + { + printf("select failed\n"); + break; + } + if(FD_ISSET(ant_pipefd[0],&readfds)) + { +#ifdef FTM_DEBUG + printf("Pipe descriptor set\n"); +#endif + read(ant_pipefd[0],&buf,1); + if(buf == 1) + break; + } + if(FD_ISSET(fd_transport_ant_cmd,&readfds)) + { +#ifdef FTM_DEBUG + printf("Read descriptor set\n"); +#endif + status = ftm_ant_qcomm_handle_event(); + if(TRUE != status) + break; + } + } + while(1); +#ifdef FTM_DEBUG + printf("\nReader thread exited\n"); +#endif + return 0; +} + +/*=========================================================================== +FUNCTION ftm_ant_open_channel + +DESCRIPTION + Open the SMD transport associated with ANT + +DEPENDENCIES + NIL + +RETURN VALUE + int value indicating success or failure + +SIDE EFFECTS + NONE + +===========================================================================*/ +static bool ftm_ant_open_channel() +{ + struct termios term_port; + int opts; + + printf("%s: \n",__func__ ); + switch (soc_type) + { + case BT_SOC_ROME: + case BT_SOC_CHEROKEE: + case BT_SOC_NAPIER: + //Use hidl_client_initialize for chip initialization + if (hidl_client_initialize(MODE_ANT,&fd_transport_ant_cmd) == false) { + printf("%s: HIDL client initialization failed, opening port with init_transpor_ant\n", __func__); + //Use libbt-vendor for chip initialization + fd_transport_ant_cmd = init_transport_ant(TRUE); + if (fd_transport_ant_cmd == -1) { + printf("%s: ANT Device open Failed, fd:%d: \n", __func__, fd_transport_ant_cmd); + return false; + } + } + break; + case BT_SOC_AR3K: + case BT_SOC_SMD: +#ifdef FTM_DEBUG + printf("ftm_ant_open_channel --> \n"); +#endif + + fd_transport_ant_cmd = open(APPS_RIVA_ANT_CMD_CH, (O_RDWR)); + if (fd_transport_ant_cmd == -1) { + printf("Ant Device open Failed= %d\n ", fd_transport_ant_cmd); + return false; + } + + // Blocking Read + opts = fcntl(fd_transport_ant_cmd, F_GETFL); + if (opts < 0) { + perror("fcntl(F_GETFL)"); + exit(EXIT_FAILURE); + } + + opts = opts & (~O_NONBLOCK); + if (fcntl(fd_transport_ant_cmd, F_SETFL, opts) < 0) { + perror("fcntl(F_SETFL)"); + exit(EXIT_FAILURE); + } + + if (tcgetattr(fd_transport_ant_cmd, &term_port) < 0) + close(fd_transport_ant_cmd); + cfmakeraw(&term_port); + if (tcsetattr(fd_transport_ant_cmd, TCSANOW, &term_port) < 0) { + printf("\n Error while setting attributes\n"); + return false; + } + + tcflush(fd_transport_ant_cmd, TCIFLUSH); +#ifdef FTM_DEBUG + printf("ftm_ant_open_channel success \n"); +#endif + break; + default: + ALOGE("%s:Unknown soc type.",__func__); + return false; + } + if (pipe(ant_pipefd) == -1) + { + printf("pipe create error"); + return STATUS_FAIL; + } + /* Creating read thread which listens for various masks & pkt requests */ + pthread_create( &ant_cmd_thread_hdl, NULL, ftm_ant_readerthread, NULL); + return true; +} + +int init_transport_ant(int on) { + + void *so_handle; + unsigned char bdaddr[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + int fd[CH_MAX], powerstate, ret = -1; + char ref_count[PROPERTY_VALUE_MAX]; + int value; + + if (on) { + so_handle = dlopen("libbt-vendor.so", RTLD_NOW); + if (!so_handle) + { + ALOGE("Failed to load vendor component"); + return -1; + } + + vendor_interface = (bt_vendor_interface_t *) dlsym(so_handle, "BLUETOOTH_VENDOR_LIB_INTERFACE"); + if (!vendor_interface) + { + ALOGE("Failed to accesst bt vendor interface"); + return -1; + } + + vendor_interface->init(&vendor_callbacks, bdaddr); + + ALOGI("Turn On BT power"); + powerstate = BT_VND_PWR_ON; + ret = vendor_interface->op(BT_VND_OP_POWER_CTRL, &powerstate); + if (ret < 0) + { + ALOGE("Failed to turn on power from bt vendor interface"); + return -1; + } + for (int i = 0; i < CH_MAX; i++) + fd[i] = -1; + +#ifdef ANDROID + if (soc_type == BT_SOC_ROME || soc_type == BT_SOC_CHEROKEE || soc_type == BT_SOC_NAPIER) { + /*call ANT_USERIAL_OPEN to get ANT handle*/ + ret = vendor_interface->op((bt_vendor_opcode_t)BT_VND_OP_ANT_USERIAL_OPEN, fd); + } +#else +#ifdef BT_SOC_TYPE_ROME + /*call ANT_USERIAL_OPEN to get ANT handle*/ + ret = vendor_interface->op((bt_vendor_opcode_t)BT_VND_OP_ANT_USERIAL_OPEN, fd); +#endif +#endif + ALOGE("ret value: %d", ret); + if (ret != 1) + { + ALOGE("Failed to get fd from bt vendor interface"); + return -1; + } else { + ALOGE("FD: %x", fd[0]); + return fd[0]; + } + } else { + if (vendor_interface) { + ALOGE("Close and cleanup the interfaces"); + +#ifdef ANDROID + if (soc_type == BT_SOC_ROME || soc_type == BT_SOC_CHEROKEE || soc_type == BT_SOC_NAPIER) { + int ret = vendor_interface->op((bt_vendor_opcode_t)BT_VND_OP_ANT_USERIAL_CLOSE, NULL); + } +#else +#ifdef BT_SOC_TYPE_ROME + int ret = vendor_interface->op((bt_vendor_opcode_t)BT_VND_OP_ANT_USERIAL_CLOSE, NULL); +#endif +#endif + + ALOGE("ret value: %d", ret); + ALOGI("Turn off BT power"); + powerstate = BT_VND_PWR_OFF; + ret = vendor_interface->op(BT_VND_OP_POWER_CTRL, &powerstate); + if (ret < 0) + { + ALOGE("Failed to turn off power from bt vendor interface"); + return -1; + } + vendor_interface->cleanup(); + vendor_interface = NULL; + return 0; + } else { + + ALOGE("Not able to find vendor interface handle"); + return -1; + } + } +} + +/*=========================================================================== +FUNCTION ftm_log_send_msg + +DESCRIPTION + Processes the buffer sent and sends it to the libdiag for sending the Cmd + response + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_ant_log_send_msg(const uint8 *pEventBuf,int event_bytes) +{ + int result = log_status(LOG_FTM_VER_2_C); + ftm_ant_log_pkt_type* ftm_ant_log_pkt_ptr = NULL; + + if((pEventBuf == NULL) || (event_bytes == 0)) + return; +#ifdef FTM_DEBUG + printf("ftm_ant_log_send_msg --> \n"); +#endif + if(result == 1) + { + ftm_ant_log_pkt_ptr = (ftm_ant_log_pkt_type *)log_alloc(LOG_FTM_VER_2_C, + FTM_ANT_LOG_HEADER_SIZE + (event_bytes-1)); + if(ftm_ant_log_pkt_ptr != NULL) + { + /* FTM ANT Log PacketID */ + ftm_ant_log_pkt_ptr->ftm_log_id = FTM_ANT_LOG_PKT_ID; + memcpy((void *)ftm_ant_log_pkt_ptr->data,(void *)pEventBuf,event_bytes); + log_commit( ftm_ant_log_pkt_ptr ); + } + } +} + +/*=========================================================================== +FUNCTION ftm_ant_dispatch + +DESCRIPTION + Dispatch routine for the various FM Rx/Tx commands. Copies the data into + a global union data structure before calling the processing routine + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +void * ftm_ant_dispatch(ftm_ant_pkt_type *ant_ftm_pkt, uint16 pkt_len) +{ + ftm_ant_generic_sudo_res *rsp; + int err = 0, i; + int data_len = ant_ftm_pkt->cmd_data_len; + bool resp = false; + unsigned char *pdata = NULL, *ptemp; +#ifdef FTM_DEBUG + printf("ftm_ant_dispatch --> \n"); +#endif + + UNUSED(pkt_len); + + if (first_ant_command == 0) { + first_ant_command = 1; + ftm_ant_open_channel(); + } + + rsp = (ftm_ant_generic_sudo_res*)diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_ANT_CMD_CODE + , sizeof(ftm_ant_generic_sudo_res) + ); + if(rsp == NULL) + { + printf("%s Failed to allocate resource",__func__); + return NULL; + } + + switch (soc_type) { + //Rome shares the same UART transport for ANT and BT. Hence, to differenciate the + //packets by controller, adding one extra byte for ANT data and control packets + case BT_SOC_ROME: + case BT_SOC_CHEROKEE: + case BT_SOC_NAPIER: + data_len = data_len + 1; + pdata = (unsigned char *) malloc(data_len); + if (pdata == NULL) { + ALOGE("Failed to allocate the memory for ANT command packet"); + rsp->result = FTM_ANT_FAIL; + return (void *) rsp; + } + //To be compatible with Legacy, SMD based PLs, send all the packets + //with cmd opcode 0x0c + pdata[0] = 0x0c; + memcpy(pdata+1, ant_ftm_pkt->data, data_len-1); + err = write(fd_transport_ant_cmd, pdata, data_len); + ptemp = pdata; + break; + case BT_SOC_AR3K: + case BT_SOC_SMD: + /* Send the packet to controller and send a dummy response back to host*/ + err = write(fd_transport_ant_cmd, ant_ftm_pkt->data, data_len); + ptemp = ant_ftm_pkt->data; + break; + default: + ALOGE("%s:Unknown soc type", __func__); + break; + } + if (err == data_len) { + rsp->result = FTM_ANT_SUCCESS; + printf("ANT CMD: "); + for (i = 1; iresult = FTM_ANT_FAIL; + printf("FTM ANT write fail len: %d\n", err); + } + if (pdata) + free(pdata); + return (void *)rsp; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_qcomm_handle_event + +DESCRIPTION + Routine called by the HAL layer reader thread to process the HCI events + The post conditions of each event is covered in a state machine pattern + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_ant_qcomm_handle_event () +{ + boolean status = TRUE; + int nbytes,i,len =0; + int event_type; + ftm_ant_generic_res *res = (ftm_ant_generic_res *)diagpkt_subsys_alloc( + DIAG_SUBSYS_FTM + , FTM_ANT_CMD_CODE + , sizeof(ftm_ant_generic_res) + ); + if(res == NULL) + { + printf("%s Failed to allocate res",__func__); + tcflush(fd_transport_ant_cmd, TCIFLUSH); + return FALSE; + } +#ifdef FTM_DEBUG + printf("ftm_ant_hci_qcomm_handle_event --> \n"); +#endif + + /* Read length and event type of Ant Resp event*/ + nbytes = read(fd_transport_ant_cmd, (void *)res->evt, 2); + if(nbytes <= 0) { + status = FALSE; + printf("ftm_ant_qcomm_handle_event read fail len=%d\n", nbytes); + return status; + } + event_type = res->evt[0]; + len = res->evt[1]; +#ifdef FTM_DEBUG + printf(" event type =%d\n",event_type); + printf("length of event =%d\n",len); +#endif + /* Read out the Ant Resp event*/ + if (len <= (int)sizeof(res->evt)) + { + nbytes = read(fd_transport_ant_cmd, (void *)res->evt, len); + if (nbytes != len) { + res->result = FTM_ANT_FAIL; + status = FALSE; + printf("ftm_ant_qcomm_handle_event read fail len=%d\n", nbytes); + } + else { + res->result = FTM_ANT_SUCCESS; + printf("ANT EVT: "); + for (i=0; ievt[i]); + } + printf("\n"); + ftm_ant_log_send_msg(res->evt, nbytes); + tcflush(fd_transport_ant_cmd, TCIOFLUSH); + } + } + else + { + res->result = FTM_ANT_FAIL; + status = FALSE; + printf("ftm_ant_qcomm_handle_event read fail len=%d is more than sizeof(res->evt)=%d\n", len, (int)sizeof(res->evt)); + } + return status; +} diff --git a/qca/ftm/src/ftm_ant_common.h b/qca/ftm/src/ftm_ant_common.h new file mode 100644 index 000000000..c40e1caf8 --- /dev/null +++ b/qca/ftm/src/ftm_ant_common.h @@ -0,0 +1,124 @@ +/*========================================================================== + + FTM FM Common Header File + +Description + Global Data declarations of the ftm ant component. + +# Copyright (c) 2012,2014 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/16/2012 ankurn Adding support for ANT+ +11/28/12 c_ssugas Adds data structures and macro for ant log event support. +===========================================================================*/ + +#ifdef CONFIG_FTM_ANT + +#include "diagpkt.h" +#include "log.h" +#include "ftm_bt_common.h" + +#include + +#define APPS_RIVA_ANT_CMD_CH "/dev/smd5" +#define APPS_RIVA_ANT_DATA_CH "/dev/smd6" + +#define FTM_ANT_CMD_CODE 94 +#define OPCODE_OFFSET 5 + +#define FTM_ANT_LOG_HEADER_SIZE (sizeof(ftm_ant_log_pkt_type) - 1) +#define FTM_ANT_LOG_PKT_ID 0x0D + +/* FTM Log Packet - Used to send back the event of a ANT Command */ +typedef PACKED struct +{ + log_hdr_type hdr; + word ftm_log_id; /* FTM log id */ + byte data[1]; /* Variable length payload, + look at FTM log id for contents */ +} ftm_ant_log_pkt_type; + +/* Generic result, used for any command that only returns an error code */ +typedef enum { + FTM_ANT_FAIL, + FTM_ANT_SUCCESS, +} ftm_ant_api_result_type; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; +} ftm_ant_generic_sudo_res; + + +/* Generic Response */ +typedef PACKED struct +{ + diagpkt_subsys_header_type header; /*Diag header*/ + uint8 evt[18]; /*allocates memory to hold longest valid event */ + char result; /* result */ +}__attribute__((packed)) ftm_ant_generic_res; + +/* FTM ANT request type */ +typedef PACKED struct +{ + diagpkt_cmd_code_type cmd_code; + diagpkt_subsys_id_type subsys_id; + diagpkt_subsys_cmd_code_type subsys_cmd_code; + uint8 cmd_id; /* command id (required) */ + uint8 cmd_data_len; + byte data[1]; +}__attribute__((packed))ftm_ant_pkt_type; + + + +/*=========================================================================== +FUNCTION ftm_ant_dispatch + +DESCRIPTION + Dispatch routine for the various ANT commands. Copies the data into + a global union data structure before calling the processing routine + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the FTM ANT packet + +SIDE EFFECTS + None + +===========================================================================*/ + +void * ftm_ant_dispatch(ftm_ant_pkt_type *ftm_ant_pkt, uint16 length ); + +/*=========================================================================== +FUNCTION ftm_ant_qcomm_handle_event + +DESCRIPTION + Handler for the various ANT Events received. Sends data as log packets + using diag to upper layers. +DEPENDENCIES + NIL + +RETURN VALUE + Status value TRUE if event received successfuly + otherwise returns status value FALSE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_ant_qcomm_handle_event (); + +#endif /* CONFIG_FTM_ANT */ diff --git a/qca/ftm/src/ftm_bt.c b/qca/ftm/src/ftm_bt.c new file mode 100644 index 000000000..4f0475140 --- /dev/null +++ b/qca/ftm/src/ftm_bt.c @@ -0,0 +1,2013 @@ +/*========================================================================== + + FTM BT Task Source File + +Description + FTM state machine and platform independent routines for BT + +# Copyright (c) 2010-2013 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +02/29/12 rrr Added/Modified LE & BR/EDR power class configuration +09/27/11 bneti Added packet indicator for hci events for msm8960 +09/28/11 rrr Moved peristent NV item related APIs to CPP, + for having BD address being programmed twice if previous + BD address was random generated. +06/07/11 bneti Add support smd support for msm8960 +09/03/11 agaja Added support for NV_READ and NV_WRITE Commands to write + onto Persist File system +02/08/11 braghave Reading the HCI commands from binary file + for non-Android case +01/19/11 rakeshk Added the connectivity test implementation +01/07/11 rakeshk Updated the debug log warnings related to typecasting +07/07/10 rakeshk Updated the function name of BT power set routine + of pointers +06/18/10 rakeshk Created a source file to implement routines for FTM + states and command processing +==========================================================================*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ftm_bt_power_hal.h" +#include "ftm_fm_common.h" +#include "ftm_bt_hci_hal.h" +#include "ftm_common.h" +#include +#ifdef BT_NV_SUPPORT +#include "ftm_bt_persist.h" +#endif +#include "hidl_client.h" + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) +#define I2C_SLAVE_ADDR 0x0C +#define MAX_PIN_CONFIGS 8 + +#define NVM_PAYLOAD_MAXLENGTH (1024) +#define MAX_FILE_NAME (255) +#define LOG_FTM_FM_C ((uint16) 0x14CC) + +extern uint8_t is_slim_bus_test; +int fd_pintest = -1; +FILE *fp; +unsigned char *nvm_cmd; +typedef struct pintest { + char *gpiostring; + /* GPIO number */ + int gpionum; + /* Pin control register */ + int pinctrlreg; + /* Data register */ + int datareg; + /* Bit position in Data register */ + int bitpos; + /* Direction of the Pin */ + char direction; +} pintest; + +typedef struct platformpintest { + /* MSM number for pin test*/ + int platform; + /* Pin test config */ + pintest pinconfig[MAX_PIN_CONFIGS]; + /* Pin direction config register 0 */ + int pinctloe0; + /* Pin direction config register 1 */ + int pinctloe1; + /* Data register 0 */ + int pinctldata0; + /* Data register 1 */ + int pinctldata1; + /* PIN CTL enable value */ + int pinctlenable; + /* Output enable mask for UART pins */ + int hcioeenablemask; + /* Output enable mask for AUX PCM pins */ + int pcmoeenablemask; +}platformpintest; + +const platformpintest pintestconfigs[] = { + { + .platform = 8660, + .pinconfig = { + { + .gpiostring = "53",/*UARTDM_TX*/ + .gpionum = 53, + .pinctrlreg = 0x87,/*BT_HCI_0_MODE*/ + .datareg = 0x0D,/*PIN_CTL_DATA0*/ + .bitpos = 7, + .direction = 1, + }, + { + .gpiostring = "54",/*UARTDM_RX*/ + .gpionum = 54, + .pinctrlreg = 0x86,/*BT_HCI_1_MODE*/ + .datareg = 0x0D,/*PIN_CTL_DATA0*/ + .bitpos = 6, + .direction = 0, + }, + { + .gpiostring = "55",/*UARTDM_CTS*/ + .gpionum = 55, + .pinctrlreg = 0x84,/*BT_HCI_3_MODE*/ + .datareg = 0x0D,/*PIN_CTL_DATA0*/ + .bitpos = 4, + .direction = 0, + }, + { + .gpiostring = "56",/*UARTDM_RFR*/ + .gpionum = 56, + .pinctrlreg = 0x85,/*BT_HCI_2_MODE*/ + .datareg = 0x0D,/*PIN_CTL_DATA0*/ + .bitpos = 5, + .direction = 1, + }, + { + .gpiostring = "111",/*AUX_PCM_DOUT_S*/ + .gpionum = 111, + .pinctrlreg = 0x89,/*BT_PCM_DIN_MODE */ + .datareg = 0x0E,/*PIN_CTL_DATA1*/ + .bitpos = 1, + .direction = 1, + }, + { + .gpiostring = "112",/*AUX_PCM_DIN_S*/ + .gpionum = 112, + .pinctrlreg = 0x8A,/*BT_PCM_DOUT_MODE*/ + .datareg = 0x0E,/*PIN_CTL_DATA1*/ + .bitpos = 2, + .direction = 0, + }, + { + .gpiostring = "113",/*AUX_PCM_SYNC_S*/ + .gpionum = 113, + .pinctrlreg = 0x8B,/*BT_PCM_SYNC_MODE*/ + .datareg= 0x0E,/*PIN_CTL_DATA1*/ + .bitpos = 3, + .direction = 1, + }, + { + .gpiostring = "114",/*AUX_PCM_CLK_S*/ + .gpionum = 114, + .pinctrlreg = 0x88,/* BT_PCM_BCLK_MODE */ + .datareg = 0x0E,/*PIN_CTL_DATA1*/ + .bitpos = 0, + .direction = 1, + }, + }, + .pinctloe0 = 0xA, + .pinctloe1 = 0xB, + .pinctldata0 = 0xD, + .pinctldata1 = 0xE, + .pinctlenable = 0x15, + .hcioeenablemask = 0x50, + .pcmoeenablemask = 0x04, + }, +}; +platformpintest *pintestconfig= (platformpintest *)&pintestconfigs[0]; +/* I2C bus and GPIO mux entry drivers */ +#define I2C_PATH "/dev/i2c-4" +#define PINTEST_ENABLE_PATH "/sys/kernel/debug/btpintest/enable" + +const char HIGH = '1'; +const char LOW = '0'; + +/* ------------------------------------------------------------------------- +** Definitions and Declarations +** ------------------------------------------------------------------------- */ + +/*Flag to manage the verbose output */ +extern int verbose; +/* HCI Command buffer */ +static uint8 bt_ftm_buffer[BT_FTM_CMD_RSP_LEN]; +/* HCI Event buffer */ +static uint8 event_buf[HC_VS_MAX_ACL]; +/* Varibale to handle the stages of Sleep disable cmds */ +static int sleep_stage =0; +/* FTM Global state variable */ +static ftm_state global_state = FTM_SOC_NOT_INITIALISED; +/* pointer to the SOC version string */ +static uint8 *bt_soc_app_version_string = NULL; +/*variable to identify the msm type*/ +static boolean is_transportSMD = 0; +/* Variables to identify the platform */ +extern char transport_type[PROPERTY_VALUE_MAX]; +/* Default hw version register contents for 4020BD B0, if it's different than it's 4020BD B1 */ +static uint8 bt_soc_hw_version[] = +{ + 0x05, 0x00, 0x00, 0x00 +}; +/* Default Bluetooth address if read from NV fails, same in AMSS */ +static const uint8 default_bt_bd_addr[] = +{ + 0x34, 0x12, 0x78, 0x56, 0xBC, 0x9A +}; +/* Uart Protocol config tag*/ +static const bt_qsoc_cfg_tbl_struct_type bt_qsoc_tag17 = +{ + 0x8, {0x01, 0x11, 0x05, 0x0A, 0x01, 0x00, 0x00, 0x00,} +}; + +/* Uart Protocol config tag for latest hw */ +static const bt_qsoc_cfg_tbl_struct_type bt_qsoc_tag17_latest_hw = +{ + 0x0B, {0x01, 0x11, 0x08, 0x02,0x01,0x0E,0x08,0x04,0x32,0x0A,0x00} +}; + +/* FTM status log size*/ +const uint8 logsize = 2; +/* HCI user Cmd pass Log Packet */ +const uint8 event_buf_user_cmd_pass[2] = {0x0f,FTM_BT_DRV_NO_ERR}; +/* HCI user Cmd fail Log Packet */ +const uint8 event_buf_user_cmd_fail[2] = {0x0f,FTM_BT_DRV_CONN_TEST_FAILS}; +/* HCI user Cmd timed out Log Packet */ +const uint8 event_buf_user_cmd_timeout[2] = {0x0f,FTM_BT_DRV_NO_SOC_RSP_TOUT}; +/* HCI user Cmd Unknown error Log Packet */ +const uint8 event_buf_user_unknown_err[2] = {0x0f,FTM_BT_DRV_UNKNOWN_ERR}; + +struct first_cmd ptr_powerup; +#ifdef USE_LIBSOCCFG +/* Run time SoC Cfg paramters */ +ftm_bt_soc_runtime_cfg_type soc_cfg_parameters; +#endif +/* Peek table Loop count for 4025 R3 SoC */ +uint loopCount; +/* Command Queue front pointer */ +cmdQ *front = NULL; +/* Command Queue rear pointer */ +cmdQ *rear = NULL; +/* cmd count for unprocessed cmds in queue */ +uint32 num_pending_cmds = 0; +/* Descriptors for connectivity test */ +static int fd_i2c; +static char ctime_buf[10]; + +char *get_current_time(void) +{ + struct timeval tv; + time_t ctime; + + gettimeofday(&tv, NULL); + ctime = tv.tv_sec; + strftime(ctime_buf, 10, "%T", localtime(&ctime)); + return ctime_buf; +} +/*=========================================================================== +FUNCTION qinsert_cmd + +DESCRIPTION + Command Queue insert routine. Add the FTM BT packet to the Queue + +DEPENDENCIES + NIL + +RETURN VALUE + RETURNS FALSE without adding queue entry in failure + to allocate a new Queue item + else returns TRUE + +SIDE EFFECTS + increments the number of commands queued + +===========================================================================*/ +boolean qinsert_cmd(ftm_bt_pkt_type *ftm_bt_pkt) +{ + cmdQ *newitem; +#ifdef FTM_DEBUG + printf("qinsert_cmd > rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif + if(num_pending_cmds == 20) + { + ftm_log_send_msg(&event_buf_user_unknown_err[0],logsize); + return FALSE; + } + newitem = (cmdQ*)malloc(sizeof(cmdQ)); + if(newitem == NULL) + { + ftm_log_send_msg(&event_buf_user_unknown_err[0],logsize); + return FALSE; + } + newitem->next=NULL; + newitem->data = (void *)malloc(ftm_bt_pkt->ftm_hdr.cmd_data_len); + if(newitem->data == NULL) + { + free(newitem); + ftm_log_send_msg(&event_buf_user_unknown_err[0],logsize); + return FALSE; + } + /* Copy the data into the queue buffer */ + memcpy(newitem->data,(void*)ftm_bt_pkt->data, ftm_bt_pkt->ftm_hdr.cmd_data_len); + /* Set Flag to notify BT command*/ + newitem->bt_command = 1; + newitem->cmd_len = ftm_bt_pkt->ftm_hdr.cmd_data_len; + + if(front==NULL && rear==NULL) + { + front=newitem; + rear=newitem; + } + else + { + (rear)->next=newitem; + rear=newitem; + } + num_pending_cmds++; +#ifdef FTM_DEBUG + printf("qinsert_cmd < rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif + return TRUE; +} + +/*=========================================================================== +FUNCTION dequeue_send + +DESCRIPTION + Command Queue delete and calls HCI send routine. Dequeues the HCI data from + the queue and sends it to HCI HAL layer. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + decrements the number of command queued + +===========================================================================*/ +void dequeue_send() +{ + cmdQ *delitem; /* Node to be deleted */ +#ifdef FTM_DEBUG + printf("dequeue_send > rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif + if((front)==NULL && (rear)==NULL) + printf("\nQueue is empty to delete any element\n"); + else + { + delitem=front; + if(delitem) + { + ftm_bt_dispatch(delitem->data,delitem->cmd_len); + front=front->next; + if(front == NULL) + { + rear = NULL; + num_pending_cmds = 0; + } + free(delitem->data); + free(delitem); + num_pending_cmds--; + } + } +#ifdef FTM_DEBUG + printf("dequeue_send < rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif +} + +/*=========================================================================== +FUNCTION cleanup_pending_cmd_queue + +DESCRIPTION + Command Queue delete routine. Dequeues the HCI cmds from the + queue. This routine is useful in case the HCI interface has + hung up and a FTM module restart is immimnent. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + NONE + +===========================================================================*/ + +void cleanup_pending_cmd_queue() +{ + cmdQ *delitem; /* Node to be deleted */ +#ifdef FTM_DEBUG + printf("cleanup_pending_cmd_queue > rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif + if((front==NULL) && (rear==NULL)) + { + printf("\nQueue is empty to delete any element\n"); + } + else + { + while(front != NULL) + { + delitem=front; + front=front->next; + if(front == NULL) + rear = NULL; + free(delitem->data); + free(delitem); + } + } +#ifdef FTM_DEBUG + printf("cleanup_pending_cmd_queue < rear = 0x%x front = 0x%x\n", + (unsigned int)rear,(unsigned int)front); +#endif +} + +/*=========================================================================== +FUNCTION ftm_bt_err_timedout + +DESCRIPTION + This routine triggers the shutdown of the HCI and Power resources in case + a HCI command previously sent times out. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + NONE + +===========================================================================*/ +void ftm_bt_err_timedout() +{ + ftm_bt_hci_hal_deinit_transport(); + if(!is_transportSMD) + ftm_bt_power_hal_set(BT_OFF); +#ifdef FTM_DEBUG + printf("\nTimed out \n"); +#endif + global_state = FTM_SOC_NOT_INITIALISED; + cleanup_pending_cmd_queue(); + ftm_log_send_msg(&event_buf_user_cmd_timeout[0],logsize); +} + +/*=========================================================================== +FUNCTION export_gpio + +DESCRIPTION + Writes the gpio number passed in the argumnet to export a sysfs entry + +DEPENDENCIES + NIL + +RETURN VALUE + number of bytes written + +SIDE EFFECTS + None + +===========================================================================*/ +int export_gpio(int fd,char *gpionum) +{ + int sz; + sz = write(fd,gpionum,strlen(gpionum)); + return sz; +} +/*=========================================================================== +FUNCTION ftm_bt_conn_init + +DESCRIPTION + Initialises the connectivity test settings + 1. Exports the sysfs entries for MSM GPIOs + 2. Configures the TLMM settings on BT SoC to be in I2C PIN + control mode and directions. + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE,if the init fails + TRUE,if it passes + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_conn_init(void) +{ + char out[] = "out"; + char in[] = "in"; + int sz,i; + unsigned char buffer; + char direction_path[64]; + int fd_gpio = -1; + int fd = -1; +#ifdef FTM_DEBUG + printf("ftm_bt_conn_init start \n"); +#endif + fd_gpio = open("/sys/class/gpio/export", O_WRONLY); + + if(fd_gpio < 0) + return FALSE; + + for(i = 0; i < MAX_PIN_CONFIGS; i++) + { +#ifdef FTM_DEBUG + printf("pintestconfig->gpiostring = %s\n",pintestconfig->pinconfig[i].gpiostring); +#endif + sz = export_gpio(fd_gpio,pintestconfig->pinconfig[i].gpiostring); + if (sz < 0) + { + goto out; + } + } +#ifdef FTM_DEBUG + printf("Enabling pin test path\n"); +#endif + /* Configure the TLMM settings for the GPIOs requested using export */ + fd = open(PINTEST_ENABLE_PATH, O_WRONLY); + if(fd < 0) + goto out; + + buffer = HIGH; + sz = write(fd,&buffer,sizeof(buffer)); + if (sz < 0) + { + goto out; + } + close(fd); +#ifdef FTM_DEBUG + printf("open I2C_PATH\n"); +#endif + fd_i2c = open(I2C_PATH,O_RDWR); + + if(fd_i2c < 0) + { + goto out; + } + + buffer = pintestconfig->pinctlenable; + for(i = 0; i < MAX_PIN_CONFIGS ; i++) + { +#ifdef FTM_DEBUG + printf("pintestconfig->pinconfig[i]pinctrlreg = 0x%x\n",pintestconfig->pinconfig[i].pinctrlreg); +#endif + sz = i2c_write(fd_i2c,pintestconfig->pinconfig[i].pinctrlreg,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + if (sz < 0) + { + goto out; + } + } + + buffer = pintestconfig->hcioeenablemask; + sz = i2c_write(fd_i2c,pintestconfig->pinctloe0,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + if (sz < 0) + { + goto out; + } + for(i = 0; i < MAX_PIN_CONFIGS; i++) + { + snprintf(direction_path,sizeof(direction_path), + "/sys/class/gpio/gpio%d/direction", pintestconfig->pinconfig[i].gpionum); + fd = open(direction_path,O_WRONLY); + if(fd < 0) + goto out; + if(pintestconfig->pinconfig[i].direction) + sz = write(fd,&out,sizeof(out)); + else + sz = write(fd,&in,sizeof(in)); + if (sz < 0) + { + goto out; + } + close(fd); + } + + buffer = pintestconfig->pcmoeenablemask; + sz = i2c_write(fd_i2c,pintestconfig->pinctloe1,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + +out : +#ifdef FTM_DEBUG + printf("ftm_bt_conn_init end\n"); +#endif + if(fd >= 0) + close(fd); + if(fd_gpio >= 0) + close(fd_gpio); + + if ((sz < 0) || (fd < 0) || (fd_gpio < 0)) + { + return FALSE; + } + return TRUE; + +} + +/*=========================================================================== +FUNCTION ftm_bt_conn_outputpin_test + +DESCRIPTION + Executes the connectivity test for a output pin on + MSM 8660 to input pin on BT SOC + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE,if the connectivity test fails + TRUE,if it passes for all pins combination + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_conn_outputpin_test(const pintest *config) +{ + int fd_gpioN = -1; + int bit; + unsigned char wr_gpio_value = HIGH,rd_reg_value = 0; + char value_path[64]; +#ifdef FTM_DEBUG + printf("ftm_bt_conn_outputpin_test\n"); +#endif + /* Test UART Tx --> HCI0(RX on SoC) */ + snprintf(value_path,sizeof(value_path), + "/sys/class/gpio/gpio%d/value", config->gpionum); + fd_gpioN = open(value_path,O_WRONLY); + wr_gpio_value = HIGH; + /* Write a HIGH on the GPIO line on MSM */ + write(fd_gpioN,&wr_gpio_value,sizeof(wr_gpio_value)); + + i2c_read(fd_i2c,config->datareg,&rd_reg_value,sizeof(rd_reg_value),I2C_SLAVE_ADDR); + + bit = ((rd_reg_value & (1 << config->bitpos)) >> config->bitpos); + /* Check the Bit position in the Pin's Data register on SoC for a 1 */ + if(bit != 1) + { + close(fd_gpioN); + printf("OUT :HIGH Test GPIO %d FAIL data reg = %d\n",config->gpionum,config->datareg); + return FALSE; + } + + wr_gpio_value = LOW; + /* Write a LOW on the GPIO line on MSM*/ + write(fd_gpioN,&wr_gpio_value,sizeof(wr_gpio_value)); + + i2c_read(fd_i2c,config->datareg,&rd_reg_value,sizeof(rd_reg_value),I2C_SLAVE_ADDR); + + bit = ((rd_reg_value & (1 << config->bitpos)) >> config->bitpos); + /* Check if the bit position in the Pin's data register on SoC is cleared */ + if(bit != 0) + { + close(fd_gpioN); + printf("OUT : HIGH Test GPIO %d FAIL data reg = %d\n",config->gpionum,config->datareg); + return FALSE; + } + close(fd_gpioN); + + printf("OUT : Test GPIO %d PASS \n",config->gpionum); + + return TRUE; + +} + +/*=========================================================================== +FUNCTION ftm_bt_conn_inputpin_test + +DESCRIPTION + Executes the connectivity test for a input pin on + MSM 8660 from output pin on BT SOC + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE,if the connectivity test fails + TRUE,if it passes for all pins combination + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_conn_inputpin_test(const pintest *config) +{ + int fd_gpioN = -1; + unsigned char wr_reg_value = HIGH,rd_gpio_value; + char value_path[64]; +#ifdef FTM_DEBUG + printf("ftm_bt_conn_inputpin_test\n"); +#endif + + snprintf(value_path,sizeof(value_path), + "/sys/class/gpio/gpio%d/value", config->gpionum); + fd_gpioN = open(value_path,O_RDONLY); + + /* Write a 1 to the Pins bit position on SoC */ + wr_reg_value = (1 << config->bitpos); + i2c_write(fd_i2c,config->datareg,&wr_reg_value,sizeof(wr_reg_value),I2C_SLAVE_ADDR); + + read(fd_gpioN,&rd_gpio_value,sizeof(rd_gpio_value)); + /* Check if the value is high on the MSM GPIO line */ + if(rd_gpio_value != HIGH) + { + close(fd_gpioN); + printf("IN : HIGH Test GPIO %d FAIL data reg = %d\n",config->gpionum,config->datareg); + return FALSE; + } + + close(fd_gpioN); + fd_gpioN = open(value_path,O_RDONLY); + /* Clear the Pins bit position on SoC */ + wr_reg_value = wr_reg_value & ~(1 << config->bitpos); + i2c_write(fd_i2c,config->datareg,&wr_reg_value,sizeof(wr_reg_value),I2C_SLAVE_ADDR); + + read(fd_gpioN,&rd_gpio_value,sizeof(rd_gpio_value)); + + /* Check if the value is low on the MSM GPIO line */ + if(rd_gpio_value != LOW) + { + close(fd_gpioN); + printf("IN : LOW Test GPIO %d FAIL data reg = %d\n",config->gpionum,config->datareg); + return FALSE; + } + close(fd_gpioN); + + printf("IN : Test GPIO %d PASS \n",config->gpionum); + + return TRUE; +} + + +/*=========================================================================== +FUNCTION ftm_bt_conn_test_execute + +DESCRIPTION + Executes the connectivity test for MSM 8660-Bahama SOC + MSM 8660 Bahama SoC + ======== ========== + UART Tx ------> UART Rx + UART Rx <------ UART Tx + UART RTS ------> UART CTS + UART CTS <------ UART RTS + + AUX_PCM_CLK ------> PCM_BCLK + AUX_PCM_SYNC ------> PCM_SYNC + AUX_PCM_DOUT ------> PCM_DIN + AUX_PCM_DIN <------ PCM_DOUT + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE,if the connectivity test fails + TRUE,if it passes for all pins combination + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_conn_test_execute(void) +{ + + int i = 0,ret = 0; + + printf("Conn test begin \n"); + + for(i = 0; i < MAX_PIN_CONFIGS; i++) + { + if(pintestconfig->pinconfig[i].direction) + ret = ftm_bt_conn_outputpin_test(&pintestconfig->pinconfig[i]); + else + ret = ftm_bt_conn_inputpin_test(&pintestconfig->pinconfig[i]); + + if(ret != TRUE) + return FALSE; + } + printf("Conn test successfully done \n"); + return TRUE; +} + +/*=========================================================================== +FUNCTION ftm_bt_conn_deinit + +DESCRIPTION + Deinitialise the resources allocated for connectivity tests which includes + 1. unexport the GPIO sysfs entries + 2. Reset the settings in I2C registers of Bahama top level module + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_bt_conn_deinit(void) +{ + int sz,fd,i; + int fd_gpio; + unsigned char buffer; + +#ifdef FTM_DEBUG + printf("ftm_bt_conn_deinit start\n"); +#endif + /* Restore the Mux settings of the requested GPIOs*/ + fd = open(PINTEST_ENABLE_PATH, O_WRONLY); + buffer = '0'; + sz = write(fd,&buffer,sizeof(buffer)); + close(fd); + /* Unexport all the GPIOs */ + fd_gpio = open("/sys/class/gpio/unexport", O_WRONLY); + + if(fd_gpio < 0) + return ; + + for(i = 0; i < MAX_PIN_CONFIGS; i++) + { + sz = export_gpio(fd_gpio,pintestconfig->pinconfig[i].gpiostring); + if (sz < 0) + { + break; + } + } + + for(i = 0; i < MAX_PIN_CONFIGS; i++) + { + if(pintestconfig->pinconfig[i].gpionum >= 53 && pintestconfig->pinconfig[i].gpionum <= 56) + buffer = 0x40; + else + buffer = 0xC0; + + sz = i2c_write(fd_i2c,pintestconfig->pinconfig[i].pinctrlreg,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + if (sz < 0) + { + break; + } + } + buffer = 0x00; + i2c_write(fd_i2c,pintestconfig->pinctloe0,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + i2c_write(fd_i2c,pintestconfig->pinctloe1,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + i2c_write(fd_i2c,pintestconfig->pinctldata0,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + i2c_write(fd_i2c,pintestconfig->pinctldata1,&buffer,sizeof(buffer),I2C_SLAVE_ADDR); + + close(fd_gpio); + close(fd_i2c); + fd_i2c = -1; +#ifdef FTM_DEBUG + printf("ftm_bt_conn_deinit end\n"); +#endif + return; +} + +/*=========================================================================== +FUNCTION ftm_bt_conn_test + +DESCRIPTION + Executes the connectivity test for MSM 8660-Bahama SOC + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE,if the connectivity test fails + TRUE,if it passes + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_conn_test(void) +{ + boolean ret; + unsigned int i = 0; +#ifdef FTM_DEBUG + printf("ftm_bt_conn_test = %d\n",pintestconfigs[i].platform); +#endif + /* Walk through the avaialble pin test configs*/ + for(i = 0; i < ARRAY_SIZE(pintestconfigs);i++) + { + printf("board type = %d stored type = %d \n",boardtype,pintestconfigs[i].platform); + if(boardtype == pintestconfigs[i].platform) + { + pintestconfig = (platformpintest *)&pintestconfigs[i]; + break; + } + } + /* If we dont find a matching test config return here itself */ + if(i == ARRAY_SIZE(pintestconfigs)) + { + printf("Board type not supported %d\n",boardtype); + return FALSE; + } + /* Initialise the connectivity test + * related settings + */ + if((ret = ftm_bt_conn_init())) + { + /* Execute the test */ + ret = ftm_bt_conn_test_execute(); + } + /* Deinitliase the pin settings and i2c resources/mux + * settings + */ + ftm_bt_conn_deinit(); + return ret; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_vs_event + +DESCRIPTION + Processes the VS event buffer and stores the App version and HW version + +DEPENDENCIES + NIL + +RETURN VALUE + NIL, Error in the event buffer will mean a NULL App version and Zero HW + version + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_bt_hci_hal_vs_event +( + const uint8* pEventBuffer, + uint8 nLength +) +{ + const uint8 poke_reg_addr[] = { 0xFF,0x0B,BT_QSOC_EDL_CMD_CODE,0x01, + 0x34,0x00,0x00,0x8C,0x04}; + if ( nLength > 3 ) + { + if ( ( pEventBuffer[ 0] == 0xFF) /* VS Event */ + && (pEventBuffer[1] > 5) /* VS Length > 5*/ + && (pEventBuffer[2] == BT_QSOC_EDL_CMD_CODE) + && (pEventBuffer[3] == BT_QSOC_VS_EDL_APPVER_RESP) + ) + { + if( NULL != bt_soc_app_version_string ) + { + free(bt_soc_app_version_string); + bt_soc_app_version_string = NULL; + } + bt_soc_app_version_string = (uint8 *)malloc(nLength-5); + if( NULL != bt_soc_app_version_string ) + { + memmove(bt_soc_app_version_string, + &pEventBuffer[5],nLength-5); + } + } + else if ( (nLength > 12) // make sure we have enough event bytes + && (!memcmp(pEventBuffer,poke_reg_addr,sizeof(poke_reg_addr)))) + { + bt_soc_hw_version[0] = pEventBuffer[9]; + bt_soc_hw_version[1] = pEventBuffer[10]; + bt_soc_hw_version[2] = pEventBuffer[11]; + bt_soc_hw_version[3] = pEventBuffer[12]; + } + } +} /* ftm_bt_hci_hal_vs_event */ + +int is_snoop_log_enabled () +{ + char value[PROPERTY_VALUE_MAX] = {'\0'}; + property_get("persist.service.bdroid.snooplog", value, "false"); + return (strcmp(value, "true") == 0); +} + +/*=========================================================================== +FUNCTION ftm_log_send_msg + +DESCRIPTION + Processes the buffer sent and sends it to the libdiag for sending the Cmd + response + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ + + +void ftm_log_send_msg(const uint8 *pEventBuf,int event_bytes) +{ + if (strcasecmp(transport_type, "smd") || ((pEventBuf != NULL) && (pEventBuf[0] == FTM_BT_CMD_NV_READ))) + { + /* ftmdaemon uses log opcode 0x1366 to send the HCI Event logs to QRCT via DIAG + * but Riva/Pronto also uses the same opcode to send the events over DIAG. + * So this is causing the QRCT to recv some time 2 events for one cmd and some + * time pkt corruption. + * With this change ftmdaemon wont send any logs to QRCT in case of Riva/Pronto + */ + ftm_bt_log_pkt_type* ftm_bt_log_pkt_ptr = NULL; + + if((pEventBuf == NULL) || (event_bytes == 0)) + return; + + if(!is_snoop_log_enabled()) + { + if(pEventBuf[0] == BT_HCI_ACL_PKT && log_status(LOG_BT_HCI_RX_ACL_C)) + { + ftm_bt_log_pkt_ptr = (ftm_bt_log_pkt_type *)log_alloc(LOG_BT_HCI_RX_ACL_C, + FTM_BT_LOG_HEADER_SIZE + (event_bytes-1)); + } + else if(pEventBuf[0] == BT_HCI_EVT_PKT && log_status(LOG_BT_HCI_EV_C)) + { + ftm_bt_log_pkt_ptr = (ftm_bt_log_pkt_type *)log_alloc(LOG_BT_HCI_EV_C, + FTM_BT_LOG_HEADER_SIZE + (event_bytes-1)); + } + } + if(pEventBuf[0] == FM_HCI_EVT_PKT ) + { + ftm_bt_log_pkt_ptr = (ftm_bt_log_pkt_type *)log_alloc(LOG_FTM_FM_C, + FTM_BT_LOG_HEADER_SIZE + (event_bytes-1)); + } + if(ftm_bt_log_pkt_ptr != NULL) + { + /* We should not send HCI event code 0x04 for the log opcode 0x1366. Hence + * move the pointer to the next location to skip first byte in HCI event. + */ + pEventBuf++; + memcpy((void *)ftm_bt_log_pkt_ptr->data,(void *)pEventBuf, event_bytes-1); + log_commit( ftm_bt_log_pkt_ptr ); + } + else + { + printf("ftm_log_send_msg: Dropping packet\n"); + return; + } + } +} +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_send_reset_cmd + +DESCRIPTION + Sends the HCI packet to reset the BT SoC + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE: If write Fails, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_hal_send_reset_cmd() +{ + const uint8 ResetCmd[4] = {0x01, 0x03, 0x0C, 0x00}; + global_state = FTM_SOC_RESET; + return ((ftm_bt_hci_hal_nwrite((uint8*)(&ResetCmd[0]), 4) == STATUS_SUCCESS) + ? TRUE: FALSE); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_retrieve_send_nvm + +DESCRIPTION + Retrieves the NVM commands from the NVM parser module + and packages the VS HCI packet before calling ftm_bt_hci_hal_vs_sendcmd + When NVM entries are exhausted it Calls the next stage of Init to + disable sleep + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE: If Failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +#ifdef USE_LIBSOCCFG +boolean ftm_bt_hci_hal_retrieve_send_nvm() +{ + bt_qsoc_nvm_status nvm_status; + uint8 * nvm_ptr=NULL; + static const bt_qsoc_cfg_tbl_struct_type bt_qsoc_tag27 = + { + 0x04, {0x01, 0x1B, 0x01, 0x00} + }; + + /* Get the next NVM "string" */ + nvm_status = bt_qsoc_nvm_get_next_cmd(&nvm_ptr); + if(nvm_status == BT_QSOC_NVM_STATUS_SUCCESS) + { + if( nvm_ptr != NULL ) + { + return ftm_bt_hci_hal_vs_sendcmd( BT_QSOC_NVM_ACCESS_OPCODE, + (uint8 *)(&nvm_ptr[1]),(uint8)(nvm_ptr[0]) ); + } + } + else + { + bt_qsoc_nvm_close(); + sleep_stage = 0; + global_state = FTM_SOC_SLEEP_DISABLE; + if ( (ftm_bt_hci_hal_vs_sendcmd ( + BT_QSOC_NVM_ACCESS_OPCODE, + (uint8 *)(bt_qsoc_tag27.vs_cmd_data), + bt_qsoc_tag27.vs_cmd_len ) + ) != TRUE ) + return FALSE; + sleep_stage++; + } + + return TRUE; +} +#endif +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_vs_sendcmd + +DESCRIPTION + Helper Routine to process the VS HCI cmd and constucts the HCI packet before + calling ftm_bt_hci_send_cmd routine + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_hal_vs_sendcmd +( + uint16 opcode, + uint8 *pCmdBuffer, + uint8 nSize +) +{ + uint8 cmd[HC_VS_MAX_CMD_EVENT]; //JN: change this + request_status status = FALSE; + + int nwrite; + cmd[0] = BT_HCI_CMD_PKT; // JN: bluetooth header files in linux has a define + // HCI_COMMAND_PKT for this but do we want to use + // something thats command between QC platforms. + cmd[1] = (uint8)(opcode & 0xFF); + cmd[2] = (uint8)( (opcode>>8) & 0xFF); + cmd[3] = (uint8)(nSize); + + memcpy(&cmd[HCI_CMD_HDR_SIZE], pCmdBuffer, nSize); + + status = ftm_bt_hci_hal_nwrite((&cmd[0]), (HCI_CMD_HDR_SIZE+nSize)); + + if (status != STATUS_SUCCESS) + { + printf("Error->Send Header failed : %d\n",status); + return FALSE; + } + return TRUE; +} +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_read_app_version + +DESCRIPTION + Helper Routine to package the VS HCI cmd to read the Application version + and calls the ftm_bt_hci_hal_vs_sendcmd + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_hal_read_app_version() +{ + const uint8 getAppVerCmd[] = {0x06}; + global_state = FTM_SOC_READ_APP_VER; + ALOGV("ftm_bt_hci_hal_read_app_version:global_state = %d\n",global_state); + return ftm_bt_hci_hal_vs_sendcmd(BT_QSOC_EDL_CMD_OPCODE,(uint8 *)&getAppVerCmd[0],1); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_read_hw_version + +DESCRIPTION + Helper Routine to package the VS HCI cmd to read the HW version + and calls the ftm_bt_hci_hal_vs_sendcmd + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_hal_read_hw_version() +{ + const uint8 getHWVerRegCmd[] = {0x0D, 0x34, 0x00, 0x00, 0x8C, 0x04 }; + global_state = FTM_SOC_READ_HW_VER; + return ftm_bt_hci_hal_vs_sendcmd(BT_QSOC_EDL_CMD_OPCODE,(uint8 *)&getHWVerRegCmd[0],6); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_nvm_download_init + +DESCRIPTION + Routine to lookup the Soc type and initiate a Poke Table in case of a R3 + Soc type or else go ahead and proceed with the NvM open with runtime parameters + in AUTO MODE +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +#ifdef USE_LIBSOCCFG +boolean ftm_bt_hci_hal_nvm_download_init() +{ + bt_qsoc_config_params_struct_type run_time_params; + bt_qsoc_lookup_param soc_data; + bt_qsoc_nvm_status nvm_status; + bt_qsoc_enum_type soc_type; + boolean returnStatus = TRUE; + int loopCount; + bt_qsoc_enum_nvm_mode nvm_mode = NVM_AUTO_MODE; + + soc_data.app_ver_str = (char *)bt_soc_app_version_string; + soc_data.hw_ver_str = (char *)bt_soc_hw_version; + soc_type = bt_qsoc_type_look_up(&soc_data); + + if (soc_type == BT_QSOC_R2B) + { + printf("bt_hci_qcomm_init Failed R2B Not supported\n"); + returnStatus = FALSE; + } + else if (soc_type == BT_QSOC_R2C) + { + printf("bt_hci_qcomm_init Failed R2C Not supported"); + returnStatus = FALSE; + } + else + { +#ifdef FTM_DEBUG + printf("\nbt_hci_qcomm_init : Found QSoC type %d.\n", soc_type); +#endif + } + // default run-time parameters for SOC + memmove((uint8*)(&run_time_params.bd_address[0]), + (const uint8 *)(&(default_bt_bd_addr[0])), + BT_QSOC_MAX_BD_ADDRESS_SIZE); + run_time_params.refclock_type = BT_SOC_REFCLOCK_19P2MHZ; + run_time_params.clock_sharing =BT_SOC_CLOCK_SHARING_ENABLED; + run_time_params.soc_logging = 0; + run_time_params.bt_2_1_lisbon_disabled = 0; + /* ROM defualt LE & BR/EDR SoC power class configurations + */ + run_time_params.bt_qsoc_bredr_dev_class = BT_QSOC_DEV_CLASS1; + run_time_params.bt_qsoc_le_dev_class = BT_QSOC_DEV_CLASS2; + + /* After the Firmware is detected, start intializing the Poke table */ + if ( returnStatus != FALSE) + { + /* Patch: Pokes Only specific to R3 */ + global_state = FTM_SOC_POKE8_TBL_INIT; + if ( soc_type == BT_QSOC_R3 ) + { + printf("bt_hci_qcomm_init - Initialize R3 Poke table"); + loopCount = 0; + if ( (ftm_bt_hci_hal_vs_sendcmd( + BT_QSOC_EDL_CMD_OPCODE, + (uint8 *)bt_qsoc_vs_poke8_tbl_r3[loopCount].vs_poke8_data, + bt_qsoc_vs_poke8_tbl_r3[loopCount].vs_poke8_data_len) + ) != TRUE) + { + printf("bt_hci_qcomm_init Failed Poke VS Set Cmds"); + returnStatus = FALSE; + return returnStatus; + } + loopCount++; + } + memcpy(&soc_cfg_parameters.run_time_params,&run_time_params, + sizeof(bt_qsoc_config_params_struct_type)); + soc_cfg_parameters.soc_type = soc_type; + soc_cfg_parameters.nvm_mode = nvm_mode; + } + else + { + nvm_status = bt_qsoc_nvm_open(soc_type, nvm_mode, &run_time_params); + + if(nvm_status != BT_QSOC_NVM_STATUS_SUCCESS) + return FALSE; + global_state = FTM_SOC_DOWNLOAD_NVM; + /* Send all the NVM data to the SOC */ + returnStatus = ftm_bt_hci_hal_retrieve_send_nvm(); + } + + return returnStatus; +} +#endif +/*=========================================================================== +FUNCTION ftm_bt_hal_soc_init + +DESCRIPTION + Opens the handle to UART/SMD, configures the BT SoC high level power, + and initiates a read for application version + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hal_soc_init(int mode) +{ + request_status ret = 0; + int i,init_success = 0; + char value; + + if(!is_transportSMD && !isLatestTarget()){ + if(ftm_bt_power_hal_check() != BT_ON) + { + ret = ftm_bt_power_hal_set(BT_ON); + if(ret != STATUS_SUCCESS) + { + return FALSE; + } + } + else + return FALSE; + } + + ret = ftm_bt_hci_hal_init_transport(mode) ; +#ifdef FTM_DEBUG + printf("Transport open ret = %d\n",ret); +#endif + if(ret != STATUS_SUCCESS) + { + return FALSE; + } + if(mode != MODE_FM) { + /*ToDo: this can be featuturized under USE_LIBSOCCFG */ + return ftm_bt_hci_hal_read_app_version(); + } + return TRUE; +} + +/*=========================================================================== +FUNCTION ftm_bt_dispatch + +DESCRIPTION + Processes the BT FTM packet and dispatches the command to FTM HCI driver + +DEPENDENCIES + NIL + +RETURN VALUE + NIL,The error in the Command Processing is sent to the DIAG App on PC via + log packets + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_bt_dispatch(void *ftm_bt_pkt ,int cmd_len ) +{ + int ret; + memcpy(bt_ftm_buffer, (void*)ftm_bt_pkt, cmd_len); + ret = ftm_bt_hci_send_cmd((uint8 *) bt_ftm_buffer, cmd_len); + if (ret != TRUE) + { + ftm_log_send_msg(&event_buf_user_unknown_err[0],logsize); + printf("Error->Send FTM command failed:: %d\n", ret); + /** We had a premature exit here even before the command is Queued + * So notify the semaphore to wait for the next command + */ + sem_post(&semaphore_cmd_complete); + return ; + } + return ; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_send_cmd + +DESCRIPTION + Helper Routine to process the HCI cmd and invokes the sub routines to intialise + /deinitialise the SoC if needed based on the state of the FTM module + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_send_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +) +{ + request_status ret = 0; + boolean status = FALSE; + if(NULL == cmd_buf) + { + return FALSE; + } + #ifdef BT_NV_SUPPORT + if (*cmd_buf == FTM_BT_CMD_NV_READ) + { + status = ftm_bt_send_nv_read_cmd(cmd_buf, cmd_len); + return status; + } + if (*cmd_buf == FTM_BT_CMD_NV_WRITE) + { + status = ftm_bt_send_nv_write_cmd(cmd_buf, cmd_len); + return status; + } +#endif /* End of BT_NV_SUPPORT */ + + if (*cmd_buf == FTM_BT_DRV_START_TEST) + { + /** Deinit the queue only if we are not initialised */ + if(global_state != FTM_SOC_NOT_INITIALISED) + { + ftm_bt_hci_hal_deinit_transport(); + if(!is_transportSMD && !isLatestTarget() ) + ftm_bt_power_hal_set(BT_OFF); + } + if(ftm_bt_conn_test() != TRUE) + return FALSE; +#ifdef FTM_DEBUG + printf("\nBT Soc Shutdown\n"); +#endif + global_state = FTM_SOC_NOT_INITIALISED; + } + + if(global_state == FTM_SOC_NOT_INITIALISED) + { +#ifdef HAS_BLUEZ_BUILDCFG + // BT disabled for FTM to procceed + // BT test is only aplicable for BLUEZ stack + if(system("/system/xbin/bttest disable") != 0) + { + printf("\nbttest disable failed"); + } + else + { + /* Bluetooth resources like bluetoothd & hciattach (if applicable + * based on transport) are asynchronously cleaned. + * This delay ensures that the transport device is released before + * being used by BT-FTM module. + * Note: This delay as expected is < 5 seconds timeout set up for + * the command complete of the received BT FTM commmand. */ + printf("\nsleep for 2 seconds"); + usleep(2000000); + } +#endif + ptr_powerup.cmd_buf = cmd_buf; + ptr_powerup.cmd_len = cmd_len; + /*To identify the transport based on the target name*/ + is_transportSMD = ftm_bt_hci_hal_set_transport(); + /* Creating power up thread for asynchronous completion of request */ + status = ftm_bt_hal_soc_init(MODE_BT); + if (*cmd_buf == FM_HCI_CMD_PKT) + status = ftm_bt_hal_soc_init(MODE_FM); + } + else + { + ret = ftm_bt_hci_hal_nwrite((uint8 *) cmd_buf, cmd_len); + if(ret == STATUS_SUCCESS) + status = TRUE; + } + return status; +} +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_read_event + +DESCRIPTION + Helper Routine to read the HCI event by invoking the UART/SMD HAL read routines + and returns the event in the pointer passed + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_hal_read_event (uint8 * event_buf_ptr) +{ + boolean status = FALSE; + boolean long_event = FALSE; + request_status rx_status; + int event_bytes; + int i, ret_val; + /*hci packet is not required to carry the Packet indicator (for UART interfaces) for msm8960 + as it is using share memory interface */ + rx_status = ftm_bt_hci_hal_nread(event_buf_ptr , PROTOCOL_BYTE_SIZE); + if (rx_status == STATUS_SHORT_READ) + { + printf("ftm_bt_hci_qcomm_handle_event: VERY SHORT READ!\n"); + return status; + } + + printf("%s:protocol byte: %02X\n", __FUNCTION__, event_buf_ptr[0]); + /* else get rest of the packet */ + if(event_buf_ptr[0] == BT_HCI_ACL_PKT) + { + rx_status = ftm_bt_hci_hal_nread(event_buf_ptr + PROTOCOL_BYTE_SIZE, HCI_ACL_HDR_SIZE - PROTOCOL_BYTE_SIZE); + if (rx_status == STATUS_SHORT_READ) + { + printf("ftm_bt_hci_qcomm_handle_event: VERY SHORT READ!\n"); + return status; + } + + event_bytes = ( event_buf_ptr[HCI_ACL_HDR_SIZE - 1 ] << 8 ) | ( event_buf_ptr[HCI_ACL_HDR_SIZE - 2 ] ) ; + if (HC_VS_MAX_ACL < event_bytes) + { + printf("ftm_bt_hci_qcomm_handle_event: LONG ACL PKT!\n"); + long_event = TRUE; + event_bytes = HC_VS_MAX_ACL; + } + + rx_status = ftm_bt_hci_hal_nread(&(event_buf_ptr[HCI_ACL_HDR_SIZE]), event_bytes); + + if (rx_status == STATUS_SUCCESS) + { + status = TRUE; + } + else + { + printf("ftm_bt_hci_qcomm_handle_event: SHORT READ!\n"); + fflush (stderr); + } + + event_bytes += HCI_ACL_HDR_SIZE; + } + else if((event_buf_ptr[0] == BT_HCI_EVT_PKT) || (event_buf_ptr[0] == FM_HCI_EVT_PKT)) + { + rx_status = ftm_bt_hci_hal_nread(event_buf_ptr + PROTOCOL_BYTE_SIZE, HCI_EVT_HDR_SIZE - PROTOCOL_BYTE_SIZE); + if (rx_status == STATUS_SHORT_READ) + { + printf("ftm_bt_hci_qcomm_handle_event: VERY SHORT READ!\n"); + return status; + } + + event_bytes = event_buf_ptr[HCI_EVT_HDR_SIZE - 1 ]; + if (HC_VS_MAX_CMD_EVENT < event_bytes) + { + printf("ftm_bt_hci_qcomm_handle_event: LONG EVENT!\n"); + long_event = TRUE; + event_bytes = HC_VS_MAX_CMD_EVENT; + } + rx_status = ftm_bt_hci_hal_nread(&(event_buf_ptr[HCI_EVT_HDR_SIZE]), event_bytes); + + if (rx_status == STATUS_SUCCESS) + { + status = TRUE; + } + else + { + printf("ftm_bt_hci_qcomm_handle_event: SHORT READ!\n"); + fflush (stderr); + } + + event_bytes += HCI_EVT_HDR_SIZE; + } + else + { + printf("ftm_bt_hci_qcomm_handle_event: Unknown packet type!\n"); + return status; + } + + /* + ** Validate if the loopback command event has arrived and has succsfull + ** response from FW, if yes enable slimbus to validate pinc connectivity + ** test + */ + + if ( event_buf_ptr[0] == BT_HCI_EVT_PKT && + event_buf_ptr[LOOP_BACK_EVT_OGF_BIT] == LOOP_BACK_EVT_OGF && + event_buf_ptr[LOOP_BACK_EVT_OCF_BIT] == LOOP_BACK_EVT_OCF && + event_buf_ptr[LOOP_BACK_EVT_STATUS_BIT] == LOOP_BACK_EVT_STATUS && + is_slim_bus_test == 1) + { + printf("\nInitializing slim bus for pin-connectivity\n"); + fd_pintest = open("/dev/pintest",O_RDONLY, O_NONBLOCK); + if(fd_pintest < 0) + printf("\nfailed to open\n"); + ret_val = ioctl(fd_pintest, BT_CMD_SLIM_TEST, NULL); + event_buf_ptr[PIN_CON_EVENT_LEN_BIT] = PIN_CON_EVENT_LEN; + event_buf_ptr[PIN_CON_EVT_OCF_BIT] = PIN_CON_CMD_OCF; + event_buf_ptr[PIN_CON_EVT_OGF_BIT] = PIN_CON_CMD_OGF; + event_buf_ptr[PIN_CON_EVT_SUB_OP_BIT] = PIN_CON_CMD_SUB_OP; + event_buf_ptr[PIN_CON_INTERFACE_ID_EVT_BIT] = PIN_CON_INTERFACE_ID; + event_bytes += EXT_PIN_CON_LEN; + if( ret_val < 0) { + event_buf_ptr[PIN_CON_EVT_STATUS_BIT] = ret_val; + printf("\nFailed to initialise slim bus %d\n", ret_val); + status = FALSE; + } else { + event_buf_ptr[PIN_CON_EVT_STATUS_BIT] = 0; + printf("\nSlim bus initiazed succesfully\n"); + } + } + + if (verbose == 1) + { + if((event_buf_ptr[0] == BT_HCI_EVT_PKT) || (event_buf_ptr[0] == FM_HCI_EVT_PKT)) + { + printf("[%s] %s: EVT:", get_current_time(), __FUNCTION__); + for (i = 0; i < event_bytes; i++) + { + printf(" %02X", event_buf_ptr[i]); + } + + printf(long_event? " ...\n": "\n"); + } + else if (event_buf_ptr[0] == BT_HCI_ACL_PKT) + { + printf("[%s] %s: ACL packet: %d bytes\n", get_current_time(), __FUNCTION__, event_bytes); + + printf(long_event? " ...\n": "\n"); + } + } + ftm_log_send_msg(event_buf_ptr,event_bytes); + return status; +} + +boolean ftm_bt_hci_hal_retrieve_nvm_and_send_efs(FILE* fp) +{ + unsigned char payload[NVM_PAYLOAD_MAXLENGTH]; + unsigned char header[HCI_CMD_HDR_SIZE]; + int n = 0; + int len=0; + static const bt_qsoc_cfg_tbl_struct_type bt_qsoc_tag27 = + { + 0x04, {0x01, 0x1B, 0x01, 0x00} + }; + + n = fread(header, 1, HCI_CMD_HDR_SIZE, fp); + + if(feof(fp)) + { + if(nvm_cmd) + free(nvm_cmd); + fclose(fp); + sleep_stage = 0; + if(!isLatestTarget()){//Do not disable sleep for ROME + global_state = FTM_SOC_SLEEP_DISABLE; + if ( (ftm_bt_hci_hal_vs_sendcmd ( + BT_QSOC_NVM_ACCESS_OPCODE,(uint8 *)(bt_qsoc_tag27.vs_cmd_data), + bt_qsoc_tag27.vs_cmd_len )) != TRUE ) + return FALSE; + sleep_stage++; + } + return TRUE; + } + + /*Last byte gives the length*/ + len = (int)header[3]; + + printf("PayLoad length: %d\n", len); + n = fread(payload, 1, len, fp); + + /*Form the resultant buffer*/ + if(nvm_cmd) + { + /*Delete the previous buffer*/ + free(nvm_cmd); + } + nvm_cmd = (unsigned char*)malloc(HCI_CMD_HDR_SIZE+len); + if(nvm_cmd) + { + memcpy(nvm_cmd, header, HCI_CMD_HDR_SIZE); + memcpy(nvm_cmd+HCI_CMD_HDR_SIZE, payload, len); + + global_state = FTM_SOC_DOWNLOAD_NVM_EFS; + + if(ftm_bt_hci_hal_nwrite((uint8 *) &nvm_cmd[0],HCI_CMD_HDR_SIZE+len) == STATUS_SUCCESS) + return TRUE; + } + return FALSE; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_qcomm_handle_event + +DESCRIPTION + Routine called by the HAL layer reader thread to process the HCI events + The post conditions of each event is covered in a state machine pattern + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_qcomm_handle_event () +{ + boolean status = TRUE; + char filename[MAX_FILE_NAME]; +#ifdef USE_LIBSOCCFG + bt_qsoc_nvm_status nvm_status; +#endif + int ret = 0; +#ifdef FTM_DEBUG + printf("ftm_bt_hci_qcomm_handle_event global_state --> %d\n",global_state); +#endif + switch(global_state) + { + case FTM_SOC_READ_APP_VER: + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) { + printf("Failed to read VS event"); + return FALSE; + } + ftm_bt_hci_hal_vs_event(&event_buf[1], 2 + event_buf[2]); + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) { + printf("Failed to read HCI event"); + return FALSE; + } + /* Until libsoccfg is part of the Android system + * we will use the system call to perform the + * soc initialisation + */ +#ifndef USE_LIBSOCCFG + if(!isLatestTarget()) + { + ret = system("/system/bin/hci_qcomm_init -e -H"); + if(ret != 0) + { + return FALSE; + } + else + { + global_state = FTM_SOC_INITIALISED; + } + } + else + { +#if 0//Do not Disable Sleep for ROME + global_state = FTM_SOC_SLEEP_DISABLE; + if ( (ftm_bt_hci_hal_vs_sendcmd(BT_QSOC_NVM_ACCESS_OPCODE, + (uint8 *)(bt_qsoc_tag17_latest_hw.vs_cmd_data), + bt_qsoc_tag17.vs_cmd_len )) != TRUE ) + { + return FALSE; + } +#endif + if(ftm_bt_hci_hal_send_reset_cmd() != TRUE) + return FALSE; + } + printf("\nFTM Global state = %d\n",global_state); + // Dont send HCI reset before inband sleep disable + if (!isLatestTarget()) + { + if(ptr_powerup.cmd_buf[0] == FTM_BT_DRV_START_TEST) + { + ftm_log_send_msg(&event_buf_user_cmd_pass[0],logsize); + sem_post(&semaphore_cmd_complete); + return TRUE; + } + if(ftm_bt_hci_hal_nwrite((uint8 *) ptr_powerup.cmd_buf, + ptr_powerup.cmd_len) != STATUS_SUCCESS) + return FALSE; + } +#else + if(ftm_bt_hci_hal_read_hw_version() != TRUE) + return FALSE; +#ifdef FTM_DEBUG + printf("FTM_SOC_READ_APP_VER Done\n"); +#endif +#endif + break; +#ifdef USE_LIBSOCCFG + case FTM_SOC_READ_HW_VER: + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + ftm_bt_hci_hal_vs_event(&event_buf[1], 2 + event_buf[2]); + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + + if(ftm_bt_hci_hal_nvm_download_init() != TRUE) + return FALSE; +#ifdef FTM_DEBUG + printf("FTM_SOC_READ_HW_VER Done\n"); +#endif + break; + case FTM_SOC_POKE8_TBL_INIT : + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + if(loopCount < BT_QSOC_R3_POKETBL_COUNT) + { + if ( (ftm_bt_hci_hal_vs_sendcmd( + BT_QSOC_EDL_CMD_OPCODE, + (uint8 *)bt_qsoc_vs_poke8_tbl_r3[loopCount].vs_poke8_data, + bt_qsoc_vs_poke8_tbl_r3[loopCount].vs_poke8_data_len) + ) != TRUE) + { + printf("bt_hci_qcomm_init Failed Poke VS Set Cmds"); + return FALSE; + } + loopCount++; + } + else + { + nvm_status = bt_qsoc_nvm_open(soc_cfg_parameters.soc_type, + soc_cfg_parameters.nvm_mode, + &soc_cfg_parameters.run_time_params); + + if(nvm_status != BT_QSOC_NVM_STATUS_SUCCESS) + return FALSE; + global_state = FTM_SOC_DOWNLOAD_NVM; + /* Send all the NVM data to the SOC */ + if(ftm_bt_hci_hal_retrieve_send_nvm() != TRUE) + return FALSE; + } + break; + case FTM_SOC_DOWNLOAD_NVM: + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + if(ftm_bt_hci_hal_retrieve_send_nvm()!= TRUE) + return FALSE; +#ifdef FTM_DEBUG + printf("FTM_SOC_DOWNLOAD_NVM in progress\n"); +#endif + break; +#endif //USE_LIBSOCCFG + + case FTM_SOC_DOWNLOAD_NVM_EFS: + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + if(ftm_bt_hci_hal_retrieve_nvm_and_send_efs(fp) != TRUE) + return FALSE; + printf("FTM_SOC_DOWNLOAD_NVM in progress\n"); + break; + + case FTM_SOC_SLEEP_DISABLE: + /* Read the VS event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + if(sleep_stage == 1) + { +#ifdef FTM_DEBUG + printf("Sleep Stage tag 17 set\n"); +#endif + if ( (ftm_bt_hci_hal_vs_sendcmd(BT_QSOC_NVM_ACCESS_OPCODE, + (uint8 *)(bt_qsoc_tag17.vs_cmd_data), + bt_qsoc_tag17.vs_cmd_len )) != TRUE ) + { + return FALSE; + } + sleep_stage++; + return TRUE; + } + if(ftm_bt_hci_hal_send_reset_cmd() != TRUE) + return FALSE; +#ifdef FTM_DEBUG + printf("FTM_SOC_SLEEP_DISABLE done\n"); +#endif + break; + case FTM_SOC_RESET: + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + global_state = FTM_SOC_INITIALISED; + if(ptr_powerup.cmd_buf[0] == FTM_BT_DRV_START_TEST) + { + ftm_log_send_msg(&event_buf_user_cmd_pass[0],logsize); + sem_post(&semaphore_cmd_complete); + return TRUE; + } + if(ftm_bt_hci_hal_nwrite((uint8 *) ptr_powerup.cmd_buf, + ptr_powerup.cmd_len) != STATUS_SUCCESS) + return FALSE; +#ifdef FTM_DEBUG + printf("FTM_SOC_RESET done queued the Command\n"); +#endif + break; + case FTM_SOC_INITIALISED : + /* Read out the HCI event*/ + if(ftm_bt_hci_hal_read_event(event_buf) != TRUE) + return FALSE; + sem_post(&semaphore_cmd_complete); + break; + default : + return FALSE; + } + return status; +} + +/*=========================================================================== +FUNCTION isLatestTarget + +DESCRIPTION +For all the target/solution which has Bluedroid as stack and libbt-vendor as +vendor initialization component considered as latest target + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean isLatestTarget() +{ +#ifdef ANDROID + int ret = 0; + char bt_soc_type[PROPERTY_VALUE_MAX]; + ret = property_get("qcom.bluetooth.soc", bt_soc_type, NULL); + if (ret != 0) + { + if (!strncasecmp(bt_soc_type, "ath3k", sizeof("ath3k"))) + { + return FALSE; + } + } + return TRUE; +#else + return TRUE; +#endif +} diff --git a/qca/ftm/src/ftm_bt.h b/qca/ftm/src/ftm_bt.h new file mode 100644 index 000000000..c807977e5 --- /dev/null +++ b/qca/ftm/src/ftm_bt.h @@ -0,0 +1,289 @@ +/*========================================================================== + + FTM BT Task Header File + +Description + Global Data declarations of the ftm bt component. + +# Copyright (c) 2010-2011, 2013-2014 by Qualcomm Technologies, Inc. +# All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +09/28/11 rrr Moved peristent NV item related APIs to CPP, + for having BD address being programmed twice if previous + BD address was random generated. +09/03/11 agaja Added support for NV_READ and NV_WRITE Commands to write + onto Persist File system +02/08/11 braghave Changes to read the HCI commands from a binary file for + non-Android case +06/18/10 rakeshk Created a header file to hold the definitons for ftm bt + task +===========================================================================*/ + +#ifdef CONFIG_FTM_BT + +#include "diagpkt.h" +#include +#ifdef USE_LIBSOCCFG +#include "btqsocnvm.h" +#include "btqsocnvmutils.h" +#endif + +/* ------------------------------------------------------------------------- +** Definitions and Declarations +** ------------------------------------------------------------------------- */ + +#define FTM_BT_CMD_CODE 4 /* BT FTM Command code */ +#define FTM_FM_CMD_CODE 28 /* FM FTM Command code */ +#define HCI_EVT_HDR_SIZE 3 +#define HCI_ACL_HDR_SIZE 5 +#define PROTOCOL_BYTE_SIZE 1 +#define HC_VS_MAX_CMD_EVENT 260 +#define HC_VS_MAX_ACL 1200 +#define FTM_BT_HCI_USER_CMD 0 +#define BT_FTM_CMD_RSP_LEN 1100 +#define FTM_BT_DRV_START_TEST 0xA + +/* MACROS for pin connectivty test*/ +#define BT_CMD_SLIM_TEST 0xBFAC +#define LOOP_BACK_EVT_OGF 0x02 +#define LOOP_BACK_EVT_OCF 0x18 +#define LOOP_BACK_EVT_STATUS 0x00 +#define LOOP_BACK_EVT_OGF_BIT 0x04 +#define LOOP_BACK_EVT_OCF_BIT 0x05 +#define LOOP_BACK_EVT_STATUS_BIT 0x06 + + +#define FTM_BT_LOG_HEADER_SIZE (sizeof(ftm_bt_log_pkt_type) - 1) + + +/* Vendor Specific command codes */ +#define BT_QSOC_EDL_CMD_OPCODE (0xFC00) +#define BT_QSOC_NVM_ACCESS_OPCODE (0xFC0B) + +#define BT_QSOC_EDL_CMD_CODE (0x00) +#define BT_QSOC_NVM_ACCESS_CODE (0x0B) +#define BT_QSOC_VS_EDL_APPVER_RESP (0x02) + +#ifndef HC_VS_MAX_CMD_EVENT +#define HC_VS_MAX_CMD_EVENT 260 +#endif /* HC_VS_MAX_CMD_EVENT */ + +#define BT_QSOC_MAX_NVM_CMD_SIZE 0x64 /* Maximum size config (NVM) cmd */ +#define BT_QSOC_MAX_BD_ADDRESS_SIZE 0x06 /**< Length of BT Address */ + +#ifndef HCI_CMD_HDR_SIZE +#define HCI_CMD_HDR_SIZE 4 +#endif /* HCI_CMD_HDR_SIZE */ + +#ifndef HCI_EVT_HDR_SIZE +#define HCI_EVT_HDR_SIZE 3 +#endif /* HCI_EVT_HDR_SIZE */ + +#define FTM_BT_LOG_PKT_ID 0x01 + + +#define BT_HCI_CMD_PKT 0x01 +#define BT_HCI_ACL_PKT 0x02 +#define BT_HCI_EVT_PKT 0x04 + +#define BT_HCI_CMD_CMPLT_EVT 0x0E +#define FM_HCI_EVT_PKT 0x14 +#define FM_HCI_CMD_PKT 0x11 + +extern int boardtype; + +/* VS command structure */ +typedef struct +{ + uint8 vs_cmd_len; + uint8 vs_cmd_data[BT_QSOC_MAX_NVM_CMD_SIZE]; +} bt_qsoc_cfg_tbl_struct_type; + +/* First Commamd structure - Used to store the First command for later +* processing +*/ +struct first_cmd +{ + uint8 *cmd_buf; + int cmd_len; +}; + +/* FTM Global State - Enum defines the various states of the FTM +* module +*/ +typedef enum ftm_state +{ + FTM_SOC_NOT_INITIALISED, + FTM_SOC_READ_APP_VER, + FTM_SOC_READ_HW_VER, + FTM_SOC_POKE8_TBL_INIT, + FTM_SOC_DOWNLOAD_NVM, + FTM_SOC_DOWNLOAD_NVM_EFS, + FTM_SOC_SLEEP_DISABLE, + FTM_SOC_RESET, + FTM_SOC_INITIALISED +}ftm_state; +/* FTM CMD status */ +typedef enum ftm_log_packet_type +{ + FTM_USER_CMD_PASS, + FTM_USER_CMD_FAIL, + FTM_HCI_EVENT +}ftm_log_packet_type; + +/* FTM Log Packet - Used to send back the event of a HCI Command */ +typedef PACKED struct +{ + log_hdr_type hdr; + byte data[1]; /* Variable length payload, + look at FTM log id for contents */ +} ftm_bt_log_pkt_type; + + +/* FTM (BT) PKT Header */ +typedef PACKED struct +{ + word cmd_id; /* command id (required) */ + word cmd_data_len; /* request pkt data length, excluding the diag and ftm headers + (optional, set to 0 if not used)*/ + word cmd_rsp_pkt_size; /* rsp pkt size, size of response pkt if different then req pkt + (optional, set to 0 if not used)*/ +} ftm_bt_cmd_header_type; + +/* Bluetooth FTM packet */ +typedef PACKED struct +{ + diagpkt_subsys_header_type diag_hdr; + ftm_bt_cmd_header_type ftm_hdr; + byte data[1]; +} ftm_bt_pkt_type; + +/* SoC Cfg open Struct*/ +#ifdef USE_LIBSOCCFG +typedef struct +{ + bt_qsoc_config_params_struct_type run_time_params; + bt_qsoc_enum_nvm_mode nvm_mode; + bt_qsoc_enum_type soc_type; +}ftm_bt_soc_runtime_cfg_type; +#endif + +/*=========================================================================== +FUNCTION ftm_bt_err_timedout + +DESCRIPTION + This routine triggers the shutdown of the HCI and Power resources in case + a HCI command previously sent times out. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + NONE + +===========================================================================*/ +void ftm_bt_err_timedout(); + +/*=========================================================================== +FUNCTION ftm_bt_dispatch + +DESCRIPTION + Processes the BT FTM packet and dispatches the command to FTM HCI driver + +DEPENDENCIES + NIL + +RETURN VALUE + NIL,The error in the Command Processing is sent to the DIAG App on PC via + log packets + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_bt_dispatch(void *ftm_bt_pkt ,int cmd_len ); + +/*=========================================================================== +FUNCTION bt_hci_send_ftm_cmd + +DESCRIPTION + Helper Routine to process the HCI cmd and invokes the sub routines to intialise + the SoC if needed based on the state of the FTM module + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ + +boolean ftm_bt_hci_send_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +); + +/*=========================================================================== +FUNCTION bt_hci_hal_vs_sendcmd + +DESCRIPTION + Helper Routine to process the VS HCI cmd and constucts the HCI packet before + calling bt_hci_send_ftm_cmd routine + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_hal_vs_sendcmd +( +uint16 opcode, /* Opcode */ +uint8 *pCmdBuffer, /* Pointer to Payload*/ +uint8 nSize /* Cmd Size */ +); + +/*=========================================================================== +FUNCTION isLatestTarget + +DESCRIPTION +For all the target/solution which has Bluedroid as stack and libbt-vendor as +vendor initialization component considered as latest target + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean isLatestTarget(); +char *get_current_time(void); +#endif /* CONFIG_FTM_BT */ diff --git a/qca/ftm/src/ftm_bt_common.h b/qca/ftm/src/ftm_bt_common.h new file mode 100644 index 000000000..5704ba65e --- /dev/null +++ b/qca/ftm/src/ftm_bt_common.h @@ -0,0 +1,115 @@ +/*========================================================================== + + FTM BT Commom Header File + +Description + The header file includes helper enums for request_status and bt_power_state. + +# Copyright (c) 2010-2011, 2014 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +09/28/11 rrr Common utility API abstracted, +06/18/10 rakeshk Created a header file to hold the helper enums for + request_status and bt_power_state +========================================================================*/ + +#ifdef CONFIG_FTM_BT + +#include "event.h" +#include "msg.h" +#include "log.h" + +#include "diag_lsm.h" +#include + +#ifndef __FTM_BT_COMMON_H__ + +#define __FTM_BT_COMMON_H__ + +#define TRUE 1 +#define FALSE 0 + +/* request_status - enum to encapuslate the status of a HAL request*/ +typedef enum request_status +{ + STATUS_SUCCESS, + STATUS_FAIL, + STATUS_NO_RESOURCES, + STATUS_SHORT_WRITE, + STATUS_SHORT_READ +}request_status; + +/* request_status - enum to encapuslate the possible statea of BT power*/ +typedef enum bt_power_state +{ + BT_OFF = 0x30, /* Its the value 0 to be input to rfkill driver */ + BT_ON = 0x31 /* ASCII value for '1'*/ +}bt_power_state; + +typedef enum +{ + FTM_BT_DRV_NO_ERR = 0, + FTM_BT_DRV_CONN_TEST_FAILS, + FTM_BT_DRV_QSOC_POWERUP_FAILS, + FTM_BT_DRV_RX_PKT_TYPE_NOT_SUPPORTED, + FTM_BT_DRV_SIO_OPEN_FAILS, + FTM_BT_DRV_NO_SOC_RSP_TOUT, + FTM_BT_DRV_BAD_NVM, +#ifdef BT_NV_SUPPORT + FTM_BT_NV_READ_FAIL, + FTM_BT_NV_WRITE_FAIL, +#endif + FTM_BT_DRV_UNKNOWN_ERR +} ftm_bt_drv_err_state_type; + +/*=========================================================================== +FUNCTION ftm_bt_hci_qcomm_handle_event + +DESCRIPTION + Routine called by the HAL layer reader thread to process the HCI events + The post conditions of each event is covered in a state machine pattern + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_qcomm_handle_event(); + +/*=========================================================================== +FUNCTION ftm_log_send_msg + +DESCRIPTION + Processes the buffer sent and sends it to the libdiag for sending the Cmd + response + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ + + +void ftm_log_send_msg(const uint8 *pEventBuf,int event_bytes); +#endif //__FTM_BT_COMMON_H__ +#endif /* CONFIG_FTM_BT */ diff --git a/qca/ftm/src/ftm_bt_hci_hal.h b/qca/ftm/src/ftm_bt_hci_hal.h new file mode 100644 index 000000000..c1b82efa1 --- /dev/null +++ b/qca/ftm/src/ftm_bt_hci_hal.h @@ -0,0 +1,161 @@ +/*========================================================================== + + FTM BT HCI PFAL Header File + +Description + Warpper API definitions of the ftm bt hci hal component. + +# Copyright (c) 2010 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a header file to hold the wrapper HAL + definitions for HCI UART control +===========================================================================*/ + +#include "ftm_bt_common.h" +#include "ftm_bt_hci_pfal.h" +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_set_transport + +DESCRIPTION + sets the type of transport based on the msm type + +DEPENDENCIES + NIL + +RETURN VALUE +returns the type of transport + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_hal_set_transport() +{ + return ftm_bt_hci_pfal_set_transport(); +} +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_deinit_transport + +DESCRIPTION + Platform independent wrapper API which intiatea a De-intialise of UART/SMD + resources with PFAL layer and returns the status of the PFAL operation + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_hal_deinit_transport() +{ + return ftm_bt_hci_pfal_deinit_transport(); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_init_transport + +DESCRIPTION + Platform independent wrapper API which intiatea a intialise of UART/SMD + resources with PFAL layer and returns the status of the PFAL operation + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_hal_init_transport (int mode) +{ + return ftm_bt_hci_pfal_init_transport(mode); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_nwrite + +DESCRIPTION + Platform independent wrapper API which intiates a write operation + with the PFAL layer and returns the status of the PFAL operation. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_hal_nwrite(uint8 *buf, int size) +{ + return ftm_bt_hci_pfal_nwrite(buf,size); + +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_nread + +DESCRIPTION + Platform independent wrapper API which intiates a read operation + with the PFAL layer and returns the status of the PFAL operation. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_hal_nread(uint8 *buf, int size) +{ + return ftm_bt_hci_pfal_nread(buf,size); +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_hal_changebaudrate + +DESCRIPTION + Platform independent wrapper API which intiatea a UART baud rate change + with the PFAL layer and returns the status of the PFAL request. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + TRUE if SUCCESS, else FAIL + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_hal_changebaudrate (uint32 new_baud) +{ + return ftm_bt_hci_pfal_changebaudrate(new_baud); +} + diff --git a/qca/ftm/src/ftm_bt_hci_pfal.h b/qca/ftm/src/ftm_bt_hci_pfal.h new file mode 100644 index 000000000..7bc199e41 --- /dev/null +++ b/qca/ftm/src/ftm_bt_hci_pfal.h @@ -0,0 +1,177 @@ +/*========================================================================== + + FTM BT HCI PFAL Header File + +Description + PFAL API declarations of the ftm bt hci pfal component. + +# Copyright (c) 2010 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a header file to hold the PFAL declarations for + HCI UART programming +===========================================================================*/ +#include "ftm_bt_common.h" + +#ifndef __FTM_BT_HCI_PFAL_H__ +#define __FTM_BT_HCI_PFAL_H__ + +#define PIN_CON_CMD_OGF 0xFC +#define PIN_CON_CMD_OCF 0x0C +#define PIN_CON_CMD_SUB_OP 0x38 +#define PIN_CON_INTERFACE_ID 0x01 +#define PIN_CON_EVENT_LEN 0x06 +#define EXT_PIN_CON_LEN 0x02 + +#define PIN_CON_CMD_OCF_BIT 0x01 +#define PIN_CON_CMD_OGF_BIT 0x02 +#define PIN_CON_CMD_SUBOP_BIT 0x04 +#define PIN_CON_CMD_INTER_BIT 0x05 + +#define PIN_CON_EVT_OGF_BIT 0x05 +#define PIN_CON_EVT_OCF_BIT 0x04 +#define PIN_CON_EVT_SUB_OP_BIT 0x07 +#define PIN_CON_INTERFACE_ID_EVT_BIT 0x08 +#define PIN_CON_EVENT_LEN_BIT 0x02 +#define PIN_CON_EVT_STATUS_BIT 0x06 + +#define LOG_TAG "ftmdaemon" + +#define PRI_INFO " I" +#define PRI_WARN " W" +#define PRI_ERROR " E" +#define PRI_DEBUG " D" +#define PRI_VERB " V" + +#define ALOG(pri, tag, fmt, arg...) fprintf(stderr, tag pri ": " fmt"\n", ##arg) +#define ALOGV(fmt, arg...) ALOG(PRI_VERB, LOG_TAG, fmt, ##arg) +#define ALOGD(fmt, arg...) ALOG(PRI_DEBUG, LOG_TAG, fmt, ##arg) +#define ALOGI(fmt, arg...) ALOG(PRI_INFO, LOG_TAG, fmt, ##arg) +#define ALOGW(fmt, arg...) ALOG(PRI_WARN, LOG_TAG, fmt, ##arg) +#define ALOGE(fmt, arg...) ALOG(PRI_ERROR, LOG_TAG, fmt, ##arg) + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_set_transport + +DESCRIPTION + sets the type of transport based on the msm type + +DEPENDENCIES + NIL + +RETURN VALUE +returns the type of transport + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_pfal_set_transport(void); + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_deinit_transport + +DESCRIPTION + Platform specific routine to de-intialise the UART/SMD resource. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_deinit_transport(); + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_init_transport + +DESCRIPTION + Platform specific routine to intialise the UART/SMD resources. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_init_transport (); + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_nwrite + +DESCRIPTION + Platform specific routine to write the data in the argument to the UART/SMD + port intialised. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_nwrite(uint8 *buf, int size); + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_nread + +DESCRIPTION + Platform specific routine to read data from the UART/SMD port intialised into + the buffer passed in argument. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_nread(uint8 *buf, int size); + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_changebaudrate + +DESCRIPTION + Platform specific routine to intiate a change in baud rate + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + TRUE if SUCCESS, else FALSE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_pfal_changebaudrate (uint32 new_baud); + +#endif //__FTM_BT_HCI_PFAL_H__ diff --git a/qca/ftm/src/ftm_bt_hci_pfal_linux.c b/qca/ftm/src/ftm_bt_hci_pfal_linux.c new file mode 100644 index 000000000..e339567b7 --- /dev/null +++ b/qca/ftm/src/ftm_bt_hci_pfal_linux.c @@ -0,0 +1,674 @@ +/*========================================================================== + + FTM Platform specfic HCI UART/SMD File + +Description + Platform specific routines to program the UART/SMD descriptors + +# Copyright (c) 2010-2011, 2013 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/07/11 bneti Add support smd support for msm8960 +06/18/10 rakeshk Created a source file to implement platform specific + routines for UART +07/07/10 rakeshk Removed the conversion of 3.2 Mbps baud rate +01/07/10 rakeshk Added support for verbose logging of Cmd and events +===========================================================================*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bt_vendor_lib.h" +#include "ftm_bt_hci_pfal.h" +#include "ftm_common.h" +#include +#include "log.h" +#include +#include "hidl_client.h" + +#ifdef ANDROID +#define VENDOR_LIB "libbt-vendor.so" +#else +#define VENDOR_LIB "libbt-vendor.so.0" +#endif + +uint8_t is_slim_bus_test = 0; +#define UNUSED(x) (void)(x) + +/*identify the transport type*/ +static char *transport_dev; + +typedef enum { + BT_SOC_DEFAULT = 0, + BT_SOC_SMD = BT_SOC_DEFAULT, + BT_SOC_AR3K, + BT_SOC_ROME, + BT_SOC_CHEROKEE, + BT_SOC_NAPIER, + /* Add chipset type here */ + BT_SOC_RESERVED +} bt_soc_type; + +static void vendor_fwcfg_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_scocfg_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_lpm_vnd_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_audio_state_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void* vendor_alloc(int size) { + UNUSED(size); + return NULL; +} +static void vendor_dealloc(void *p_buf) { + UNUSED(p_buf); +} +static uint8_t vendor_xmit_cb(uint16_t opcode, void *p_buf, tINT_CMD_CBACK p_cback) { + UNUSED(opcode); + UNUSED(p_buf); + UNUSED(p_cback); + return 0; +} +static void vendor_epilog_cb(bt_vendor_op_result_t result) { + UNUSED(result); +} +static void vendor_a2dp_offload_cb(bt_vendor_op_result_t result, bt_vendor_opcode_t op, unsigned char handle) { + UNUSED(result); + UNUSED(op); + UNUSED(handle); +} + + +bt_vendor_interface_t *vendor_interface=NULL; +static const bt_vendor_callbacks_t vendor_callbacks = { + sizeof(bt_vendor_callbacks_t), + vendor_fwcfg_cb, + vendor_scocfg_cb, + vendor_lpm_vnd_cb, + vendor_audio_state_cb, + vendor_alloc, + vendor_dealloc, + vendor_xmit_cb, + vendor_epilog_cb, + vendor_a2dp_offload_cb +}; + + +/*BT HS UART TTY DEVICE */ +#define BT_HS_UART_DEVICE "/dev/ttyHS0" + +/*BT RIVA-SMD CHANNELS */ +#define APPS_RIVA_BT_ACL_CH "/dev/smd2" +#define APPS_RIVA_BT_CMD_CH "/dev/smd3" + +/* Variables to identify the platform */ +char transport_type[PROPERTY_VALUE_MAX]; +static boolean is_transportSMD; + +extern int soc_type; + +/* Reader thread handle */ +pthread_t hci_cmd_thread_hdl; +/* Pipe file descriptors for cancelling read operation */ +int pipefd[2]; +/* Transport file descriptor */ +int fd_transport; +/* Starting baud rate to init the tty device */ +int starting_baud = 115200; +/* Verbose output monitoring variable */ +int verbose = 1; +/* Defintion to convert integer baud rate to the + * Data type understood by tty device + */ +#define BAUDCLAUS(i) case (i): return ( B##i ) + +/*=========================================================================== +FUNCTION convert_baud + +DESCRIPTION + Routine to convert the integer baud rate to type speed_t + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + Converted Baud rate, else default 0 + +SIDE EFFECTS + None + +===========================================================================*/ +static speed_t convert_baud(uint32 baud_rate) +{ + switch (baud_rate) + { + BAUDCLAUS(50); + BAUDCLAUS(75); + BAUDCLAUS(110); + BAUDCLAUS(134); + BAUDCLAUS(150); + BAUDCLAUS(200); + BAUDCLAUS(300); + BAUDCLAUS(600); + BAUDCLAUS(1200); + BAUDCLAUS(1800); + BAUDCLAUS(2400); + BAUDCLAUS(4800); + BAUDCLAUS(9600); + BAUDCLAUS(19200); + BAUDCLAUS(38400); + BAUDCLAUS(57600); + BAUDCLAUS(115200); + BAUDCLAUS(230400); + BAUDCLAUS(460800); + BAUDCLAUS(500000); + BAUDCLAUS(576000); + BAUDCLAUS(921600); + BAUDCLAUS(1000000); + BAUDCLAUS(1152000); + BAUDCLAUS(1500000); + BAUDCLAUS(2000000); + BAUDCLAUS(2500000); + BAUDCLAUS(3000000); + BAUDCLAUS(3500000); + BAUDCLAUS(4000000); + + default: return 0; + } +} + +/*=========================================================================== +FUNCTION ftm_readerthread + +DESCRIPTION + Thread Routine to perfom asynchrounous handling of events coming on Uart/Smd + descriptor. It invokes a callback to the FTM BT layer to intiate a request + to read event bytes. + +DEPENDENCIES + The LifeTime of ReaderThraad is dependent on the status returned by the + call to ftm_bt_hci_qcomm_handle_event + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void *ftm_readerthread(void *ptr) +{ + UNUSED(ptr); + boolean status = FALSE; + int retval; + fd_set readfds; + int buf; + + do + { + FD_ZERO(&readfds); + FD_SET(fd_transport, &readfds); + FD_SET(pipefd[0],&readfds); + retval = select((pipefd[0] > fd_transport? pipefd[0] : fd_transport) + 1, + &readfds, NULL, NULL, NULL); + if(retval == -1) + { + printf("select failed\n"); + break; + } + if(FD_ISSET(pipefd[0],&readfds)) + { +#ifdef FTM_DEBUG + printf("Pipe descriptor set\n"); +#endif + read(pipefd[0],&buf,1); + if(buf == 1) + break; + } + if(FD_ISSET(fd_transport,&readfds)) + { +#ifdef FTM_DEBUG + printf("Read descriptor set\n"); +#endif + status = ftm_bt_hci_qcomm_handle_event(); + if(TRUE != status) + break; + } + } + while(1); +#ifdef FTM_DEBUG + printf("\nReader thread exited\n"); +#endif + return 0; +} +/*=========================================================================== +FUNCTION ftm_bt_pfal_set_transport + +DESCRIPTION + sets the type of transport based on the msm type + +DEPENDENCIES + NIL + +RETURN VALUE +returns the type of transport +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_pfal_set_transport(void) +{ + if (soc_type == BT_SOC_ROME || soc_type == BT_SOC_CHEROKEE || soc_type == BT_SOC_NAPIER) { + strlcpy(transport_type, "uart", sizeof(transport_type)); + printf("[%s]: Transport type is: %s\n", __FUNCTION__, transport_type); + is_transportSMD = 0; + transport_dev = BT_HS_UART_DEVICE; + } else { + strlcpy(transport_type, "smd", sizeof(transport_type)); + printf("[%s]: Transport type is: %s\n", __FUNCTION__, transport_type); + is_transportSMD = 1; + transport_dev = APPS_RIVA_BT_CMD_CH; + } + return is_transportSMD; +} + + +int init_transport_bdroid(boolean on) { + + void *so_handle; + unsigned char bdaddr[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; + request_status st; + int fd[CH_MAX], powerstate, ret; + + if (on) { + so_handle = dlopen(VENDOR_LIB, RTLD_NOW); + if (!so_handle) + { + ALOGE("Failed to load vendor component %s", dlerror()); + return -1; + } + + vendor_interface = (bt_vendor_interface_t *) dlsym(so_handle, "BLUETOOTH_VENDOR_LIB_INTERFACE"); + if (!vendor_interface) + { + ALOGE("Failed to accesst bt vendor interface"); + return -1; + } + + vendor_interface->init(&vendor_callbacks, bdaddr); + + ALOGI("Turn On BT power"); + powerstate = BT_VND_PWR_ON; + ret = vendor_interface->op(BT_VND_OP_POWER_CTRL, &powerstate); + if (ret < 0) + { + ALOGE("Failed to turn on power from bt vendor interface"); + return -1; + } + ret = vendor_interface->op(BT_VND_OP_USERIAL_OPEN, fd); + ALOGE("ret value: %d", ret); + /* This is just a hack; needs to be removed */ + ret = 1; + ALOGE("setting ret value to 1 manually"); + if (ret != 1) + { + ALOGE("Failed to get fd from bt vendor interface"); + return -1; + } else { + ALOGE("FD: %x", fd[0]); + return fd[0]; + } + } else { + if (vendor_interface) { + ALOGE("Close and cleanup the interfaces"); + int ret = vendor_interface->op(BT_VND_OP_USERIAL_CLOSE, NULL); + + ALOGE("ret value: %d", ret); + vendor_interface->cleanup(); + return 0; + } else { + + ALOGE("Not able to find vendor interface handle"); + return -1; + } + } +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_deinit_transport + +DESCRIPTION + Platform specific routine to de-intialise the UART/SMD resource. + +PLATFORM SPECIFIC DESCRIPTION + Closes the TTY/SMD file descriptor and sets the descriptor value to -1 + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + The Close of the descriptor will trigger a failure in the Reader Thread + and hence cause a Deinit of the ReaderThread + +===========================================================================*/ +request_status ftm_bt_hci_pfal_deinit_transport() +{ + int buf = 1; + write(pipefd[1],&buf,1); + if(!isLatestTarget()) + { + close(fd_transport); + fd_transport = -1; + } + else + { + //Use libbt-vendor for chip de-initialization + init_transport_bdroid(FALSE); + } + return STATUS_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_init_uart + +DESCRIPTION + Platform specific routine to intialise the UART/SMD resources. + +PLATFORM SPECIFIC DESCRIPTION + Opens the TTY/SMD device file descriptor, congiures the TTY/SMD device for CTS/RTS + flow control,sets 115200 for TTY as the default baudrate and starts the Reader + Thread + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_init_transport(int mode) +{ + struct termios term; + if(isLatestTarget()) + { + printf("%s: ",__func__ ); + //Use hidl_client_initialize for chip initialization + if (hidl_client_initialize(mode, &fd_transport) == false) { + printf("%s: HIDL client initialization failed \n", __func__); + return STATUS_NO_RESOURCES; + } + printf("%s: , fd:%d: ", __func__, fd_transport); + } + else + { + fd_transport = open(transport_dev, (O_RDWR | O_NOCTTY)); + + if (-1 == fd_transport) + { + return STATUS_NO_RESOURCES; + } + + if (tcflush(fd_transport, TCIOFLUSH) < 0) + { + close(fd_transport); + return STATUS_FAIL; + } + + if (tcgetattr(fd_transport, &term) < 0) + { + close(fd_transport); + return STATUS_FAIL; + } + + cfmakeraw(&term); + /* Set RTS/CTS HW Flow Control*/ + term.c_cflag |= (CRTSCTS | CLOCAL); + + if (tcsetattr(fd_transport, TCSANOW, &term) < 0) + { + close(fd_transport); + return STATUS_FAIL; + } + + /* Configure the /dev/ttyHS0 device to operate at 115200. + no need for msm8960 as it is using smd as transport + */ + if (!is_transportSMD) + if (ftm_bt_hci_pfal_changebaudrate(starting_baud) == FALSE) + { + close(fd_transport); + return STATUS_FAIL; + } + } + if (pipe(pipefd) == -1) + { + printf("pipe create error"); + return STATUS_FAIL; + } + if(mode != MODE_FM) { + /* Creating read thread which listens for various masks & pkt requests */ + pthread_create( &hci_cmd_thread_hdl, NULL, ftm_readerthread, NULL); + } + return STATUS_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_nwrite + +DESCRIPTION + Platform specific routine to write the data in the argument to the UART/SMD + port intialised. + +PLATFORM SPECIFIC DESCRIPTION + Write the buffer to the tty device and ensure it is completely written + In case of short write report error to the BT FTM layer. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_nwrite(uint8 *buf, int size) +{ + int tx_bytes = 0, nwrite; + int i = 0, buf_size = size; + uint8 loop_back_cmd[6] = {0x1, 0x02, 0x18, 0x01, 0x01}; + /*hci packet is not required to carry the Packet indicator (for UART interfaces) for msm8960 + as it is using share memory interface */ + int hci_uart_pkt_ind = 0; + + if(fd_transport < 0) + return STATUS_NO_RESOURCES; + if ( buf[PIN_CON_CMD_OGF_BIT] == PIN_CON_CMD_OGF && + buf[PIN_CON_CMD_OCF_BIT] == PIN_CON_CMD_OCF && + (size > PIN_CON_CMD_SUBOP_BIT) && + buf[PIN_CON_CMD_SUBOP_BIT] == PIN_CON_CMD_SUB_OP && + (size > PIN_CON_CMD_INTER_BIT) && + buf[PIN_CON_CMD_INTER_BIT] == PIN_CON_INTERFACE_ID) + { + is_slim_bus_test = 1; + printf("\nPinConnectivityTest: Sending loopback command to SOC before initiasing slimbus\n"); + strlcpy(buf, loop_back_cmd, size); + } + do + { + nwrite = write(fd_transport, (buf + hci_uart_pkt_ind + tx_bytes), (size - hci_uart_pkt_ind - tx_bytes)); + + if (nwrite < 0) + { + printf("Error while writing ->\n"); + return STATUS_SHORT_WRITE; + } + if (nwrite == 0) + { + printf("ftm_bt_hci_pfal_nwrite: zero-length write\n"); + return STATUS_SHORT_WRITE; + } + + tx_bytes += nwrite; + size -= nwrite; + } while (tx_bytes < size - hci_uart_pkt_ind); + + if (verbose == 1) + { + printf("[%s] %s: CMD:", get_current_time(), __FUNCTION__); + for (i = 0; i < buf_size; i++) + { + printf(" %02X", buf[i]); + } + printf("\n"); + } + + return STATUS_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_nread + +DESCRIPTION + Platform specific routine to read data from the UART/SMD port intialised into + the buffer passed in argument. + +PLATFORM SPECIFIC DESCRIPTION + Read from the tty device into the buffer and ensure the read request is + completed, in case of short read report error to the BT FTM layer. + + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_hci_pfal_nread(uint8 *buf, int size) +{ + int rx_bytes = 0, nread; + + if(fd_transport < 0) + return STATUS_NO_RESOURCES; + + do + { + nread = read(fd_transport, (buf + rx_bytes), (size - rx_bytes)); + if (nread < 0) + { + printf("Error while reading ->\n"); + return STATUS_SHORT_READ; + } + + rx_bytes += nread; + + } while (rx_bytes < size); + + return STATUS_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_bt_hci_pfal_changebaudrate + +DESCRIPTION + Platform specific routine to intiate a change in baud rate + +PLATFORM SPECIFIC DESCRIPTION + Convert the Baud rate passed to the speed_t type and program the + Baud rate change after ensuring all transmit is drained at the + current baud rate + +DEPENDENCIES + It is expected that the Upper layer will intiate a Flow Off to the + BT SoC, to signal the stop of receive if the baud rate change is + initiated while SoC init is in progress + +RETURN VALUE + RETURN VALUE + TRUE if SUCCESS, else FALSE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_hci_pfal_changebaudrate (uint32 new_baud) +{ + struct termios term; + boolean status = TRUE; + speed_t baud_code; + speed_t actual_baud_code; + + if (tcgetattr(fd_transport, &term) < 0) + { + printf("Can't get port settings\n"); + status = FALSE; + } + else + { + baud_code = convert_baud(new_baud); + (void) cfsetospeed(&term, baud_code); + if (tcsetattr(fd_transport, TCSADRAIN, &term) < 0) /* don't change speed until last write done */ + { + printf("bt_hci_qcomm_pfal_changebaudrate: tcsetattr:\n"); + status = FALSE; + } + /* make sure that we reportedly got the speed we tried to set */ + if (1 < verbose) + { + if (tcgetattr(fd_transport, &term) < 0) + { + printf("bt_hci_qcomm_pfal_changebaudrate: tcgetattr:\n"); + status = FALSE; + } + if (baud_code != (actual_baud_code = cfgetospeed(&term))) + { + printf("bt_hci_qcomm_pfal_changebaudrate: new baud %u FAILED, got 0x%x\n", new_baud, actual_baud_code); + } + else + { + printf("bt_hci_qcomm_pfal_changebaudrate: new baud %u SUCCESS, got 0x%x\n", new_baud, actual_baud_code); + } + } + } + + return status; +} diff --git a/qca/ftm/src/ftm_bt_persist.cpp b/qca/ftm/src/ftm_bt_persist.cpp new file mode 100644 index 000000000..e1e659bf2 --- /dev/null +++ b/qca/ftm/src/ftm_bt_persist.cpp @@ -0,0 +1,278 @@ +/*========================================================================== + + BT persist NV items access source file + +Description + Read/Write APIs for retreiving NV items from persist memory. + +# Copyright (c) 2011-12 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/25/12 jav Added FTM log that will display bt address while testing. +09/27/11 rrr Moved persist related API for c/c++ compatibility, needed + for random BD address to be persistent across target + reboots. +==========================================================================*/ + +#include "ftm_bt_persist.h" +#include + +#ifdef BT_NV_SUPPORT +#include "bt_nv.h" + +/* Semaphore shared by the Event handler and main thread */ +extern sem_t semaphore_cmd_complete; +/*Flag to manage the verbose output */ +extern int verbose; + +/*=========================================================================== +FUNCTION ftm_bt_send_nv_read_cmd + +DESCRIPTION + Helper Routine to process the nv read command + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_send_nv_read_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +) +{ + nv_persist_item_type my_nv_item; + nv_persist_stat_enum_type cmd_result; + boolean result = TRUE; + + if(cmd_len >1) + { + switch(*(cmd_buf+1)) + { + case NV_BD_ADDR_I: + cmd_result = (nv_persist_stat_enum_type)bt_nv_cmd(NV_READ_F, NV_BD_ADDR_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + if (verbose > 0) + { + fprintf (stderr, "nv_cmd_remote failed to get BD_ADDR from NV, code %d\n", cmd_result); + } + /* Send fail response */ + result = FALSE; + } + else + { + /* copy bytes */ + event_buf_nv_read_response[0] = FTM_BT_CMD_NV_READ; + event_buf_nv_read_response[1] = NV_BD_ADDR_I; + event_buf_nv_read_response[7] = my_nv_item.bd_addr[5]; + event_buf_nv_read_response[6] = my_nv_item.bd_addr[4]; + event_buf_nv_read_response[5] = my_nv_item.bd_addr[3]; + event_buf_nv_read_response[4] = my_nv_item.bd_addr[2]; + event_buf_nv_read_response[3] = my_nv_item.bd_addr[1]; + event_buf_nv_read_response[2] = my_nv_item.bd_addr[0]; + /* send BD_ADDR in the response */ + fprintf (stderr, "nv_cmd_remote got NV_BD_ADDR_I from NV: %x:%x:%x:%x:%x:%x\n", + (unsigned int) my_nv_item.bd_addr[5], (unsigned int) my_nv_item.bd_addr[4], + (unsigned int) my_nv_item.bd_addr[3], (unsigned int) my_nv_item.bd_addr[2], + (unsigned int) my_nv_item.bd_addr[1], (unsigned int) my_nv_item.bd_addr[0]); + + ftm_log_send_msg((const uint8 *)event_buf_nv_read_response,nv_read_response_size); + result = TRUE; + } + break; + + case NV_BT_SOC_REFCLOCK_TYPE_I: + cmd_result = (nv_persist_stat_enum_type)bt_nv_cmd(NV_READ_F, NV_BT_SOC_REFCLOCK_TYPE_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + if (verbose > 0) + { + fprintf (stderr, "nv_cmd_remote failed to get BD_ADDR from NV, code %d\n", cmd_result); + } + /* Send fail response */ + result = FALSE; + } + else + { + event_buf_nv_read_response[0] = FTM_BT_CMD_NV_READ; + event_buf_nv_read_response[1] = NV_BT_SOC_REFCLOCK_TYPE_I; + event_buf_nv_read_response[2] = (uint8) my_nv_item.bt_soc_refclock_type ; + event_buf_nv_read_response[7] = 0x0; + event_buf_nv_read_response[6] = 0x0; + event_buf_nv_read_response[5] = 0x0; + event_buf_nv_read_response[4] = 0x0; + event_buf_nv_read_response[3] = 0x0; + fprintf (stderr, "nv_cmd_remote got NV_BT_SOC_REFCLOCK_TYPE_I from NV: 0x%x\n", + (unsigned int) my_nv_item.bt_soc_refclock_type); + ftm_log_send_msg((const uint8 *)event_buf_nv_read_response,nv_read_response_size); + result = TRUE; + } + break; + + case NV_BT_SOC_CLK_SHARING_TYPE_I: + cmd_result = (nv_persist_stat_enum_type)bt_nv_cmd(NV_READ_F, NV_BT_SOC_CLK_SHARING_TYPE_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + if (verbose > 0) + { + fprintf (stderr, "nv_cmd_remote failed to get CLK_SHARING from NV, code %d\n", cmd_result); + } + /* Send fail response */ + result = FALSE; + } + else + { + event_buf_nv_read_response[0] = FTM_BT_CMD_NV_READ; + event_buf_nv_read_response[1] = NV_BT_SOC_CLK_SHARING_TYPE_I; + event_buf_nv_read_response[2] = (uint8) my_nv_item.bt_soc_clk_sharing_type ; + event_buf_nv_read_response[7] = 0x0; + event_buf_nv_read_response[6] = 0x0; + event_buf_nv_read_response[5] = 0x0; + event_buf_nv_read_response[4] = 0x0; + event_buf_nv_read_response[3] = 0x0; + fprintf (stderr, "nv_cmd_remote got NV_BT_SOC_CLK_SHARING_TYPE_I from NV: 0x%x\n", + (unsigned int) my_nv_item.bt_soc_refclock_type); + ftm_log_send_msg((const uint8 *)event_buf_nv_read_response,nv_read_response_size); + result = TRUE; + } + break; + } + if(result == FALSE) + ftm_log_send_msg(event_buf_nv_read_response_fail,nv_read_response_size_fail); + + sem_post(&semaphore_cmd_complete); + return result; + } + return TRUE; +} +/*=========================================================================== +FUNCTION ftm_bt_send_nv_write_cmd + +DESCRIPTION + Helper Routine to process the nv write command + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_send_nv_write_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +) +{ + nv_persist_item_type my_nv_item; + nv_persist_stat_enum_type cmd_result; + boolean result = TRUE; + if(cmd_len >1) + { + switch(*(cmd_buf+1)) + { + case NV_BD_ADDR_I: + memcpy(&my_nv_item.bd_addr, (cmd_buf+2), NV_BD_ADDR_SIZE); + cmd_result = (nv_persist_stat_enum_type)bt_nv_cmd(NV_WRITE_F, NV_BD_ADDR_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + if (verbose > 0) + { + fprintf (stderr, "nv_cmd_remote failed to get BD_ADDR from NV, code %d\n", cmd_result); + } + /* Send fail response */ + result = FALSE; + } + else + { + result = TRUE; + } + break; + + case NV_BT_SOC_REFCLOCK_TYPE_I: + switch (*(cmd_buf+2)) + { + case NV_PS_BT_SOC_REFCLOCK_32MHZ: + case NV_PS_BT_SOC_REFCLOCK_19P2MHZ: + my_nv_item.bt_soc_refclock_type = (nv_ps_bt_soc_refclock_enum_type)(*(cmd_buf+2)) ; + break; + default: + fprintf (stderr, "Invalid Ref Clock option\n"); + result = FALSE; + } + if (result != FALSE) + { + cmd_result= (nv_persist_stat_enum_type)bt_nv_cmd(NV_WRITE_F, NV_BT_SOC_REFCLOCK_TYPE_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + fprintf (stderr, "nv_cmd_remote failed to write SOC_REFCLOCK_TYPE to NV, code %d\n", cmd_result); + result = FALSE; + } + else + { + result = TRUE; + } + break; + } + case NV_BT_SOC_CLK_SHARING_TYPE_I: + switch (*(cmd_buf+2)) + { + case NV_PS_BT_SOC_CLOCK_SHARING_ENABLED: + case NV_PS_BT_SOC_CLOCK_SHARING_DISABLED: + my_nv_item.bt_soc_clk_sharing_type = (nv_ps_bt_soc_clock_sharing_enum_type)(*(cmd_buf+2)) ; + break; + default: + fprintf (stderr, "Invalid Clock Sharing option\n"); + result = FALSE; + } + if (result != FALSE) + { + cmd_result= (nv_persist_stat_enum_type)bt_nv_cmd(NV_WRITE_F, NV_BT_SOC_CLK_SHARING_TYPE_I, &my_nv_item); + if (NV_SUCCESS != cmd_result) + { + fprintf (stderr, "nv_cmd_remote failed to write SOC_CLK_SHARING_TYPE to NV, code %d\n", cmd_result); + result = FALSE; + } + else + { + result = TRUE; + } + break; + } + } + if(result == FALSE) + { + ftm_log_send_msg(event_buf_bt_nv_write_fail,nv_write_response_size); + sem_post(&semaphore_cmd_complete); + } + else + { + ftm_log_send_msg((const uint8 *)event_buf_bt_nv_write_pass,nv_write_response_size); + sem_post(&semaphore_cmd_complete); + } + return result; + } + return TRUE; +} +#endif /* End of BT_NV_SUPPORT */ diff --git a/qca/ftm/src/ftm_bt_persist.h b/qca/ftm/src/ftm_bt_persist.h new file mode 100644 index 000000000..353c12faa --- /dev/null +++ b/qca/ftm/src/ftm_bt_persist.h @@ -0,0 +1,113 @@ +#ifndef _FTM_BT_PERSIST_H_ +#define _FTM_BT_PERSIST_H_ + +/*========================================================================== + + BT persist NV items access source file + +Description + Read/Write APIs for retreiving NV items from persist memory. + +# Copyright (c) 2011 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +09/27/11 rrr Moved persist related API for c/c++ compatibility, needed + for random BD address to be persistent across target + reboots. +==========================================================================*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "ftm_bt_common.h" +#include + + +#ifdef BT_NV_SUPPORT + +#define FTM_BT_CMD_NV_READ 0xB +#define FTM_BT_CMD_NV_WRITE 0xC + +const uint8 nv_read_response_size = 8; +const uint8 nv_read_response_size_fail = 2; +const uint8 nv_write_response_size = 2; + +/* NV Write Responses */ +const uint8 event_buf_bt_nv_write_pass[2] = { FTM_BT_CMD_NV_WRITE, FTM_BT_DRV_NO_ERR}; +const uint8 event_buf_bt_nv_write_fail[2] = { FTM_BT_CMD_NV_WRITE, FTM_BT_NV_WRITE_FAIL}; + +/* NV Read Responses */ +const uint8 event_buf_nv_read_response_fail[8] = +{ + FTM_BT_CMD_NV_READ, FTM_BT_NV_READ_FAIL, 0x0, 0x0,0x0,0x0,0x0,0x0 +}; + +uint8 event_buf_nv_read_response[8]; +#endif /* BT_NV_SUPPORT */ + +/*=========================================================================== +FUNCTION ftm_bt_send_nv_read_cmd + +DESCRIPTION + Helper Routine to process the nv read command + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_send_nv_read_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +); + +/*=========================================================================== +FUNCTION ftm_bt_send_nv_write_cmd + +DESCRIPTION + Helper Routine to process the nv write command + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + FALSE = failure, else TRUE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean ftm_bt_send_nv_write_cmd +( + uint8 * cmd_buf, /* pointer to Cmd */ + uint16 cmd_len /* Cmd length */ +); + +#ifdef __cplusplus +} +#endif + +#endif /* _FTM_BT_PERSIST_H_ */ + diff --git a/qca/ftm/src/ftm_bt_power_hal.h b/qca/ftm/src/ftm_bt_power_hal.h new file mode 100644 index 000000000..2c861b92b --- /dev/null +++ b/qca/ftm/src/ftm_bt_power_hal.h @@ -0,0 +1,76 @@ +/*========================================================================== + + FTM BT POWER HAL Header File + +Description + Wrapper API definitions of the ftm bt power hal component. + +# Copyright (c) 2010 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a header file to include the wrapper API + definitions for BT power control +07/07/10 rakeshk Modified the function name of BT power set HAL routine +===========================================================================*/ +#include "ftm_bt_common.h" +#include "ftm_bt_power_pfal.h" + + +#ifndef __FTM_BT_POWER_HAL_H__ +#define __FTM_BT_POWER_HAL_H__ +/*=========================================================================== +FUNCTION ftm_bt_power_hal_set + +DESCRIPTION + Platform independent wrapper API which sets a BT power from PFAL + layer and returns the status of the PFAL operation. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_power_hal_set(bt_power_state state) +{ + return ftm_bt_power_pfal_set(state); +} +/*=========================================================================== +FtUNCTION ftm_bt_power_hal_check + +DESCRIPTION + + Platform independent wrapper API which gets the BT power from PFAL + layer and returns the current state of the BT HW. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + Current BT power state + +SIDE EFFECTS + None + +===========================================================================*/ +bt_power_state ftm_bt_power_hal_check() +{ + return ftm_bt_power_pfal_check(); +} + +#endif //__FTM_BT_POWER_HAL_H__ diff --git a/qca/ftm/src/ftm_bt_power_pfal.h b/qca/ftm/src/ftm_bt_power_pfal.h new file mode 100644 index 000000000..d81c47fb3 --- /dev/null +++ b/qca/ftm/src/ftm_bt_power_pfal.h @@ -0,0 +1,71 @@ +/*========================================================================== + + FTM BT POWER PFAL Header File + +Description + PFAL API declarations of the ftm bt power pfal component. + +# Copyright (c) 2010 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a header file to hold the PFAL declarations for + BT power programming +07/07/10 rakeshk Modified the function name of BT power set PFAL routine +===========================================================================*/ +#include "ftm_bt_common.h" + +#ifndef __FTM_BT_POWER_PFAL_H__ +#define __FTM_BT_POWER_PFAL_H__ + +/*=========================================================================== +FUNCTION ftm_bt_power_pfal_set + +DESCRIPTION + Platform dependent interface API which sets the BT power + and returns the status of the toggle operation. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_power_pfal_set(bt_power_state state); + +/*=========================================================================== +FUNCTION ftm_bt_power_pfal_check + +DESCRIPTION + + Platform dependent interface API which intiates a BT power read/check + and returns the current state of the BT HW. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + Current BT power state + +SIDE EFFECTS + None + +===========================================================================*/ +bt_power_state ftm_bt_power_pfal_check(); + +#endif + diff --git a/qca/ftm/src/ftm_bt_power_pfal_linux.c b/qca/ftm/src/ftm_bt_power_pfal_linux.c new file mode 100644 index 000000000..aa45bd01a --- /dev/null +++ b/qca/ftm/src/ftm_bt_power_pfal_linux.c @@ -0,0 +1,197 @@ +/*========================================================================== + + FTM Platform specfic BT power File + +Description + Platform specific routines to toggle/read the BT power state + +# Copyright (c) 2010-2011 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a source file to implement platform specific + routines for BT power. +07/07/10 rakeshk Added routine to find the sysfs entry for bluetooth in + runtime +07/07/10 rakeshk Added call to init the rfkill state path in case of first + read +===========================================================================*/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ftm_bt_power_pfal.h" +#include + +/* Bluetooth Rfkill Entry for Android */ +static char *rfkill_state_path = NULL; +/*=========================================================================== +FUNCTION init_rfkill_path + +DESCRIPTION + Opens the sysfs entry for different types of rfkill and finds the one + which matches Bluetooth by iterating through the rfkill entries + and checking for bluetooth + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + TRUE if SUCCESS, else FALSE + +SIDE EFFECTS + None + +===========================================================================*/ +boolean init_rfkill_path() +{ + int fd; + int readsize; + int rfkillid; + char rfkill_path[64]; + char buf[16]; + + for (rfkillid = 0; ; rfkillid++) + { + /* Open the different rfkill type entries and check if type macthes bluetooth */ + snprintf(rfkill_path, sizeof(rfkill_path), "/sys/class/rfkill/rfkill%d/type", rfkillid); + fd = open(rfkill_path, O_RDONLY); + if (fd < 0) + { + printf("open(%s) failed: \n", rfkill_path); + return FALSE; + } + readsize = read(fd, &buf, sizeof(buf)); + close(fd); + + if (memcmp(buf, "bluetooth", 9) == 0) + { + break; + } + } + + asprintf(&rfkill_state_path, "/sys/class/rfkill/rfkill%d/state", rfkillid); + return TRUE; +} + +/*=========================================================================== +FUNCTION ftm_bt_power_pfal_set + +DESCRIPTION + Platform dependent interface API which sets the BT power state + and returns the status of the toggle operation. + +PLATFORM SPECIFIC DESCRIPTION + Opens the rfkill entry for Bleutooth and initiates a write of the value + passed as argument. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + STATUS_SUCCESS if SUCCESS, else other reasons + +SIDE EFFECTS + None + +===========================================================================*/ +request_status ftm_bt_power_pfal_set(bt_power_state state) +{ + int sz; + int fd = -1; + request_status ret = STATUS_FAIL; + const char buffer = state; + if(rfkill_state_path == NULL) + { + if(init_rfkill_path() != TRUE) + goto out; + } + + fd = open(rfkill_state_path, O_WRONLY); + if (fd < 0) + { + ret = STATUS_NO_RESOURCES; + goto out; + } + sz = write(fd, &buffer, 1); + if (sz < 0) + { + goto out; + } + ret = STATUS_SUCCESS; + +out: + if (fd >= 0) + close(fd); + return ret; +} + +/*=========================================================================== +FUNCTION ftm_bt_power_pfal_check + +DESCRIPTION + + Platform dependent interface API which intiates a BT power read/check + and returns the current state of the BT HW. + +PLATFORM SPECIFIC DESCRIPTION + Opens the rfkill entry for Bleutooth and initiates a read on the rfkill + descriptor. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN VALUE + Current BT power state + +SIDE EFFECTS + None + +===========================================================================*/ +bt_power_state ftm_bt_power_pfal_check() +{ + int sz; + bt_power_state state= BT_OFF; + int fd = -1; + char buffer = '0'; + + if(rfkill_state_path == NULL) + { + if(init_rfkill_path() != TRUE) + goto out; + } + fd = open(rfkill_state_path, O_RDONLY); + if (fd < 0) + { + goto out; + } + sz = read(fd, &buffer, 1); + if (sz < 0) + { + goto out; + } + +out: + if (fd >= 0) + close(fd); + state = (bt_power_state)buffer; + return state; +} + diff --git a/qca/ftm/src/ftm_common.h b/qca/ftm/src/ftm_common.h new file mode 100644 index 000000000..48bb478a9 --- /dev/null +++ b/qca/ftm/src/ftm_common.h @@ -0,0 +1,141 @@ +/*========================================================================== + + FTM BT HCI PFAL Header File + +Description + Queue insert/delete routines and data structures + +# Copyright (c) 2010-2011, 2014 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created +11/09/10 rakeshk Added two APIs to perform read/write of BT Top level + I2C registers +===========================================================================*/ + +#if defined(CONFIG_FTM_BT) || defined(CONFIG_FTM_FM) +#include +#include "ftm_bt.h" +#include +#include +/* Semaphore shared by the Event handler and main thread */ +extern sem_t semaphore_cmd_complete; +/* Structure used by the FTM BT/FM component to + * queue the FTM packet contents + */ + +pthread_mutex_t fm_event_lock; +pthread_cond_t fm_event_cond; +extern int fm_passthrough; + +typedef struct cmdQ +{ + int command_id;/*Command id */ + void *data; /* Command data */ + boolean bt_command; /* whether BT or FM command */ + int cmd_len; /* Command length */ + struct cmdQ *next; /* pointer to next CmdQ item */ +}cmdQ; + +/* Callback declaration for BT FTM packet processing */ +void *bt_ftm_diag_dispatch(void *req_pkt, uint16 pkt_len); + +/*=========================================================================== +FUNCTION qinsert_cmd + +DESCRIPTION + Command Queue insert routine. Add the FTM BT packet to the Queue + +DEPENDENCIES + NIL + +RETURN VALUE + RETURNS FALSE without adding queue entry in failure + to allocate a new Queue item + else returns TRUE + +SIDE EFFECTS + increments the number of commands queued + +===========================================================================*/ +boolean qinsert_cmd(ftm_bt_pkt_type *ftm_bt_pkt); +/*=========================================================================== +FUNCTION dequeue_send + +DESCRIPTION + Command Queue delete and calls HCI send routine. Dequeues the HCI data from + the queue and sends it to HCI HAL layer. + +DEPENDENCIES + NIL + +RETURN VALUE + RETURN NIL + +SIDE EFFECTS + decrements the number of command queued + +===========================================================================*/ +void dequeue_send(); + +/*=========================================================================== +FUNCTION i2c_write + +DESCRIPTION + Helper function to construct the I@C request to be sent to the FM I2C + driver + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ +int i2c_write +( +int fd, +unsigned char offset, +const unsigned char* buf, +unsigned char len, +unsigned int slave_addr +); + +/*=========================================================================== +FUNCTION i2c_read + +DESCRIPTION + Helper function to construct the I2C request to read data from the FM I2C + driver + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ +int i2c_read +( +int fd, +unsigned char offset, +const unsigned char* buf, +unsigned char len, +unsigned int slave_addr +); +#endif diff --git a/qca/ftm/src/ftm_dbg.h b/qca/ftm/src/ftm_dbg.h new file mode 100644 index 000000000..592b44aa6 --- /dev/null +++ b/qca/ftm/src/ftm_dbg.h @@ -0,0 +1,34 @@ +/*========================================================================== + + FTM WLAN Source File + +# Copyright (c) 2013-2014 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ +#ifndef _FTM_DBG_H_ +#define _FTM_DBG_H_ + +#define FTM_DBG_ERROR 0x00000001 +#define FTM_DBG_INFO 0x00000002 +#define FTM_DBG_TRACE 0x00000004 + +#define FTM_DBG_DEFAULT (FTM_DBG_ERROR) + +extern unsigned int g_dbg_level; + +#ifdef DEBUG +void current_time(); +#define DPRINTF(_level, _x...)\ + do {\ + if (g_dbg_level & (_level))\ + {\ + fprintf(stderr, _x);\ + }\ + } while (0); + +#else +#define DPRINTF(_level, x...) do { } while (0); +#endif + +#endif /* _FTM_DBG_H_ */ diff --git a/qca/ftm/src/ftm_fm.c b/qca/ftm/src/ftm_fm.c new file mode 100644 index 000000000..f266b10bf --- /dev/null +++ b/qca/ftm/src/ftm_fm.c @@ -0,0 +1,3804 @@ +/*========================================================================== + + FTM FM Source File + +Description + FTM platform independent processing of packet data + +# Copyright (c) 2010-2012 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +08/03/2011 uppalas Adding support for new ftm commands +06/18/10 rakeshk Created a source file to implement routines for FTM + command processing for FM +07/06/10 rakeshk Updated the ftm_fm_dispatch with new commands +01/07/11 rakeshk Removed the check condition in FM bus read/write for + FM On. This is due to the reason that the top level i2c + read/write of the Bahama/Marimba SoC doesnot depend on FM + SoC being intialised. + Added support for new FM FTM APIS +02/09/11 rakeshk Added support for BLER FTM APIs +04/03/11 ananthk Added support for FM FTM Transmit APIs +===========================================================================*/ +#include +#include "event.h" +#include "msg.h" +#include "log.h" + +#include "diag_lsm.h" + +#include "diagpkt.h" +#include "diagcmd.h" +#include "diag.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "ftm_fm_pfal.h" +#include "ftm_common.h" +#include +#include +#include +#include +#include + +#define UNUSED(x) (void)(x) + +#define FTM_DEBUG +const int PROP_SET_SUCC = 0; +const int init_audio_vlm = 50; //set the initial volume to 50 +const char *const fm_audio_disable = "quit"; +const char *const audio_ftm_cmds = "/data/vendor/misc/audio/ftm_commands"; +/* Global union type for FM params */ +fm_cfg_request fmrequestparams; +static uint8 fm_audio_output = -1; +static uint8 enable_mm_fmconfig = 0; +extern int ftm_audio_fd; +volatile fm_power_state fmPowerState = FM_POWER_OFF; +fm_i2c_params common_handle; +extern fm_station_params_available fm_global_params; +/*=========================================================================== +FUNCTION ftm_send_async_msg + +DESCRIPTION + Processes the log buffer sent and writes it to the libdiag for sending the Cmd + response + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ + +void ftm_send_async_msg( + uint8 EvName, + /**< Event ID indicates which event is being returned. */ + + FmEvResultType EvResult, + /**< Event result indicates success or failure. */ + + PACKED void* response, + /**< Event body contains the returned event information. */ + + uint16 length + /**< Event response length. */) +{ + int result = log_status(LOG_FTM_FM_C); + ftm_fm_log_pkt_type* ftm_fm_log_pkt_ptr = NULL; + + if((response == NULL) || (length == 0)) + { + return; + } + + if(result == 1) + { + ftm_fm_log_pkt_ptr = (ftm_fm_log_pkt_type *)log_alloc(LOG_FTM_FM_C,FTM_FM_LOG_HEADER_SIZE + (length-1)); + if(ftm_fm_log_pkt_ptr != NULL) + { + /* FTM LOG FM ID */ + ftm_fm_log_pkt_ptr->EvName = EvName; + ftm_fm_log_pkt_ptr->EvResult = EvResult; + memcpy((void *)ftm_fm_log_pkt_ptr->data,(void *)response,length); + log_commit( ftm_fm_log_pkt_ptr ); + } + } +} + +/*=========================================================================== +FUNCTION convert_cmdstatus_to_ftmstatus + +DESCRIPTION + Helper routine to convert the FM command status to FTM command status + +DEPENDENCIES + NIL + +RETURN VALUE + FTM command status + +SIDE EFFECTS + None + +===========================================================================*/ +ftm_fm_api_result_type convert_cmdstatus_to_ftmstatus(fm_cmd_status_type cmdStatus) +{ + switch(cmdStatus) + { + case FM_CMD_SUCCESS: + return FTM_FM_SUCCESS; + case FM_CMD_NO_RESOURCES: + return FTM_NO_RESOURCES; + case FM_CMD_INVALID_PARAM: + return FTM_INVALID_PARAM; + case FM_CMD_DISALLOWED: + return FTM_FM_DISALLOWED; + case FM_CMD_UNRECOGNIZED_CMD: + return FTM_FM_UNRECOGNIZED_CMD; + case FM_CMD_FAILURE: + return FTM_FAIL; + case FM_CMD_PENDING: + return FTM_FM_PENDING; + default : + return FTM_FAIL; + } +} + +/*=========================================================================== +FUNCTION ftm_fm_copy_request_data + +DESCRIPTION + Helper routine to copy the FTM command data to the global union data type + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void ftm_fm_copy_request_data +( + PACKED void * request , + uint16 length +) +{ + ftm_fm_pkt_type* req_pkt; + int i; + req_pkt = (ftm_fm_pkt_type *) request; + /* Copy any params into our union if they exist. */ + memmove((void*)(&fmrequestparams), + (void*)(&req_pkt->data), + (length)); +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_enable_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + EnableReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Enable Receiver + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_enable_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + if(fmPowerState == FM_TX_ON || fmPowerState == FM_POWER_TRANSITION) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + else if (fmPowerState == FM_RX_ON) + return response; + + ftm_fm_run_mm(); + cmdStatus = EnableFM(&fmrequestparams.cfg_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_enable_transmitter + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + EnableTransmitter, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Enable Transmitter + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_enable_transmitter +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + printf("\n Inside ftm_fm_tx_enable_transmitter() function...\n"); + + response->result = FTM_FM_SUCCESS; + if(fmPowerState == FM_RX_ON || fmPowerState == FM_POWER_TRANSITION) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + else if (fmPowerState == FM_TX_ON) + return response; + + fmrequestparams.cfg_param.is_fm_tx_on = 1; + cmdStatus = EnableFM(&fmrequestparams.cfg_param); + + printf("\nValue of 'cmdStatus' is %d",cmdStatus); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_tx_ps_info + +DESCRIPTION + This routine is used to send the RDS PS Info over the transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Enable Transmitter + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_ps_info +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + printf("\n Inside ftm_fm_tx_ps_info() function...\n"); + + cmdStatus = TransmitPS(&fmrequestparams.tuFmPSParams); + + printf("\nValue of 'cmdStatus' is %d",cmdStatus); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_stop_ps_info + +DESCRIPTION + This routine is used to stop transmitting the RDS PS info + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the stopTransmitPS + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_stop_ps_info +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + printf("\n Inside ftm_fm_tx_stop_ps_info() function...\n"); + + cmdStatus = stopTransmitPS(); + + printf("\nValue of 'cmdStatus' is %d",cmdStatus); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*=========================================================================== */ + + +/*=========================================================================== +FUNCTION ftm_fm_tx_rt_info + +DESCRIPTION + This routine is used to send the RDS RT Info over the transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the RT Start + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_rt_info +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + printf("\n Inside ftm_fm_tx_rt_info() function...\n"); + + cmdStatus = TransmitRT(&fmrequestparams.tuFmRTParams); + + printf("\nValue of 'cmdStatus' is %d",cmdStatus); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== */ +/*=========================================================================== +FUNCTION ftm_fm_tx_stop_rt_info + +DESCRIPTION + This routine is used to stop transmitting the RDS RT info + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the stopTransmitRT + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_stop_rt_info +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + printf("\n Inside ftm_fm_tx_stop_rt_info() function...\n"); + + cmdStatus = stopTransmitRT(); + + printf("\nValue of 'cmdStatus' is %d",cmdStatus); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*=========================================================================== */ + +/*=========================================================================== +FUNCTION ftm_fm_tx_get_ps_features + +DESCRIPTION + This routine is used to get all the supported TX PS features + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the getTxPSFeatures() + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_get_ps_features +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + +#ifdef FTM_DEBUG + printf("\n Inside ftm_fm_tx_get_ps_features function...\n"); +#endif + + cmdStatus = getTxPSFeatures(); + +#ifdef FTM_DEBUG + printf("\nValue of 'cmdStatus' is %d",cmdStatus); +#endif + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + + +/*=========================================================================== + +FUNCTION ftm_fm_disable_audio + +DESCRIPTION + This function is used to disable FTM FM audio. + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_disable_audio +( +void +) +{ + int ret; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( generic_response ) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + printf("enter ftm_fm_disable_audio\n"); + + if (response != NULL) { + response->result = FTM_FM_SUCCESS; + ret = property_set("ftm.fm_stop", "true"); + if (ret != PROP_SET_SUCC) { + response->result = FTM_FAIL; + return response; + } + } else + printf("ftm_fm_disable_audio unable to allocate memory for response packet \n"); + if (ftm_audio_fd > 0) + close(ftm_audio_fd); + printf("Disable audio\n"); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_disable_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + DisableFM, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the DisableFM + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_disable_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + + if(fmPowerState == FM_POWER_OFF) + return response; + + else if(fmPowerState == FM_TX_ON || fmPowerState == FM_POWER_TRANSITION) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + cmdStatus = DisableFM(&fmrequestparams.cfg_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + fmPowerState = FM_POWER_OFF; + ftm_fm_disable_audio(); + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_tx_disable_transmitter + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + DisableFM, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the DisableFM + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_disable_transmitter +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + + if(fmPowerState == FM_POWER_OFF) + return response; + else if (fmPowerState == FM_RX_ON || fmPowerState == FM_POWER_TRANSITION) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } + + cmdStatus = DisableFM(&fmrequestparams.cfg_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + fmPowerState = FM_POWER_OFF; + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_configure_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + ConfigureFM, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the ConfigureFM + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_configure_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + fmrequestparams.cfg_param.is_fm_tx_on = 0; + cmdStatus = ConfigureFM(&fmrequestparams.cfg_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_configure_transmitter + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + ConfigureFM, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the ConfigureFM + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_configure_transmitter +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + fmrequestparams.cfg_param.is_fm_tx_on = 1; + cmdStatus = ConfigureFM(&fmrequestparams.cfg_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_setfrequency_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + SetFrequencyReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Frequency + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setfrequency_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetFrequencyReceiver(fmrequestparams.freq); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_setfrequency_transmitter + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + SetFrequencyTransmitter, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Frequency + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_setfrequency_transmitter +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetFrequencyTransmitter(fmrequestparams.freq); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_setmutemode_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + SetMuteModeReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Mute Mode + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setmutemode_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + mutemode_response * response = (mutemode_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(mutemode_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetMuteModeReceiver(fmrequestparams.mute_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + response->mutemode = fmrequestparams.mute_param; + return response; +} + + +/*=========================================================================== +FUNCTION ftm_fm_set_soft_mute_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + SetMuteModeReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Mute Mode + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_set_soft_mute_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetSoftMuteModeReceiver(fmrequestparams.soft_mute_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_set_antenna + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + setAntenna, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Antenna + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_set_antenna +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = SetAntenna(fmrequestparams.antenna_type); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_peek_riva_word + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmRivaPeekData, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the peek riva word + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_peek_riva_word +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + rivaData_response * response = (rivaData_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(rivaData_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + + cmdStatus = FmRivaPeekData(fmrequestparams.riva_peek_params); + response->start_address = fm_global_params.riva_data_access_params.startaddress; + response->length = fm_global_params.riva_data_access_params.payload_length; + memcpy(&response->data[0], &fm_global_params.riva_data_access_params.data[0], + response->length); + response->sub_opcode = fm_global_params.riva_data_access_params.subOpcode; + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; + +} + +/*=========================================================================== +FUNCTION ftm_fm_poke_riva_word + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmRivaPokeData, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the poke riva word + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_poke_riva_word +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = FmRivaPokeData(fmrequestparams.riva_data_access_params); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; + +} + +/*=========================================================================== +FUNCTION ftm_fm_poke_ssbi_reg + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmSSBIPokeData, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the poke ssbi reg + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_poke_ssbi_reg +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; +#ifdef FTM_DEBUG + printf("ssbi address = %x \n", fmrequestparams.ssbi_access_params.startaddress); + printf("ssbi data = %x \n",fmrequestparams.ssbi_access_params.data); +#endif + + cmdStatus = FmSSBIPokeData(fmrequestparams.ssbi_access_params); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_peek_ssbi_reg + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmSSBIPeekData, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the poke ssbi reg + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_peek_ssbi_reg +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + ssbiPeek_response * response = (ssbiPeek_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(ssbiPeek_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; +#ifdef FTM_DEBUG + printf("SSBI peek address = %x",fmrequestparams.ssbi_access_params.startaddress); +#endif + + cmdStatus = FmSSBIPeekData(fmrequestparams.ssbi_access_params); + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + response->data = fm_global_params.ssbi_peek_data; + return response; + +} + +/*=========================================================================== +FUNCTION ftm_fm_set_get_reset_agc + +DESCRIPTION + This is a synchronous command for Set/Get Gain State and Reset AGC. + +DEPENDENCIES + NIL + +RETURN VALUE + Current AGC Gain State + AGC Gain State one Change ago + AGC Gain State two Changes ago + AGC Gain State three changes ago + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_set_get_reset_agc +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + set_get_reset_agc_response * response = (set_get_reset_agc_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(set_get_reset_agc_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) //&& (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + +#ifdef FM_SOC_TYPE_CHEROKEE + response->result = FTM_FM_SUCCESS; + + printf("AGC req. ucctrl params = %x\n",fmrequestparams.set_get_agc_req_parameters.ucCtrl); + printf("AGC req. params state = %x\n",fmrequestparams.set_get_agc_req_parameters.ucGainState); + + cmdStatus = FmSetGetResetAGC(fmrequestparams.set_get_agc_req_parameters); + + sleep(1); //In order to get the current value which can be delayed. + + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + response->uccurrentgainstate = fm_global_params.set_get_reset_agc_params.ucCurrentGainState; + response->ucgainstatechange1 = fm_global_params.set_get_reset_agc_params.ucGainStateChange1; + response->ucgainstatechange2 = fm_global_params.set_get_reset_agc_params.ucGainStateChange2; + response->ucgainstatechange3 = fm_global_params.set_get_reset_agc_params.ucGainStateChange3; + + printf("response->result = %d\n", response->result); + + if (fmrequestparams.set_get_agc_req_parameters.ucCtrl == 0x00) { + printf("AGC states set successfully\n"); + } else if (fmrequestparams.set_get_agc_req_parameters.ucCtrl == 0x02) { + printf("AGC states reset successfully\n"); + } else { + printf("AGC response: \nCurrentGainState: %x\nGainStateChangeBack1: %x\nGainStateChangeBack2:\ + %x\nGainStateChangeBack3: %x\n", response->uccurrentgainstate, response->ucgainstatechange1, + response->ucgainstatechange2, response->ucgainstatechange3); + } + + return response; + +#else + printf("response->result = %d\n", response->result); + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + +#endif + +} + +/*=========================================================================== +FUNCTION ftm_fm_read_rds_grp_cntrs + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmReadRdsGrpCntrs, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Read RDS Grp + counters FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + + +PACKED void * ftm_fm_read_rds_grp_cntrs +( +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + ReadRDSCntrs_responce * response = (ReadRDSCntrs_responce *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(ReadRDSCntrs_responce) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = FmRDSGrpcntrs(fmrequestparams.rds_grp_counters); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + memcpy(&response->read_rds_cntrs.totalRdsSBlockErrors , + &fm_global_params.rds_group_counters,sizeof(fm_rds_grp_cntrsparams)); + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_read_rds_grp_cntrs_ext + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmReadRdsGrpCntrsExt, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Read RDS Grp + counters FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + + +PACKED void * ftm_fm_read_rds_grp_cntrs_ext +( +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + ReadRDSCntrs_ext_response * response = (ReadRDSCntrs_ext_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(ReadRDSCntrs_ext_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + +#ifdef FM_SOC_TYPE_CHEROKEE + response->result = FTM_FM_SUCCESS; + cmdStatus = FmRDSGrpcntrsExt(fmrequestparams.rds_grp_counters_ext); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + memcpy(&response->read_rds_cntrs_ext.totalRdsSyncLoss , + &fm_global_params.rds_group_counters_extended,sizeof(fm_rds_grpcntrs_extendedparams)); + return response; +#else + printf("response->result = %d\n", response->result); + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; +#endif +} + +/*=========================================================================== +FUNCTION ftm_fm_default_read + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + FmDefaultRead, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Read Default FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_default_read +( +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + default_read_rsp * response = (default_read_rsp *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(default_read_rsp) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if ((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->status= convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } +#ifdef FTM_DEBUG + printf("\n Inside ftm_fm_read_defaults() function...\n"); +#endif + + cmdStatus = FmDefaultRead(fmrequestparams.rd_default); + response->status = convert_cmdstatus_to_ftmstatus(cmdStatus); +#ifdef FTM_DEBUG + printf("\nValue of 'response->status'is %d",response->status); +#endif + if (response->status == FTM_FM_SUCCESS) { + response->data_length = fm_global_params.default_read_data.data_length; + memcpy(&response->data[0], &fm_global_params.default_read_data.data[0], + response->data_length); + } + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_default_write + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + DefaultWrite, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the write Default FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_default_write +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if ((fmPowerState != FM_RX_ON) && (fmPowerState != FM_TX_ON)) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_DISALLOWED); + return response; + } +#ifdef FTM_DEBUG + printf("\n Inside ftm_fm_rx_write_defaults() function...\n"); +#endif + cmdStatus = FmDefaultWrite(&fmrequestparams.wr_default); +#ifdef FTM_DEBUG + printf("\nValue of 'cmdStatus' is %d",cmdStatus); +#endif + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); +#ifdef FTM_DEBUG + printf("\nValue of 'response->result' is %d",response->result); +#endif + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_pwr_lvl_cfg + +DESCRIPTION + + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the tx power level + configuration command + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_pwr_lvl_cfg +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc(DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if (fmPowerState != FM_TX_ON) { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; +#ifdef FTM_DEBUG + printf("FM Tx power configuration to = %x", fmrequestparams.tx_pwr_cfg); +#endif + + cmdStatus = FmTxPwrLvlCfg(fmrequestparams.tx_pwr_cfg); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_tx_tone_generation + +DESCRIPTION + + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the tx tonoe generator + command + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_tx_tone_generation +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_TX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + +#ifdef FTM_DEBUG + printf("FM Tx tone type is setting to = %x",fmrequestparams.tx_tone_param); +#endif + + cmdStatus = FmTxToneGen(fmrequestparams.tx_tone_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_set_hlsi + +DESCRIPTION + + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set HlSi + command + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_set_hlsi +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + +#ifdef FTM_DEBUG + printf("FM Rx HlSi is setting to = %x",fmrequestparams.hlsi); +#endif + + cmdStatus = FmSetHlSi(fmrequestparams.hlsi); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_set_notch_filter + +DESCRIPTION + + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set notch filter + command + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_set_notch_filter +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + +#ifdef FTM_DEBUG + printf("FM Rx Notch filter is setting to = %x",fmrequestparams.notch); +#endif + + cmdStatus = FmSetNotchFilter(fmrequestparams.notch); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + printf("responce->staus= %d",response->result); + return response; +} + + + + +/*=========================================================================== +FUNCTION ftm_fm_rx_setstereomode_receiver + +DESCRIPTION + HAL routine to process the response from the PFAL layer call + SetStereoModeReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set Stereo Mode + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setstereomode_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + stereomode_response * response = (stereomode_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(stereomode_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetStereoModeReceiver(fmrequestparams.stereo_param); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + response->stereomode = fmrequestparams.stereo_param; + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_getstationparameters_receiver + +DESCRIPTION + HAL routine to aggregrate the reponse from the PFAL layer call + GetStationParametersReceiver, also constructs the response packet + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Get Station + parameters FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getstationparameters_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + fm_station_params_available getparamavble; + fm_rx_get_station_parameters_response * response = (fm_rx_get_station_parameters_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(fm_rx_get_station_parameters_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = GetStationParametersReceiver(&getparamavble); + if(cmdStatus == FM_CMD_SUCCESS) + { + response->result = FTM_FM_SUCCESS; + response->stationFreq = getparamavble.current_station_freq; + response->servAvble = getparamavble.service_available; + response->rssi = getparamavble.rssi; + response->stereoProgram = getparamavble.stype; + response->rdsSyncStatus = getparamavble.rds_sync_status; + response->muteMode = getparamavble.mute_status; + } + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_rx_setrdsoptions_receiver + +DESCRIPTION + HAL routine to set the RDS options for the RDS/RDBS subsystem. + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set RDS options + FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setrdsoptions_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetRdsOptionsReceiver(fmrequestparams.rds_options); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_setrdsgroupproc_receiver + +DESCRIPTION + HAL routine to set the RDS group process options for the RDS/RDBS + subsystem. + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the Set RDS group proc + options FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + +PACKED void * ftm_fm_rx_setrdsgroupproc_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetRdsGroupProcReceiver(fmrequestparams.rds_group_options); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_setpowermode_receiver + +DESCRIPTION + HAL routine to set the power mode of FM Receiver Operation + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setpowermode_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetPowerModeReceiver(fmrequestparams.power_mode); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_setsignalthreshold_receiver + +DESCRIPTION + HAL routine to set the signal threshold of FM Receiver + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_setsignalthreshold_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SetSignalThresholdReceiver(fmrequestparams.signal_threshold); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_getsignalthreshold_receiver + +DESCRIPTION + HAL routine to get the signal threshold of FM Receiver + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getsignalthreshold_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + threshold_response * response = (threshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(threshold_response) + ); + uint8 threshold; + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = GetSignalThresholdReceiver(&threshold); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + response->threshold = threshold; + return response; +} + + +/*=========================================================================== +FUNCTION ftm_fm_rx_getrssilimit_receiver + +DESCRIPTION + HAL routine to print the rssi limit of FM Receiver + This command is used for debug purposes + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getrssilimit_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = GetRSSILimits(); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_getpsinfo_receiver + +DESCRIPTION + HAL routine to print the PS info of tuned channel on the Diag + This command is used for debug purposes + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getpsinfo_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + fmrdsps_response * response = (fmrdsps_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(fmrdsps_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + memcpy(response->string, fm_global_params.pgm_services, + fm_global_params.fm_ps_length); + response->length = fm_global_params.fm_ps_length; + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_getrtinfo_receiver + +DESCRIPTION + HAL routine to print the Radio text data of tuned channel on the Diag + This command is used for debug purposes + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getrtinfo_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + fmrdsrt_response * response = (fmrdsrt_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(fmrdsrt_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + memcpy(response->string, fm_global_params.radio_text, + fm_global_params.fm_rt_length); + response->length = fm_global_params.fm_rt_length; + return response; +} + + +/*=========================================================================== +FUNCTION ftm_fm_rx_getafinfo_receiver + +DESCRIPTION + HAL routine to print the Alternate Frequency list of current tuned channel + on the Diag. This command is used for debug purposes + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + None + +===========================================================================*/ +PACKED void * ftm_fm_rx_getafinfo_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = GetAFInfoReceiver(); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_searchstations_receiver + +DESCRIPTION + HAL routine to search for stations from the currently tuned frequency + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + The Result of the search will be output on the Diag through debug messages + +===========================================================================*/ +PACKED void * ftm_fm_rx_searchstations_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SearchStationsReceiver(fmrequestparams.search_stations_options); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_searchrdsstations_receiver + +DESCRIPTION + HAL routine to search for stations from the currently tuned frequency with + a specific program type match + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + The Result of the search will be output on the Diag through debug messages + +===========================================================================*/ +PACKED void * ftm_fm_rx_searchrdsstations_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SearchRdsStationsReceiver(fmrequestparams.search_rds_stations_options); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== +FUNCTION ftm_fm_rx_searchstationslist_receiver + +DESCRIPTION + HAL routine to search for list of stations from the currently tuned frequency with + a specific program type match,signal quality etc + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + The Result of the search will be output on the Diag through debug messages + +===========================================================================*/ +PACKED void * ftm_fm_rx_searchstationslist_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = SearchStationListReceiver(fmrequestparams.search_list_stations_options); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + + +/*=========================================================================== +FUNCTION ftm_fm_rx_cancelsearch_receiver + +DESCRIPTION + HAL routine to cancel the previous search for stations + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + NONE + +===========================================================================*/ +PACKED void * ftm_fm_rx_cancelsearch_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = CancelSearchReceiver(); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*=========================================================================== +FUNCTION ftm_fm_rx_fmbuswrite_receiver + +DESCRIPTION + HAL routine to perform a I2C bus write operation to FM Slave ID + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + NONE + +===========================================================================*/ +PACKED void * ftm_fm_rx_fmbuswrite_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = FmBusWriteReceiver(fmrequestparams.i2c_params); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + + +/*=========================================================================== +FUNCTION ftm_fm_rx_fmbusread_receiver + +DESCRIPTION + HAL routine to perform a I2C bus read operation to FM Slave ID + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the generic response to the FTM FM + packet + +SIDE EFFECTS + NONE + +===========================================================================*/ +PACKED void * ftm_fm_rx_fmbusread_receiver +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + fmbusread_response * response = (fmbusread_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(fmbusread_response) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + response->result = FTM_FM_SUCCESS; + cmdStatus = FmBusReadReceiver(&fmrequestparams.i2c_params); + response->length = fmrequestparams.i2c_params.payload_length; + memcpy(response->data,fmrequestparams.i2c_params.data,fmrequestparams.i2c_params.payload_length); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + + +/*=========================================================================== + +FUNCTION ftm_fm_rx_get_af_threshold + +DESCRIPTION + This function is used to get the current AF threshold of the FM SoC + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_rx_get_af_threshold +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + fmrxsetafthreshold_response * response = (fmrxsetafthreshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetafthreshold_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + /* Populate the registers 0x20-0x2F */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x0F; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + usleep(WAIT_ON_ISR_DELAY); + + /* Read the RDS AF threshold value */ + common_handle.offset = AFTH_OFFSET; + common_handle.payload_length = 0x02; + + /* Clear buffer */ + memset(&common_handle.data[0], + 0, + sizeof(common_handle.data)); + + if (FM_CMD_SUCCESS != FmBusReadReceiver(&common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + printf(" Get AF threshold data [0] = 0x%x data[1] = 0x%x\n",common_handle.data[0],common_handle.data[1]); + +out : + response->afthreshold = (common_handle.data[0] << 8) | (common_handle.data[1]); + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" ftm_fm_get_af_threshold Failure - %d", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" ftm_fm_get_af_threshold - FM_CMD_SUCCESS\n"); + printf(" ftm_fm_get_af_threshold = 0x%x \n", response->afthreshold); + response->result = FTM_FM_SUCCESS; + } + + return response; +} + +/*=========================================================================== + +FUNCTION ftm_fm_rx_get_rssi_check_timer + +DESCRIPTION + This function is used to get the configured periodic timer to monitor + channel quality + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_rx_get_rssi_check_timer +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + + fmrxsetrssichecktimer_response * response = (fmrxsetrssichecktimer_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetrssichecktimer_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + /* Populate the registers 0x20-0x2C */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x16; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + usleep(WAIT_ON_ISR_DELAY); + + /* Read the CHCOND value */ + common_handle.offset = CHCOND_OFFSET; + common_handle.payload_length = 0x01; + + /* Clear buffer */ + memset(&common_handle.data[0], + 0, + sizeof(common_handle.data)); + + if (FM_CMD_SUCCESS != FmBusReadReceiver(&common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + } +out : + response->rssitimer = common_handle.data[0]; + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" ftm_fm_get_rssi_check_timer Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" ftm_fm_get_rssi_check_timer - FM_CMD_SUCCESS\n"); + printf(" ftm_fm_get_rssi_check_timer = 0x%x \n", response->rssitimer); + response->result = FTM_FM_SUCCESS; + } + return response; +} + +/*=========================================================================== + +FUNCTION ftm_fm_rx_get_rds_pi_timer + +DESCRIPTION + This function is used to get the time set to wait for an RDS interrupt before + reporting no RDS data + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_rx_get_rds_pi_timer +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + + fmrxsetrdspitimer_response * response = (fmrxsetrdspitimer_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetrdspitimer_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + /* Populate the registers 0x20-0x2C */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x16; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + usleep(WAIT_ON_ISR_DELAY); + /* Read the RDS timeout value */ + common_handle.offset = RDSTIMEOUT_OFFSET; + common_handle.payload_length = 0x01; + + /* Clear buffer */ + memset(&common_handle.data[0], + 0, + sizeof(common_handle.data)); + + if (FM_CMD_SUCCESS != FmBusReadReceiver(&common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + } + +out : + response->rdspitimer = common_handle.data[0]; + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" ftm_fm_get_rds_pi_timer Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" ftm_fm_get_rds_pi_timer - FM_CMD_SUCCESS\n"); + printf(" ftm_fm_get_rds_pi_timer = 0x%x \n", response->rdspitimer); + response->result = FTM_FM_SUCCESS; + } + return response; +} +/*=========================================================================== + +FUNCTION ftm_fm_rx_set_af_threshold + +DESCRIPTION + This function is used to set the AF threshold of the FM SoC + +DEPENDENCIES + none + +===========================================================================*/ + +PACKED void* ftm_fm_rx_set_af_threshold +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + fmrxsetafthreshold_response * response = (fmrxsetafthreshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetafthreshold_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + /* Populate the registers 0x20-0x2F */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x0F; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + /* Wait for 15 ms to allow the SoC to poulate the registers 0x20-0x2F */ + usleep(WAIT_ON_ISR_DELAY); + + /* Override the RDS AF threshold value */ + common_handle.offset = AFTH_OFFSET; + common_handle.data[0] = ((fmrequestparams.rx_af_threshold >> 8) & 0xFF); + common_handle.data[1] = ((fmrequestparams.rx_af_threshold) & 0xFF); + common_handle.payload_length = 0x02; + + printf(" Set AF threshold data [0] = 0x%x data[1] = 0x%x\n",common_handle.data[0],common_handle.data[1]); + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + /* Apply back the new values */ + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x8F; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + +out : + response->afthreshold = fmrequestparams.rx_af_threshold; + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" FmApi_SetAfThreshold Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" FmApi_SetAfThreshold - fmrequestparams.rx_af_threshold = 0x%x\n", fmrequestparams.rx_af_threshold); + response->result = FTM_FM_SUCCESS; + } + + return response; + +} + +/*=========================================================================== + +FUNCTION ftm_fm_rx_set_rssi_check_timer + +DESCRIPTION + This function is used to set the periodic timer to monitor channel quality + +DEPENDENCIES + none + +===========================================================================*/ + +PACKED void* ftm_fm_rx_set_rssi_check_timer +( +void +) +{ + fm_cmd_status_type fmCmdStatus= FM_CMD_SUCCESS; + + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + + fmrxsetrssichecktimer_response * response = (fmrxsetrssichecktimer_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetrssichecktimer_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + printf(" ftm_fm_set_rssi_check_timer gtsFtmFM.tuFmParams.ucRxRssichecktimer = %d\n",fmrequestparams.rx_rssi_checktimer); + /* Populate the registers 0x20-0x2C */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x16; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + /* Wait for 15 ms to allow the SoC to poulate the registers 0x20-0x2C */ + usleep(WAIT_ON_ISR_DELAY); + + /* Override the CHCOND value */ + common_handle.offset = CHCOND_OFFSET; + common_handle.data[0] = (fmrequestparams.rx_rssi_checktimer & 0xFF); + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + /* Apply back the new values */ + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x96; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + +out : + response->rssitimer = fmrequestparams.rx_rssi_checktimer; + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" FmApi_SetRssiCheckTimer Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" FmApi_SetRssiCheckTimer - fmrequestparams.rx_rssi_checktimer = %d\n", + fmrequestparams.rx_rssi_checktimer); + response->result = FTM_FM_SUCCESS; + } + + return response; +} + +/*=========================================================================== + +FUNCTION ftm_fm_rx_set_rds_pi_timer + +DESCRIPTION + This function is used to set the time to wait for an RDS interrupt before + reporting no RDS data + +DEPENDENCIES + none + +===========================================================================*/ + +PACKED void* ftm_fm_rx_set_rds_pi_timer +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + + /* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */ + + fmrxsetrdspitimer_response * response = (fmrxsetrdspitimer_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( fmrxsetrdspitimer_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + printf(" ftm_fm_set_rds_pi_timer gtsFtmFM.tuFmParams.ucRxRdsPItimer = %d\n",fmrequestparams.rx_rds_pi_timer); + /* Populate the registers 0x20-0x2C */ + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x16; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + /* Wait for 15 ms to allow the SoC to poulate the registers 0x20-0x2C */ + usleep(WAIT_ON_ISR_DELAY); + + /* Override the RDS timeout value */ + common_handle.offset = RDSTIMEOUT_OFFSET; + common_handle.data[0] = (fmrequestparams.rx_rds_pi_timer & 0xFF); + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + + /* Apply back the new values */ + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = 0x96; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + +out : + response->rdspitimer = fmrequestparams.rx_rds_pi_timer; + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" FmApi_SetRdsPiTimer Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" FmApi_SetRdsPiTimer - fmrequestparams.rx_rds_pi_timer = %d\n", + fmrequestparams.rx_rds_pi_timer); + response->result = FTM_FM_SUCCESS; + } + + return response; + +} +/*=========================================================================== + +FUNCTION ftm_fm_rx_get_sinr_samples + +DESCRIPTION + This function is used to get the signal to noise ratio samples + +DEPENDENCIES + none + +===========================================================================*/ + +PACKED void * ftm_fm_rx_get_sinr_samples +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + getsinrsamples_response * response = (getsinrsamples_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(getsinrsamples_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = GetSINRSamples(); + response->sinr_sample = fm_global_params.sinr_samples; + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*=========================================================================== + +FFUNCTION ftm_fm_rx_set_sinr_samples + +DESCRIPTION + This function is used to set the signal to noise ratio samples to take into + accounts for SINR avg calculation + +DEPENDENCIES + none + +===========================================================================*/ + +PACKED void * ftm_fm_rx_set_sinr_samples +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = SetSINRSamples( fmrequestparams.sinr_samples ); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*======================================================================== + FUNCTION ftm_fm_rx_get_sinr_threshold + +DESCRIPTION + This function is used to get the SINR threshold + +DEPENDENCIES + none + +==========================================================================*/ +PACKED void * ftm_fm_rx_get_sinr_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + getsinrthreshold_response * response = (getsinrthreshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(getsinrthreshold_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = GetSINRThreshold(); + response->sinr_threshold = fm_global_params.sinr_threshold; + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*======================================================================== + FUNCTION ftm_fm_rx_set_sinr_threshold + +DESCRIPTION + This function is used to set the SINR threshold + +DEPENDENCIES + none + +==========================================================================*/ +PACKED void * ftm_fm_rx_set_sinr_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = SetSINRThreshold( fmrequestparams.sinr_threshold ); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*======================================================================== + FUNCTION ftm_fm_rx_get_onchannel_threshold + +DESCRIPTION + This function is used to get the on channel threshold + +DEPENDENCIES + none + +==========================================================================*/ +PACKED void * ftm_fm_rx_get_onchannel_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + getonchannelthreshold_response * response = (getonchannelthreshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(getonchannelthreshold_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = GetOnChannelThreshold(); + response->sinr_on_th = fm_global_params.On_channel_threshold; + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*======================================================================== + FUNCTION ftm_fm_rx_set_onchannel_threshold + +DESCRIPTION + This function is used to set the on channel threshold + +DEPENDENCIES + none + +==========================================================================*/ + +PACKED void * ftm_fm_rx_set_onchannel_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = SetOnChannelThreshold( fmrequestparams.On_channel_threshold ); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + +/*======================================================================== + FUNCTION ftm_fm_rx_get_offchannel_threshold + +DESCRIPTION + This function is used to get the Off channel threshold + +DEPENDENCIES + none + +==========================================================================*/ +PACKED void * ftm_fm_rx_get_offchannel_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + getoffchannelthreshold_response * response = (getoffchannelthreshold_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(getoffchannelthreshold_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = GetOffChannelThreshold(); + response->sinr_off_th = fm_global_params.Off_channel_threshold; + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} +/*======================================================================== + FUNCTION ftm_fm_rx_set_offchannel_threshold + +DESCRIPTION + This function is used to set the off channel threshold + +DEPENDENCIES + none + +==========================================================================*/ +PACKED void * ftm_fm_rx_set_offchannel_threshold +( + void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof(generic_response) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + if(fmPowerState != FM_RX_ON) + { + response->result = convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + return response; + } + response->result = FTM_FM_SUCCESS; + cmdStatus = SetOffChannelThreshold( fmrequestparams.Off_channel_threshold ); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + return response; +} + + +/*=========================================================================== + +FUNCTION ftm_fm_rx_get_rds_block_err + +DESCRIPTION + This function is used to get the current RDS block error parameters + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_rx_get_rds_block_err +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + + + rds_err_count_response * response = (rds_err_count_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( rds_err_count_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + common_handle.data[0] = FTM_FM_RDS_COUNT; + common_handle.payload_length = 0x01; + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + usleep(WAIT_ON_ISR_DELAY); + /* Read the RDS block error rate */ + common_handle.offset = RDSERR_OFFSET; + common_handle.payload_length = 0x08; + + /* Clear buffer */ + memset(&common_handle.data[0], + 0, + sizeof(common_handle.data)); + + if (FM_CMD_SUCCESS != FmBusReadReceiver(&common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + } + +out : + response->rdserrcount = ((common_handle.data[0] << 24) | (common_handle.data[1] << 16) + | (common_handle.data[2] << 8) | common_handle.data[3]); + response->numofblocks = BLOCKS_PER_GROUP *((common_handle.data[4] << 24) | (common_handle.data[5] << 16) + | (common_handle.data[6] << 8) | common_handle.data[7]); + + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" ftm_fm_rx_get_rds_block_err Failure - %d\n", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" ftm_fm_rx_get_rds_block_err - FM_CMD_SUCCESS\n"); + printf(" ftm_fm_rx_get_rds_block_err = 0x%x 0x%x\n", (unsigned int)response->rdserrcount,(unsigned int)response->numofblocks); + response->result = FTM_FM_SUCCESS; + } + return response; +} + + +/*=========================================================================== + +FUNCTION ftm_fm_enable_audio + +DESCRIPTION + This function is used to take the audio output mode from QRCT. + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_enable_audio +( +void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( generic_response ) + ); + + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + printf("enter ftm_fm_enable_audio\n"); + + if (response != NULL) { + response->result = FTM_FM_SUCCESS; + mkfifo(audio_ftm_cmds, 0777) ; + + fm_audio_output = fmrequestparams.audio_output; + cmdStatus = ftm_fm_audio(fm_audio_output, init_audio_vlm); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); + } else + printf("ftm_fm_enable_audio unable to allocate memory for response packet \n"); + + return response; +} + + +/*=========================================================================== + +FUNCTION ftm_fm_setting_volume + +DESCRIPTION + This function is used to set the FM volume. + +DEPENDENCIES + none + +===========================================================================*/ +#define MSEC_TO_NSEC (1000 * 1000) + +#ifdef FM_SOC_TYPE_CHEROKEE +#define DISABLE_SLIMBUS_DATA_PORT 0 +#define ENABLE_SLIMBUS_DATA_PORT 1 +#define ENABLE_SLIMBUS_CLOCK_DATA 2 +#endif + +PACKED void* ftm_fm_setting_volume +( +void +) +{ + fm_cmd_status_type cmdStatus = FM_CMD_UNRECOGNIZED_CMD; + struct timespec ts; + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( generic_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + printf("enter ftm_fm_setting_volume\n"); + ts.tv_sec = 0; + ts.tv_nsec = 100 * MSEC_TO_NSEC; + + if (response != NULL) { + response->result = FTM_FM_SUCCESS; + printf("Disabling audio"); + ftm_fm_disable_audio(); +#ifdef FM_SOC_TYPE_CHEROKEE + nanosleep(&ts, NULL); + ftm_fm_enable_slimbus(DISABLE_SLIMBUS_DATA_PORT); +#endif + + printf("audio_output = %d", fmrequestparams.audio_output); + printf("audio_vlm = %d",fmrequestparams.audio_vlm); + cmdStatus = ftm_fm_audio(fm_audio_output, fmrequestparams.audio_vlm); + response->result = convert_cmdstatus_to_ftmstatus(cmdStatus); +#ifdef FM_SOC_TYPE_CHEROKEE + sleep(1); + ftm_fm_enable_slimbus(ENABLE_SLIMBUS_DATA_PORT); +#endif + } else + printf("ftm_fm_setting_volume NULL repsonse packet\n"); + + return response; +} +/*=========================================================================== + +FUNCTION ftm_fm_rx_reset_rds_err_count + +DESCRIPTION + This function is used to reseet the current RDS block error parameters + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_rx_reset_rds_err_count +( +void +) +{ + fm_cmd_status_type fmCmdStatus = FM_CMD_SUCCESS; + /* Default data to be written for Marimba versions + * not applicable for Bahama versions + */ + uint8 uData[] = { 0xD0 ,0x03 ,0xCE, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + + generic_response * response = (generic_response *) + diagpkt_subsys_alloc( DIAG_SUBSYS_FTM + , FTM_FM_CMD_CODE + , sizeof( generic_response ) + ); + if(response == NULL) + { + printf("%s Failed to allocate resource",__func__); + return (void *)convert_cmdstatus_to_ftmstatus(FM_CMD_NO_RESOURCES); + } + + /* if chip version not determined we can't reset */ + if(chipVersion == 0) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + if((chipVersion == FMQSOCCOM_FM6500_WCN2243_10_VERSION) || + (chipVersion == FMQSOCCOM_FM6500_WCN2243_20_VERSION)) + { + uint8 uData_bahama[] = {0xD0, 0x00, 0xE6, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}; + printf("Chip Id is 0x%x\n",chipVersion); + /* The Reset data for Bahama is different from + * Marimba the data is dynamically selected based + * on ChipVersion + */ + memcpy(uData,uData_bahama,sizeof(uData)); + } + common_handle.slaveaddress = FM_SLAVE_ADDR; + common_handle.offset = XFR_CTRL_OFFSET; + /* Copy the data to i2c request buffer */ + memcpy(&common_handle.data[0], + uData, + sizeof(uData)); + common_handle.payload_length = sizeof(uData); + + if (FM_CMD_SUCCESS != FmBusWriteReceiver(common_handle)) + { + fmCmdStatus = FM_CMD_FAILURE; + goto out; + } + + usleep(WAIT_ON_ISR_DELAY); + +out: + if(FM_CMD_SUCCESS != fmCmdStatus) + { + printf(" ftm_fm_reset_rds_err_count Failure - %d", fmCmdStatus); + response->result = FTM_FAIL; + } + else + { + printf(" ftm_fm_reset_rds_err_count - FM_CMD_SUCCESS"); + response->result = FTM_FM_SUCCESS; + } + return(response); + +} + + +/*=========================================================================== +FUNCTION ftm_fm_dispatch + +DESCRIPTION + Dispatch routine for the various FM Rx/Tx commands. Copies the data into + a global union data structure before calling the processing routine + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ +void * ftm_fm_dispatch(ftm_fm_pkt_type *ftm_fm_pkt, uint16 length ) +{ + ftm_fm_sub_cmd_type ftm_fm_sub_cmd; + + UNUSED(length); + ftm_fm_sub_cmd = (ftm_fm_sub_cmd_type)ftm_fm_pkt->cmd_id; +#ifdef FTM_DEBUG + printf("ftm_fm_pkt->cmd_id = %d\n cmd_data_len = %d\n", ftm_fm_pkt->cmd_id,ftm_fm_pkt->cmd_data_len); +#endif + ftm_fm_copy_request_data(ftm_fm_pkt,ftm_fm_pkt->cmd_data_len); + switch(ftm_fm_sub_cmd) + { + if(!fm_passthrough) + { + case FTM_FM_RX_ENABLE_RECEIVER: + return(ftm_fm_rx_enable_receiver()); + case FTM_FM_RX_DISABLE_RECEIVER: + return(ftm_fm_rx_disable_receiver()); + case FTM_FM_RX_CONFIGURE_RECEIVER: + return(ftm_fm_rx_configure_receiver()); + case FTM_FM_RX_SET_STATION: + return(ftm_fm_rx_setfrequency_receiver()); + case FTM_FM_RX_SET_MUTE_MODE: + return(ftm_fm_rx_setmutemode_receiver()); + case FTM_FM_RX_SET_STEREO_MODE: + return(ftm_fm_rx_setstereomode_receiver()); + case FTM_FM_RX_GET_STATION_PARAMETERS: + return(ftm_fm_rx_getstationparameters_receiver()); + case FTM_FM_RX_RDS_GROUP_OPTIONS : + return (ftm_fm_rx_setrdsoptions_receiver()); + case FTM_FM_RX_SET_POWER_MODE : + return (ftm_fm_rx_setpowermode_receiver()); + case FTM_FM_RX_SET_SIGNAL_THRESHOLD : + return (ftm_fm_rx_setsignalthreshold_receiver()); + case FTM_FM_RX_GET_RSSI_LIMIT : + return (ftm_fm_rx_getrssilimit_receiver()); + case FTM_FM_RX_SEARCH_STATIONS : + return (ftm_fm_rx_searchstations_receiver()); + case FTM_FM_RX_SEARCH_RDS_STATIONS : + return (ftm_fm_rx_searchrdsstations_receiver()); + case FTM_FM_RX_SEARCH_STATIONS_LIST : + return (ftm_fm_rx_searchstationslist_receiver()); + case FTM_FM_RX_CANCEL_SEARCH: + return (ftm_fm_rx_cancelsearch_receiver()); + case FTM_FM_RX_GET_PS_INFO : + return (ftm_fm_rx_getpsinfo_receiver()); + case FTM_FM_RX_GET_RT_INFO : + return (ftm_fm_rx_getrtinfo_receiver()); + case FTM_FM_RX_GET_AF_INFO : + return (ftm_fm_rx_getafinfo_receiver()); + case FTM_FM_BUS_WRITE: + return (ftm_fm_rx_fmbuswrite_receiver()); + case FTM_FM_BUS_READ: + return (ftm_fm_rx_fmbusread_receiver()); + case FTM_FM_RX_RDS_GROUP_PROC_OPTIONS: + return (ftm_fm_rx_setrdsgroupproc_receiver()); + case FTM_FM_RX_GET_AF_THRESHOLD: + return(ftm_fm_rx_get_af_threshold()); + case FTM_FM_RX_GET_RSSI_CHECK_TIMER: + return(ftm_fm_rx_get_rssi_check_timer()); + case FTM_FM_RX_GET_RDS_PI_TIMER: + return(ftm_fm_rx_get_rds_pi_timer()); + case FTM_FM_RX_SET_AF_THRESHOLD: + return(ftm_fm_rx_set_af_threshold()); + case FTM_FM_RX_SET_RSSI_CHECK_TIMER: + return(ftm_fm_rx_set_rssi_check_timer()); + case FTM_FM_RX_SET_RDS_PI_TIMER: + return(ftm_fm_rx_set_rds_pi_timer()); + case FTM_FM_RX_GET_SIGNAL_THRESHOLD : + return (ftm_fm_rx_getsignalthreshold_receiver()); + case FTM_FM_RX_GET_RDS_ERR_COUNT : + return (ftm_fm_rx_get_rds_block_err()); + case FTM_FM_RX_RESET_RDS_ERR_COUNT : + return (ftm_fm_rx_reset_rds_err_count()); + case FTM_FM_TX_ENABLE_TRANSMITTER : + return(ftm_fm_tx_enable_transmitter()); + case FTM_FM_TX_CONFIGURE_TRANSMITTER: + return(ftm_fm_tx_configure_transmitter()); + case FTM_FM_TX_DISABLE_TRANSMITTER: + return(ftm_fm_tx_disable_transmitter()); + case FTM_FM_TX_SET_STATION: + return(ftm_fm_tx_setfrequency_transmitter()); + case FTM_FM_TX_TX_PS_INFO : + return ftm_fm_tx_ps_info(); + case FTM_FM_TX_STOP_PS_INFO_TX : + return ftm_fm_tx_stop_ps_info(); + case FTM_FM_TX_TX_RT_INFO : + return ftm_fm_tx_rt_info(); + case FTM_FM_TX_STOP_RT_INFO_TX : + return ftm_fm_tx_stop_rt_info(); + case FTM_FM_TX_GET_PS_FEATURES : + return ftm_fm_tx_get_ps_features(); + case FTM_FM_SET_SOFT_MUTE: + return ftm_fm_set_soft_mute_receiver(); + case FTM_FM_SET_ANTENNA: + return ftm_fm_set_antenna(); + case FTM_FM_POKE_RIVA_WORD: + return ftm_fm_poke_riva_word(); + case FTM_FM_PEEK_RIVA_WORD: + return ftm_fm_peek_riva_word(); + case FTM_FM_PEEK_SSBI: + return ftm_fm_peek_ssbi_reg(); + case FTM_FM_POKE_SSBI: + return ftm_fm_poke_ssbi_reg(); + case FTM_FM_SET_TONE_GENERATION: + return (ftm_fm_tx_tone_generation()); + case FTM_FM_READ_RDS_GRP_CNTRS: + return (ftm_fm_read_rds_grp_cntrs()); + case FTM_FM_READ_RDS_GRP_CNTRS_EXT: + return (ftm_fm_read_rds_grp_cntrs_ext()); + case FTM_FM_SET_HLSI: + return (ftm_fm_set_hlsi()); + case FTM_FM_RX_GET_SINR_SAMPLES: + return (ftm_fm_rx_get_sinr_samples()); + case FTM_FM_RX_SET_SINR_SAMPLES: + return (ftm_fm_rx_set_sinr_samples()); + case FTM_FM_RX_GET_SINR_THRESHOLD: + return (ftm_fm_rx_get_sinr_threshold()); + case FTM_FM_RX_SET_SINR_THRESHOLD: + return (ftm_fm_rx_set_sinr_threshold()); + case FTM_FM_RX_GET_ONCHANNEL_TH: + return (ftm_fm_rx_get_onchannel_threshold()); + case FTM_FM_RX_SET_ONCHANNEL_TH: + return (ftm_fm_rx_set_onchannel_threshold()); + case FTM_FM_RX_GET_OFFCHANNEL_TH: + return (ftm_fm_rx_get_offchannel_threshold()); + case FTM_FM_RX_SET_OFFCHANNEL_TH: + return (ftm_fm_rx_set_offchannel_threshold()); + case FTM_FM_SET_NOTCH_FILTER: + return (ftm_fm_set_notch_filter()); + case FTM_FM_RX_GET_DEFAULTS: + return (ftm_fm_default_read()); + case FTM_FM_RX_SET_DEFAULTS: + return (ftm_fm_default_write()); + case FTM_FM_TX_PWR_LVL_CFG: + return ftm_fm_tx_pwr_lvl_cfg(); + case FTM_FM_SET_GET_RESET_AGC: + return ftm_fm_set_get_reset_agc(); + } + case FTM_FM_ENABLE_AUDIO: + return ftm_fm_enable_audio(); + case FTM_FM_DISABLE_AUDIO: + return ftm_fm_disable_audio(); + case FTM_FM_VOLUME_SETTING: + return ftm_fm_setting_volume(); + default: + if(fm_passthrough) { + if(!enable_mm_fmconfig) + { + ftm_fm_run_mm(); + enable_mm_fmconfig = 1; + } + return bt_ftm_diag_dispatch(ftm_fm_pkt, length); + } + return NULL; + } +} diff --git a/qca/ftm/src/ftm_fm_common.h b/qca/ftm/src/ftm_fm_common.h new file mode 100644 index 000000000..77025f004 --- /dev/null +++ b/qca/ftm/src/ftm_fm_common.h @@ -0,0 +1,993 @@ +/*========================================================================== + + FTM FM Common Header File + +Description + Global Data declarations of the ftm fm component. + +# Copyright (c) 2010-2012, 2014 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +08/03/2011 uppalas Adding support for new ftm commands +06/18/10 rakeshk Created a header file to hold the definitons for ftm fm + task +07/06/10 rakeshk Clean roomed the data structures and defined data + structures to be passed to the PFAL layers +01/11/11 rakeshk Added support for new FTM APIS +02/09/11 rakeshk Added support for BLER FTM APIs +04/03/11 ananthk Added support for FM FTM Transmit APIs +===========================================================================*/ +#ifdef CONFIG_FTM_FM + +#include "diagpkt.h" +#include "log.h" +#include + +#define FTM_FM_LOG_PKT_ID 65 +#define FTM_FM_CMD_CODE 28 +#define LOG_FTM_FM_C ((uint16) 0x14CC) +#define FEATURE_FTM_FM_DEBUG +#define DEFAULT_DATA_SIZE 249 + +/* FM6500 A0 chip version. + **/ +#define FM6500_A0_VERSION (0x01010013) +/** + * * FM6500 2.0 chip version. + **/ +#define FMQSOCCOM_FM6500_20_VERSION (0x01010010) +/** + * * FM6500 2.1 chip version. + **/ +#define FMQSOCCOM_FM6500_21_VERSION (0x02010204) +/** + * WCN 2243 1.0's FM chip version. + */ +#define FMQSOCCOM_FM6500_WCN2243_10_VERSION (0x0302010A) +/** + * WCN 2243 2.0's FM chip version. + */ +#define FMQSOCCOM_FM6500_WCN2243_20_VERSION (0x04020205) + +extern int chipVersion; + +/* RDS Group processing parameters */ +#define FM_RX_RDS_GRP_RT_EBL 1 +#define FM_RX_RDS_GRP_PS_EBL 2 +#define FM_RX_RDS_GRP_AF_EBL 4 +#ifdef FM_SOC_TYPE_CHEROKEE +#define FM_RX_RDS_GRP_PS_SIMPLE_EBL 8 +#define FM_RX_RDS_GRP_ECC_EBL 32 +#define FM_RX_RDS_GRP_PTYN_EBL 64 +#define FM_RX_RDS_GRP_RT_PLUS_EBL 128 +#else +#define FM_RX_RDS_GRP_PS_SIMPLE_EBL 16 +#endif + + +/* lower and upper band limits of regions */ +#define REGION_US_EU_BAND_LOW 87500 +#define REGION_US_EU_BAND_HIGH 107900 +#define REGION_JAPAN_STANDARD_BAND_LOW 76000 +#define REGION_JAPAN_STANDARD_BAND_HIGH 90000 +#define REGION_JAPAN_WIDE_BAND_LOW 90000 +#define REGION_JAPAN_WIDE_BAND_HIGH 108000 +#define V4L2_CID_PRIVATE_BASE 0x08000000 +#define MAX_RDS_PS_LENGTH 108 +#define MAX_RDS_RT_LENGTH 64 +#define V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS_EXT 0x08000042 + +typedef enum { +V4L2_CID_PRIVATE_IRIS_HLSI = (V4L2_CID_PRIVATE_BASE + 0x1d), +V4L2_CID_PRIVATE_IRIS_SOFT_MUTE, +V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR, +V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN, +V4L2_CID_PRIVATE_IRIS_RIVA_PEEK, +V4L2_CID_PRIVATE_IRIS_RIVA_POKE, +V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR, +V4L2_CID_PRIVATE_IRIS_SSBI_PEEK, +V4L2_CID_PRIVATE_IRIS_SSBI_POKE, +V4L2_CID_PRIVATE_IRIS_TX_TONE, +V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS, +V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER, +V4L2_CID_PRIVATE_IRIS_AGC_CTRL = 0x08000043, +V4L2_CID_PRIVATE_IRIS_AGC_STATE, +V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,//using private CIDs under userclass +V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT, +}v4l2_cid_private_iris_t_copy; +typedef enum +{ + /* Total no. of PS names that can be transmitted : 12 + Width of each transmitted PS name is : 8 + Total no. of PS characters that can be transmitted : (12*8 = 96) + */ + MAX_TX_PS_LEN = 96, + MAX_TX_PS_RPT_CNT = 15, +}FmTxPSFeatures; + +/* FTM FM command IDs */ +typedef enum +{ +#ifdef FEATURE_FTM_FM_DEBUG + FTM_FM_RX_SET_POWER_MODE = 13, + FTM_FM_RX_SET_SIGNAL_THRESHOLD = 14, + FTM_FM_RX_GET_RSSI_LIMIT = 16, + FTM_FM_RX_GET_PS_INFO = 17, + FTM_FM_RX_GET_RT_INFO = 18, + FTM_FM_RX_GET_AF_INFO = 19, + FTM_FM_RX_SEARCH_STATIONS = 20, + FTM_FM_RX_SEARCH_RDS_STATIONS = 21, + FTM_FM_RX_SEARCH_STATIONS_LIST = 22, + FTM_FM_RX_CANCEL_SEARCH = 23, + FTM_FM_RX_RDS_GROUP_PROC_OPTIONS = 25, + FTM_FM_RX_RDS_PI_MATCH_OPTIONS = 26, + FTM_FM_TX_GET_PS_FEATURES = 36, + FTM_FM_TX_TX_PS_INFO = 38, + FTM_FM_TX_STOP_PS_INFO_TX = 39, + FTM_FM_TX_TX_RT_INFO = 40, + FTM_FM_TX_STOP_RT_INFO_TX = 41, + FTM_FM_RX_GET_SIGNAL_THRESHOLD = 46, + FTM_FM_FMWAN_REG_RD = 51, + FTM_FM_RX_GET_DEFAULTS = 62, + FTM_FM_RX_SET_DEFAULTS = 63, + FTM_FM_RX_GET_SINR_SAMPLES = 64, + FTM_FM_RX_SET_SINR_SAMPLES = 65, + FTM_FM_RX_GET_SINR_THRESHOLD = 66, + FTM_FM_RX_SET_SINR_THRESHOLD = 67, + FTM_FM_RX_GET_ONCHANNEL_TH = 68, + FTM_FM_RX_SET_ONCHANNEL_TH = 69, + FTM_FM_RX_GET_OFFCHANNEL_TH = 70, + FTM_FM_RX_SET_OFFCHANNEL_TH = 71, + FTM_FM_TX_PWR_LVL_CFG = 72, +#endif /* FEATURE_FTM_FM_DEBUG */ + + FTM_FM_RX_ENABLE_RECEIVER = 7, + FTM_FM_RX_DISABLE_RECEIVER = 8, + FTM_FM_RX_CONFIGURE_RECEIVER = 9, + FTM_FM_RX_SET_MUTE_MODE = 10, + FTM_FM_RX_SET_STEREO_MODE = 11, + FTM_FM_RX_SET_STATION = 12, + FTM_FM_RX_GET_STATION_PARAMETERS = 15, + FTM_FM_RX_RDS_GROUP_OPTIONS = 24, + FTM_FM_TX_ENABLE_TRANSMITTER = 33, + FTM_FM_TX_DISABLE_TRANSMITTER = 34, + FTM_FM_TX_CONFIGURE_TRANSMITTER = 35, + FTM_FM_TX_SET_STATION = 37, + FTM_FM_TX_TX_RDS_GROUPS = 42, + FTM_FM_TX_TX_CONT_RDS_GROUPS = 43, + FTM_FM_TX_TX_RDS_CTRL = 44, + FTM_FM_TX_GET_RDS_GROUP_BUF_SIZE = 45, + FTM_FM_BUS_WRITE = 47, + FTM_FM_BUS_READ = 48, + FTM_FM_NOTIFY_WAN = 49, + FTM_FM_NOTIFY_FM = 50, + FTM_FM_ROUTE_AUDIO = 52, + FTM_FM_RX_SET_AF_THRESHOLD = 53, + FTM_FM_RX_SET_RSSI_CHECK_TIMER = 54, + FTM_FM_RX_SET_RDS_PI_TIMER = 55, + FTM_FM_RX_GET_AF_THRESHOLD = 56, + FTM_FM_RX_GET_RSSI_CHECK_TIMER = 57, + FTM_FM_RX_GET_RDS_PI_TIMER = 58, + FTM_FM_RX_GET_RDS_ERR_COUNT = 59, + FTM_FM_RX_RESET_RDS_ERR_COUNT = 60, + FTM_FM_TX_SEARCH_STATIONS = 61, + FTM_FM_SET_HLSI = 100, + FTM_FM_SET_SOFT_MUTE = 101, + FTM_FM_SET_ANTENNA = 102, + FTM_FM_SET_NOTCH_FILTER = 103, + FTM_FM_READ_RDS_GRP_CNTRS = 104, + FTM_FM_SET_TONE_GENERATION = 105, + FTM_FM_PEEK_SSBI = 106, + FTM_FM_POKE_SSBI = 107, + FTM_FM_PEEK_RIVA_WORD = 108, + FTM_FM_POKE_RIVA_WORD = 109, + FTM_FM_ENABLE_AUDIO = 111, + FTM_FM_DISABLE_AUDIO = 112, + FTM_FM_VOLUME_SETTING = 113, + FTM_FM_READ_RDS_GRP_CNTRS_EXT = 114, + FTM_FM_SET_GET_RESET_AGC = 115, + FTM_FM_MAX +} ftm_fm_sub_cmd_type; + +#define XFR_CTRL_OFFSET 0x1F +/* Wait time for ensuring XFR is generated */ +#define WAIT_ON_ISR_DELAY 15000 //15 ms +#define AFTH_OFFSET 0x2E +#define CHCOND_OFFSET 0x22 +#define RDSTIMEOUT_OFFSET 0x25 +#define FM_SLAVE_ADDR 0x2A +#define RDSERR_OFFSET 0x24 +#define RDSRESET_OFFSET 0x20 +#define BLOCKS_PER_GROUP 0x04 +#define FTM_FM_RDS_COUNT 0x11 + + +#define MAX_RIVA_DATA_LEN 245 +#define MAX_RIVA_PEEK_RSP_SIZE 251 +#define SSBI_PEEK_DATA_SIZE 1 + +#define IRIS_BUF_PEEK 6 +#define IRIS_BUF_SSBI_PEEK IRIS_BUF_PEEK+1 +#define IRIS_BUF_RDS_CNTRS IRIS_BUF_SSBI_PEEK+1 +#define IRIS_BUF_RD_DEFAULT IRIS_BUF_RDS_CNTRS+1 +#ifdef FM_SOC_TYPE_CHEROKEE +#define RDS_GRP_CNTRS_SIZE 48 +#else +#define RDS_GRP_CNTRS_SIZE 36 +#endif +/* Generic result, used for any command that only returns an error code */ +typedef enum +{ + FTM_FM_SUCCESS, + FTM_FAIL, + FTM_FILE_DOES_NOT_EXIST, + FTM_MMC_ERROR, + FTM_FM_UNRECOGNIZED_CMD, + FTM_NO_RESOURCES, + FTM_FM_PENDING, + FTM_INVALID_PARAM, + FTM_FM_DISALLOWED, + FTM_TEST_NOT_IMPLEMENTED, + FTM_CUST_HW_ID_UNKNOWN, + FTM_FM_BUS_WRITE_ERROR, + FTM_FM_BUS_READ_ERROR, + FTM_FM_CLIENT_MAX, + +} ftm_fm_api_result_type; + +/* FM power state enum */ +typedef enum +{ + FM_POWER_OFF, + FM_POWER_TRANSITION, + FM_RX_ON, + FM_TX_ON +}fm_power_state; + +/* FM command status enum */ +typedef enum +{ + FM_CMD_SUCCESS, + FM_CMD_PENDING, + FM_CMD_NO_RESOURCES, + FM_CMD_INVALID_PARAM, + FM_CMD_DISALLOWED, + FM_CMD_UNRECOGNIZED_CMD, + FM_CMD_FAILURE +}fm_cmd_status_type; + +/** +* FM event result. +*/ +typedef enum +{ + FM_EV_SUCCESS = 0, + /**< Event indicates success. */ + + FM_EV_FAILURE = 1, + /**< Event is a response to a command that failed */ + + FM_EV_CMD_DISALLOWED = 2, + /**< Event is a response to a command that was disallowed. */ + + FM_EV_CMD_INVALID_PARAM = 3 + /**< Event is a response to a command that contained an invalid parameter. */ + +} FmEvResultType; + +/** +* FM Receiver event names. +*/ +typedef enum +{ + /* ----------------------------------------------- + 1 -> FM Receiver initialization events + ----------------------------------------------- */ + + FM_RX_EV_ENABLE_RECEIVER = 0, + + FM_RX_EV_DISABLE_RECEIVER, + + FM_RX_EV_CFG_RECEIVER, + + /* ----------------------------------------------- + 2 -> FM receiver control events + ----------------------------------------------- */ + + FM_RX_EV_MUTE_MODE_SET, + + FM_RX_EV_STEREO_MODE_SET, + + FM_RX_EV_RADIO_STATION_SET, + + FM_RX_EV_PWR_MODE_SET, + + FM_RX_EV_SET_SIGNAL_THRESHOLD, + + /* ----------------------------------------------- + 3 -> FM receiver status events + ----------------------------------------------- */ + + FM_RX_EV_RADIO_TUNE_STATUS, + + FM_RX_EV_STATION_PARAMETERS, + + FM_RX_EV_RDS_LOCK_STATUS, + + FM_RX_EV_STEREO_STATUS, + + FM_RX_EV_SERVICE_AVAILABLE, + + FM_RX_EV_GET_SIGNAL_THRESHOLD, + + /* ----------------------------------------------- + 4 -> FM search status events + ----------------------------------------------- */ + + FM_RX_EV_SEARCH_IN_PROGRESS, + + FM_RX_EV_SEARCH_RDS_IN_PROGRESS, + + FM_RX_EV_SEARCH_LIST_IN_PROGRESS, + + FM_RX_EV_SEARCH_COMPLETE, + + FM_RX_EV_SEARCH_RDS_COMPLETE, + + FM_RX_EV_SEARCH_LIST_COMPLETE, + + FM_RX_EV_SEARCH_CANCELLED, + + /* ----------------------------------------------- + 5 -> FM RDS status events + ----------------------------------------------- */ + + FM_RX_EV_RDS_GROUP_DATA, + + FM_RX_EV_RDS_PS_INFO, + + FM_RX_EV_RDS_RT_INFO, + + FM_RX_EV_RDS_AF_INFO, + + FM_RX_EV_RDS_PI_MATCH_AVAILABLE, + + /* ----------------------------------------------- + 6 -> FM RDS control events + ----------------------------------------------- */ + + FM_RX_EV_RDS_GROUP_OPTIONS_SET, + + FM_RX_EV_RDS_PROC_REG_DONE, + + FM_RX_EV_RDS_PI_MATCH_REG_DONE, + + FM_RX_EV_MAX_EVENT + +} FmRxEventType; + +typedef enum radio_band_type +{ + FM_US_EU = 0x0, + FM_JAPAN_STANDARD = 0x1, + FM_JAPAN_WIDE = 0x2, + FM_USER_DEFINED = 0x4 +}radio_band_type; + +typedef enum emphasis_type +{ + FM_RX_EMP75 = 0x0, + FM_RX_EMP50 = 0x1 +}emphasis_type; + +typedef enum channel_space_type +{ + FM_RX_SPACE_200KHZ = 0x0, + FM_RX_SPACE_100KHZ = 0x1, + FM_RX_SPACE_50KHZ = 0x2 +}channel_space_type; + +typedef enum rds_system_type +{ + FM_RX_RDBS_SYSTEM = 0x0, + FM_RX_RDS_SYSTEM = 0x1, + FM_RX_NO_RDS_SYSTEM = 0x2 +}rds_sytem_type; + +typedef struct band_limit_freq +{ + uint32 lower_limit; + uint32 upper_limit; +}band_limit_freq; + + +typedef enum rds_sync_type +{ + FM_RDS_NOT_SYNCED = 0x0, + FM_RDS_SYNCED = 0x1 +}rds_sync_type; + +typedef enum stereo_type +{ + FM_RX_MONO = 0x0, + FM_RX_STEREO = 0x1 +}stereo_type; + +typedef enum fm_service_available +{ + FM_SERVICE_NOT_AVAILABLE = 0x0, + FM_SERVICE_AVAILABLE = 0x1 +}fm_service_available; + +typedef enum mute_type +{ + FM_RX_NO_MUTE = 0x00, + FM_RX_MUTE_RIGHT = 0x01, + FM_RX_MUTE_LEFT = 0x02, + FM_RX_MUTE_BOTH = 0x03 +}mute_type; + +typedef enum antenna_type +{ + WIRED_HS, + PWB_ANT +}antenna_type; + +typedef enum audio_output +{ + HEADSET, + SPEAKER, +} audio_output; +/** +* RDS/RBDS Program Type type. +*/ +typedef uint8 fm_prgm_type; + +/** +* RDS/RBDS Program Identification type. +*/ +typedef uint16 fm_prgmid_type; +/** +* RDS/RBDS Program Services type. +*/ +typedef char fm_prm_services; +/** +* RDS/RBDS Radio Text type. +*/ +/* +* FM RX RIVA peek request +*/ +typedef struct fm_riva_peek_word +{ + uint8 subOpcode; + uint32 startaddress; + uint8 payload_length;/*In Bytes*/ + uint8 data[MAX_RIVA_DATA_LEN]; +}__attribute__((packed))fm_riva_peek_word; + +/* +* FM RX RIVA poke request +*/ +typedef struct fm_riva_poke_word +{ + uint8 subOpcode; + uint32 startaddress; + uint8 payload_length;/*In Bytes*/ + uint8 data[MAX_RIVA_DATA_LEN]; +}__attribute__((packed))fm_riva_poke_word ; + + +/* +* FM RX SSBI peek/poke request +*/ +typedef struct fm_ssbi_poke_reg +{ + uint16 startaddress; + uint8 data; +}__attribute__((packed))fm_ssbi_poke_reg; + +/* +* fm Set Get Reset AGC request +*/ +typedef struct fm_set_get_reset_agc_req +{ + uint8 ucCtrl; + uint8 ucGainState; +}__attribute__((packed))fm_set_get_reset_agc_req; + +typedef struct fm_set_get_reset_agc_params +{ + uint8 ucCurrentGainState; + uint8 ucGainStateChange1; + uint8 ucGainStateChange2; + uint8 ucGainStateChange3; +}__attribute__((packed))fm_set_get_reset_agc_params; + +typedef PACKED struct +{ + uint8 status ; + uint8 data_length ; + uint8 data[DEFAULT_DATA_SIZE]; +}__attribute__((packed)) readDefaults_data; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + uint8 status ; + uint8 data_length ; + uint8 data[DEFAULT_DATA_SIZE]; +}__attribute__((packed)) default_read_rsp; + +/*RDS Group counters*/ +typedef struct fm_rds_grp_cntrsparams +{ + uint32 totalRdsSBlockErrors; + uint32 totalRdsGroups; + uint32 totalRdsGroup0; + uint32 totalRdsGroup2; + uint32 totalRdsBlockB; + uint32 totalRdsProcessedGroup0; + uint32 totalRdsProcessedGroup2; + uint32 totalRdsGroupFiltered; + uint32 totalRdsChangeFiltered; +}__attribute__((packed)) fm_rds_grp_cntrsparams; + +/*RDS Group counters extended */ +typedef struct fm_rds_grpcntrs_extendedparams +{ + uint32 totalRdsSyncLoss; + uint32 totalRdsNotSync; + uint32 totalRdsSyncInt; +}__attribute__((packed)) fm_rds_grpcntrs_extendedparams; + +typedef char fm_radiotext_info; +/** +* FM Global Paramaters struct. +*/ +typedef struct +{ + uint32 current_station_freq;/*a frequency in kHz the band range*/ + uint8 service_available; + uint8 rssi; /* rssi range from 0-100*/ + uint8 stype; + uint8 rds_sync_status; + uint8 mute_status; + uint8 ssbi_peek_data; + fm_prgmid_type pgm_id; /* Program Id */ + fm_prgm_type pgm_type; /* Program type */ + fm_prm_services pgm_services[MAX_RDS_PS_LENGTH]; + fm_radiotext_info radio_text[MAX_RDS_RT_LENGTH];/* RT maximum is 64 bytes */ + fm_riva_poke_word riva_data_access_params; + fm_set_get_reset_agc_params set_get_reset_agc_params; + fm_rds_grp_cntrsparams rds_group_counters; + fm_rds_grpcntrs_extendedparams rds_group_counters_extended; + readDefaults_data default_read_data; + uint8 fm_ps_length; + uint8 fm_rt_length; + uint8 sinr_samples; + char sinr_threshold; + uint8 On_channel_threshold; + uint8 Off_channel_threshold; +}fm_station_params_available; +/** +* FM Config Request structure. +*/ +typedef struct fm_config_data +{ + uint8 band; + uint8 emphasis; + uint8 spacing; + uint8 rds_system; + band_limit_freq bandlimits; + uint8 is_fm_tx_on; +}fm_config_data; + +/* +* FM RDS Options Config Request +*/ +typedef struct fm_rds_options +{ + uint32 rds_group_mask; + uint32 rds_group_buffer_size; + uint8 rds_change_filter; +}fm_rds_options; +/* +* FM RX Search stations request +*/ +typedef struct fm_search_stations +{ + uint8 search_mode; + uint8 dwell_period; + uint8 search_dir; +}fm_search_stations; + +/* +* FM RX Search DDS stations request +*/ +typedef struct fm_search_rds_stations +{ + uint8 search_mode; + uint8 dwell_period; + uint8 search_dir; + uint8 program_type; + uint16 program_id; +}fm_search_rds_stations; + +/* +* FM RX Search station lists request +*/ +typedef struct fm_search_list_stations +{ + uint8 search_mode; + uint8 search_dir; + uint32 srch_list_max; + /**< Maximum number of stations that can be returned from a search. */ + uint8 program_type; +}fm_search_list_stations; + +/* +* FM RX I2C request +*/ +typedef struct fm_i2c_params +{ + uint8 slaveaddress; + uint8 offset; + uint8 payload_length; + uint8 data[64]; +}fm_i2c_params; + +/* Structure containing the RDS PS Info to be transmitted */ +typedef struct _tsFtmFmRdsTxPsType +{ + uint32 ulPSStrLen; + /**< The size of the cTxPSStrPtr buffer. + */ + + uint32 ucTxPSRptCnt; + /**< The number of times each 8 character string is repeated before the next + string is transmitted. + */ + + uint16 tusTxPi; + /**< RDS/RBDS Program Identification to use for Program Service transmissions. + */ + + uint8 tucTxPSPty; + /**< The RDS/RBDS Program Type to transmit. + */ + + const char cTxPSStrPtr[108]; + /**< A pointer to a buffer containing the Program Service string to transmit + (must be null terminated). + */ + +} tsFtmFmRdsTxPsType; + +typedef struct _tsFtmFmRdsTxRtType +{ + uint32 ulRTStrLen; + /**< The size of the cTxRTStrPtr buffer. + */ + + uint16 tusTxPi; + /**< RDS/RBDS Program Identification to use for RadioText transmissions. + */ + + uint8 tucTxRTPty; + /**< The RDS/RBDS Program Type to transmit. + */ + + const char cTxRTStrPtr[65]; + /**< A pointer to a buffer containing the RadioText string to transmit + (must be null terminated). + */ + +} tsFtmFmRdsTxRtType; + +typedef struct _ftm_def_data_rd_req +{ + uint8 mode; + uint8 length; + uint8 param_len; + uint8 param; +} __attribute__((packed))ftm_fm_def_data_rd_req; + +typedef struct _ftm_def_data_wr_req +{ + uint8 mode; + uint8 length; + uint8 data[DEFAULT_DATA_SIZE]; +} __attribute__((packed))ftm_fm_def_data_wr_req; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 length; /*RDS PS string length*/ + uint8 string[MAX_RDS_PS_LENGTH]; /* RDS string */ +}__attribute__((packed)) fmrdsps_response; + + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 length; /*RDS PS string length*/ + uint8 string[MAX_RDS_RT_LENGTH]; /* RDS string */ +}__attribute__((packed)) fmrdsrt_response; + + +/** +* FM All Request Union type. +*/ +typedef union fm_cfg_request +{ + fm_config_data cfg_param; + uint8 mute_param; + uint8 stereo_param; + uint32 freq; + fm_rds_options rds_options; + uint8 power_mode; + uint8 signal_threshold; + fm_search_stations search_stations_options; + fm_search_rds_stations search_rds_stations_options; + fm_search_list_stations search_list_stations_options; + fm_i2c_params i2c_params; + uint32 rds_group_options; + uint16 rx_af_threshold; + uint8 rx_rssi_checktimer; + uint rx_rds_pi_timer; + tsFtmFmRdsTxPsType tuFmPSParams; + tsFtmFmRdsTxRtType tuFmRTParams; + uint8 soft_mute_param; + uint8 antenna_type; + uint8 tx_tone_param; + uint8 rds_grp_counters; + uint8 rds_grp_counters_ext; + uint8 hlsi; + uint8 sinr_samples; + char sinr_threshold; + uint8 On_channel_threshold; + uint8 Off_channel_threshold; + uint8 notch; + fm_riva_peek_word riva_peek_params; + fm_riva_poke_word riva_data_access_params; + fm_ssbi_poke_reg ssbi_access_params; + fm_set_get_reset_agc_req set_get_agc_req_parameters; + ftm_fm_def_data_rd_req rd_default; + ftm_fm_def_data_wr_req wr_default; + uint8 tx_pwr_cfg; + uint8 audio_output; + uint8 audio_vlm; +}fm_cfg_request; + +/* FTM FM request type */ +typedef PACKED struct +{ + diagpkt_cmd_code_type cmd_code; + diagpkt_subsys_id_type subsys_id; + diagpkt_subsys_cmd_code_type subsys_cmd_code; + uint16 cmd_id; /* command id (required) */ + uint16 cmd_data_len; + uint16 cmd_rsp_pkt_size; + byte data[1]; +}__attribute__((packed))ftm_fm_pkt_type; + +/* Set MuteMode Response */ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 mutemode; +}__attribute__((packed)) mutemode_response; + +/* Set StereoMode Response */ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 stereomode; +}__attribute__((packed)) stereomode_response; + +/* I2C Response */ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint32 length; /*length of data read */ + uint8 data[64]; /* I2C read dat buffer */ +}__attribute__((packed)) fmbusread_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 sub_opcode; + uint32 start_address; + uint8 length; /*length of data read */ + uint8 data[MAX_RIVA_DATA_LEN]; /* read dat buffer */ +}__attribute__((packed)) rivaData_response; + + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 data; +}__attribute__((packed)) ssbiPeek_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint8 uccurrentgainstate; + uint8 ucgainstatechange1; + uint8 ucgainstatechange2; + uint8 ucgainstatechange3; +}__attribute__((packed)) set_get_reset_agc_response; + +/*Read RDS Group counters responce*/ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + fm_rds_grp_cntrsparams read_rds_cntrs; +}__attribute__((packed)) ReadRDSCntrs_responce; + +/*Read RDS Group counters response*/ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + fm_rds_grpcntrs_extendedparams read_rds_cntrs_ext; +}__attribute__((packed)) ReadRDSCntrs_ext_response; + + +/* Generic Response */ +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ +}__attribute__((packed)) generic_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint16 afthreshold; +} fmrxsetafthreshold_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 sinr_sample; +} getsinrsamples_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + char sinr_threshold; +} getsinrthreshold_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 sinr_on_th; +} getonchannelthreshold_response; +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 sinr_off_th; +} getoffchannelthreshold_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 rssitimer; +} fmrxsetrssichecktimer_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 rdspitimer; +} fmrxsetrdspitimer_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint8 threshold; +} threshold_response; + +typedef PACKED struct +{ + diagpkt_subsys_header_type header ; + char result ; + uint32 rdserrcount; + uint32 numofblocks; +} rds_err_count_response; + +/* Custom response for Get station parameters request */ +struct fm_rx_get_station_parameters_response_t +{ + diagpkt_subsys_header_type header ; /*Diag header*/ + char result ;/* result */ + uint32 stationFreq; + /* The currently tuned frequency in kHz (Example: 96500 -> 96.5Mhz)*/ + uint8 servAvble; + /* The current service available indicator for the current station */ + uint8 rssi; + /* The current signal strength level (0-100 range). */ + uint8 stereoProgram; + /* The current mono/stereo indicator for this station */ + uint8 rdsSyncStatus; + /* The current RDS/RBDS synchronization status */ + uint8 muteMode; + /* The current FM mute mode */ +}__attribute__((packed)); + +/* FTM Log Packet - Used to send back the event of a HCI Command */ +typedef PACKED struct +{ + log_hdr_type hdr; + byte EvName; + /* Event ID indicates which event is being returned. */ + byte EvResult; + byte data[1]; /* Variable length payload, + look at FTM log id for contents */ +} ftm_fm_log_pkt_type; +#define FTM_FM_LOG_HEADER_SIZE (sizeof (ftm_fm_log_pkt_type) - 1) + +typedef struct fm_rx_get_station_parameters_response_t fm_rx_get_station_parameters_response; +/*=========================================================================== +FUNCTION ftm_fm_dispatch + +DESCRIPTION + Dispatch routine for the various FM Rx/Tx commands. Copies the data into + a global union data structure before calling the processing routine + +DEPENDENCIES + NIL + +RETURN VALUE + A Packed structre pointer including the response to the FTM FM packet + +SIDE EFFECTS + None + +===========================================================================*/ + +void * ftm_fm_dispatch(ftm_fm_pkt_type *ftm_fm_pkt, uint16 length ); + + +/*=========================================================================== + +FUNCTION ftm_fm_enable_audio + +DESCRIPTION + This function is used to take the audio output mode from QRCT. + +DEPENDENCIES + none + +===========================================================================*/ +PACKED void* ftm_fm_enable_audio( void ); +PACKED void* ftm_fm_disable_audio( void ); +PACKED void* ftm_fm_setting_volume(void); + +#endif /* CONFIG_FTM_FM */ diff --git a/qca/ftm/src/ftm_fm_pfal.h b/qca/ftm/src/ftm_fm_pfal.h new file mode 100644 index 000000000..cde8d18de --- /dev/null +++ b/qca/ftm/src/ftm_fm_pfal.h @@ -0,0 +1,1178 @@ +/*========================================================================== + + FTM FM PFAL Header File + +Description + Function declarations of the PFAL interfaces for FM. + +# Copyright (c) 2010-2012 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +08/03/2011 uppalas Adding support for new ftm commands +06/18/10 rakeshk Created a header file to hold the interface declarations + for ftm fm commands +07/06/10 rakeshk Added the support for new PFAL APIs for FM Rx +04/03/11 ananthk Added the support for FM Tx functionalities +===========================================================================*/ +#ifdef CONFIG_FTM_FM + +#include "event.h" +#include "diagpkt.h" +#include "ftm_fm_common.h" + +/*=========================================================================== +FUNCTION EnableFM + +DESCRIPTION + PFAL specific routine to enable FM with the Radio Configuration parameters + passed. + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type EnableFM +( + fm_config_data* radiocfgptr +); + +/*=========================================================================== +FUNCTION ConfigureFM + +DESCRIPTION + PFAL specific routine to configure FM with the Radio Configuration + parameters passed. + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type ConfigureFM +( + fm_config_data* radiocfgptr +); + +/*=========================================================================== +FUNCTION SetFrequencyTransmitter + +DESCRIPTION + PFAL specific routine to configure the FM transmitter's Frequency of reception + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyTransmitter +( + uint32 ulfreq +); + +/*=========================================================================== +FUNCTION TransmitPS + +DESCRIPTION + PFAL specific routine to transmit RDS PS strings + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type TransmitPS +( + tsFtmFmRdsTxPsType* tuFmPSParams +); + +/*=========================================================================== +FUNCTION stopTransmitPS + +DESCRIPTION + PFAL specific routine to stop transmitting the PS string. + +PARAMS PASSED + NIL + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +============================================================================*/ +fm_cmd_status_type stopTransmitPS +( + void +); + +/*=========================================================================== +FUNCTION TransmitRT + +DESCRIPTION + PFAL specific routine to transmit the RT string which provides a brief info + of the audio content being transmitted. This includes artist name, movie name + few lines of the audio. Usually the metadata of the song is transmitted as RT + +PARAMS PASSED + 'tuFmRTParams' containing RDS PI, and RT information of the transmitting + station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None +===========================================================================*/ +fm_cmd_status_type TransmitRT +( + tsFtmFmRdsTxRtType* tuFmRTParams +); +/*=========================================================================== +FUNCTION stopTransmitRT + +DESCRIPTION + PFAL specific routine to stop transmitting the RT string for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type stopTransmitRT +( + void +); + +/*=========================================================================== +FUNCTION getTxPSFeatures + +DESCRIPTION + PFAL specific routine to get the supported PS features for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type getTxPSFeatures +( + void +); + +/*=========================================================================== +FUNCTION SetTxPowerLevel + +DESCRIPTION + PFAL specific routine to configure the FM transmitter's power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetTxPowerLevel +( + uint32 ulfreq +); + +/*=========================================================================== +FUNCTION DisableFM + +DESCRIPTION + PFAL specific routine to disable FM and free all the FM resources + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type DisableFM +( + fm_config_data* radiocfgptr +); + +/*=========================================================================== +FUNCTION SetFrequencyReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Frequency of reception + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyReceiver +( + uint32 ulfreq +); + +/*=========================================================================== +FUNCTION SetMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSoftMuteModeReceiver +( + mute_type mutemode +); + +/*=========================================================================== +FUNCTION SetMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetMuteModeReceiver +( + mute_type mutemode +); + +/*=========================================================================== +FUNCTION SetAntenna + +DESCRIPTION + PFAL specific routine to configure the FM receiver's antenna type + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetAntenna +( + antenna_type antenna +); + + +/*=========================================================================== +FUNCTION SetStereoModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Audio mode on the + frequency tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetStereoModeReceiver +( + stereo_type stereomode +); + +/*=========================================================================== +FUNCTION GetStationParametersReceiver + +DESCRIPTION + PFAL specific routine to get the station parameters of the Frequency at + which the Radio receiver is tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetStationParametersReceiver +( + fm_station_params_available* configparams +); +/*=========================================================================== +FUNCTION SetRdsOptionsReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsOptionsReceiver +( + fm_rds_options rdsoptions +); + +/*=========================================================================== +FUNCTION SetRdsGroupProcReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS group proc options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsGroupProcReceiver +( + uint32 rdsgroupoptions +); + +/*=========================================================================== +FUNCTION SetPowerModeReceiver + +DESCRIPTION + PFAL specific routine to configure the power mode of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetPowerModeReceiver +( + uint8 powermode +); + +/*=========================================================================== +FUNCTION SetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to configure the signal threshold of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSignalThresholdReceiver +( + uint8 signalthreshold +); + +/*=========================================================================== +FUNCTION GetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to get the signal threshold of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetSignalThresholdReceiver +( + uint8* signalthreshold +); + + +/*=========================================================================== +FUNCTION GetRSSILimits + +DESCRIPTION + PFAL specific routine to print the RSSI limits of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRSSILimits +( +); + + +/*=========================================================================== +FUNCTION GetPSInfoReceiver + +DESCRIPTION + PFAL specific routine to print the PS info of current frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetPSInfoReceiver +( +); + +/*=========================================================================== +FUNCTION GetRTInfoReceiver + +DESCRIPTION + PFAL specific routine to print the Radio text info of current frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRTInfoReceiver +( +); + +/*=========================================================================== +FUNCTION GetAFInfoReceiver + +DESCRIPTION + PFAL specific routine to print the AF list for current frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetAFInfoReceiver +( +); + +/*=========================================================================== +FUNCTION SearchStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationsReceiver +( +fm_search_stations searchstationsoptions +); + + +/*=========================================================================== +FUNCTION SearchRDSStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver with a specific program type and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchRdsStationsReceiver +( +fm_search_rds_stations searchrdsstationsoptions +); + + +/*=========================================================================== +FUNCTION SearchStationListReceiver + +DESCRIPTION + PFAL specific routine to search for stations with a specific mode of + informaation like WEAK,STRONG,STRONGEST etc + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationListReceiver +( +fm_search_list_stations searchliststationsoptions +); + + +/*=========================================================================== +FUNCTION CancelSearchReceiver + +DESCRIPTION + PFAL specific routine to cancel the ongoing search operation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type CancelSearchReceiver +( +); + +/*=========================================================================== +FUNCTION FmBusWriteReceiver + +DESCRIPTION + PFAL specific routine to program the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusWriteReceiver +( +fm_i2c_params writeparams +); + +/*=========================================================================== +FUNCTION FmBusReadReceiver + +DESCRIPTION + PFAL specific routine to read the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusReadReceiver +( +fm_i2c_params *readparams +); + +/*=========================================================================== +FUNCTION FmRivaPeekData + +DESCRIPTION + PFAL specific routine to get the data from Riva Memory + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmRivaPeekData +( +fm_riva_peek_word peek_word +); + +/*=========================================================================== +FUNCTION FmRivaPokeData + +DESCRIPTION + PFAL specific routine to write the data into the Riva Memory + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmRivaPokeData +( +fm_riva_poke_word poke_word +); + +/*=========================================================================== +FUNCTION FmSSBIPeekData + +DESCRIPTION + PFAL specific routine to get the data from SSBI registers + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmSSBIPeekData( +fm_ssbi_poke_reg peek_reg +); + +/*=========================================================================== +FUNCTION FmSetGetResetAGC + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmSetGetResetAGC( +fm_set_get_reset_agc_req agc_params +); + +/*=========================================================================== +FUNCTION FmSSBIPokeData + +DESCRIPTION + PFAL specific routine to program the SSBI registers + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmSSBIPokeData( +fm_ssbi_poke_reg peek_reg +); + +/*=========================================================================== +FUNCTION FmTxToneGen + +DESCRIPTION + PFAL specific routine to configure the FM Tx internal tone Generation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmTxToneGen +( +uint8 txTone +); + +/*=========================================================================== +FUNCTION FmRDSGrpcntrs + +DESCRIPTION + PFAL specific routine to read the FM RDS group counters + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmRDSGrpcntrs +( + uint8 rdsCounters +); + +/*=========================================================================== +FUNCTION FmRDSGrpcntrsExt + +DESCRIPTION + PFAL specific routine to read the FM RDS group counters extended + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmRDSGrpcntrsExt +( + uint8 rdsCounters +); + +/*=========================================================================== +FUNCTION FmSetHlSi + +DESCRIPTION + PFAL specific routine to configure the FM receiver's HlSi on the + frequency tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmSetHlSi +( + uint8 hlsi +); + +/*=========================================================================== +FUNCTION GetSINRSamples + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR samples + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRSamples +( + +); +/*=========================================================================== +FUNCTION SetSINRSamples + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR samples + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetSINRSamples +( + uint8 sinr_sample +); + +/*=========================================================================== +FUNCTION GetSINRThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRThreshold +( + +); +/*=========================================================================== +FUNCTION SetSINRThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetSINRThreshold +( + char sinr_threshold +); + +/*=========================================================================== +FUNCTION GetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's on channel threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOnChannelThreshold +( + +); + +/*=========================================================================== +FUNCTION SetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's on channel threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOnChannelThreshold +( + uint8 on_channel_th +); + +/*=========================================================================== +FUNCTION GetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's off channel threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOffChannelThreshold +( + +); + +/*=========================================================================== +FUNCTION SetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's off channel threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOffChannelThreshold +( + uint8 off_channel_th +); +/*=========================================================================== +FUNCTION FmSetNotchFilter + +DESCRIPTION + PFAL specific routine to configure the FM receiver's notch filter + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmSetNotchFilter +( + uint8 notch +); + +/*=========================================================================== +FUNCTION FmDefaultRead + +DESCRIPTION + PFAL specific routine to get the FM Default Values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmDefaultRead +( + ftm_fm_def_data_rd_req defaultRead +); + +/*=========================================================================== +FUNCTION FmDefaultWrite + +DESCRIPTION + PFAL specific routine to write the default values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmDefaultWrite +( + ftm_fm_def_data_wr_req* + defaults +); + +/*=========================================================================== +FUNCTION FmTxPwrLvlCfg + +DESCRIPTION + PFAL specific routine to configure the FM Tx power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmTxPwrLvlCfg +( + uint8 pwrCfg +); + +/*=========================================================================== + +FUNCTION ftm_fm_run_mm + +DESCRIPTION + This function is used to run mm-audio-ftm. + +DEPENDENCIES + none + +===========================================================================*/ +void ftm_fm_run_mm +( + void +); + +/*=========================================================================== + +FUNCTION ftm_fm_audio + +DESCRIPTION + This function is used to load the target based config file and + set the audio output and volume. + +DEPENDENCIES + none + +===========================================================================*/ +fm_cmd_status_type ftm_fm_audio +( + uint8 source, + uint8 volume +); + +#endif /* CONFIG_FTM_FM */ +void ftm_fm_enable_slimbus(int val); diff --git a/qca/ftm/src/ftm_fm_pfal_linux.c b/qca/ftm/src/ftm_fm_pfal_linux.c new file mode 100644 index 000000000..206c33062 --- /dev/null +++ b/qca/ftm/src/ftm_fm_pfal_linux.c @@ -0,0 +1,3668 @@ +/*========================================================================== + +Description + Platform specific routines to program the V4L2 driver for FM + +# Copyright (c) 2010-2015 by Qualcomm Technologies, Inc. All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +08/03/2011 uppalas Adding support for new ftm commands +04/05/11 ananthk Added support for FM Tx functionalities +03/15/11 naveenr Choosing I2C device path based on board type. Added + support for 7x30 +02/08/11 braghave Calling the fm_qsoc_patches with right parameter + for non-Android case. +06/30/10 rakeshk Created a source file to implement platform specific + routines for FM +07/06/10 rakeshk Added support for all the Rx commands and clean roomed + the header and data structures +01/07/11 rakeshk Added two support APIs to read/write the I2C bus with +==========================================================================*/ + +#include "ftm_fm_pfal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ANDROID +#include +#endif +#include +#include +#include +#include +#include +#include "ftm_common.h" +#include +#define BIT16 (1<<16) +#define FM_SLAVE_ADDR 0x2A +/* Multiplying factor to convert to Radio freqeuncy */ +#define TUNE_MULT 16000 +/* Constant to request for Radio Events */ +#define EVENT_LISTEN 1 +/* 1000 multiplier */ +#define MULTIPLE_1000 1000 +/* Tavaura I2C address */ +int SLAVE_ADDR = 0x2A; +/* Tavaura I2C statu register*/ +#define INTSTAT_0 0x0 +/* Debug Macro */ +#define FTM_DEBUG +#ifdef FTM_DEBUG +#define print(x) printf(x) +#define print2(x,y) printf(x,y) +#define print3(x,y,z) printf(x,y,z) +#else +#define print(x) +#define print2(x,y) +#define print3(x,y,z) +#endif + +#define UNUSED(x) (void)(x) + +enum tavarua_buf_t { + TAVARUA_BUF_SRCH_LIST, + TAVARUA_BUF_EVENTS, + TAVARUA_BUF_RT_RDS, + TAVARUA_BUF_PS_RDS, + TAVARUA_BUF_RAW_RDS, + TAVARUA_BUF_AF_LIST, + TAVARUA_BUF_MAX +}; + +enum tavarua_xfr_ctrl_t { + RDS_PS_0 = 0x01, + RDS_PS_1, + RDS_PS_2, + RDS_PS_3, + RDS_PS_4, + RDS_PS_5, + RDS_PS_6 +}; + +enum tavarua_evt_t { + TAVARUA_EVT_RADIO_READY, + TAVARUA_EVT_TUNE_SUCC, + TAVARUA_EVT_SEEK_COMPLETE, + TAVARUA_EVT_SCAN_NEXT, + TAVARUA_EVT_NEW_RAW_RDS, + TAVARUA_EVT_NEW_RT_RDS, + TAVARUA_EVT_NEW_PS_RDS, + TAVARUA_EVT_ERROR, + TAVARUA_EVT_BELOW_TH, + TAVARUA_EVT_ABOVE_TH, + TAVARUA_EVT_STEREO, + TAVARUA_EVT_MONO, + TAVARUA_EVT_RDS_AVAIL, + TAVARUA_EVT_RDS_NOT_AVAIL, + TAVARUA_EVT_NEW_SRCH_LIST, + TAVARUA_EVT_NEW_AF_LIST, + TAVARUA_EVT_TXRDSDAT, + TAVARUA_EVT_TXRDSDONE, + TAVARUA_EVT_RADIO_DISABLED +}; + +#define TAVARUA_BUF_PS_RDS 3 +#define V4L2_CID_PRIVATE_TAVARUA_REGION 0x08000007 +#define V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT 0x08000015 +#define V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME 0x08000016 +#define V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT 0x08000017 +#define V4L2_CID_PRIVATE_TAVARUA_STATE 0x08000004 +#define V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH 0x8000029 +#define V4L2_CID_PRIVATE_TAVARUA_RDSON 0x0800000F +#define V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC 0x08000010 +#define V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK 0x08000006 +#define V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF 0x08000013 +#define V4L2_CID_PRIVATE_TAVARUA_ANTENNA 0x08000012 +#define V4L2_CID_PRIVATE_TAVARUA_RDSON 0x0800000F +#define V4L2_CID_PRIVATE_TAVARUA_EMPHASIS 0x0800000C +#define V4L2_CID_PRIVATE_TAVARUA_SPACING 0x0800000E +#define V4L2_CID_PRIVATE_TAVARUA_RDS_STD 0x0800000D +#define V4L2_CID_PRIVATE_TAVARUA_LP_MODE 0x08000011 +#define V4L2_CID_PRIVATE_TAVARUA_SRCHMODE 0x08000001 +#define V4L2_CID_PRIVATE_TAVARUA_SCANDWELL 0x08000002 +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_PI 0x0800000A +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT 0x0800000B +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY 0x08000009 +#define V4L2_CID_PRIVATE_TAVARUA_SRCHON 0x08000003 +#define V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD 0x800002D +#define V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD 0x800002E +#define V4L2_CID_PRIVATE_SINR_THRESHOLD 0x800002F +#define V4L2_CID_PRIVATE_SINR_SAMPLES 0x8000030 +#define V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH 0x08000008 +#define SRCH_DIR_UP (0) +#define SRCH_DIR_DOWN (1) + +#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */ +#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */ +#define RDS_Tx 0x80 +const char* fm_i2c_path_8660 = "/dev/i2c-4"; +const char* fm_i2c_path_7x30 = "/dev/i2c-2"; +const char* fm_i2c_path_7627a = "/dev/i2c-1"; +/* To get the current status of PS/RT transmission */ +volatile unsigned char is_rt_transmitting = 0; +volatile unsigned char is_ps_transmitting = 0; +int ftm_audio_fd = -1; +const char *const audio_config = "-c /vendor/etc/ftm_test_config"; +const char *const ext_audio_config = "-c /system/etc/ftm_test_config_wcd9335"; +const unsigned int CMD_len = 16; +const int config_len = 31; +const int ext_config_len = 39; +const int sound_card_name_len = 16; +const char *const mm_audio_path = "/vendor/bin/mm-audio-ftm"; +/* enum to montior the Power On status */ +typedef enum +{ + INPROGRESS, + COMPLETE +}poweron_status; + +boolean cmd_queued = FALSE; +/* Resourcse Numbers for Rx/TX */ +int FM_RX = 1; +int FM_TX = 2; +/* Boolean to control the power down sequence */ +volatile boolean power_down = FALSE; +/* V4L2 radio handle */ +int fd_radio = -1; +/* FM asynchornous thread to perform the long running ON */ +pthread_t fm_interrupt_thread,fm_on_thread; +/* Prototype ofFM ON thread */ +void *(ftm_on_long_thread)(void *ptr); +/* Global state ofthe FM task */ +fm_station_params_available fm_global_params; + +volatile poweron_status poweron; + +int chipVersion = 0; +extern volatile fm_power_state fmPowerState; +static char transport[PROPERTY_VALUE_MAX]; + +/*=========================================================================== +FUNCTION WaitonInterrupt + +DESCRIPTION + Helper function to read the Interrupt register to check for a trasnfer + complete interrupt + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ + +int WaitonInterrupt(int fd,unsigned int intmask,unsigned int waittime) +{ + unsigned char buf[4]; + unsigned int maxtries=0; + unsigned int readdata=0; + int ret; + print("WaitonInterrupt >\n"); + while(((readdata & intmask) != intmask)&&(maxtries < 10)) + { + usleep(waittime*MULTIPLE_1000); + /* Read the 3 interrupt registers */ + ret = i2c_read(fd, INTSTAT_0, buf, 3,SLAVE_ADDR); + if (ret < 0) + { + return -1; + } + readdata |= buf[0]; + readdata |= buf[1] << 8; + readdata |= buf[2] << 16; + maxtries++; + } + if((readdata & intmask) != intmask) + { + return -1; + } + print("WaitonInterrupt <\n"); + return 0; +} + +/*=========================================================================== +FUNCTION set_v4l2_ctrl + +DESCRIPTION + Sets the V4L2 control sent as argument with the requested value and returns the status + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE in failure,TRUE in success + +SIDE EFFECTS + None + +===========================================================================*/ +boolean set_v4l2_ctrl(int fd,uint32 id,int32 value) +{ + struct v4l2_control control; + int err; + + control.value = value; + control.id = id; + switch(id) + { + case V4L2_CID_PRIVATE_TAVARUA_REGION : + if (value == FM_US_EU) + { + print("\n Region : US-EUROPE\n"); + control.value = FM_US_EU; + } + /* + Increment the 'control.value' to match the 'tavarua_region_t' enum + variable defined in the V4L2 driver. + + FTM: V4L2: + + US/EUROPE - '0' US - '0' + JAPAN STD - '1' EU - '1' + JAPAN WIDE - '2' JAPAN - '2' + USER-DEFINED - '3' JAPAN WIDE - '3' + REGION OTHER - '4' + */ + + else if(value == FM_JAPAN_STANDARD) + { + print("\n Region : JAPAN-STANARD\n"); + control.value = FM_JAPAN_STANDARD+1; + } + else if(value == FM_JAPAN_WIDE) + { + print("\n Region : JAPAN-WIDE\n"); + control.value = FM_JAPAN_WIDE+1; + } + else if(value == 3) + { + print("\n Region : USER-DEFINED\n"); + control.value = FM_USER_DEFINED; + } + break; + } + err = ioctl(fd,VIDIOC_S_CTRL,&control); + if(err < 0) + { + print3("set_v4l2_ctrl failed for control : %x with return value : %d\n",control.id,err); + return FALSE; + } + return TRUE; +} + +/*=========================================================================== +FUNCTION read_data_from_v4l2 + +DESCRIPTION + reads the fm_radio handle and updates the FM global configuration based on + the interrupt data received + +DEPENDENCIES + NIL + +RETURN VALUE + FALSE in failure,TRUE in success + +SIDE EFFECTS + None + +===========================================================================*/ +int read_data_from_v4l2(int fd,uint8* buf,int index) +{ + struct v4l2_requestbuffers reqbuf; + struct v4l2_buffer v4l2_buf; + int err; + memset(&reqbuf, 0x0, sizeof(reqbuf)); + enum v4l2_buf_type type = V4L2_BUF_TYPE_PRIVATE; + + reqbuf.type = V4L2_BUF_TYPE_PRIVATE; + reqbuf.memory = V4L2_MEMORY_USERPTR; + memset(&v4l2_buf, 0x0, sizeof(v4l2_buf)); + v4l2_buf.index = index; + v4l2_buf.type = type; + v4l2_buf.length = 128; + v4l2_buf.m.userptr = (unsigned long)buf; + err = ioctl(fd,VIDIOC_DQBUF,&v4l2_buf) ; + if(err < 0) + { + print2("ioctl failed with error = %d\n",err); + return -1; + } + return v4l2_buf.bytesused; +} + +/*=========================================================================== +FUNCTION extract_program_service + +DESCRIPTION + Helper routine to read the Program Services data from the V4L2 buffer + following a PS event + +DEPENDENCIES + PS event + +RETURN VALUE + TRUE if success,else FALSE + +SIDE EFFECTS + Updates the Global data strutures PS info entry + +===========================================================================*/ +boolean extract_program_service() +{ + uint8 buf[64]; + int ret; + print("extract_program_service\n"); + ret = read_data_from_v4l2(fd_radio,buf,TAVARUA_BUF_PS_RDS); + print2("read_data_from_v4l2 ret = %d\n",ret); + int num_of_ps = (int)(buf[0] & 0x0F); + int ps_services_len = ((int )((num_of_ps*8) + 5)) - 5; + fm_global_params.fm_ps_length = ps_services_len; + fm_global_params.pgm_id = (((buf[2] & 0xFF) << 8) | (buf[3] & 0xFF)); + fm_global_params.pgm_type = (int)( buf[1] & 0x1F); + memset(fm_global_params.pgm_services,0x0,MAX_RDS_PS_LENGTH); + memcpy(fm_global_params.pgm_services,&buf[5],ps_services_len); + fm_global_params.pgm_services[ps_services_len] = '\0'; + print2("Pid = %d\n",fm_global_params.pgm_id); + print2("Ptype = %d\n",fm_global_params.pgm_type); + print2("PS name %s\n",fm_global_params.pgm_services); + return TRUE; +} +/*=========================================================================== +FUNCTION extract_radio_text + +DESCRIPTION + Helper routine to read the Radio text data from the V4L2 buffer + following a RT event + +DEPENDENCIES + RT event + +RETURN VALUE + TRUE if success,else FALSE + +SIDE EFFECTS + Updates the Global data strutures RT info entry + +===========================================================================*/ + +boolean extract_radio_text() +{ + uint8 buf[120]; + + int bytesread = read_data_from_v4l2(fd_radio,buf,TAVARUA_BUF_RT_RDS); + int radiotext_size = (int)(buf[0] & 0x0F); + fm_global_params.fm_rt_length = radiotext_size; + fm_global_params.pgm_id = (((buf[2] & 0xFF) << 8) | (buf[3] & 0xFF)); + fm_global_params.pgm_type = (int)( buf[1] & 0x1F); + memset(fm_global_params.radio_text,0x0,MAX_RDS_RT_LENGTH); + memcpy(fm_global_params.radio_text,&buf[5],radiotext_size); + printf("RT is %s\n", fm_global_params.radio_text); + return TRUE; +} + + +/*=========================================================================== +FUNCTION extract_peek_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a riva peek data command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data strutures member riva_data_access_params + +===========================================================================*/ + +void extract_peek_data() +{ + uint8 buf[MAX_RIVA_PEEK_RSP_SIZE]; + int bytesread = read_data_from_v4l2(fd_radio,buf,IRIS_BUF_PEEK); + struct fm_riva_poke_word *responce = (struct fm_riva_poke_word *)buf; + memcpy((void*)&fm_global_params.riva_data_access_params, + (void*)responce,sizeof(buf)); +} +/*=========================================================================== +FUNCTION extract_ssbi_peek_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a ssbi peek data command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data strutures member ssbi_peek_data + +===========================================================================*/ + + +void extract_ssbi_peek_data() +{ + uint8 buf[SSBI_PEEK_DATA_SIZE]; + int bytesread = read_data_from_v4l2(fd_radio,buf,IRIS_BUF_SSBI_PEEK); + fm_global_params.ssbi_peek_data = buf[0]; +} + +/*=========================================================================== +FUNCTION extract_rds_grp_cntr_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a Read Rds Group counters command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data strutures member rds_group_counters + +===========================================================================*/ + +void extract_rds_grp_cntr_data() +{ + uint8 buf[RDS_GRP_CNTRS_SIZE]; + int bytesread = read_data_from_v4l2(fd_radio,buf,IRIS_BUF_RDS_CNTRS); + struct RDSCntrsParams *responce = (struct RDSCntrsParams *)buf; + memcpy((void*)&fm_global_params.rds_group_counters,(void*)responce,sizeof(buf)); +} +/*=========================================================================== +FUNCTION extract_default_read_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a defaultRead command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data struture member rd_default + +===========================================================================*/ + +void extract_default_read_data() +{ + uint8 buf[DEFAULT_DATA_SIZE+2]; //2-bytes for status and data length + int bytesread = read_data_from_v4l2(fd_radio,buf,IRIS_BUF_RD_DEFAULT); + readDefaults_data *response = (readDefaults_data *)buf; + memcpy((void*)&fm_global_params.default_read_data,(void*)response,bytesread); +} +/*=========================================================================== +FUNCTION reset_rds + +DESCRIPTION + Reset the existing RDS data. + +DEPENDENCIES + Radio event + +RETURN VALUE + void + +IDE EFFECTS + Reset the Global RDS data info like RT, PS etc. +===========================================================================*/ + +void reset_rds() +{ + memset(fm_global_params.pgm_services,0x0,MAX_RDS_PS_LENGTH); + memset(fm_global_params.radio_text,0x0,MAX_RDS_RT_LENGTH); + fm_global_params.pgm_id = 0; + fm_global_params.pgm_type = 0; +} +/*=========================================================================== +FUNCTION process_radio_event + +DESCRIPTION + Helper routine to process the radio event read from the V4L2 and performs + the corresponding action. + +DEPENDENCIES + Radio event + +RETURN VALUE + TRUE if success,else FALSE + +SIDE EFFECTS + Updates the Global data strutures info entry like frequency, station + available, RDS sync status etc. + +===========================================================================*/ + +boolean process_radio_event(uint8 event_buf) +{ + print2("Process event %d\n",event_buf); + struct v4l2_frequency freq; + boolean ret= TRUE; + switch(event_buf) + { + case TAVARUA_EVT_RADIO_READY: + print("Radio ON complete\n"); + break; + case TAVARUA_EVT_TUNE_SUCC: + print("Tune successful\n"); + reset_rds(); + freq.type = V4L2_TUNER_RADIO; + if(ioctl(fd_radio, VIDIOC_G_FREQUENCY, &freq)< 0) + { + return FALSE; + } + fm_global_params.current_station_freq =((freq.frequency*MULTIPLE_1000)/TUNE_MULT); + break; + case TAVARUA_EVT_SEEK_COMPLETE: + print("Seek Complete\n"); + freq.type = V4L2_TUNER_RADIO; + if(ioctl(fd_radio, VIDIOC_G_FREQUENCY, &freq)< 0) + { + return FALSE; + } + fm_global_params.current_station_freq =((freq.frequency*MULTIPLE_1000)/TUNE_MULT); + break; + case TAVARUA_EVT_SCAN_NEXT: + print("Event Scan next\n"); + break; + case TAVARUA_EVT_NEW_RAW_RDS: + print("Received Raw RDS info\n"); + break; + case TAVARUA_EVT_NEW_RT_RDS: + print("Received RT \n"); + ret = extract_radio_text(); + break; + case TAVARUA_EVT_NEW_PS_RDS: + print("Received PS\n"); + ret = extract_program_service(); + break; + case TAVARUA_EVT_ERROR: + print("Received Error\n"); + break; + case TAVARUA_EVT_BELOW_TH: + print("Received Below TH\n"); + fm_global_params.service_available = FM_SERVICE_NOT_AVAILABLE; + break; + case TAVARUA_EVT_ABOVE_TH: + print("Received above TH\n"); + fm_global_params.service_available = FM_SERVICE_AVAILABLE; + break; + case TAVARUA_EVT_STEREO: + print("Received Stereo Mode\n"); + fm_global_params.stype = FM_RX_STEREO; + break; + case TAVARUA_EVT_MONO: + print("Received Mono Mode\n"); + fm_global_params.stype = FM_RX_MONO; + break; + case TAVARUA_EVT_RDS_AVAIL: + print("Received RDS Available\n"); + fm_global_params.rds_sync_status = FM_RDS_SYNCED; + break; + case TAVARUA_EVT_RDS_NOT_AVAIL: + print("Received RDS Not Available\n"); + fm_global_params.rds_sync_status = FM_RDS_NOT_SYNCED; + break; + case TAVARUA_EVT_NEW_SRCH_LIST: + print("Received new search list\n"); + break; + case TAVARUA_EVT_NEW_AF_LIST: + print("Received new AF List\n"); + break; + case (RDS_Tx | RDS_PS_0): + print("\nSuccessfully transmitted PS Header\n"); + break; + case (RDS_Tx | RDS_PS_1): + case (RDS_Tx | RDS_PS_2): + case (RDS_Tx | RDS_PS_3): + case (RDS_Tx | RDS_PS_4): + case (RDS_Tx | RDS_PS_5): + case (RDS_Tx | RDS_PS_6): + print("\n Successfully transmitted PS Contents \n"); + break; + + } + /* + * This logic is applied to ensure the exit ofthe Event read thread + * before the FM Radio control is turned off. This is a temporary fix + */ + if(power_down == TRUE) + return FALSE; + return ret; +} + +/*=========================================================================== +FUNCTION ftm_fm_interrupt_thread + +DESCRIPTION + Thread to perform a continous read on the radio handle for events + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ + +void * ftm_fm_interrupt_thread(void *ptr) +{ + print("Starting FM event listener\n"); + uint8 buf[128]; + boolean status = TRUE; + int i =0; + int bytesread = 0; + + UNUSED(ptr); + + while(1) + { + bytesread = read_data_from_v4l2(fd_radio,buf,EVENT_LISTEN); + if(bytesread == -1) + break; + for(i =0;iis_fm_tx_on) + print("\nEnable Transmitter entry\n"); + else + print("\nEnable Receiver entry\n"); +#endif + /*Opening the handle to the V4L2 device */ + fd_radio = open("/dev/radio0",O_RDONLY, O_NONBLOCK); + if(fd_radio < 0) + { + if(radiocfgptr->is_fm_tx_on) + { + print2("EnableTransmitter Failed to open = %d\n",fd_radio); + return FM_CMD_FAILURE; + } + else + { + print2("EnableReceiver Failed to open = %d\n",fd_radio); + return FM_CMD_FAILURE; + } + } + + if(radiocfgptr->is_fm_tx_on) + print("\nOpened Transmitter\n"); + else + print("\nOpened Receiver\n"); + +/* + Starting 'ftm_on_long_thread' where we do all the FM configurations + and intializations. + +*/ + fmPowerState = FM_POWER_TRANSITION; + pthread_create( &fm_on_thread, NULL, ftm_on_long_thread, radiocfgptr); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION TransmitPS + +DESCRIPTION + PFAL specific routine to transmit RDS PS strings + +PARAMS PASSED + 'tuFmPSParams' containing RDS PI, PTY, max. no. of PS repeat count and + PS name of the transmitting station + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to transmit the PS string describing the transmitter's + information and genre of the audio content being transmitted + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type TransmitPS +( + tsFtmFmRdsTxPsType* tuFmPSParams +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + print("\n Entering Transmit PS \n"); + + /* Set Program Type (PTY) */ + control.id = V4L2_CID_RDS_TX_PTY; + control.value = 0; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PTY failed \n"); + return FM_CMD_FAILURE; + } + + /* Set Program Identifier (PI) */ + control.id = V4L2_CID_RDS_TX_PI; + control.value = tuFmPSParams->tusTxPi; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PI failed \n"); + return FM_CMD_FAILURE; + } + + /*Set PS max. repeat count */ + control.id = V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT; + control.value = tuFmPSParams->ucTxPSRptCnt; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set MAX_REPEAT_CNT failed \n"); + return FM_CMD_FAILURE; + } + + /*Set Program Service name (PS) */ + ext_ctl.id = V4L2_CID_RDS_TX_PS_NAME; + ext_ctl.string = (char *)tuFmPSParams->cTxPSStrPtr; + ext_ctl.size = tuFmPSParams->ulPSStrLen; + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_FM_TX; + v4l2_ctls.count = 0; + v4l2_ctls.controls = &ext_ctl; + + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set PS failed \n"); + return FM_CMD_FAILURE; + } + is_ps_transmitting = 1; + print("\n Exiting Transmit PS \n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION stopTransmitPS + +DESCRIPTION + PFAL specific routine to stop transmitting the PS string. + +PARAMS PASSED + NIL + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to stop transmitting the PS string + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +============================================================================*/ +fm_cmd_status_type stopTransmitPS +( + void +) +{ + int ret = 0; + struct v4l2_control control; + + print("\n Entering stopTransmitPS \n"); + + control.id = V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME; + ret = ioctl(fd_radio, VIDIOC_S_CTRL , &control); + if(ret < 0){ + print("Failed to stop Transmit PS"); + return FM_CMD_FAILURE; + } + else { + print("\nStopped transmitting PS\n"); + is_ps_transmitting = 0; + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION TransmitRT + +DESCRIPTION + PFAL specific routine to transmit the RT string. + +PARAMS PASSED + 'tuFmRTParams' containing RDS PI, and RT information of the transmitting + station + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to transmit the RT string which provides a brief info + of the audio content being transmitted. This includes artist name, movie name + few lines of the audio. Usually the metadata of the song is transmitted as RT + + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None +===========================================================================*/ +fm_cmd_status_type TransmitRT +( + tsFtmFmRdsTxRtType* tuFmRTParams +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_FM_TX; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + print("\n Entering Transmit RT \n"); + + if(tuFmRTParams == NULL) + { + print("\n 'tuFmRTParams ' is not NULL \n "); + return FM_CMD_FAILURE; + } + else + { + ext_ctl.id = V4L2_CID_RDS_TX_RADIO_TEXT; + ext_ctl.string = (char *)tuFmRTParams->cTxRTStrPtr; + ext_ctl.size = tuFmRTParams->ulRTStrLen; + } + /* Set Program Type (PTY) */ + control.id = V4L2_CID_RDS_TX_PTY; + control.value = 0; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PTY failed \n"); + return FM_CMD_FAILURE; + } + + /* Set Program Identifier (PI) */ + control.id = V4L2_CID_RDS_TX_PI; + control.value = tuFmRTParams->tusTxPi; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PI failed \n"); + return FM_CMD_FAILURE; + } + + /* Set the Radio Text (RT) to be transmitted */ + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set RT failed \n"); + return FM_CMD_FAILURE; + } + + is_rt_transmitting = 1; + return FM_CMD_SUCCESS; + +} + +/*=========================================================================== +FUNCTION stopTransmitRT + +DESCRIPTION + PFAL specific routine to stop transmitting the RT string. + +PLATFORM SPECIFIC DESCRIPTION + This routine is called to stop transmitting the RT string for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type stopTransmitRT +( + void +) +{ + int ret = 0; + + print("\n Entering stopTransmitRT \n"); + + struct v4l2_control control; + control.id = V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT; + ret = ioctl(fd_radio, VIDIOC_S_CTRL , &control); + if(ret < 0){ + print("Failed to stop Transmit RT"); + return FM_CMD_FAILURE; + } + else { + print("\nStopped transmitting RT\n"); + is_rt_transmitting = 0; + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION getTxPSFeatures + +DESCRIPTION + PFAL specific routine to get all the supported Tx PS features + +PLATFORM SPECIFIC DESCRIPTION + This routine is called to get the supported PS features for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type getTxPSFeatures +( + void +) +{ + print("\n Entering getTxPSFeatures() \n"); + printf("\n Supported Tx PS Features:\n"); + printf("\n Max PS Count : %d\n",MAX_TX_PS_LEN); + printf("\n Max PS Repeat Count : %d\n",MAX_TX_PS_RPT_CNT); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_on_long_thread + +DESCRIPTION + Helper routine to perform the rest ofthe FM calibration and SoC Patch + download and configuration settings following the opening ofradio handle + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void *(ftm_on_long_thread)(void *ptr) +{ + int ret = 0; + struct v4l2_control control; + struct v4l2_tuner tuner; + int i,init_success = 0; + char value[PROPERTY_VALUE_MAX]; + struct v4l2_capability cap; + char versionStr[40]; + char cmdBuffer[40]; + char product_board_platform_type[PROPERTY_VALUE_MAX]; + fm_cmd_status_type status; + + fm_config_data* radiocfgptr = (fm_config_data *)ptr; + + /* Query the V4L2 device for capabilities */ + ret = ioctl(fd_radio, VIDIOC_QUERYCAP, &cap); + + if(ret < 0 ) + { + print("Failed to retrieve the Fm SOC version\n"); + return NULL; + } + else + { + print3("VIDIOC_QUERYCAP returns :%d: version: %d \n", ret , cap.version ); + chipVersion = cap.version; + } + + property_get("qcom.bluetooth.soc", value, NULL); + print2("BT soc is %s\n", value); + if (strcmp(value, "rome") != 0) + { + print("Initiating Soc patch download\n"); + +#ifndef ANDROID + snprintf(cmdBuffer, sizeof(cmdBuffer)-1, "fm_qsoc_patches %d %d", cap.version, 0); + ret = system(cmdBuffer); + if(ret != 0) + { + print2("Failed to download patches = %d\n",ret); + return NULL; + } +#else + if( ret >= 0 ) + { + print2("Driver Version(Same as ChipId): %x \n", cap.version ); + /*Convert the integer to string */ + snprintf(versionStr, sizeof(versionStr)-1, "%d", cap.version ); + property_set("hw.fm.version", versionStr); + } + else + { + return NULL; + } + /*Set the mode for soc downloader*/ + property_set("hw.fm.mode", "normal"); + property_set("ctl.start", "fm_dl"); + sleep(1); + for(i=0;i<9;i++) + { + property_get("hw.fm.init", value, NULL); + if(strcmp(value, "1") == 0) + { + init_success = 1; + break; + } + else + { + sleep(1); + } + } + print3("init_success:%d after %d seconds \n", init_success, i); + if(!init_success) + { + property_set("ctl.stop", "fm_dl"); + // close the fd(power down) + close(fd_radio); + return NULL; + } + + property_get("ro.qualcomm.bt.hci_transport", transport, NULL); + print2("ro.qualcomm.bt.hci_transport = %s\n", transport); + if ((3 == strlen(transport)) && (!strncmp("smd", transport, 3))) { + print("Not a WCN2243 target.\n"); + } else { + /* + * For WCN2243 based targets check what is the target type. + * DAC configuration is applicable only msm7627a target. + */ + property_get("ro.board.platform", product_board_platform_type, NULL); + if (!strncmp("msm7627a", product_board_platform_type, + strlen(product_board_platform_type))) { + property_set("hw.fm.mode", "config_dac"); + property_set("hw.fm.init", "0"); + property_set("hw.fm.isAnalog", "true"); + property_set("ctl.start", "fm_dl"); + for (i = 0; i < 3; i++) { + property_get("hw.fm.init", value, NULL); + if (strcmp(value, "1") == 0) { + init_success = 1; + break; + } else { + sleep(1); + } + } + print3("init_success:%d after %d seconds \n", init_success, i); + if (!init_success) { + property_set("ctl.stop", "fm_dl"); + close(fd_radio); + return NULL; + } + } else { + print("Analog audio path not supported\n"); + } + } + +#endif + } + /** + * V4L2_CID_PRIVATE_TAVARUA_STATE + * V4L2_CID_PRIVATE_TAVARUA_EMPHASIS + * V4L2_CID_PRIVATE_TAVARUA_SPACING + * V4L2_CID_PRIVATE_TAVARUA_RDS_STD + * V4L2_CID_PRIVATE_TAVARUA_REGION + */ + + /* Switching on FM */ + if (radiocfgptr->is_fm_tx_on) + { + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_STATE,FM_TX); + if(ret == FALSE) + { + print("Failed to turn on FM Trnasmitter\n"); + return NULL; + } + else + print("\nEnabled FM Transmitter successfully\n"); + } + else + { + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_STATE,FM_RX); + if(ret == FALSE) + { + print("Failed to turn on FM Receiver\n"); + return NULL; + } + else + print("\nEnabled FM Receiver successfully\n"); + } + + /*Enable Analog audio path*/ + ret = set_v4l2_ctrl(fd_radio, V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH, 1); + if(ret == FALSE) + { + print("Failed to set Audio path \n"); + } + + status = ConfigureFM(radiocfgptr); + if(status != FM_CMD_SUCCESS) + { + print("Failed to configure fm\n"); + return NULL; + } + + /* Setting RDS On */ + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSON,1); + if(ret == FALSE) + { + print("Failed to set RDS on \n"); + return NULL; + } + + /* Set the RDS Group Processing : Only in case of FM Receiver */ + if (!radiocfgptr->is_fm_tx_on) + { + control.id = V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC; + ret = ioctl(fd_radio,VIDIOC_G_CTRL,&control); + if(ret < 0) + { + print2("Failed to set RDS group!!!Return value : %d\n",ret); + return NULL; + } + + int rdsMask = FM_RX_RDS_GRP_RT_EBL | FM_RX_RDS_GRP_PS_EBL | + FM_RX_RDS_GRP_AF_EBL | FM_RX_RDS_GRP_PS_SIMPLE_EBL ; + + byte rds_group_mask = (byte)control.value; + byte rdsFilt = 0; + int psAllVal=rdsMask & (1 << 4); + print2("rdsOptions: rdsMask: %x\n",rdsMask); + rds_group_mask &= 0xC7; + + rds_group_mask |= ((rdsMask & 0x07) << 3); + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC, + rds_group_mask); + + if(ret == FALSE) + { + print("Failed to set RDS GROUP PROCESSING!!!\n"); + return NULL; + } + + if (strcmp(value, "rome") == 0) + { + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK, 1); + if (ret == FALSE) + { + print("Failed to set RDS GRP MASK!!!\n"); + return NULL; + } + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF, 1); + if (ret == FALSE) + { + print("Failed to set RDS BUF!!!\n"); + return NULL; + } + } + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_ANTENNA,0); + if(ret == FALSE) + { + print("Failed to set ANTENNA!!!\n"); + return NULL; + } + ret = set_v4l2_ctrl(fd_radio, V4L2_CID_PRIVATE_IRIS_SOFT_MUTE, 0); + if(ret == FALSE) + { + print("Failed to Disable Soft Mute!!!\n"); + return NULL; + } + + } + + /* + + Start the 'ftm_fm_interrupt_thread' thread which listens for and processes + radio events received from the SoC + + */ + pthread_create( &fm_interrupt_thread, NULL, ftm_fm_interrupt_thread, NULL); + power_down = FALSE; + + + + if(radiocfgptr->is_fm_tx_on) { +#ifdef FTM_DEBUG + print("\nEnable Transmitter exit\n"); +#endif + fmPowerState = FM_TX_ON; + } + else { +#ifdef FTM_DEBUG + print("\nEnable Receiver exit\n"); +#endif + fmPowerState = FM_RX_ON; + } + poweron = COMPLETE; + return NULL; +} + +/*=========================================================================== +FUNCTION DisableFM + +DESCRIPTION + PFAL specific routine to disable FM and free the FM resources + +PLATFORM SPECIFIC DESCRIPTION + Closes the handle to /dev/radio0 V4L2 device + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None +===========================================================================*/ +fm_cmd_status_type DisableFM +( + fm_config_data* radiocfgptr +) +{ + struct v4l2_control control; + uint8 buf[128]; + double tune; + char value[PROPERTY_VALUE_MAX]; + struct v4l2_frequency freq_struct; + int ret; + + /* Wait till the previous ON sequence has completed */ + while(poweron != COMPLETE); + +#ifdef FTM_DEBUG + print("DisableFM start\n"); +#endif + + power_down = TRUE; + + /* Set RDS Off */ + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSON,0); + if(ret == FALSE) + { + print("DisableFM failed to set RDS off \n"); + return FM_CMD_FAILURE; + } + + /* Turn off FM */ + /* As part of Turning off FM we will get 'READY' event */ + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_STATE,0); + if(ret == FALSE) + { + if(radiocfgptr->is_fm_tx_on) + { + print("\nFailed to Turn Off FM Transmitter\n"); + return FM_CMD_FAILURE; + } + else + { + print("\nFailed to Turn Off FM Receiver\n"); + return FM_CMD_FAILURE; + } + } + + /* Wait for 'fm_interrupt_thread' thread to complete its execution */ + pthread_join(fm_interrupt_thread,NULL); + +#ifdef FTM_DEBUG + + print("Stopping the FM control\n"); + +#endif + +#ifdef ANDROID + + property_get("qcom.bluetooth.soc", value, NULL); + print2("BT soc is %s\n", value); + if (strcmp(value, "rome") != 0) + { + property_set("ctl.stop", "fm_dl"); + } + +#endif/*ANDROID*/ + + print2("Stopping the FM control = %d\n",close(fd_radio)); + fd_radio = -1; + cmd_queued = TRUE; + +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("Disabled FM Transmitter\n"); + else + print("Disabled FM Receiver\n"); + +#endif + fmPowerState = FM_POWER_OFF; + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION ConfigureFM + +DESCRIPTION + PFAL specific routine to configure FM with the Radio Configuration + parameters passed. + +PLATFORM SPECIFIC DESCRIPTION + Configures the Init parameters like emphasis, channel spacing, Band Limit, + RDS type, Frequency Band, and Radio State. + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type ConfigureFM +( + fm_config_data* radiocfgptr +) +{ + int ret = 0; + struct v4l2_control control; + struct v4l2_tuner tuner; + +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("\nConfigure FM Transmitter entry\n"); + else + print("\nConfigure FM Receiver entry\n"); +#endif + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + /* Set Emphasis, Channel spacing and RDS Standard : + Emphasis : + '0' - 75 - US/EU + '1' - 50 - JAPAN/JAPAN-WIDE/ASIA + Channel Spacing : + '0' - 200kHz - US/EU + '1' - 100kHz - JAPAN + '2' - 50kHz - JAPAN-WIDE + RDS/RDBS Standard : + '0' - RDBS - US/EU + '1' - RDS - All regions + */ + switch(radiocfgptr->band) + { + case FM_US_EU: + radiocfgptr->emphasis = 0; + radiocfgptr->spacing = 0; + radiocfgptr->rds_system = 0; + break; + case FM_JAPAN_STANDARD: + radiocfgptr->emphasis = 1; + radiocfgptr->spacing = 1; + radiocfgptr->rds_system = 1; + case FM_JAPAN_WIDE: + radiocfgptr->emphasis = 1; + radiocfgptr->spacing = 2; + radiocfgptr->rds_system = 1; + break; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_EMPHASIS, + radiocfgptr->emphasis); + if(ret == FALSE) + { + print("ConfigureFM : Failed to set Emphasis \n"); + return FM_CMD_FAILURE; + } + + /* Set channel spacing */ + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SPACING, + radiocfgptr->spacing); + if(ret == FALSE) + { + print("ConfigureFM : Failed to set channel spacing \n"); + return FM_CMD_FAILURE; + } + + /* Set RDS/RDBS Standard */ + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDS_STD, + radiocfgptr->rds_system); + if(ret == FALSE) + { + print("ConfigureFM : Failed to set RDS std \n"); + return FM_CMD_FAILURE; + } + + /* Set band limit and audio mode to Mono/Stereo */ + tuner.index = 0; + tuner.signal = 0; + + switch(radiocfgptr->band) + { + case FM_US_EU: + tuner.rangelow = REGION_US_EU_BAND_LOW * (TUNE_MULT/1000); + tuner.rangehigh = REGION_US_EU_BAND_HIGH * (TUNE_MULT/1000); + break; + case FM_JAPAN_STANDARD: + tuner.rangelow = REGION_JAPAN_STANDARD_BAND_LOW * (TUNE_MULT/1000); + tuner.rangehigh = REGION_JAPAN_STANDARD_BAND_HIGH * (TUNE_MULT/1000); + break; + case FM_JAPAN_WIDE: + tuner.rangelow = REGION_JAPAN_WIDE_BAND_LOW * (TUNE_MULT/1000); + tuner.rangehigh = REGION_JAPAN_WIDE_BAND_HIGH * (TUNE_MULT/1000); + break; + default: + tuner.rangelow = radiocfgptr->bandlimits.lower_limit * (TUNE_MULT/1000); + tuner.rangehigh = radiocfgptr->bandlimits.upper_limit * (TUNE_MULT/1000); + break; + } + + ret = ioctl(fd_radio,VIDIOC_S_TUNER,&tuner); + if(ret < 0) + { + print("ConfigureFM : Failed to set band limits and audio mode \n"); + return FM_CMD_FAILURE; + } + + /* Set Region */ + radiocfgptr->band = FM_USER_DEFINED; + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_REGION,radiocfgptr->band); + if(ret == FALSE) + { + print("ConfigureFM : Failed to set band\n"); + return FM_CMD_FAILURE; + } + +out : +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("\nConfigure FM Transmitter exit\n"); + else + print("\nConfigure FM Receiver exit\n"); +#endif + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetFrequencyReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Frequency ofreception + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyReceiver +( + uint32 ulfreq +) +{ + int err; + double tune; + struct v4l2_frequency freq_struct; + struct v4l2_tuner tuner; +#ifdef FTM_DEBUG + print2("\nSetFrequency Receiver entry freq = %d\n",(int)ulfreq); +#endif + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + tuner.index = 0; + + err = ioctl(fd_radio,VIDIOC_G_TUNER,&tuner); + if(err < 0) + { + print("SetFrequencyReceiver : Failed to get band limits and audio mode \n"); + return FM_CMD_FAILURE; + } + freq_struct.type = V4L2_TUNER_RADIO; + freq_struct.frequency = (ulfreq) * (TUNE_MULT/1000); + if (freq_struct.frequency >= tuner.rangelow && freq_struct.frequency <= tuner.rangehigh) + { + err = ioctl(fd_radio, VIDIOC_S_FREQUENCY, &freq_struct); + if(err < 0) + { + return FM_CMD_FAILURE; + } + } + else + { + print("SetFrequencyReceiver : frequency out of band limits \n"); + return FM_CMD_DISALLOWED; + } +#ifdef FTM_DEBUG + print("\nSetFrequency Receiver exit\n"); +#endif + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetFrequencyTransmitter + +DESCRIPTION + PFAL specific routine to configure the FM Transmitter's frequency + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyTransmitter +( + uint32 ulfreq +) +{ + int err; + double tune; + struct v4l2_frequency freq_struct; + struct v4l2_control control; + struct v4l2_tuner tuner; +#ifdef FTM_DEBUG + print2("\n SetFrequencyTransmitter() entry : Freq = %d \n",(int)ulfreq); +#endif + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + /* Stop transmitting PS/RT frequency of currently tuned station */ + print2("\n Currently tuned station is : %u \n",fm_global_params.current_station_freq); + if(is_ps_transmitting) + stopTransmitPS(); + if(is_rt_transmitting) + stopTransmitRT(); + + tuner.index = 0; + + err = ioctl(fd_radio,VIDIOC_G_TUNER,&tuner); + if(err < 0) + { + print("SetFrequencyTransmitter : Failed to get band limits and audio mode \n"); + return FM_CMD_FAILURE; + } + + /* Fill up the 'v4l2_frequency' structure */ + freq_struct.type = V4L2_TUNER_RADIO; + freq_struct.frequency = (ulfreq) * (TUNE_MULT/1000); + if (freq_struct.frequency >= tuner.rangelow && freq_struct.frequency <= tuner.rangehigh) + { + err = ioctl(fd_radio, VIDIOC_S_FREQUENCY, &freq_struct); + if(err < 0) + return FM_CMD_FAILURE; + else + print2("\n Frequency : %u \n",ulfreq); + } + else + { + print("SetFrequencyTransmitter : Frequency out of bandlimits\n"); + return FM_CMD_DISALLOWED; + } + +#ifdef FTM_DEBUG + print("\n SetFrequencyTransmitter() exit \n"); +#endif + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetTxPowerLevel + +DESCRIPTION + PFAL specific routine to configure the FM transmitter's power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetTxPowerLevel +( + uint32 ulfreq +) +{ + int err; + struct v4l2_control control; + + /* Set the power level as requested */ + control.id = V4L2_CID_TUNE_POWER_LEVEL; + control.value = FM_TX_PWR_LVL_MAX; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if(err < 0) + { + if( err == -ETIME) + print("\nTimeout to read PHY_TX gain Register\n"); + else + { + print2("\nFailed to set the Power Level for %u\n",ulfreq); + return FM_CMD_FAILURE; + } + } + else + print2("\nSuccessfully set the Power Level for %u\n",ulfreq); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetMuteModeReceiver +( + mute_type mutemode +) +{ + int err,i; + struct v4l2_control control; + print2("SetMuteModeReceiver mode = %d\n",mutemode); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = mutemode; + control.id = V4L2_CID_AUDIO_MUTE; + + for(i=0;i<3;i++) + { + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetMuteMode Success\n"); + return FM_CMD_SUCCESS; + } + } + print2("Set mute mode ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== + +FUNCTION SetSoftMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's soft mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSoftMuteModeReceiver +( + mute_type mutemode +) +{ + int err; + struct v4l2_control control; + print2("SetMuteModeReceiver mode = %d\n",mutemode); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = mutemode; + control.id = V4L2_CID_PRIVATE_IRIS_SOFT_MUTE; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetMuteMode Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set mute mode ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION SetAntenna + +DESCRIPTION + PFAL specific routine to configure the FM receiver's antenna type + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type SetAntenna +( + antenna_type antenna +) +{ + int err; + struct v4l2_control control; + control.value = antenna; + control.id = V4L2_CID_PRIVATE_TAVARUA_ANTENNA; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetAntenna Success\n"); + return FM_CMD_SUCCESS; + } + + print2("Set antenna ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION FmRivaPeekData + +DESCRIPTION + PFAL specific routine to get the data from Riva Memory +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmRivaPeekData +( + fm_riva_peek_word peek_word +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = peek_word.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.value = peek_word.payload_length; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetDataLen Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_PEEK; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + extract_peek_data(); + print("RivaPeek Success\n"); + return FM_CMD_SUCCESS; + } + + print2("RivaPeekData ret = %d\n",err); + return FM_CMD_FAILURE; +} + + +/*=========================================================================== +FUNCTION FmRivaPokeData + +DESCRIPTION + PFAL specific routine to write the data into the Riva Memory +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmRivaPokeData +( + fm_riva_poke_word poke_word +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = poke_word.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.value = poke_word.payload_length; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetDataLen Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_POKE; + control.value = (uint32)(uintptr_t)(&poke_word.data); + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("RivaPoke Success\n"); + return FM_CMD_SUCCESS; + } + + print2("RivaPokeData ret = %d\n",err); + return FM_CMD_FAILURE; +} + + +/*=========================================================================== +FUNCTION FmSSBIPeekData + +DESCRIPTION + PFAL specific routine to get the data from SSBI registers +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmSSBIPeekData +( + fm_ssbi_poke_reg peek_reg +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_PEEK; + control.value = peek_reg.startaddress; + if( control.value == 0x00) + return FM_CMD_FAILURE; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + extract_ssbi_peek_data(); + print2("SSBIPeek Success\n %d",peek_reg.data); + return FM_CMD_SUCCESS; + } + + print2("SSBIPeekData ret = %d\n",err); + return FM_CMD_FAILURE; +} + + +/*=========================================================================== +FUNCTION FmSSBIPokeData + +DESCRIPTION + PFAL specific routine to program the SSBI registers +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmSSBIPokeData +( + fm_ssbi_poke_reg poke_reg +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = poke_reg.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_POKE; + control.value = poke_reg.data; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print2("SSBIPoke Success\n value =%d",poke_reg.data); + return FM_CMD_SUCCESS; + } + + print2("SSBIPokeData ret = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmTxPwrLvlCfg + +DESCRIPTION + PFAL specific routine to configure the FM Tx power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmTxPwrLvlCfg +( + uint8 pwrlvl +) +{ + int err; + struct v4l2_control control; + control.value = pwrlvl; + control.id = V4L2_CID_TUNE_POWER_LEVEL; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if (err >= 0) { + print2("Tx power level set to %d\n", pwrlvl); + return FM_CMD_SUCCESS; + } + print2("Set Tx power level failed = %d\n", err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmTxToneGen + +DESCRIPTION + PFAL specific routine to configure the FM Tx internal tone Generation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmTxToneGen +( + uint8 txTone +) +{ + int err; + struct v4l2_control control; + control.value = txTone; + control.id = V4L2_CID_PRIVATE_IRIS_TX_TONE; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("Set Tx internal tone Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set Tx internal tone = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmRDSGrpcntrs + +DESCRIPTION + PFAL specific routine to get the FM RDS group conuters + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmRDSGrpcntrs +( + uint8 rdsCounters +) +{ + int err; + struct v4l2_control control; + control.value = rdsCounters; + control.id = V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS; + + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + extract_rds_grp_cntr_data(); + print("Read RDS GROUP counters success\n"); + return FM_CMD_SUCCESS; + } + print2("Read RDS GROUP counters = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmDefaultRead + +DESCRIPTION + PFAL specific routine to get the FM Default Values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmDefaultRead +( + ftm_fm_def_data_rd_req defaultRead +) +{ + int err; + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + ext_ctl.id = V4L2_CID_PRIVATE_IRIS_READ_DEFAULT; + ext_ctl.size = sizeof(ftm_fm_def_data_rd_req); + memcpy(ext_ctl.string,(char *)&defaultRead,ext_ctl.size); + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_USER; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + err = ioctl(fd_radio,VIDIOC_G_EXT_CTRLS,&v4l2_ctls); + if(err >= 0) + { + extract_default_read_data(); + print("Read Defaults success\n"); + return FM_CMD_SUCCESS; + } + print2("Read Defaults =%d \n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmDefaultWrite + +DESCRIPTION + PFAL specific routine to write the default values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmDefaultWrite +( + ftm_fm_def_data_wr_req* writedefaults +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + if(writedefaults == NULL) + { + print("\n 'writedefaults' is NULL \n "); + return FM_CMD_FAILURE; + } + ext_ctl.id = V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT; + ext_ctl.size = (writedefaults->length + 2); + ext_ctl.string = (char *)&writedefaults->mode; + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_USER; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + print("\n Entering Write defaults \n"); + + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set Default failed \n"); + return FM_CMD_FAILURE; + } + + return FM_CMD_SUCCESS; + +} + +/*=========================================================================== +FUNCTION FmSetHlSi + +DESCRIPTION + PFAL specific routine to configure the FM receiver's HlSi + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmSetHlSi +( + uint8 hlsi +) +{ + int err; + struct v4l2_control control; + control.value = hlsi; + control.id = V4L2_CID_PRIVATE_IRIS_HLSI; + print2("Setting HLSI to = %d",hlsi); + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("Set HlSi success"); + return FM_CMD_SUCCESS; + } + print2("Set HlSi status = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmSetNotchFilter + +DESCRIPTION + PFAL specific routine to configure the FM receiver's notch filter + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmSetNotchFilter +( + uint8 notch +) +{ + int err; + struct v4l2_control control; + control.value = notch; + control.id = V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER; + print2("Setting Notch filter to = %d",notch); + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("Set Notch filter success"); + return FM_CMD_SUCCESS; + } + print2("Set Notch filter status = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION SetStereoModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Audio mode on the + frequency tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetStereoModeReceiver +( + stereo_type stereomode +) +{ + struct v4l2_tuner tuner; + int err; + print2("SetStereoModeReceiver stereomode = %d \n",stereomode); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + tuner.index = 0; + err = ioctl(fd_radio, VIDIOC_G_TUNER, &tuner); + print3("Get stereo mode ret = %d tuner.audmode = %d\n",err,tuner.audmode); + if(err < 0) + return FM_CMD_FAILURE; + +/*There is a discrepancy between V4L2 macros and FTM/HCI +Interface documentation. The stereo/mono settings are swapped +In FTM/HCI documentation. So we are providing a work around by +Swapping the mono/stereo settings here*/ + + tuner.audmode = (!stereomode); + err = ioctl(fd_radio, VIDIOC_S_TUNER, &tuner); + print2("Set stereo mode ret = %d\n",err); + if(err < 0) + return FM_CMD_FAILURE; + print("SetStereoMode Success\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetStationParametersReceiver + +DESCRIPTION + PFAL specific routine to get the station parameters ofthe Frequency at + which the Radio receiver is tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetStationParametersReceiver +( + fm_station_params_available* configparams +) +{ + int i; + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + configparams->current_station_freq = fm_global_params.current_station_freq; + configparams->service_available = fm_global_params.service_available; + + struct v4l2_tuner tuner; + tuner.index = 0; + tuner.signal = 0; + if(ioctl(fd_radio, VIDIOC_G_TUNER, &tuner) < 0) + return FM_CMD_FAILURE; + + configparams->rssi = tuner.signal; + configparams->stype = fm_global_params.stype; + configparams->rds_sync_status = fm_global_params.rds_sync_status; + + struct v4l2_control control; + control.id = V4L2_CID_AUDIO_MUTE; + + for(i=0;i<3;i++) + { + int err = ioctl(fd_radio,VIDIOC_G_CTRL,&control); + if(err >= 0) + { + configparams->mute_status = control.value; + return FM_CMD_SUCCESS; + } + } + + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION SetRdsOptionsReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsOptionsReceiver +( + fm_rds_options rdsoptions +) +{ + int ret; + print("SetRdsOptionsReceiver\n"); + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK, + rdsoptions.rds_group_mask); + if(ret == FALSE) + { + print2("SetRdsOptionsReceiver Failed to set RDS group options = %d\n",ret); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF, + rdsoptions.rds_group_buffer_size); + if(ret == FALSE) + { + print2("SetRdsOptionsReceiver Failed to set RDS group options = %d\n",ret); + return FM_CMD_FAILURE; + } + + /*Chnage Filter not supported */ + print("SetRdsOptionsReceiver<\n"); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetRdsGroupProcReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS group proc options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsGroupProcReceiver +( + uint32 rdsgroupoptions +) +{ + int ret; + print("SetRdsGroupProcReceiver\n"); + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC, + rdsgroupoptions); + if(ret == FALSE) + { + print2("SetRdsGroupProcReceiver Failed to set RDS proc = %d\n",ret); + return FM_CMD_FAILURE; + } + + print("SetRdsGroupProcReceiver<\n"); + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION SetPowerModeReceiver + +DESCRIPTION + PFAL specific routine to configure the power mode of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetPowerModeReceiver +( + uint8 powermode +) +{ + struct v4l2_control control; + int i,err; + print2("SetPowerModeReceiver mode = %d\n",powermode); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = powermode; + control.id = V4L2_CID_PRIVATE_TAVARUA_LP_MODE; + + for(i=0;i<3;i++) + { + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetPowerMode Success\n"); + return FM_CMD_SUCCESS; + } + } + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION SetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to configure the signal threshold ofFM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSignalThresholdReceiver +( + uint8 signalthreshold +) +{ + struct v4l2_control control; + int i,err; + print2("SetSignalThresholdReceiver threshold = %d\n",signalthreshold); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = signalthreshold; + control.id = V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH; + + for(i=0;i<3;i++) + { + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("SetSignalThresholdReceiver Success\n"); + return FM_CMD_SUCCESS; + } + } + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION GetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to get the signal threshold of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetSignalThresholdReceiver +( + uint8* signalthreshold +) +{ + struct v4l2_control control; + int i,err; + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.id = V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH; + + for(i=0;i<3;i++) + { + err = ioctl(fd_radio,VIDIOC_G_CTRL,&control); + if(err >= 0) + { + print2("GetSignalThresholdReceiver Success = %d\n",control.value); + *signalthreshold = control.value; + return FM_CMD_SUCCESS; + } + } + + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION GetRSSILimits + +DESCRIPTION + PFAL specific routine to print the RSSI limts ofFM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRSSILimits +( +) +{ + int limits[] ={0,100}; + + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION GetPSInfoReceiver + +DESCRIPTION + PFAL specific routine to print the PS info ofcurrent frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetPSInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetRTInfoReceiver + +DESCRIPTION + PFAL specific routine to print the Radio text info ofcurrent frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRTInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetAFInfoReceiver + +DESCRIPTION + PFAL specific routine to print the AF list for current frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetAFInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SearchStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationsReceiver +( +fm_search_stations searchstationsoptions +) +{ + int err,i; + struct v4l2_control control; + struct v4l2_hw_freq_seek hwseek; + boolean ret; + print("SearchStationsReceiver\n"); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchstationsoptions.search_mode); + if(ret == FALSE) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SCANDWELL, + searchstationsoptions.dwell_period); + if(ret == FALSE) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + if (searchstationsoptions.search_dir) + searchstationsoptions.search_dir = SRCH_DIR_UP; + else + searchstationsoptions.search_dir = SRCH_DIR_DOWN; + + hwseek.seek_upward = searchstationsoptions.search_dir; + hwseek.type = V4L2_TUNER_RADIO; + err = ioctl(fd_radio,VIDIOC_S_HW_FREQ_SEEK,&hwseek); + + if(err < 0) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + print("SearchRdsStationsReceiver<\n"); + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION SearchRDSStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver with a specific program type and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchRdsStationsReceiver +( +fm_search_rds_stations searchrdsstationsoptions +) +{ + int i,err; + boolean ret; + struct v4l2_control control; + struct v4l2_hw_freq_seek hwseek; + + print("SearchRdsStationsReceiver>\n"); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchrdsstationsoptions.search_mode); + if(ret == FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SCANDWELL, + searchrdsstationsoptions.dwell_period); + if(ret == FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY, + searchrdsstationsoptions.program_type); + if(ret == FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl(fd_radio,V4L2_CID_PRIVATE_TAVARUA_SRCH_PI, + searchrdsstationsoptions.program_id); + if(ret == FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + hwseek.seek_upward = searchrdsstationsoptions.search_dir; + hwseek.type = V4L2_TUNER_RADIO; + err = ioctl( fd_radio, VIDIOC_S_HW_FREQ_SEEK,&hwseek); + + if(err < 0) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + print("SearchRdsStationsReceiver<\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SearchStationListReceiver + +DESCRIPTION + PFAL specific routine to search for stations with a specific mode of + informaation like WEAK,STRONG,STRONGEST etc + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationListReceiver +( +fm_search_list_stations searchliststationsoptions +) +{ + int i,err; + boolean ret; + struct v4l2_control control; + struct v4l2_hw_freq_seek hwseek; + + print("SearchStationListReceiver>\n"); + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + ret = set_v4l2_ctrl( fd_radio, V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchliststationsoptions.search_mode); + if(ret == FALSE) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl( fd_radio, V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT, + searchliststationsoptions.srch_list_max); + if(ret == FALSE) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = set_v4l2_ctrl( fd_radio, V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY, + searchliststationsoptions.program_type); + if(ret == FALSE) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + + hwseek.seek_upward = searchliststationsoptions.search_dir; + hwseek.type = V4L2_TUNER_RADIO; + err = ioctl( fd_radio, VIDIOC_S_HW_FREQ_SEEK,&hwseek); + + if(err < 0) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + print("SearchStationListReceiver<\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION + +DESCRIPTION + PFAL specific routine to cancel the ongoing search operation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type CancelSearchReceiver +( +) +{ + struct v4l2_control control; + boolean ret; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + ret = set_v4l2_ctrl( fd_radio, V4L2_CID_PRIVATE_TAVARUA_SRCHON,0); + if(ret == FALSE) + { + return FM_CMD_FAILURE; + } + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetSINRSamples + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR sample + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRSamples +( + +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_SINR_SAMPLES; + err = ioctl(fd_radio, VIDIOC_G_CTRL, &control); + if( err < 0 ) + { + print("Failed to get the SINR samples"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.sinr_samples = control.value; + print2("Successfully get the SINR samples %d\n", control.value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetSINRSamples + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR sample + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSINRSamples +( + uint8 sinr_sample +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_SINR_SAMPLES; + control.value = sinr_sample; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if( err < 0 ) + { + print("Failed to set the SINR samples\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the SINR samples %d\n", sinr_sample); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION GetSINRThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRThreshold +( + +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_SINR_THRESHOLD; + err = ioctl(fd_radio, VIDIOC_G_CTRL, &control); + if( err < 0 ) + { + print("Failed to get the SINR threshold\n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.sinr_threshold = control.value; + print2("Successfully get the SINR threshold %d\n", control.value); + return FM_CMD_SUCCESS; + } +} + + +/*=========================================================================== +FUNCTION SetSINRThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSINRThreshold +( + char sinr_th +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_SINR_THRESHOLD; + control.value = sinr_th; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if( err < 0 ) + { + print("Failed to set the SINR threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the SINR threshold %d\n", sinr_th); + return FM_CMD_SUCCESS; + } +} + + +/*=========================================================================== +FUNCTION GetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's On channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOnChannelThreshold +( + +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD; + err = ioctl(fd_radio, VIDIOC_G_CTRL, &control); + if( err < 0 ) + { + print("Failed to get the On channel threshold \n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.On_channel_threshold = control.value; + print2("Successfully get the On channel threshold %d\n", control.value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's On channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOnChannelThreshold +( + uint8 on_channel_th +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD; + control.value = on_channel_th; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if( err < 0 ) + { + print("Failed to set the On channel threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the On channel threshold %d\n", on_channel_th); + return FM_CMD_SUCCESS; + } +} +/*=========================================================================== +FUNCTION GetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's Off channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOffChannelThreshold +( + +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD; + err = ioctl(fd_radio, VIDIOC_G_CTRL, &control); + if( err < 0 ) + { + print("Failed to get the Off channel threshold \n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.Off_channel_threshold = control.value; + print2("Successfully get the Off channel threshold %d\n", control.value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's Off channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOffChannelThreshold +( + uint8 off_channel_th +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD; + control.value = off_channel_th; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if( err < 0 ) + { + print("Failed to set the Off channel threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the Off channel threshold %d\n", off_channel_th); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION get_fm_i2c_path + +DESCRIPTION + Helper function to get the path of i2c based on the board + +DEPENDENCIES + NIL + +RETURN VALUE + Path to the i2c device. NULL in case of failure. + +SIDE EFFECTS + None + +===========================================================================*/ + +static char* get_fm_i2c_path( void ) +{ + char *fm_i2c_path = NULL; + char board_platform_type[92]; // max possible length for 'value' from property_get() + property_get("ro.board.platform", board_platform_type, "default"); + print2("ro.board.platform %s \n", board_platform_type); + if(strcasestr(board_platform_type, "default")) + { + print("unable to determine the board platform type \n"); + return NULL; + } + if(strcasestr(board_platform_type, "msm8660")) + { + fm_i2c_path = (char *)fm_i2c_path_8660; + } + else if(strcasestr(board_platform_type, "msm7630_surf")) + { + fm_i2c_path = (char *)fm_i2c_path_7x30; + } + else if(strcasestr(board_platform_type, "msm7627a")) + { + fm_i2c_path = (char *)fm_i2c_path_7627a; + } + if(fm_i2c_path != NULL) + print2("I2c device path is %s \n", fm_i2c_path); + + return fm_i2c_path; +} + + +/*=========================================================================== +FUNCTION FmBusWriteReceiver + +DESCRIPTION + PFAL specific routine to program the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusWriteReceiver +( +fm_i2c_params writeparams +) +{ + int fd_i2c; + int ret; + char *i2cdevice = get_fm_i2c_path(); + if (i2cdevice == NULL) + { + print("== I2C device path not available \n"); + return FM_CMD_FAILURE; + } + fd_i2c = open(i2cdevice, O_RDWR); + print("FmBusWriteReceiver >\n"); + if(fd_i2c < 0) + return FM_CMD_FAILURE; + ret = i2c_write( fd_i2c, writeparams.offset, writeparams.data, + writeparams.payload_length, writeparams.slaveaddress); + if (ret < 0) + { + print(" i2c_write failed to Write the data \n"); + close(fd_i2c); + return FM_CMD_FAILURE; + } + print2("== I2C Write SLAVE_ADDR = 0x%x\n",writeparams.slaveaddress); + print2("== I2C reg = 0x%x ===\n",writeparams.offset); + print2("== I2C data = 0x%x \n",writeparams.data[0]); + + close(fd_i2c); + print("FmBusWriteReceiver <\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION FmBusReadReceiver + +DESCRIPTION + PFAL specific routine to read the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusReadReceiver +( +fm_i2c_params *readparams +) +{ + int fd_i2c; + int ret; + char *i2cdevice = get_fm_i2c_path(); + if (i2cdevice == NULL) + { + print("== I2C device path not available \n"); + return FM_CMD_FAILURE; + } + fd_i2c = open(i2cdevice, O_RDWR); + print("FmBusReadReceiver >\n"); + ret = i2c_read( fd_i2c, readparams->offset, readparams->data, + readparams->payload_length, readparams->slaveaddress); + if (ret < 0) + { + print(" i2c_read failed to read the data \n"); + close(fd_i2c); + return FM_CMD_FAILURE; + } + close(fd_i2c); + print2("== I2C Read SLAVE_ADDR = 0x%x\n",readparams->slaveaddress); + print2("== I2C reg = 0x%x ===\n",readparams->offset); + print2("== I2C data = 0x%x \n",readparams->data[0]); + + print("FmBusReadReceiver <\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== + +FUNCTION ftm_fm_run_mm + +DESCRIPTION + This function is used to run mm-audio-ftm. + +DEPENDENCIES + none + +===========================================================================*/ +void ftm_fm_run_mm(void) { + pid_t pid; + int err = 1; + + printf("entered ftm_fm_run_mm\n"); + pid = fork(); + + if (!pid) { + err = execl(mm_audio_path, mm_audio_path, NULL); + printf("mm module error %d\n", err); + exit(0); + } else if (pid < 0) { + printf("could not create child process to execute mm audio module\n"); + } + return; +} + +/*=========================================================================== + +FUNCTION ftm_fm_audio + +DESCRIPTION + This function is used to load the target based config file and + set the audio output and volume. + +DEPENDENCIES + none + +===========================================================================*/ +fm_cmd_status_type ftm_fm_audio(uint8 source, uint8 volume) { + + char *cmd = NULL; + char vlm[4]; + int sound_card_fd = -1; + char sound_card_name[sound_card_name_len]; + char *buffer; + size_t len; + ssize_t ret; + int tmp; + fm_cmd_status_type status = FM_CMD_FAILURE; + int prop_ret = 0; + char bt_soc_type[PROPERTY_VALUE_MAX]; + + printf("Enter ftm_fm_audio\n"); + memset(sound_card_name, 0, sizeof(sound_card_name)); + cmd = (char*) malloc(CMD_len * sizeof(char)); + if (!cmd) { + printf("memory allocation failed\n"); + goto failure; + } + memset(cmd, 0, CMD_len); + + if (strlcat(cmd, "-tc ", CMD_len) >= CMD_len) + goto failure; + + printf("string = %s \n",cmd); + printf("audio_output = %d\n", source); + buffer = source ? "51 -v " : "74 -v "; + if (strlcat(cmd, buffer, CMD_len) >= CMD_len) + goto failure; + + printf("string = %s \n",cmd); + tmp = snprintf(vlm, sizeof(vlm), "%d", volume); + if (tmp < 0 || sizeof (vlm) <= (size_t)tmp) + goto failure; + if (strlcat(cmd, vlm, CMD_len) >= CMD_len) + goto failure; + + sound_card_fd = open("/proc/asound/card0/id", O_RDWR); + if (sound_card_fd < 0) { + printf("failed to open sound card. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + + len = sound_card_name_len - 1; + while (len > 0) { + ret = read (sound_card_fd, + &sound_card_name[sound_card_name_len - 1 - len], len); + if (ret < 0) { + printf("Failed to read sound card name. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + if (!ret) { + if(!sound_card_name[0]) + goto failure; + else + break; + } + len -= ret; + } + printf("sound_card_name = %s\n", sound_card_name); + printf("string = %s \n",cmd); + + ftm_audio_fd = open("/data/vendor/misc/audio/ftm_commands", O_RDWR); + if (ftm_audio_fd < 0) { + printf("Failed to open ftm_commands with write. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + printf(" writing config path\n"); + prop_ret = property_get("qcom.bluetooth.soc", bt_soc_type, NULL); + if (prop_ret != 0) { + printf("qcom.bluetooth.soc set to %s\n", bt_soc_type); + if (!strncasecmp(bt_soc_type, "rome", sizeof("rome"))) { + buffer = audio_config; + len = config_len; + goto skip; + } + } + if (strstr(sound_card_name, "tasha")) { + printf("using external codec\n"); + buffer = (char *)ext_audio_config; + len = ext_config_len; + } else { + printf("using internal codec\n"); + buffer = (char *)audio_config; + len = config_len; + } + +skip: + while (len > 0) { + ret = write(ftm_audio_fd, buffer, len); + if (ret < 0) { + printf("Failed to write config_file. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + len -= ret; + buffer += ret; + } + printf("done write config path\n"); + sleep(1); + printf("writing command for path = 0x%zx \n", strlen(cmd)); + len = strlen(cmd) + 1; + + buffer = cmd; + while (len > 0) { + ret = write(ftm_audio_fd, buffer, strlen(cmd) + 1); + if (ret < 0) { + printf("Failed to write cmd. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + len -= ret; + buffer += ret; + } + printf("done write command for path\n"); + status = FM_CMD_SUCCESS; + // fall through intentional +failure: + if (cmd) + free(cmd); + if (sound_card_fd > 0) + close(sound_card_fd); + if (ftm_audio_fd > 0) { + close(ftm_audio_fd); + ftm_audio_fd = -1; + } + return status; +} + diff --git a/qca/ftm/src/ftm_fm_pfal_linux_3990.c b/qca/ftm/src/ftm_fm_pfal_linux_3990.c new file mode 100644 index 000000000..88ec7da15 --- /dev/null +++ b/qca/ftm/src/ftm_fm_pfal_linux_3990.c @@ -0,0 +1,3338 @@ +/*========================================================================== +* +* Description +* Platform specific routines to program FM over Uart transport +* Copyright (c) 2010-2017 Qualcomm Technologies, Inc. +* All Rights Reserved. +* Confidential and Proprietary - Qualcomm Technologies, Inc. +* +*===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +3/10/16 ssugasi Add FTM support for FM module for uart based chipsets +==========================================================================*/ + +#include "ftm_fm_pfal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ANDROID +#include +#endif +#include +#include +#include +#include +#include +#include "ftm_common.h" +#include "radio-helium-commands.h" +#include +#define BIT16 (1<<16) + +/* Multiplying factor to convert to Radio freqeuncy */ +#define TUNE_MULT 16000 +/* Constant to request for Radio Events */ +#define EVENT_LISTEN 1 +/* 1000 multiplier */ +#define MULTIPLE_1000 1000 +/* Tavaura I2C address */ +int SLAVE_ADDR = 0x2A; +/* Tavaura I2C statu register*/ +#define INTSTAT_0 0x0 +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(*a)) +/* Debug Macro */ +#define FTM_DEBUG +#ifdef FTM_DEBUG +#define print(x) printf(x) +#define print2(x,y) printf(x,y) +#define print3(x,y,z) printf(x,y,z) +#else +#define print(x) +#define print2(x,y) +#define print3(x,y,z) +#endif +typedef unsigned char boolean; + +#define TAVARUA_BUF_PS_RDS 3 +#define V4L2_CID_PRIVATE_TAVARUA_REGION 0x08000007 +#define V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT 0x08000015 +#define V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME 0x08000016 +#define V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT 0x08000017 +#define V4L2_CID_PRIVATE_TAVARUA_STATE 0x08000004 +#define V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH 0x8000029 +#define V4L2_CID_PRIVATE_TAVARUA_RDSON 0x0800000F +#define V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC 0x08000010 +#define V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK 0x08000006 +#define V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF 0x08000013 +#define V4L2_CID_PRIVATE_TAVARUA_ANTENNA 0x08000012 +#define V4L2_CID_PRIVATE_TAVARUA_RDSON 0x0800000F +#define V4L2_CID_PRIVATE_TAVARUA_EMPHASIS 0x0800000C +#define V4L2_CID_PRIVATE_TAVARUA_SPACING 0x0800000E +#define V4L2_CID_PRIVATE_TAVARUA_RDS_STD 0x0800000D +#define V4L2_CID_PRIVATE_TAVARUA_LP_MODE 0x08000011 +#define V4L2_CID_PRIVATE_TAVARUA_SRCHMODE 0x08000001 +#define V4L2_CID_PRIVATE_TAVARUA_SCANDWELL 0x08000002 +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_PI 0x0800000A +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT 0x0800000B +#define V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY 0x08000009 +#define V4L2_CID_PRIVATE_TAVARUA_SRCHON 0x08000003 +#define V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD 0x800002D +#define V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD 0x800002E +#define V4L2_CID_PRIVATE_SINR_THRESHOLD 0x800002F +#define V4L2_CID_PRIVATE_SINR_SAMPLES 0x8000030 +#define V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH 0x08000008 +#define V4L2_CID_PRV_ENABLE_SLIMBUS 0x00980940 +#define SRCH_DIR_UP (0) +#define SRCH_DIR_DOWN (1) + +#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */ +#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */ +#define RDS_Tx 0x80 +const char* fm_i2c_path_8660 = "/dev/i2c-4"; +const char* fm_i2c_path_7x30 = "/dev/i2c-2"; +const char* fm_i2c_path_7627a = "/dev/i2c-1"; +/* To get the current status of PS/RT transmission */ +volatile unsigned char is_rt_transmitting = 0; +volatile unsigned char is_ps_transmitting = 0; +int ftm_audio_fd = -1; +const char *const audio_config = "-c /vendor/etc/ftm_test_config"; +const unsigned int CMD_len = 16; +const int config_len = 31; +const int ext_config_len = 39; +const int sound_card_len = 200; +const char *const mm_audio_path = "/vendor/bin/mm-audio-ftm"; +char *FM_LIBRARY_NAME = "fm_helium.so"; +char *FM_LIBRARY_SYMBOL_NAME = "FM_HELIUM_LIB_INTERFACE"; +void *lib_handle; + +fm_config_data * fmconfig_ptr; +typedef void (*enb_result_cb)(); +typedef void (*tune_rsp_cb)(int Freq); +typedef void (*seek_rsp_cb)(int Freq); +typedef void (*scan_rsp_cb)(); +typedef void (*srch_list_rsp_cb)(uint16_t *scan_tbl); +typedef void (*stereo_mode_cb)(boolean status); +typedef void (*rds_avl_sts_cb)(boolean status); +typedef void (*af_list_cb)(uint16_t *af_list); +typedef void (*rt_cb)(char *rt); +typedef void (*ps_cb)(char *ps); +typedef void (*oda_cb)(); +typedef void (*rt_plus_cb)(char *rt_plus); +typedef void (*ert_cb)(char *ert); +typedef void (*disable_cb)(); +typedef void (*callback_thread_event)(unsigned int evt); +typedef void (*rds_grp_cntrs_cb)(char *rds_params); +typedef void (*rds_grp_cntrs_ext_cb)(char *rds_params); +typedef void (*fm_peek_cb)(char *peek_rsp); +typedef void (*fm_ssbi_peek_cb)(char *ssbi_peek_rsp); +typedef void (*fm_agc_gain_cb)(char *agc_gain_rsp); +typedef void (*fm_ch_det_th_cb)(char *ch_det_rsp); +typedef void (*fm_sig_thr_cb) (int val, int status); +typedef void (*fm_get_ch_det_thrs_cb) (int val, int status); +typedef void (*fm_def_data_rd_cb) (int val, int status); +typedef void (*fm_get_blnd_cb) (int val, int status); +typedef void (*fm_set_ch_det_thrs_cb) (int status); +typedef void (*fm_def_data_wrt_cb) (int status); +typedef void (*fm_set_blnd_cb) (int status); +typedef void (*fm_get_stn_prm_cb) (int val, int status); +typedef void (*fm_get_stn_dbg_prm_cb) (int val, int status); +typedef void (*fm_ecc_evt_cb)(char *ecc_rsp); +typedef void (*fm_enable_sb_cb) (int status); + +/* enum to montior the Power On status */ +typedef enum +{ + INPROGRESS, + COMPLETE +}poweron_status; + +boolean cmd_queued = FALSE; +/* Resourcse Numbers for Rx/TX */ +int FM_RX = 1; +int FM_TX = 2; +/* Boolean to control the power down sequence */ +volatile boolean power_down = FALSE; +/* V4L2 radio handle */ +int fd_radio = -1; +/* FM asynchornous thread to perform the long running ON */ +pthread_t fm_interrupt_thread,fm_on_thread; +/* Prototype ofFM ON thread */ +void *(ftm_on_long_thread)(void *ptr); +/* Global state ofthe FM task */ +fm_station_params_available fm_global_params; + +volatile poweron_status poweron; + +int chipVersion = 0; +extern volatile fm_power_state fmPowerState; +static char transport[PROPERTY_VALUE_MAX]; + +typedef struct { + size_t size; + enb_result_cb enabled_cb; + tune_rsp_cb tune_cb; + seek_rsp_cb seek_cmpl_cb; + scan_rsp_cb scan_next_cb; + srch_list_rsp_cb srch_list_cb; + stereo_mode_cb stereo_status_cb; + rds_avl_sts_cb rds_avail_status_cb; + af_list_cb af_list_update_cb; + rt_cb rt_update_cb; + ps_cb ps_update_cb; + oda_cb oda_update_cb; + rt_plus_cb rt_plus_update_cb; + ert_cb ert_update_cb; + disable_cb disabled_cb; + rds_grp_cntrs_cb rds_grp_cntrs_rsp_cb; + rds_grp_cntrs_ext_cb rds_grp_cntrs_ext_rsp_cb; + fm_peek_cb fm_peek_rsp_cb; + fm_ssbi_peek_cb fm_ssbi_peek_rsp_cb; + fm_agc_gain_cb fm_agc_gain_rsp_cb; + fm_ch_det_th_cb fm_ch_det_th_rsp_cb; + fm_ecc_evt_cb fm_ext_country_code_cb; + callback_thread_event thread_evt_cb; + fm_sig_thr_cb fm_get_sig_thres_cb; + fm_get_ch_det_thrs_cb fm_get_ch_det_thr_cb; + fm_def_data_rd_cb fm_def_data_read_cb; + fm_get_blnd_cb fm_get_blend_cb; + fm_set_ch_det_thrs_cb fm_set_ch_det_thr_cb; + fm_def_data_wrt_cb fm_def_data_write_cb; + fm_set_blnd_cb fm_set_blend_cb; + fm_get_stn_prm_cb fm_get_station_param_cb; + fm_get_stn_dbg_prm_cb fm_get_station_debug_param_cb; + fm_enable_sb_cb fm_enable_slimbus_cb; +} fm_vendor_callbacks_t; + +typedef struct { + int (*hal_init)(fm_vendor_callbacks_t *p_cb); + int (*set_fm_ctrl)(int ioctl, int val); + int (*get_fm_ctrl) (int ioctl, int* val); +} fm_interface_t; + +void fm_enabled_cb() { + ALOGE("Entered %s", __func__); +} + +void fm_tune_cb(int Freq) +{ + ALOGE("TUNE:Freq:%d", Freq); + fm_global_params.current_station_freq =Freq; +} + +void fm_seek_cmpl_cb(int Freq) +{ + ALOGE("SEEK_CMPL: Freq: %d", Freq); + fm_global_params.current_station_freq =Freq; +} + +void fm_scan_next_cb() +{ + ALOGE("SCAN_NEXT"); +} + +void fm_srch_list_cb(uint16_t *scan_tbl) +{ + ALOGE("SRCH_LIST"); +} + +void fm_stereo_status_cb(boolean stereo) +{ + ALOGE("STEREO: %d", stereo); + fm_global_params.stype = stereo; +} + +void fm_rds_avail_status_cb(boolean rds_avl) +{ + ALOGE("fm_rds_avail_status_cb: %d", rds_avl); + fm_global_params.rds_sync_status = rds_avl; +} + +void fm_rt_update_cb(char *rt) +{ + ALOGE("Entered %s", __func__); + int radiotext_size = (int)(rt[0] & 0xFF); + fm_global_params.fm_rt_length = radiotext_size; + print2("radio text size = %d\n",fm_global_params.fm_rt_length); + fm_global_params.pgm_id = (((rt[2] & 0xFF) << 8) | (rt[3] & 0xFF)); + fm_global_params.pgm_type = (int)( rt[1] & 0x1F); + memset(fm_global_params.radio_text,0x0,MAX_RDS_RT_LENGTH); + memcpy(fm_global_params.radio_text,&rt[5],radiotext_size); +} + +void fm_ps_update_cb(char *buf) +{ + ALOGE("Entered %s", __func__); + int num_of_ps = (int)(buf[0] & 0xFF); + int ps_services_len = ((int )((num_of_ps*8) + 5)) - 5; + fm_global_params.fm_ps_length = ps_services_len; + fm_global_params.pgm_id = (((buf[2] & 0xFF) << 8) | (buf[3] & 0xFF)); + fm_global_params.pgm_type = (int)( buf[1] & 0x1F); + memset(fm_global_params.pgm_services,0x0,MAX_RDS_PS_LENGTH); + memcpy(fm_global_params.pgm_services,&buf[5],ps_services_len); + fm_global_params.pgm_services[ps_services_len] = '\0'; + print2("Pid = %d\n",fm_global_params.pgm_id); + print2("Ptype = %d\n",fm_global_params.pgm_type); + print2("PS name %s\n",fm_global_params.pgm_services); + +} +void fm_oda_update_cb() +{ + ALOGD("ODA_EVT"); +} + +void fm_af_list_update_cb(uint16_t *af_list) +{ + ALOGD("Entered %s", __func__); + +} +void fm_rt_plus_update_cb(char *rt_plus) +{ + ALOGD("Entered %s", __func__); +} + +void fm_ert_update_cb(char *ert) +{ + ALOGD("Entered %s", __func__); +} +void fm_disabled_cb() +{ + ALOGD("Entered %s", __func__); +} + +void rds_grp_cntrs_rsp_cb(char *rds_grp_cntr_buff) +{ + ALOGV("Entered %s", __func__); + struct fm_rds_grp_cntrsparams *response = (struct fm_rds_grp_cntrsparams *)rds_grp_cntr_buff; + ALOGI("copy RDS grp counter response "); + memcpy((void*)&fm_global_params.rds_group_counters,(void*)response,RDS_GRP_CNTRS_SIZE); + pthread_mutex_lock(&fm_event_lock); + pthread_cond_signal(&fm_event_cond); + pthread_mutex_unlock(&fm_event_lock); + ALOGD("Exit %s", __func__); +} +void rds_grp_cntrs_ext_rsp_cb(char * rds_grp_cntr_buff) +{ + ALOGD("rds_grp_cntrs_ext_rsp_cb"); + struct fm_rds_grpcntrs_extendedparams *response = (struct fm_rds_grpcntrs_extendedparams*)rds_grp_cntr_buff; + memcpy((void*)&fm_global_params.rds_group_counters_extended,(void*)response,sizeof(fm_rds_grpcntrs_extendedparams)); + ALOGV(" response totalRdsSyncLoss:%d\n totalRdsNotSync:%d\n totalRdsSyncInt:%d\n ", + fm_global_params.rds_group_counters_extended.totalRdsNotSync, + fm_global_params.rds_group_counters_extended.totalRdsSyncInt, + fm_global_params.rds_group_counters_extended.totalRdsSyncLoss); + ALOGV("Exit %s", __func__); +} + +void fm_peek_rsp_cb(char *peek_rsp) { + struct fm_riva_poke_word *responce = (struct fm_riva_poke_word *)peek_rsp; + memcpy((void*)&fm_global_params.riva_data_access_params, + (void*)responce,sizeof(struct fm_riva_poke_word)); +} + +void fm_ssbi_peek_rsp_cb(char *ssbi_peek_rsp){ + fm_global_params.ssbi_peek_data = ssbi_peek_rsp[0]; +} + +void fm_agc_gain_rsp_cb(char *agc_gain_Resp){ + ALOGD("Entered %s", __func__); + struct fm_set_get_reset_agc_params *response =( + struct fm_set_get_reset_agc_params *)agc_gain_Resp; + memcpy((void*)&fm_global_params.set_get_reset_agc_params, + (void*)response, sizeof(struct fm_set_get_reset_agc_params)); + + ALOGV("Get AGC gain state success\n"); + ALOGV("Current state: %x\nUcGainStateChng1: %x\nUcGainStateChng2: %x\nUcGainStateChng3: %x", + fm_global_params.set_get_reset_agc_params.ucCurrentGainState, + fm_global_params.set_get_reset_agc_params.ucGainStateChange1, + fm_global_params.set_get_reset_agc_params.ucGainStateChange2, + fm_global_params.set_get_reset_agc_params.ucGainStateChange3); +} + +void fm_ch_det_th_rsp_cb(char *ch_det_rsp){ + ALOGD("Entered %s", __func__); +} + +void fm_thread_evt_cb(unsigned int event) +{ + ALOGE("Entered %s", __func__); +} + + static void fm_get_sig_thres_cb(int val, int status) +{ + ALOGD("Get signal Thres callback"); +} + +static void fm_get_ch_det_thr_cb(int val, int status) +{ + ALOGI("fm_get_ch_det_thr_cb"); +} + +static void fm_set_ch_det_thr_cb(int status) +{ + ALOGE("fm_set_ch_det_thr_cb"); +} + +static void fm_def_data_read_cb(int val, int status) +{ + ALOGE("fm_def_data_read_cb"); +} + +static void fm_def_data_write_cb(int status) +{ + ALOGE("fm_def_data_write_cb"); +} + +static void fm_get_blend_cb(int val, int status) +{ + ALOGE("fm_get_blend_cb"); +} + +static void fm_set_blend_cb(int status) +{ + ALOGE("fm_set_blend_cb"); +} + +static void fm_get_station_param_cb(int val, int status) +{ + if (status == 0) + fm_global_params.rssi = val; + else + fm_global_params.rssi = 0; + pthread_mutex_lock(&fm_event_lock); + pthread_cond_signal(&fm_event_cond); + pthread_mutex_unlock(&fm_event_lock); + ALOGD("fm_get_station_param_cb rssi =%d\n",fm_global_params.rssi); +} + +static void fm_get_station_debug_param_cb(int val, int status) +{ + ALOGE("fm_get_station_debug_param_cb"); +} + +static void fm_ext_country_code_cb(char *ecc_rsp) +{ + ALOGD("Entered %s", __func__); +} + +static void fm_enable_slimbus_cb(int status) +{ + ALOGD("%s status %d", __func__, status); + pthread_mutex_lock(&fm_event_lock); + pthread_cond_signal(&fm_event_cond); + pthread_mutex_unlock(&fm_event_lock); +} + +fm_interface_t *vendor_interface; +static fm_vendor_callbacks_t fm_callbacks = { + sizeof(fm_callbacks), + fm_enabled_cb, + fm_tune_cb, + fm_seek_cmpl_cb, + fm_scan_next_cb, + fm_srch_list_cb, + fm_stereo_status_cb, + fm_rds_avail_status_cb, + fm_af_list_update_cb, + fm_rt_update_cb, + fm_ps_update_cb, + fm_oda_update_cb, + fm_rt_plus_update_cb, + fm_ert_update_cb, + fm_disabled_cb, + rds_grp_cntrs_rsp_cb, + rds_grp_cntrs_ext_rsp_cb, + fm_peek_rsp_cb, + fm_ssbi_peek_rsp_cb, + fm_agc_gain_rsp_cb, + fm_ch_det_th_rsp_cb, + fm_ext_country_code_cb, + fm_thread_evt_cb, + fm_get_sig_thres_cb, + fm_get_ch_det_thr_cb, + fm_def_data_read_cb, + fm_get_blend_cb, + fm_set_ch_det_thr_cb, + fm_def_data_write_cb, + fm_set_blend_cb, + fm_get_station_param_cb, + fm_get_station_debug_param_cb, + fm_enable_slimbus_cb +}; + +/*=========================================================================== +FUNCTION extract_rds_grp_cntr_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a Read Rds Group counters command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data strutures member rds_group_counters + +===========================================================================*/ + +void extract_rds_grp_cntr_data() +{ + uint8 buf[RDS_GRP_CNTRS_SIZE]; + struct RDSCntrsParams *responce = (struct RDSCntrsParams *)buf; + memcpy((void*)&fm_global_params.rds_group_counters,(void*)responce,sizeof(buf)); +} +/*=========================================================================== +FUNCTION extract_default_read_data + +DESCRIPTION + Helper routine to read the data from the V4L2 buffer + following a defaultRead command complete + +DEPENDENCIES + NIL + +RETURN VALUE + void + +SIDE EFFECTS + Updates the Global data struture member rd_default + +===========================================================================*/ + +void extract_default_read_data() +{ + print("Not implemented"); +} +/*=========================================================================== +FUNCTION reset_rds + +DESCRIPTION + Reset the existing RDS data. + +DEPENDENCIES + Radio event + +RETURN VALUE + void + +IDE EFFECTS + Reset the Global RDS data info like RT, PS etc. +===========================================================================*/ + +void reset_rds() +{ + memset(fm_global_params.pgm_services,0x0,MAX_RDS_PS_LENGTH); + memset(fm_global_params.radio_text,0x0,MAX_RDS_RT_LENGTH); + fm_global_params.pgm_id = 0; + fm_global_params.pgm_type = 0; +} + +struct timespec* set_time_out(int secs) +{ + struct timespec *ts; + struct timeval tp; + ts = malloc(sizeof(struct timespec)); + if(!ts) + { + printf("malloc failed"); + return NULL; + } + gettimeofday(&tp, NULL); + ts->tv_sec = tp.tv_sec; + ts->tv_nsec = tp.tv_usec * 1000; + ts->tv_sec += secs; + + return ts; +} + +/*=========================================================================== +FUNCTION EnableFM + +DESCRIPTION + PFAL specific routine to enable the FM receiver/transmitter with the Radio + Configuration parameters passed. + +PLATFORM SPECIFIC DESCRIPTION + Opens the handle to /dev/radio0 V4L2 device and intiates a Soc Patch + download, configurs the Init parameters like emphasis, channel spacing, + band limit, RDS type, frequency band, and Radio State. + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type EnableFM +( + fm_config_data* radiocfgptr +) +{ + int status; +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("\nEnable Transmitter entry\n"); + else + print("\nEnable Receiver entry\n"); +#endif + + lib_handle = dlopen(FM_LIBRARY_NAME, RTLD_NOW); + if (!lib_handle) { + ALOGE("%s unable to open %s: %s", __func__, FM_LIBRARY_NAME, dlerror()); + lib_handle = NULL; + return FM_CMD_NO_RESOURCES; + } + + printf("Obtaining handle: '%s' to the shared object library...\n", FM_LIBRARY_SYMBOL_NAME); + vendor_interface = (fm_interface_t *)dlsym(lib_handle, FM_LIBRARY_SYMBOL_NAME); + if (!vendor_interface) { + ALOGE("%s unable to find symbol %s in %s: %s", __func__, FM_LIBRARY_SYMBOL_NAME, FM_LIBRARY_NAME, dlerror()); + vendor_interface = NULL; + if (lib_handle) + dlclose(lib_handle); + return FM_CMD_NO_RESOURCES; + } + + if (vendor_interface) { + ALOGE("Initializing the FM HAL module & registering the JNI callback functions..."); + status = vendor_interface->hal_init(&fm_callbacks); + if (status) { + ALOGE("%s unable to initialize vendor library: %d", __func__, status); + return FM_CMD_NO_RESOURCES; + } + ALOGD("***** FM HAL Initialization complete *****\n"); + } + + if(radiocfgptr->is_fm_tx_on) + print("\nOpened Transmitter\n"); + else + print("\nOpened Receiver\n"); + +/* + Starting 'ftm_on_long_thread' where we do all the FM configurations + and intializations. + +*/ + fmPowerState = FM_POWER_TRANSITION; + pthread_create( &fm_on_thread, NULL, ftm_on_long_thread, radiocfgptr); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION TransmitPS + +DESCRIPTION + PFAL specific routine to transmit RDS PS strings + +PARAMS PASSED + 'tuFmPSParams' containing RDS PI, PTY, max. no. of PS repeat count and + PS name of the transmitting station + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to transmit the PS string describing the transmitter's + information and genre of the audio content being transmitted + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type TransmitPS +( + tsFtmFmRdsTxPsType* tuFmPSParams +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + print("\n Entering Transmit PS \n"); + + /* Set Program Type (PTY) */ + control.id = V4L2_CID_RDS_TX_PTY; + control.value = 0; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PTY failed \n"); + return FM_CMD_FAILURE; + } + + /* Set Program Identifier (PI) */ + control.id = V4L2_CID_RDS_TX_PI; + control.value = tuFmPSParams->tusTxPi; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PI failed \n"); + return FM_CMD_FAILURE; + } + + /*Set PS max. repeat count */ + control.id = V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT; + control.value = tuFmPSParams->ucTxPSRptCnt; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set MAX_REPEAT_CNT failed \n"); + return FM_CMD_FAILURE; + } + + /*Set Program Service name (PS) */ + ext_ctl.id = V4L2_CID_RDS_TX_PS_NAME; + ext_ctl.string = (char *)tuFmPSParams->cTxPSStrPtr; + ext_ctl.size = tuFmPSParams->ulPSStrLen; + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_FM_TX; + v4l2_ctls.count = 0; + v4l2_ctls.controls = &ext_ctl; + + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set PS failed \n"); + return FM_CMD_FAILURE; + } + is_ps_transmitting = 1; + print("\n Exiting Transmit PS \n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION stopTransmitPS + +DESCRIPTION + PFAL specific routine to stop transmitting the PS string. + +PARAMS PASSED + NIL + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to stop transmitting the PS string + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +============================================================================*/ +fm_cmd_status_type stopTransmitPS +( + void +) +{ + int ret = 0; + struct v4l2_control control; + + print("\n Entering stopTransmitPS \n"); + + control.id = V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME; + ret = ioctl(fd_radio, VIDIOC_S_CTRL , &control); + if(ret < 0){ + print("Failed to stop Transmit PS"); + return FM_CMD_FAILURE; + } + else { + print("\nStopped transmitting PS\n"); + is_ps_transmitting = 0; + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION TransmitRT + +DESCRIPTION + PFAL specific routine to transmit the RT string. + +PARAMS PASSED + 'tuFmRTParams' containing RDS PI, and RT information of the transmitting + station + +PLATFORM SPECIFIC DESCRIPTION + This routine is used to transmit the RT string which provides a brief info + of the audio content being transmitted. This includes artist name, movie name + few lines of the audio. Usually the metadata of the song is transmitted as RT + + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None +===========================================================================*/ +fm_cmd_status_type TransmitRT +( + tsFtmFmRdsTxRtType* tuFmRTParams +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_FM_TX; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + print("\n Entering Transmit RT \n"); + + if(tuFmRTParams == NULL) + { + print("\n 'tuFmRTParams ' is not NULL \n "); + return FM_CMD_FAILURE; + } + else + { + ext_ctl.id = V4L2_CID_RDS_TX_RADIO_TEXT; + ext_ctl.string = (char *)tuFmRTParams->cTxRTStrPtr; + ext_ctl.size = tuFmRTParams->ulRTStrLen; + } + /* Set Program Type (PTY) */ + control.id = V4L2_CID_RDS_TX_PTY; + control.value = 0; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PTY failed \n"); + return FM_CMD_FAILURE; + } + + /* Set Program Identifier (PI) */ + control.id = V4L2_CID_RDS_TX_PI; + control.value = tuFmRTParams->tusTxPi; + ret = ioctl(fd_radio, VIDIOC_S_CTRL,&control ); + if(ret < 0 ) + { + print("\n VIDIOC_S_CTRL ioctl: Set PI failed \n"); + return FM_CMD_FAILURE; + } + + /* Set the Radio Text (RT) to be transmitted */ + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set RT failed \n"); + return FM_CMD_FAILURE; + } + + is_rt_transmitting = 1; + return FM_CMD_SUCCESS; + +} + +/*=========================================================================== +FUNCTION stopTransmitRT + +DESCRIPTION + PFAL specific routine to stop transmitting the RT string. + +PLATFORM SPECIFIC DESCRIPTION + This routine is called to stop transmitting the RT string for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type stopTransmitRT +( + void +) +{ + int ret = 0; + + print("\n Entering stopTransmitRT \n"); + + struct v4l2_control control; + control.id = V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT; + ret = ioctl(fd_radio, VIDIOC_S_CTRL , &control); + if(ret < 0){ + print("Failed to stop Transmit RT"); + return FM_CMD_FAILURE; + } + else { + print("\nStopped transmitting RT\n"); + is_rt_transmitting = 0; + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION getTxPSFeatures + +DESCRIPTION + PFAL specific routine to get all the supported Tx PS features + +PLATFORM SPECIFIC DESCRIPTION + This routine is called to get the supported PS features for the + transmitting station + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type getTxPSFeatures +( + void +) +{ + print("\n Entering getTxPSFeatures() \n"); + printf("\n Supported Tx PS Features:\n"); + printf("\n Max PS Count : %d\n",MAX_TX_PS_LEN); + printf("\n Max PS Repeat Count : %d\n",MAX_TX_PS_RPT_CNT); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION ftm_on_long_thread + +DESCRIPTION + Helper routine to perform the rest ofthe FM calibration and SoC Patch + download and configuration settings following the opening ofradio handle + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + None + +===========================================================================*/ +void *(ftm_on_long_thread)(void *ptr) +{ + int ret = 0; + struct v4l2_control control; + struct v4l2_tuner tuner; + int i,init_success = 0; + char value[PROPERTY_VALUE_MAX]; + struct v4l2_capability cap; + char versionStr[40]; + char cmdBuffer[40]; + char product_board_platform_type[PROPERTY_VALUE_MAX]; + fm_cmd_status_type status; + + fm_config_data* radiocfgptr = (fm_config_data *)ptr; + + property_get("qcom.bluetooth.soc", value, NULL); + print2("BT soc is %s\n", value); + /** + * V4L2_CID_PRIVATE_TAVARUA_STATE + * V4L2_CID_PRIVATE_TAVARUA_EMPHASIS + * V4L2_CID_PRIVATE_TAVARUA_SPACING + * V4L2_CID_PRIVATE_TAVARUA_RDS_STD + * V4L2_CID_PRIVATE_TAVARUA_REGION + */ + + /* Switching on FM */ + if (radiocfgptr->is_fm_tx_on) + { + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_STATE, FM_TX); + if(ret < FALSE) + { + print("Failed to turn on FM Trnasmitter\n"); + return NULL; + } + else + print("\nEnabled FM Transmitter successfully\n"); + } + else + { + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_STATE, FM_RX); + if(ret < FALSE) + { + print("Failed to turn on FM Receiver\n"); + return NULL; + } + else + print("\nEnabled FM Receiver successfully\n"); + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH,1); + if(ret < FALSE) + { + print("Failed to set Audio path \n"); + } + + status = ConfigureFM(radiocfgptr); + if(status != FM_CMD_SUCCESS) + { + print("Failed to configure fm\n"); + return NULL; + } + + /* Setting RDS On */ + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSON,1); + if(ret is_fm_tx_on) + { + int rdsMask = FM_RX_RDS_GRP_RT_EBL | FM_RX_RDS_GRP_PS_EBL | + FM_RX_RDS_GRP_AF_EBL | FM_RX_RDS_GRP_PS_SIMPLE_EBL | + FM_RX_RDS_GRP_ECC_EBL| FM_RX_RDS_GRP_PTYN_EBL | + FM_RX_RDS_GRP_RT_PLUS_EBL; + + byte rdsFilt = 0; + int psAllVal=rdsMask & (1 << 4); + print2("rdsOptions: rdsMask: %x\n",rdsMask); + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC, + rdsMask); + if(ret < FALSE) + { + print("Failed to set RDS GROUP PROCESSING!!!\n"); + return NULL; + } + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,0x0FFF); + if (ret < FALSE) + { + print("Failed to set RDS GRP MASK!!!\n"); + return NULL; + } + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,1); + if (ret < FALSE) + { + print("Failed to set RDS BUF!!!\n"); + return NULL; + } + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_ANTENNA,0); + if(ret < FALSE) + { + print("Failed to set ANTENNA!!!\n"); + return NULL; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SOFT_MUTE, 0); + if(ret < FALSE) + { + print("Failed to Disable Soft Mute!!!\n"); + return NULL; + } + + } + power_down = FALSE; + + if(radiocfgptr->is_fm_tx_on) { +#ifdef FTM_DEBUG + print("\nEnable Transmitter exit\n"); +#endif + fmPowerState = FM_TX_ON; + } + else { +#ifdef FTM_DEBUG + print("\nEnable Receiver exit\n"); +#endif + fmPowerState = FM_RX_ON; + } + poweron = COMPLETE; + return NULL; +} + +/*=========================================================================== +FUNCTION DisableFM + +DESCRIPTION + PFAL specific routine to disable FM and free the FM resources + +PLATFORM SPECIFIC DESCRIPTION + Closes the handle to /dev/radio0 V4L2 device + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None +===========================================================================*/ +fm_cmd_status_type DisableFM +( + fm_config_data* radiocfgptr +) +{ + struct v4l2_control control; + uint8 buf[128]; + double tune; + char value[PROPERTY_VALUE_MAX]; + struct v4l2_frequency freq_struct; + int ret; + + /* Wait till the previous ON sequence has completed */ + while(poweron != COMPLETE); + +#ifdef FTM_DEBUG + print("DisableFM start\n"); +#endif + + power_down = TRUE; + + /* Set RDS Off */ + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSON,0); + if(ret < FALSE) + { + print("DisableFM failed to set RDS off \n"); + return FM_CMD_FAILURE; + } + + /* Turn off FM */ + /* As part of Turning off FM we will get 'READY' event */ + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_STATE,0); + if(ret < FALSE) + { + if(radiocfgptr->is_fm_tx_on) + { + print("\nFailed to Turn Off FM Transmitter\n"); + return FM_CMD_FAILURE; + } + else + { + print("\nFailed to Turn Off FM Receiver\n"); + return FM_CMD_FAILURE; + } + } + +#ifdef FTM_DEBUG + print("Stopping the FM control\n"); +#endif + +#ifdef ANDROID + + property_get("qcom.bluetooth.soc", value, NULL); + print2("BT soc is %s\n", value); + if (strcmp(value, "rome") != 0) + { + property_set("ctl.stop", "fm_dl"); + } + +#endif/*ANDROID*/ +cmd_queued = TRUE; + +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("Disabled FM Transmitter\n"); + else + print("Disabled FM Receiver\n"); + +#endif + fmPowerState = FM_POWER_OFF; + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION ConfigureFM + +DESCRIPTION + PFAL specific routine to configure FM with the Radio Configuration + parameters passed. + +PLATFORM SPECIFIC DESCRIPTION + Configures the Init parameters like emphasis, channel spacing, Band Limit, + RDS type, Frequency Band, and Radio State. + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type ConfigureFM +( + fm_config_data* radiocfgptr +) +{ + int ret = 0; + struct v4l2_control control; + struct v4l2_tuner tuner; + +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("\nConfigure FM Transmitter entry\n"); + else + print("\nConfigure FM Receiver entry\n"); +#endif + + /* Set Emphasis, Channel spacing and RDS Standard : + Emphasis : + '0' - 75 - US/EU + '1' - 50 - JAPAN/JAPAN-WIDE/ASIA + Channel Spacing : + '0' - 200kHz - US/EU + '1' - 100kHz - JAPAN + '2' - 50kHz - JAPAN-WIDE + RDS/RDBS Standard : + '0' - RDBS - US/EU + '1' - RDS - All regions + */ + fmconfig_ptr =(fm_config_data *) malloc(sizeof(fm_config_data)); + if(!fmconfig_ptr) + { + print("malloc failed"); + return FM_CMD_FAILURE; + } + fmconfig_ptr->band = radiocfgptr->band; + switch(radiocfgptr->band) + { + case FM_US_EU: + radiocfgptr->emphasis = 0; + radiocfgptr->spacing = 0; + radiocfgptr->rds_system = 0; + break; + case FM_JAPAN_STANDARD: + radiocfgptr->emphasis = 1; + radiocfgptr->spacing = 1; + radiocfgptr->rds_system = 1; + case FM_JAPAN_WIDE: + radiocfgptr->emphasis = 1; + radiocfgptr->spacing = 2; + radiocfgptr->rds_system = 1; + break; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_EMPHASIS, radiocfgptr->emphasis); + if(ret < FALSE) + { + print("ConfigureFM : Failed to set Emphasis \n"); + return FM_CMD_FAILURE; + } + + /* Set channel spacing */ + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SPACING,radiocfgptr->spacing); + if(ret < FALSE) + { + print("ConfigureFM : Failed to set channel spacing \n"); + return FM_CMD_FAILURE; + } + + /* Set RDS/RDBS Standard */ + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDS_STD,radiocfgptr->rds_system); + if(ret < FALSE) + { + print("ConfigureFM : Failed to set RDS std \n"); + return FM_CMD_FAILURE; + } + + /* Set band limit and audio mode to Mono/Stereo */ + tuner.index = 0; + tuner.signal = 0; + + print2("ConfigureFM : radio band = %d\n",radiocfgptr->band); + switch(radiocfgptr->band) + { + case FM_US_EU: + tuner.rangelow = REGION_US_EU_BAND_LOW ; + tuner.rangehigh = REGION_US_EU_BAND_HIGH; + break; + case FM_JAPAN_STANDARD: + tuner.rangelow = REGION_JAPAN_STANDARD_BAND_LOW; + tuner.rangehigh = REGION_JAPAN_STANDARD_BAND_HIGH; + break; + case FM_JAPAN_WIDE: + tuner.rangelow = REGION_JAPAN_WIDE_BAND_LOW; + tuner.rangehigh = REGION_JAPAN_WIDE_BAND_HIGH; + break; + default: + tuner.rangelow = radiocfgptr->bandlimits.lower_limit; + tuner.rangehigh = radiocfgptr->bandlimits.upper_limit; + break; + } + + ret = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_UPPER_BAND, tuner.rangehigh); + ret = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_LOWER_BAND, tuner.rangelow); + fmconfig_ptr->bandlimits.lower_limit = tuner.rangelow; + fmconfig_ptr->bandlimits.upper_limit = tuner.rangehigh; + print3("ConfigureFM : set band limits: lower_limit=%d\t upper_limit = %d \n", fmconfig_ptr->bandlimits.lower_limit,fmconfig_ptr->bandlimits.upper_limit ); + if(ret < 0) + { + print("ConfigureFM : Failed to set band limits and audio mode \n"); + return FM_CMD_FAILURE; + } + + /* Set Region */ + radiocfgptr->band = FM_USER_DEFINED; + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_REGION,radiocfgptr->band); + if(ret < FALSE) + { + print("ConfigureFM : Failed to set band\n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSON,1); + if(ret < 0) + { + print("ConfigureFM : Failed to set RDS ON \n"); + return FM_CMD_FAILURE; + } +out : +#ifdef FTM_DEBUG + + if(radiocfgptr->is_fm_tx_on) + print("\nConfigure FM Transmitter exit\n"); + else + print("\nConfigure FM Receiver exit\n"); +#endif + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetFrequencyReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Frequency ofreception + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyReceiver +( + uint32 ulfreq +) +{ + int err; + int freq_rangehigh,freq_rangelow; +#ifdef FTM_DEBUG + print2("\nSetFrequency Receiver entry freq = %d\n",(int)ulfreq); +#endif + freq_rangehigh = fmconfig_ptr->bandlimits.upper_limit; + freq_rangelow = fmconfig_ptr->bandlimits.lower_limit; + printf("\n set frequency=%d\t range_high=%d\t range_low =%d\n",ulfreq,freq_rangehigh,freq_rangelow); + ALOGE("\n set frequency=%d\t range_high=%d\t range_low =%d\n",ulfreq,freq_rangehigh,freq_rangelow); + if (ulfreq >= freq_rangelow && ulfreq <= freq_rangehigh) + { + err = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_FREQ, ulfreq); + if (err < 0) + { + print("SetFrequencyReceiver : Failed to set Freq \n"); + return FM_CMD_FAILURE; + } + } + else + { + print("SetFrequencyReceiver : frequency out of band limits \n"); + return FM_CMD_DISALLOWED; + } + +#ifdef FTM_DEBUG + print("\nSetFrequency Receiver exit\n"); +#endif + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetFrequencyTransmitter + +DESCRIPTION + PFAL specific routine to configure the FM Transmitter's frequency + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetFrequencyTransmitter +( + uint32 ulfreq +) +{ + int err; + double tune; + struct v4l2_frequency freq_struct; + struct v4l2_control control; + struct v4l2_tuner tuner; +#ifdef FTM_DEBUG + print2("\n SetFrequencyTransmitter() entry : Freq = %d \n",(int)ulfreq); +#endif + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + /* Stop transmitting PS/RT frequency of currently tuned station */ + print2("\n Currently tuned station is : %ld \n",fm_global_params.current_station_freq); + if(is_ps_transmitting) + stopTransmitPS(); + if(is_rt_transmitting) + stopTransmitRT(); + + tuner.index = 0; + + err = ioctl(fd_radio,VIDIOC_G_TUNER,&tuner); + if(err < 0) + { + print("SetFrequencyTransmitter : Failed to get band limits and audio mode \n"); + return FM_CMD_FAILURE; + } + + /* Fill up the 'v4l2_frequency' structure */ + freq_struct.type = V4L2_TUNER_RADIO; + freq_struct.frequency = (ulfreq) * (TUNE_MULT/1000); + if (freq_struct.frequency >= tuner.rangelow && freq_struct.frequency <= tuner.rangehigh) + { + err = ioctl(fd_radio, VIDIOC_S_FREQUENCY, &freq_struct); + if(err < 0) + return FM_CMD_FAILURE; + else + print2("\n Frequency : %ld \n",ulfreq); + } + else + { + print("SetFrequencyTransmitter : Frequency out of bandlimits\n"); + return FM_CMD_DISALLOWED; + } + +#ifdef FTM_DEBUG + print("\n SetFrequencyTransmitter() exit \n"); +#endif + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetTxPowerLevel + +DESCRIPTION + PFAL specific routine to configure the FM transmitter's power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetTxPowerLevel +( + uint32 ulfreq +) +{ + int err; + struct v4l2_control control; + + /* Set the power level as requested */ + control.id = V4L2_CID_TUNE_POWER_LEVEL; + control.value = FM_TX_PWR_LVL_MAX; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if(err < 0) + { + if( err == -ETIME) + print("\nTimeout to read PHY_TX gain Register\n"); + else + { + print2("\nFailed to set the Power Level for %ld\n",ulfreq); + return FM_CMD_FAILURE; + } + } + else + print2("\nSuccessfully set the Power Level for %ld\n",ulfreq); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetMuteModeReceiver +( + mute_type mutemode +) +{ + int err,i; + struct v4l2_control control; + print2("SetMuteModeReceiver mode = %d\n",mutemode); + + err = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_AUDIO_MUTE,mutemode); + if(err >= 0) + { + print("SetMuteMode Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set mute mode ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== + +FUNCTION SetSoftMuteModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's soft mute status + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSoftMuteModeReceiver +( + mute_type mutemode +) +{ + int err; + struct v4l2_control control; + print2("SetMuteModeReceiver mode = %d\n",mutemode); + + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SOFT_MUTE,mutemode); + if(err >= 0) + { + print("SetMuteMode Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set mute mode ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION SetAntenna + +DESCRIPTION + PFAL specific routine to configure the FM receiver's antenna type + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type SetAntenna +( + antenna_type antenna +) +{ + int err; + struct v4l2_control control; + control.value = antenna; + control.id = V4L2_CID_PRIVATE_TAVARUA_ANTENNA; + + err = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_ANTENNA,antenna); + if(err >= 0) + { + print("SetAntenna Success\n"); + return FM_CMD_SUCCESS; + } + + print2("Set antenna ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION FmRivaPeekData + +DESCRIPTION + PFAL specific routine to get the data from Riva Memory +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmRivaPeekData +( + fm_riva_peek_word peek_word +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = peek_word.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR, + peek_word.startaddress); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.value = peek_word.payload_length; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN, + peek_word.payload_length); + if(err >= 0) + { + print("SetDataLen Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_PEEK; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_PEEK, control.value); + if(err >= 0) + { + print("RivaPeek Success\n"); + return FM_CMD_SUCCESS; + } + + print2("RivaPeekData ret = %d\n",err); + return FM_CMD_FAILURE; +} + + +/*=========================================================================== +FUNCTION FmRivaPokeData + +DESCRIPTION + PFAL specific routine to write the data into the Riva Memory +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmRivaPokeData +( + fm_riva_poke_word poke_word +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = poke_word.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR, + poke_word.startaddress); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.value = poke_word.payload_length; + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN; +// err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN, + poke_word.payload_length); + if(err >= 0) + { + print("SetDataLen Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_RIVA_POKE; + control.value = (uint32)(uintptr_t)(&poke_word.data); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RIVA_POKE, + control.value); + if(err >= 0) + { + print("RivaPoke Success\n"); + return FM_CMD_SUCCESS; + } + + print2("RivaPokeData ret = %d\n",err); + return FM_CMD_FAILURE; +} + + +/*=========================================================================== +FUNCTION FmSSBIPeekData + +DESCRIPTION + PFAL specific routine to get the data from SSBI registers +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmSSBIPeekData +( + fm_ssbi_poke_reg peek_reg +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_PEEK; + control.value = peek_reg.startaddress; + if( control.value == 0x00) + return FM_CMD_FAILURE; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SSBI_PEEK, + peek_reg.startaddress); + if(err >= 0) + { + //extract_ssbi_peek_data(); + print2("SSBIPeek Success\n %d",peek_reg.data); + return FM_CMD_SUCCESS; + } + + print2("SSBIPeekData ret = %d\n",err); + return FM_CMD_FAILURE; +} + +fm_cmd_status_type FmSetGetResetAGC +( + fm_set_get_reset_agc_req agc_params +) +{ + int err; + struct v4l2_control control; + control.value = agc_params.ucCtrl; + control.id = V4L2_CID_PRIVATE_IRIS_AGC_CTRL; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_AGC_CTRL, + agc_params.ucCtrl); + if(err >= 0) + { + print("Sending AGC ucCtrL Success\n"); + } + control.value = agc_params.ucGainState; + control.id = V4L2_CID_PRIVATE_IRIS_AGC_STATE; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_AGC_STATE, + agc_params.ucGainState); + if(err >= 0) + { + print("Set ucGainstate Success\n"); + return FM_CMD_SUCCESS; + } + + print2("SetGetResetAGC ret = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION FmSSBIPokeData + +DESCRIPTION + PFAL specific routine to program the SSBI registers +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmSSBIPokeData +( + fm_ssbi_poke_reg poke_reg +) +{ + int err; + struct v4l2_control control; + + if(fd_radio < 0) + return FM_CMD_NO_RESOURCES; + + control.value = poke_reg.startaddress; + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR, + poke_reg.startaddress); + if(err >= 0) + { + print("SetRiva Address Success\n"); + } + control.id = V4L2_CID_PRIVATE_IRIS_SSBI_POKE; + control.value = poke_reg.data; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SSBI_POKE, + control.value); + if(err >= 0) + { + print2("SSBIPoke Success\n value =%d",poke_reg.data); + return FM_CMD_SUCCESS; + } + + print2("SSBIPokeData ret = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmTxPwrLvlCfg + +DESCRIPTION + PFAL specific routine to configure the FM Tx power level + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmTxPwrLvlCfg +( + uint8 pwrlvl +) +{ + int err; + struct v4l2_control control; + control.value = pwrlvl; + control.id = V4L2_CID_TUNE_POWER_LEVEL; + err = ioctl(fd_radio, VIDIOC_S_CTRL, &control); + if (err >= 0) { + print2("Tx power level set to %d\n", pwrlvl); + return FM_CMD_SUCCESS; + } + print2("Set Tx power level failed = %d\n", err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmTxToneGen + +DESCRIPTION + PFAL specific routine to configure the FM Tx internal tone Generation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + + +fm_cmd_status_type FmTxToneGen +( + uint8 txTone +) +{ + int err; + struct v4l2_control control; + control.value = txTone; + control.id = V4L2_CID_PRIVATE_IRIS_TX_TONE; + err = ioctl(fd_radio,VIDIOC_S_CTRL,&control); + if(err >= 0) + { + print("Set Tx internal tone Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set Tx internal tone = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmRDSGrpcntrs + +DESCRIPTION + PFAL specific routine to get the FM RDS group conuters + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmRDSGrpcntrs +( + uint8 rdsCounters +) +{ + int err; + struct timespec* ts; + pthread_mutex_lock(&fm_event_lock); + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS, rdsCounters); + if (err >= 0) + { + print("Read RDS GROUP counters success\n"); + ts = set_time_out(2); + if(ts) + { + err = pthread_cond_timedwait(&fm_event_cond, &fm_event_lock, ts); + ALOGD("Unlocked mutex timedout or condition satisfied %s", __func__); + pthread_mutex_unlock(&fm_event_lock); + free(ts); + return FM_CMD_SUCCESS; + } + } + print2("Read RDS GROUP counters = %d\n",err); + pthread_mutex_unlock(&fm_event_lock); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION FmRDSGrpcntrsExt + +DESCRIPTION + PFAL specific routine to get the FM RDS group conuters + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmRDSGrpcntrsExt +( + uint8 rdsCounters +) +{ + int err; + struct v4l2_control control; + control.value = rdsCounters; + control.id = V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS_EXT; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS_EXT, rdsCounters); + if(err >= 0) + { + print("Read RDS GROUP counters extn success\n"); + return FM_CMD_SUCCESS; + } + print2("Read RDS GROUP counters extn = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION FmDefaultRead + +DESCRIPTION + PFAL specific routine to get the FM Default Values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmDefaultRead +( + ftm_fm_def_data_rd_req defaultRead +) +{ + int err; + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + ext_ctl.id = V4L2_CID_PRIVATE_IRIS_READ_DEFAULT; + ext_ctl.size = sizeof(ftm_fm_def_data_rd_req); + memcpy(ext_ctl.string,(char *)&defaultRead,ext_ctl.size); + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_USER; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + err = ioctl(fd_radio,VIDIOC_G_EXT_CTRLS,&v4l2_ctls); + if(err >= 0) + { + extract_default_read_data(); + print("Read Defaults success\n"); + return FM_CMD_SUCCESS; + } + print2("Read Defaults =%d \n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmDefaultWrite + +DESCRIPTION + PFAL specific routine to write the default values + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmDefaultWrite +( + ftm_fm_def_data_wr_req* writedefaults +) +{ + int ret = 0; + + struct v4l2_control control; + struct v4l2_ext_controls v4l2_ctls; + struct v4l2_ext_control ext_ctl; + + if(writedefaults == NULL) + { + print("\n 'writedefaults' is NULL \n "); + return FM_CMD_FAILURE; + } + ext_ctl.id = V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT; + ext_ctl.size = (writedefaults->length + 2); + ext_ctl.string = (char *)&writedefaults->mode; + + v4l2_ctls.ctrl_class = V4L2_CTRL_CLASS_USER; + v4l2_ctls.count = 1; + v4l2_ctls.controls = &ext_ctl; + + print("\n Entering Write defaults \n"); + + ret = ioctl(fd_radio, VIDIOC_S_EXT_CTRLS, &v4l2_ctls ); + if(ret < 0 ) + { + print("\n VIDIOC_S_EXT_CTRLS ioctl: Set Default failed \n"); + return FM_CMD_FAILURE; + } + + return FM_CMD_SUCCESS; + +} + +/*=========================================================================== +FUNCTION FmSetHlSi + +DESCRIPTION + PFAL specific routine to configure the FM receiver's HlSi + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmSetHlSi +( + uint8 hlsi +) +{ + int err = -1; + struct v4l2_control control; + control.value = hlsi; + control.id = V4L2_CID_PRIVATE_IRIS_HLSI; + err = vendor_interface->set_fm_ctrl( FTM_FM_SET_HLSI, hlsi); + print2("Setting HLSI to = %d",hlsi); + if(err >= 0) + { + print("Set HlSi success"); + return FM_CMD_SUCCESS; + } + print2("Set HlSi status = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION FmSetNotchFilter + +DESCRIPTION + PFAL specific routine to configure the FM receiver's notch filter + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type FmSetNotchFilter +( + uint8 notch +) +{ + int err = -1 ; + struct v4l2_control control; + control.value = notch; + control.id = V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER; + print2("Setting Notch filter to = %d",notch); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER, notch); + if(err >= 0) + { + print("Set Notch filter success"); + return FM_CMD_SUCCESS; + } + print2("Set Notch filter status = %d\n",err); + return FM_CMD_FAILURE; +} +/*=========================================================================== +FUNCTION SetStereoModeReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's Audio mode on the + frequency tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetStereoModeReceiver +( + stereo_type stereomode +) +{ + int err = -1; + err = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_AUDIO_MODE,stereomode); + ALOGD("Stereo mode =%d ... %s", stereomode,__func__); + if(err >= 0) { + print("SetStereoMode Success\n"); + return FM_CMD_SUCCESS; + } + print2("Set Stereo Mode status = %d\n",err); + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION GetStationParametersReceiver + +DESCRIPTION + PFAL specific routine to get the station parameters ofthe Frequency at + which the Radio receiver is tuned + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetStationParametersReceiver +( + fm_station_params_available* configparams +) +{ + int ret = 0, value = 0; + struct timespec* ts; + configparams->current_station_freq = fm_global_params.current_station_freq; + configparams->service_available = fm_global_params.service_available; + + pthread_mutex_lock(&fm_event_lock); + ret = vendor_interface->get_fm_ctrl(HCI_FM_HELIUM_RMSSI, &value); + if (ret < 0) { + print2("GetStationParametersReceiver:Failed to get Rssi error = %d\n",ret); + pthread_mutex_unlock(&fm_event_lock); + return FM_CMD_FAILURE; + } + ts = set_time_out(2); + if(ts) + { + ret = pthread_cond_timedwait(&fm_event_cond, &fm_event_lock, ts); + ALOGD("Unlocked mutex timedout or condition satisfied %s", __func__); + free(ts); + } + else + { + print("Cmd timeout failed .."); + pthread_mutex_unlock(&fm_event_lock); + return FM_CMD_FAILURE; + } + pthread_mutex_unlock(&fm_event_lock); + + ret = vendor_interface->get_fm_ctrl(HCI_FM_HELIUM_AUDIO_MUTE,&value); + if (ret < 0) { + print2("Failed to get mute status error = %d\n",ret); + return FM_CMD_FAILURE; + } + configparams->mute_status = value; + print2("GetStationParametersReceiver: Rssi = %d\n",fm_global_params.rssi); + configparams->rssi = fm_global_params.rssi; + configparams->stype = fm_global_params.stype; + configparams->rds_sync_status = fm_global_params.rds_sync_status; + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetRdsOptionsReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsOptionsReceiver +( + fm_rds_options rdsoptions +) +{ + int ret; + print("SetRdsOptionsReceiver\n"); + ALOGE("SetRdsOptionsReceiver\n"); + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK, + rdsoptions.rds_group_mask); + if(ret < FALSE) + { + print2("SetRdsOptionsReceiver Failed to set RDS group options = %d\n",ret); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF, + rdsoptions.rds_group_buffer_size); + if(ret < FALSE) + { + print2("SetRdsOptionsReceiver Failed to set RDS group options = %d\n",ret); + return FM_CMD_FAILURE; + } + + /*Chnage Filter not supported */ + print("SetRdsOptionsReceiver<\n"); + + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetRdsGroupProcReceiver + +DESCRIPTION + PFAL specific routine to configure the FM receiver's RDS group proc options + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetRdsGroupProcReceiver +( + uint32 rdsgroupoptions +) +{ + int ret; + print("SetRdsGroupProcReceiver\n"); + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC, + rdsgroupoptions); + if(ret < FALSE) + { + print2("SetRdsGroupProcReceiver Failed to set RDS proc = %d\n",ret); + return FM_CMD_FAILURE; + } + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_RDSON,1); + if(ret < FALSE) + { + print2(" Failed to set RDS proc ON = %d\n",ret); + return FM_CMD_FAILURE; + } + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION SetPowerModeReceiver + +DESCRIPTION + PFAL specific routine to configure the power mode of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetPowerModeReceiver +( + uint8 powermode +) +{ + struct v4l2_control control; + int i,err; + print2("SetPowerModeReceiver mode = %d\n",powermode); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_LP_MODE, powermode); + if (err < 0) + { + print("SetPowerMode Failed\n"); + return FM_CMD_FAILURE; + } + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to configure the signal threshold ofFM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSignalThresholdReceiver +( + uint8 signalthreshold +) +{ + struct v4l2_control control; + int i,err; + print2("SetSignalThresholdReceiver threshold = %d\n",signalthreshold); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,signalthreshold); + if(err >= 0) + { + print("SetSignalThresholdReceiver Success\n"); + return FM_CMD_SUCCESS; + } + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION GetSignalThresholdReceiver + +DESCRIPTION + PFAL specific routine to get the signal threshold of FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetSignalThresholdReceiver +( + uint8* signalthreshold +) +{ + int i,err,value=0; + + err = vendor_interface->get_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH, &value); + if(err >= 0) + { + print2("GetSignalThresholdReceiver Success = %d\n",value); + *signalthreshold = value; + return FM_CMD_SUCCESS; + } + + return FM_CMD_FAILURE; +} + +/*=========================================================================== +FUNCTION GetRSSILimits + +DESCRIPTION + PFAL specific routine to print the RSSI limts ofFM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRSSILimits +( +) +{ + int limits[] ={0,100}; + + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION GetPSInfoReceiver + +DESCRIPTION + PFAL specific routine to print the PS info ofcurrent frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetPSInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetRTInfoReceiver + +DESCRIPTION + PFAL specific routine to print the Radio text info ofcurrent frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetRTInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetAFInfoReceiver + +DESCRIPTION + PFAL specific routine to print the AF list for current frequency of + FM receiver + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type GetAFInfoReceiver +( +) +{ + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SearchStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationsReceiver +( +fm_search_stations searchstationsoptions +) +{ + int err,i; + int ret; + print("SearchStationsReceiver\n"); + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchstationsoptions.search_mode); + if(ret < FALSE) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SCANDWELL, + searchstationsoptions.dwell_period); + if(ret < FALSE) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + if (searchstationsoptions.search_dir) + searchstationsoptions.search_dir = SRCH_DIR_UP; + else + searchstationsoptions.search_dir = SRCH_DIR_DOWN; + + err = vendor_interface->set_fm_ctrl(HCI_FM_HELIUM_SEEK,searchstationsoptions.search_dir); + if(err < 0) + { + print("SearchStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + print("SearchRdsStationsReceiver<\n"); + return FM_CMD_SUCCESS; +} + + +/*=========================================================================== +FUNCTION SearchRDSStationsReceiver + +DESCRIPTION + PFAL specific routine to search for stations from the current frequency of + FM receiver with a specific program type and print the information on diag + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchRdsStationsReceiver +( +fm_search_rds_stations searchrdsstationsoptions +) +{ + int i,err; + int ret; + + print("SearchRdsStationsReceiver>\n"); + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchrdsstationsoptions.search_mode); + if(ret < FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SCANDWELL, + searchrdsstationsoptions.dwell_period); + if(ret < FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY, + searchrdsstationsoptions.program_type); + if(ret < FALSE) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCH_PI, + searchrdsstationsoptions.program_id); + if(ret set_fm_ctrl(HCI_FM_HELIUM_SEEK,searchrdsstationsoptions.search_dir); + if(err < 0) + { + print("SearchRdsStationsReceiver failed \n"); + return FM_CMD_FAILURE; + } + + print("SearchRdsStationsReceiver<\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION SearchStationListReceiver + +DESCRIPTION + PFAL specific routine to search for stations with a specific mode of + informaation like WEAK,STRONG,STRONGEST etc + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SearchStationListReceiver +( +fm_search_list_stations searchliststationsoptions +) +{ + int i,ret; + + print("SearchStationListReceiver>\n"); + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCHMODE, + searchliststationsoptions.search_mode); + if(ret < FALSE) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT, + searchliststationsoptions.srch_list_max); + if(ret < FALSE) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY, + searchliststationsoptions.program_type); + if(ret set_fm_ctrl(HCI_FM_HELIUM_SEEK,searchliststationsoptions.search_dir); + if(ret < 0) + { + print("SearchStationListReceiver failed \n"); + return FM_CMD_FAILURE; + } + print("SearchStationListReceiver<\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION + +DESCRIPTION + PFAL specific routine to cancel the ongoing search operation + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type CancelSearchReceiver +( +) +{ + int ret; + + ret = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_TAVARUA_SRCHON,0); + if(ret < FALSE) + { + return FM_CMD_FAILURE; + } + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION GetSINRSamples + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR sample + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRSamples +( + +) +{ + int err,value=0; + err = vendor_interface->get_fm_ctrl(V4L2_CID_PRIVATE_SINR_SAMPLES,&value); + if( err < 0 ) + { + print("Failed to get the SINR samples"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.sinr_samples = value; + print2("Successfully get the SINR samples %d\n", value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetSINRSamples + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR sample + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSINRSamples +( + uint8 sinr_sample +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_SINR_SAMPLES; + control.value = sinr_sample; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_SINR_SAMPLES, sinr_sample); + if( err < 0 ) + { + print("Failed to set the SINR samples\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the SINR samples %d\n", sinr_sample); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION GetSINRThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's SINR Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetSINRThreshold +( + +) +{ + int err,value=0; + err = vendor_interface->get_fm_ctrl(V4L2_CID_PRIVATE_SINR_THRESHOLD, + &value); + if( err < 0 ) + { + print("Failed to get the SINR threshold\n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.sinr_threshold = value; + print2("Successfully get the SINR threshold %d\n", value); + return FM_CMD_SUCCESS; + } +} + + +/*=========================================================================== +FUNCTION SetSINRThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's SINR Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type SetSINRThreshold +( + char sinr_th +) +{ + int err,value; + value = (int)sinr_th; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_SINR_THRESHOLD, + sinr_th); + if( err < 0 ) + { + print("Failed to set the SINR threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the SINR threshold %d\n", sinr_th); + return FM_CMD_SUCCESS; + } +} + + +/*=========================================================================== +FUNCTION GetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's On channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOnChannelThreshold +( + +) +{ + int err,value=0; + + err = vendor_interface->get_fm_ctrl(V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, + &value); + if( err < 0 ) + { + print("Failed to get the On channel threshold \n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.On_channel_threshold = value; + print2("Successfully get the On channel threshold %d\n",value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetOnChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's On channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOnChannelThreshold +( + uint8 on_channel_th +) +{ + int err; + + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, on_channel_th); + if( err < 0 ) + { + print("Failed to set the On channel threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the On channel threshold %d\n", on_channel_th); + return FM_CMD_SUCCESS; + } +} +/*=========================================================================== +FUNCTION GetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to get the FM receiver's Off channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type GetOffChannelThreshold +( + +) +{ + int err,value=0; + + err = vendor_interface->get_fm_ctrl(V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, + &value); + if( err < 0 ) + { + print("Failed to get the Off channel threshold \n"); + return FM_CMD_FAILURE; + } + else + { + fm_global_params.Off_channel_threshold = value; + print2("Successfully get the Off channel threshold %d\n",value); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION SetOffChannelThreshold + +DESCRIPTION + PFAL specific routine to set the FM receiver's Off channel Threshold + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ + +fm_cmd_status_type SetOffChannelThreshold +( + uint8 off_channel_th +) +{ + int err; + struct v4l2_control control; + + control.id = V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD; + control.value = off_channel_th; + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, + off_channel_th); + if( err < 0 ) + { + print("Failed to set the Off channel threshold\n"); + return FM_CMD_FAILURE; + } + else + { + print2("Successfully set the Off channel threshold %d\n", off_channel_th); + return FM_CMD_SUCCESS; + } +} + +/*=========================================================================== +FUNCTION get_fm_i2c_path + +DESCRIPTION + Helper function to get the path of i2c based on the board + +DEPENDENCIES + NIL + +RETURN VALUE + Path to the i2c device. NULL in case of failure. + +SIDE EFFECTS + None + +===========================================================================*/ + +/*=========================================================================== +FUNCTION FmBusWriteReceiver + +DESCRIPTION + PFAL specific routine to program the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusWriteReceiver +( +fm_i2c_params writeparams +) +{ + print("FmBusWriteReceiver <\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== +FUNCTION FmBusReadReceiver + +DESCRIPTION + PFAL specific routine to read the FM I2C bus + +DEPENDENCIES + NIL + +RETURN VALUE + FM command status + +SIDE EFFECTS + None + +===========================================================================*/ +fm_cmd_status_type FmBusReadReceiver +( +fm_i2c_params *readparams +) +{ + + print("FmBusReadReceiver <\n"); + return FM_CMD_SUCCESS; +} + +/*=========================================================================== + +FUNCTION ftm_fm_run_mm + +DESCRIPTION + This function is used to run mm-audio-ftm. + +DEPENDENCIES + none + +===========================================================================*/ +void ftm_fm_run_mm(void) { + pid_t pid; + int err = 1; + + printf("entered ftm_fm_run_mm\n"); + pid = fork(); + + if (!pid) { + err = execl(mm_audio_path, mm_audio_path, NULL); + printf("mm module error %d\n", err); + exit(0); + } else if (pid < 0) { + printf("could not create child process to execute mm audio module\n"); + } + return; +} + +/*=========================================================================== + +FUNCTION ftm_fm_audio + +DESCRIPTION + This function is used to load the target based config file and + set the audio output and volume. + +DEPENDENCIES + none + +===========================================================================*/ +fm_cmd_status_type ftm_fm_audio(uint8 source, uint8 volume) { + + char *cmd = NULL; + char vlm[4]; + FILE *sound_card_fp = NULL; + FILE *config_fp = NULL; + char sound_card_name[sound_card_len] = {0}; + char sound_card_info[sound_card_len] = {0}; + char config_path[sound_card_len] = {0}; + char *buffer; + char *config_file = NULL; + size_t len; + ssize_t ret; + int tmp; + fm_cmd_status_type status = FM_CMD_FAILURE; + + printf("Enter ftm_fm_audio\n"); + cmd = (char*) malloc(CMD_len * sizeof(char)); + if (!cmd) { + printf("memory allocation failed\n"); + goto failure; + } + memset(cmd, 0, CMD_len); + + if (strlcat(cmd, "-tc ", CMD_len) >= CMD_len) + goto failure; + + printf("string = %s \n",cmd); + printf("audio_output = %d\n", source); + + buffer = source ? "83 -v " : "74 -v "; + if (strlcat(cmd, buffer, CMD_len) >= CMD_len) + goto failure; + + printf("string = %s \n",cmd); + tmp = snprintf(vlm, sizeof(vlm), "%d", volume); + if (tmp < 0 || sizeof (vlm) <= (size_t)tmp) + goto failure; + if (strlcat(cmd, vlm, CMD_len) >= CMD_len) + goto failure; + + sound_card_fp = fopen("/proc/asound/cards", "r"); + if (!sound_card_fp) { + printf("failed to open sound card. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + + while (fgets(sound_card_info, sizeof(sound_card_info), sound_card_fp) != NULL) { + sscanf(sound_card_info, "%*s%*s%*s%*s%s", sound_card_name); + printf("soundCard Name = %s\n", sound_card_name); + snprintf(config_path, sizeof(config_path), "%s_%s",audio_config, + sound_card_name); + } + fclose(sound_card_fp); + + if (!(config_file = strchr(config_path, '/'))) { + memset(config_path, 0,sizeof(config_path)); + snprintf(config_path, sizeof(config_path), "%s", audio_config); + } else if ((config_fp = fopen(config_file, "r")) == NULL) { + printf("%s file doesn't exist.\n", config_file); + memset(config_path, 0,sizeof(config_path)); + snprintf(config_path, sizeof(config_path), "%s", audio_config); + } + + if (config_fp) + fclose (config_fp); + + printf("Use audio config file %s\n", config_path); + printf("string = %s \n",cmd); + + ftm_audio_fd = open("/data/vendor/misc/audio/ftm_commands", O_RDWR); + if (ftm_audio_fd < 0) { + printf("Failed to open ftm_commands with write. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + printf(" writing config path\n"); + buffer = config_path; + len = strlen(config_path) + 1; + + while (len > 0) { + ret = write(ftm_audio_fd, buffer, len); + if (ret < 0) { + printf("Failed to write config_file. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + len -= ret; + buffer += ret; + } + printf("done write config path\n"); + sleep(1); + printf("writing command for path = 0x%zx \n", strlen(cmd)); + len = strlen(cmd) + 1; + + buffer = cmd; + while (len > 0) { + ret = write(ftm_audio_fd, buffer, strlen(cmd) + 1); + if (ret < 0) { + printf("Failed to write cmd. err: %d (%s)\n", errno, + strerror(errno)); + goto failure; + } + len -= ret; + buffer += ret; + } + printf("done write command for path\n"); + status = FM_CMD_SUCCESS; + // fall through intentional +failure: + if (cmd) + free(cmd); + if (ftm_audio_fd > 0) { + close(ftm_audio_fd); + ftm_audio_fd = -1; + } + return status; +} + +void ftm_fm_enable_slimbus(int val) +{ + int err = 0; + struct timespec* ts; + + printf("++%s val %d\n", __func__, val); + + pthread_mutex_lock(&fm_event_lock); + err = vendor_interface->set_fm_ctrl(V4L2_CID_PRV_ENABLE_SLIMBUS, val); + if (err < 0) + printf("set_fm_ctrl failed for V4L2_CID_PRV_ENABLE_SLIMBUS\n"); + else { + ts = set_time_out(1); + if(ts) { + err = pthread_cond_timedwait(&fm_event_cond, &fm_event_lock, ts); + ALOGD("%s: event received", __func__); + pthread_mutex_unlock(&fm_event_lock); + free(ts); + } + } + pthread_mutex_unlock(&fm_event_lock); + printf("--%s\n", __func__); +} diff --git a/qca/ftm/src/ftm_iot.c b/qca/ftm/src/ftm_iot.c new file mode 100644 index 000000000..7cbff7d91 --- /dev/null +++ b/qca/ftm/src/ftm_iot.c @@ -0,0 +1,544 @@ +/* +*Copyright (c) 2018-2020 Qualcomm Technologies, Inc. +* +*All Rights Reserved. +*Confidential and Proprietary - Qualcomm Technologies, Inc. +*/ + +/* IPQ-QCA402X specific file */ + +#ifdef IPQ_AP_HOST_IOT + +#include +#include +#include +#include +#include +#include + +#include +#include +#include "comdef.h" +#include "diagcmd.h" +#include "ftm_wlan.h" +#include "ftm_dbg.h" +#include "ftm_iot.h" +#ifdef IPQ_AP_HOST_IOT_QCA402X +#include "diag_api.h" +#endif /* IPQ_AP_HOST_IOT_QCA402X */ +#ifdef IPQ_AP_HOST_IOT_IPQ50XX +#include "btdaemon.h" +#endif /* IPQ_AP_HOST_IOT_IPQ50XX */ + +#define NHDLC_TERM 126 +#define NHDLC_VERSION 1 +#define NHDLC_TERM_SIZE 1 +#define FLASH_CMD_ID_POS 1 +#define MAX_BUF_SIZE 2048 +#define WAIT_TIME_MS 100 +#define SUBSYS_CMD_ID_POS 2 +#define RESERVED_CMD_ID 0 +#define DUT_INTERFACE_SELECT 1 +#define DUT_INTERFACE_ID_POS 4 +#define DUT_INTERFACE_SELECT_POS 10 +#define DIAG_HDR_LEN (sizeof(diag_nonhdlc_hdr_t) + NHDLC_TERM_SIZE) +#define FTM_IOT_LOG_HEADER_SIZE sizeof(ftm_iot_log_pkt_type) + +/* Sempahore Timeout Period set for 2 seconds */ +#define SEM_WAIT_TIMEOUT 5 +#define MEMSET_RESET_VALUE 0 +#define DIAG_HEADER_SIZE 12 + +extern void diagpkt_free(void *pkt); + +void print_array(uint8_t *addr, int len) +{ + int i; + int line = 1; + for (i = 0; i < len; i++) { + if (i == (line * 80)) { + DPRINTF(FTM_DBG_TRACE, "\n"); + line++; + } + DPRINTF(FTM_DBG_TRACE, "%02X ", addr[i]); + } + DPRINTF(FTM_DBG_TRACE, "\n"); +} +#ifdef IPQ_AP_HOST_IOT_QCA402X +/*=========================================================================== + FUNCTION iot_thr_func_qca402x + + DESCRIPTION + Continously polls QCA402X for asynchronous data responses and + logs receievd asynchronous data responses to Diag module using + log-submit() + + DEPENDENCIES + NIL + + RETURN VALUE + Returns NULL on failure. Function also exits with NULL return value + when main indicates that this thread should be stopped + + SIDE EFFECTS + NONE + + ===========================================================================*/ +void *iot_thr_func_qca402x(void *hdl) +{ + int bytes = 0; + void *rsp2 = NULL; + int diag_hdr_len = DIAG_HDR_LEN ; + void *new_iot_ftm_rsp2_pkt = NULL; + + if (!hdl) { + DPRINTF(FTM_DBG_ERROR, "Invalid iotd handle\n"); + return NULL; + } + + new_iot_ftm_rsp2_pkt = malloc(MAX_BUF_SIZE); + if (!new_iot_ftm_rsp2_pkt) { + DPRINTF(FTM_DBG_ERROR, "Could not allocate response packet \n"); + return NULL; + } + + while(1) { + + if (thread_stop == 1) { + DPRINTF(FTM_DBG_TRACE, "FTMd: Exiting thread.\n"); + break; + } + + memset(new_iot_ftm_rsp2_pkt, MEMSET_RESET_VALUE, MAX_BUF_SIZE); + sem_wait(&iot_sem); + + /*If we recieve a response from QCA402X, allocate a buffer using diag alloc with correct + subsystem code and length */ + while ((bytes = diag_recv(hdl, (uint8_t *)new_iot_ftm_rsp2_pkt, + MAX_BUF_SIZE, + WAIT_TIME_MS)) >= 0) { + if (bytes > MAX_BUF_SIZE || bytes <= diag_hdr_len) { + DPRINTF(FTM_DBG_ERROR, "Could not allocate async log response packet\n"); + free (new_iot_ftm_rsp2_pkt); + return NULL; + } + + rsp2 = diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, ftm_iot_cmd_code, (bytes - diag_hdr_len)); + if (!rsp2) { + DPRINTF(FTM_DBG_ERROR, "Could not allocate async log response packet\n"); + free (new_iot_ftm_rsp2_pkt); + return NULL; + } + + /* Remove NHDLC header from recieved packet and store contents in + buffer allocated above */ + memcpy(rsp2, (new_iot_ftm_rsp2_pkt + diag_hdr_len - NHDLC_TERM_SIZE), + (bytes - diag_hdr_len)); + + DPRINTF(FTM_DBG_TRACE, "FTMd: Asynchronous Data response has been sent.\n"); + print_array((uint8_t *)rsp2, (bytes - diag_hdr_len) ); + + /*Remove an additional 4 bytes of header and log packet to diag module + asynchronously for further processing*/ + log_submit(rsp2 + diag_hdr_len - NHDLC_TERM_SIZE); + diagpkt_free (rsp2); + memset(new_iot_ftm_rsp2_pkt, MEMSET_RESET_VALUE, MAX_BUF_SIZE); + } + + sem_post(&iot_sem_async); + } + + free (new_iot_ftm_rsp2_pkt); + diagpkt_free (rsp2); + pthread_exit(NULL); +} + +/*=========================================================================== + FUNCTION ftm_iot_dispatch_qca402x + + DESCRIPTION + Function processes WIN IOT specific requests and relays to + QCA402x FTM layer for further processing. Recieves response + buffer from QCA402x and returns buffer meant for diag call back + + This function handles NHDLC to HDLC translation and vice-versa + before sending and receivng buffers to QCA402X FTM layer + + DEPENDENCIES + NIL + + RETURN VALUE + Returns back buffer that is meant for diag callback + + SIDE EFFECTS + NONE + + ===========================================================================*/ + +void *ftm_iot_dispatch_qca402x(void *iot_ftm_pkt, int pkt_len, void *hdl) +{ + int diag_hdr_len = DIAG_HDR_LEN; + int ret = 0; + byte *payload_ptr = NULL; + void *rsp1 = NULL; + ftm_iot_req_pkt_type *new_iot_ftm_pkt = NULL; + void *new_iot_ftm_rsp_pkt = NULL; + char command[50] = {'\0'}; + uint16_t *ftm_iot_flash_ptr = NULL; + uint16 ftm_iot_flash_cmd_code = 0; + /* The new packet length will be length of original request packet + + size of NHDLC header + 1 byte of termination character */ + int new_pkt_len = pkt_len + diag_hdr_len; + + if (!iot_ftm_pkt || !pkt_len || !hdl) { + DPRINTF(FTM_DBG_ERROR, "Invalid ftm iot request packet or iotd handle\n"); + return NULL; + } + + new_iot_ftm_pkt = malloc(sizeof(ftm_iot_req_pkt_type) + pkt_len + NHDLC_TERM_SIZE); + if (!new_iot_ftm_pkt) { + DPRINTF(FTM_DBG_ERROR, "Could not create new ftm iot request packet\n"); + return NULL; + } + memset(new_iot_ftm_pkt, MEMSET_RESET_VALUE, (sizeof(ftm_iot_req_pkt_type) + pkt_len + NHDLC_TERM_SIZE)); + + new_iot_ftm_rsp_pkt = malloc(MAX_BUF_SIZE); + if (!new_iot_ftm_rsp_pkt) { + DPRINTF(FTM_DBG_ERROR, "Could not create new ftm iot response packet\n"); + free (new_iot_ftm_pkt); + return NULL; + } + memset(new_iot_ftm_rsp_pkt, MEMSET_RESET_VALUE, MAX_BUF_SIZE); + + /* Add Non-HDLC header to request packet + and populate NHDLC header*/ + new_iot_ftm_pkt->hdr.start = NHDLC_TERM; + new_iot_ftm_pkt->hdr.version = NHDLC_VERSION; + new_iot_ftm_pkt->hdr.length = pkt_len; + memcpy(&(new_iot_ftm_pkt->payload), iot_ftm_pkt, pkt_len); + payload_ptr = (byte *) &(new_iot_ftm_pkt->payload); + *( payload_ptr + pkt_len) = NHDLC_TERM; + ftm_iot_cmd_code = *(payload_ptr + SUBSYS_CMD_ID_POS); + ftm_iot_dut_interface_code = *(payload_ptr + DUT_INTERFACE_ID_POS); + ftm_iot_reserved_code = *(payload_ptr + SUBSYS_CMD_ID_POS + 1); + ftm_iot_flash_ptr = (uint16_t *) &(new_iot_ftm_pkt->payload); + ftm_iot_flash_cmd_code = *(ftm_iot_flash_ptr + FLASH_CMD_ID_POS); + /*Print packet after adding headers */ + DPRINTF(FTM_DBG_TRACE, "FTMd: Request Packet of size %d bytes sent:\n", new_pkt_len); + print_array((uint8_t *)new_iot_ftm_pkt, new_pkt_len); + + /*If the request packet it a DUT interface selection command, + update interface number and return a response packet that + is an encho of the request packet. ( In the case of multiple + QCA402x DUT attaches on IPQ platforms) */ + if (((ftm_iot_cmd_code == MFG_CMD_ID_BLE_HCI) || (ftm_iot_cmd_code == MFG_CMD_ID_I15P4_HMI)) + && (ftm_iot_dut_interface_code == DUT_INTERFACE_SELECT) + && (ftm_iot_reserved_code == RESERVED_CMD_ID)){ + interface = *(payload_ptr + DUT_INTERFACE_SELECT_POS) - 1; + if (interface < 0) { + DPRINTF(FTM_DBG_ERROR, "Invalid DUT interface selection command\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + rsp1 = diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, ftm_iot_cmd_code, pkt_len); + if (!rsp1){ + DPRINTF(FTM_DBG_ERROR, "Could not allocate response packet for interface selection\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + memcpy(rsp1, iot_ftm_pkt, pkt_len); + + DPRINTF(FTM_DBG_TRACE, "FTMd: The DUT interface selected is %d \n",interface); + DPRINTF(FTM_DBG_TRACE, "FTMd: DUT interface resp packet of size %d bytes sent:\n",pkt_len); + print_array((uint8_t *)rsp1, pkt_len); + + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + + /*This resp pointer will be freed by diag later*/ + return rsp1; + } + + /*If the request packet is a MFG PROG command, + launch flash script and return a response packet that indicates + flashing mode of QCA402x is enabled or disabled */ + if ((ftm_iot_flash_cmd_code == MFG_CMD_ID_MISC_PROG_MODE)){ + + if (ftm_iot_dut_interface_code == MFG_FLASH_ON){ + strlcpy(command, "/usr/bin/qca402x_flash.sh flash on", sizeof(command)); + } + + if (ftm_iot_dut_interface_code == MFG_FLASH_OFF){ + strlcpy(command, "/usr/bin/qca402x_flash.sh flash off", sizeof(command)); + } + + if (ftm_iot_dut_interface_code == MFG_USB_OFF){ + strlcpy(command, "/usr/bin/qca402x_flash.sh usb-select off", sizeof(command)); + } + + if (ftm_iot_dut_interface_code == MFG_USB_ON){ + strlcpy(command, "/usr/bin/qca402x_flash.sh usb-select on", sizeof(command)); + } + + if (ftm_iot_dut_interface_code == MFG_EDL_OFF){ + strlcpy(command, "/usr/bin/qca402x_flash.sh edl off", sizeof(command)); + } + + if (ftm_iot_dut_interface_code == MFG_EDL_ON){ + strlcpy(command, "/usr/bin/qca402x_flash.sh edl on", sizeof(command)); + } + + /*Return with NULL if string is empty or packet length is less than + 10 for a DUT interface selection command to make sure there will be + no out of bound access */ + if ( (command[0] == '\0') || (pkt_len <= DUT_INTERFACE_ID_POS) ) { + DPRINTF(FTM_DBG_ERROR, "Error: Invalid MFG Program command\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + system(command); + DPRINTF(FTM_DBG_TRACE, "\n FTMd: Sent system command: %s \n", command); + + /* Check of size for packet pointed to by payload_ptr has been done above + using pkt_len to make sure there is no out of bound access */ + + *(payload_ptr + DUT_INTERFACE_ID_POS) = MFG_PROG_RESP; + + rsp1 = diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, ftm_iot_cmd_code, pkt_len); + if (!rsp1){ + DPRINTF(FTM_DBG_ERROR, "Could not allocate response packet for MFG flash commands\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + memcpy(rsp1, payload_ptr, pkt_len); + + DPRINTF(FTM_DBG_TRACE, "FTMd: MFG Flash resp packet of size %d bytes sent:\n",pkt_len); + print_array((uint8_t *)rsp1, pkt_len); + + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + + /*This resp pointer will be freed by diag later*/ + return rsp1; + } + + sem_wait(&iot_sem_async); + /* Call IPQ-QCA402x diag APIs */ + ret = diag_send(hdl, interface, (uint8_t *)new_iot_ftm_pkt, new_pkt_len); + if ((ret < 0) || (ret > MAX_BUF_SIZE)) { + DPRINTF(FTM_DBG_ERROR, "Could not send the request packet to QCA402x \n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + ret = diag_recv(hdl, (uint8_t *)new_iot_ftm_rsp_pkt, MAX_BUF_SIZE, WAIT_TIME_MS); + if ((ret < 0) || (ret > MAX_BUF_SIZE) || (ret <= diag_hdr_len)) { + DPRINTF(FTM_DBG_ERROR, "Could not recieve packet from QCA402x\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + DPRINTF(FTM_DBG_TRACE,"Received Command Response of %d bytes\n",ret); + print_array((uint8_t *)new_iot_ftm_rsp_pkt, ret); + + rsp1 = diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, ftm_iot_cmd_code, (ret - diag_hdr_len)); + if (!rsp1){ + DPRINTF(FTM_DBG_ERROR, "Could not allocate response packet\n"); + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + return NULL; + } + + memcpy(rsp1, (new_iot_ftm_rsp_pkt + diag_hdr_len - NHDLC_TERM_SIZE), (ret - diag_hdr_len)); + + free (new_iot_ftm_pkt); + free (new_iot_ftm_rsp_pkt); + sem_post(&iot_sem); + + /*This resp pointer will be freed by diag module later*/ + return (void *)rsp1; +} +#endif /* IPQ_AP_HOST_IOT_QCA402X */ + +#ifdef IPQ_AP_HOST_IOT_IPQ50XX +/*=========================================================================== + FUNCTION iot_thr_func_ipq50xx + + DESCRIPTION + Continously polls IPQ50XX BTSS for asynchronous data responses and + logs received asynchronous data responses to Diag module using + log-submit() + + DEPENDENCIES + NIL + + RETURN VALUE + Returns NULL on failure. Function also exits with NULL return value + when main indicates that this thread should be stopped + + SIDE EFFECTS + NONE + +===========================================================================*/ + +void *iot_thr_func_ipq50xx(void *hdl) +{ + int bytes_read = 0, handle = 0; + void *buffer = NULL; + void *rsp = NULL; + struct timespec ts; + ftm_bt_rsp_pkt_type *ftm_async_pkt; + + buffer = malloc(MAX_BUF_SIZE); + if (!buffer) + { + DPRINTF(FTM_DBG_ERROR, "Could not allocate memory to the buffer \n"); + return NULL; + } + + memset(buffer, MEMSET_RESET_VALUE, MAX_BUF_SIZE); + + if(hdl == NULL || *((int*)hdl) < 0) + { + DPRINTF(FTM_DBG_ERROR, "\n Invalid Handle received from BTSS \n"); + free(buffer); + return NULL; + } + + handle = *((int*)hdl); + while(1) + { + if (thread_stop == 1) { + DPRINTF(FTM_DBG_TRACE, "FTMd: Exiting thread.\n"); + break; + } + + if (clock_gettime(CLOCK_REALTIME, &ts) == -1) + { + DPRINTF(FTM_DBG_ERROR, "clock_gettime"); + free(buffer); + return NULL; + } + ts.tv_sec += SEM_WAIT_TIMEOUT; + sem_timedwait(&iot_sem, &ts); + while((bytes_read = bt_daemon_receive(handle, &buffer)) > 0) + { + rsp = log_alloc(LOG_BT_HCI_EV_C, (DIAG_HEADER_SIZE + bytes_read)); + if (!rsp) + { + DPRINTF(FTM_DBG_ERROR, "Could not allocate rsp packet \n"); + free(buffer); + return NULL; + } + + ftm_async_pkt = (ftm_bt_rsp_pkt_type*)rsp; + memcpy(ftm_async_pkt->buf, buffer, bytes_read); + DPRINTF(FTM_DBG_TRACE, "\n Printing the Async Packet sent to QDART\n"); + print_array((uint8_t *)rsp, (DIAG_HEADER_SIZE + bytes_read)); + + log_submit(rsp); + log_free(rsp); + memset(buffer, MEMSET_RESET_VALUE, MAX_BUF_SIZE); + } + sem_post(&iot_sem_async); + } + free(buffer); + pthread_exit(NULL); +} +/*=========================================================================== + FUNCTION ftm_iot_dispatch_ipq50xx + + DESCRIPTION + Function processes WIN IOT specific requests and relays to + IPQ50XX BTSS for further processing. Constructs response packet + and returns buffer meant for callback. + + DEPENDENCIES + NIL + + RETURN VALUE + Returns back buffer that is meant for diag callback + + SIDE EFFECTS + NONE + + ===========================================================================*/ + +void *ftm_iot_dispatch_ipq50xx(void *iot_ftm_pkt, int pkt_len, int *hdl) +{ + void *rsp = NULL; + struct timespec ts; + int bytes_sent = -1; + + if(hdl == NULL || *hdl < 0) + { + DPRINTF(FTM_DBG_ERROR, "\n Invalid Handle received from BTSS \n"); + return NULL; + } + + if (!iot_ftm_pkt) + { + DPRINTF(FTM_DBG_ERROR, "Invalid iot_ftm_pkt received \n"); + return NULL; + } + + if (clock_gettime(CLOCK_REALTIME, &ts) == -1) + { + perror("clock_gettime"); + return NULL; + } + ts.tv_sec += SEM_WAIT_TIMEOUT; + sem_timedwait(&iot_sem_async, &ts); + + DPRINTF(FTM_DBG_TRACE, "\n Request Packet received for IPQ50xx BTSS\n"); + print_array((uint8_t *)iot_ftm_pkt, pkt_len); + + bytes_sent = bt_daemon_send(*hdl, iot_ftm_pkt); + if(bytes_sent < 0) + { + perror("Unable to send Request Packet to IPQ50xx BTSS"); + return NULL; + } + + /* Constructing ACK Packet */ + rsp = diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, ftm_iot_cmd_code, pkt_len); + if (!rsp) + { + DPRINTF(FTM_DBG_ERROR, "\n Unable to allocate diag response packet \n"); + return NULL; + } + + memcpy(rsp, iot_ftm_pkt, pkt_len); + + DPRINTF(FTM_DBG_TRACE, "\n ACK Packet constructed in FTM layer\n"); + print_array((uint8_t *)rsp, pkt_len); + + sem_post(&iot_sem); + + /*This rsp pointer will be freed by diag later */ + return rsp; +} +#endif /* IPQ_AP_HOST_IOT_IPQ50XX */ + +void *ftm_iot_dispatch(void *iot_ftm_pkt, int pkt_len, void *hdl) +{ + void* retValue = NULL; +#ifdef IPQ_AP_HOST_IOT_QCA402X + retValue = ftm_iot_dispatch_qca402x(iot_ftm_pkt, pkt_len ,hdl); +#endif +#ifdef IPQ_AP_HOST_IOT_IPQ50XX + retValue = ftm_iot_dispatch_ipq50xx(iot_ftm_pkt, pkt_len ,(int *)hdl); +#endif + return retValue; +} + +#endif /*ifdef IPQ_AP_HOST_IOT*/ diff --git a/qca/ftm/src/ftm_iot.h b/qca/ftm/src/ftm_iot.h new file mode 100644 index 000000000..435a701fb --- /dev/null +++ b/qca/ftm/src/ftm_iot.h @@ -0,0 +1,131 @@ +/* + *Copyright (c) 2018-2020 Qualcomm Technologies, Inc. + * + *All Rights Reserved. + *Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +/* IPQ-QCA402X specific file */ +#ifdef IPQ_AP_HOST_IOT + +#include +#include +#include "diagpkt.h" +#include "log.h" + +#define MFG_CMD_ID_BLE_HCI 4 +#define MFG_CMD_ID_I15P4_HMI 5 +#define MFG_CMD_ID_OTP_INVALID 256 +#define MFG_CMD_ID_OTP_SET_BITS 257 +#define MFG_CMD_ID_OTP_WRITE_BYTE 258 +#define MFG_CMD_ID_OTP_READ_BYTE 259 +#define MFG_CMD_ID_OTP_TLV_INIT 260 +#define MFG_CMD_ID_OTP_TLV_READ 261 +#define MFG_CMD_ID_OTP_TLV_WRITE 262 +#define MFG_CMD_ID_OTP_TLV_STATUS 263 +#define MFG_CMD_ID_OTP_TLV_DELETE 264 + +#define MFG_CMD_ID_RAWFLASH_INVALID 288 +#define MFG_CMD_ID_RAWFLASH_CLEAR_BITS 289 +#define MFG_CMD_ID_RAWFLASH_WRITE 290 +#define MFG_CMD_ID_RAWFLASH_READ 291 +#define MFG_CMD_ID_RAWFLASH_ERASE 292 +#define MFG_CMD_ID_RAWFLASH_DISABLE_MFG 293 + +#define MFG_CMD_ID_FS_INVALID 304 +#define MFG_CMD_ID_FS_READ 305 +#define MFG_CMD_ID_FS_WRITE 306 +#define MFG_CMD_ID_FS_DELETE 307 +#define MFG_CMD_ID_FS_LIST_SETUP 308 +#define MFG_CMD_ID_FS_LIST_NEXT 309 +#define MFG_CMD_ID_FS_MOUNT 310 +#define MFG_CMD_ID_FS_UNMOUNT 311 + +/* Add more MFG tool commands for QCA402x. These +command are interpreted internally within QCA402x */ +#define MFG_CMD_ID_MISC_REBOOT 352 +#define MFG_CMD_ID_MISC_ADDR_READ 353 +#define MFG_CMD_ID_MISC_ADDR_WRITE 354 +#define MFG_CMD_ID_MISC_HWSS_DONE 355 +#define MFG_CMD_ID_MISC_XTAL_CAP_SET 356 +#define MFG_CMD_ID_MISC_PART_SZ_GET 357 + +/* Add MFG tool command to enable flashing of QCA402x +by putting QCA402x in EDL mode and selecting USB mux +select option to tie USB port 81 on IPQ402x to QCA402x */ +#define MFG_CMD_ID_MISC_PROG_MODE 358 + +/*Command to invalidate specified QCA402x Imageset */ +#define MFG_CMD_ID_MISC_FWUP 359 +/* Add MFG tool PROG_MODE subcommands to enable flashing +of QCA402x on IPQ807x. Interpretation of sub-commands is as +follows: + +MFG_FLASH_ON - Put QCA402x into reset state, Put QCA402x in +EDL mode and enable USB port to be tied to QCA402x + +MFG_FLASH_OFF - Pull QCA402x out of EDL mode and Pull QCA402x +out of reset + +MFG_EDL_ON - Put QCA402x in EDL mode + +MFG_FLASH_OFF - Pull QCA402x out of EDL mode + +MFG_USB_ON - Enable USB port to be tied to QCA402x + +MFG_USB_OFF - Enable USB port to be tied to IPQ807x + +MFG_PROG_RESP - Expected response field +*/ + +enum flash_state { + MFG_PROG_RESP, + MFG_FLASH_ON, + MFG_FLASH_OFF, + MFG_EDL_ON, + MFG_EDL_OFF, + MFG_USB_ON, + MFG_USB_OFF +}; + +typedef struct +{ + uint8 start; + uint8 version; + uint16 length; +} PACKED_STRUCT diag_nonhdlc_hdr_t; + +typedef struct +{ + diag_nonhdlc_hdr_t hdr; + byte payload[0]; +} PACKED_STRUCT ftm_iot_req_pkt_type; + +typedef struct +{ + log_hdr_type hdr; + byte buf[1]; +} PACKED_STRUCT ftm_bt_rsp_pkt_type; + +/* Two semaphores are used to handle sequencing of requests, ack responses +and multiple asynchronous data responses from QCA402x */ + +sem_t iot_sem; +sem_t iot_sem_async; + +int ftm_iot_cmd_code; +int ftm_iot_dut_interface_code; +int ftm_iot_reserved_code; +int interface; +int thread_stop; + +void *ftm_iot_dispatch(void *iot_ftm_pkt, int pkt_len, void *hdl); +#ifdef IPQ_AP_HOST_IOT_QCA402X +void *ftm_iot_dispatch_qca402x(void *iot_ftm_pkt, int pkt_len, void *hdl); +void *iot_thr_func_qca402x(void *hdl); +#endif +#ifdef IPQ_AP_HOST_IOT_IPQ50XX +void *ftm_iot_dispatch_ipq50xx(void *iot_ftm_pkt, int pkt_len, int *hdl); +void *iot_thr_func_ipq50xx(void *hdl); +#endif +#endif /*ifdef IPQ_AP_HOST_IOT*/ diff --git a/qca/ftm/src/ftm_main.c b/qca/ftm/src/ftm_main.c new file mode 100644 index 000000000..1a487ebc8 --- /dev/null +++ b/qca/ftm/src/ftm_main.c @@ -0,0 +1,1033 @@ +/* Copyright (c) 2010-2020 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. +*/ + +/*========================================================================== + + FTM Main Task Source File + +Description + Unit test component file for regsitering the routines to Diag library + for BT and FTM commands + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/18/10 rakeshk Created a source file to implement routines for + registering the callback routines for FM and BT FTM + packets +07/06/10 rakeshk changed the name of FM common header file in inclusion +07/07/10 rakeshk Removed the sleep and wake in the main thread loop +===========================================================================*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifndef WIN_AP_HOST +#include +#endif +#include +#include +#ifndef WIN_AP_HOST +#include +#endif +#ifndef ANDROID +#include +#include +#endif +#ifndef WIN_AP_HOST +#include "hidl_client.h" +#endif +/* Diag related header files */ +#include "event.h" +#include "msg.h" +#include "log.h" +#include "diag_lsm.h" +#include "diagpkt.h" +#include "diagcmd.h" +#include "diag.h" + +#ifdef WIN_AP_HOST_OPEN +#include "signal.h" +#include "libtcmd.h" +#endif +#include "ftm_dbg.h" +#include "ftm_wlan.h" +#include "ftm_common.h" +#include "ftm_ant_common.h" +#ifndef WIN_AP_HOST +#ifdef CONFIG_FTM_BT +#include "ftm_bt_hci_pfal.h" +#endif +#ifdef CONFIG_FTM_FM +#include "ftm_fm_pfal.h" +#endif + +#include "ftm_nfc.h" +#endif +#ifdef USE_GLIB +#include +#define strlcat g_strlcat +#define strlcpy g_strlcpy +#endif + +#ifdef IPQ_AP_HOST_IOT +#include +#include "ftm_iot.h" +#ifdef IPQ_AP_HOST_IOT_QCA402X +#include "diag_api.h" +#endif /* Including IPQ-QCA402x specific headerfiles */ +#endif + +extern void hidl_client_close(); +int boardtype = 8660; +int first_ant_command; + +int fm_passthrough = 0; +int sibs_enabled = 0; +static char *progname = NULL; + +unsigned int g_dbg_level = FTM_DBG_DEFAULT; + +#define SHOW_PRIO 1 +#define SHOW_TIME 2 +#define SHOW_POLICY 4 +#define SHOW_CPU 8 +#define SHOW_MACLABEL 16 +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(*a)) + +#ifndef WIN_AP_HOST +#ifndef ANDROID +#define SOCKETNAME "/etc/bluetooth/btprop" +static int sk; +#endif +#endif + +#ifdef CONFIG_FTM_BT +/* Semaphore to monitor the completion of +* the queued command before sending down the +* next HCI cmd +*/ +sem_t semaphore_cmd_complete; +/* Semaphore to monitor whether a command +* is queued before proceeding to dequeue +* the HCI packet +*/ +sem_t semaphore_cmd_queued; + +typedef enum { + BT_SOC_DEFAULT = 0, + BT_SOC_SMD = BT_SOC_DEFAULT, + BT_SOC_AR3K, + BT_SOC_ROME, + BT_SOC_CHEROKEE, + BT_SOC_NAPIER, + /* Add chipset type here */ + BT_SOC_RESERVED +} bt_soc_type; + +int soc_type; + +/* Diag pkt table for BT */ +static const diagpkt_user_table_entry_type bt_ftm_diag_func_table[] = +{ + {FTM_BT_CMD_CODE, FTM_BT_CMD_CODE, bt_ftm_diag_dispatch}, +}; +#endif /* CONFIG_FTM_BT */ + +#ifdef DEBUG +void current_time() +{ + + struct timeval curTime; + time_t now; + int milli, usec; + struct tm timeinfo; + char buffer[80]; + char currentTime[84] = ""; + gettimeofday(&curTime, NULL); + now = curTime.tv_sec; + milli = curTime.tv_usec / 1000; + usec = curTime.tv_usec; + localtime_r(&now, &timeinfo); + strftime(buffer, sizeof(buffer), "%Y-%m-%d %H:%M:%S", &timeinfo); + snprintf(currentTime, sizeof(currentTime), "%s:%03d:%06d", buffer, milli, usec); + DPRINTF(FTM_DBG_TRACE, "Time:%s\n", currentTime); + +} +#endif /* DEBUG */ + + + +#ifdef CONFIG_FTM_FM +/* Callback declaration for BT FTM packet processing */ +void *fm_ftm_diag_dispatch (void *req_pkt, uint16 pkt_len); + +/* Diag pkt table for FM */ +static const diagpkt_user_table_entry_type fm_ftm_diag_func_table[] = +{ + {FTM_FM_CMD_CODE, FTM_FM_CMD_CODE, fm_ftm_diag_dispatch}, +}; +#endif /* CONFIG_FTM_FM */ + +#ifdef CONFIG_FTM_ANT +/* Callback declaration for ANT FTM packet processing */ +void *ant_ftm_diag_dispatch(void *req_pkt, uint16 pkt_len); + +/*Diag pkt table for ANT */ +static const diagpkt_user_table_entry_type ant_ftm_diag_func_table[] = +{ + {FTM_ANT_CMD_CODE, FTM_ANT_CMD_CODE, ant_ftm_diag_dispatch} +}; +#endif /* CONFIG_FTM_ANT */ + +#ifdef CONFIG_FTM_WLAN +/* Callback declaration for WLAN FTM packet processing */ +void * wlan_ftm_diag_dispatch (void *req_pkt, + uint16 pkt_len); + +/* Diag pkt table for WLAN */ +static const diagpkt_user_table_entry_type wlan_ftm_diag_func_table[] = +{ + {FTM_WLAN_CMD_CODE, FTM_WLAN_CMD_CODE, wlan_ftm_diag_dispatch} +}; +#endif + +#ifdef IPQ_AP_HOST_IOT +/*IPQ-QCA402x specific diag API handler*/ +void *iotd_desc; +#ifdef IPQ_AP_HOST_IOT_IPQ50XX +int btss_desc; +extern int btss_init(); +extern void btss_deinit(); +#endif /* IPQ_AP_HOST_IOT_IPQ50XX */ +/* Callback declaration for IPQ-QCA402x FTM packet processing */ +void *iot_ftm_diag_dispatch (void *req_pkt, + uint16 pkt_len); + + + /* Diag pkt table for IPQ-QCA402X */ + static const diagpkt_user_table_entry_type iot_ftm_diag_func_table[] = + { + {MFG_CMD_ID_BLE_HCI, MFG_CMD_ID_BLE_HCI, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_I15P4_HMI, MFG_CMD_ID_I15P4_HMI, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_WRITE_BYTE, MFG_CMD_ID_OTP_WRITE_BYTE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_READ_BYTE, MFG_CMD_ID_OTP_READ_BYTE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_INVALID, MFG_CMD_ID_OTP_INVALID, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_SET_BITS, MFG_CMD_ID_OTP_SET_BITS, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_TLV_INIT, MFG_CMD_ID_OTP_TLV_INIT, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_TLV_READ, MFG_CMD_ID_OTP_TLV_READ, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_TLV_WRITE, MFG_CMD_ID_OTP_TLV_WRITE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_TLV_STATUS, MFG_CMD_ID_OTP_TLV_STATUS, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_OTP_TLV_DELETE, MFG_CMD_ID_OTP_TLV_DELETE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_INVALID, MFG_CMD_ID_FS_INVALID, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_READ, MFG_CMD_ID_FS_READ, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_WRITE, MFG_CMD_ID_FS_WRITE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_DELETE, MFG_CMD_ID_FS_DELETE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_LIST_SETUP, MFG_CMD_ID_FS_LIST_SETUP, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_LIST_NEXT, MFG_CMD_ID_FS_LIST_NEXT, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_MOUNT, MFG_CMD_ID_FS_MOUNT, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_FS_UNMOUNT, MFG_CMD_ID_FS_UNMOUNT, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_REBOOT, MFG_CMD_ID_MISC_REBOOT, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_ADDR_READ, MFG_CMD_ID_MISC_ADDR_READ, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_ADDR_WRITE, MFG_CMD_ID_MISC_ADDR_WRITE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_HWSS_DONE, MFG_CMD_ID_MISC_HWSS_DONE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_XTAL_CAP_SET, MFG_CMD_ID_MISC_XTAL_CAP_SET, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_PART_SZ_GET, MFG_CMD_ID_MISC_PART_SZ_GET, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_PROG_MODE, MFG_CMD_ID_MISC_PROG_MODE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_MISC_FWUP, MFG_CMD_ID_MISC_FWUP, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_INVALID, MFG_CMD_ID_RAWFLASH_INVALID, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_CLEAR_BITS, MFG_CMD_ID_RAWFLASH_CLEAR_BITS, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_READ, MFG_CMD_ID_RAWFLASH_READ, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_WRITE, MFG_CMD_ID_RAWFLASH_WRITE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_ERASE, MFG_CMD_ID_RAWFLASH_ERASE, iot_ftm_diag_dispatch}, + {MFG_CMD_ID_RAWFLASH_DISABLE_MFG, MFG_CMD_ID_RAWFLASH_DISABLE_MFG, iot_ftm_diag_dispatch}, + }; + +#endif /*ifdef IPQ_AP_HOST_IOT*/ + +#ifdef CONFIG_FTM_NFC +/* Callback declaration for NFC FTM packet processing */ +void *nfc_ftm_diag_dispatch (void *req_pkt, uint16 pkt_len); + +/*Diag pkt table for NFC */ +static const diagpkt_user_table_entry_type nfc_ftm_diag_func_table[] = +{ + {FTM_NFC_CMD_CODE, FTM_NFC_CMD_CODE, nfc_ftm_diag_dispatch} +}; +#endif /* CONFIG_FTM_NFC */ +#ifdef WIN_AP_HOST_OPEN +static void signal_handler(int32_t signum) +{ + printf("FTM Daemon Exit called signal %d\n", signum ); + tcmd_tx_stop(); + exit(0); +} +#endif + +#ifdef CONFIG_FTM_BT +#ifndef WIN_AP_HOST +#ifndef ANDROID +/* set up Socket connection to btproperty */ +int prop_get(const char *key, char *value, const char *default_value) +{ + char prop_string[200]; + int ret, bytes_read = 0, i = 0; + sprintf(prop_string, "get_property %s,", key); + ret = send(sk, prop_string, strlen(prop_string), 0); + memset(value, 0, sizeof(value)); + do + { + bytes_read = recv(sk, &value[i], 1, 0); + if (bytes_read == 1) + { + if (value[i] == ',') + { + value[i] = '\0'; + break; + } + i++; + } + } while(1); + ALOGI("property_get_bt: key(%s) has value: %s", key, value); + if (bytes_read) { + return 0; + } else { + strncpy(value, default_value, strlen(default_value)); + return 1; + } +} + +int prop_set(const char *key, const char *value) +{ + char prop_string[200]; + int ret; + sprintf(prop_string, "set_property %s %s,", key, value); + ALOGI("property_set_bt: setting key(%s) to value: %s\n", key, value); + ret = send(sk, prop_string, strlen(prop_string), 0); + return 0; +} + +int bt_property_init(void) +{ + int len; /* length of sockaddr */ + struct sockaddr_un name; + if( (sk = socket(AF_UNIX, SOCK_STREAM, 0) ) < 0) { + perror("socket"); + exit(1); + } + /*Create the address of the server.*/ + memset(&name, 0, sizeof(struct sockaddr_un)); + name.sun_family = AF_UNIX; + strlcpy(name.sun_path, SOCKETNAME, sizeof(name.sun_path)); + ALOGI("connecting to %s, fd = %d", SOCKETNAME, sk); + len = sizeof(name.sun_family) + strlen(name.sun_path); + /*Connect to the server.*/ + if (connect(sk, (struct sockaddr *) &name, len) < 0){ + perror("connect"); + exit(1); + } +#if (BT_SOC_TYPE_ROME || BT_SOC_TYPE_CHEROKEE) + prop_set("qcom.bluetooth.soc", "rome"); +#else + prop_set("qcom.bluetooth.soc", "pronto"); +#endif +} +#endif + +/* Get Bluetooth SoC type from system setting */ +static int get_bt_soc_type(void) +{ + int ret = 0; + char bt_soc_type[PROPERTY_VALUE_MAX]; + + ALOGI("bt-hci: get_bt_soc_type"); +#ifdef ANDROID + ret = property_get("qcom.bluetooth.soc", bt_soc_type, NULL); + if (ret != 0) { +#else + ret = prop_get("qcom.bluetooth.soc", bt_soc_type, NULL); + if (ret == 0) { +#endif + ALOGI("qcom.bluetooth.soc set to %s\n", bt_soc_type); + if (!strncasecmp(bt_soc_type, "rome", sizeof("rome"))) { + return BT_SOC_ROME; + } + else if (!strncasecmp(bt_soc_type, "cherokee", sizeof("cherokee"))) { + return BT_SOC_CHEROKEE; + } + else if (!strncasecmp(bt_soc_type, "pronto", sizeof("pronto"))) { + return BT_SOC_DEFAULT; + } + else if (!strncasecmp(bt_soc_type, "ath3k", sizeof("ath3k"))) { + return BT_SOC_AR3K; + } + else if(!strncasecmp(bt_soc_type, "napier", sizeof("napier"))) { + return BT_SOC_NAPIER; + } + else { + ALOGI("qcom.bluetooth.soc not set, so using default.\n"); + return BT_SOC_DEFAULT; + } + } + else { + ALOGE("%s: Failed to get soc type", __FUNCTION__); + ret = BT_SOC_DEFAULT; + } + + return ret; +} +#endif //ifndef WIN_AP_HOST +#endif //ifdef CONFIG_FTM_BT + +/*=========================================================================== +FUNCTION ioctl_write + +DESCRIPTION + Helper function to package the ioctl messages and send it to the I2C driver + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ + +static int ioctl_readwrite(int fd, struct i2c_msg *msgs, int nmsgs) +{ + struct i2c_rdwr_ioctl_data msgset = + { + .msgs = msgs, + .nmsgs = nmsgs, + }; + + if ((fd < 0) || (NULL == msgs) || (nmsgs <= 0)) + { + return -1; + } + + if (ioctl(fd, I2C_RDWR, &msgset) < 0) + { + return -1; + } + return 0; +} +/*=========================================================================== +FUNCTION i2c_write + +DESCRIPTION + Helper function to construct the I@C request to be sent to the FM I2C + driver + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ +int i2c_write +( +int fd, +unsigned char offset, +const unsigned char* buf, +unsigned char len, +unsigned int slave_addr +) +{ + unsigned char offset_data[((1 + len) * sizeof(unsigned char))]; + struct i2c_msg msgs[] = + { + [0] = { + .addr = slave_addr, + .flags = 0, + .buf = (void *)offset_data, + .len = (1 + len) * sizeof(*offset_data), + }, + }; + + offset_data[0] = offset; + memcpy(offset_data + 1, buf, len); + + return ioctl_readwrite(fd, msgs, ARRAY_SIZE(msgs)); +} + +/*=========================================================================== +FUNCTION i2c_read + +DESCRIPTION + Helper function to construct the I2C request to read data from the FM I2C + driver + +DEPENDENCIES + NIL + +RETURN VALUE + -1 in failure,positive or zero in success + +SIDE EFFECTS + None + +===========================================================================*/ +int i2c_read +( +int fd, +unsigned char offset, +const unsigned char* buf, +unsigned char len, +unsigned int slave_addr +) +{ + unsigned char offset_data[] = {offset}; + struct i2c_msg msgs[] = + { + [0] = { + .addr = slave_addr, + .flags = 0, + .buf = (void *)offset_data, + .len = sizeof(*offset_data), + }, + [1] = { + .addr = slave_addr, + .flags = I2C_M_RD, + .buf = (void *)buf, + .len = len, + }, + }; + + return ioctl_readwrite(fd, msgs, ARRAY_SIZE(msgs)); +} + +#ifdef CONFIG_FTM_FM +/*========================================================================= +FUNCTION fm_ftm_diag_dispatch + +DESCRIPTION + Processes the request packet and sends it to the FTM FM layer for further + processing + +DEPENDENCIES + NIL + +RETURN VALUE + pointer to FTM FM Response packet + +SIDE EFFECTS + None + +===========================================================================*/ +void *fm_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + + DPRINTF(FTM_DBG_TRACE, "FM I2C Send Response = %d\n",pkt_len); + + // Allocate the same length as the request. + rsp = ftm_fm_dispatch(req_pkt,pkt_len); + return rsp; +} +#endif /* CONFIG_FTM_FM */ + +#ifdef CONFIG_FTM_ANT +/*=========================================================================== +FUNCTION ant_ftm_diag_dispatch + +DESCRIPTION + Processes the request packet and sends it to the FTM ANT layer for further + processing +DEPENDENCIES + NIL + +RETURN VALUE + pointer to FTM ANT Response packet + +SIDE EFFECTS + None + +===========================================================================*/ +void *ant_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + + DPRINTF(FTM_DBG_TRACE, "ANT diag dispatch send response = %d\n", pkt_len); + +// Allocate the same length as the request. + rsp = ftm_ant_dispatch(req_pkt,pkt_len); + return rsp; +} +#endif /* CONFIG_FTM_ANT */ + +#ifdef CONFIG_FTM_BT +/*=========================================================================== +FUNCTION bt_ftm_diag_dispatch + +DESCRIPTION + Processes the request packet and sends it to the FTM BT layer for further + processing + +DEPENDENCIES + NIL + +RETURN VALUE + pointer to FTM BT Response packet + +SIDE EFFECTS + None + +===========================================================================*/ +void *bt_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + boolean status = TRUE; + + DPRINTF(FTM_DBG_TRACE, "Send Response = %d\n",pkt_len); + + // Allocate the same length as the request. + rsp = diagpkt_subsys_alloc (DIAG_SUBSYS_FTM, FTM_BT_CMD_CODE, pkt_len); + + if (rsp != NULL) + { + memcpy ((void *) rsp, (void *) req_pkt, pkt_len); + } + /* Spurious incoming request packets are occasionally received + * by DIAG_SUBSYS_FTM which needs to be ignored and accordingly responded. + * TODO: Reason for these spurious incoming request packets is yet to be + * found, though its always found to be corresponding to this majic + * length of 65532. + */ + if (pkt_len == 65532) + { + printf("\nIgnore spurious DIAG packet processing & respond immediately"); + } + else + { + + DPRINTF(FTM_DBG_TRACE, "Insert BT packet = %d\n", pkt_len); + + /* add the BT packet into the Cmd Queue + * and notify the main thread its queued + */ + status = qinsert_cmd((ftm_bt_pkt_type *)req_pkt); + if(status == TRUE) + sem_post(&semaphore_cmd_queued); + + DPRINTF(FTM_DBG_TRACE, "Insert BT packet done\n"); + + } + return (rsp); +} +#endif /* CONFIG_FTM_BT */ + +#ifdef CONFIG_FTM_WLAN +/*=========================================================================== +FUNCTION wlan_ftm_diag_dispatch + +DESCRIPTION + Processes the request packet and sends it to the FTM WLAN layer for further + processing + +DEPENDENCIES + NIL + +RETURN VALUE + pointer to FTM WLAN Response packet + +SIDE EFFECTS + None + +===========================================================================*/ + +void * wlan_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + + DPRINTF(FTM_DBG_TRACE, "WLAN Send Response = %d\n", pkt_len); + + rsp = ftm_wlan_dispatch(req_pkt, pkt_len); + + return rsp; +} +#endif /* CONFIG_FTM_WLAN */ + +#ifdef IPQ_AP_HOST_IOT + +void *iot_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + rsp = ftm_iot_dispatch(req_pkt, pkt_len ,iotd_desc); + return rsp; +} + +#endif /*IPQ_AP_HOST_IOT*/ + +#ifdef CONFIG_FTM_NFC +/*=========================================================================== +FUNCTION nfcs_ftm_diag_dispatch + +DESCRIPTION + Processes the request packet and sends it to the FTM NFC layer for further + processing +DEPENDENCIES + NIL + +RETURN VALUE + + +SIDE EFFECTS + + +===========================================================================*/ +void *nfc_ftm_diag_dispatch +( + void *req_pkt, + uint16 pkt_len +) +{ + void *rsp = NULL; + boolean status = TRUE; + + DPRINTF(FTM_DBG_TRACE, " NFC Send Response = %d\n",pkt_len); + + /*now send the incoming nfc diag command packet to the nfc ftm layer to + get it processed*/ + rsp = ftm_nfc_dispatch(req_pkt, pkt_len); + + /* send same response as recieved back*/ + return rsp; +} +#endif /* CONFIG_FTM_NFC */ + +static void usage(void) +{ + fprintf(stderr, "\nusage: %s [options] \n" + " -n, --nodaemon do not run as a daemon\n" + " -p, --passthrough FM passthrough mode \n" + " -d show more debug messages (-dd for even more)\n" +#ifdef CONFIG_FTM_BT + " -b, --board-type Board Type\n" +#endif +#ifdef CONFIG_FTM_WLAN + " -i \n" + " --interface=\n" + " wlan adapter name (wlan, eth, etc.) default wlan\n" +#endif +#ifdef CONFIG_FTM_NFC + " -f nfc firmware download\n" + " -t nfc test\n" +#endif + " --help display this help and exit\n" + , progname); + exit(EXIT_FAILURE); +} + +/*=========================================================================== +FUNCTION main + +DESCRIPTION + Initialises the Diag library and registers the PKT table for FM and BT + and daemonises + +DEPENDENCIES + NIL + +RETURN VALUE + NIL, Error in the event buffer will mean a NULL App version and Zero HW + version + +SIDE EFFECTS + None + +===========================================================================*/ + +int main(int argc, char *argv[]) +{ + int c; + static struct option options[] = + { + {"help", no_argument, NULL, 'h'}, +#ifdef CONFIG_FTM_WLAN + {"interface", required_argument, NULL, 'i'}, +#endif +#ifdef CONFIG_FTM_BT + {"board-type", required_argument, NULL, 'b'}, +#endif +#ifdef CONFIG_FTM_NFC + {"firmware-download", no_argument, NULL, 'f'}, + {"nfc-test", no_argument, NULL, 't'}, +#endif + {"nodaemon", no_argument, NULL, 'n'}, + {"passthrough", no_argument, NULL, 'p'}, + {"uart-baudrate", no_argument, NULL, 'u'}, + {"sibs", no_argument, NULL, 's'}, + {0, 0, 0, 0} + }; + int daemonize = 1; + + progname = argv[0]; + + while (1) + { + c = getopt_long(argc, argv, "hdi:npb:ft", options, NULL); + if (c < 0) + break; + + switch (c) + { +#ifdef CONFIG_FTM_WLAN + case 'i': + strlcpy(g_ifname, optarg, IFNAMSIZ); + break; +#endif + case 'n': + daemonize = 0; + break; + case 'p': + fm_passthrough = 1; + daemonize = 0; +#ifndef WIN_AP_HOST + property_set("wc_transport.skip_patch_dload" , "true"); +#endif + break; + case 'd': +#ifdef DEBUG + g_dbg_level = g_dbg_level << 1 | 0x1; +#else + printf("Debugging disabled, please build with -DDEBUG option\n"); + exit(EXIT_FAILURE); +#endif + break; + +#ifdef CONFIG_FTM_BT + case 'b': + boardtype = atoi(optarg); + break; +#endif + +#ifdef CONFIG_FTM_NFC + case 'f': + ftm_nfc_dispatch_nq_fwdl(); + break; + case 't': + ftm_nfc_dispatch_nq_test( argc, argv); + break; +#endif + + case 'h': + default: + usage(); + break; + } + } + + if (optind < argc) + usage(); + + if (daemonize && daemon(0, 0)) + { + perror("daemon"); + exit(EXIT_FAILURE); + } + + DPRINTF(FTM_DBG_TRACE, "FTM Daemon calling LSM init\n"); + + if (!Diag_LSM_Init(NULL)) + { + DPRINTF(FTM_DBG_ERROR, "FTM Daemon: Diag_LSM_Init() failed\n"); + exit(EXIT_FAILURE); + } + + DPRINTF(FTM_DBG_TRACE, "FTMDaemon: Diag_LSM_Init succesful\n"); + +#ifdef CONFIG_FTM_BT +#ifndef WIN_AP_HOST +#ifndef ANDROID + bt_property_init(); +#endif + soc_type = get_bt_soc_type(); +#endif +#endif + +#ifdef CONFIG_FTM_FM + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, fm_ftm_diag_func_table); +#endif + +#ifdef CONFIG_FTM_WLAN + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, wlan_ftm_diag_func_table); +#ifdef WIN_AP_HOST_OPEN + signal(SIGINT, signal_handler); + signal(SIGTERM, signal_handler); +#endif +#endif +#ifdef IPQ_AP_HOST_IOT + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, iot_ftm_diag_func_table); + interface = 0; + thread_stop = 0; + pthread_t *iot_thr = NULL; + iotd_desc = NULL; + +#ifdef IPQ_AP_HOST_IOT_QCA402X + iotd_desc = diag_open("/iotdiag"); +#endif /* IPQ_AP_HOST_IOT_QCA402X */ +#ifdef IPQ_AP_HOST_IOT_IPQ50XX + btss_desc = -1; + btss_desc = btss_init(); + if(btss_desc < 0) + { + DPRINTF(FTM_DBG_ERROR, "FTMd : Unable to fetch BT Devnode Descriptor \n"); + } + else + { + iotd_desc = (void *)(&btss_desc); + } +#endif /* IPQ_AP_HOST_IOT_IPQ50XX */ + if (iotd_desc != NULL) { +#ifdef IPQ_AP_HOST_IOT_QCA402X + DPRINTF(FTM_DBG_ERROR, "FTMd : FTMd has registered a handle with IOTD \n"); +#endif /* IPQ_AP_HOST_IOT_QCA402X */ + sem_init(&iot_sem, 0, 0); + sem_init(&iot_sem_async, 0, 1); + + iot_thr = (pthread_t *)malloc( sizeof(*iot_thr)); + if (!iot_thr) { + DPRINTF(FTM_DBG_ERROR, "Could not create thread for async log packets \n"); + } + else + { +#ifdef IPQ_AP_HOST_IOT_QCA402X + pthread_create(iot_thr, NULL, (void*)iot_thr_func_qca402x, (void *)iotd_desc); +#endif +#ifdef IPQ_AP_HOST_IOT_IPQ50XX + pthread_create(iot_thr, NULL, (void*)iot_thr_func_ipq50xx, (void *)iotd_desc); +#endif + } + } + + if (iotd_desc == NULL) + { + DPRINTF(FTM_DBG_ERROR, "FTMd : IOT Daemon has not been enabled \n"); + } + +#endif /* IPQ_AP_HOST_IOT */ + +#ifdef CONFIG_FTM_ANT + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, ant_ftm_diag_func_table); +#endif + +#ifdef CONFIG_FTM_NFC + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, nfc_ftm_diag_func_table); +#endif + +#ifdef CONFIG_FTM_BT + DIAGPKT_DISPATCH_TABLE_REGISTER( DIAG_SUBSYS_FTM, bt_ftm_diag_func_table); + + sem_init(&semaphore_cmd_complete,0, 1); + sem_init(&semaphore_cmd_queued,0,0); + first_ant_command = 0; + + DPRINTF(FTM_DBG_TRACE, "Initialised the BT FTM cmd queue handlers \n"); + + do + { + struct timespec ts; + int sem_status; + /* We have the freedom to send the first request without wating + * for a command complete + */ + DPRINTF(FTM_DBG_TRACE, + "Wait on cmd complete from the previous command\n"); + if (clock_gettime(CLOCK_REALTIME, &ts) == -1) + printf("get clock_gettime error"); + ts.tv_sec += 5; + /*we wait for 5 secs for a command already queued for + * transmision + */ + sem_status = sem_timedwait(&semaphore_cmd_complete,&ts); + if(sem_status == -1) + { + printf("Command complete timed out\n"); + ftm_bt_err_timedout(); + } + + DPRINTF(FTM_DBG_TRACE, "Waiting on next Cmd to be queued\n"); + + sem_wait(&semaphore_cmd_queued); + dequeue_send(); + } + while(1); +#else /* CONFIG_FTM_BT */ +#ifdef CONFIG_FTM_FM + pthread_cond_init(&fm_event_cond, NULL); + pthread_mutex_init(&fm_event_lock, NULL); +#endif + while (1); +#endif + + DPRINTF(FTM_DBG_TRACE, "\nFTMDaemon Deinit the LSM\n"); +#ifdef CONFIG_FTM_FM + pthread_cond_destroy(&fm_event_cond); + pthread_mutex_destroy(&fm_event_lock); +#endif + +#ifdef IPQ_AP_HOST_IOT + if (iotd_desc != NULL) { + thread_stop = 1; + pthread_join(*iot_thr, NULL); + free(iot_thr); +#ifdef IPQ_AP_HOST_IOT_IPQ50XX + btss_deinit(); +#endif + } +#endif /* IPQ_AP_HOST_IOT */ + hidl_client_close(); + /* Clean up before exiting */ + Diag_LSM_DeInit(); + + exit(EXIT_SUCCESS); +} diff --git a/qca/ftm/src/ftm_nfc.c b/qca/ftm/src/ftm_nfc.c new file mode 100644 index 000000000..121aa4aba --- /dev/null +++ b/qca/ftm/src/ftm_nfc.c @@ -0,0 +1,108 @@ +/*========================================================================= + NFC FTM C File +Description + This file contains the definitions of the function used to check + which chip is present on the device. + +Copyright (c) 2013-2015 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ +/*=========================================================================== + Edit History +when who what, where, why +-------- --- ---------------------------------------------------------- +===========================================================================*/ + +#include "ftm_nfc.h" + +CHIP_TYPE chipType = UNDEFINED_CHIP_TYPE; + +/*========================================================================= +FUNCTION checkChip + +DESCRIPTION + Checks whether it can open the NQ Kernel, if not, it means + the device has a QTI chip. + +PARAMETERS + None + +RETURN VALUE + void + +===========================================================================*/ +void checkChip( void ) +{ + int ret = 0; + + ret = ftm_nq_nfc_open( ); // can you open the NQ Kernel? + + if( ret > 0 ) // yes + { + printf( "%s: NQ CHIP \n", __func__ ); + chipType = NQ_CHIP; // so it's an NQ Chip + + ret = ftm_nq_nfc_close( ); // close the handle + if( ret != 0 ) // not successful? + { + printf( "%s: Could not close the File Handle for NQ Chip \n", __func__ ); + chipType = CHIP_ERROR; // something is wrong + } + } + else + { + printf( "%s: QTI CHIP \n", __func__ ); + chipType = QTI_CHIP; + } +} + +/*========================================================================= +FUNCTION ftm_nfc_dispatch + +DESCRIPTION + Dispatches QRCT commands and Chip Replies/Notifications/Data + to the required FTM NFC Chip Handler + +PARAMETERS + ftm_nfc_pkt_type *nfc_ftm_pkt - FTM Packet + uint16 pkt_len - FTM Packet Length + +RETURN VALUE + void * + +===========================================================================*/ +void* ftm_nfc_dispatch( ftm_nfc_pkt_type *nfc_ftm_pkt, uint16 pkt_len ) +{ + ftm_nfc_pkt_type *reply = NULL; + + if( UNDEFINED_CHIP_TYPE == chipType ) + { + printf( "%s: Checking Chip Type \n", __func__ ); + checkChip( ); + } + + switch( chipType ) + { + case NQ_CHIP: + if( nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id == FTM_NFC_REQ_CHIP_TYPE ) + reply = PrepareRsp( nfc_ftm_pkt ); + else + reply = ftm_nfc_dispatch_nq( nfc_ftm_pkt, pkt_len ); + break; + + case QTI_CHIP: + if( nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id == FTM_NFC_REQ_CHIP_TYPE ) + reply = PrepareRsp( nfc_ftm_pkt ); + else + reply = ftm_nfc_dispatch_qti( nfc_ftm_pkt, pkt_len ); + break; + + default: + printf( "%s: ERROR - THIS SHOULD HAVE NEVER BEEN REACHED, CHIP TYPE %d", __func__, chipType ); + break; + } + + return reply; +} diff --git a/qca/ftm/src/ftm_nfc.h b/qca/ftm/src/ftm_nfc.h new file mode 100644 index 000000000..3a48f7541 --- /dev/null +++ b/qca/ftm/src/ftm_nfc.h @@ -0,0 +1,37 @@ +/*========================================================================= + NFC FTM HEADER File +Description + This file contains the definitions of the function used to check + which chip is present on the device. + +Copyright (c) 2013-2016 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ + +#ifndef _FTM_NFC +#define _FTM_NFC + +#include "ftm_nfcnq.h" + +#define NFC_QCA1990 // Defnition to enable the NFC FTM inclusion + +typedef enum _CHIP_TYPE{ + UNDEFINED_CHIP_TYPE = 0, + QTI_CHIP = 1, + NQ_CHIP = 2, + CHIP_ERROR = 3, + MAXIMUM_CHIP_TYPE = 4, +} CHIP_TYPE; + +extern CHIP_TYPE chipType; + +void* ftm_nfc_dispatch(ftm_nfc_pkt_type *ftm_nfc_pkt, uint16 pkt_len); + +void* ftm_nfc_dispatch_qti(ftm_nfc_pkt_type *ftm_nfc_pkt, uint16 pkt_len); + +void ftm_nfc_dispatch_nq_fwdl(); + +void ftm_nfc_dispatch_nq_test(int argc, char **argv); +#endif // _FTM_NFC diff --git a/qca/ftm/src/ftm_nfcnq.c b/qca/ftm/src/ftm_nfcnq.c new file mode 100644 index 000000000..3b1f72573 --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq.c @@ -0,0 +1,807 @@ +/*========================================================================= + NQ NFC FTM C File +Description + This file contains the definitions of the functions + used to communicate with the NQ Chip. + +Copyright (c) 2015-2016 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ +/*=========================================================================== + Edit History +when who what, where, why +-------- --- ---------------------------------------------------------- +===========================================================================*/ + +#include "ftm_nfcnq.h" +#include "ftm_nfc.h" +#include "ftm_nfcnq_fwdl.h" + +/* Global variables */ +pthread_t clientThread; +PNCI_MESSAGE pNCIMessage; +sem_t sRspReady; +int fdNfc = 0; +uint8_t nciReplyMessage[ 255 ] = { 0 }; +NQ_CHIP_TYPE whatNQChip = UNKNOWN_NQ_CHIP_TYPE; +uint8_t RFdeactivateCmd[ ] = { 0x21, 0x06, 0x01, 0x03}; +uint8_t EseDataRsp[ ] = { 0x03, 0x00, 0x21, 0x99, 0x50, 0xFE}; + +/*========================================================================= +FUNCTION ftm_nq_nfc_close + +DESCRIPTION + Close the kernel driver for the NQ Chip + +PARAMETERS + None + +RETURN VALUE + int + +===========================================================================*/ +int ftm_nq_nfc_close( void ) +{ + fdNfc = close( fdNfc ); // close the file descriptor + + LOG_MESSAGE( "%s : Exit with fdNfc = %d \n", __func__, fdNfc ); + + return fdNfc; // return the result +} + +/*========================================================================= +FUNCTION ftm_nq_nfc_open + +DESCRIPTION + Open the kernel driver for the NQ Chip + +PARAMETERS + None + +RETURN VALUE + int + +===========================================================================*/ +int ftm_nq_nfc_open( void ) +{ + fdNfc = open( "/dev/nq-nci", // try to open /dev/nq-nci + O_RDWR ); + + LOG_MESSAGE( "%s : Exit with fdNfc = %d \n", __func__, fdNfc ); + + return fdNfc; // return the result +} + +/*========================================================================= +FUNCTION ftm_nfc_hw_reset + +DESCRIPTION + Resets the NQ Chip + +PARAMETERS + None + +RETURN VALUE + int + +===========================================================================*/ +int ftm_nfc_hw_reset( void ) +{ + + int ret = -1; // return value + + do + { + if( fdNfc < 0 ) // fdNfc valid? + break; + + ret = ioctl( fdNfc, NFC_SET_PWR, POWER_ON ); // turn the chip on + if( ret != 0 ) // successful? + { + LOG_ERROR( "%s ioctl( fdNfc, NFC_SET_PWR, POWER_ON ) returned %d", __func__, ret ); + ret = -2; + break; + } + usleep( 1000 ); // wait + + ret = ioctl( fdNfc, NFC_SET_PWR, POWER_OFF ); // turn the chip off + if( ret != 0 ) // successful? + { + LOG_ERROR( "%s ioctl( fdNfc, NFC_SET_PWR, POWER_OFF ) returned %d", __func__, ret ); + ret = -3; + break; + } + usleep( 1000 ); // wait + + ret = ioctl( fdNfc, NFC_SET_PWR, POWER_ON ); // turn the chip back on + if( ret != 0 ) // successful? + { + LOG_ERROR( "%s ioctl( fdNfc, NFC_SET_PWR, POWER_ON ) returned %d", __func__, ret ); + ret = -4; + break; + } + + }while( 0 ); + + return ret; +} + +/*========================================================================= +FUNCTION PrintBytes + +DESCRIPTION + Print bytes from an array + +PARAMETERS + uint8_t *buf - Byte array to print + uint8_t len - Length of the array +RETURN VALUE + void + +===========================================================================*/ +void PrintBytes( uint8_t *buf, uint8_t len) +{ +#ifdef NFC_FTM_DEBUG + int idx; + + LOG_INFORMATION( "%s: Length: %d bytes \n", __func__, len ); // print the number of bytes + for( idx = 0; idx < len; idx++ ) // print every byte + { + LOG_INFORMATION( "%02x ", buf[idx] ); + } + LOG_INFORMATION( "\n" ); +#else + UNUSED_PARAMETER( buf ); + UNUSED_PARAMETER( len ); +#endif +} + +/*========================================================================= +FUNCTION ftm_nfc_send + +DESCRIPTION + Sends a message to the chip + +PARAMETERS + uint8_t *buf - buffer to be sent + int len - the length of the buffer + +RETURN VALUE + int ret - Status + +===========================================================================*/ +int ftm_nfc_send( uint8_t* buf ) +{ + int ret = -1; // return value + int retries = 15; // number of retries + int i; + uint16_t nciSendMessageLength; + PNCI_MESSAGE pMessageToSend = ( PNCI_MESSAGE ) buf; + pfirmware_download_packet_t pFirmwarePacketsToSend = + ( pfirmware_download_packet_t ) buf; + + + do + { + if( fdNfc < 0 ) // fdNfc valid? + break; + + if( NULL == buf ) // is the buffer valid? + { + ret = -2; + LOG_ERROR( "%s: buf == NULL Invalid Buffer", __func__ ); + break; + } + + if( ( pFirmwarePacketsToSend->fFragmentedPacket == FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_NONE ) || + ( pFirmwarePacketsToSend->fFragmentedPacket == FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_SET ) ) + nciSendMessageLength = pFirmwarePacketsToSend->payloadLen + + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN + + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN; + else + nciSendMessageLength = pMessageToSend->len + offsetof( NCI_MESSAGE, buf ); + + PrintBytes( buf, nciSendMessageLength ); + + do + { + retries--; // retries left + ret = write( fdNfc, + buf, + nciSendMessageLength ); // try to write + + if( ret < nciSendMessageLength ) // did you write the length? + { + LOG_MESSAGE( "%s: %d = write( fdNfc, buf, nciSendMessageLength ), errno = %d, tries left = %d \n", __func__, ret, errno, retries ); + continue; // try again + } + else + break; // done + + } while( retries > 0 ); + } while( 0 ); + + return ret; +} + +/*========================================================================= +FUNCTION ProcessCommand + +DESCRIPTION + Processes a Command for the NQ Chip + +PARAMETERS + uint8_t *nci_data - NCI Data to send + +RETURN VALUE + int ret - 0 if successfully received a reply + +===========================================================================*/ +int ProcessCommand( uint8_t *nci_data ) +{ + int ret = -1; // return value + struct timespec time_sec; + + do + { + LOG_MESSAGE( "%s: FTM_NFC_SEND_DATA \n", __func__ ); + + ret = ftm_nfc_send( nci_data ); // send the message + + LOG_MESSAGE( "%s: Wait for response \n", __func__ ); + + ret = clock_gettime( CLOCK_REALTIME, &time_sec ); + + if( ret == -1 ) + { // didn't get the time? + LOG_ERROR( "%s: clock_gettime for nci_data error \n", __func__ ); + break; + } + + time_sec.tv_sec += FTM_NFC_CMD_CMPL_TIMEOUT; // maximum wait + ret = sem_timedwait( &sRspReady, // start waiting + &time_sec ); + + if( ret == -1 ) // wait finished, not signalled? + { + if(!ese_dwp_test) + LOG_ERROR( "%s: nfc ftm command timed out \n", __func__ ); + break; + } + } while( 0 ); + + return ret; +} +/*========================================================================= +FUNCTION ftm_nfc_read + +DESCRIPTION + Reads a message from the chip + +PARAMETERS + int len - the length of the buffer + +RETURN VALUE + int ret - Number of bytes read + +===========================================================================*/ +int ftm_nfc_read( uint8_t* buf, int len ) +{ + int ret = -1; + + do + { + if( fdNfc < 0 ) // fdNfc valid? + break; + + ret = read( fdNfc, buf, len ); // try to read + + } while( 0 ); + + return ret; +} + +/*========================================================================== +FUNCTION + CommitLog + +DESCRIPTION + This commits the log to Diag + +PARAMETERS + NCI_MESSAGE pReadNCIMessage - Pointer to the read NCI Message + +RETURN VALUE + void +==========================================================================*/ +void CommitLog( PNCI_MESSAGE pReadNCIMessage ) +{ + pftm_nfc_log_pkt_type pLogBuff; + + do + { + pLogBuff = ( ftm_nfc_log_pkt_type * ) log_alloc( LOG_NFC_FTM, // allocate a buffer for the log + pReadNCIMessage->len + offsetof( NCI_MESSAGE, buf ) + LOG_HEADER_LENGTH ); + if( NULL == pLogBuff ) + { + LOG_ERROR( "%s: log_alloc returned NULL \n", __func__ ); + break; + } + + memcpy( pLogBuff->data, // fill the buffer + pReadNCIMessage, + pReadNCIMessage->len + offsetof( NCI_MESSAGE, buf ) ); + + log_commit( pLogBuff ); // commit the log + } while ( 0 ); + +} + +/*============================================================================= +FUNCTION + ProcessReturnedMessage + +DESCRIPTION + Routine that processes an NCI Message that was returned and + will decide if the message is a notification or a response. + +PARAMETERS + PNCI_MESSAGE pReadNCIMessage - Pointer to the read message + +RETURN VALUE + void +==============================================================================*/ +void ProcessReturnedMessage( PNCI_MESSAGE pReadNCIMessage ) +{ + + switch( pReadNCIMessage->gid & NCIMT_NTF ) // check the first byte + { + case NCIMT_RSP: // reply? + sem_post( &sRspReady ); // notify the dispatch function + break; + + case NCIMT_NTF: // notification? + if (pReadNCIMessage->oid == 0x05) + { + LOG_INFORMATION("\n << ...TAG DETECTED... >> \n"); + printTecnologyDetails(pReadNCIMessage->buf[3],pReadNCIMessage->buf[2]); + sem_post( &sRfNtf ); + ProcessCommand( RFdeactivateCmd ); + } + case NCIMT_DATA: // data? + if (ese_dwp_test) + { + if( memcmp( EseDataRsp, nciReplyMessage, sizeof( EseDataRsp ) ) == 0 ) + { + LOG_INFORMATION("\n << ESE detected over DWP >> \n\n"); + } + } + if( log_status( LOG_NFC_FTM ) ) // logging enabled? + { + CommitLog( pReadNCIMessage ); + } + break; + + default: + LOG_ERROR( "%s: ERROR - SHOULD NOT HAVE REACHED THIS POINT", __func__ ); + break; + } + +} + +/*========================================================================= +FUNCTION nfc_read_thread + +DESCRIPTION + Thread that constantly looks for messages from the chip + +PARAMETERS + void + +RETURN VALUE + void + +===========================================================================*/ +void *nfc_read_thread( void *arg ) +{ + uint8_t readLength = 0; + int i; + uint8_t readNCIUpToLength = offsetof( NCI_MESSAGE, buf ); + + UNUSED_PARAMETER( arg ); + + for( ; ; ) // keep reading + { + readLength = ftm_nfc_read( nciReplyMessage, readNCIUpToLength ); // read the first 3 bytes + + if( readLength == readNCIUpToLength ) // read the message up to NCI Len? + { + readLength = ftm_nfc_read( pNCIMessage->buf, // go and get the rest + pNCIMessage->len ); + + if( readLength == pNCIMessage->len ) // successful? + { + PrintBytes( nciReplyMessage, pNCIMessage->len + readNCIUpToLength ); + + ProcessReturnedMessage( pNCIMessage ); // Process the read message + + } + } + } + +} + +/*========================================================================== +FUNCTION PrepareRsp + +DESCRIPTION + Routine to prepare a response for diag. + +PARAMETERS + ftm_nfc_pkt_type *nfc_ftm_pkt - FTM Packet + +RETURN VALUE + void * +==========================================================================*/ +void *PrepareRsp( ftm_nfc_pkt_type *nfc_ftm_pkt ) +{ + void *response = NULL; + switch( nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id ) + { + case FTM_NFC_NFCC_COMMAND: + { + ftm_nfc_pkt_type *nfc_nci_rsp = ( ftm_nfc_pkt_type* ) diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof( ftm_nfc_pkt_type ) ); // get a Response Buffer for NFCC Command + + if( NULL == nfc_nci_rsp ) + { + LOG_ERROR( "%s: diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, FTM_NFC_CMD_CODE, sizeof( ftm_nfc_pkt_type ) ) returned NULL \n", __func__ ); + } + else + { + nfc_nci_rsp->ftm_nfc_hdr.nfc_cmd_id = FTM_NFC_NFCC_COMMAND; + nfc_nci_rsp->ftm_nfc_hdr.nfc_cmd_len = offsetof( ftm_nfc_cmd_header, nfc_cmd_len ) + offsetof( NCI_MESSAGE, buf ) + pNCIMessage->len ; + nfc_nci_rsp->nfc_nci_pkt_len = offsetof( NCI_MESSAGE, buf ) + pNCIMessage->len; + + memcpy( nfc_nci_rsp->nci_data, + pNCIMessage, + nfc_nci_rsp->nfc_nci_pkt_len ); + + response = ( void* ) nfc_nci_rsp; + } + break; + } + + case FTM_NFC_REQ_CHIP_TYPE: + { + // change from a NCI packet type to a request chip type packet type + ftm_nfc_chip_type_pkt_type *nfc_chip_type_rsp = ( ftm_nfc_chip_type_pkt_type* ) diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof( ftm_nfc_chip_type_pkt_type ) ); // get a Response Buffer for Request Chip Type Command + if( NULL == nfc_chip_type_rsp ) + { + LOG_ERROR( "%s: diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, FTM_NFC_CMD_CODE, sizeof( ftm_nfc_chip_type_pkt_type ) ) returned NULL \n", __func__ ); + } + else + { + nfc_chip_type_rsp->nfc_chip_type_cmd_id = FTM_NFC_REQ_CHIP_TYPE; + nfc_chip_type_rsp->nfc_chip_type_pkt_len = 1; // only 1 byte for response packet data + if( chipType == 1 ) // 1 for QTI, 2 for NQ + nfc_chip_type_rsp->nfc_chip_type_pkt_data = FTM_NFC_QTI_CHIP; + else + nfc_chip_type_rsp->nfc_chip_type_pkt_data = FTM_NFC_NQ_CHIP; + + response = ( void* ) nfc_chip_type_rsp; + } + break; + } + + case FTM_NFC_FWPIN_CTRL: + { + // change from a NCI packet type to a firmware download packet type + ftm_nfc_fwdl_pkt_type *nfc_fwdl_rsp = ( ftm_nfc_fwdl_pkt_type* ) diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof( ftm_nfc_fwdl_pkt_type ) ); // get a Response Buffer for Firmware Download Pin Command + if( NULL == nfc_fwdl_rsp ) + { + LOG_ERROR( "%s: diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, FTM_NFC_CMD_CODE, sizeof( ftm_nfc_fwdl_pkt_type ) ) returned NULL \n", __func__ ); + } + else + { + nfc_fwdl_rsp->nfc_fwdl_cmd_id = FTM_NFC_FWPIN_CTRL; + nfc_fwdl_rsp->nfc_fwdl_pkt_len = 1; // only 1 byte for response packet data + nfc_fwdl_rsp->nfc_fwdl_pkt_data = FTM_NFC_FWDL_SUCCESS; // 0 for fail, 1 for success + + response = ( void* ) nfc_fwdl_rsp; + } + break; + } + + default : + + LOG_ERROR( "%s: ERROR - SHOULD NOT HAVE ENDED UP HERE: default case \n", __func__ ); + break; + } + + return response; + +} + +/*========================================================================= +FUNCTION ftm_nfc_nq_vs_nxp + +DESCRIPTION + Check whether the chip is an NQ Chip + +PARAMETERS + None + +RETURN VALUE + int + +===========================================================================*/ +int ftm_nfc_nq_vs_nxp( void ) +{ + int ret = 0; + uint8_t coreResetCmd[ ] = { 0x20, 0x00, 0x01, 0x00 }; + uint8_t coreResetRsp[ ] = { 0x40, 0x00, 0x03, 0x00, 0x11, 0x00 }; + uint8_t coreInitCmd[ ] = { 0x20, 0x01, 0x00 }; + + do + { + ret = ProcessCommand( coreResetCmd ); // send a Core Reset CMD + + if( ret == -1 ) // wait finished, not signalled? + { + LOG_ERROR( "%s: ProcessCommand( coreResetCmd ) error %d \n", __func__, ret ); + break; + } + + if( memcmp( coreResetRsp, nciReplyMessage, sizeof( coreResetRsp ) ) ) + { // not a good reply? + coreResetRsp[4] = 0x10; + if( memcmp( coreResetRsp, nciReplyMessage, sizeof( coreResetRsp ) ) ) + { // check if NCI version is 1.0 + ret = -1; + LOG_ERROR( "%s: bad reply for coreResetRsp", __func__ ); + break; + } + } + + ret = ProcessCommand( coreInitCmd ); // send the message + + if( ret == -1 ) // wait finished, not signalled? + { + LOG_ERROR( "%s: ProcessCommand( coreInitCmd ) error %d \n", __func__, ret ); + break; + } + + switch( nciReplyMessage[ CHIP_ID ] ) // what type of chip is it? + { + case 0x48: + whatNQChip = NQ_210; + LOG_INFORMATION( "Connected to NQ210 \n" ); + break; + + case 0x58: + whatNQChip = NQ_220; + LOG_INFORMATION( "Connected to NQ220 \n" ); + break; + + case 0x40: + case 0x41: + whatNQChip = NQ_310; + LOG_INFORMATION( "Connected to NQ310 \n" ); + break; + + case 0x50: + case 0x51: + whatNQChip = NQ_330; + LOG_INFORMATION( "Connected to NQ330 \n" ); + break; + + default: + whatNQChip = UNKNOWN_NQ_CHIP_TYPE; + ret = -1; + LOG_INFORMATION( "ERROR Connected to an unknown NQ Chip \n" ); + break; + } + }while( 0 ); + + return ret; +} + +/*========================================================================= +FUNCTION ftm_nfc_set_fwdl_pin + +DESCRIPTION + Sets or resets the firmware download pin high or low + +PARAMETERS + ftm_nfc_pkt_type *nfc_ftm_pkt - FTM Packet + +RETURN VALUE + void + +===========================================================================*/ +void ftm_nfc_set_fwdl_pin( ftm_nfc_pkt_type *nfc_ftm_pkt ) +{ + int ret = 0; + // change from a NCI packet type to a firmware download packet type + pftm_nfc_fwdl_pkt_type pnfc_fwdl_pkt = ( pftm_nfc_fwdl_pkt_type ) nfc_ftm_pkt; + + switch ( pnfc_fwdl_pkt->nfc_fwdl_pkt_data ) + { + case 0: + + ret = ftm_nfc_hw_reset( ); // Can you reset the hardware? + if( ret < 0 ) // successful? + { + LOG_ERROR( "%s: ftm_nfc_hw_reset() failed with ret = %d \n", __func__, ret ); + break; + } + + LOG_MESSAGE( "%s: Firmware download pin set LOW\n", __func__ ); + break; + + + case 1: + + ret = ioctl( fdNfc, NFC_SET_PWR, FIRMWARE_MODE ); + if( ret != 0 ) // successful? + { + LOG_ERROR( "%s ioctl( fdNfc, NFC_SET_PWR, FIRMWARE_MODE ) returned %d", __func__, ret ); + break; + } + + LOG_MESSAGE( "%s: Firmware download pin set HIGH\n", __func__ ); + break; + + default : + + LOG_ERROR( "%s: ERROR - SHOULD NOT HAVE ENDED UP HERE: default case \n", __func__ ); + break; + } + + ret = ftm_nq_nfc_close( ); // close the handle + if( ret != 0 ) // not successful? + { + LOG_ERROR( "\n\t %s: ftm_nq_nfc_close() failed with ret = %d \n", __func__, ret ); + } + + ret = ftm_nq_nfc_open( ); // open the kernel driver + if( ret < 0 ) // successful? + { + LOG_ERROR( "\n\t %s: ftm_nq_nfc_open() failed with ret = %d \n", __func__, ret ); + } +} + +/*========================================================================= +FUNCTION ftm_nfc_dispatch_nq + +DESCRIPTION + Dispatches QRCT commands and Chip Replies/Notifications/Data + +PARAMETERS + ftm_nfc_pkt_type *nfc_ftm_pkt - FTM Packet + uint16 pkt_len - FTM Packet Length + +RETURN VALUE + void * + +===========================================================================*/ +void* ftm_nfc_dispatch_nq( ftm_nfc_pkt_type *nfc_ftm_pkt, uint16 pkt_len ) +{ + int ret = 0; + int len = 0; + struct timespec time_sec; + char *SkipNQHardwareCheck = NULL; + + void *rsp = NULL; + UNUSED_PARAMETER( pkt_len ); + + do + { + if( !fdNfc ) // Already initialized? + { + ret = ftm_nq_nfc_open( ); // open the kernel driver + if( ret < 0 ) // successful? + { + LOG_ERROR( "\n\t %s: ftm_nq_nfc_open() failed with ret = %d \n", __func__, ret ); + break; + } + + ret = ftm_nfc_hw_reset( ); // Can you reset the hardware? + if( ret < 0 ) // successful? + { + LOG_ERROR( "%s: ftm_nfc_hw_reset() failed with ret = %d \n", __func__, ret ); + break; + } + + pNCIMessage = ( PNCI_MESSAGE ) nciReplyMessage; + + ret = pthread_create( &clientThread, // Start the Read Thread + NULL, + &nfc_read_thread, + NULL ); + if( ret != 0 ) // successful? + { + LOG_MESSAGE( "%s: pthread_create( nfc_read_thread ) failed with ret = %d \n", __func__, ret ); + break; + } + + SkipNQHardwareCheck = getenv( SKIP_NQ_HARDWARE_CHECK ); + LOG_MESSAGE( "%s: SkipNQHardwareCheck = %s \n", __func__, SkipNQHardwareCheck ); + + if( NULL == SkipNQHardwareCheck ) // no value so check for NQ Chip? + { + ret = ftm_nfc_nq_vs_nxp( ); + if( ret < 0 ) // Not an NQ Chip? + { + LOG_ERROR( "ERROR NOT A KNOWN NQ Chip \n" ); + break; + } + } + else + { + LOG_INFORMATION( " Skipping NQ Chip Check \n" ); + whatNQChip = SKIP_CHIP_CHECK; + } + + LOG_INFORMATION( "FTM for NFC SUCCESSFULLY STARTED \n" ); + } + + if( UNKNOWN_NQ_CHIP_TYPE == whatNQChip ) + { + LOG_ERROR( "ERROR This version of the chip is not accepted" ); + break; + } + + if( NULL == nfc_ftm_pkt ) // valid packet? + { + LOG_ERROR( "%s: Error : nfc_ftm_pkt is NULL \n", __func__ ); + break; + } + + if( offsetof( ftm_nfc_pkt_type, ftm_nfc_hdr ) < MIN_CMD_PKT_LEN ) + { // packet contains anything? + LOG_ERROR( "%s: Error : Invalid FTM Packet \n", __func__ ); + break; + } + + switch( nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id ) // what type of packet is it? + { + + case FTM_NFC_NFCC_COMMAND: // NFC Command? + case FTM_NFC_SEND_DATA: // NFC Data? + + ret = ProcessCommand( nfc_ftm_pkt->nci_data ); + if( ret == -1 ) // wait finished, not signalled? + { + LOG_ERROR( "%s: ProcessCommand( nfc_ftm_pkt->nci_data ) error %d \n", __func__, ret ); + break; + } + rsp = PrepareRsp( nfc_ftm_pkt ); // Prepare the response for Diag + + break; + + case FTM_NFC_REQ_CHIP_TYPE: + case FTM_NFC_FWPIN_CTRL: + + ftm_nfc_set_fwdl_pin( nfc_ftm_pkt ); + + rsp = PrepareRsp( nfc_ftm_pkt ); // Prepare the response for Diag + break; + + default : + LOG_ERROR( "%s: ERROR - SHOULD NOT HAVE ENDED UP HERE: default case \n", __func__ ); + break; + + } + } while( 0 ); + + return rsp; +} diff --git a/qca/ftm/src/ftm_nfcnq.h b/qca/ftm/src/ftm_nfcnq.h new file mode 100644 index 000000000..af8c2db56 --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq.h @@ -0,0 +1,168 @@ +/*========================================================================= + NQ NFC FTM Header File +Description + This file contains the declarations of the functions + used to communicate with the NQ Chip and various definitions. + +Copyright (c) 2015-2017 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ +/*=========================================================================== + Edit History +when who what, where, why +-------- --- ---------------------------------------------------------- +===========================================================================*/ + +#ifndef _FTM_NFCNQ +#define _FTM_NFCNQ + +#include "msg.h" +#include "diagpkt.h" +#include "diagcmd.h" +#include "errno.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "log.h" + +#define LOG_ERROR( ... ) printf( __VA_ARGS__ ) +#define LOG_INFORMATION( ... ) printf( __VA_ARGS__ ) + +#ifdef NFC_FTM_DEBUG +#define LOG_MESSAGE( ... ) printf( __VA_ARGS__ ) +#else +#define LOG_MESSAGE( ... ) do{ } while ( FALSE ) +#endif + +typedef PACKED struct _ftm_nfc_cmd_header{ + uint16 nfc_cmd_id; + uint16 nfc_cmd_len; +} ftm_nfc_cmd_header, *pftm_nfc_cmd_header; + +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + ftm_nfc_cmd_header ftm_nfc_hdr; + uint16 nfc_nci_pkt_len; + byte nci_data[258]; +}ftm_nfc_pkt_type, *pftm_nfc_pkt_type; + +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + uint16 nfc_fwdl_cmd_id; + byte nfc_fwdl_pkt_len; + byte nfc_fwdl_pkt_data; +}ftm_nfc_fwdl_pkt_type, *pftm_nfc_fwdl_pkt_type; + +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + uint16 nfc_chip_type_cmd_id; + byte nfc_chip_type_pkt_len; + byte nfc_chip_type_pkt_data; +}ftm_nfc_chip_type_pkt_type, *pftm_nfc_chip_type_pkt_type; + +typedef PACKED struct{ + log_hdr_type hdr; + byte data[1]; +} ftm_nfc_log_pkt_type, *pftm_nfc_log_pkt_type; + +typedef PACKED struct _NCI_MESSAGE +{ + byte gid; // Group ID + byte oid; // Operation ID + byte len; // payload length in bytes + byte buf[ 252 ]; // Payload Buffer +} NCI_MESSAGE, *PNCI_MESSAGE; + +typedef enum +{ + NCIMT_DATA = 0x00, /**< DATA packet. */ + NCIMT_CMD = 0x20, /**< Control packet - Command. */ + NCIMT_RSP = 0x40, /**< Control packet - Response. */ + NCIMT_NTF = 0x60, /**< Control packet - Notification. */ + + NCIMT_INVALID_VALUE = 0xFF, /**< Invalid packet type. */ + + NCIMT_BITMASK = 0xE0, /**< Most significant three bits. */ + NCIMT_BITSHIFT = 5 + +} NCIMT; + +typedef enum +{ + UNKNOWN_NQ_CHIP_TYPE = 0, + SKIP_CHIP_CHECK = 1, + NQ_110 = 11, + NQ_120 = 12, + NQ_210 = 21, + NQ_220 = 22, + NQ_310 = 31, + NQ_330 = 33, + MAXIMUM_NQ_CHIP_TYPE +} NQ_CHIP_TYPE; + +struct nqx_devinfo +{ + unsigned char chip_type; + unsigned char rom_version; + unsigned char fw_major; + unsigned char fw_minor; +}; + +union nqx_uinfo +{ + unsigned int i; + struct nqx_devinfo info; +}; + +int ftm_nq_nfc_open( void ); +int ftm_nq_nfc_close( void ); +int ftm_nfc_hw_reset( void ); +int ProcessCommand( uint8_t *nci_data ); +void *PrepareRsp( ftm_nfc_pkt_type *nfc_ftm_pkt ); +void *ftm_nfc_dispatch_nq( ftm_nfc_pkt_type *nfc_ftm_pkt, uint16 pkt_len); +void *nfc_read_thread( void *arg ); +extern sem_t sRfNtf; +extern int ese_dwp_test; +extern void printTecnologyDetails(char technology, char protocol); + +#define FTM_NFC_CMD_CODE 55 +#define FTM_NFC_NFCC_COMMAND 0x02 +#define FTM_NFC_SEND_DATA 0x03 +#define FTM_NFC_REQ_CHIP_TYPE 0x04 +#define FTM_NFC_FWPIN_CTRL 0x05 +#define FTM_NFC_CMD_CMPL_TIMEOUT 3 + +#define FTM_NFC_QTI_CHIP 0x00 +#define FTM_NFC_NQ_CHIP 0x01 +#define FTM_NFC_FWDL_SUCCESS 0x01 + +#define MIN_CMD_PKT_LEN 4 // Minimum length for a valid FTM packet, 2 bytes for Diag header, 2 bytes for command ID + +#define LOG_NFC_FTM 0x1802 +#define LOG_HEADER_LENGTH 12 + +#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int) +#define NFCC_GET_INFO _IOW(0xE9, 0x09, unsigned int) +#define POWER_OFF 0 +#define POWER_ON 1 +#define FIRMWARE_MODE 2 + +#define EXPECTED_CORE_INIT_RSP_LEN 29 +#define CHIP_ID 24 + +#define SKIP_NQ_HARDWARE_CHECK "SkipNQHardwareCheck" +#define HARDWARE_TYPE_TIMEOUT 2 + +#define UNUSED_PARAMETER( x ) ( void )( x ) + +#endif // _FTM_NFCNQ diff --git a/qca/ftm/src/ftm_nfcnq_fwdl.c b/qca/ftm/src/ftm_nfcnq_fwdl.c new file mode 100644 index 000000000..458bcde64 --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq_fwdl.c @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2016-2017 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Not a Contribution. + * Apache license notifications and license are retained + * for attribution purposes only. + */ + +/* + * Copyright (C) 2015 NXP Semiconductors + * The original Work has been changed by NXP Semiconductors. + * + * Copyright (C) 2010 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*========================================================================= + FTM NFC NQ Firmware Download Source File + Description + This file contains the definitions of the functions + used to download firmware onto the NQ Chip. +===========================================================================*/ + +#include "ftm_nfcnq_fwdl.h" +#include "ftm_nfcnq.h" + +unsigned int chip_version = 0x00; + +/* lookup table for CRC-16-CCITT calculation */ +static uint16_t const crcTable[ 256 ] = + { 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, + 0xe1ce, 0xf1ef, 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, 0x9339, 0x8318, 0xb37b, + 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, + 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, + 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, + 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, + 0x9b79, 0x8b58, 0xbb3b, 0xab1a, 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, 0xedae, + 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, + 0x1e51, 0x0e70, 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, + 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, + 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, 0x34e2, 0x24c3, + 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, + 0xd73c, 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, 0xd94c, 0xc96d, 0xf90e, 0xe92f, + 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, 0xcb7d, + 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, + 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, + 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 }; + + +/*========================================================================================================== +FUNCTION + load_firmware_from_library + +DESCRIPTION + gets a pointer to the firmware image and the length of the image + +PARAMETERS + const char *pathToLib - path to the firmware image library + uint8_t **ppFirmwareImage - pointer to the pointer to the firmware image + uint16_t *pFirmwareImageLen - pointer to the firmware image length + +RETURN VALUE + void + +==========================================================================================================*/ +static void load_firmware_from_library( const char *pathToLib, uint8_t **ppFirmwareImage, + uint16_t *pFirmwareImageLen ) +{ + void *pFirmwareLibHandle = NULL; + void *pTempFirmwareImage = NULL; + void *pTempFirmwareImageLen = NULL; + int status = -1; + + do + { + if( NULL == pathToLib ) + { + if(chip_version == 0x51 || chip_version == 0x50 || chip_version == 0x41 || chip_version == 0x40 ) + pathToLib = "/system/vendor/firmware/libpn553_fw.so"; // set the path to pn553 firmware library + else + pathToLib = "/system/vendor/firmware/libpn548ad_fw.so"; // set the default path to pn548ad firmware library + } + + if( NULL != pFirmwareLibHandle ) + { + status = dlclose( pFirmwareLibHandle ); // if the firmware library handle is not NULL, release the handle + pFirmwareLibHandle = NULL; + + dlerror( ); // clear existing errors + if( 0 != status ) + { + LOG_ERROR( "%s: dlclose() failed with status = %d \n", __FUNCTION__, status ); + break; + } + } + + pFirmwareLibHandle = dlopen( pathToLib, RTLD_LAZY ); // get a handle to firmware library + LOG_MESSAGE( "Opening library handle from %s\n", pathToLib ); + + if( NULL == pFirmwareLibHandle ) + { + LOG_ERROR( "%s: dlopen() failed \n", __FUNCTION__ ); + break; + } + dlerror( ); // clear existing errors + + pTempFirmwareImage = ( void * )dlsym( pFirmwareLibHandle, "gphDnldNfc_DlSeq" ); // get a pointer to the firmware library + + if( dlerror( ) || ( NULL == pTempFirmwareImage ) ) + { + LOG_ERROR( "%s: dlsym() failed, failed to load gphDnldNfc_DlSeq symbol \n", __FUNCTION__ ); + break; + } + *ppFirmwareImage = *( uint8_t ** )pTempFirmwareImage; // the returned pointer is a pointer to an uint8_t array + + pTempFirmwareImageLen = ( void * ) dlsym( pFirmwareLibHandle, "gphDnldNfc_DlSeqSz" ); // get a pointer to the firmware library length + + if( dlerror( ) || ( NULL == pTempFirmwareImageLen ) ) + { + LOG_ERROR( "%s: dlsym() failed, failed to load gphDnldNfc_DlSeqSz symbol \n", __FUNCTION__ ); + break; + } + *pFirmwareImageLen = ( uint16_t )( *( ( uint16_t * )pTempFirmwareImageLen ) ); // the returned pointer is a pointer to the length of the image + + } while( FALSE ); +} + +/*========================================================================================================== +FUNCTION + send_packet_packet_to_chip + +DESCRIPTION + sends the constructed packets to the NFC chip by calling ProcessCommand() from ftm_nfcnq.c + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void send_packet_packet_to_chip( pfirmware_download_context_t pDownloadContext ) +{ + int status = -1; + + status = ProcessCommand( &pDownloadContext->packetToSend ); // call ProcessCommand() from ftm_nfcnq.c + if( 0 != status ) + { + LOG_ERROR( "%s: ProcessCommand() failed with status = %d \n", __FUNCTION__, status ); + } +} + +/*========================================================================================================== +FUNCTION + calculate_crc16 + +DESCRIPTION + calculates CRC-16-CCITT of a given buffer with a given length with seed value of 0xffff(Hex) + +PARAMETERS + uint8_t *pBuff - buffer for CRC-16-CCITT calculation + uint16_t buffLen - length of buffer for CRC-16-CCITT calculation + +RETURN VALUE + uint16_t - calculated CRC-16-CCITT value of buffer + +==========================================================================================================*/ +static uint16_t calculate_crc16( uint8_t *pBuff, uint16_t buffLen ) +{ + uint16_t temp = 0; + uint16_t value = 0; + uint16_t crc = 0xffff; // seed value + uint32_t i = 0; + + if ( ( NULL == pBuff ) || ( 0 == buffLen ) ) + { + LOG_ERROR( "%s: Invalid parameters \n", __FUNCTION__ ); + } + else + { + for( i = 0; i < buffLen; i++ ) + { + value = 0x00ffU & ( uint16_t )pBuff[ i ]; + temp = ( crc >> 8U ) ^ value; + crc = ( crc << 8U ) ^ crcTable[ temp ]; + } + } + + return crc; +} + +/*========================================================================================================== +FUNCTION + insert_crc16 + +DESCRIPTION + inserts the calculated CRC-16-CCITT value into the end of the buffer + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void insert_crc16( pfirmware_download_context_t pDownloadContext ) +{ + uint16_t crcValueToWrite = 0; + uint8_t *crcValueInBytes = NULL; + + /* get CRC-16-CCITT value of packet and convert it into 2 bytes */ + crcValueToWrite = calculate_crc16( &pDownloadContext->packetToSend, + pDownloadContext->headerPlusPayloadLen ); + crcValueInBytes = ( uint8_t * )&crcValueToWrite; + + /* insert crc value into last 2 bytes of the packet */ + if( pDownloadContext->packetToSend.payloadLen < ( FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN - 1 )) + { + pDownloadContext->packetToSend.payloadBuff[ pDownloadContext->packetToSend.payloadLen ] = crcValueInBytes[ 1 ]; + pDownloadContext->packetToSend.payloadBuff[ pDownloadContext->packetToSend.payloadLen + 1 ] = crcValueInBytes[ 0 ]; + } + else + { + LOG_ERROR( "%s: Packet to send payloadLen more than maximum payloadBuff size \n", __FUNCTION__ ); + } +} + +/*========================================================================================================== +FUNCTION + read_response_from_chip + +DESCRIPTION + reader thread that constantly checks for responses from NFC chip, checks the integrity of the + response packets by matching the CRC-16-CCITT values and signals the semaphore held by + the call to ProcessCommand() + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void read_response_from_chip( pfirmware_download_context_t pDownloadContext ) +{ + uint8_t lenRead = 0; + uint8_t *pPacketReceived = NULL; + uint16_t calculatedCrcValue = 0; + uint16_t crcValueFromResponse = 0; + + do + { + if( fdNfc < 0 ) + { + LOG_ERROR( "%s: Invalid handle \n", __FUNCTION__ ); + break; + } + + lenRead = read( fdNfc, &pDownloadContext->packetReceived, // get the response packet header + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN ); + + if( 0 == lenRead ) + { + LOG_ERROR( "%s: Error reading response packet header \n", __FUNCTION__ ); + break; + } + else + { + pDownloadContext->totalPacketLen = lenRead; + } + + lenRead = read( fdNfc, &pDownloadContext->packetReceived.payloadBuff, // get the rest fo the response packet + ( pDownloadContext->packetReceived.payloadLen + + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN ) ); + + if( 0 == lenRead ) + { + LOG_ERROR( "%s: Error reading response packet payload \n", __FUNCTION__ ); + break; + } + else + { + pDownloadContext->totalPacketLen += lenRead; // update the total length of the received packet + } + + calculatedCrcValue = calculate_crc16( &pDownloadContext->packetReceived, // calculate the CRC-16-CCITT value of the received packet + ( pDownloadContext->packetReceived.payloadLen + + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN ) ); + + /* convert crc value from the response packet to an uint16_t */ + if( pDownloadContext->packetReceived.payloadLen < ( FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN - 1 )) + { + crcValueFromResponse = pDownloadContext->packetReceived.payloadBuff[ pDownloadContext->packetReceived.payloadLen ]; + crcValueFromResponse <<= 8; + crcValueFromResponse |= pDownloadContext->packetReceived.payloadBuff[ pDownloadContext->packetReceived.payloadLen + 1 ]; + } + else + { + LOG_ERROR( "%s: Packet received payloadLen more than maximum payloadBuff size \n", __FUNCTION__ ); + } + + if( calculatedCrcValue != crcValueFromResponse ) // compare the CRC-16-CCITT values + { + LOG_ERROR( "%s: CRC-16-CCITT values do not match, discarding packet \n", __FUNCTION__ ); + break; + } + else + { + sem_post( &sRspReady ); // signal the semaphore for subsequent packets to be sent + } + + } while( FALSE == pDownloadContext->fExitReadThread ); // exit only when the flag is set +} + +/*========================================================================================================== +FUNCTION + get_device_firmware_version + +DESCRIPTION + sends the get-firmware-version command (0xF1) to the device and outputs the firmware version of + the device + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void get_device_firmware_version( pfirmware_download_context_t pDownloadContext ) +{ + uint8_t getFirmwareVersionCommand[ ] = { 0x00, 0x04, 0xF1, 0x00, 0x00, 0x00 }; // command to get firmware version on device + uint8_t firmwareMajorVersion = 0; + uint8_t firmwareMinorVersion = 0; + + pDownloadContext->headerPlusPayloadLen = + sizeof( getFirmwareVersionCommand ) / sizeof( getFirmwareVersionCommand[ 0 ] ); + + memcpy( &pDownloadContext->packetToSend, &getFirmwareVersionCommand, // construct the command packet + ( pDownloadContext->headerPlusPayloadLen ) ); + + insert_crc16( pDownloadContext ); // insert the CRC-16-CCITT value + + send_packet_packet_to_chip( pDownloadContext ); // send the command packet to NFC chip + + /* continues from here once the reader thread reads the response and flags the semaphore, + the last 2 bytes of the get version response payload contains the firmware version currently on the device */ + firmwareMajorVersion = pDownloadContext->packetReceived.payloadBuff[ pDownloadContext->packetReceived.payloadLen - 1 ]; + firmwareMinorVersion = pDownloadContext->packetReceived.payloadBuff[ pDownloadContext->packetReceived.payloadLen - 2 ]; + + if(chip_version == 0x51 || chip_version == 0x50 || chip_version == 0x41 || chip_version == 0x40 ) + LOG_INFORMATION( "Firmware version: 11.%02X.%02X\n", firmwareMajorVersion, firmwareMinorVersion ); + else + LOG_INFORMATION( "Firmware version: 10.%02X.%02X\n", firmwareMajorVersion, firmwareMinorVersion ); +} + +/*========================================================================================================== +FUNCTION + build_first_packet + +DESCRIPTION + constructs the first packet to be sent to the NFC chip + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void build_first_packet( pfirmware_download_context_t pDownloadContext ) +{ + memset( pDownloadContext->packetToSend.payloadBuff, 0, // initialise the payload buffer to zero + FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN ); + + memcpy( &pDownloadContext->packetToSend, // copy the first chunk from the firmware library to the packet + pDownloadContext->pFirmwareImage, + pDownloadContext->headerPlusPayloadLen ); + + insert_crc16( pDownloadContext ); // insert the CRC-16-CCITT value +} + +/*========================================================================================================== +FUNCTION + build_next_packet + +DESCRIPTION + constructs subsequent packets required to be sent to the NFC chip + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void build_next_packet( pfirmware_download_context_t pDownloadContext ) +{ + /* for chunks from library that are larger than 256 bytes, the packets have to be fragmented */ + if( pDownloadContext->bytesLeftToSend > FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN ) + { + pDownloadContext->headerPlusPayloadLen = FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN + // length of header plus the payload for CRC-16-CCITT calculation + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN; + + pDownloadContext->totalPacketLen = FIRMWARE_DOWNLOAD_MAX_PACKET_LEN; // length of the entire packet to be sent + + pDownloadContext->packetToSend.fFragmentedPacket = FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_SET; // set the fragment flag as the first byte + + pDownloadContext->packetToSend.payloadLen = FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN; // insert the payload length in the second byte + + memcpy( ( &pDownloadContext->packetToSend.payloadBuff ), // copy payload from firmware library + &pDownloadContext->pFirmwareImage[ pDownloadContext->readIndexFromLib ], + FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN ); + + pDownloadContext->readIndexFromLib += FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN; // update the buffer index used to read from firmware library + + pDownloadContext->bytesLeftToSend -= FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN; // update the number of bytes left to send from the chunk + } + + /* for chunks from library that are smaller than 256 bytes, no fragmentation needed */ + else + { + pDownloadContext->headerPlusPayloadLen = pDownloadContext->bytesLeftToSend + // length of header plus the payload for CRC-16-CCITT calculation + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN; + + pDownloadContext->totalPacketLen = pDownloadContext->bytesLeftToSend + // length of the entire packet to be sent + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN + + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN; + + pDownloadContext->packetToSend.fFragmentedPacket = FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_NONE; // set the fragment flag to none as the first byte + + pDownloadContext->packetToSend.payloadLen = pDownloadContext->bytesLeftToSend; // insert the payload length in the second byte + + memcpy( ( &pDownloadContext->packetToSend.payloadBuff ), // copy payload from firmware library + &pDownloadContext->pFirmwareImage[ pDownloadContext->readIndexFromLib ], + pDownloadContext->bytesLeftToSend ); + + pDownloadContext->readIndexFromLib += pDownloadContext->bytesLeftToSend; // update the buffer index used to read from firmware library + + pDownloadContext->bytesLeftToSend = 0; // most likely the last fragment from the chunk + } + + insert_crc16( pDownloadContext ); +} + +/*========================================================================================================== +FUNCTION + process_packets_to_send + +DESCRIPTION + determines if the incoming packet is the first one or any subsequent ones and process them + accordingly + +PARAMETERS + pfirmware_download_context_t pDownloadContext - pointer to structure containing all the + information required + +RETURN VALUE + void + +==========================================================================================================*/ +static void process_packets_to_send( pfirmware_download_context_t pDownloadContext ) +{ + uint8_t firstChunkLenFromLib = 0; + uint16_t nextChunkLenFromLib = 0; + uint16_t buffIndex = pDownloadContext->readIndexFromLib; + + if( TRUE == pDownloadContext->fFirstPacket ) + { + pDownloadContext->fFirstPacket = FALSE; // indicates that the first packet has been processed + + firstChunkLenFromLib = pDownloadContext->pFirmwareImage[ 1 ] + // length of the first chunk read from firmware library + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN; + + pDownloadContext->totalPacketLen = firstChunkLenFromLib + // length of the entire packet to send + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN; + + pDownloadContext->readIndexFromLib += firstChunkLenFromLib; // update the buffer index used to read from firmware library + + pDownloadContext->headerPlusPayloadLen = firstChunkLenFromLib; // length of header plus the payload for CRC-16-CCITT calculation + + build_first_packet( pDownloadContext ); // build the first packet + + send_packet_packet_to_chip( pDownloadContext ); // send the packet to the NFC chip + } + else if( FALSE == pDownloadContext->fFirstPacket ) + { + nextChunkLenFromLib = pDownloadContext->pFirmwareImage[ buffIndex ]; // length of next chunk read from the firmware library + + /* length of next chunk is stored in 2 bytes in the firmware library */ + nextChunkLenFromLib <<= 8; + nextChunkLenFromLib |= pDownloadContext->pFirmwareImage[ buffIndex + 1 ]; + + buffIndex += 2; // add 2 bytes to the buffer index after length of next chunk is read + + pDownloadContext->readIndexFromLib = buffIndex; // update the buffer index used to read from firmware library + + pDownloadContext->bytesLeftToSend = nextChunkLenFromLib; // number of bytes left on the chunk to be sent to the chip + + while( pDownloadContext->bytesLeftToSend > 0 ) // constructs and sends packets as long as there are bytes left in the chunk + { + build_next_packet( pDownloadContext ); + send_packet_packet_to_chip( pDownloadContext ); + } + } + else + { + LOG_ERROR( "%s: Should not reach this point \n", __FUNCTION__ ); + } +} + +/*========================================================================================================== +FUNCTION + ftm_nfc_dispatch_nq_fwdl + +DESCRIPTION + called by main() in ftm_main.c to start the firmware download routine + +PARAMETERS + none + +RETURN VALUE + void + +==========================================================================================================*/ +void ftm_nfc_dispatch_nq_fwdl( void ) +{ + int status = 0; + + char *pathToLib = NULL; + uint8_t *pFirmwareImage = NULL; + uint16_t firmwareImageLen = 0; + + uint8_t *pNextChunkFromLib = NULL; + uint16_t nextChunkLenFromLib = 0; + uint16_t totalBytesReadFromLib = 0; + uint16_t readIndexFromLib = 0; + union nqx_uinfo nqx_info; + pthread_t readerThread; + + firmware_download_context_t downloadContext = { 0 }; + pfirmware_download_context_t pDownloadContext = &downloadContext; + pDownloadContext->fFirstPacket = TRUE; + + + do + { + if( !fdNfc ) + { + status = ftm_nq_nfc_open( ); // get a handle to the kernel driver + if( status < 0 ) + { + LOG_ERROR( "\n%s: ftm_nq_nfc_open() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + status = ftm_nfc_hw_reset( ); // reset NFC hardware + if( status < 0 ) + { + LOG_ERROR( "%s: ftm_nq_nfc_reset() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + nqx_info.i = ioctl( fdNfc, NFCC_GET_INFO, 0 ); + if( nqx_info.i < 0 ) + { + LOG_ERROR( "%s: nqnfcinfo not enabled, info = %d \n", __FUNCTION__, nqx_info.i ); + } + chip_version = nqx_info.info.chip_type; + LOG_INFORMATION( "\n NQ Chip ID : %x\n", chip_version); + } + + status = pthread_create( &readerThread, NULL, // create a reader thread + &read_response_from_chip, pDownloadContext ); + if( 0 != status ) + { + LOG_ERROR( "%s: pthread_create() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + load_firmware_from_library( pathToLib, &pFirmwareImage, &firmwareImageLen ); // get a pointer to firmware library image and get its length + if( ( NULL == pFirmwareImage ) || ( 0 == firmwareImageLen ) ) + { + LOG_ERROR( "%s: Firmware library image extraction failed\n", __FUNCTION__ ); + break; + } + + LOG_MESSAGE( "Firmware major version number: %02X\n", pFirmwareImage[ 5 ] ); + LOG_MESSAGE( "Firmware minor version number: %02X\n", pFirmwareImage[ 4 ] ); + LOG_MESSAGE( "Firmware library image length: %d\n", firmwareImageLen ); + LOG_MESSAGE( "Firmware library image pointer: %X\n", ( uintptr_t )pFirmwareImage ); + + pDownloadContext->pFirmwareImage = pFirmwareImage; + pDownloadContext->firmwareImageLen = firmwareImageLen; + + status = ioctl( fdNfc, NFC_SET_PWR, FIRMWARE_MODE ); // set NFCC to firmware download mode + if( 0 != status ) + { + LOG_ERROR( "%s: Failed to set firmware pin high.\n", __FUNCTION__ ); + break; + } + + LOG_INFORMATION( "\nBefore firmware update...\n" ); + get_device_firmware_version( pDownloadContext ); // get device version before loading firmware + + LOG_INFORMATION( "\nSending firmware packets... Please wait\n" ); + while( pDownloadContext->readIndexFromLib < pDownloadContext->firmwareImageLen ) + { + process_packets_to_send( pDownloadContext ); // build and send download packets with payload from the firmware library image + } + + LOG_INFORMATION( "All packets sent!\n\n" ); + + pDownloadContext->fExitReadThread = TRUE; // set flag to indicate that reader thread is safe to exit + + LOG_INFORMATION( "After firmware update...\n" ); + get_device_firmware_version( pDownloadContext ); // get device version number after loading firmware + + LOG_MESSAGE( "Waiting for reader thread to terminate...\n" ); + pthread_join( readerThread, NULL ); // wait for reader thread to terminate + LOG_MESSAGE( "Reader thread terminated!\n" ); + + LOG_MESSAGE( "Resetting NFCC...\n" ); + + status = ftm_nfc_hw_reset( ); // reset the NFC hardware which resets the firmware pin as well + if( status < 0 ) + { + LOG_ERROR( "%s: ftm_nfc_hw_reset() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + status = ftm_nq_nfc_close( ); // release the handle to the kernel driver + if( 0 != status ) + { + LOG_ERROR( "%s: ftm_nq_nfc_close() failed with status = %d \n", __FUNCTION__, status ); + } + + LOG_INFORMATION( "All done!\n\n" ); + + } while( FALSE ); + +} diff --git a/qca/ftm/src/ftm_nfcnq_fwdl.h b/qca/ftm/src/ftm_nfcnq_fwdl.h new file mode 100644 index 000000000..b8f308dd7 --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq_fwdl.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2016 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Not a Contribution. + * Apache license notifications and license are retained + * for attribution purposes only. + */ + +/* + * Copyright (C) 2015 NXP Semiconductors + * The original Work has been changed by NXP Semiconductors. + * + * Copyright (C) 2010 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*========================================================================= + FTM NFC NQ Firmware Download Header File + Description + This file contains the declarations of the functions and various + definitions used to download firmware onto the NQ Chip. +===========================================================================*/ + +#include +#include +#include +#include +#include +#include + +#define FALSE ( 0 ) +#define TRUE ( !FALSE ) + +#define FIRMWARE_DOWNLOAD_MAX_PACKET_LEN ( 0x100U ) // maximum length for a download packet +#define FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN ( 0x02U ) // length of the header +#define FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN ( 0x02U ) // length of CRC-16-CCITT value +#define FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN FIRMWARE_DOWNLOAD_MAX_PACKET_LEN - \ + FIRMWARE_DOWNLOAD_PACKET_HEADER_LEN - \ + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN + +/* Values for the first byte of each packet, indicates if the packet is fragmented */ +#define FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_NONE ( 0x00U ) // not fragmented +#define FIRMWARE_DOWNLOAD_PACKET_FRAG_FLAG_SET ( 0x04U ) // fragmented packet, next packet is a part of this one + +extern sem_t sRspReady; // semaphore used by reader thread +extern int fdNfc; // a handle to the kernel driver + +typedef uint8_t bool_t; + +/* structure of the packet to be sent or received */ +typedef struct firmware_download_packet +{ + uint8_t fFragmentedPacket; // flag to indicate if the packet is fragmented + uint8_t payloadLen; // length of payload + uint8_t payloadBuff[ FIRMWARE_DOWNLOAD_PACKET_MAX_PAYLOAD_LEN + + FIRMWARE_DOWNLOAD_PACKET_CRC16_LEN ]; // buffer containing the payload and CRC-16-CCITT value +} firmware_download_packet_t, *pfirmware_download_packet_t; + +/* structure that contains all the other information about the packets */ +typedef struct firmware_download_context +{ + const uint8_t *pFirmwareImage; // pointer to the firmware image library + uint16_t firmwareImageLen; // length of the firmware image + + uint8_t headerPlusPayloadLen; // header and payload length of a packet for CRC calculation + uint16_t readIndexFromLib; // index used to read from the firmware library + uint16_t bytesLeftToSend; // number of bytes left to send when the chunk read is fragmented + uint16_t totalPacketLen; // total length of packet to be sent or received + bool_t fFirstPacket; // flag to indicate if it is the first packet + bool_t fExitReadThread; // flag to indicate if reader thread is safe to exit + firmware_download_packet_t packetToSend; // contains information about packet to be sent + firmware_download_packet_t packetReceived; // contains information about packet from response received +} firmware_download_context_t, *pfirmware_download_context_t; + + + +/** + + Firmware download packet format + + ----------------------------------------------------------------------------------------------------- + | Header | Payload | CRC-16-CCITT value | + ----------------------------------------------------------------------------------------------------- + | Fragment flag | Payload length | Command/Response | Data | CRC-16-CCITT value | + ----------------------------------------------------------------------------------------------------- + | 1 byte | 1 byte | 1 byte | n bytes | 2 bytes | + ----------------------------------------------------------------------------------------------------- + + + Firmware library image format + + --------------------------------------------------------------------------------- ---------------------------------- + | 0x00 | First chunk length | First chunk | Next chunk length | Next chunk | ... | Last chunk length | Last chunk | + --------------------------------------------------------------------------------- ---------------------------------- + | 1 byte | 1 byte | n bytes | 2 bytes | n bytes | ... | 2 bytes | n bytes | + --------------------------------------------------------------------------------- ---------------------------------- + +*/ diff --git a/qca/ftm/src/ftm_nfcnq_test.c b/qca/ftm/src/ftm_nfcnq_test.c new file mode 100644 index 000000000..7581ac8ff --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq_test.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2017 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + */ + +#include +#include "ftm_nfcnq.h" +#include "ftm_nfcnq_test.h" + +/* Global variables */ +pthread_t clientThread; +PNCI_MESSAGE pNCIMessage; +char *progname; + +/*============================================================================== +FUNCTION + eseSpiTest + +DESCRIPTION + Send APDU for eSE SPI HLOS test + +PARAMETERS + int argc - argument count + char **argv - argument vector + +RETURN VALUE + void + +=============================================================================*/ +void eseSpiTest(int argc, char **argv ) +{ + int ret = 0; + int test_mode = 0; + unsigned char i = 0; + int fp = 0; + int choice = 0; + unsigned char send_APDU[] = {0x5A,0x00,0x05,0x00,0xA4,0x04,0x00,0x00,0xA5}; + int size_APDU = 0; + unsigned char recv_response[259] = {0}; + progname = basename(argv[2]); + test_mode = getopt(argc, argv, "01"); + size_APDU = sizeof(send_APDU); + + LOG_INFORMATION("\n### eSE SPI test ###\n"); + + if(test_mode == '0') + { + choice = 0; + LOG_INFORMATION("\nInterrupt Mode test\n"); + } + else + { + choice = 1; + LOG_INFORMATION("\nPoll Mode test(default)\n"); + } + + do + { + //open module + if ((ret = (fp = open("/dev/ese", O_RDWR))) < 0) + { + LOG_INFORMATION("eSE open error retcode = %d, errno = %d\n", ret, errno); + LOG_INFORMATION("\n... eSE SPI Test requires modified boot and TZ image ..."); + break; + } + LOG_INFORMATION("eSE open : Ret = %2d\n", ret); + + //enable the logs + ioctl(fp, ESE_SET_DBG, 1); + //hardware reset + ioctl(fp, ESE_SET_PWR, 1); + + ioctl(fp, ESE_SET_MODE, choice); + + //write one APDU + ret = write(fp, send_APDU, sizeof(send_APDU)); + if (ret < 0) + { + LOG_INFORMATION("ese write error retcode = %d, errno = %d\n", ret, errno); + break; + } + LOG_INFORMATION("ese Write : Ret = %.2X \n", ret); + LOG_INFORMATION("APDU sent to eSE: "); + for (i=0; inci_data, -1, MAX_CMD_LEN); + memcpy(nfc_pkt->nci_data, &buffer[rows], payloadlen); + ret = ProcessCommand( nfc_pkt->nci_data ); + if( ret == -1 ) // wait finished, not signalled? + { + LOG_ERROR( "Waited for NCI NTF/DATA timeout\n" ); + } + } +} + +/*============================================================================== +FUNCTION + usage + +DESCRIPTION + Print usage information for test + +PARAMETERS + +RETURN VALUE + void + +=============================================================================*/ +void usage() +{ + LOG_INFORMATION("\nUsage:"); + LOG_INFORMATION(" %s [-n] [-e] [-d] [h] \n", progname); + LOG_INFORMATION(" %s -n ..for NFC test only\n", progname); + LOG_INFORMATION(" %s -e ..for eSE SPI test only\n \t-0 ..Interrupt Mode\n \t-1 ..Poll Mode\n", progname); + LOG_INFORMATION(" %s -d ..for eSE DWP test only\n", progname); + LOG_INFORMATION(" %s -h HELP\n", progname); + LOG_INFORMATION(" %s default NFC test only\n", progname); +} + +/*============================================================================== +FUNCTION + nfc_ese_pwr + +DESCRIPTION + Set ESE power using NFC driver + +PARAMETERS + +RETURN VALUE + void + +=============================================================================*/ +void nfc_ese_pwr() +{ + int ret; + ret = ioctl( fdNfc, NFC_ESE_SET_PWR, POWER_ON ); // turn the chip on + if( ret != 0 ) + { + LOG_INFORMATION("Can't find ESE GPIO in NFC driver: "); + LOG_INFORMATION("ret=%d\n",ret); + } +} + + + +/*============================================================================== +FUNCTION + ftm_nfc_dispatch_nq_test + +DESCRIPTION + called by main() in ftm_main.c to start the nfc test routine + +PARAMETERS + int argc - argument count + char **argv - argument vector + +RETURN VALUE + void + +=============================================================================*/ +void ftm_nfc_dispatch_nq_test( int argc, char **argv ) +{ + int cmds = 0; + unsigned int chip_version = 0x00; + unsigned int major_version = 0x00; + unsigned int minor_version = 0x00; + unsigned int rom_version = 0x00; + char firmware_version[10]; + struct timespec time_sec; + int type_of_test = 0; + int default_test = 0; + int status = 0; + + union nqx_uinfo nqx_info; + pthread_t readerThread; + + do + { + if( !fdNfc ) + { + status = ftm_nq_nfc_open( ); // get a handle to the kernel driver + if( status < 0 ) + { + LOG_ERROR( "\n%s: ftm_nq_nfc_open() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + status = ftm_nfc_hw_reset( ); // reset NFC hardware + if( status < 0 ) + { + LOG_ERROR( "%s: ftm_nq_nfc_reset() failed with status = %d \n", __FUNCTION__, status ); + break; + } + + nqx_info.i = ioctl( fdNfc, NFCC_GET_INFO, 0 ); + if( nqx_info.i < 0 ) + { + LOG_ERROR( "%s: nqnfcinfo not enabled, info = %d \n", __FUNCTION__, nqx_info.i ); + } + + chip_version = nqx_info.info.chip_type; + rom_version = nqx_info.info.rom_version; + major_version = nqx_info.info.fw_major; + minor_version = nqx_info.info.fw_minor; + + LOG_INFORMATION( "\n NQ Chip ID : %x\n", chip_version); + snprintf(firmware_version, 10, "%02x.%02x.%02x", rom_version, major_version, minor_version); + LOG_INFORMATION(" Firmware version : %s\n\n", firmware_version); + + + if(sem_init(&sRspReady, 0, 0) != 0) + { + LOG_ERROR("NFC FTM :semaphore_halcmd_complete creation failed \n"); + break; + } + if(sem_init(&sRfNtf, 0, 0) != 0) + { + LOG_ERROR("NFC FTM :semaphore_halcmd_complete creation failed \n"); + break; + } + + pNCIMessage = ( PNCI_MESSAGE ) nciReplyMessage; + status = pthread_create( &clientThread, NULL, &nfc_read_thread, NULL ); // Start the Read Thread + + if( status != 0 ) // successful? + { + LOG_ERROR("nqnfc %s: pthread_create( nfc_read_thread ) failed with ret = %d \n", __func__, status ); + break; + } + + status = ftm_nfc_nq_vs_nxp( ); + if( status < 0 ) // Not an NQ Chip? + { + LOG_ERROR("ERROR NOT A KNOWN NQ Chip \n" ); + } + } + + progname = basename(argv[1]); + type_of_test = getopt(argc, argv, "nedhf"); + + switch (type_of_test) { + case 'n': + LOG_INFORMATION("NFC test only\n"); + break; + case 'e': + LOG_INFORMATION("eSE SPI test only\n"); + nfc_ese_pwr(); + ese_spi_test = 1; + eseSpiTest(argc, argv); + break; + case 'd': + LOG_INFORMATION("eSE DWP test only\n"); + ese_dwp_test = 1; + eseDwpTest(); + break; + case 'h': + usage(); + break; + default: + usage(); + default_test = 1; + LOG_INFORMATION("\nDefault NFC test only\n"); + } + + if(ese_dwp_test || ese_spi_test) + break; + + if(type_of_test == 'n' || default_test) + { + switch(whatNQChip) + { + case NQ_210: + case NQ_220: + cmds = sizeof(NQ220_cmds) / sizeof(NQ220_cmds[0]); + sendcmds(NQ220_cmds, cmds); + break; + case NQ_310: + case NQ_330: + cmds = sizeof(NQ330_cmds) / sizeof(NQ330_cmds[0]); + sendcmds(NQ330_cmds, cmds); + break; + default: + LOG_INFORMATION( "Chip not supported, taking NQ330 as default\n "); + cmds = sizeof(NQ330_cmds) / sizeof(NQ330_cmds[0]); + sendcmds(NQ330_cmds, cmds); + break; + } + + LOG_INFORMATION("\n<<>> Waiting for TAG detect or 20sec timeout <<>> ...\n"); + status = clock_gettime( CLOCK_REALTIME, &time_sec ); + time_sec.tv_sec += NFC_NTF_TIMEOUT; + status = sem_timedwait( &sRfNtf, &time_sec ); //start waiting + if (status <0) { + LOG_INFORMATION("\n No NFC Tag detected, continue ...\n"); + } + } + + status = ftm_nq_nfc_close( ); // release the handle to the kernel driver + if( 0 != status ) + { + LOG_ERROR( "%s: ftm_nq_nfc_close() failed with status = %d \n", __FUNCTION__, status ); + } + + } while( FALSE ); + +} diff --git a/qca/ftm/src/ftm_nfcnq_test.h b/qca/ftm/src/ftm_nfcnq_test.h new file mode 100644 index 000000000..d2c73ed5d --- /dev/null +++ b/qca/ftm/src/ftm_nfcnq_test.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2017 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Not a Contribution. + * Apache license notifications and license are retained + * for attribution purposes only. + * + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define ESE_MAGIC 0xEA +#define ESE_SET_PWR _IOW(ESE_MAGIC, 0x01, unsigned int) +#define ESE_SET_DBG _IOW(ESE_MAGIC, 0x02, unsigned int) +#define ESE_SET_MODE _IOW(ESE_MAGIC, 0x03, unsigned int) +#define NFC_ESE_SET_PWR _IOW(0xE9, 0x02, unsigned int) +#define NFC_ESE_GET_PWR _IOR(0xE9, 0x03, unsigned int) +#define NFC_NTF_TIMEOUT 20 + +/* Supported Protocols */ +#define NFC_PROTOCOL_UNKNOWN 0x00 /* Unknown */ +#define NFC_PROTOCOL_T1T 0x01 /* Type1Tag - NFC-A */ +#define NFC_PROTOCOL_T2T 0x02 /* Type2Tag - NFC-A */ +#define NFC_PROTOCOL_T3T 0x03 /* Type3Tag - NFC-F */ +#define NFC_PROTOCOL_ISO_DEP 0x04 /* Type 4A,4B - NFC-A or NFC-B */ +#define NFC_PROTOCOL_NFC_DEP 0x05 /* NFCDEP/LLCP - NFC-A or NFC-F */ + +#define MAX_CMD_LEN 255 +#define READ_SAMPLE_SIZE 258 +extern int fdNfc; // a handle to the kernel driver +extern uint8_t nciReplyMessage[ 255 ]; +extern NQ_CHIP_TYPE whatNQChip; +extern sem_t sRspReady; +extern int ftm_nfc_nq_vs_nxp( void ); +int ese_dwp_test = 0; +int ese_spi_test = 0; +void sendcmds(uint8_t buffer[][255], int no_of_cmds); +void printTecnologyDetails(char technology, char protocol); +sem_t sRfNtf; + +struct ese_spi_platform_data +{ + unsigned int use_pwr_req; + unsigned int pwr_req; + unsigned int ese_intr; +}; + +/* + * Enum definition contains RF technology modes supported. + * This information is a part of RF_DISCOVER_NTF or RF_INTF_ACTIVATED_NTF. + */ +typedef enum +{ + NFC_NFCA_Poll = 0x00, /* Nfc A Technology in Poll Mode */ + NFC_NFCB_Poll = 0x01, /* Nfc B Technology in Poll Mode */ + NFC_NFCF_Poll = 0x02, /* Nfc F Technology in Poll Mode */ + NFC_NFCA_Active_Poll = 0x03, /* Nfc A Technology in Active Poll Mode */ + NFC_NFCF_Active_Poll = 0x05, /* Nfc F Technology in Active Poll Mode */ + NFC_NFCISO15693_Poll = 0x06, /* Nfc ISO15693 Technology in Poll Mode */ + NFC_NxpProp_NFCHID_Poll = 0x70, /* Nfc Hid Technology in Poll Mode */ + NFC_NxpProp_NFCEPFGEN2_Poll = 0x71, /* Nfc EpcGen2 Technology in Poll Mode */ + NFC_NxpProp_NFCKOVIO_Poll = 0x72, /* Nfc Kovio Technology in Poll Mode */ + NFC_NFCA_Listen = 0x80, /* Nfc A Technology in Listen Mode */ + NFC_NFCB_Listen = 0x81, /* Nfc B Technology in Listen Mode */ + NFC_NFCF_Listen = 0x82, /* Nfc F Technology in Listen Mode */ + NFC_NFCA_Active_Listen = 0x83, /* Nfc A Technology in Active Listen Mode */ + NFC_NFCF_Active_Listen = 0x85, /* Nfc F Technology in Active Listen Mode */ + NFC_NFCISO15693_Active_Listen = 0x86 /* Nfc ISO15693 Technology in Listen Mode */ +} NFC_RfTechMode_t; + +uint8_t NQ330_cmds[][255] = +{ +{ 0x20,0x00,0x01,0x00 }, +{ 0x20,0x01,0x00}, +{ 0x2F,0x02,0x00 }, +{ 0x20,0x03,0x03,0x01,0xA0,0x0F }, +{ 0x20,0x03,0x03,0x01,0xA0,0xFC }, +{ 0x20,0x03,0x03,0x01,0xA0,0xF2 }, +{ 0x20,0x03,0x03,0x01,0xA0,0xD7 }, +{ 0x20,0x03,0x07,0x03,0xA0,0x02,0xA0,0x03,0xA0,0x04 }, +{ 0x20,0x02,0x09,0x02,0xA0,0x03,0x01,0x01,0xA0,0x04,0x01,0x06 }, +{ 0x20,0x02,0x0F,0x01,0xA0,0x0E,0x0B,0x11,0x01,0xC2,0xB2,0x00,0xB2,0x1E,0x1F,0x00,0xD0,0x0C }, +{ 0x20,0x02,0x05,0x01,0xA0,0xF2,0x01,0x01 }, +{ 0x20,0x03,0x03,0x01,0xA0,0xEC }, +{ 0x20,0x03,0x03,0x01,0xA0,0xD4 }, +{ 0x20,0x03,0x03,0x01,0xA0,0x14 }, +{ 0x20,0x02,0x2E,0x0E,0x28,0x01,0x00,0x21,0x01,0x00,0x30,0x01,0x08,0x31,0x01,0x03,0x32,0x01,0x60,0x38,0x01,0x01,0x33,0x04,0x01,0x02,0x03,0x04,0x54,0x01,0x06,0x50,0x01,0x02,0x5B,0x01,0x00,0x80,0x01,0x01,0x81,0x01,0x01,0x82,0x01,0x0E,0x18,0x01,0x01 }, +{ 0x20,0x02,0x05,0x01,0xA0,0x62,0x01,0x01 }, +{ 0x20,0x02,0x06,0x01,0xA0,0xF3,0x02,0x10,0x27 }, +{ 0x20,0x03,0x03,0x01,0xA0,0x85 }, +{ 0x21,0x01,0x07,0x00,0x01,0x01,0x03,0x00,0x01,0x05 }, +{ 0x20,0x02,0x05,0x01,0xA0,0xF1,0x01,0x00 }, +{ 0x20,0x03,0x03,0x01,0xA0,0x0F }, +{ 0x20,0x03,0x03,0x01,0xA0,0xEB }, +{ 0x20,0x00,0x01,0x00 }, +{ 0x20,0x01,0x00}, +{ 0x20,0x03,0x02,0x01,0x00 }, +{ 0x20,0x03,0x02,0x01,0x29 }, +{ 0x20,0x03,0x02,0x01,0x61 }, +{ 0x20,0x03,0x02,0x01,0x60 }, +{ 0x20,0x02,0x0F,0x01,0xA0,0x0E,0x0B,0x11,0x01,0xC2,0xB2,0x00,0xB2,0x1E,0x1F,0x00,0xD0,0x0C }, +{ 0x21,0x00,0x0D,0x04,0x04,0x03,0x02,0x05,0x03,0x03,0x03,0x02,0x01,0x80,0x01,0x80 }, +{ 0x20,0x03,0x07,0x03,0xA0,0xEC,0xA0,0xED,0xA0,0xD4 }, +{ 0x20,0x03,0x03,0x01,0xA0,0xEB }, +{ 0x20,0x03,0x03,0x01,0xA0,0xF0 }, +{ 0x22,0x01,0x02,0xC0,0x01 }, +{ 0x22,0x03,0x02,0xC0,0x00 }, +{ 0x20,0x03,0x03,0x01,0xA0,0x14 }, +{ 0x20,0x03,0x03,0x01,0xA0,0xEB }, +{ 0x20,0x03,0x03,0x01,0xA0,0x07 }, +{ 0x20,0x03,0x02,0x01,0x52 }, +{ 0x2F,0x15,0x01,0x02 }, +{ 0x21,0x03,0x07,0x03,0x80,0x01,0x81,0x01,0x82,0x01 }, +{ 0x21,0x06,0x01,0x00 }, +{ 0x2F,0x15,0x01,0x00 }, +{ 0x20,0x02,0x07,0x02,0x32,0x01,0x60,0x38,0x01,0x01 }, +{ 0x21,0x01,0x1B,0x00,0x05,0x01,0x03,0x00,0x01,0x03,0x01,0x03,0x00,0x41,0x04,0x01,0x03,0x00,0x41,0xA0,0x01,0x03,0x00,0x01,0x05,0x00,0x03,0xC0,0xC3,0x02 }, +{ 0x20,0x02,0x07,0x02,0x32,0x01,0x60,0x38,0x01,0x01}, +{ 0x21,0x03,0x19,0x0C,0x00,0x01,0x01,0x01,0x02,0x01,0x03,0x01,0x05,0x01,0x80,0x01,0x81,0x01,0x82,0x01,0x83,0x01,0x85,0x01,0x06,0x01,0x70,0x01} +}; + +uint8_t NQ330_ESE_DWP[][255] = +{ +{ 0x20,0x00,0x01,0x00 }, +{ 0x20,0x01,0x00}, +{ 0x20,0x02,0x05,0x01,0xA0,0xF2,0x01,0x01 }, +{ 0x22,0x00,0x01,0x01 }, +{ 0x22,0x01,0x2,0x01,0x01 }, +{ 0x20,0x04,0x06,0x03,0x01,0x01,0x02,0x01,0x01 }, +{ 0x03,0x00,0x03,0x81,0x02,0x01 }, +{ 0x03,0x00,0x03,0x81,0x02,0x04 }, +{ 0x03,0x00,0x03,0x81,0x02,0x07 }, +{ 0x21,0x01,0x1B,0x00,0x05,0x01,0x03,0x00,0x01,0x03,0x01,0x03,0x00,0x41,0x04,0x01,0x03,0x00,0x41,0xA0,0x01,0x03,0x00,0x01,0x05,0x00,0x03,0xC0,0xC3,0x02 }, +{ 0x21,0x03,0x19,0x0C,0x00,0x01,0x01,0x01,0x02,0x01,0x03,0x01,0x05,0x01,0x80,0x01,0x81,0x01,0x82,0x01,0x83,0x01,0x85,0x01,0x06,0x01,0x70,0x01}, +{ 0x03,0x00,0x07,0x99,0x50,0x00,0x70,0x00,0x00,0x01}, +{ 0x03,0x00,0x09,0x99,0x50,0x80,0xCA,0x00,0xFE,0x02,0xDF,0x21 } +}; + +uint8_t NQ220_cmds[][255] = +{ + { 0x20,0x00,0x01,0x00 }, + { 0x20,0x01,0x00 }, + { 0x2F,0x02,0x00 }, + { 0x20,0x03,0x03,0x01,0xA0,0x0F }, + { 0x20,0x03,0x07,0x03,0xA0,0x02,0xA0,0x03,0xA0,0x04 }, + { 0x20,0x02,0x05,0x01,0xA0,0x44,0x01,0x00 }, + { 0x20,0x02,0x0B,0x02,0xA0,0x66,0x01,0x00,0xA0,0x0E,0x03,0x02,0x09,0x00 }, + { 0x20,0x02,0x26,0x09,0xA0,0xEC,0x01,0x01,0xA0,0xED,0x01,0x03,0xA0,0x5E,0x01,0x01,0xA0,0x12,0x01,0x02,0xA0,0x40,0x01,0x01,0xA0,0xDD,0x01,0x2D,0xA0,0xF2,0x01,0x01,0xA0,0x96,0x01,0x01,0xA0,0x9F,0x02,0x08,0x08 }, + { 0x20,0x03,0x03,0x01,0xA0,0xEC }, + { 0x20,0x03,0x03,0x01,0xA0,0x14 }, + { 0x20,0x02,0x2E,0x0E,0x28,0x01,0x00,0x21,0x01,0x00,0x30,0x01,0x08,0x31,0x01,0x03,0x32,0x01,0x60,0x38,0x01,0x01,0x33,0x04,0x01,0x02,0x03,0x04,0x54,0x01,0x06,0x50,0x01,0x02,0x5B,0x01,0x00,0x80,0x01,0x01,0x81,0x01,0x01,0x82,0x01,0x0E,0x18,0x01,0x01 }, + { 0x20,0x02,0x05,0x01,0xA0,0x62,0x01,0x01 }, + { 0x20,0x02,0x06,0x01,0xA0,0xF3,0x02,0x10,0x27 }, + { 0x20,0x03,0x03,0x01,0xA0,0x85 }, + { 0x21,0x01,0x07,0x00,0x01,0x01,0x03,0x00,0x01,0x05 }, + { 0x20,0x02,0x05,0x01,0xA0,0xF1,0x01,0x00 }, + { 0x20,0x02,0x05,0x01,0xA0,0x91,0x01,0x01 }, + { 0x20,0x03,0x03,0x01,0xA0,0x0F }, + { 0x20,0x03,0x03,0x01,0xA0,0xEB }, + { 0x20,0x00,0x01,0x00 }, + { 0x20,0x01,0x00 }, + { 0x20,0x03,0x02,0x01,0x00 }, + { 0x20,0x03,0x02,0x01,0x29 }, + { 0x20,0x03,0x02,0x01,0x61 }, + { 0x20,0x03,0x02,0x01,0x60 }, + { 0x21,0x00,0x0D,0x04,0x04,0x03,0x02,0x05,0x03,0x03,0x03,0x02,0x01,0x80,0x01,0x80 }, + { 0x22,0x00,0x01,0x01 }, + { 0x20,0x04,0x06,0x03,0x01,0x01,0x02,0x01,0x01 }, + { 0x03,0x00,0x05,0x81,0x01,0x03,0x02,0xC0 }, + { 0x03,0x00,0x05,0x81,0x01,0x06,0x01,0x00 }, + { 0x03,0x00,0x03,0x81,0x02,0x01 }, + { 0x03,0x00,0x03,0x81,0x02,0x04 }, + { 0x20,0x03,0x05,0x02,0xA0,0xEC,0xA0,0xED }, + { 0x20,0x03,0x03,0x01,0xA0,0xEB }, + { 0x20,0x03,0x03,0x01,0xA0,0xF0 }, + { 0x20,0x03,0x05,0x02,0xA0,0xEC,0xA0,0xED }, + { 0x20,0x03,0x03,0x01,0xA0,0x14 }, + { 0x20,0x03,0x03,0x01,0xA0,0xEB }, + { 0x20,0x03,0x03,0x01,0xA0,0x07 }, + { 0x20,0x02,0x05,0x01,0xA0,0x07,0x01,0x03 }, + { 0x20,0x03,0x02,0x01,0x52 }, + { 0x21,0x01,0x16,0x00,0x04,0x01,0x03,0x00,0x01,0x03,0x01,0x03,0x00,0x41,0x04,0x01,0x03,0x00,0x41,0xA0,0x01,0x03,0x00,0x01,0x05 }, + { 0x20,0x02,0x0A,0x03,0x32,0x01,0x20,0x38,0x01,0x01,0x50,0x01,0x00 }, + { 0x21,0x03,0x07,0x03,0x80,0x01,0x81,0x01,0x82,0x01 }, + { 0x21,0x06,0x01,0x00 }, + { 0x20,0x02,0x17,0x01,0x61,0x14,0x46,0x66,0x6D,0x01,0x01,0x12,0x02,0x02,0x07,0xFF,0x03,0x02,0x00,0x13,0x04,0x01,0x64,0x07,0x01,0x03 }, + { 0x20,0x02,0x0A,0x03,0x32,0x01,0x60,0x38,0x01,0x01,0x50,0x01,0x02 }, + { 0x21,0x03,0x19,0x0C,0x00,0x01,0x01,0x01,0x02,0x01,0x03,0x01,0x05,0x01,0x80,0x01,0x81,0x01,0x82,0x01,0x83,0x01,0x85,0x01,0x06,0x01,0x70,0x01 } +}; diff --git a/qca/ftm/src/ftm_nfcqti.c b/qca/ftm/src/ftm_nfcqti.c new file mode 100644 index 000000000..cfe1a6ec7 --- /dev/null +++ b/qca/ftm/src/ftm_nfcqti.c @@ -0,0 +1,724 @@ +/*========================================================================= + NFC FTM Source File +Description + This file contains the routines to communicate with the NFCC in FTM mode. + +Copyright (c) 2015 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. +===========================================================================*/ +/*=========================================================================== + Edit History +when who what, where, why +-------- --- ---------------------------------------------------------- +===========================================================================*/ +/*==========================================================================* +* INCLUDE FILES * +*==========================================================================*/ +#include "ftm_nfcqti.h" + +#define UNUSED(x) (void)(x) + +/*=========================================================================* +* file scope local defnitions * +*==========================================================================*/ +const hw_module_t* hw_module = NULL; +nfc_nci_device_t* dev = NULL; +uint8 hal_state = NCI_HAL_INIT, nfc_ftmthread = FALSE; +uint8 *nfc_cmd_buff = NULL, len = 0; +uint16 res_len = 0, async_msg_cnt = 0; +uint8 *response_buff = NULL; +static uint8 hal_opened = FALSE, wait_rsp = FALSE; +static uint8 async_msg_available = FALSE, ftm_data_rsp_pending = FALSE; +asyncdata *buff = NULL; +asyncdata *start = NULL; +/*I2C read/write*/ +static uint8 i2c_cmd_cnt = 0; +uint8 i2c_status=0,i2c_req_write = FALSE, i2c_req_read = FALSE; +uint8 i2c_num_of_reg_to_read = 0, i2c_reg_read_data[40]={0}, ii = 0; +pthread_mutex_t nfcftm_mutex = PTHREAD_MUTEX_INITIALIZER; +/*===================================================================================* +* Function Defnitions * +*===================================================================================*/ +/*==================================================================================== +FUNCTION nfc_ftm_hal_cback +DESCRIPTION + This is the call back function which will indicate if the nfc hal open is successful + or failed. +DEPENDENCIES + NIL +RETURN VALUE +none +SIDE EFFECTS + NONE +=====================================================================================*/ +static void nfc_ftm_cback(uint8 event, uint8 status) +{ + switch(event) + { + case HAL_NFC_OPEN_CPLT_EVT: + if(status == HAL_NFC_STATUS_OK) + { + /* Release semaphore to indicate that hal open is done + and change the state to write.*/ + hal_state = NCI_HAL_WRITE; + hal_opened = TRUE; + printf("HAL Open Success..state changed to Write \n"); + } + else + { + printf("HAL Open Failed \n"); + hal_state = NCI_HAL_ERROR; + hal_opened = FALSE; + } + sem_post(&semaphore_halcmd_complete); + break; + case HAL_NFC_CLOSE_CPLT_EVT: + printf("HAL_NFC_CLOSE_CPLT_EVT recieved..\n"); + break; + default: + printf ("nfc_ftm_hal_cback unhandled event %x \n", event); + break; + } +} +/*========================================================================================== +FUNCTION fill_async_data +DESCRIPTION +This function will store all the incoming async msgs( like ntfs and data from QCA1990) +in to a list to be committed further. +DEPENDENCIES + NIL +RETURN VALUE + NONE +SIDE EFFECTS + NONE +==============================================================================================*/ +void fill_async_data(uint16 data_len, uint8 *p_data) +{ + uint16 i = 0; + asyncdata *next_node = NULL; + printf("fill_async_data() function \n"); + /* Initialize a list which will store all async message untill they are sent*/ + if(buff == NULL) + { + /* first node creation*/ + buff = (asyncdata*)malloc(sizeof(asyncdata)); + if(buff) + { + start = buff; + buff->response_buff = (uint8*)malloc(data_len); + if(buff->response_buff) + { + memcpy(buff->response_buff, p_data, data_len); + buff->async_datalen = data_len; + buff->next = NULL; + async_msg_cnt = 0; + async_msg_cnt++; + } + else + { + printf("mem allocation failed while storing asysnc msg \n"); + } + } + else + { + printf("mem allocation failed while trying to make the async list \n"); + } + } + else + { + /* this is the case when some data is already present in the list which has not been sent yet*/ + next_node = (asyncdata*)malloc(sizeof(asyncdata)); + if(next_node) + { + next_node->response_buff = (uint8*)malloc(data_len); + if(next_node->response_buff) + { + memcpy(next_node->response_buff, p_data,data_len); + next_node->async_datalen = data_len; + next_node->next = NULL; + async_msg_cnt++; + while(buff->next != NULL) + { + buff = buff->next; + } + buff->next = next_node; + } + else + { + printf("mem allocation failed while storing asysnc msg \n"); + } + } + else + { + printf("mem allocation failed while trying to make the async list \n"); + } + } +} +/*====================================================================================================== +FUNCTION nfc_ftm_data_cback +DESCRIPTION + This is the call back function which will provide back incoming data from the QCA1990 + to nfc ftm. +DEPENDENCIES + NIL +RETURN VALUE + NONE +SIDE EFFECTS + NONE +========================================================================================================*/ +static void nfc_ftm_data_cback(uint16 data_len, uint8 *p_data) +{ + uint8 i = 0; + if(hal_opened == FALSE) + { + /* Reject data call backs untill HAL in initialized */ + return; + } + if((data_len == 0x00) || (p_data == NULL)) + { + printf("Error case : wrong data lentgh or buffer revcieved \n"); + return; + } + if((i2c_req_write == TRUE) || (i2c_req_read == TRUE)) + { + if(i2c_req_write) + { + /*check the incoming status*/ + if(p_data[0] != 0x00) /* 0x00 = Command executed successfully*/ + { + /* some error has occured in I2C write.Send the status code back now to pc app*/ + i2c_status = p_data[0]; + printf("Error occured in I2C write .. reporting to application..Error Code = %X \n", i2c_status); + hal_state = NCI_HAL_READ; + sem_post(&semaphore_halcmd_complete); + } + else + { + /*status is fine. Complete further requests as ftmdaemon is writing one by one*/ + if(len) + { + /*send further addr and value pair*/ + printf("I2C write status correct..sending next..\n"); + hal_state = NCI_HAL_WRITE; + } + else + { + /*All I2C write completed .Send final status to app*/ + i2c_status = p_data[0]; + printf(" All I2C write completed i2c_status = %X \n", i2c_status); + hal_state = NCI_HAL_READ; + } + sem_post(&semaphore_halcmd_complete); + } + } + else + { + /*I2C read rsp arrived . fill it in buffer if correct or report error if wrong*/ + if(p_data[0] != 0x00) + { + /* some error has occured in I2C read.Send the status code to app*/ + i2c_status = p_data[0]; + printf("Error occured in I2C read .. reporting to application..Error Code = %X \n", i2c_status); + hal_state = NCI_HAL_READ; + memset(nfc_cmd_buff, 0, len); + sem_post(&semaphore_halcmd_complete); + } + else + { + if(len) + { + /*send further addr to read*/ + i2c_status = p_data[0]; + i2c_reg_read_data[ii++] = p_data[1]; + hal_state = NCI_HAL_WRITE; + } + else + { + /*All I2C read completed .Send the read data back to pc app*/ + i2c_status = p_data[0]; + i2c_reg_read_data[ii++] = p_data[1]; + hal_state = NCI_HAL_READ; + ii = 0; + } + sem_post(&semaphore_halcmd_complete); + } + } + } + else + { + if(((p_data[0] & 0xF0) == 0x60 /*ntf packets*/) || ((p_data[0] & 0xF0) == 0x00)/*data packet rsps*/) + { + async_msg_available = TRUE; + pthread_mutex_lock(&nfcftm_mutex); + fill_async_data(data_len, p_data); + pthread_mutex_unlock(&nfcftm_mutex); + if(ftm_data_rsp_pending == TRUE) + { + printf("Sending data rsp \n"); + hal_state = NCI_HAL_READ; + sem_post(&semaphore_halcmd_complete); + ftm_data_rsp_pending = FALSE; + } + else + { + if((wait_rsp == FALSE) || ((p_data[0] == 0x60) && (p_data[1] == 0x00))) + { + /*This is the case when ntf receieved after rsp is logged to pc app*/ + printf("Sending async msg to logging subsystem \n"); + hal_state = NCI_HAL_ASYNC_LOG; + sem_post(&semaphore_halcmd_complete); + } + } + } + else + { + if(response_buff || res_len) + { + printf("nfc_ftm_data_cback : response_buff = %p, res_len = %d", response_buff, res_len); + return; + } + response_buff = (uint8*)malloc(data_len); + if(response_buff) + { + memcpy(response_buff, p_data, data_len); + res_len = data_len; + printf("nfc_ftm_data_cback: res_len=%d data_len=%d response_buff= %X %X %X %X %X %X \n", res_len,data_len, \ + response_buff[0],response_buff[1],response_buff[2],response_buff[3],response_buff[4],response_buff[5]); + hal_state = NCI_HAL_READ; + sem_post(&semaphore_halcmd_complete); + } + else + { + printf("Mem allocation failed in nfc_ftm_data_cback \n"); + } + } + } +} +/*=========================================================================== +FUNCTION ftm_nfc_hal_open +DESCRIPTION + This function will open the nfc hal for ftm nfc command processing. +DEPENDENCIES + NIL +RETURN VALUE + void +SIDE EFFECTS + NONE +===============================================================================*/ +uint8 ftm_nfc_hal_open(void) +{ + uint8 ret = 0; + ret = hw_get_module(NFC_NCI_HARDWARE_MODULE, &hw_module); + if(ret == 0) + { + dev = (nfc_nci_device_t*)malloc(sizeof(nfc_nci_device_t)); + if(!dev) + { + printf("NFC FTM : mem allocation failed \n"); + return FALSE; + } + else + { + ret = nfc_nci_open (hw_module, &dev); + if(ret != 0) + { + printf("NFC FTM : nfc_nci_open fail \n"); + free(dev); + return FALSE; + } + else + { + printf("NFC FTM : opening NCI HAL \n"); + dev->common.reserved[0] = FTM_MODE; + dev->open (dev, nfc_ftm_cback, nfc_ftm_data_cback); + sem_wait(&semaphore_halcmd_complete); + } + } + } + else + { + printf("NFC FTM : hw_get_module() call failed \n"); + return FALSE; + } + return TRUE; +} +/*================================================================================================= +FUNCTION ftm_nfc_log_send_msg +DESCRIPTION +This function will log the asynchronous messages(NTFs and data packets) to the logging subsystem + of DIAG. +DEPENDENCIES +RETURN VALUE +TRUE if data logged successfully and FALSE if failed. +SIDE EFFECTS + None +==================================================================================================*/ +int ftm_nfc_log_send_msg(void) +{ + uint16 i = 0; + ftm_nfc_log_pkt_type* ftm_nfc_log_pkt_ptr = NULL; + asyncdata* node = NULL; + uint8 arr[1]= {'\n'}; + if(log_status(LOG_NFC_FTM)) + { + buff = start; + if(buff != NULL) + { + do{ + printf("buff->async_datalen : %d \n", buff->async_datalen); + ftm_nfc_log_pkt_ptr = (ftm_nfc_log_pkt_type *)log_alloc(LOG_NFC_FTM, (FTM_NFC_LOG_HEADER_SIZE + (buff->async_datalen))); + if(ftm_nfc_log_pkt_ptr) + { + memcpy((void *)ftm_nfc_log_pkt_ptr->data, (void *)buff->response_buff, buff->async_datalen); + printf("Async msg is = "); + for(i=0; iasync_datalen; i++) + { + printf("%X ", ftm_nfc_log_pkt_ptr->data[i]); + } + printf("%c",arr[0]); + node = buff; + buff = buff->next; + free(node); + printf("Commiting the log message(async msg) \n"); + log_commit(ftm_nfc_log_pkt_ptr); + } + else + { + printf("\nmem alloc failed in log_alloc \n"); + return FALSE; + } + }while(buff != NULL); + printf("all msgs committed \n"); + async_msg_available = FALSE; + return TRUE; + } + else + { + printf("No async message left to be logged \n"); + } + } + else + { + printf("LOG_NFC_FTM code is not enabled in logging subsystem \n"); + } + return FALSE; +} +/*=========================================================================== +FUNCTION nfc_ftm_readerthread +DESCRIPTION + Thread Routine to perfom asynchrounous handling of events coming from + NFCC. It will perform read and write for all type of commands/data. +DEPENDENCIES +RETURN VALUE + RETURN NIL +SIDE EFFECTS + None +===========================================================================*/ +void* nfc_ftm_thread(void *ptr) +{ + uint8 i2c_buff[3] = {0}; + + UNUSED(ptr); + + while(1) + { + printf("Waiting for Cmd/Rsp \n"); + sem_wait (&semaphore_halcmd_complete); + switch(hal_state) + { + case NCI_HAL_INIT: + printf("NFC FTM : HAL Open request recieved..\n"); + if(ftm_nfc_hal_open() == FALSE) + { + hal_state = NCI_HAL_ERROR; + hal_opened = FALSE; + } + else + { + break; + } + case NCI_HAL_ERROR: + /* HAL open failed.Post sem and handle error case*/ + sem_post(&semaphore_nfcftmcmd_complete); + break; + case NCI_HAL_WRITE: + if(dev != NULL) + { + printf("NFC FTM : Cmd recieved for nfc ftm..sending.\n"); + if((!i2c_req_write) && (!i2c_req_read)) + { + /* send data to the NFCC*/ + if(nfc_cmd_buff[0] == 0x00 /*data req*/) + { + printf("Data send request arrived \n"); + ftm_data_rsp_pending = TRUE; + } + else + { + printf("cmd request arrived \n"); + wait_rsp = TRUE; + } + dev->write(dev, len, nfc_cmd_buff); + } + else + { + if(i2c_req_write) + { + i2c_buff[0] = 0xFF; + i2c_buff[1] = nfc_cmd_buff[i2c_cmd_cnt++]; /* addr*/ + i2c_buff[2] = nfc_cmd_buff[i2c_cmd_cnt++]; /*value*/ + len -=2; + dev->write(dev, 3, i2c_buff); + } + else + { + /* I2c Read req*/ + i2c_buff[0] = 0xFF; + i2c_buff[1] = nfc_cmd_buff[i2c_cmd_cnt++]; /* I2C addr to read*/ + i2c_reg_read_data[ii++] = i2c_buff[1]; /* store address to send in response.*/ + len -= 1; + dev->write(dev, 2, i2c_buff); + } + } + } + else + { + printf("dev is null \n"); + } + break; + case NCI_HAL_READ: + /* indicate to ftm that response is avilable now*/ + sem_post(&semaphore_nfcftmcmd_complete); + printf("NFC FTM : State changed to READ i2c_req_read: %d\n",i2c_req_read); + break; + case NCI_HAL_ASYNC_LOG: + /* indicate to ftm that response is avilable now*/ + printf("NFC FTM : State changed to NCI_HAL_ASYNC_LOG.Logging aysnc message \n"); + pthread_mutex_lock(&nfcftm_mutex); + if(ftm_nfc_log_send_msg()) + { + printf("async msgs commited to the log system..changing HAL state to write \n"); + } + else + { + printf("async msgs commit failed..changing HAL state to write \n"); + } + hal_state = NCI_HAL_WRITE; + pthread_mutex_unlock(&nfcftm_mutex); + break; + default: + break; + } + } +} +/*=========================================================================== +FUNCTION ftm_nfc_dispatch +DESCRIPTION +This is the function which will be called by the NFC FTM layer callback function +registered with the DIAG service./ +DEPENDENCIES +RETURN VALUE + RETURN rsp pointer(containing the NFCC rsp packets) to the callback function + (subsequently for DIAG service) +SIDE EFFECTS + None +===========================================================================*/ +void* ftm_nfc_dispatch_qti(ftm_nfc_pkt_type *nfc_ftm_pkt, uint16 pkt_len) +{ + ftm_nfc_i2c_write_rsp_pkt_type *i2c_write_rsp = NULL; + ftm_nfc_i2c_read_rsp_pkt_type *i2c_read_rsp = NULL; + ftm_nfc_pkt_type *rsp = NULL; + ftm_nfc_data_rsp_pkt_type *nfc_data_rsp = NULL; + struct timespec time_sec; + int sem_status; + + UNUSED(pkt_len); + + printf("NFC FTM : nfc ftm mode requested \n"); + if(nfc_ftm_pkt == NULL) + { + printf("Error : NULL packet recieved from DIAG \n"); + goto error_case; + } + /* Start nfc_ftm_thread which will process all requests as per + state machine flow. By Default First state will be NCI_HAL_INIT*/ + if(!nfc_ftmthread) + { + if(sem_init(&semaphore_halcmd_complete, 0, 1) != 0) + { + printf("NFC FTM :semaphore_halcmd_complete creation failed \n"); + goto error_case; + } + if(sem_init(&semaphore_nfcftmcmd_complete, 0, 0) != 0) + { + printf("NFC FTM :semaphore_nfcftmcmd_complete creation failed \n"); + goto error_case; + } + printf("NFC FTM : nfc ftm thread is being started \n"); + pthread_create(&nfc_thread_handle, NULL, nfc_ftm_thread, NULL); + nfc_ftmthread = TRUE; + } + /* parse the diag packet to identify the NFC FTM command which needs to be sent + to QCA 1990*/ + if(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_len > 2) + { + len = nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_len-2; + } + else + { + /*Wrong nfc ftm packet*/ + goto error_case; + } + switch(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id) + { + case FTM_NFC_I2C_SLAVE_WRITE: + i2c_req_write = TRUE; + break; + case FTM_NFC_I2C_SLAVE_READ: + i2c_num_of_reg_to_read = len; + i2c_req_read = TRUE; + break; + case FTM_NFC_NFCC_COMMAND: + case FTM_NFC_SEND_DATA: + break; + default : + goto error_case; + break; + } + /*copy command to send it further to QCA1990*/ + nfc_cmd_buff = (uint8 *)malloc(len+1); + if(nfc_cmd_buff) + { + memcpy(nfc_cmd_buff, nfc_ftm_pkt->nci_data, len); + } + else + { + printf("Mem allocation failed for cmd storage"); + goto error_case; + } + /*send the command */ + sem_post(&semaphore_halcmd_complete); + printf("\nwaiting for nfc ftm response \n"); + if (clock_gettime(CLOCK_REALTIME, &time_sec) == -1) + { + printf("get clock_gettime error"); + } + time_sec.tv_sec += FTM_NFC_CMD_CMPL_TIMEOUT; + sem_status = sem_timedwait(&semaphore_nfcftmcmd_complete,&time_sec); + if(sem_status == -1) + { + printf("nfc ftm command timed out\n"); + goto error_case; + } + if(!hal_opened) + { + /*Hal open is failed */ + free(nfc_cmd_buff); + hal_state = NCI_HAL_INIT; + goto error_case; + } + printf("\n\n *****Framing the response to send back to Diag service******** \n\n"); + /* Frame the response as per the cmd request*/ + switch(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id) + { + case FTM_NFC_I2C_SLAVE_WRITE: + printf("Framing the response for FTM_NFC_I2C_SLAVE_WRITE cmd \n"); + i2c_write_rsp = (ftm_nfc_i2c_write_rsp_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof(ftm_nfc_i2c_write_rsp_pkt_type)); + if(i2c_write_rsp) + { + i2c_write_rsp->nfc_i2c_slave_status = i2c_status; + i2c_status = 0; + i2c_cmd_cnt = 0; + i2c_req_write = FALSE; + } + break; + case FTM_NFC_I2C_SLAVE_READ: + printf("Framing the response for FTM_NFC_I2C_SLAVE_READ cmd \n"); + i2c_read_rsp = (ftm_nfc_i2c_read_rsp_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof(ftm_nfc_i2c_read_rsp_pkt_type)); + if(i2c_read_rsp) + { + i2c_read_rsp->ftm_nfc_hdr.nfc_cmd_id = FTM_NFC_I2C_SLAVE_READ; + i2c_read_rsp->ftm_nfc_hdr.nfc_cmd_len = 2+(2*i2c_num_of_reg_to_read); + i2c_read_rsp->nfc_i2c_slave_status = i2c_status; + if(i2c_status == 0x00) + { + i2c_read_rsp->nfc_nb_reg_reads = i2c_num_of_reg_to_read; + } + else + { + i2c_read_rsp->nfc_nb_reg_reads = 0x00; // error case so return num of read as 0x00. + } + memcpy(i2c_read_rsp->i2c_reg_read_rsp, i2c_reg_read_data, (i2c_num_of_reg_to_read*2)); + i2c_cmd_cnt = 0; + } + break; + case FTM_NFC_NFCC_COMMAND: + printf("Framing the response for FTM_NFC_NFCC_COMMAND cmd \n"); + if(response_buff && res_len) + { + rsp = (ftm_nfc_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof(ftm_nfc_pkt_type)); + if(rsp) + { + rsp->ftm_nfc_hdr.nfc_cmd_id = FTM_NFC_NFCC_COMMAND; + rsp->ftm_nfc_hdr.nfc_cmd_len = 2+res_len; + rsp->nfc_nci_pkt_len = res_len; + memcpy(rsp->nci_data, response_buff, res_len); + free(response_buff); + response_buff = 0; + res_len = 0; + } + } + else + printf("ftm_nfc_dispatch : response_buff = %p, res_len = %d", response_buff, res_len); + break; + case FTM_NFC_SEND_DATA: + printf("Framing the response for FTM_NFC_SEND_DATA cmd \n"); + nfc_data_rsp = (ftm_nfc_data_rsp_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_NFC_CMD_CODE, + sizeof(ftm_nfc_data_rsp_pkt_type)); + if(nfc_data_rsp) + { + nfc_data_rsp->ftm_nfc_hdr.nfc_cmd_id = FTM_NFC_SEND_DATA; + nfc_data_rsp->ftm_nfc_hdr.nfc_cmd_len = 0;/*Rsp as per the NFC FTM data rsp req*/ + } + break; + default: + goto error_case; + break; + } + free(nfc_cmd_buff); + hal_state = NCI_HAL_WRITE; + if(async_msg_available) + { + printf(" Some async message available.. committing now.\n"); + hal_state = NCI_HAL_ASYNC_LOG; + sem_post(&semaphore_halcmd_complete); + } + wait_rsp = FALSE; + if(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id == FTM_NFC_I2C_SLAVE_WRITE) + { + return(void*)i2c_write_rsp; + } + else if(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id == FTM_NFC_I2C_SLAVE_READ) + { + i2c_req_read = FALSE; + return(void*)i2c_read_rsp; + } + else if(nfc_ftm_pkt->ftm_nfc_hdr.nfc_cmd_id == FTM_NFC_NFCC_COMMAND) + { + return(void*)rsp; + } + else + { + return(void*)nfc_data_rsp; + } +error_case: + return NULL; +} diff --git a/qca/ftm/src/ftm_nfcqti.h b/qca/ftm/src/ftm_nfcqti.h new file mode 100644 index 000000000..28968b991 --- /dev/null +++ b/qca/ftm/src/ftm_nfcqti.h @@ -0,0 +1,141 @@ +#ifndef FTM_NFCQTI_H_ +#define FTM_NFCQTI_H_ +/*========================================================================== + + nfc FTM header File + +Description + This file contains the decalarations used by ftm_nfc.c + +Copyright (c) 2015 Qualcomm Technologies, Inc. +All Rights Reserved. +Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +08/06/13 NFC FTM layer +===========================================================================*/ + +#ifdef CONFIG_FTM_NFC + +#include "stdio.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "msg.h" +#include "log.h" + +#include "diag_lsm.h" +#include "diagpkt.h" +#include "diagcmd.h" +#include "diag.h" +#include "termios.h" + +/*==========================================================================* +* Defnitions * +*==========================================================================*/ +#define FTM_MODE 1 +#define TRUE 1 +#define FALSE 0 +#define FTM_MODE 1 +#define FTM_NFC_CMD_CODE 55 +#define LOG_NFC_FTM 0x1802 +#define FTM_NFC_LOG_HEADER_SIZE 12 + +#define FTM_NFC_I2C_SLAVE_WRITE 0x00 +#define FTM_NFC_I2C_SLAVE_READ 0x01 +#define FTM_NFC_NFCC_COMMAND 0x02 +#define FTM_NFC_SEND_DATA 0x03 + +#define FTM_NFC_CMD_CMPL_TIMEOUT 15 + +#ifdef ANDROID_M +#define NFC_NCI_HARDWARE_MODULE "nfc_nci.qc199x" +#else +#define NFC_NCI_HARDWARE_MODULE "nfc_nci" +#endif + +enum +{ + NCI_HAL_INIT, + NCI_HAL_WRITE, + NCI_HAL_READ, + NCI_HAL_DEINIT, + NCI_HAL_ASYNC_LOG, + NCI_HAL_ERROR +}; +/*==========================================================================* +* Declarations * +*==========================================================================*/ +/* Reader thread handle */ +pthread_t nfc_thread_handle; +sem_t semaphore_halcmd_complete; +sem_t semaphore_nfcftmcmd_complete; + +/* structure that contains nfc cmd id and len + part of the packet recieved from DIAG*/ +PACKED struct ftm_nfc_cmd_header_type{ + uint16 nfc_cmd_id; + uint16 nfc_cmd_len; +}; + +/* nfc FTM packet(for NCI cmd/rsp messages)*/ +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + struct ftm_nfc_cmd_header_type ftm_nfc_hdr; + uint16 nfc_nci_pkt_len; + byte nci_data[258]; +}ftm_nfc_pkt_type; + +/* nfc FTM packet (for I2C write messgaes)*/ +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + uint8 nfc_i2c_slave_status; +}ftm_nfc_i2c_write_rsp_pkt_type; + +/* nfc FTM packet (for I2C read messgaes)*/ +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + struct ftm_nfc_cmd_header_type ftm_nfc_hdr; + uint8 nfc_i2c_slave_status; + uint8 nfc_nb_reg_reads; + byte i2c_reg_read_rsp[30]; +}ftm_nfc_i2c_read_rsp_pkt_type; + + +typedef PACKED struct{ + diagpkt_subsys_header_type diag_hdr; + struct ftm_nfc_cmd_header_type ftm_nfc_hdr; +}ftm_nfc_data_rsp_pkt_type; + +typedef PACKED struct{ + log_hdr_type hdr; + byte data[1]; +}ftm_nfc_log_pkt_type; + +/*Data buffer linked list*/ +typedef struct asyncdata { + uint8 *response_buff; + uint8 async_datalen; + struct asyncdata *next; +}asyncdata; + +typedef void (tHAL_NFC_CBACK) (uint8 event, uint8 status); +typedef void (tHAL_NFC_DATA_CBACK) (uint16 data_len, uint8 *p_data); + +void* ftm_nfc_dispatch_qti(ftm_nfc_pkt_type *ftm_nfc_pkt, uint16 pkt_len); + +#endif /* CONFIG_FTM_NFC */ +#endif /* FTM_NFCQTI_H_ */ diff --git a/qca/ftm/src/ftm_wlan.c b/qca/ftm/src/ftm_wlan.c new file mode 100644 index 000000000..68e5189ca --- /dev/null +++ b/qca/ftm/src/ftm_wlan.c @@ -0,0 +1,1110 @@ +/*========================================================================== + + FTM WLAN Source File + +============================================================================ + +# Copyright (c) 2011, 2013-2018 Qualcomm Technologies, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +07/11/11 karthikm Wrapper that contains routines for directing FTM commands + sent from host to the IOCTL calls of Atheros driver. +*/ + +/* + * Copyright (c) 2006 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// FTM_WLAN_TCMD +// Based on athtestcmd.c from AR6003 drop +// +// + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "comdef.h" +#include "diagcmd.h" + +#include "testcmd.h" +#include "libtcmd.h" +#include "ftm_wlan.h" +#include "ftm_dbg.h" + +#define INVALID_FREQ 0 +#define A_RATE_NUM 28 +#define G_RATE_NUM 28 +#define RATE_STR_LEN 20 + +int old_iface_id = -1; +#ifdef CONFIG_FTM_WLAN_AUTOLOAD +#define MODULE_FILE "/proc/modules" +#define DRIVER_MODULE_TAG "wlan" +#define WLAN_CFG_FILE "/persist/wlan_mac.bin" +/* Offset for set mac address cmd */ +#define MAIN_CMD_OFFSET 16 +#define SUB_CMD_OFFSET 24 +#define LENGTH_OFFSET 32 +#define NMAC_OFFSET 48 +#define PMAC_OFFSET 49 + +#if defined(ANDROID) +#if defined(BOARD_HAS_ATH_WLAN_AR6320) +#if BOARD_HAS_ATH_WLAN_AR6320 +#define FTM_WLAN_LOAD_CMD "/system/bin/insmod " \ + "/system/lib/modules/wlan.ko con_mode=5" +#define FTM_WLAN_UNLOAD_CMD "/system/bin/rmmod wlan" +#endif +#endif +#elif defined(MDM_LE) +#define FTM_WLAN_LOAD_CMD "/etc/init.d/wlan start_ftm" +#define FTM_WLAN_UNLOAD_CMD "/etc/init.d/wlan stop" +#else +#warning "Load and Unload driver may not work!" +#endif + +typedef enum { + SUBCMD_DRIVER_LOAD = 'L', + SUBCMD_DRIVER_UNLOAD = 'U', + SUBCMD_DRIVER_AUTO_MODE = 'A', +} sub_cmds; + +static int load_wifi_driver_testmode(void); +static int unload_wifi_driver(void); +static bool is_wifi_driver_loaded(char *mod_tag); +static bool flag_driver_auto_load = false; +#endif /* CONFIG_FTM_WLAN_AUTOLOAD */ +extern void diagpkt_free(void *pkt); + +char bdf_file[128] = {'0'}; +static void rxReport(void *buf); +#ifndef WIN_AP_HOST +char g_ifname[IFNAMSIZ] = "wlan"; +#else +#ifdef WIN_AP_HOST_OPEN +char g_ifname[IFNAMSIZ] = "wlan"; +#else +char g_ifname[IFNAMSIZ] = "wifi"; +#endif +#endif + +#ifdef WIN_AP_HOST + +#define WIN_COMMON_OP_REQ 0xFE +#define BT_CMD_REQ 198 +#define BTCMD_ID_POS 64 +#define BT_MAC_LEN_POS 80 +#define BT_CMD_LEN 0xC + +#endif + +void print_uchar_array(uint8_t *addr, int len) +{ + int i; + for (i = 0;i< len; i++) + DPRINTF(FTM_DBG_TRACE, "%02X ", addr[i]); + DPRINTF(FTM_DBG_TRACE, "\n"); +} + +void print_uint16_array(uint16_t *addr, int len) +{ + int i; + for (i = 0;i< len; i++) + DPRINTF(FTM_DBG_TRACE, "%02X %02X ", addr[i]>>8, addr[i]&0xFF); + DPRINTF(FTM_DBG_TRACE, "\n"); +} + +/*=========================================================================== +FUNCTION rxReport + +DESCRIPTION + Quick debug routine that will print all the receive statistics + +DEPENDENCIES + NIL + +RETURN VALUE + NIL + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void rxReport(void *buf) +{ + uint32 pkt; + int rssi; + uint32 crcError; + uint32 secErr; + uint16 rateCnt[TCMD_MAX_RATES]; + uint16 rateCntShortGuard[TCMD_MAX_RATES]; + + pkt = *(uint32 *)buf; + rssi = (int)(*((uint32 *)buf + 1)); + crcError = *((uint32 *)buf + 2); + secErr = *((uint32 *)buf + 3); + + DPRINTF(FTM_DBG_TRACE, "total pkt %u, crcError pkt %u, secErr pkt %u, average rssi %d\n", + pkt, crcError, secErr, (int)( pkt ? (rssi / (int)pkt) : 0)); + + + memcpy(rateCnt, ((unsigned char *)buf) + (4 * sizeof(uint32)), sizeof(rateCnt)); + memcpy(rateCntShortGuard, ((unsigned char *)buf) + (4 * sizeof(uint32)) + + (TCMD_MAX_RATES * sizeof(uint16)), sizeof(rateCntShortGuard)); + + DPRINTF(FTM_DBG_INFO, "1Mbps %d\n", rateCnt[0]); + DPRINTF(FTM_DBG_INFO, "2Mbps %d\n", rateCnt[1]); + DPRINTF(FTM_DBG_INFO, "5.5Mbps %d\n", rateCnt[2]); + DPRINTF(FTM_DBG_INFO, "11Mbps %d\n", rateCnt[3]); + DPRINTF(FTM_DBG_INFO, "6Mbps %d\n", rateCnt[4]); + DPRINTF(FTM_DBG_INFO, "9Mbps %d\n", rateCnt[5]); + DPRINTF(FTM_DBG_INFO, "12Mbps %d\n", rateCnt[6]); + DPRINTF(FTM_DBG_INFO, "18Mbps %d\n", rateCnt[7]); + DPRINTF(FTM_DBG_INFO, "24Mbps %d\n", rateCnt[8]); + DPRINTF(FTM_DBG_INFO, "36Mbps %d\n", rateCnt[9]); + DPRINTF(FTM_DBG_INFO, "48Mbps %d\n", rateCnt[10]); + DPRINTF(FTM_DBG_INFO, "54Mbps %d\n", rateCnt[11]); + DPRINTF(FTM_DBG_INFO, "\n"); + DPRINTF(FTM_DBG_INFO, "HT20 MCS0 6.5Mbps %d (SGI: %d)\n", rateCnt[12], rateCntShortGuard[12]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS1 13Mbps %d (SGI: %d)\n", rateCnt[13], rateCntShortGuard[13]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS2 19.5Mbps %d (SGI: %d)\n", rateCnt[14], rateCntShortGuard[14]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS3 26Mbps %d (SGI: %d)\n", rateCnt[15], rateCntShortGuard[15]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS4 39Mbps %d (SGI: %d)\n", rateCnt[16], rateCntShortGuard[16]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS5 52Mbps %d (SGI: %d)\n", rateCnt[17], rateCntShortGuard[17]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS6 58.5Mbps %d (SGI: %d)\n", rateCnt[18], rateCntShortGuard[18]); + DPRINTF(FTM_DBG_INFO, "HT20 MCS7 65Mbps %d (SGI: %d)\n", rateCnt[19], rateCntShortGuard[19]); + DPRINTF(FTM_DBG_INFO, "\n"); + DPRINTF(FTM_DBG_INFO, "HT40 MCS0 13.5Mbps %d (SGI: %d)\n", rateCnt[20], rateCntShortGuard[20]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS1 27.0Mbps %d (SGI: %d)\n", rateCnt[21], rateCntShortGuard[21]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS2 40.5Mbps %d (SGI: %d)\n", rateCnt[22], rateCntShortGuard[22]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS3 54Mbps %d (SGI: %d)\n", rateCnt[23], rateCntShortGuard[23]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS4 81Mbps %d (SGI: %d)\n", rateCnt[24], rateCntShortGuard[24]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS5 108Mbps %d (SGI: %d)\n", rateCnt[25], rateCntShortGuard[25]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS6 121.5Mbps %d (SGI: %d)\n", rateCnt[26], rateCntShortGuard[26]); + DPRINTF(FTM_DBG_INFO, "HT40 MCS7 135Mbps %d (SGI: %d)\n", rateCnt[27], rateCntShortGuard[27]); +} + +ftm_wlan_rsp_pkt_type *g_rsp = NULL; +TCMD_ID tcmd = TCMD_CONT_RX_ID; +uint32 mode = 0; + +/*=========================================================================== +FUNCTION ftm_wlan_tcmd_rx + +DESCRIPTION + Call back handler + +DEPENDENCIES + NIL + +RETURN VALUE + NONE + +SIDE EFFECTS + NONE + +===========================================================================*/ + +void ftm_wlan_tcmd_rx(void *buf, int len) +{ + void *data = NULL; + int data_len = 0; + struct TCMD_CONT_RX_REPORT *report = NULL; + TC_CMDS *tCmd = NULL; + u_int32_t *src, *dest; + int j; + +#ifdef DEBUG + current_time(); +#endif + DPRINTF(FTM_DBG_TRACE, "Rx call back received with len %d\n", len); + + /* Build the response to be sent */ + switch(tcmd) { + case TCMD_CONT_RX_ID: + report = &((TCMD_CONT_RX *) buf)->u.report; + + if (mode == TCMD_CONT_RX_REPORT) { + rxReport((void*)report); + } else if (mode == TCMD_CONT_RX_GETMAC) { + tCmd = (TC_CMDS *)buf; + + DPRINTF(FTM_DBG_TRACE, "length %d version %d act %d\n", + tCmd->hdr.u.parm.length, tCmd->hdr.u.parm.version, + tCmd->hdr.act); + + DPRINTF(FTM_DBG_INFO, + "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", + tCmd->buf[0], tCmd->buf[1], tCmd->buf[2], + tCmd->buf[3], tCmd->buf[4], tCmd->buf[5]); + } + + data = report; + data_len = sizeof(struct TCMD_CONT_RX_REPORT); + break; + + case TC_CMDS_ID: + tCmd = (TC_CMDS *)buf; + + DPRINTF(FTM_DBG_TRACE, "length %d version %d act %d\n", + tCmd->hdr.u.parm.length, tCmd->hdr.u.parm.version, + tCmd->hdr.act); + data = buf; + data_len = sizeof(TC_CMDS); + + if ( mode == TC_CMDS_READTHERMAL ) + DPRINTF(FTM_DBG_INFO, "Chip Thermal value: %d\n", tCmd->buf[0]); + break; + + case TC_CMD_TLV_ID: + data = buf; + data_len = len; + src = (u_int32_t *)buf; + dest = (u_int32_t *)buf; + for (j = 0; j < roundup(len, sizeof(u_int32_t))/4; j++) { + *(dest+j) = le32toh(*(src+j)); + } + print_uchar_array(buf, len); + + DPRINTF(FTM_DBG_TRACE, "tcmd_rx TC_CMD_TLV_ID length %d\n", len); + break; + + default: + data_len = 0; + data = NULL; + DPRINTF(FTM_DBG_TRACE, "Unknown TCMD response\n"); + break; + } + + g_rsp = (ftm_wlan_rsp_pkt_type*)diagpkt_subsys_alloc( DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, (sizeof(g_rsp->common_header) + + sizeof(g_rsp->cmd.common_ops) + data_len)); + + if (g_rsp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate diag packet! tcmd: %d", + tcmd); + return; + } + +#ifdef WIN_AP_HOST + /* Handle win specific fw responses */ + if (data == NULL || data_len == 0) + g_rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + else + win_host_handle_fw_resp(g_rsp, data, data_len); + if (g_rsp == NULL) + return; +#else + + if (data && data_len != 0) + memcpy(g_rsp->cmd.common_ops.rx_and_therm.rxReport.data, data, data_len); + + g_rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_PASS); +#endif +} + +/*=========================================================================== +FUNCTION isResponseNeeded + +DESCRIPTION + Do we need a response for the command + +DEPENDENCIES + NIL + +RETURN VALUE + boolean response required/not + +SIDE EFFECTS + NONE + +===========================================================================*/ +static bool isResponseNeeded(void *buf) +{ + bool respNeeded = false; + + tcmd = le32toh(*((uint32 *) buf)); + mode = le32toh(*((uint32 *) buf + 1)); + + /// Insert commands which need response + switch (tcmd) + { + case TC_CMD_TLV_ID: + respNeeded = true; + break; + case TCMD_CONT_RX_ID: + switch (mode) + { + case TCMD_CONT_RX_REPORT: + case TCMD_CONT_RX_GETMAC: + respNeeded = true; + break; + } + break; + case TC_CMDS_ID: + switch (mode) + { + case TC_CMDS_READTHERMAL: + case TC_CMDS_EFUSEDUMP: + case TC_CMDS_EFUSEWRITE: + case TC_CMDS_OTPSTREAMWRITE: + case TC_CMDS_OTPDUMP: + respNeeded = true; //TC_CMDS_EFUSEDUMP, TC_CMDS_EFUSEWRITE, TC_CMDS_OTPSTREAMWRITE, TC_CMDS_OTPDUMP, TC_CMDS_READTHERMAL + break; + } + break; + default: + break; + } + + if (respNeeded) + { + DPRINTF(FTM_DBG_TRACE, "cmdID %d response needed\n", tcmd); + } + else + { + DPRINTF(FTM_DBG_TRACE, "cmdID %d response not needed\n", tcmd); + } + + return respNeeded; +} + + +/*=========================================================================== +FUNCTION ftm_wlan_common_op + +DESCRIPTION + Process ftm commands like load driver, Tx, Rx and few test commands + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_common_op(ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len) +{ + uint8_t *input_msg = (uint8_t*)wlan_ftm_pkt; + uint32_t *cmd; + ftm_wlan_rsp_pkt_type *rsp; + int data_len = pkt_len - sizeof(diagpkt_subsys_header_v2_type) - 4; + char ifname[IFNAMSIZ]; + bool resp = false; + int curr_iface_id; + + snprintf(ifname, sizeof(ifname), "%s%d", g_ifname, + wlan_ftm_pkt->cmd.common_ops.wlandeviceno); + if (data_len <= 0) { + DPRINTF(FTM_DBG_ERROR, "Invalid data_len: %d\n", data_len); + return NULL; + } + + cmd = (uint32_t*)(wlan_ftm_pkt->cmd.common_ops.data); + DPRINTF(FTM_DBG_TRACE, "Command ID rec'd: 0x%X length %d\n", le32toh(*cmd), data_len); + + print_uchar_array((uint8_t*)(wlan_ftm_pkt->cmd.common_ops.data), data_len); + + g_rsp = NULL; + + rsp = (ftm_wlan_rsp_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + sizeof(rsp->common_header) + + sizeof(rsp->cmd.common_ops)); + + if (rsp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag packet: %p\n", rsp); + goto err_out; + } + + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_PASS); + +#ifdef CONFIG_FTM_WLAN_AUTOLOAD + if (le32toh(*cmd) == TCMD_LOAD_DRIVER) { + /* Get sub-cmd */ + unsigned int sub_cmd = 0; + if (data_len >= (int)(2*sizeof(uint32))) + sub_cmd = *((uint32*)wlan_ftm_pkt->cmd.common_ops.data + 1); + + /* execute sub_cmd */ + if (sub_cmd == SUBCMD_DRIVER_LOAD) { + load_wifi_driver_testmode(); + } else if (sub_cmd == SUBCMD_DRIVER_UNLOAD) { + unload_wifi_driver(); + } else if (sub_cmd == SUBCMD_DRIVER_AUTO_MODE) { + flag_driver_auto_load = true; + } + + /* These commands will not go to firmware */ + return rsp; + } + else if ((data_len > PMAC_OFFSET) && *(wlan_ftm_pkt->cmd.common_ops.data + MAIN_CMD_OFFSET) == OP_GENERIC_NART_CMD) { + if (*(wlan_ftm_pkt->cmd.common_ops.data + SUB_CMD_OFFSET) == TCMD_SET_MAC_ADDR) { + int i = 0; + uint8_t length = 0, nMac = 0, *pMac = NULL; + length = *(wlan_ftm_pkt->cmd.common_ops.data + LENGTH_OFFSET); + nMac = *(wlan_ftm_pkt->cmd.common_ops.data + NMAC_OFFSET); + pMac = (wlan_ftm_pkt->cmd.common_ops.data + PMAC_OFFSET); + + DPRINTF(FTM_DBG_TRACE, "Handling WLAN request of setting Mac address\n"); + + if (!nMac || (length < (5 + 6*nMac))) { + DPRINTF(FTM_DBG_ERROR, "invalid data, nMac = %u, length = %u\n", + nMac, length); + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + goto err_out; + } + + FILE *fp = fopen(WLAN_CFG_FILE, "wb"); + if (fp == NULL) { + DPRINTF(FTM_DBG_INFO, "Can't open file %s\n", WLAN_CFG_FILE); + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + goto err_out; + } + + for (i = 0; i < nMac; i++) { + fprintf(fp, "Intf%dMacAddress=%02X%02X%02X%02X%02X%02X\n", i, + pMac[0], pMac[1], pMac[2], pMac[3], pMac[4], pMac[5]); + pMac = pMac + 6; + } + fprintf(fp, "END"); + fclose(fp); + /* This command will not go to the firmware */ + return rsp; + } + } + + if ((flag_driver_auto_load == true) \ + && (!is_wifi_driver_loaded(DRIVER_MODULE_TAG))) { + /* load the driver to testmode */ + load_wifi_driver_testmode(); + } +#endif + +#ifdef WIN_AP_HOST + /* 0xFE is the command id(first byte) for BD capture/Flash write requests */ + if (le32toh(*cmd) == WIN_COMMON_OP_REQ) { + diagpkt_free(rsp); + rsp = win_host_handle_bdf_req (wlan_ftm_pkt, pkt_len); + return (void *)rsp; + } + if (data_len > BTCMD_ID_POS) { + if((input_msg[BTCMD_ID_POS] == BT_CMD_REQ) && (input_msg[BT_MAC_LEN_POS] == BT_CMD_LEN)){ + diagpkt_free(rsp); + rsp = win_bt_mac_flash_write(wlan_ftm_pkt, pkt_len); + if (rsp) + return (void *)rsp; + else { + DPRINTF(FTM_DBG_ERROR, "Response is NULL!\n"); + goto err_out; + } + } + } +#endif + curr_iface_id = wlan_ftm_pkt->cmd.common_ops.wlandeviceno; + if (curr_iface_id != old_iface_id) + { + DPRINTF(FTM_DBG_TRACE, "Initializing Interface: %s\n", ifname); + + if (tcmd_tx_init(ifname, ftm_wlan_tcmd_rx)) + { + DPRINTF(FTM_DBG_ERROR, "Couldn't init tcmd transport!\n"); + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + goto err_out; + } + + DPRINTF(FTM_DBG_TRACE, "tcmd: Initialized Interface: %s\n", ifname); +#ifdef WIN_AP_HOST_OPEN + tcmd_tx_start(); + DPRINTF(FTM_DBG_TRACE, "tcmd: tcmd_tx_start done\n"); +#endif + old_iface_id = curr_iface_id; + } + + resp = isResponseNeeded( (void*)wlan_ftm_pkt->cmd.common_ops.data); + + if (tcmd_tx(wlan_ftm_pkt->cmd.common_ops.data, data_len, resp)) + { + DPRINTF(FTM_DBG_ERROR, "TCMD timed out!\n"); + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + goto err_out; + } + + if (resp) + { + if (g_rsp) + { + diagpkt_free(rsp); + return (void *) g_rsp; + } + else + { + DPRINTF(FTM_DBG_ERROR, "No response got probably timing out.... \n"); + rsp->cmd.common_ops.result = htole32(FTM_ERR_CODE_IOCTL_FAIL); + } + } else { + DPRINTF(FTM_DBG_ERROR, "Resp is false \n"); + } + +err_out: + return (void *) rsp; +} + +/*=========================================================================== +FUNCTION ftm_wlan_bdf_read + +DESCRIPTION + Read the data from bdf_file + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_bdf_read(ftm_wlan_req_pkt_type *wlan_ftm_read_pkt) +{ + FILE *fp; + byte err_code; + int ret; + unsigned long file_size; + unsigned int size; /*actual number of bytes transferred in resp pkt*/ + char *buf = NULL; + struct stat st; + int byte_rem; + uint16 rsp_pkt_size; + ftm_wlan_rsp_pkt_type *ftm_read_resp = NULL; + + rsp_pkt_size = sizeof(ftm_read_resp->common_header) + sizeof(ftm_read_resp->cmd.read_file); + + fp = fopen(bdf_file, "r"); + if (fp == NULL) { + DPRINTF(FTM_DBG_ERROR, " failed to open file: %s\n", bdf_file); + err_code = WLAN_BDF_FILE_OPEN_FAIL; + goto ftm_read_out; + } + st.st_size = 0; + /*get size of the file*/ + if (stat(bdf_file, &st) == 0) + file_size = st.st_size; + else { + DPRINTF(FTM_DBG_ERROR, "Failed to get file size \n"); + err_code = WLAN_BDF_FILE_STAT_FAIL; + goto ftm_read_out; + } + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: %s file size is: %lu\n", bdf_file, file_size); + if (file_size <= wlan_ftm_read_pkt->cmd.read_file.offset) { + DPRINTF(FTM_DBG_ERROR, " Bad offset \n"); + err_code = WLAN_BDF_BAD_OFFSET; + goto ftm_read_out; + } + + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: offset: %d\n", wlan_ftm_read_pkt->cmd.read_file.offset); + ret = fseek(fp, wlan_ftm_read_pkt->cmd.read_file.offset, SEEK_SET); + if (ret == -1) { + DPRINTF(FTM_DBG_ERROR, "fseek failed \n"); + err_code = WLAN_BDF_FILE_SEEK_FAIL; + goto ftm_read_out; + } + + /*validate the size(number of bytes) to be read from file */ + if ((wlan_ftm_read_pkt->cmd_rsp_pkt_size - rsp_pkt_size) > (file_size - wlan_ftm_read_pkt->cmd.read_file.offset)) { + size = file_size - wlan_ftm_read_pkt->cmd.read_file.offset; + } else + size = wlan_ftm_read_pkt->cmd_rsp_pkt_size - rsp_pkt_size; + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: number of bytes to be read: %d\n", size); + + buf = (char *)malloc(size); + if(!buf) { + DPRINTF(FTM_DBG_ERROR, " failed to allocate buf memory \n"); + err_code = WLAN_BDF_READ_FAILED; + goto ftm_read_out; + } + ret = fread(buf, 1, size, fp); + if (ret ==(signed)size || feof(fp)) { + size = ret; + err_code = WLAN_BDF_READ_SUCCESS; + rsp_pkt_size += size; + } else { + DPRINTF(FTM_DBG_ERROR, "ftm_daemon: fread failed\n"); + err_code = WLAN_BDF_READ_FAILED; + } + +ftm_read_out: + if (err_code != WLAN_BDF_READ_SUCCESS) + rsp_pkt_size += 1; //need to send atleast 1 byte of data to diag in case of read failure + + ftm_read_resp = (ftm_wlan_rsp_pkt_type *)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + rsp_pkt_size + ); + if (ftm_read_resp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag resp packet\n"); + if (fp) + fclose(fp); + if (buf) + free(buf); + return NULL; + } + ftm_read_resp->common_header.cmd_id = htole16(FTM_WLAN_BDF_READ); + ftm_read_resp->common_header.cmd_rsp_pkt_size = htole16(rsp_pkt_size); + ftm_read_resp->cmd.read_file.result = err_code; + if (err_code == WLAN_BDF_READ_SUCCESS) { + ftm_read_resp->cmd.read_file.size = htole16(size); + byte_rem = file_size - (size + wlan_ftm_read_pkt->cmd.read_file.offset); + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: byte_rem: %d\n", byte_rem); + memcpy(ftm_read_resp->cmd.read_file.bytes_remaining, &byte_rem, sizeof(ftm_read_resp->cmd.read_file.bytes_remaining)); + memcpy(ftm_read_resp->cmd.read_file.data, buf, size); + } else + memset(ftm_read_resp->cmd.read_file.data, 0, 1); + + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: read resp msg dump:\n"); + print_uchar_array((uint8_t *)ftm_read_resp, (int)rsp_pkt_size); + + if (fp) + fclose(fp); + if (buf) + free(buf); + return (void *)ftm_read_resp; +} + +/*=========================================================================== +FUNCTION ftm_wlan_bdf_write + +DESCRIPTION + Write the data received from application to bdf_file + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_bdf_write(ftm_wlan_req_pkt_type *wlan_ftm_write_pkt) +{ + FILE *fp; + byte err_code; + ftm_wlan_rsp_pkt_type *ftm_write_resp = NULL; + uint16 rsp_pkt_len; + + rsp_pkt_len = sizeof(ftm_write_resp->common_header) + sizeof(ftm_write_resp->cmd.write_file) + 1; + ftm_write_resp = (ftm_wlan_rsp_pkt_type *)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + rsp_pkt_len + ); + if (ftm_write_resp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag resp packet\n"); + return NULL; + } + + if (!wlan_ftm_write_pkt->cmd.write_file.append_flag) { + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: bdf_file = %s open in write mode\n", bdf_file); + fp = fopen(bdf_file, "w"); + if (fp == NULL) { + DPRINTF(FTM_DBG_ERROR, " failed to open file: %s\n", bdf_file); + err_code = WLAN_BDF_FILE_OPEN_FAIL; + goto ftm_write_out; + } + } else { + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: bdf_file = %s open in append mode\n", bdf_file); + fp = fopen(bdf_file, "a"); + if (fp == NULL) { + DPRINTF(FTM_DBG_ERROR, " failed to open file: %s\n", bdf_file); + err_code = WLAN_BDF_FILE_OPEN_FAIL; + goto ftm_write_out; + } + } + + fwrite(&(wlan_ftm_write_pkt->cmd.write_file.data), 1, wlan_ftm_write_pkt->cmd.write_file.size, fp); + if (ferror(fp)) { + DPRINTF(FTM_DBG_ERROR, " failed to write\n"); + err_code = WLAN_BDF_WRITE_FAILED; + } else + err_code = WLAN_BDF_WRITE_SUCCESS; + +ftm_write_out: + if (fp) + fclose(fp); + ftm_write_resp->common_header.cmd_id = htole16(FTM_WLAN_BDF_WRITE); + ftm_write_resp->common_header.cmd_rsp_pkt_size = htole16(rsp_pkt_len); + ftm_write_resp->cmd.write_file.result = err_code; + memset(ftm_write_resp->cmd.write_file.rsvd, 0, + sizeof(ftm_write_resp->cmd.write_file.rsvd)); + memset(ftm_write_resp->cmd.write_file.data, 0, 1); + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: write resp msg dump:\n"); + print_uchar_array((uint8_t *)ftm_write_resp, (int)rsp_pkt_len); + + return (void *)ftm_write_resp; +} + +/*=========================================================================== +FUNCTION ftm_wlan_bdf_get_filename + +DESCRIPTION + Get bdf_file path + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_bdf_get_filename() +{ + ftm_wlan_rsp_pkt_type *ftm_get_fname_resp = NULL; + uint16 rsp_pkt_len; + int fname_len = 1; //allocate 1 byte of data in case of error + byte err_code; + + if (bdf_file[0]) + fname_len = strlen(bdf_file); + + rsp_pkt_len = sizeof(ftm_get_fname_resp->common_header) + sizeof(ftm_get_fname_resp->cmd.get_fname) + fname_len; + ftm_get_fname_resp = (ftm_wlan_rsp_pkt_type *)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + rsp_pkt_len + ); + if (ftm_get_fname_resp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag resp packet\n"); + return NULL; + } + + if (!bdf_file[0] || strlen(bdf_file) > 128) { + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: get_filename failed: bdf_file:%s fname_len: %d\n", bdf_file, fname_len); + err_code = WLAN_BDF_PATH_GET_FAILED; + memset(ftm_get_fname_resp->cmd.get_fname.data, 0, 1); + } else { + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: bdf_file is %s\n", bdf_file); + memcpy(ftm_get_fname_resp->cmd.get_fname.data, bdf_file, fname_len); + err_code = WLAN_BDF_PATH_GET_SUCCESS; + } + + ftm_get_fname_resp->common_header.cmd_id = htole16(FTM_WLAN_BDF_GET_FNAMEPATH); + ftm_get_fname_resp->common_header.cmd_rsp_pkt_size = htole16(rsp_pkt_len); + memset(ftm_get_fname_resp->cmd.get_fname.rsvd, 0, sizeof(ftm_get_fname_resp->cmd.get_fname.rsvd)); + ftm_get_fname_resp->cmd.get_fname.result = err_code; + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: get_filename resp msg dump:\n"); + print_uchar_array((uint8_t *)ftm_get_fname_resp, (int)rsp_pkt_len); + + return (void *)ftm_get_fname_resp; +} + +/*=========================================================================== +FUNCTION ftm_wlan_bdf_set_filename + +DESCRIPTION + Set bdf_file path for further bdf file read/write operation + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_bdf_set_filename(ftm_wlan_req_pkt_type *wlan_ftm_set_fname_pkt) +{ + ftm_wlan_rsp_pkt_type *ftm_set_fname_resp = NULL; + uint16 rsp_pkt_len; + uint16 size; + byte err_code; + + rsp_pkt_len = sizeof(ftm_set_fname_resp->common_header) + sizeof(ftm_set_fname_resp->cmd.set_fname); + size = wlan_ftm_set_fname_pkt->cmd_data_len - rsp_pkt_len; + rsp_pkt_len += 1; //for 1 byte of reserved data + ftm_set_fname_resp = (ftm_wlan_rsp_pkt_type *)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + rsp_pkt_len + ); + if (ftm_set_fname_resp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag resp packet\n"); + return NULL; + } + ftm_set_fname_resp->common_header.cmd_id = htole16(FTM_WLAN_BDF_SET_FNAMEPATH); + + if (size == 0 || size >= 128) { + DPRINTF(FTM_DBG_ERROR, "ftm_daemon: set_filename failed: fname_length %d\n", size); + err_code = WLAN_BDF_PATH_SET_FAILED; + } else { + memcpy(bdf_file, wlan_ftm_set_fname_pkt->cmd.set_fname.data, size); + bdf_file[size] = '\0'; + if (strncmp(bdf_file, "/firmware", 9) == 0) { + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: remount /firmware partition as rw\n"); + system("mount -o rw,remount /firmware /firmware"); + } + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: bdf_file set to %s\n", bdf_file); + err_code = WLAN_BDF_PATH_SET_SUCCESS; + } + + ftm_set_fname_resp->common_header.cmd_rsp_pkt_size = htole16(rsp_pkt_len); + ftm_set_fname_resp->cmd.set_fname.result = err_code; + memset(ftm_set_fname_resp->cmd.set_fname.rsvd, 0, sizeof(ftm_set_fname_resp->cmd.set_fname.rsvd)); + memset(ftm_set_fname_resp->cmd.set_fname.data, 0, 1); + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: set_filename resp msg dump:\n"); + print_uchar_array((uint8_t *)ftm_set_fname_resp, (int)rsp_pkt_len); + return (void *)ftm_set_fname_resp; +} + +/*=========================================================================== +FUNCTION ftm_wlan_bdf_get_max_transfer_size + +DESCRIPTION + Get maximum transfer size(in bytes) for further bdf file read/write operation + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +static void *ftm_wlan_bdf_get_max_transfer_size() +{ + ftm_wlan_rsp_pkt_type *ftm_get_max_size_resp = NULL; + uint16 rsp_pkt_len; + + rsp_pkt_len = sizeof(ftm_get_max_size_resp->common_header) + sizeof(ftm_get_max_size_resp->cmd.get_max_transfer_size); + ftm_get_max_size_resp = (ftm_wlan_rsp_pkt_type *)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + rsp_pkt_len + ); + if (ftm_get_max_size_resp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag resp packet\n"); + return NULL; + } + ftm_get_max_size_resp->common_header.cmd_id = htole16(FTM_WLAN_BDF_GET_MAX_TRANSFER_SIZE); + ftm_get_max_size_resp->common_header.cmd_rsp_pkt_size = htole16(rsp_pkt_len); + ftm_get_max_size_resp->cmd.get_max_transfer_size.max_size = 1024; + ftm_get_max_size_resp->cmd.get_max_transfer_size.result = 0; + memset(ftm_get_max_size_resp->cmd.get_max_transfer_size.rsvd, 0, + sizeof(ftm_get_max_size_resp->cmd.get_max_transfer_size.rsvd)); + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: get_max_transfer_size resp msg dump:\n"); + print_uchar_array((uint8_t *)ftm_get_max_size_resp, (int)rsp_pkt_len); + return (void *)ftm_get_max_size_resp; + } + +#ifdef CONFIG_FTM_WLAN_AUTOLOAD +/*=========================================================================== +FUNCTION + load_wifi_driver_testmode + +DESCRIPTION + Use system call to load driver + +DEPENDENCIES + NIL + +RETURN VALUE + NONE + +SIDE EFFECTS + NONE +===========================================================================*/ + +static int load_wifi_driver_testmode(void) +{ + int ret = 0; + + /* clean-up the driver state */ + if ((ret = unload_wifi_driver())) { + DPRINTF(FTM_DBG_ERROR, "%s: Unload driver failed: %d\n", __func__, ret); + return ret; + } + +#ifdef FTM_WLAN_LOAD_CMD + if ((ret = system(FTM_WLAN_LOAD_CMD))) { + DPRINTF(FTM_DBG_ERROR, "WLAN driver load failed!\n"); + return ret; + } +#else +#error "FTM_WLAN_LOAD_CMD is not defined!" +#endif + + DPRINTF(FTM_DBG_TRACE, "WLAN driver loaded in FTM mode successfully!\n"); + + return ret; +} +/*=========================================================================== +FUNCTION + Unload_wifi_driver if the drvier is detected existing already + +DESCRIPTION + Use system call to unload driver + +DEPENDENCIES + NIL + +RETURN VALUE + NONE + +SIDE EFFECTS + NONE +===========================================================================*/ +static int unload_wifi_driver(void) +{ + int ret = 0; + + if (is_wifi_driver_loaded(DRIVER_MODULE_TAG)) { +#ifdef FTM_WLAN_UNLOAD_CMD + if ((ret = system(FTM_WLAN_UNLOAD_CMD))) { + DPRINTF(FTM_DBG_ERROR, "WLAN driver unload failed!\n"); + return ret; + } +#else +#error "FTM_WLAN_UNLOAD_CMD is not defined!" +#endif + } + + DPRINTF(FTM_DBG_TRACE, "WLAN driver unloaded successfully!\n"); + + return ret; +} + +/*=========================================================================== +FUNCTION + is_wifi_driver_loaded + +DESCRIPTION + Check if WLAN driver is loaded or not + +DEPENDENCIES + NIL + +RETURN VALUE + Returns true if driver already loaded, false if driver not loaded + +SIDE EFFECTS + NONE +===========================================================================*/ +static bool is_wifi_driver_loaded(char *mod_tag) +{ + FILE *proc = NULL; + char cmd[NAME_MAX + 64]; /* File name max + room for command */ + bool ret = false; + + snprintf(cmd, sizeof(cmd), "cat /proc/modules | grep %s", mod_tag); + + proc = popen(cmd, "r"); + + if (proc == NULL) { + DPRINTF(FTM_DBG_ERROR, "%s failed!\n", __func__); + return ret; + } + + if (fread (cmd, 1, sizeof(cmd), proc) > 0) + ret = true; + + fclose(proc); + + return ret; +} +#endif /* CONFIG_FTM_WLAN_AUTOLOAD */ + +/*=========================================================================== +FUNCTION ftm_wlan_dispatch + +DESCRIPTION + WLAN FTM dispatch routine. Main entry point routine for WLAN FTM for + AR6003 + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant to be passed to the diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +void* ftm_wlan_dispatch(ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len) +{ + if (!wlan_ftm_pkt || !pkt_len) { + DPRINTF(FTM_DBG_ERROR, "Invalid ftm wlan Requst Packet\n"); + return NULL; + } +#ifdef DEBUG + current_time(); +#endif + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: cmd: %d\n", wlan_ftm_pkt->cmd_id); + DPRINTF(FTM_DBG_TRACE, "ftm_daemon: Request Packet Dump:\n"); + print_uchar_array((uint8_t *)wlan_ftm_pkt, pkt_len); + + switch (le16toh(wlan_ftm_pkt->cmd_id)) { + case FTM_WLAN_COMMON_OP: + return ftm_wlan_common_op(wlan_ftm_pkt, pkt_len); + case FTM_WLAN_BDF_GET_MAX_TRANSFER_SIZE: + return ftm_wlan_bdf_get_max_transfer_size(); + case FTM_WLAN_BDF_READ: + return ftm_wlan_bdf_read(wlan_ftm_pkt); + case FTM_WLAN_BDF_WRITE: + return ftm_wlan_bdf_write(wlan_ftm_pkt); + case FTM_WLAN_BDF_GET_FNAMEPATH: + return ftm_wlan_bdf_get_filename(); + case FTM_WLAN_BDF_SET_FNAMEPATH: + return ftm_wlan_bdf_set_filename(wlan_ftm_pkt); + default: + DPRINTF(FTM_DBG_ERROR, " Unknown Command\n"); + return NULL; + } +} + + + diff --git a/qca/ftm/src/ftm_wlan.h b/qca/ftm/src/ftm_wlan.h new file mode 100644 index 000000000..fc9e1a5c5 --- /dev/null +++ b/qca/ftm/src/ftm_wlan.h @@ -0,0 +1,221 @@ +/*========================================================================== + + FTM WLAN Header File + +Description + The header file includes enums, struct definitions for WLAN FTM packets + +# Copyright (c) 2010-2011, 2014 by Qualcomm Technologies, Inc. +# All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + + Edit History + + +when who what, where, why +-------- --- ---------------------------------------------------------- +07/11/11 karthikm Created header file to include enums, struct for WLAN FTM + for Atheros support +========================================================================*/ + +#ifndef FTM_WLAN_H_ +#define FTM_WLAN_H_ + +#ifdef CONFIG_FTM_WLAN + +#include "diagpkt.h" +#include + +#define FTM_WLAN_CMD_CODE 22 + +/* TODO: For LE platforms only - need to extend it for BE platform too*/ +#define cpu32_to_le32(buf, val) \ + do { \ + buf[0] = val & 0xff; \ + buf[1] = (val >> 8) & 0xff; \ + buf[2] = (val >> 16) & 0xff; \ + buf[3] = (val >> 24) & 0xff; \ + } while(0) + +/* TODO: For LE platforms only - need to extend it for BE platform too*/ +#define le_to_cpu16(buf, uint16_val) \ + do { \ + uint16_val = (buf[0] | buf[1] << 8); \ + } while(0) + +/* TODO: For LE platforms only - need to extend it for BE platform too*/ +#define le_to_cpu32(buf, uint32_val) \ + do { \ + uint32_val = (buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24); \ + } while(0) + +extern char g_ifname[]; + +/* Various ERROR CODES supported by the FTM WLAN module*/ +typedef enum { + FTM_ERR_CODE_PASS = 0, + FTM_ERR_CODE_IOCTL_FAIL, + FTM_ERR_CODE_SOCK_FAIL, + FTM_ERR_CODE_UNRECOG_FTM +}FTM_WLAN_LOAD_ERROR_CODES; + + +#define CONFIG_HOST_TCMD_SUPPORT 1 +#define AR6000_IOCTL_SUPPORTED 1 + +#define ATH_MAC_LEN 6 + +typedef enum { + FTM_WLAN_COMMON_OP, + FTM_WLAN_BDF_GET_MAX_TRANSFER_SIZE, + FTM_WLAN_BDF_READ, + FTM_WLAN_BDF_WRITE, + FTM_WLAN_BDF_GET_FNAMEPATH, + FTM_WLAN_BDF_SET_FNAMEPATH +}FTM_WLAN_CMD; + +typedef enum { + WLAN_BDF_READ_SUCCESS, + WLAN_BDF_READ_FAILED, + WLAN_BDF_WRITE_SUCCESS, + WLAN_BDF_WRITE_FAILED, + WLAN_BDF_INVALID_SIZE = 5, + WLAN_BDF_BAD_OFFSET, + WLAN_BDF_FILE_OPEN_FAIL, + WLAN_BDF_FILE_SEEK_FAIL, + WLAN_BDF_FILE_STAT_FAIL, + WLAN_BDF_PATH_GET_SUCCESS, + WLAN_BDF_PATH_GET_FAILED, + WLAN_BDF_PATH_SET_SUCCESS, + WLAN_BDF_PATH_SET_FAILED +}FTM_WLAN_ERROR_CODES; + +#ifdef WIN_AP_HOST +#define PACKED_STRUCT __attribute__((__packed__)) +#else +#define PACKED_STRUCT __attribute__((packed)) +#endif + +/*FTM WLAN request type*/ + +typedef struct +{ + diagpkt_cmd_code_type cmd_code; + diagpkt_subsys_id_type subsys_id; + diagpkt_subsys_cmd_code_type subsys_cmd_code; + uint16 cmd_id; /* command id (required) */ + uint16 cmd_data_len; + uint16 cmd_rsp_pkt_size; + union { + struct { + uint16 rsvd; + byte rsvd1; + byte rsvd2; + byte wlanslotno; + byte wlandeviceno; + byte data[0]; + }PACKED_STRUCT common_ops; + struct { + byte rsvd[6]; + byte data[0]; + }PACKED_STRUCT get_max_transfer_size; + struct { + uint32 offset; + byte rsvd[2]; + byte data[0]; + }PACKED_STRUCT read_file; + struct { + uint16 size; + uint8 append_flag; + byte rsvd[3]; + byte data[0]; + }PACKED_STRUCT write_file; + struct { + byte rsvd[6]; + byte data[0]; + }PACKED_STRUCT get_fname; + struct { + byte rsvd[6]; + byte data[0]; + }PACKED_STRUCT set_fname; + }cmd; +}PACKED_STRUCT ftm_wlan_req_pkt_type; + +/*FTM WLAM response type */ +typedef struct +{ + struct { + diagpkt_subsys_header_type header; /*diag header*/ + uint16 cmd_id; /* command id (required) */ + uint16 cmd_data_len; + uint16 cmd_rsp_pkt_size; + }PACKED_STRUCT common_header; + union { + struct { + uint16 rsvd; + uint32 result ;/* error_code */ + union { + struct { + byte data[0]; /*rxReport*/ + }rxReport; + struct { + byte data[0]; /*ThermValReport*/ + }thermval_report; + }rx_and_therm; + }PACKED_STRUCT common_ops; + struct { + uint16 result; /*error_code*/ + byte rsvd[4]; + uint16 max_size; + }PACKED_STRUCT get_max_transfer_size; + struct { + byte result; /*error_code*/ + uint16 size; + byte bytes_remaining[3]; + byte data[0]; + }PACKED_STRUCT read_file; + struct { + byte result; + byte rsvd[5]; + byte data[0]; + }PACKED_STRUCT write_file; + struct { + byte result; + byte rsvd[5]; + byte data[0]; + }PACKED_STRUCT get_fname; + struct { + byte result; + byte rsvd[5]; + byte data[0]; + }PACKED_STRUCT set_fname; + struct { + uint16 win_cmd_specific; + uint16 data_len; + uint8 rsvd; + uint8 wlandeviceno; + byte data[0]; + }PACKED_STRUCT win_resp; + }cmd; +}PACKED_STRUCT ftm_wlan_rsp_pkt_type; + +void* ftm_wlan_dispatch(ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len); + +#ifdef WIN_AP_HOST +void setBoardDataCaptureFlag (int flag); +void setDeviceId(int id); +extern ftm_wlan_rsp_pkt_type *win_bt_mac_flash_write( + ftm_wlan_req_pkt_type *wlan_ftm_pkt, + int pkt_len); + +extern void win_host_handle_fw_resp (ftm_wlan_rsp_pkt_type *rsp, void *data, uint32_t data_len); +extern ftm_wlan_rsp_pkt_type *win_host_handle_bdf_req( + ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len); +#endif + +#endif /* CONFIG_FTM_WLAN */ +#endif /* FTM_WLAN_H_ */ diff --git a/qca/ftm/src/ftm_wlan_win.h b/qca/ftm/src/ftm_wlan_win.h new file mode 100644 index 000000000..0a4c51683 --- /dev/null +++ b/qca/ftm/src/ftm_wlan_win.h @@ -0,0 +1,194 @@ +/* +*Copyright (c) 2017-2019 Qualcomm Technologies, Inc. +* +*All Rights Reserved. +*Confidential and Proprietary - Qualcomm Technologies, Inc. +*/ + +#ifndef __FTM_WLAN_WIN_H +#define __FTM_WLAN_WIN_H + +#include +#include +#include +#include +#include +#include + +#include +#include +#include "comdef.h" +#include "diagcmd.h" + +#include "ftm_wlan.h" +#include "ftm_dbg.h" + +#define MAC_XTAL_LENGTH 7 +#define MAC_LENGTH_POS 103 +#define MAC_POS 105 +#define BT_TLV1_RESP_LEN 84 +#define BT_RESP_LEN 100 +#define FLASH_SECTOR_SIZE 0x10000 +#define BD_LEN_EXPECTED 500 +#define BD_SIZE_REQ_ID 106 +#define BD_SIZE_REQ_POS 28 +#define BD_SIZE_VAL 60 + +/* Identifier for first segment of + * Board data response + */ +#define FIRST_SEG 48 + +/* Identifier for second segment of + * board data response + */ +#define SECOND_SEG 49 +#define THIRD_SEG 50 +#define NO_ERROR 0 + +/* header length for first segment of + * board data response + */ +#define FIRST_SEG_TLV_HDR 84 +#define SECOND_SEG_TLV_HDR 28 +#define THIRD_SEG_TLV_HDR 28 + +#define SEQUENCE_ID_POS 24 + +/* Position at which first parameter of + * TLV request is located + */ +#define TLV_PAYLOAD_PARAM_1 80 + +/* Position at which second paramter of + * TLV request is located + */ +#define TLV_PAYLOAD_PARAM_2 96 + +/* Parameter 1 value if request is for + * board data capture + */ +#define BD_CAPTURE_REQ 101 + +/* Parameter 1 value if flash write request */ +#define FLASH_WRITE_REQ 102 + +/* Parameter 1 value for device identify request */ +#define DEVICE_IDENTIFY 103 + + +/* Parameter 2 value for swift device identify */ +#define QC9887_DEVICE_ID 0x50 +#define QC9888_DEVICE_ID 0x3c +#define QC99xx_DEVICE_ID 0x46 +#define QCN9000_DEVICE_ID 0x1104 + +#define TLV1_CMD_RESP_SIZE 118 +#define TLV1_RESP_LEN 102 + +/* Offset at which BT_mac is to be stored in flash */ +#define BT_MAC_OFFSET 0x40 + +#define FLASH_BASE_CALDATA_OFFSET_SOC_0 0x1000 +#define FLASH_BASE_CALDATA_OFFSET_SOC_1 0x33000 +#define REQ_SEG_SIZE 4096 + +#define FLASH_BASE_CALDATA_OFFSET_PCI_1 0x26800 +#define FLASH_BASE_CALDATA_OFFSET_PCI_2 0x4C000 + +#define DIAG_HDR_LEN 16 + +#define FLASH_PARTITION "/dev/caldata" +#define VIRTUAL_FLASH_PARTITION "/tmp/virtual_art.bin" +#define WRITE_ART "/lib/compress_vart.sh write_caldata" + +/* (0x33000-0x1000)=0x32000, Max available BDF size */ +#define MAX_BDF_SIZE 200*1024 + +#define QC98XX_BLOCK_SIZE 512 + +#define BD_BLOCK_SIZE 256 + +/* Position of block size for the data */ +#define QC98XX_BLOCK_SIZE_VAL 164 + +/* Position of block size for the data (radio != qc98XX) */ +#define LEGACY_BLOCK_SIZE_VAL 100 + +#define M_EEEPROM_BLOCK_READ_ID_QC98XX 0xC8 + +#define M_EEEPROM_BLOCK_READ_ID_LEGACY 0xE9 + +/* Position where block data starts */ +#define QC98XX_BLOCK_START_POS 200 + +#define LEGACY_BLOCK_START_POS 104 + +#define BD_READ_CMD_ID_POS 48 + +#define BD_READ_RESP_PARAM_POS 88 + +#define BD_READ_RESP_PARAM 0x7 + +/* Use of this parameter is not known */ +#define LEGACY_RADIO_PARAM_POS 103 + +#define LEGACY_RADIO_PARAM_THRESHOLD 0x30 + +/* Valid caldata in each segment from FW */ +#define CALDATA_SIZE_FIRST_SEG 1480 +#define CALDATA_SIZE_SECOND_SEG 1536 +#define CALDATA_SIZE_THIRD_SEG 1080 + + +uint16_t TLV2_Specific_byte; + +unsigned char BDbuffer[MAX_BDF_SIZE]; +uint32_t BDbuffer_offset; +uint32_t resp_counter; +uint32_t bd_size; +uint8_t start_capture; + +/* Deviceno is the instance id sent from + * Qdart for the radio. + */ +int deviceno; + +/* Device id received in the radio's + * radio flash write requests, defaults to 0 + */ +int deviceid = 0; + +/* This is the remainder after whole 4096 size responses are sent */ +uint32_t remaining_bytes ; +uint32_t total_4K_responses; + +unsigned char BTsetmacResponse[] = { + 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x38, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC6, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* Response sent for BDcapture and Flash write Requests */ +unsigned char ftm_wlan_tlvRespMsg[] = { + 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x4A, 0x00, 0x00, 0x00, + 0x72, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xEA, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x2F +}; + +#endif /* __FTM_WLAN_WIN_H */ + diff --git a/qca/ftm/src/ftm_write_to_flash.c b/qca/ftm/src/ftm_write_to_flash.c new file mode 100644 index 000000000..6de1cc41a --- /dev/null +++ b/qca/ftm/src/ftm_write_to_flash.c @@ -0,0 +1,505 @@ +/* +*Copyright (c) 2017-2019 Qualcomm Technologies, Inc. +* +*All Rights Reserved. +*Confidential and Proprietary - Qualcomm Technologies, Inc. +*/ + +#ifdef WIN_AP_HOST + +#include "ftm_wlan_win.h" +#include + +/*=========================================================================== +FUNCTION bt_setmac_flash_write + +DESCRIPTION + Write MAC and XTAL to flash region + +DEPENDENCIES + NIL + +RETURN VALUE + Returns status success or failure + +SIDE EFFECTS + NONE + +===========================================================================*/ +int bt_setmac_flash_write(uint8_t *mac, unsigned int len) +{ + int fd; + int offset; + int i; + uint8_t *flashdata; + + fd = open(VIRTUAL_FLASH_PARTITION, O_RDWR); + + if (fd < 0) { + perror("Could not open flash. Returning without write\n"); + return -1; + } + + DPRINTF(FTM_DBG_TRACE,"\nNumber of bytes = %d\n",len); + + offset = BT_MAC_OFFSET; + lseek(fd, offset, SEEK_SET); + if (write(fd, mac, len) < 1) { + DPRINTF(FTM_DBG_TRACE,"flash write error. Returning\n"); + close(fd); + return -1; + } + + DPRINTF(FTM_DBG_TRACE, + "BT mac written successfully to flash @ offset %X size %X\n", + offset, len); + + flashdata = (uint8_t *)malloc(len); + if (!flashdata){ + DPRINTF(FTM_DBG_TRACE, "Write verification failed. Unable to allocate memory.\n"); + close(fd); + return -1; + } + + lseek(fd, offset, SEEK_SET); + if (read(fd, flashdata, len) < 1){ + DPRINTF(FTM_DBG_TRACE, "Flashdata read failed\n"); + free(flashdata); + return -1; + } + for(i = 0; i < len; i++){ + DPRINTF(FTM_DBG_TRACE, "input mac = 0x%x, flashdata = 0x%x\n", mac[i], flashdata[i]); + } + + free(flashdata); + close(fd); + return 1; +} + + +/*=========================================================================== +FUNCTION win_bt_mac_flash_write + +DESCRIPTION + Call bt_setmac_flash_write function and populate response to Qdart + +DEPENDENCIES + NIL + +RETURN VALUE + Returns resp to qdart + +SIDE EFFECTS + NONE + +===========================================================================*/ +ftm_wlan_rsp_pkt_type *win_bt_mac_flash_write(ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len) +{ + int i; + int status; + ftm_wlan_rsp_pkt_type *rsp; + unsigned char BtDiagMAC[MAC_XTAL_LENGTH]; + unsigned int dataLen = 0; + uint8_t *input_msg = (uint8_t*)wlan_ftm_pkt; + TLV2_Specific_byte = wlan_ftm_pkt->cmd.common_ops.rsvd; + + dataLen = input_msg[MAC_LENGTH_POS]; + for(i=0; icommon_header) + + sizeof(rsp->cmd.common_ops)+ + BT_TLV1_RESP_LEN )); + if (!rsp) + return rsp; + + rsp->common_header.cmd_rsp_pkt_size = BT_RESP_LEN; + rsp->common_header.cmd_data_len = 0; + rsp->cmd.win_resp.data_len = BT_TLV1_RESP_LEN; + rsp->cmd.win_resp.win_cmd_specific = TLV2_Specific_byte; + + status = bt_setmac_flash_write(BtDiagMAC, dataLen); + if (status > 0) { + memcpy(rsp->cmd.win_resp.data, BTsetmacResponse, BT_TLV1_RESP_LEN); + DPRINTF(FTM_DBG_TRACE,"Response sent to Qdart\n"); + /*print_uchar_array((uint8_t*)(rsp->cmd.win_resp.data), BT_TLV1_RESP_LEN);*/ + return rsp; + } + else + return rsp; +} + +/*=========================================================================== +FUNCTION win_host_handle_bdf_req + +DESCRIPTION + Function to process WIN specific bdf requests. + This handles the requests related to device identify, + boarddata capture and flash write requests, and sends + the response to QDART. + + +DEPENDENCIES + NIL + +RETURN VALUE + Returns back buffer that is meant for diag callback + +SIDE EFFECTS + NONE + +===========================================================================*/ +ftm_wlan_rsp_pkt_type *win_host_handle_bdf_req(ftm_wlan_req_pkt_type *wlan_ftm_pkt, int pkt_len) +{ + uint8_t *input_msg = (uint8_t*)wlan_ftm_pkt; + int error = 0; + int fd; + int file_offset; + int art_slot_id; + ftm_wlan_rsp_pkt_type *rsp; + deviceno = wlan_ftm_pkt->cmd.common_ops.wlandeviceno; + art_slot_id = wlan_ftm_pkt->cmd.common_ops.wlanslotno; + TLV2_Specific_byte = wlan_ftm_pkt->cmd.common_ops.rsvd; + rsp = (ftm_wlan_rsp_pkt_type*)diagpkt_subsys_alloc(DIAG_SUBSYS_FTM, + FTM_WLAN_CMD_CODE, + (sizeof(rsp->common_header) + + sizeof(rsp->cmd.common_ops)+ + TLV1_RESP_LEN)); + + if (rsp == NULL) { + DPRINTF(FTM_DBG_ERROR, "Failed to allocate Diag packet: %p\n", rsp); + return rsp; + } + rsp->cmd.win_resp.win_cmd_specific = htole16(TLV2_Specific_byte); + rsp->common_header.cmd_rsp_pkt_size = htole16(TLV1_CMD_RESP_SIZE); + rsp->common_header.cmd_data_len = 0; + rsp->cmd.win_resp.data_len = htole16(TLV1_RESP_LEN); + rsp->cmd.win_resp.rsvd = 0; + rsp->cmd.win_resp.wlandeviceno = deviceno; + + DPRINTF(FTM_DBG_TRACE, "Received FTM daemon specific TLV\n"); + + /* Byte 80 in request signifies type of request, 101 is used for BD capture*/ + if(input_msg[TLV_PAYLOAD_PARAM_1] == BD_CAPTURE_REQ) { + DPRINTF(FTM_DBG_TRACE, "BOARD_DATA_CAPTURE\n"); + if (input_msg[TLV_PAYLOAD_PARAM_2] == 1) { + setBoardDataCaptureFlag(1); + } else if (input_msg[TLV_PAYLOAD_PARAM_2] == 0) { + setBoardDataCaptureFlag(0); + } + + } else if (input_msg[TLV_PAYLOAD_PARAM_1] == FLASH_WRITE_REQ) { + fd = open(VIRTUAL_FLASH_PARTITION, O_RDWR); + if (fd < 0) { + DPRINTF(FTM_DBG_TRACE, "FILE OPEN FAILED\n"); + error = WLAN_BDF_FILE_OPEN_FAIL; + } else { + DPRINTF(FTM_DBG_TRACE, "FILE OPEN SUCCESSFULL\n"); + if (!deviceid) { + file_offset = FLASH_BASE_CALDATA_OFFSET_SOC_0; + + if(art_slot_id == 1) + file_offset = FLASH_BASE_CALDATA_OFFSET_PCI_1; + else if(art_slot_id == 2) + file_offset = FLASH_BASE_CALDATA_OFFSET_PCI_2; + + } else if (deviceid == QC9887_DEVICE_ID || + deviceid == QC9888_DEVICE_ID) { + file_offset = FLASH_BASE_CALDATA_OFFSET_SOC_1; + } else if (deviceid == QC99xx_DEVICE_ID) { + file_offset = FLASH_BASE_CALDATA_OFFSET_SOC_1; + } else if (deviceid == QCN9000_DEVICE_ID) { + if(art_slot_id == 1) + file_offset = FLASH_BASE_CALDATA_OFFSET_PCI_1; + else if(art_slot_id == 2) + file_offset = FLASH_BASE_CALDATA_OFFSET_PCI_2; + else { + close(fd); + return rsp; + } + } else { + DPRINTF(FTM_DBG_TRACE, "%s:%d - Invalid Device ID %d\n", + __func__, __LINE__, deviceid); + close(fd); + return rsp; + } + lseek(fd, file_offset, SEEK_SET); + if (write(fd, BDbuffer , BDbuffer_offset) < 1) { + DPRINTF(FTM_DBG_TRACE, "%s:%d - Flash write error\n", + __func__, __LINE__); + error = WLAN_BDF_WRITE_FAILED; + close(fd); + } else { + fsync(fd); + close(fd); + system(WRITE_ART); + + DPRINTF(FTM_DBG_INFO, + "Flash commit success @ offset %0x Size %d\n", + file_offset, BDbuffer_offset); + } + } + + } else if (input_msg[TLV_PAYLOAD_PARAM_1] == DEVICE_IDENTIFY) { + DPRINTF(FTM_DBG_TRACE, "Device Identify \n"); + setDeviceId(input_msg[TLV_PAYLOAD_PARAM_2]); + } + if (error!=NO_ERROR) + /* These commands will not go to firmware */ + return rsp; + else { + memcpy(rsp->cmd.win_resp.data, ftm_wlan_tlvRespMsg, TLV1_RESP_LEN); + return rsp; + } +} + +/*=========================================================================== +FUNCTION setBordDataCaptureFlag + +DESCRIPTION + Sets the BDCapture variable + +DEPENDENCIES + NIL + +RETURN VALUE + NONE + +SIDE EFFECTS + NONE + +===========================================================================*/ +void setBoardDataCaptureFlag (int flag) +{ + DPRINTF(FTM_DBG_TRACE, "Setting BDCapture flag to %d\n", flag); + if (flag == 1) { + BDbuffer_offset = 0; + resp_counter = 0; + start_capture = 1; + } + + // when board data capture is turned off, set the device id to 0 + if (flag == 0){ + start_capture = 0; + setDeviceId(0); + } +} + +/*=========================================================================== +FUNCTION setDeviceId + +DESCRIPTION + Sets the global variable device id, upon requests + according to the parameter 2 of the TLV command + +DEPENDENCIES + NIL + +RETURN VALUE + NONE + +SIDE EFFECTS + NONE +============================================================================*/ +void setDeviceId(int id) +{ + DPRINTF(FTM_DBG_TRACE, "Setting Device id to %d\n", id); + deviceid = id; +} + +/*=========================================================================== +FUNCTION win_host_handle_fw_resp + +DESCRIPTION + WIN specific handler for responses from FW. + FW responses for board data are snooped here + and stored in a global buffer which is then + accessed by the WIN request handler for flash + write requests. + +DEPENDENCIES + NIL + +RETURN VALUE + 0 on success + 1 on failure + +SIDE EFFECTS + NONE +===========================================================================*/ + +void win_host_handle_fw_resp (ftm_wlan_rsp_pkt_type *rsp, void *data, uint32_t data_len) +{ + uint32_t sequence_id; + int legacy_dataSize; + if (!rsp || !data || !data_len) { + DPRINTF(FTM_DBG_ERROR, "rsp/data is NULL\n"); + rsp = NULL; + return; + } + rsp->cmd.win_resp.win_cmd_specific = htole16(TLV2_Specific_byte); + rsp->common_header.cmd_rsp_pkt_size = htole16(data_len + DIAG_HDR_LEN); + rsp->cmd.win_resp.data_len = htole16(data_len); + rsp->cmd.win_resp.wlandeviceno = deviceno; + rsp->cmd.win_resp.rsvd = 0; + memcpy(rsp->cmd.win_resp.data, data, data_len); + + /*TODO: Need better identification method for BDF responses*/ + /* Check if the deviceid is set */ + + switch (deviceid) { + + /* DeviceId is 0 for HK and lithium family targets */ + case 0: + { /* Check if request is for BD_get size. */ + if (((uint8_t *)data)[BD_SIZE_REQ_POS] == BD_SIZE_REQ_ID ) { + bd_size = 0 ; + BDbuffer_offset = 0; + resp_counter = 0; + le_to_cpu32(((uint8_t *)data + BD_SIZE_VAL), bd_size); + DPRINTF(FTM_DBG_INFO, "bd_size = %d \n", bd_size); + total_4K_responses = bd_size / REQ_SEG_SIZE; + remaining_bytes = bd_size % REQ_SEG_SIZE; + DPRINTF(FTM_DBG_INFO, "Total_responses= %d \n", + total_4K_responses); + DPRINTF(FTM_DBG_INFO, "Remaining_bytes = %d \n", + remaining_bytes); + } + + if (data_len > BD_LEN_EXPECTED && start_capture == 1) { + sequence_id = ((uint8_t *)data)[SEQUENCE_ID_POS]; + DPRINTF(FTM_DBG_INFO, "Sequence_ID= %d\n", sequence_id); + + if (sequence_id == FIRST_SEG) + resp_counter ++; + DPRINTF(FTM_DBG_INFO, "Response counter == %d\n", + resp_counter); + DPRINTF(FTM_DBG_INFO, "Buffer offset == %d\n", + BDbuffer_offset); + + if (resp_counter < total_4K_responses + 1) { + /* Handle 3 segments of BDF resonses + * 1st segment - BDF is from offset 84 + * 2nd segment - BDF is from offset 28 + * 3rd segment - BDF is from offset 28 + */ + switch (sequence_id) { + + case FIRST_SEG: + memcpy(BDbuffer + BDbuffer_offset, + (void *)((uint8_t*)data + FIRST_SEG_TLV_HDR), + data_len - FIRST_SEG_TLV_HDR); + BDbuffer_offset += (data_len - FIRST_SEG_TLV_HDR); + break; + + case SECOND_SEG: + memcpy(BDbuffer + BDbuffer_offset, + (void *)((uint8_t *)data + SECOND_SEG_TLV_HDR), + data_len - SECOND_SEG_TLV_HDR); + BDbuffer_offset += (data_len - SECOND_SEG_TLV_HDR); + break; + + case THIRD_SEG: + memcpy(BDbuffer + BDbuffer_offset, + (void *)((uint8_t*)data + THIRD_SEG_TLV_HDR), + data_len - THIRD_SEG_TLV_HDR); + BDbuffer_offset += (data_len - THIRD_SEG_TLV_HDR); + break; + + default: + /* error */ + break; + + } + /* In case of total bdf data size not being a multiple + * of 4k, extra remaining bdf data is handled based on + * which segment of 4k it belongs to. + */ + } else { + switch (sequence_id) { + case FIRST_SEG: + if (remaining_bytes < CALDATA_SIZE_FIRST_SEG) { + memcpy(BDbuffer + BDbuffer_offset, + data + FIRST_SEG_TLV_HDR, + remaining_bytes); + BDbuffer_offset += remaining_bytes; + } else { + memcpy(BDbuffer + BDbuffer_offset, + data + FIRST_SEG_TLV_HDR, + data_len - FIRST_SEG_TLV_HDR); + BDbuffer_offset += (data_len - FIRST_SEG_TLV_HDR); + remaining_bytes -= CALDATA_SIZE_FIRST_SEG; + } + break; + + case SECOND_SEG: + if (remaining_bytes < CALDATA_SIZE_SECOND_SEG) { + memcpy(BDbuffer + BDbuffer_offset, + data + SECOND_SEG_TLV_HDR, + remaining_bytes); + BDbuffer_offset += remaining_bytes; + } else { + memcpy(BDbuffer + BDbuffer_offset, + data + SECOND_SEG_TLV_HDR, + data_len - SECOND_SEG_TLV_HDR); + BDbuffer_offset += (data_len - SECOND_SEG_TLV_HDR); + remaining_bytes -= CALDATA_SIZE_SECOND_SEG; + } + break; + + case THIRD_SEG: + memcpy(BDbuffer + BDbuffer_offset, + (void *)((uint8_t*)data + THIRD_SEG_TLV_HDR), + remaining_bytes); + BDbuffer_offset += remaining_bytes; + break; + } + } + } + break; + } + case QC9887_DEVICE_ID: + case QC9888_DEVICE_ID: + { + if ((((uint8_t *)data)[BD_READ_CMD_ID_POS] == M_EEEPROM_BLOCK_READ_ID_QC98XX) && + (((uint8_t *)data)[BD_READ_RESP_PARAM_POS] == BD_READ_RESP_PARAM)){ + le_to_cpu32(((uint8_t *)data + QC98XX_BLOCK_SIZE_VAL), + legacy_dataSize); + DPRINTF(FTM_DBG_TRACE, + "Capturing Caldata for QC98xx by FTM :: Size %d\n", + legacy_dataSize); + DPRINTF(FTM_DBG_TRACE, + "BDbuffer Offset : %d \n", + (resp_counter * QC98XX_BLOCK_SIZE)); + memcpy(BDbuffer + BDbuffer_offset, (void *)((uint8_t *)data + + QC98XX_BLOCK_START_POS), + legacy_dataSize); + resp_counter = resp_counter + 1; + BDbuffer_offset += legacy_dataSize; + } + break; + } + case QC99xx_DEVICE_ID: + { + if ((((uint8_t *)data)[BD_READ_CMD_ID_POS] == M_EEEPROM_BLOCK_READ_ID_LEGACY) && + (((uint8_t *)data)[BD_READ_RESP_PARAM_POS] == BD_READ_RESP_PARAM) && + ((uint8_t *)data)[LEGACY_RADIO_PARAM_POS] < LEGACY_RADIO_PARAM_THRESHOLD) { + le_to_cpu16(((uint8_t *)data + LEGACY_BLOCK_SIZE_VAL), legacy_dataSize); + DPRINTF(FTM_DBG_TRACE, + "Capturing Caldata by FTM :: Size %d\n", + legacy_dataSize); + DPRINTF(FTM_DBG_TRACE, + "BDbuffer Offset : %d \n", + (resp_counter * BD_BLOCK_SIZE)); + memcpy(BDbuffer + BDbuffer_offset, + (void *)((uint8_t *)data + LEGACY_BLOCK_START_POS), + legacy_dataSize); + resp_counter = resp_counter + 1; + BDbuffer_offset+=legacy_dataSize; + } + break; + } + } +} +#endif diff --git a/qca/ftm/src/testcmd.h b/qca/ftm/src/testcmd.h new file mode 100644 index 000000000..9a7b89934 --- /dev/null +++ b/qca/ftm/src/testcmd.h @@ -0,0 +1,159 @@ +/*========================================================================== + + TCMD header File + +# Copyright (c) 2011, 2013-2014 by Qualcomm Technologies, Inc. +# All Rights Reserved. +# Qualcomm Technologies Proprietary and Confidential. + +===========================================================================*/ + +/*=========================================================================== + +*/ + +/* + * Copyright (c) 2006 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// + * + */ + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#include + +#ifdef AR6002_REV2 +#define TCMD_MAX_RATES 12 +#else +#define TCMD_MAX_RATES 28 +#endif + +#define PREPACK +#define POSTPACK __attribute__ ((packed)) + +#define ATH_MAC_LEN 6 +#define TC_CMDS_SIZE_MAX 256 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS = 0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE, + TC_CMD_RESP, + TCMD_CONT_RX_GETMAC, +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + uint32_t testCmdId; + uint32_t act; + uint32_t enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + uint32_t freq; + uint32_t antenna; + uint32_t wlanMode; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + uint32_t totalPkt; + int32_t rssiInDBm; + uint32_t crcErrPkt; + uint32_t secErrPkt; + uint16_t rateCnt[TCMD_MAX_RATES]; + uint16_t rateCntShortGuard[TCMD_MAX_RATES]; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + char addr[ATH_MAC_LEN]; + char btaddr[ATH_MAC_LEN]; + uint16_t regDmn[2]; + uint32_t otpWriteFlag; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + uint32_t antswitch1; + uint32_t antswitch2; + } POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +typedef enum { + TC_CMDS_TS =0, + TC_CMDS_CAL, + TC_CMDS_TPCCAL = TC_CMDS_CAL, + TC_CMDS_TPCCAL_WITH_OTPWRITE, + TC_CMDS_OTPDUMP, + TC_CMDS_OTPSTREAMWRITE, + TC_CMDS_EFUSEDUMP, + TC_CMDS_EFUSEWRITE, + TC_CMDS_READTHERMAL, +} TC_CMDS_ACT; + +typedef PREPACK struct { + uint32_t testCmdId; + uint32_t act; + PREPACK union { + uint32_t enANI; // to be identical to CONT_RX struct + struct PREPACK { + uint16_t length; + uint8_t version; + uint8_t bufLen; + } POSTPACK parm; + } POSTPACK u; +} POSTPACK TC_CMDS_HDR; + +typedef PREPACK struct { + TC_CMDS_HDR hdr; + char buf[TC_CMDS_SIZE_MAX]; +} POSTPACK TC_CMDS; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID, + TC_CMDS_ID, + TCMD_SET_REG_ID, + TC_CMD_TLV_ID, + OP_GENERIC_NART_CMD = 8, + + /*For synergy purpose we added the following tcmd id but these + tcmd's will not go to the firmware instead we will write values + to the NV area */ + + TCMD_NIC_MAC = 100, + TCMD_CAL_FILE_INDEX = 101, + TCMD_LOAD_DRIVER = 102, + TCMD_SET_MAC_ADDR = 198, +} TCMD_ID; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff --git a/qca/ftm/src/wds/Android.mk b/qca/ftm/src/wds/Android.mk new file mode 100644 index 000000000..1d00d925b --- /dev/null +++ b/qca/ftm/src/wds/Android.mk @@ -0,0 +1,45 @@ +ifeq ($(call is-vendor-board-platform,QCOM),true) +ifeq ($(findstring true, $(BOARD_HAVE_QCOM_FM) $(BOARD_HAVE_BLUETOOTH)),true) + +LOCAL_PATH := $(call my-dir) + +include $(CLEAR_VARS) + +BDROID_DIR:= system/bt +ifeq ($(TARGET_SUPPORTS_WEARABLES),true) +QTI_DIR := hardware/qcom/bt/msm8909/libbt-vendor +else +QTI_DIR := hardware/qcom/bt/libbt-vendor +endif + +LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/common/inc +LOCAL_C_INCLUDES += $(BDROID_DIR)/hci/include +LOCAL_C_INCLUDES += $(QTI_DIR)/include +ifeq ($(TARGET_SUPPORTS_WEARABLES),true) +LOCAL_C_INCLUDES += device/qcom/msm8909w/opensource/bluetooth/tools/hidl_client/inc +else +LOCAL_C_INCLUDES += vendor/qcom/opensource/bluetooth/tools/hidl_client/inc +endif + +LOCAL_CFLAGS := -DANDROID + +ifneq ($(BOARD_ANT_WIRELESS_DEVICE), ) +LOCAL_CFLAGS += -DCONFIG_ANT +endif +LOCAL_SRC_FILES := wds_main.c +LOCAL_SRC_FILES += wds_hci_pfal_linux.c + +LOCAL_MODULE_PATH := $(TARGET_OUT_VENDOR_EXECUTABLES) +LOCAL_MODULE := wdsdaemon +ifeq ($(PRODUCT_VENDOR_MOVE_ENABLED),true) +LOCAL_PROPRIETARY_MODULE := true +endif +LOCAL_MODULE_TAGS := optional +LOCAL_SHARED_LIBRARIES := libdiag +LOCAL_SHARED_LIBRARIES += libcutils \ + libdl \ + libbt-hidlclient + +include $(BUILD_EXECUTABLE) +endif # filter +endif # is-vendor-board-platform diff --git a/qca/ftm/src/wds/wds_hci_pfal.h b/qca/ftm/src/wds/wds_hci_pfal.h new file mode 100644 index 000000000..60bd8830f --- /dev/null +++ b/qca/ftm/src/wds/wds_hci_pfal.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2016 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Copyright (c) 2012 by Qualcomm Atheros, Inc.. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + */ + +#ifndef DEBUG +#define DEBUG printf +#endif + +#ifndef ERROR +#define ERROR printf +#endif + +#include "bt_vendor_qcom.h" + +/* error codes */ +enum { + STATUS_SUCCESS, + STATUS_ERROR, + STATUS_INVALID_LENGTH, + STATUS_NO_MEMORY, + STATUS_NULL_POINTER, + STATUS_CLIENT_ERROR, +}; + +enum { + RX_ERROR = -1, + RX_BT_EVT_IND = 1, + RX_BT_HDR, + RX_BT_DATA, + RX_ANT_HDR, + RX_ANT_DATA, + RX_FM_EVT_IND, + RX_FM_HDR, + RX_FM_DATA, + RX_PKT_IND +}; + +enum pkt_type { + BT_PKT_TYPE = 1, + FM_PKT_TYPE, + ANT_PKT_TYPE +}; +/* device to communicate between PC and DUT */ +#define BT_HS_NMEA_DEVICE "/dev/ttyGS0" +#define BT_HSLITE_UART_DEVICE "/dev/ttyHSL0" + +/* interface between PC-DUT */ +typedef struct pc_uart_interafce { + unsigned char *intf; + int uart_fd; +} pc_uart_interface; + +typedef union pc_interface { + pc_uart_interface uart; +} pc_interface; + +/* device to communicate between DUT and BTSOC */ +#define APPS_RIVA_FM_CMD_CH "/dev/smd1" +#define APPS_RIVA_BT_ACL_CH "/dev/smd2" +#define APPS_RIVA_BT_CMD_CH "/dev/smd3" +#define APPS_RIVA_ANT_CMD "/dev/smd5" +#define APPS_RIVA_ANT_DATA "/dev/smd6" +#define BT_HS_UART_DEVICE "/dev/ttyHS0" + +/* SMD interface between DUT-SOC */ +typedef struct soc_smd_interface { + unsigned char *fm_cmd; + unsigned char *bt_acl; + unsigned char *bt_cmd; + unsigned char *ant_cmd; + unsigned char *ant_data; + int fm_cmd_fd; + int bt_acl_fd; + int bt_cmd_fd; + int ant_cmd_fd; + int ant_data_fd; +} soc_smd_interface; + +/* UART interface between DUT-SOC */ +typedef struct soc_uart_interface { + unsigned char *intf; + int uart_fd; +} soc_uart_interface; + +typedef union soc_interface { + soc_smd_interface smd; + soc_uart_interface uart; +} soc_interface; + +/* context for wdsdaemon */ +typedef struct wdsdaemon { + int mode; + int soc_type; + bool pcinit_mask; + pc_interface pc_if; + soc_interface soc_if; + bool is_server_enabled; + int server_socket_fd; + pthread_t soc_rthread; +} wdsdaemon; + +/* packet types */ +#define PACKET_TYPE_INVALID (0) +#define PACKET_TYPE_BT_CMD (1) +#define PACKET_TYPE_FM_CMD (2) +#define PACKET_TYPE_BT_ACL (3) +#define PACKET_TYPE_ANT_CMD (4) +#define PACKET_TYPE_ANT_DATA (5) + +/* operation modes for wdsdaemon */ +#define MODE_BT_SMD (0) +#define MODE_FM_SMD (1) +#define MODE_ANT_SMD (2) +#define MODE_ALL_SMD (3) +#define MODE_BT_UART (4) +#define MODE_ANT_UART (5) +#define MODE_FM_UART (6) + +/* Bluetooth Header */ +#define BT_CMD_PKT_HDR_LEN (2) +#define BT_EVT_PKT_HDR_LEN (2) +#define BT_FM_PKT_UART_HDR_LEN (4) +#define BT_ACL_PKT_HDR_LEN (4) +#define BT_ACL_PKT_UART_HDR_LEN (5) + +/* FM Header */ +#define FM_CMD_PKT_HDR_LEN (3) //Opcode(2byte) + Param len(1 byte) +#define FM_EVT_PKT_HDR_LEN (2) //Opcode(1 byte) + Param len(1 byte) + +/* ANT Header */ +#define ANT_CMD_PKT_HDR_LEN (1) +#define ANT_DATA_PKT_HDR_LEN (1) +#define ANT_CMD_DATA_PKT_UART_HDR_LEN (2) + +#define BT_EVT_PKT_HDR_LEN_UART (BT_CMD_PKT_HDR_LEN+1) +#define BT_ACL_PKT_HDR_LEN_UART (BT_ACL_PKT_HDR_LEN+1) + +/* ANT data packet type */ +#define ANT_DATA_TYPE_BROADCAST (0x4E) +#define ANT_DATA_TYPE_ACKNOWLEDGED (0x4F) +#define ANT_DATA_TYPE_BURST (0x50) +#define ANT_DATA_TYPE_ADV_BURST (0x72) + +/*Packet Identifiers */ +#define BT_CMD_PKT_ID 0x01 +#define FM_CMD_PKT_ID 0x11 +#define BT_EVT_PKT_ID 0x04 +#define FM_EVT_PKT_ID 0x14 +#define ANT_CMD_PKT_ID 0x0C +#define ANT_EVT_PKT_ID 0x0C +#define ANT_DATA_PKT_ID 0x0E +#define BT_ACL_DATA_PKT_ID 0x02 + +#define SMD_BUF_SIZE (9000) +#define UART_BUF_SIZE (9000) + +#define PC_TO_SOC (1) +#define SOC_TO_PC (2) + +int get_acl_pkt_length(unsigned char, unsigned char); +unsigned short get_pkt_data_len(unsigned char type, unsigned char *buf); +int init_pc_interface(wdsdaemon *wds); +int init_soc_interface(wdsdaemon *wds); +int establish_server_socket(wdsdaemon *wds); diff --git a/qca/ftm/src/wds/wds_hci_pfal_linux.c b/qca/ftm/src/wds/wds_hci_pfal_linux.c new file mode 100644 index 000000000..05f47344a --- /dev/null +++ b/qca/ftm/src/wds/wds_hci_pfal_linux.c @@ -0,0 +1,720 @@ +/* + * Copyright (c) 2016 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Copyright (c) 2012 by Qualcomm Atheros, Inc.. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wds_hci_pfal.h" +#include +#include +#include +#include +#include "hidl_client.h" + +#ifdef ANDROID +#include "bt_vendor_lib.h" +#else +#ifdef BT_SOC_TYPE_ROME +#include "bt_vendor_lib.h" +#endif +#endif + +#define SOCKET_NAME "wdssock" + +typedef unsigned char uint8; +extern int process_packet_type(wdsdaemon *wds, unsigned char pkt_id, + int *dst_fd, int *len, int dir); + +#ifdef ANDROID +extern int soc_type; +#endif + +static int find_max(int *arr, int len) +{ + int max = arr[0]; + int i; + + for (i = 1; i < len; i++) { + if (arr[i] > max) + max = arr[i]; + } + + return max; +} + +unsigned short get_pkt_data_len(unsigned char type, + unsigned char *buf) +{ + unsigned short len = 0; + switch (type) { + case BT_EVT_PKT_ID: + /* Event packet: 1 byte length */ + len = buf[BT_EVT_PKT_HDR_LEN_UART - 1]; + break; + case BT_ACL_DATA_PKT_ID: + /* ACL packet: 2 byte length */ + len = + (((unsigned short) buf[BT_ACL_PKT_HDR_LEN_UART - 1] << 8) & + 0xFF00) | (((unsigned short) buf[BT_ACL_PKT_HDR_LEN_UART - 2]) + & 0x00FF); + break; + case BT_CMD_PKT_ID: + len = buf[BT_EVT_PKT_HDR_LEN_UART]; + break; + case FM_CMD_PKT_ID: + /* FM Cmd packet param len: 1 byte length */ + len = buf[FM_CMD_PKT_HDR_LEN]; + break; + case FM_EVT_PKT_ID: + /* FM Evt packet param len: 1 byte length */ + len = buf[FM_EVT_PKT_HDR_LEN]; + break; + } + return len; +} + +static int process_soc_data_to_pc(wdsdaemon *wds, unsigned char *buf_in, + int src_fd) +{ + int retval = STATUS_SUCCESS; + ssize_t n_bytes = 0, n_total = 0; + int len = 1, dst_fd = 0, i; + int state = RX_PKT_IND, offset = 0; + unsigned char pkt_ind_to_read = 1; + + + /* In case of Pronto, we have different channels for CMD and ACL, + * so we don't get packet indicator from SoC. + * Below condition will skip reading packet indicator byte in + * case of Pronto. + */ + if (wds->mode != MODE_BT_UART && wds->mode != MODE_ANT_UART && + wds->mode != MODE_FM_UART) { + pkt_ind_to_read = 0; + offset++; + } + + do { + while (len) { + if (pkt_ind_to_read == 0) + goto dont_read_pkt_ind; + + if ((n_bytes = read(src_fd, + (unsigned char *)(&buf_in[offset + n_total]), + len)) > 0) { + n_total += n_bytes; + len -= n_bytes; + if (len) + continue; +dont_read_pkt_ind: + switch(state) { + case RX_PKT_IND: + pkt_ind_to_read = 1; + state = process_packet_type(wds, buf_in[0], &dst_fd, &len, + SOC_TO_PC); + break; + case RX_BT_HDR: + len = get_pkt_data_len(buf_in[0], buf_in); + state = RX_BT_DATA; + break; + case RX_BT_DATA: + len = 0; + break; + case RX_ANT_HDR: + pkt_ind_to_read = 1; + len = buf_in[n_total]; + state = RX_ANT_DATA; + break; + case RX_ANT_DATA: + if (buf_in[2] == + ANT_DATA_TYPE_BROADCAST || + buf_in[2] == + ANT_DATA_TYPE_ACKNOWLEDGED || + buf_in[2] == ANT_DATA_TYPE_BURST || + buf_in[2] == ANT_DATA_TYPE_ADV_BURST) + buf_in[0] = ANT_DATA_PKT_ID; + else + buf_in[0] = ANT_EVT_PKT_ID; + + retval = STATUS_SUCCESS; + break; + case RX_FM_HDR: + len = get_pkt_data_len(buf_in[0], buf_in); + state = RX_FM_DATA; + break; + case RX_FM_DATA: + len = 0; + break; + default: + retval = STATUS_ERROR; + break; + } + } else { + ERROR("%s Failed To read from SoC fd = %d\n",__func__, src_fd); + break; + } + } + if (retval) + break; + n_total += offset; + len = 0; + + DEBUG("evt:\t"); + for (i = 0; i < n_total; i++) + DEBUG("0x%x\t", buf_in[i]); + DEBUG("\n"); + while (n_total) { + if((n_bytes = write(dst_fd, buf_in + len, n_total)) >= 0) { + len += n_bytes; + n_total -= n_bytes; + } + else { + if (wds->is_server_enabled) { + retval = STATUS_CLIENT_ERROR; + ERROR("%s: unable to write to client socket, fd = %d err = %s\n", __func__, dst_fd, strerror(errno)); + } + else { + retval = STATUS_ERROR; + ERROR("%s: unable to write to pc_if fd = %d err = %s\n", __func__, dst_fd, strerror(errno)); + } + break; + } + } + } while (0); + + return retval; +} + +static void *process_soc_data(void *arg) +{ + int retval = STATUS_ERROR; + fd_set readfds, saved_readfds; + wdsdaemon *wds = (wdsdaemon *) arg; + int max, src_fd = 0, dst_fd = 0; + size_t sz = 0; + unsigned char *buf_in = NULL; + int arr[5], num = 0; + + FD_ZERO(&readfds); + FD_ZERO(&saved_readfds); + + if (wds->mode == MODE_BT_UART || wds->mode == MODE_ANT_UART || + wds->mode == MODE_FM_UART) { + FD_SET(wds->soc_if.uart.uart_fd, &saved_readfds); + max = wds->soc_if.uart.uart_fd; + sz = UART_BUF_SIZE * sizeof(unsigned char); + } else { + if (wds->mode == MODE_BT_SMD || wds->mode == MODE_ALL_SMD) { + FD_SET((arr[num] = wds->soc_if.smd.bt_acl_fd), &saved_readfds);num++; + FD_SET((arr[num] = wds->soc_if.smd.bt_cmd_fd), &saved_readfds);num++; + } + if (wds->mode == MODE_ANT_SMD || wds->mode == MODE_ALL_SMD) { + FD_SET((arr[num] = wds->soc_if.smd.ant_cmd_fd), &saved_readfds);num++; + FD_SET((arr[num] = wds->soc_if.smd.ant_data_fd), &saved_readfds);num++; + } + + if (wds->mode == MODE_FM_SMD || wds->mode == MODE_ALL_SMD) + FD_SET((arr[num] = wds->soc_if.smd.fm_cmd_fd), &saved_readfds);num++; + + max = find_max(arr, num); + + sz = SMD_BUF_SIZE * sizeof(unsigned char); + } + + buf_in = (unsigned char *) calloc(sz, 1); + if (!buf_in) { + ERROR("Insufficient Memory"); + retval = STATUS_NO_MEMORY; + goto failed; + } + + do { + readfds = saved_readfds; + retval = select(max + 1, &readfds, NULL, NULL, NULL); + if (retval == -1) { + ERROR("select failed, Error: %s (%d)\n", strerror(errno), + errno); + break; + } + + switch (wds->mode) { + case MODE_BT_UART: + case MODE_FM_UART: + case MODE_ANT_UART: + src_fd = wds->soc_if.uart.uart_fd; + if (FD_ISSET(src_fd,&readfds)) + retval = process_soc_data_to_pc(wds, buf_in, src_fd); + break; + case MODE_ALL_SMD: + case MODE_BT_SMD: + src_fd = wds->soc_if.smd.bt_cmd_fd; + if (FD_ISSET(src_fd ,&readfds)) { + buf_in[0] = BT_EVT_PKT_ID; + retval = process_soc_data_to_pc(wds, buf_in,src_fd); + } + src_fd = wds->soc_if.smd.bt_acl_fd; + if (FD_ISSET(src_fd ,&readfds)) { + buf_in[0] = BT_ACL_DATA_PKT_ID; + retval = process_soc_data_to_pc(wds, buf_in, src_fd); + } + if (wds->mode == MODE_BT_SMD) + break; + case MODE_FM_SMD: + src_fd = wds->soc_if.smd.fm_cmd_fd; + if (FD_ISSET(src_fd ,&readfds)) { + buf_in[0] = FM_EVT_PKT_ID; + retval = process_soc_data_to_pc(wds, buf_in, src_fd); + } + if (wds->mode == MODE_FM_SMD) + break; + break; + case MODE_ANT_SMD: + src_fd = wds->soc_if.smd.ant_cmd_fd; + if (FD_ISSET(src_fd, &readfds)) { + buf_in[0] = ANT_EVT_PKT_ID; + retval = process_soc_data_to_pc(wds, buf_in, src_fd); + } + src_fd = wds->soc_if.smd.ant_data_fd; + if (FD_ISSET(src_fd ,&readfds)) { + buf_in[0] = ANT_DATA_PKT_ID; + retval = process_soc_data_to_pc(wds, buf_in, src_fd); + } + break; + } + + if (STATUS_SUCCESS != retval) { + if (retval == STATUS_CLIENT_ERROR) { + ERROR("Write to client failed\n"); + continue; + } + ERROR("Failed to process SOC data\n"); + break; + } + } while(1); + +failed: + ERROR("\nReader thread exited\n"); + if (buf_in) { + free(buf_in); + buf_in = NULL; + } + return 0; +} + +static int set_port_raw_mode(int fd) +{ + struct termios term; + int ret = STATUS_SUCCESS; + + if (tcgetattr(fd, &term) < 0) { + ERROR("Failed to get attributes"); + ERROR("Error: %s (%d)", strerror(errno), errno); + return STATUS_ERROR; + } + cfmakeraw(&term); + if (tcsetattr(fd, TCSANOW, &term) < 0) { + ERROR("Failed to set attributes"); + ERROR("Error: %s (%d)", strerror(errno), errno); + return STATUS_ERROR; + } + if (tcflush(fd, TCIFLUSH) < 0) { + ERROR("Failed to flush port"); + ERROR("Error: %s (%d)", strerror(errno), errno); + return STATUS_ERROR; + } + + return ret; +} + +/*=========================================================================== +FUNCTION port_init_libbt + +DESCRIPTION +Initilize port and open the file through libbt-vendor + +DEPENDENCIES +NIL + +RETURN VALUE +RETURN fd handle + +SIDE EFFECTS +None + +===========================================================================*/ +#ifndef BT_BLUEZ +static int port_init_libbt(uint8 option) +{ + int fd_array[CH_MAX]; + bt_vendor_callbacks_t cb; + uint8_t init_bd_addr[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; + bt_vendor_interface_t * p_btf = NULL; + bt_vendor_opcode_t opCmd1, opCmd2; + int iState; + + void* vendor_handle = dlopen("libbt-vendor.so", RTLD_NOW); + if(!vendor_handle){ + ERROR("Error open libbt-vendor \n"); + return -1; + } + p_btf = (bt_vendor_interface_t *)dlsym(vendor_handle, + "BLUETOOTH_VENDOR_LIB_INTERFACE"); + if(!p_btf){ + ERROR("Failed obtain the address of libbt-vendor \n"); + return -1; + } + if (p_btf->init(&cb, &init_bd_addr[0]) < 0){ + ERROR("bt vendor init failed \n"); + return -1; + } + + switch (option) { + case MODE_BT_UART: + opCmd1 = BT_VND_OP_POWER_CTRL; + opCmd2 = BT_VND_OP_USERIAL_OPEN; + break; + case MODE_FM_UART: + opCmd1 = FM_VND_OP_POWER_CTRL; + opCmd2 = BT_VND_OP_FM_USERIAL_OPEN; + break; + case MODE_ANT_UART: + opCmd1 = BT_VND_OP_POWER_CTRL; + opCmd2 = BT_VND_OP_USERIAL_OPEN; + break; + default: + printf("Invalid option\n"); + return -1; + } + + iState = BT_VND_PWR_ON; + + if (p_btf->op(opCmd1, &iState) < 0){ + ERROR("Power on failed \n"); + return -1; + } + + if (p_btf->op(opCmd2, (void*)fd_array) < 0){ + ERROR("op(VND_OP_USERIAL_OPEN) failed \n"); + return -1; + } + + return fd_array[0]; +} +#endif + +static int change_baud(int fd, speed_t baud) +{ + struct termios term; + int ret = STATUS_SUCCESS; /* assume success */ + + do { + if (tcgetattr(fd, &term) < 0) { + ERROR("Failed to get attributes"); + ret = STATUS_ERROR; + break; + } + cfsetospeed(&term, baud); + /* don't change speed until last write done */ + if (tcsetattr(fd, TCSADRAIN, &term) < 0) { + ERROR("Failed to set attribute"); + ERROR("Error: %s (%d)", strerror(errno), errno); + ret = STATUS_ERROR; + break; + } + } while(0); + return 0; +} + +int init_soc_interface(wdsdaemon *wds) +{ + int ret = STATUS_ERROR; + int fd = 0; + struct termios term; + + if (!wds) { + ret = STATUS_NULL_POINTER; + ERROR("Invalid input argument\n"); + return ret; + } + + switch (wds->mode) { + case MODE_FM_UART: + if(hidl_client_initialize(MODE_FM,&fd) == false) + { + ERROR("HIDL client initialization failed"); + exit(1); + } + wds->soc_if.uart.uart_fd = fd; + ret = STATUS_SUCCESS; + break; + case MODE_BT_UART: +#ifdef BT_BLUEZ + fd = open(wds->soc_if.uart.intf, + O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + break; + } + if (tcflush(fd, TCIOFLUSH) < 0) { + ERROR("Failed to flush port: %s\n", + wds->soc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + close(fd); + break; + } + if (tcgetattr(fd, &term) < 0) { + ERROR("Failed to get attributes for port: %s\n", + wds->soc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + close(fd); + break; + } + cfmakeraw(&term); + /* enable flow control */ + term.c_cflag |= (CRTSCTS | CLOCAL); + if (tcsetattr(fd, TCSANOW, &term) < 0) { + ERROR("Failed to set attributes for port: %s\n", + wds->soc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + close(fd); + break; + } + if (STATUS_SUCCESS != change_baud(fd, B3000000)) { //TODO:set baud rate + ERROR("Failed to change baud rate\n"); + close(fd); + break; + } +#else + if(hidl_client_initialize(MODE_BT,&fd) == false) + { + ERROR("HIDL client initialization failed"); + exit(1); + } +#endif + /* everything okay */ + wds->soc_if.uart.uart_fd = fd; + ret = STATUS_SUCCESS; + break; + case MODE_ANT_UART: +#ifndef BT_BLUEZ + if(hidl_client_initialize(MODE_ANT,&fd) == true){ + wds->soc_if.uart.uart_fd = fd; + } + else { + ERROR("HIDL client initialization failed, opening port with port_init_libbt\n"); + wds->soc_if.uart.uart_fd = port_init_libbt(wds->mode); + } + ret = STATUS_SUCCESS; +#endif + break; + case MODE_ALL_SMD: + case MODE_ANT_SMD: + /* ANT commdnas */ + fd = open(wds->soc_if.smd.ant_cmd, + O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.smd.ant_cmd); + ERROR("Error: %s (%d)\n", strerror(errno), + errno); + break; + } + set_port_raw_mode(fd); + wds->soc_if.smd.ant_cmd_fd = fd; + /* ANT data */ + fd = open(wds->soc_if.smd.ant_data, + O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.smd.ant_data); + ERROR("Error: %s (%d)", strerror(errno), + errno); + break; + } + set_port_raw_mode(fd); + wds->soc_if.smd.ant_data_fd = fd; + if (wds->mode == MODE_ANT_SMD) { + ret = STATUS_SUCCESS; + break; + } + /* fallthrough intentional for MODE_ALL_SMD */ + case MODE_BT_SMD: + /* BT commdnas */ + fd = open(wds->soc_if.smd.bt_cmd, + O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.smd.bt_cmd_fd); + ERROR("Error: %s (%d)\n", + strerror(errno), errno); + break; + } + set_port_raw_mode(fd); + wds->soc_if.smd.bt_cmd_fd = fd; + /* BT ACL */ + fd = open(wds->soc_if.smd.bt_acl, + O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.smd.bt_acl); + ERROR("Error: %s (%d)\n", + strerror(errno), errno); + break; + } + set_port_raw_mode(fd); + wds->soc_if.smd.bt_acl_fd = fd; + if (wds->mode == MODE_BT_SMD) { + ret = STATUS_SUCCESS; + break; + } + /* fallthrough intentional for MODE_ALL_SMD */ + case MODE_FM_SMD: + /* FM commdnas */ + fd = open(wds->soc_if.smd.fm_cmd, O_RDWR | O_NONBLOCK | O_NOCTTY); + if (-1 == fd) { + ERROR("Failed to open port: %s\n", + wds->soc_if.smd.fm_cmd_fd); + ERROR("Error: %s (%d)\n", + strerror(errno), errno); + break; + } + set_port_raw_mode(fd); + wds->soc_if.smd.fm_cmd_fd = fd; + ret = STATUS_SUCCESS; + break; + } + + if (ret == STATUS_SUCCESS) + if (pthread_create(&wds->soc_rthread, NULL, process_soc_data, + wds) != 0) { + ERROR("%s:Unable to create pthread err = %s\n", __func__, + strerror(errno)); + close(fd); + ret = STATUS_ERROR; + } + +failed: + return ret; +} + +int init_pc_interface(wdsdaemon *wds) +{ + int fd = 0; + int ret = STATUS_ERROR; + struct termios term; + + if (!wds) { + ret = STATUS_NULL_POINTER; + ERROR("Invalid input argument"); + return ret; + } + + do { + fd = open(wds->pc_if.uart.intf, O_RDWR); + if (-1 == fd) { + ERROR("Unable to open port: %s", wds->pc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + ret = STATUS_ERROR; + break; + } + /* set terminal properties */ + if (tcgetattr(fd, &term) < 0) { + ERROR("Failed to get attributes of port: %s", + wds->pc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + close(fd); + ret = STATUS_ERROR; + break; + } + cfmakeraw(&term); + term.c_lflag = term.c_lflag & ((tcflag_t)(~ECHO)); + /* TODO: Make baud rate command line argument */ + cfsetospeed(&term, B115200); + cfsetispeed(&term, B115200); + if (tcsetattr(fd, TCSANOW, &term) < 0) { + ERROR("Failed to set attributes of port: %s", + wds->pc_if.uart.intf); + ERROR("Error: %s (%d)", strerror(errno), errno); + close(fd); + ret = STATUS_ERROR; + break; + } + tcflush(fd, TCIOFLUSH); + + /* everything okay, set success */ + wds->pc_if.uart.uart_fd = fd; + ret = STATUS_SUCCESS; + } while(0); + + return ret; +} + +int establish_server_socket(wdsdaemon *wds) +{ + int fd = -1; + struct sockaddr_un client_address; + socklen_t clen; + int sock_id, ret = STATUS_ERROR; + DEBUG("%s(%s) Entry \n", __func__, SOCKET_NAME); + + if (!wds) { + ret = STATUS_NULL_POINTER; + ERROR("Invalid input argument\n"); + return ret; + } + + sock_id = socket(AF_LOCAL, SOCK_STREAM, 0); + if (sock_id < 0) { + ERROR("%s: server Socket creation failure\n", __func__); + return ret; + } + + DEBUG("convert name to android abstract name:%s %d\n", SOCKET_NAME, sock_id); + if (socket_local_server_bind(sock_id, + SOCKET_NAME, ANDROID_SOCKET_NAMESPACE_ABSTRACT) >= 0) { + if (listen(sock_id, 5) == 0) { + DEBUG("listen to local socket:%s, fd:%d\n", SOCKET_NAME, sock_id); + } else { + ERROR("listen to local socket:failed\n"); + close(sock_id); + return ret; + } + } else { + close(sock_id); + ERROR("%s: server bind failed for socket : %s\n", __func__, SOCKET_NAME); + return ret; + } + + clen = sizeof(client_address); + DEBUG("%s: before accept_server_socket\n", SOCKET_NAME); + fd = accept(sock_id, (struct sockaddr *)&client_address, &clen); + if (fd > 0) { + DEBUG("%s accepted fd:%d for server fd:%d\n", SOCKET_NAME, fd, sock_id); + close(sock_id); + wds->server_socket_fd = fd; + return STATUS_SUCCESS; + } else { + ERROR("Accept failed fd:%d sock d:%d error %s\n", fd, sock_id, strerror(errno)); + close(sock_id); + return ret; + } +} diff --git a/qca/ftm/src/wds/wds_main.c b/qca/ftm/src/wds/wds_main.c new file mode 100644 index 000000000..9c1c8f768 --- /dev/null +++ b/qca/ftm/src/wds/wds_main.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016 Qualcomm Technologies, Inc. + * All Rights Reserved. + * Confidential and Proprietary - Qualcomm Technologies, Inc. + * + * Copyright (c) 2012 by Qualcomm Atheros, Inc.. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + */ + +/* +* Description: +* Added wdsdaemon to enable testing of Host Controller Interface (HCI) +* communication with stack layers bypassed. +* 1. Acts as a communication bridge between PC to DUT over UART (/dev/ttyHSL0) +* and also UART transport between DUT and BTSOC (/dev/ttyHS0). +* 2. Used to test exchange of BT-FM HCI commands, events and ACL data packets +* between host and controller. +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wds_hci_pfal.h" +#include "hidl_client.h" + +#ifdef ANDROID +#include +#endif + +/*=========================================================================== +FUNCTION get_pkt_type + +DESCRIPTION + Routine to get the packet type from the data bytes received + +DEPENDENCIES + NIL + +RETURN VALUE + Packet type for the data bytes received + +SIDE EFFECTS + None + +===========================================================================*/ +static int get_packet_type(unsigned char id) +{ + int type; + + switch (id) { + case BT_CMD_PKT_ID: + type = PACKET_TYPE_BT_CMD; + break; + case FM_CMD_PKT_ID: + type = PACKET_TYPE_FM_CMD; + break; + case BT_ACL_DATA_PKT_ID: + type = PACKET_TYPE_BT_ACL; + break; + case ANT_CMD_PKT_ID: + type = PACKET_TYPE_ANT_CMD; + break; + case ANT_DATA_PKT_ID: + type = PACKET_TYPE_ANT_DATA; + break; + default: + type = PACKET_TYPE_INVALID; + } + + return type; +} + +#ifdef ANDROID + +int soc_type; + +/** Get Bluetooth SoC type from system setting */ +static int get_bt_soc_type() +{ + int ret = 0; + char bt_soc_type[PROPERTY_VALUE_MAX]; + + DEBUG("bt-hci: get_bt_soc_type\n"); + + ret = property_get("qcom.bluetooth.soc", bt_soc_type, NULL); + if (ret != 0) { + DEBUG("qcom.bluetooth.soc set to %s\n", bt_soc_type); + if (!strncasecmp(bt_soc_type, "rome", sizeof("rome"))) { + return BT_SOC_ROME; + } + else if (!strncasecmp(bt_soc_type, "cherokee", sizeof("cherokee"))) { + return BT_SOC_CHEROKEE; + } + else if (!strncasecmp(bt_soc_type, "ath3k", sizeof("ath3k"))) { + return BT_SOC_AR3K; + } + else if (!strncasecmp(bt_soc_type, "napier", sizeof("napier"))) { + return BT_SOC_NAPIER; + } + else { + DEBUG("qcom.bluetooth.soc not set, so using default.\n"); + return BT_SOC_DEFAULT; + } + } + else { + DEBUG("%s: Failed to get soc type\n", __FUNCTION__); + ret = BT_SOC_DEFAULT; + } + + return ret; +} +#endif + +static int parse_options(wdsdaemon *wds, int argc, char *argv[]) +{ + int ret = STATUS_SUCCESS; + int opt; + + if (argc > 2) { + ERROR("Invalid number of arguments\n"); + ret = STATUS_INVALID_LENGTH; + ERROR("Usage %s [-abfunht]", argv[0]); + return ret; + } + + if (argc == 1) { + wds->mode = MODE_ALL_SMD; + return ret; + } + + while ((opt = getopt(argc, argv, "abfunhstm")) != -1) { + switch (opt) { + case 'a': + DEBUG("Opening ANT SMD channels\n"); + wds->mode = MODE_ANT_SMD; + break; + case 'b': + DEBUG("Opening BT SMD channels\n"); + wds->mode = MODE_BT_SMD; + break; + case 'f': + DEBUG("Opening FM SMD channels\n"); + wds->mode = MODE_FM_SMD; + break; + case 't': + ERROR("Setting mask for pc initialization\n"); + wds->pcinit_mask = true; + break; + case 's': + ERROR("Opening WDS server socket\n"); + wds->is_server_enabled = true; + wds->pcinit_mask = true; + break; +#ifdef ANDROID + if (soc_type == BT_SOC_ROME || soc_type == BT_SOC_CHEROKEE) { + case 'u': + DEBUG("Opening UART BT Channel\n"); + wds->mode = MODE_BT_UART; + break; + } + if (soc_type == BT_SOC_CHEROKEE) { + case 'm': + DEBUG("Opening UART FM Channel\n"); + wds->mode = MODE_FM_UART; + break; + } +#else +#ifdef BT_SOC_TYPE_ROME + case 'u': + DEBUG("Opening UART BT Channel\n"); + wds->mode = MODE_BT_UART; + break; +#endif +#endif +#ifdef CONFIG_ANT + case 'n': + ERROR("Opening ANT UART channels\n"); + wds->mode = MODE_ANT_UART; + break; +#endif + case 'h': + DEBUG("By Default, it will open all SMD channels\n"); + DEBUG("Use -a for opening only ANT Channels\n"); + DEBUG("Use -b for opening only BT Channels\n"); + DEBUG("Use -f for opening only FM Channels\n"); + +#ifdef ANDROID + if (soc_type == BT_SOC_ROME || soc_type == BT_SOC_CHEROKEE) { + DEBUG("Use -u for opening only UART Channel for BT (ROME)\n"); + } + if (soc_type == BT_SOC_CHEROKEE) { + DEBUG("Use -m for opening only UART Channel for FM\n"); + } +#else +#ifdef BT_SOC_TYPE_ROME + DEBUG("Use -u for opening only UART Channel for BT (ROME)\n"); +#endif +#endif + +#ifdef CONFIG_ANT + DEBUG("Use -n for opening ANT UART channels only\n"); +#endif + DEBUG("Use -t for masking pc initialization\n"); + DEBUG("Use -s for setting communication via server socket\n"); + DEBUG("Use -h to print help\n"); + ret = STATUS_ERROR; + break; + default: + DEBUG("Usage %s [-abfunhmst]\n", argv[0]); + ret = STATUS_ERROR; + break; + } + } + + return ret; +} + +static void wdsdaemon_init(wdsdaemon *wds) +{ + /* PC-DUT interface */ +#ifdef BT_BLUEZ + wds->pc_if.uart.intf = (unsigned char *)BT_HSLITE_UART_DEVICE; +#else + wds->pc_if.uart.intf = (unsigned char *)BT_HS_NMEA_DEVICE; +#endif + + /* DUT-BTSOC interface */ + switch (wds->mode) { + case MODE_ALL_SMD: + wds->soc_if.smd.fm_cmd = (unsigned char *)APPS_RIVA_FM_CMD_CH; + wds->soc_if.smd.bt_acl = (unsigned char*)APPS_RIVA_BT_ACL_CH; + wds->soc_if.smd.bt_cmd = (unsigned char *)APPS_RIVA_BT_CMD_CH; + wds->soc_if.smd.ant_cmd = (unsigned char *)APPS_RIVA_ANT_CMD; + wds->soc_if.smd.ant_data = (unsigned char *)APPS_RIVA_ANT_DATA; + break; + case MODE_ANT_SMD: + wds->soc_if.smd.ant_cmd = (unsigned char *)APPS_RIVA_ANT_CMD; + wds->soc_if.smd.ant_data = (unsigned char *)APPS_RIVA_ANT_DATA; + break; + case MODE_BT_SMD: + wds->soc_if.smd.bt_acl = (unsigned char *)APPS_RIVA_BT_ACL_CH; + wds->soc_if.smd.bt_cmd = (unsigned char *)APPS_RIVA_BT_CMD_CH; + break; + case MODE_FM_SMD: + wds->soc_if.smd.fm_cmd = (unsigned char *)APPS_RIVA_FM_CMD_CH; + break; + case MODE_BT_UART: + case MODE_ANT_UART: + wds->soc_if.uart.intf = (unsigned char *)BT_HS_UART_DEVICE; + break; + } +} + +int process_packet_type(wdsdaemon *wds, unsigned char pkt_id, + int *dst_fd, int *len, int dir) +{ + int state; + + switch(pkt_id) { + case BT_CMD_PKT_ID: + *len = BT_EVT_PKT_HDR_LEN_UART; + case BT_EVT_PKT_ID: + case BT_ACL_DATA_PKT_ID: + state = RX_BT_HDR; + if (wds->mode == MODE_BT_UART) + *dst_fd = wds->soc_if.uart.uart_fd; + else + if (pkt_id == BT_CMD_PKT_ID) + *dst_fd = wds->soc_if.smd.bt_cmd_fd; + else + *dst_fd = wds->soc_if.smd.bt_acl_fd; + if (pkt_id == BT_ACL_DATA_PKT_ID) + *len = BT_ACL_PKT_HDR_LEN; + else if (pkt_id == BT_EVT_PKT_ID) + *len = BT_EVT_PKT_HDR_LEN; + break; + case FM_CMD_PKT_ID: + if (wds-> mode == MODE_FM_UART) + *dst_fd = wds->soc_if.uart.uart_fd; + else + *dst_fd = wds->soc_if.smd.fm_cmd_fd; + case FM_EVT_PKT_ID: + state = RX_FM_HDR; + if (pkt_id == FM_CMD_PKT_ID) + *len = FM_CMD_PKT_HDR_LEN; + else if (pkt_id == FM_EVT_PKT_ID) + *len = FM_EVT_PKT_HDR_LEN; + break; + case ANT_CMD_PKT_ID: + case ANT_DATA_PKT_ID: + state = RX_ANT_HDR; + if (wds->mode == MODE_ANT_UART) + *dst_fd = wds->soc_if.uart.uart_fd; + else + if (pkt_id == ANT_CMD_PKT_ID) + *dst_fd = wds->soc_if.smd.ant_cmd_fd; + else + *dst_fd = wds->soc_if.smd.ant_data_fd; + break; + default: + state = RX_ERROR; + break; + } + + if (dir == SOC_TO_PC) { + if (wds->is_server_enabled) + *dst_fd = wds->server_socket_fd; + else + *dst_fd = wds->pc_if.uart.uart_fd; + } + + return state; +} + +static int process_pc_data_to_soc(wdsdaemon *wds, unsigned char *buf, int src_fd) +{ + int retval = STATUS_SUCCESS; + int len = 1, n_bytes = 0, n_total = 0; + int pkt_id = 0, dst_fd = 0; + int state = RX_PKT_IND, i; + + do { + if ((n_bytes = read(src_fd, (unsigned char *)&buf[n_total], len)) > 0) { + n_total += n_bytes; + len -= n_bytes; + if (len) + continue; + + switch(state) { + case RX_PKT_IND: + pkt_id = buf[0]; + state = process_packet_type(wds, pkt_id, &dst_fd, &len, + PC_TO_SOC); + break; + case RX_BT_HDR: + len = get_pkt_data_len(pkt_id, buf); + state = RX_BT_DATA; + break; + case RX_ANT_HDR: + len = buf[0]; + state = RX_ANT_DATA; + break; + case RX_FM_HDR: + len = get_pkt_data_len(pkt_id, buf); + state = RX_FM_DATA; + break; + case RX_BT_DATA: + case RX_ANT_DATA: + case RX_FM_DATA: + len = 0; + break; + default: + retval = STATUS_ERROR; + break; + } + } else { + ERROR("%s: error while reading from fd = %d err = %s\n", + __func__, src_fd, strerror(errno)); + if (n_bytes < 0) + ERROR("%s:read returns err: %d\n", __func__,n_bytes); + if (n_bytes == 0) + ERROR("%s: This indicates the close of other end\n", __func__); + retval = STATUS_ERROR; + break; + } + } while (len); + + if(retval) + goto fail; + + /* In case of Pronto, for BT, we have different channels for CMD and ACL, + * so we don't send packet indicator to SoC. + * Below condition will skip the packet indicator byte to Soc in\ + * case of Pronto. + */ + if (wds->mode != MODE_BT_UART && wds->mode != MODE_ANT_UART && + wds->mode != MODE_FM_UART) { + n_total -= 1; + len = 1; + } + while(n_total) { + if((n_bytes = write(dst_fd, buf + len, n_total)) > 0) { + len += n_bytes; + n_total -= n_bytes; + } else + ERROR("%s :Error while writeto fd = %d err = %s\n", + __func__, dst_fd, strerror(errno)); + break; + } + + DEBUG("cmd:\t"); + for (i = 0; i < len; i++) + DEBUG("0x%x\t", buf[i]); + DEBUG("\n"); + + if (n_total) + retval = STATUS_ERROR; + +fail: + return retval; +} + +static void thread_exit_handler(int signo){ + DEBUG("%s: %d",__func__,signo); +} + +int server_create(wdsdaemon *wds,int *src_fd) { + int retval = establish_server_socket(wds); + if (STATUS_SUCCESS == retval) + *src_fd = wds->server_socket_fd; + else + ERROR("Failed to init server socket\n"); + + return retval; +} + +int main(int argc, char *argv[]) +{ + int retval = STATUS_ERROR, src_fd = 0; + fd_set readfds; + wdsdaemon wds; + unsigned char *buf = NULL; + size_t size = UART_BUF_SIZE; + struct sigaction action; + sigset_t sigmask, emptymask; + + sigemptyset(&sigmask); + sigaddset(&sigmask, SIGINT); + sigaddset(&sigmask, SIGPIPE); + if (sigprocmask(SIG_BLOCK, &sigmask, NULL) == -1) { + ERROR("failed to sigprocmask"); + } + memset(&action, 0, sizeof(struct sigaction)); + sigemptyset(&action.sa_mask); + action.sa_flags = 0; + action.sa_handler = thread_exit_handler; + + sigemptyset(&emptymask); + + if (sigaction(SIGINT, &action, NULL) < 0) { + ERROR("%s:sigaction failed\n", __func__); + } + + memset(&wds, 0, sizeof(wdsdaemon)); + +#ifdef ANDROID + soc_type = get_bt_soc_type(); +#endif + + /* parse options */ + retval = parse_options(&wds, argc, argv); + if (STATUS_SUCCESS != retval) { + goto fail; + } + + wdsdaemon_init(&wds); + + if(!(wds.pcinit_mask)) + { + retval = init_pc_interface(&wds); + if (STATUS_SUCCESS != retval) { + ERROR("Failed to init DUT-PC interface\n"); + goto fail; + } + src_fd = wds.pc_if.uart.uart_fd; + } + + retval = init_soc_interface(&wds); + if (STATUS_SUCCESS != retval) { + ERROR("Failed to init DUT-BTSOC interface\n"); + goto fail; + } +#ifdef BT_BLUEZ + fflush(stdout); + fflush(stderr); +#endif + + buf = (unsigned char *)calloc(size, 1); + if (!buf) { + ERROR("%s:Unable to allocate memory\n", __func__); + goto fail; + } + + if( wds.is_server_enabled && ( server_create(&wds, &src_fd)!= STATUS_SUCCESS )) + goto fail; + + do { + FD_ZERO(&readfds); + FD_SET(src_fd, &readfds); + + DEBUG("Waiting for data:\n"); + if ((retval = select(src_fd + 1, &readfds, NULL, NULL, NULL)) == -1) { + ERROR("%s:select failed\n", __func__); + if (wds.is_server_enabled) + { + ERROR("%s:closing the server socket and reopening\n", __func__); + close(src_fd); + if(server_create(&wds, &src_fd)== STATUS_SUCCESS) + continue; + } + break; + } + + if (FD_ISSET(src_fd, &readfds)) { + retval = process_pc_data_to_soc(&wds, buf, src_fd); + } else + ERROR("%s:src_fd port not set\n",__func__); + if (retval != STATUS_SUCCESS) { + ERROR("%s: Error while processing Data to SoC err = %d\n", __func__, retval); + if (wds.is_server_enabled) + { + ERROR("%s:closing the server socket and reopening\n", __func__); + close(src_fd); + if(server_create(&wds, &src_fd)== STATUS_SUCCESS) + continue; + } + break; + } + }while(1); + +fail: + if (buf) + free(buf); + shutdown(src_fd, SHUT_RDWR); + switch (wds.mode) { + case MODE_BT_UART: + case MODE_FM_UART: + case MODE_ANT_UART: + shutdown(wds.soc_if.uart.uart_fd, SHUT_RDWR); + break; + case MODE_ALL_SMD: + case MODE_BT_SMD: + shutdown(wds.soc_if.smd.bt_cmd_fd, SHUT_RDWR); + shutdown(wds.soc_if.smd.bt_acl_fd, SHUT_RDWR); + if(wds.mode == MODE_BT_SMD) + break; + case MODE_FM_SMD: + shutdown(wds.soc_if.smd.fm_cmd_fd, SHUT_RDWR); + if (wds.mode == MODE_FM_SMD) + break; + case MODE_ANT_SMD: + shutdown(wds.soc_if.smd.ant_cmd_fd, SHUT_RDWR); + shutdown(wds.soc_if.smd.ant_data_fd, SHUT_RDWR); + break; + } + pthread_join(wds.soc_rthread, NULL); + + hidl_client_close(); + return retval; +} diff --git a/qca/hostapd/Config.in b/qca/hostapd/Config.in new file mode 100644 index 000000000..5c00f3e24 --- /dev/null +++ b/qca/hostapd/Config.in @@ -0,0 +1,89 @@ +# wpa_supplicant config +config WPA_RFKILL_SUPPORT + bool "Add rfkill support" + depends on PACKAGE_wpa-supplicant || \ + PACKAGE_wpa-supplicant-openssl || \ + PACKAGE_wpa-supplicant-wolfssl || \ + PACKAGE_wpa-supplicant-mesh-openssl || \ + PACKAGE_wpa-supplicant-mesh-wolfssl || \ + PACKAGE_wpa-supplicant-basic || \ + PACKAGE_wpa-supplicant-mini || \ + PACKAGE_wpa-supplicant-p2p || \ + PACKAGE_wpad || \ + PACKAGE_wpad-openssl || \ + PACKAGE_wpad-wolfssl || \ + PACKAGE_wpad-basic || \ + PACKAGE_wpad-basic-openssl || \ + PACKAGE_wpad-basic-wolfssl || \ + PACKAGE_wpad-mini || \ + PACKAGE_wpad-mesh-openssl || \ + PACKAGE_wpad-mesh-wolfssl + default n + +config WPA_MSG_MIN_PRIORITY + int "Minimum debug message priority" + depends on PACKAGE_wpa-supplicant || \ + PACKAGE_wpa-supplicant-openssl || \ + PACKAGE_wpa-supplicant-wolfssl || \ + PACKAGE_wpa-supplicant-mesh-openssl || \ + PACKAGE_wpa-supplicant-mesh-wolfssl || \ + PACKAGE_wpa-supplicant-basic || \ + PACKAGE_wpa-supplicant-mini || \ + PACKAGE_wpa-supplicant-p2p || \ + PACKAGE_wpad || \ + PACKAGE_wpad-openssl || \ + PACKAGE_wpad-wolfssl || \ + PACKAGE_wpad-basic || \ + PACKAGE_wpad-basic-openssl || \ + PACKAGE_wpad-basic-wolfssl || \ + PACKAGE_wpad-mini || \ + PACKAGE_wpad-mesh-openssl || \ + PACKAGE_wpad-mesh-wolfssl + default 3 + help + Useful values are: + 0 = all messages + 1 = raw message dumps + 2 = most debugging messages + 3 = info messages + 4 = warnings + 5 = errors + +config WPA_WOLFSSL + bool + default PACKAGE_wpa-supplicant-wolfssl ||\ + PACKAGE_wpad-wolfssl ||\ + PACKAGE_wpad-basic-wolfssl || \ + PACKAGE_wpad-mesh-wolfssl ||\ + PACKAGE_eapol-test-wolfssl + select WOLFSSL_HAS_AES_CCM + select WOLFSSL_HAS_ARC4 + select WOLFSSL_HAS_DH + select WOLFSSL_HAS_OCSP + select WOLFSSL_HAS_SESSION_TICKET + select WOLFSSL_HAS_WPAS + +config DRIVER_WEXT_SUPPORT + bool + default n + +config DRIVER_11N_SUPPORT + bool + default n + +config DRIVER_11AC_SUPPORT + bool + default n + +config DRIVER_11AX_SUPPORT + bool + default n + +config WPA_ENABLE_WEP + bool "Enable support for unsecure and obsolete WEP" + help + Wired equivalent privacy (WEP) is an obsolete cryptographic data + confidentiality algorithm that is not considered secure. It should not be used + for anything anymore. The functionality needed to use WEP is available in the + current hostapd release under this optional build parameter and completely + removed in a future release. diff --git a/qca/hostapd/Makefile b/qca/hostapd/Makefile new file mode 100644 index 000000000..24638ed38 --- /dev/null +++ b/qca/hostapd/Makefile @@ -0,0 +1,710 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2006-2021 OpenWrt.org + +include $(TOPDIR)/rules.mk + +PKG_NAME:=hostapd +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=http://w1.fi/hostap.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-02-20 +PKG_SOURCE_VERSION:=59e9794c7d7e +PKG_MIRROR_HASH:=22ef855a2731aa5889e19d1e61f0128ba5a092a94c15de5cadad3baf42048f3d + +PKG_MAINTAINER:=Felix Fietkau +PKG_LICENSE:=BSD-3-Clause +PKG_CPE_ID:=cpe:/a:w1.fi:hostapd + +PKG_BUILD_PARALLEL:=1 +PKG_ASLR_PIE_REGULAR:=1 + +PKG_CONFIG_DEPENDS:= \ + CONFIG_PACKAGE_kmod-ath9k \ + CONFIG_PACKAGE_kmod-cfg80211 \ + CONFIG_PACKAGE_hostapd \ + CONFIG_PACKAGE_hostapd-basic \ + CONFIG_PACKAGE_hostapd-mini \ + CONFIG_WPA_RFKILL_SUPPORT \ + CONFIG_DRIVER_WEXT_SUPPORT \ + CONFIG_DRIVER_11N_SUPPORT \ + CONFIG_DRIVER_11AC_SUPPORT \ + CONFIG_DRIVER_11AX_SUPPORT \ + CONFIG_WPA_ENABLE_WEP + +EAPOL_TEST_PROVIDERS:=eapol-test eapol-test-openssl eapol-test-wolfssl + +SUPPLICANT_PROVIDERS:= +HOSTAPD_PROVIDERS:= + +LOCAL_TYPE=$(strip \ + $(if $(findstring wpad,$(BUILD_VARIANT)),wpad, \ + $(if $(findstring supplicant,$(BUILD_VARIANT)),supplicant, \ + hostapd \ + ))) + +LOCAL_AND_LIB_VARIANT=$(patsubst hostapd-%,%,\ + $(patsubst wpad-%,%,\ + $(patsubst supplicant-%,%,\ + $(BUILD_VARIANT)\ + ))) + +LOCAL_VARIANT=$(patsubst %-internal,%,\ + $(patsubst %-openssl,%,\ + $(patsubst %-wolfssl,%,\ + $(LOCAL_AND_LIB_VARIANT)\ + ))) + +SSL_VARIANT=$(strip \ + $(if $(findstring openssl,$(LOCAL_AND_LIB_VARIANT)),openssl,\ + $(if $(findstring wolfssl,$(LOCAL_AND_LIB_VARIANT)),wolfssl,\ + internal\ + ))) + +CONFIG_VARIANT:=$(LOCAL_VARIANT) +ifeq ($(LOCAL_VARIANT),mesh) + CONFIG_VARIANT:=full +endif + +include $(INCLUDE_DIR)/package.mk + +STAMP_CONFIGURED:=$(STAMP_CONFIGURED)_$(CONFIG_WPA_MSG_MIN_PRIORITY) + + +ifneq ($(CONFIG_DRIVER_11N_SUPPORT),) + HOSTAPD_IEEE80211N:=y +endif + +ifneq ($(CONFIG_DRIVER_11AC_SUPPORT),) + HOSTAPD_IEEE80211AC:=y +endif + +ifneq ($(CONFIG_DRIVER_11AX_SUPPORT),) + HOSTAPD_IEEE80211AX:=y +endif + +DRIVER_MAKEOPTS= \ + CONFIG_ACS=$(CONFIG_PACKAGE_kmod-cfg80211) \ + CONFIG_DRIVER_NL80211=$(CONFIG_PACKAGE_kmod-cfg80211) \ + CONFIG_IEEE80211N=$(HOSTAPD_IEEE80211N) \ + CONFIG_IEEE80211AC=$(HOSTAPD_IEEE80211AC) \ + CONFIG_IEEE80211AX=$(HOSTAPD_IEEE80211AX) \ + CONFIG_DRIVER_WEXT=$(CONFIG_DRIVER_WEXT_SUPPORT) \ + +ifeq ($(SSL_VARIANT),openssl) + DRIVER_MAKEOPTS += CONFIG_TLS=openssl CONFIG_SAE=y + TARGET_LDFLAGS += -lcrypto -lssl + + ifeq ($(LOCAL_VARIANT),basic) + DRIVER_MAKEOPTS += CONFIG_OWE=y + endif + ifeq ($(LOCAL_VARIANT),mesh) + DRIVER_MAKEOPTS += CONFIG_AP=y CONFIG_MESH=y + endif + ifeq ($(LOCAL_VARIANT),full) + DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y + endif +endif + +ifeq ($(SSL_VARIANT),wolfssl) + DRIVER_MAKEOPTS += CONFIG_TLS=wolfssl CONFIG_SAE=y + TARGET_LDFLAGS += -lwolfssl + + ifeq ($(LOCAL_VARIANT),basic) + DRIVER_MAKEOPTS += CONFIG_OWE=y + endif + ifeq ($(LOCAL_VARIANT),mesh) + DRIVER_MAKEOPTS += CONFIG_AP=y CONFIG_MESH=y CONFIG_WPS_NFC=1 + endif + ifeq ($(LOCAL_VARIANT),full) + DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y CONFIG_WPS_NFC=1 + endif +endif + +ifneq ($(LOCAL_TYPE),hostapd) + ifdef CONFIG_WPA_RFKILL_SUPPORT + DRIVER_MAKEOPTS += NEED_RFKILL=y + endif +endif + +ifdef CONFIG_USE_GLIBC + TARGET_LDFLAGS += -lrt + TARGET_LDFLAGS_C += -lrt +endif + +DRV_DEPENDS:=+PACKAGE_kmod-cfg80211:libnl-tiny + + +define Package/hostapd/Default + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD + TITLE:=IEEE 802.1x Authenticator + URL:=http://hostap.epitest.fi/ + DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus + USERID:=network=101:network=101 + PROVIDES:=hostapd + CONFLICTS:=$(HOSTAPD_PROVIDERS) + HOSTAPD_PROVIDERS+=$(1) +endef + +define Package/hostapd +$(call Package/hostapd/Default,$(1)) + TITLE+= (built-in full) + VARIANT:=full-internal +endef + +define Package/hostapd/description + This package contains a full featured IEEE 802.1x/WPA/EAP/RADIUS + Authenticator. +endef + +define Package/hostapd-openssl +$(call Package/hostapd/Default,$(1)) + TITLE+= (OpenSSL full) + VARIANT:=full-openssl + DEPENDS+=+libopenssl +endef + +Package/hostapd-openssl/description = $(Package/hostapd/description) + +define Package/hostapd-wolfssl +$(call Package/hostapd/Default,$(1)) + TITLE+= (wolfSSL full) + VARIANT:=full-wolfssl + DEPENDS+=+libwolfssl +endef + +Package/hostapd-wolfssl/description = $(Package/hostapd/description) + +define Package/hostapd-basic +$(call Package/hostapd/Default,$(1)) + TITLE+= (WPA-PSK, 11r, 11w) + VARIANT:=basic +endef + +define Package/hostapd-basic/description + This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support. +endef + +define Package/hostapd-basic-openssl +$(call Package/hostapd/Default,$(1)) + TITLE+= (WPA-PSK, 11r and 11w) + VARIANT:=basic-openssl + DEPENDS+=+libopenssl +endef + +define Package/hostapd-basic-openssl/description + This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support. +endef + +define Package/hostapd-basic-wolfssl +$(call Package/hostapd/Default,$(1)) + TITLE+= (WPA-PSK, 11r and 11w) + VARIANT:=basic-wolfssl + DEPENDS+=+libwolfssl +endef + +define Package/hostapd-basic-wolfssl/description + This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support. +endef + +define Package/hostapd-mini +$(call Package/hostapd/Default,$(1)) + TITLE+= (WPA-PSK only) + VARIANT:=mini +endef + +define Package/hostapd-mini/description + This package contains a minimal IEEE 802.1x/WPA Authenticator (WPA-PSK only). +endef + + +define Package/wpad/Default + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD + TITLE:=IEEE 802.1x Auth/Supplicant + DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus + USERID:=network=101:network=101 + URL:=http://hostap.epitest.fi/ + PROVIDES:=hostapd wpa-supplicant + CONFLICTS:=$(HOSTAPD_PROVIDERS) $(SUPPLICANT_PROVIDERS) + HOSTAPD_PROVIDERS+=$(1) + SUPPLICANT_PROVIDERS+=$(1) +endef + +define Package/wpad +$(call Package/wpad/Default,$(1)) + TITLE+= (built-in full) + VARIANT:=wpad-full-internal +endef + +define Package/wpad/description + This package contains a full featured IEEE 802.1x/WPA/EAP/RADIUS + Authenticator and Supplicant +endef + +define Package/wpad-openssl +$(call Package/wpad/Default,$(1)) + TITLE+= (OpenSSL full) + VARIANT:=wpad-full-openssl + DEPENDS+=+libopenssl +endef + +Package/wpad-openssl/description = $(Package/wpad/description) + +define Package/wpad-wolfssl +$(call Package/wpad/Default,$(1)) + TITLE+= (wolfSSL full) + VARIANT:=wpad-full-wolfssl + DEPENDS+=+libwolfssl +endef + +Package/wpad-wolfssl/description = $(Package/wpad/description) + +define Package/wpad-basic +$(call Package/wpad/Default,$(1)) + TITLE+= (WPA-PSK, 11r, 11w) + VARIANT:=wpad-basic +endef + +define Package/wpad-basic/description + This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, 802.11r and 802.11w support. +endef + +define Package/wpad-basic-openssl +$(call Package/wpad/Default,$(1)) + TITLE+= (OpenSSL, 11r, 11w) + VARIANT:=wpad-basic-openssl + DEPENDS+=+libopenssl +endef + +define Package/wpad-basic-openssl/description + This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, SAE (WPA3-Personal), 802.11r and 802.11w support. +endef + +define Package/wpad-basic-wolfssl +$(call Package/wpad/Default,$(1)) + TITLE+= (wolfSSL, 11r, 11w) + VARIANT:=wpad-basic-wolfssl + DEPENDS+=+libwolfssl +endef + +define Package/wpad-basic-wolfssl/description + This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, SAE (WPA3-Personal), 802.11r and 802.11w support. +endef + +define Package/wpad-mini +$(call Package/wpad/Default,$(1)) + TITLE+= (WPA-PSK only) + VARIANT:=wpad-mini +endef + +define Package/wpad-mini/description + This package contains a minimal IEEE 802.1x/WPA Authenticator and Supplicant (WPA-PSK only). +endef + +define Package/wpad-mesh +$(call Package/wpad/Default,$(1)) + DEPENDS+=@PACKAGE_kmod-cfg80211 @(!TARGET_uml||BROKEN) + PROVIDES+=wpa-supplicant-mesh wpad-mesh +endef + +define Package/wpad-mesh/description + This package contains a minimal IEEE 802.1x/WPA Authenticator and Supplicant (with 802.11s mesh and SAE support). +endef + +define Package/wpad-mesh-openssl +$(call Package/wpad-mesh,$(1)) + TITLE+= (OpenSSL, 11s, SAE) + DEPENDS+=+libopenssl + VARIANT:=wpad-mesh-openssl +endef + +Package/wpad-mesh-openssl/description = $(Package/wpad-mesh/description) + +define Package/wpad-mesh-wolfssl +$(call Package/wpad-mesh,$(1)) + TITLE+= (wolfSSL, 11s, SAE) + DEPENDS+=+libwolfssl + VARIANT:=wpad-mesh-wolfssl +endef + +Package/wpad-mesh-wolfssl/description = $(Package/wpad-mesh/description) + + +define Package/wpa-supplicant/Default + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD + TITLE:=WPA Supplicant + URL:=http://hostap.epitest.fi/wpa_supplicant/ + DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus + USERID:=network=101:network=101 + PROVIDES:=wpa-supplicant + CONFLICTS:=$(SUPPLICANT_PROVIDERS) + SUPPLICANT_PROVIDERS+=$(1) +endef + +define Package/wpa-supplicant +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (built-in full) + VARIANT:=supplicant-full-internal +endef + +define Package/wpa-supplicant-openssl +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (OpenSSL full) + VARIANT:=supplicant-full-openssl + DEPENDS+=+libopenssl +endef + +define Package/wpa-supplicant-wolfssl +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (wolfSSL full) + VARIANT:=supplicant-full-wolfssl + DEPENDS+=+libwolfssl +endef + +define Package/wpa-supplicant/config + source "$(SOURCE)/Config.in" +endef + +define Package/wpa-supplicant-p2p +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (Wi-Fi P2P support) + DEPENDS+=@PACKAGE_kmod-cfg80211 + VARIANT:=supplicant-p2p-internal +endef + +define Package/wpa-supplicant-mesh/Default +$(call Package/wpa-supplicant/Default,$(1)) + DEPENDS+=@PACKAGE_kmod-cfg80211 @(!TARGET_uml||BROKEN) + PROVIDES+=wpa-supplicant-mesh +endef + +define Package/wpa-supplicant-mesh-openssl +$(call Package/wpa-supplicant-mesh/Default,$(1)) + TITLE+= (OpenSSL, 11s, SAE) + VARIANT:=supplicant-mesh-openssl + DEPENDS+=+libopenssl +endef + +define Package/wpa-supplicant-mesh-wolfssl +$(call Package/wpa-supplicant-mesh/Default,$(1)) + TITLE+= (wolfSSL, 11s, SAE) + VARIANT:=supplicant-mesh-wolfssl + DEPENDS+=+libwolfssl +endef + +define Package/wpa-supplicant-basic +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (11r, 11w) + VARIANT:=supplicant-basic +endef + +define Package/wpa-supplicant-mini +$(call Package/wpa-supplicant/Default,$(1)) + TITLE+= (minimal) + VARIANT:=supplicant-mini +endef + + +define Package/hostapd-common + TITLE:=hostapd/wpa_supplicant common support files + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD +endef + +define Package/hostapd-utils + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD + TITLE:=IEEE 802.1x Authenticator (utils) + URL:=http://hostap.epitest.fi/ + DEPENDS:=@$(subst $(space),||,$(foreach pkg,$(HOSTAPD_PROVIDERS),PACKAGE_$(pkg))) +endef + +define Package/hostapd-utils/description + This package contains a command line utility to control the + IEEE 802.1x/WPA/EAP/RADIUS Authenticator. +endef + +define Package/wpa-cli + SECTION:=net + CATEGORY:=Network + SUBMENU:=WirelessAPD + DEPENDS:=@$(subst $(space),||,$(foreach pkg,$(SUPPLICANT_PROVIDERS),PACKAGE_$(pkg))) + TITLE:=WPA Supplicant command line control utility +endef + +define Package/eapol-test/Default + TITLE:=802.1x auth test utility + SECTION:=net + SUBMENU:=WirelessAPD + CATEGORY:=Network + DEPENDS:=$(DRV_DEPENDS) +libubus +endef + +define Package/eapol-test + $(call Package/eapol-test/Default,$(1)) + TITLE+= (built-in full) + VARIANT:=supplicant-full-internal +endef + +define Package/eapol-test-openssl + $(call Package/eapol-test/Default,$(1)) + TITLE+= (OpenSSL full) + VARIANT:=supplicant-full-openssl + CONFLICTS:=$(filter-out eapol-test-openssl ,$(EAPOL_TEST_PROVIDERS)) + DEPENDS+=+libopenssl + PROVIDES:=eapol-test +endef + +define Package/eapol-test-wolfssl + $(call Package/eapol-test/Default,$(1)) + TITLE+= (wolfSSL full) + VARIANT:=supplicant-full-wolfssl + CONFLICTS:=$(filter-out eapol-test-openssl ,$(filter-out eapol-test-wolfssl ,$(EAPOL_TEST_PROVIDERS))) + DEPENDS+=+libwolfssl + PROVIDES:=eapol-test +endef + + +ifneq ($(wildcard $(PKG_BUILD_DIR)/.config_*),$(subst .configured_,.config_,$(STAMP_CONFIGURED))) + define Build/Configure/rebuild + $(FIND) $(PKG_BUILD_DIR) -name \*.o -or -name \*.a | $(XARGS) rm -f + rm -f $(PKG_BUILD_DIR)/hostapd/hostapd + rm -f $(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant + rm -f $(PKG_BUILD_DIR)/.config_* + touch $(subst .configured_,.config_,$(STAMP_CONFIGURED)) + endef +endif + +define Build/Configure + $(Build/Configure/rebuild) + $(if $(wildcard ./files/hostapd-$(CONFIG_VARIANT).config), \ + $(CP) ./files/hostapd-$(CONFIG_VARIANT).config $(PKG_BUILD_DIR)/hostapd/.config \ + ) + $(if $(wildcard ./files/wpa_supplicant-$(CONFIG_VARIANT).config), \ + $(CP) ./files/wpa_supplicant-$(CONFIG_VARIANT).config $(PKG_BUILD_DIR)/wpa_supplicant/.config + ) +endef + +TARGET_CPPFLAGS := \ + -I$(STAGING_DIR)/usr/include/libnl-tiny \ + -I$(PKG_BUILD_DIR)/src/crypto \ + $(TARGET_CPPFLAGS) \ + -DCONFIG_LIBNL20 \ + -D_GNU_SOURCE \ + $(if $(CONFIG_WPA_MSG_MIN_PRIORITY),-DCONFIG_MSG_MIN_PRIORITY=$(CONFIG_WPA_MSG_MIN_PRIORITY)) + +TARGET_CFLAGS += -ffunction-sections -fdata-sections -flto +TARGET_LDFLAGS += -Wl,--gc-sections -flto=jobserver -fuse-linker-plugin -lubox -lubus + +ifdef CONFIG_PACKAGE_kmod-cfg80211 + TARGET_LDFLAGS += -lm -lnl-tiny +endif + +ifdef CONFIG_WPA_ENABLE_WEP + DRIVER_MAKEOPTS += CONFIG_WEP=y +endif + +define Build/RunMake + CFLAGS="$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)" \ + $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(1) \ + $(TARGET_CONFIGURE_OPTS) \ + $(DRIVER_MAKEOPTS) \ + LIBS="$(TARGET_LDFLAGS)" \ + LIBS_c="$(TARGET_LDFLAGS_C)" \ + AR="$(TARGET_CROSS)gcc-ar" \ + BCHECK= \ + $(if $(findstring s,$(OPENWRT_VERBOSE)),V=1) \ + $(2) +endef + +define Build/Compile/wpad + echo ` \ + $(call Build/RunMake,hostapd,-s MULTICALL=1 dump_cflags); \ + $(call Build/RunMake,wpa_supplicant,-s MULTICALL=1 dump_cflags) | \ + sed -e 's,-n ,,g' -e 's^$(TARGET_CFLAGS)^^' \ + ` > $(PKG_BUILD_DIR)/.cflags + sed -i 's/"/\\"/g' $(PKG_BUILD_DIR)/.cflags + +$(call Build/RunMake,hostapd, \ + CFLAGS="$$$$(cat $(PKG_BUILD_DIR)/.cflags)" \ + MULTICALL=1 \ + hostapd_cli hostapd_multi.a \ + ) + +$(call Build/RunMake,wpa_supplicant, \ + CFLAGS="$$$$(cat $(PKG_BUILD_DIR)/.cflags)" \ + MULTICALL=1 \ + wpa_cli wpa_supplicant_multi.a \ + ) + +export MAKEFLAGS="$(MAKE_JOBSERVER)"; $(TARGET_CC) -o $(PKG_BUILD_DIR)/wpad \ + $(TARGET_CFLAGS) \ + ./files/multicall.c \ + $(PKG_BUILD_DIR)/hostapd/hostapd_multi.a \ + $(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant_multi.a \ + $(TARGET_LDFLAGS) +endef + +define Build/Compile/hostapd + +$(call Build/RunMake,hostapd, \ + hostapd hostapd_cli \ + ) +endef + +define Build/Compile/supplicant + +$(call Build/RunMake,wpa_supplicant, \ + wpa_cli wpa_supplicant \ + ) +endef + +define Build/Compile/supplicant-full-internal + +$(call Build/RunMake,wpa_supplicant, \ + eapol_test \ + ) +endef + +define Build/Compile/supplicant-full-openssl + +$(call Build/RunMake,wpa_supplicant, \ + eapol_test \ + ) +endef + +define Build/Compile/supplicant-full-wolfssl + +$(call Build/RunMake,wpa_supplicant, \ + eapol_test \ + ) +endef + +define Build/Compile + $(Build/Compile/$(LOCAL_TYPE)) + $(Build/Compile/$(BUILD_VARIANT)) +endef + +define Install/hostapd + $(INSTALL_DIR) $(1)/usr/sbin +endef + +define Install/supplicant + $(INSTALL_DIR) $(1)/usr/sbin +endef + +define Package/hostapd-common/install + $(INSTALL_DIR) $(1)/etc/capabilities $(1)/etc/rc.button $(1)/etc/hotplug.d/ieee80211 $(1)/etc/init.d $(1)/lib/netifd $(1)/usr/share/acl.d + $(INSTALL_DATA) ./files/hostapd.sh $(1)/lib/netifd/hostapd.sh + $(INSTALL_BIN) ./files/wpad.init $(1)/etc/init.d/wpad + $(INSTALL_BIN) ./files/wps-hotplug.sh $(1)/etc/rc.button/wps + $(INSTALL_DATA) ./files/wpad_acl.json $(1)/usr/share/acl.d + $(INSTALL_DATA) ./files/wpad.json $(1)/etc/capabilities +endef + +define Package/hostapd/install + $(call Install/hostapd,$(1)) + $(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd $(1)/usr/sbin/ +endef +Package/hostapd-basic/install = $(Package/hostapd/install) +Package/hostapd-basic-openssl/install = $(Package/hostapd/install) +Package/hostapd-basic-wolfssl/install = $(Package/hostapd/install) +Package/hostapd-mini/install = $(Package/hostapd/install) +Package/hostapd-openssl/install = $(Package/hostapd/install) +Package/hostapd-wolfssl/install = $(Package/hostapd/install) + +ifneq ($(LOCAL_TYPE),supplicant) + define Package/hostapd-utils/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd_cli $(1)/usr/sbin/ + endef +endif + +define Package/wpad/install + $(call Install/hostapd,$(1)) + $(call Install/supplicant,$(1)) + $(INSTALL_BIN) $(PKG_BUILD_DIR)/wpad $(1)/usr/sbin/ + $(LN) wpad $(1)/usr/sbin/hostapd + $(LN) wpad $(1)/usr/sbin/wpa_supplicant + $(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd_cli $(1)/usr/sbin/ +endef +Package/wpad-basic/install = $(Package/wpad/install) +Package/wpad-basic-openssl/install = $(Package/wpad/install) +Package/wpad-basic-wolfssl/install = $(Package/wpad/install) +Package/wpad-mini/install = $(Package/wpad/install) +Package/wpad-openssl/install = $(Package/wpad/install) +Package/wpad-wolfssl/install = $(Package/wpad/install) +Package/wpad-mesh-openssl/install = $(Package/wpad/install) +Package/wpad-mesh-wolfssl/install = $(Package/wpad/install) + +define Package/wpa-supplicant/install + $(call Install/supplicant,$(1)) + $(INSTALL_BIN) $(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant $(1)/usr/sbin/ +endef +Package/wpa-supplicant-basic/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-mini/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-p2p/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-openssl/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-wolfssl/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-mesh-openssl/install = $(Package/wpa-supplicant/install) +Package/wpa-supplicant-mesh-wolfssl/install = $(Package/wpa-supplicant/install) + +ifneq ($(LOCAL_TYPE),hostapd) + define Package/wpa-cli/install + $(INSTALL_DIR) $(1)/usr/sbin + $(CP) $(PKG_BUILD_DIR)/wpa_supplicant/wpa_cli $(1)/usr/sbin/ + endef +endif + +ifeq ($(BUILD_VARIANT),supplicant-full-internal) + define Package/eapol-test/install + $(INSTALL_DIR) $(1)/usr/sbin + $(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/ + endef +endif + +ifeq ($(BUILD_VARIANT),supplicant-full-openssl) + define Package/eapol-test-openssl/install + $(INSTALL_DIR) $(1)/usr/sbin + $(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/ + endef +endif + +ifeq ($(BUILD_VARIANT),supplicant-full-wolfssl) + define Package/eapol-test-wolfssl/install + $(INSTALL_DIR) $(1)/usr/sbin + $(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/ + endef +endif + +$(eval $(call BuildPackage,hostapd)) +$(eval $(call BuildPackage,hostapd-basic)) +$(eval $(call BuildPackage,hostapd-basic-openssl)) +$(eval $(call BuildPackage,hostapd-basic-wolfssl)) +$(eval $(call BuildPackage,hostapd-mini)) +$(eval $(call BuildPackage,hostapd-openssl)) +$(eval $(call BuildPackage,hostapd-wolfssl)) +$(eval $(call BuildPackage,wpad)) +$(eval $(call BuildPackage,wpad-mesh-openssl)) +$(eval $(call BuildPackage,wpad-mesh-wolfssl)) +$(eval $(call BuildPackage,wpad-basic)) +$(eval $(call BuildPackage,wpad-basic-openssl)) +$(eval $(call BuildPackage,wpad-basic-wolfssl)) +$(eval $(call BuildPackage,wpad-mini)) +$(eval $(call BuildPackage,wpad-openssl)) +$(eval $(call BuildPackage,wpad-wolfssl)) +$(eval $(call BuildPackage,wpa-supplicant)) +$(eval $(call BuildPackage,wpa-supplicant-mesh-openssl)) +$(eval $(call BuildPackage,wpa-supplicant-mesh-wolfssl)) +$(eval $(call BuildPackage,wpa-supplicant-basic)) +$(eval $(call BuildPackage,wpa-supplicant-mini)) +$(eval $(call BuildPackage,wpa-supplicant-p2p)) +$(eval $(call BuildPackage,wpa-supplicant-openssl)) +$(eval $(call BuildPackage,wpa-supplicant-wolfssl)) +$(eval $(call BuildPackage,wpa-cli)) +$(eval $(call BuildPackage,hostapd-utils)) +$(eval $(call BuildPackage,hostapd-common)) +$(eval $(call BuildPackage,eapol-test)) +$(eval $(call BuildPackage,eapol-test-openssl)) +$(eval $(call BuildPackage,eapol-test-wolfssl)) diff --git a/qca/hostapd/files/hostapd-basic.config b/qca/hostapd/files/hostapd-basic.config new file mode 100644 index 000000000..33c38192b --- /dev/null +++ b/qca/hostapd/files/hostapd-basic.config @@ -0,0 +1,401 @@ +# Example hostapd build time configuration +# +# This file lists the configuration options that are used when building the +# hostapd binary. All lines starting with # are ignored. Configuration option +# lines must be commented out complete, if they are not to be included, i.e., +# just setting VARIABLE=n is not disabling that variable. +# +# This file is included in Makefile, so variables like CFLAGS and LIBS can also +# be modified from here. In most cass, these lines should use += in order not +# to override previous values of the variables. + +# Driver interface for Host AP driver +#CONFIG_DRIVER_HOSTAP=y + +# Driver interface for wired authenticator +CONFIG_DRIVER_WIRED=y + +# Driver interface for drivers using the nl80211 kernel interface +CONFIG_DRIVER_NL80211=y + +# QCA vendor extensions to nl80211 +#CONFIG_DRIVER_NL80211_QCA=y + +# driver_nl80211.c requires libnl. If you are compiling it yourself +# you may need to point hostapd to your version of libnl. +# +#CFLAGS += -I$ +#LIBS += -L$ + +# Use libnl v2.0 (or 3.0) libraries. +#CONFIG_LIBNL20=y + +# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored) +#CONFIG_LIBNL32=y + + +# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver) +#CONFIG_DRIVER_BSD=y +#CFLAGS += -I/usr/local/include +#LIBS += -L/usr/local/lib +#LIBS_p += -L/usr/local/lib +#LIBS_c += -L/usr/local/lib + +# Driver interface for no driver (e.g., RADIUS server only) +#CONFIG_DRIVER_NONE=y + +# IEEE 802.11F/IAPP +#CONFIG_IAPP=y + +# WPA2/IEEE 802.11i RSN pre-authentication +CONFIG_RSN_PREAUTH=y + +# IEEE 802.11w (management frame protection) +#CONFIG_IEEE80211W=y + +# Support Operating Channel Validation +#CONFIG_OCV=y + +# Integrated EAP server +#CONFIG_EAP=y + +# EAP Re-authentication Protocol (ERP) in integrated EAP server +#CONFIG_ERP=y + +# EAP-MD5 for the integrated EAP server +#CONFIG_EAP_MD5=y + +# EAP-TLS for the integrated EAP server +#CONFIG_EAP_TLS=y + +# EAP-MSCHAPv2 for the integrated EAP server +#CONFIG_EAP_MSCHAPV2=y + +# EAP-PEAP for the integrated EAP server +#CONFIG_EAP_PEAP=y + +# EAP-GTC for the integrated EAP server +#CONFIG_EAP_GTC=y + +# EAP-TTLS for the integrated EAP server +#CONFIG_EAP_TTLS=y + +# EAP-SIM for the integrated EAP server +#CONFIG_EAP_SIM=y + +# EAP-AKA for the integrated EAP server +#CONFIG_EAP_AKA=y + +# EAP-AKA' for the integrated EAP server +# This requires CONFIG_EAP_AKA to be enabled, too. +#CONFIG_EAP_AKA_PRIME=y + +# EAP-PAX for the integrated EAP server +#CONFIG_EAP_PAX=y + +# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK) +#CONFIG_EAP_PSK=y + +# EAP-pwd for the integrated EAP server (secure authentication with a password) +#CONFIG_EAP_PWD=y + +# EAP-SAKE for the integrated EAP server +#CONFIG_EAP_SAKE=y + +# EAP-GPSK for the integrated EAP server +#CONFIG_EAP_GPSK=y +# Include support for optional SHA256 cipher suite in EAP-GPSK +#CONFIG_EAP_GPSK_SHA256=y + +# EAP-FAST for the integrated EAP server +#CONFIG_EAP_FAST=y + +# EAP-TEAP for the integrated EAP server +# Note: The current EAP-TEAP implementation is experimental and should not be +# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number +# of conflicting statements and missing details and the implementation has +# vendor specific workarounds for those and as such, may not interoperate with +# any other implementation. This should not be used for anything else than +# experimentation and interoperability testing until those issues has been +# resolved. +#CONFIG_EAP_TEAP=y + +# Wi-Fi Protected Setup (WPS) +#CONFIG_WPS=y +# Enable UPnP support for external WPS Registrars +#CONFIG_WPS_UPNP=y +# Enable WPS support with NFC config method +#CONFIG_WPS_NFC=y + +# EAP-IKEv2 +#CONFIG_EAP_IKEV2=y + +# Trusted Network Connect (EAP-TNC) +#CONFIG_EAP_TNC=y + +# EAP-EKE for the integrated EAP server +#CONFIG_EAP_EKE=y + +# PKCS#12 (PFX) support (used to read private key and certificate file from +# a file that usually has extension .p12 or .pfx) +#CONFIG_PKCS12=y + +# RADIUS authentication server. This provides access to the integrated EAP +# server from external hosts using RADIUS. +#CONFIG_RADIUS_SERVER=y + +# Build IPv6 support for RADIUS operations +#CONFIG_IPV6=y + +# IEEE Std 802.11r-2008 (Fast BSS Transition) +CONFIG_IEEE80211R=y + +# Use the hostapd's IEEE 802.11 authentication (ACL), but without +# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211) +#CONFIG_DRIVER_RADIUS_ACL=y + +# IEEE 802.11n (High Throughput) support +CONFIG_IEEE80211N=y + +# Wireless Network Management (IEEE Std 802.11v-2011) +# Note: This is experimental and not complete implementation. +#CONFIG_WNM=y + +# IEEE 802.11ac (Very High Throughput) support +CONFIG_IEEE80211AC=y + +# IEEE 802.11ax HE support +# Note: This is experimental and work in progress. The definitions are still +# subject to change and this should not be expected to interoperate with the +# final IEEE 802.11ax version. +#CONFIG_IEEE80211AX=y + +# Remove debugging code that is printing out debug messages to stdout. +# This can be used to reduce the size of the hostapd considerably if debugging +# code is not needed. +#CONFIG_NO_STDOUT_DEBUG=y + +# Add support for writing debug log to a file: -f /tmp/hostapd.log +# Disabled by default. +#CONFIG_DEBUG_FILE=y + +# Send debug messages to syslog instead of stdout +CONFIG_DEBUG_SYSLOG=y + +# Add support for sending all debug messages (regardless of debug verbosity) +# to the Linux kernel tracing facility. This helps debug the entire stack by +# making it easy to record everything happening from the driver up into the +# same file, e.g., using trace-cmd. +#CONFIG_DEBUG_LINUX_TRACING=y + +# Remove support for RADIUS accounting +CONFIG_NO_ACCOUNTING=y + +# Remove support for RADIUS +CONFIG_NO_RADIUS=y + +# Remove support for VLANs +#CONFIG_NO_VLAN=y + +# Enable support for fully dynamic VLANs. This enables hostapd to +# automatically create bridge and VLAN interfaces if necessary. +#CONFIG_FULL_DYNAMIC_VLAN=y + +# Use netlink-based kernel API for VLAN operations instead of ioctl() +# Note: This requires libnl 3.1 or newer. +#CONFIG_VLAN_NETLINK=y + +# Remove support for dumping internal state through control interface commands +# This can be used to reduce binary size at the cost of disabling a debugging +# option. +CONFIG_NO_DUMP_STATE=y + +# Enable tracing code for developer debugging +# This tracks use of memory allocations and other registrations and reports +# incorrect use with a backtrace of call (or allocation) location. +#CONFIG_WPA_TRACE=y +# For BSD, comment out these. +#LIBS += -lexecinfo +#LIBS_p += -lexecinfo +#LIBS_c += -lexecinfo + +# Use libbfd to get more details for developer debugging +# This enables use of libbfd to get more detailed symbols for the backtraces +# generated by CONFIG_WPA_TRACE=y. +#CONFIG_WPA_TRACE_BFD=y +# For BSD, comment out these. +#LIBS += -lbfd -liberty -lz +#LIBS_p += -lbfd -liberty -lz +#LIBS_c += -lbfd -liberty -lz + +# hostapd depends on strong random number generation being available from the +# operating system. os_get_random() function is used to fetch random data when +# needed, e.g., for key generation. On Linux and BSD systems, this works by +# reading /dev/urandom. It should be noted that the OS entropy pool needs to be +# properly initialized before hostapd is started. This is important especially +# on embedded devices that do not have a hardware random number generator and +# may by default start up with minimal entropy available for random number +# generation. +# +# As a safety net, hostapd is by default trying to internally collect +# additional entropy for generating random data to mix in with the data +# fetched from the OS. This by itself is not considered to be very strong, but +# it may help in cases where the system pool is not initialized properly. +# However, it is very strongly recommended that the system pool is initialized +# with enough entropy either by using hardware assisted random number +# generator or by storing state over device reboots. +# +# hostapd can be configured to maintain its own entropy store over restarts to +# enhance random number generation. This is not perfect, but it is much more +# secure than using the same sequence of random numbers after every reboot. +# This can be enabled with -e command line option. The specified +# file needs to be readable and writable by hostapd. +# +# If the os_get_random() is known to provide strong random data (e.g., on +# Linux/BSD, the board in question is known to have reliable source of random +# data from /dev/urandom), the internal hostapd random pool can be disabled. +# This will save some in binary size and CPU use. However, this should only be +# considered for builds that are known to be used on devices that meet the +# requirements described above. +CONFIG_NO_RANDOM_POOL=y + +# Should we attempt to use the getrandom(2) call that provides more reliable +# yet secure randomness source than /dev/random on Linux 3.17 and newer. +# Requires glibc 2.25 to build, falls back to /dev/random if unavailable. +CONFIG_GETRANDOM=y + +# Should we use poll instead of select? Select is used by default. +#CONFIG_ELOOP_POLL=y + +# Should we use epoll instead of select? Select is used by default. +CONFIG_ELOOP_EPOLL=y + +# Should we use kqueue instead of select? Select is used by default. +#CONFIG_ELOOP_KQUEUE=y + +# Select TLS implementation +# openssl = OpenSSL (default) +# gnutls = GnuTLS +# internal = Internal TLSv1 implementation (experimental) +# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental) +# none = Empty template +CONFIG_TLS=internal + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1) +# can be enabled to get a stronger construction of messages when block ciphers +# are used. +#CONFIG_TLSV11=y + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2) +# can be enabled to enable use of stronger crypto algorithms. +#CONFIG_TLSV12=y + +# Select which ciphers to use by default with OpenSSL if the user does not +# specify them. +#CONFIG_TLS_DEFAULT_CIPHERS="DEFAULT:!EXP:!LOW" + +# If CONFIG_TLS=internal is used, additional library and include paths are +# needed for LibTomMath. Alternatively, an integrated, minimal version of +# LibTomMath can be used. See beginning of libtommath.c for details on benefits +# and drawbacks of this option. +#CONFIG_INTERNAL_LIBTOMMATH=y +#ifndef CONFIG_INTERNAL_LIBTOMMATH +#LTM_PATH=/usr/src/libtommath-0.39 +#CFLAGS += -I$(LTM_PATH) +#LIBS += -L$(LTM_PATH) +#LIBS_p += -L$(LTM_PATH) +#endif +# At the cost of about 4 kB of additional binary size, the internal LibTomMath +# can be configured to include faster routines for exptmod, sqr, and div to +# speed up DH and RSA calculation considerably +#CONFIG_INTERNAL_LIBTOMMATH_FAST=y + +# Interworking (IEEE 802.11u) +# This can be used to enable functionality to improve interworking with +# external networks. +#CONFIG_INTERWORKING=y + +# Hotspot 2.0 +#CONFIG_HS20=y + +# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file +#CONFIG_SQLITE=y + +# Enable Fast Session Transfer (FST) +#CONFIG_FST=y + +# Enable CLI commands for FST testing +#CONFIG_FST_TEST=y + +# Testing options +# This can be used to enable some testing options (see also the example +# configuration file) that are really useful only for testing clients that +# connect to this hostapd. These options allow, for example, to drop a +# certain percentage of probe requests or auth/(re)assoc frames. +# +#CONFIG_TESTING_OPTIONS=y + +# Automatic Channel Selection +# This will allow hostapd to pick the channel automatically when channel is set +# to "acs_survey" or "0". Eventually, other ACS algorithms can be added in +# similar way. +# +# Automatic selection is currently only done through initialization, later on +# we hope to do background checks to keep us moving to more ideal channels as +# time goes by. ACS is currently only supported through the nl80211 driver and +# your driver must have survey dump capability that is filled by the driver +# during scanning. +# +# You can customize the ACS survey algorithm with the hostapd.conf variable +# acs_num_scans. +# +# Supported ACS drivers: +# * ath9k +# * ath5k +# * ath10k +# +# For more details refer to: +# http://wireless.kernel.org/en/users/Documentation/acs +# +#CONFIG_ACS=y + +# Multiband Operation support +# These extentions facilitate efficient use of multiple frequency bands +# available to the AP and the devices that may associate with it. +#CONFIG_MBO=y + +# Client Taxonomy +# Has the AP retain the Probe Request and (Re)Association Request frames from +# a client, from which a signature can be produced which can identify the model +# of client device like "Nexus 6P" or "iPhone 5s". +#CONFIG_TAXONOMY=y + +# Fast Initial Link Setup (FILS) (IEEE 802.11ai) +#CONFIG_FILS=y +# FILS shared key authentication with PFS +#CONFIG_FILS_SK_PFS=y + +# Include internal line edit mode in hostapd_cli. This can be used to provide +# limited command line editing and history support. +#CONFIG_WPA_CLI_EDIT=y + +# Opportunistic Wireless Encryption (OWE) +# Experimental implementation of draft-harkins-owe-07.txt +#CONFIG_OWE=y + +# Airtime policy support +CONFIG_AIRTIME_POLICY=y + +# Override default value for the wpa_disable_eapol_key_retries configuration +# parameter. See that parameter in hostapd.conf for more details. +#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1 + +# uBus IPC/RPC System +# Services can connect to the bus and provide methods +# that can be called by other services or clients. +CONFIG_UBUS=y + +# OpenWrt patch 380-disable-ctrl-iface-mib.patch +# leads to the MIB only being compiled in if +# CONFIG_CTRL_IFACE_MIB is enabled. +#CONFIG_CTRL_IFACE_MIB=y diff --git a/qca/hostapd/files/hostapd-full.config b/qca/hostapd/files/hostapd-full.config new file mode 100644 index 000000000..20f261ce3 --- /dev/null +++ b/qca/hostapd/files/hostapd-full.config @@ -0,0 +1,401 @@ +# Example hostapd build time configuration +# +# This file lists the configuration options that are used when building the +# hostapd binary. All lines starting with # are ignored. Configuration option +# lines must be commented out complete, if they are not to be included, i.e., +# just setting VARIABLE=n is not disabling that variable. +# +# This file is included in Makefile, so variables like CFLAGS and LIBS can also +# be modified from here. In most cass, these lines should use += in order not +# to override previous values of the variables. + +# Driver interface for Host AP driver +#CONFIG_DRIVER_HOSTAP=y + +# Driver interface for wired authenticator +CONFIG_DRIVER_WIRED=y + +# Driver interface for drivers using the nl80211 kernel interface +CONFIG_DRIVER_NL80211=y + +# QCA vendor extensions to nl80211 +#CONFIG_DRIVER_NL80211_QCA=y + +# driver_nl80211.c requires libnl. If you are compiling it yourself +# you may need to point hostapd to your version of libnl. +# +#CFLAGS += -I$ +#LIBS += -L$ + +# Use libnl v2.0 (or 3.0) libraries. +#CONFIG_LIBNL20=y + +# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored) +#CONFIG_LIBNL32=y + + +# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver) +#CONFIG_DRIVER_BSD=y +#CFLAGS += -I/usr/local/include +#LIBS += -L/usr/local/lib +#LIBS_p += -L/usr/local/lib +#LIBS_c += -L/usr/local/lib + +# Driver interface for no driver (e.g., RADIUS server only) +#CONFIG_DRIVER_NONE=y + +# IEEE 802.11F/IAPP +CONFIG_IAPP=y + +# WPA2/IEEE 802.11i RSN pre-authentication +CONFIG_RSN_PREAUTH=y + +# IEEE 802.11w (management frame protection) +#CONFIG_IEEE80211W=y + +# Support Operating Channel Validation +#CONFIG_OCV=y + +# Integrated EAP server +CONFIG_EAP=y + +# EAP Re-authentication Protocol (ERP) in integrated EAP server +CONFIG_ERP=y + +# EAP-MD5 for the integrated EAP server +CONFIG_EAP_MD5=y + +# EAP-TLS for the integrated EAP server +CONFIG_EAP_TLS=y + +# EAP-MSCHAPv2 for the integrated EAP server +CONFIG_EAP_MSCHAPV2=y + +# EAP-PEAP for the integrated EAP server +CONFIG_EAP_PEAP=y + +# EAP-GTC for the integrated EAP server +CONFIG_EAP_GTC=y + +# EAP-TTLS for the integrated EAP server +CONFIG_EAP_TTLS=y + +# EAP-SIM for the integrated EAP server +#CONFIG_EAP_SIM=y + +# EAP-AKA for the integrated EAP server +#CONFIG_EAP_AKA=y + +# EAP-AKA' for the integrated EAP server +# This requires CONFIG_EAP_AKA to be enabled, too. +#CONFIG_EAP_AKA_PRIME=y + +# EAP-PAX for the integrated EAP server +#CONFIG_EAP_PAX=y + +# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK) +CONFIG_EAP_PSK=y + +# EAP-pwd for the integrated EAP server (secure authentication with a password) +CONFIG_EAP_PWD=y + +# EAP-SAKE for the integrated EAP server +#CONFIG_EAP_SAKE=y + +# EAP-GPSK for the integrated EAP server +#CONFIG_EAP_GPSK=y +# Include support for optional SHA256 cipher suite in EAP-GPSK +#CONFIG_EAP_GPSK_SHA256=y + +# EAP-FAST for the integrated EAP server +CONFIG_EAP_FAST=y + +# EAP-TEAP for the integrated EAP server +# Note: The current EAP-TEAP implementation is experimental and should not be +# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number +# of conflicting statements and missing details and the implementation has +# vendor specific workarounds for those and as such, may not interoperate with +# any other implementation. This should not be used for anything else than +# experimentation and interoperability testing until those issues has been +# resolved. +#CONFIG_EAP_TEAP=y + +# Wi-Fi Protected Setup (WPS) +CONFIG_WPS=y +# Enable UPnP support for external WPS Registrars +#CONFIG_WPS_UPNP=y +# Enable WPS support with NFC config method +#CONFIG_WPS_NFC=y + +# EAP-IKEv2 +#CONFIG_EAP_IKEV2=y + +# Trusted Network Connect (EAP-TNC) +#CONFIG_EAP_TNC=y + +# EAP-EKE for the integrated EAP server +#CONFIG_EAP_EKE=y + +# PKCS#12 (PFX) support (used to read private key and certificate file from +# a file that usually has extension .p12 or .pfx) +CONFIG_PKCS12=y + +# RADIUS authentication server. This provides access to the integrated EAP +# server from external hosts using RADIUS. +#CONFIG_RADIUS_SERVER=y + +# Build IPv6 support for RADIUS operations +CONFIG_IPV6=y + +# IEEE Std 802.11r-2008 (Fast BSS Transition) +CONFIG_IEEE80211R=y + +# Use the hostapd's IEEE 802.11 authentication (ACL), but without +# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211) +#CONFIG_DRIVER_RADIUS_ACL=y + +# IEEE 802.11n (High Throughput) support +CONFIG_IEEE80211N=y + +# Wireless Network Management (IEEE Std 802.11v-2011) +# Note: This is experimental and not complete implementation. +CONFIG_WNM=y + +# IEEE 802.11ac (Very High Throughput) support +CONFIG_IEEE80211AC=y + +# IEEE 802.11ax HE support +# Note: This is experimental and work in progress. The definitions are still +# subject to change and this should not be expected to interoperate with the +# final IEEE 802.11ax version. +#CONFIG_IEEE80211AX=y + +# Remove debugging code that is printing out debug messages to stdout. +# This can be used to reduce the size of the hostapd considerably if debugging +# code is not needed. +#CONFIG_NO_STDOUT_DEBUG=y + +# Add support for writing debug log to a file: -f /tmp/hostapd.log +# Disabled by default. +#CONFIG_DEBUG_FILE=y + +# Send debug messages to syslog instead of stdout +CONFIG_DEBUG_SYSLOG=y + +# Add support for sending all debug messages (regardless of debug verbosity) +# to the Linux kernel tracing facility. This helps debug the entire stack by +# making it easy to record everything happening from the driver up into the +# same file, e.g., using trace-cmd. +#CONFIG_DEBUG_LINUX_TRACING=y + +# Remove support for RADIUS accounting +#CONFIG_NO_ACCOUNTING=y + +# Remove support for RADIUS +#CONFIG_NO_RADIUS=y + +# Remove support for VLANs +#CONFIG_NO_VLAN=y + +# Enable support for fully dynamic VLANs. This enables hostapd to +# automatically create bridge and VLAN interfaces if necessary. +CONFIG_FULL_DYNAMIC_VLAN=y + +# Use netlink-based kernel API for VLAN operations instead of ioctl() +# Note: This requires libnl 3.1 or newer. +#CONFIG_VLAN_NETLINK=y + +# Remove support for dumping internal state through control interface commands +# This can be used to reduce binary size at the cost of disabling a debugging +# option. +CONFIG_NO_DUMP_STATE=y + +# Enable tracing code for developer debugging +# This tracks use of memory allocations and other registrations and reports +# incorrect use with a backtrace of call (or allocation) location. +#CONFIG_WPA_TRACE=y +# For BSD, comment out these. +#LIBS += -lexecinfo +#LIBS_p += -lexecinfo +#LIBS_c += -lexecinfo + +# Use libbfd to get more details for developer debugging +# This enables use of libbfd to get more detailed symbols for the backtraces +# generated by CONFIG_WPA_TRACE=y. +#CONFIG_WPA_TRACE_BFD=y +# For BSD, comment out these. +#LIBS += -lbfd -liberty -lz +#LIBS_p += -lbfd -liberty -lz +#LIBS_c += -lbfd -liberty -lz + +# hostapd depends on strong random number generation being available from the +# operating system. os_get_random() function is used to fetch random data when +# needed, e.g., for key generation. On Linux and BSD systems, this works by +# reading /dev/urandom. It should be noted that the OS entropy pool needs to be +# properly initialized before hostapd is started. This is important especially +# on embedded devices that do not have a hardware random number generator and +# may by default start up with minimal entropy available for random number +# generation. +# +# As a safety net, hostapd is by default trying to internally collect +# additional entropy for generating random data to mix in with the data +# fetched from the OS. This by itself is not considered to be very strong, but +# it may help in cases where the system pool is not initialized properly. +# However, it is very strongly recommended that the system pool is initialized +# with enough entropy either by using hardware assisted random number +# generator or by storing state over device reboots. +# +# hostapd can be configured to maintain its own entropy store over restarts to +# enhance random number generation. This is not perfect, but it is much more +# secure than using the same sequence of random numbers after every reboot. +# This can be enabled with -e command line option. The specified +# file needs to be readable and writable by hostapd. +# +# If the os_get_random() is known to provide strong random data (e.g., on +# Linux/BSD, the board in question is known to have reliable source of random +# data from /dev/urandom), the internal hostapd random pool can be disabled. +# This will save some in binary size and CPU use. However, this should only be +# considered for builds that are known to be used on devices that meet the +# requirements described above. +CONFIG_NO_RANDOM_POOL=y + +# Should we attempt to use the getrandom(2) call that provides more reliable +# yet secure randomness source than /dev/random on Linux 3.17 and newer. +# Requires glibc 2.25 to build, falls back to /dev/random if unavailable. +CONFIG_GETRANDOM=y + +# Should we use poll instead of select? Select is used by default. +#CONFIG_ELOOP_POLL=y + +# Should we use epoll instead of select? Select is used by default. +CONFIG_ELOOP_EPOLL=y + +# Should we use kqueue instead of select? Select is used by default. +#CONFIG_ELOOP_KQUEUE=y + +# Select TLS implementation +# openssl = OpenSSL (default) +# gnutls = GnuTLS +# internal = Internal TLSv1 implementation (experimental) +# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental) +# none = Empty template +CONFIG_TLS=internal + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1) +# can be enabled to get a stronger construction of messages when block ciphers +# are used. +#CONFIG_TLSV11=y + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2) +# can be enabled to enable use of stronger crypto algorithms. +#CONFIG_TLSV12=y + +# Select which ciphers to use by default with OpenSSL if the user does not +# specify them. +#CONFIG_TLS_DEFAULT_CIPHERS="DEFAULT:!EXP:!LOW" + +# If CONFIG_TLS=internal is used, additional library and include paths are +# needed for LibTomMath. Alternatively, an integrated, minimal version of +# LibTomMath can be used. See beginning of libtommath.c for details on benefits +# and drawbacks of this option. +CONFIG_INTERNAL_LIBTOMMATH=y +#ifndef CONFIG_INTERNAL_LIBTOMMATH +#LTM_PATH=/usr/src/libtommath-0.39 +#CFLAGS += -I$(LTM_PATH) +#LIBS += -L$(LTM_PATH) +#LIBS_p += -L$(LTM_PATH) +#endif +# At the cost of about 4 kB of additional binary size, the internal LibTomMath +# can be configured to include faster routines for exptmod, sqr, and div to +# speed up DH and RSA calculation considerably +#CONFIG_INTERNAL_LIBTOMMATH_FAST=y + +# Interworking (IEEE 802.11u) +# This can be used to enable functionality to improve interworking with +# external networks. +CONFIG_INTERWORKING=y + +# Hotspot 2.0 +#CONFIG_HS20=y + +# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file +#CONFIG_SQLITE=y + +# Enable Fast Session Transfer (FST) +#CONFIG_FST=y + +# Enable CLI commands for FST testing +#CONFIG_FST_TEST=y + +# Testing options +# This can be used to enable some testing options (see also the example +# configuration file) that are really useful only for testing clients that +# connect to this hostapd. These options allow, for example, to drop a +# certain percentage of probe requests or auth/(re)assoc frames. +# +#CONFIG_TESTING_OPTIONS=y + +# Automatic Channel Selection +# This will allow hostapd to pick the channel automatically when channel is set +# to "acs_survey" or "0". Eventually, other ACS algorithms can be added in +# similar way. +# +# Automatic selection is currently only done through initialization, later on +# we hope to do background checks to keep us moving to more ideal channels as +# time goes by. ACS is currently only supported through the nl80211 driver and +# your driver must have survey dump capability that is filled by the driver +# during scanning. +# +# You can customize the ACS survey algorithm with the hostapd.conf variable +# acs_num_scans. +# +# Supported ACS drivers: +# * ath9k +# * ath5k +# * ath10k +# +# For more details refer to: +# http://wireless.kernel.org/en/users/Documentation/acs +# +#CONFIG_ACS=y + +# Multiband Operation support +# These extentions facilitate efficient use of multiple frequency bands +# available to the AP and the devices that may associate with it. +#CONFIG_MBO=y + +# Client Taxonomy +# Has the AP retain the Probe Request and (Re)Association Request frames from +# a client, from which a signature can be produced which can identify the model +# of client device like "Nexus 6P" or "iPhone 5s". +CONFIG_TAXONOMY=y + +# Fast Initial Link Setup (FILS) (IEEE 802.11ai) +CONFIG_FILS=y +# FILS shared key authentication with PFS +CONFIG_FILS_SK_PFS=y + +# Include internal line edit mode in hostapd_cli. This can be used to provide +# limited command line editing and history support. +#CONFIG_WPA_CLI_EDIT=y + +# Opportunistic Wireless Encryption (OWE) +# Experimental implementation of draft-harkins-owe-07.txt +#CONFIG_OWE=y + +# Airtime policy support +CONFIG_AIRTIME_POLICY=y + +# Override default value for the wpa_disable_eapol_key_retries configuration +# parameter. See that parameter in hostapd.conf for more details. +#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1 + +# uBus IPC/RPC System +# Services can connect to the bus and provide methods +# that can be called by other services or clients. +CONFIG_UBUS=y + +# OpenWrt patch 380-disable-ctrl-iface-mib.patch +# leads to the MIB only being compiled in if +# CONFIG_CTRL_IFACE_MIB is enabled. +CONFIG_CTRL_IFACE_MIB=y diff --git a/qca/hostapd/files/hostapd-mini.config b/qca/hostapd/files/hostapd-mini.config new file mode 100644 index 000000000..b3050f7bb --- /dev/null +++ b/qca/hostapd/files/hostapd-mini.config @@ -0,0 +1,401 @@ +# Example hostapd build time configuration +# +# This file lists the configuration options that are used when building the +# hostapd binary. All lines starting with # are ignored. Configuration option +# lines must be commented out complete, if they are not to be included, i.e., +# just setting VARIABLE=n is not disabling that variable. +# +# This file is included in Makefile, so variables like CFLAGS and LIBS can also +# be modified from here. In most cass, these lines should use += in order not +# to override previous values of the variables. + +# Driver interface for Host AP driver +#CONFIG_DRIVER_HOSTAP=y + +# Driver interface for wired authenticator +CONFIG_DRIVER_WIRED=y + +# Driver interface for drivers using the nl80211 kernel interface +CONFIG_DRIVER_NL80211=y + +# QCA vendor extensions to nl80211 +#CONFIG_DRIVER_NL80211_QCA=y + +# driver_nl80211.c requires libnl. If you are compiling it yourself +# you may need to point hostapd to your version of libnl. +# +#CFLAGS += -I$ +#LIBS += -L$ + +# Use libnl v2.0 (or 3.0) libraries. +#CONFIG_LIBNL20=y + +# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored) +#CONFIG_LIBNL32=y + + +# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver) +#CONFIG_DRIVER_BSD=y +#CFLAGS += -I/usr/local/include +#LIBS += -L/usr/local/lib +#LIBS_p += -L/usr/local/lib +#LIBS_c += -L/usr/local/lib + +# Driver interface for no driver (e.g., RADIUS server only) +#CONFIG_DRIVER_NONE=y + +# IEEE 802.11F/IAPP +#CONFIG_IAPP=y + +# WPA2/IEEE 802.11i RSN pre-authentication +CONFIG_RSN_PREAUTH=y + +# IEEE 802.11w (management frame protection) +#CONFIG_IEEE80211W=y + +# Support Operating Channel Validation +#CONFIG_OCV=y + +# Integrated EAP server +#CONFIG_EAP=y + +# EAP Re-authentication Protocol (ERP) in integrated EAP server +#CONFIG_ERP=y + +# EAP-MD5 for the integrated EAP server +#CONFIG_EAP_MD5=y + +# EAP-TLS for the integrated EAP server +#CONFIG_EAP_TLS=y + +# EAP-MSCHAPv2 for the integrated EAP server +#CONFIG_EAP_MSCHAPV2=y + +# EAP-PEAP for the integrated EAP server +#CONFIG_EAP_PEAP=y + +# EAP-GTC for the integrated EAP server +#CONFIG_EAP_GTC=y + +# EAP-TTLS for the integrated EAP server +#CONFIG_EAP_TTLS=y + +# EAP-SIM for the integrated EAP server +#CONFIG_EAP_SIM=y + +# EAP-AKA for the integrated EAP server +#CONFIG_EAP_AKA=y + +# EAP-AKA' for the integrated EAP server +# This requires CONFIG_EAP_AKA to be enabled, too. +#CONFIG_EAP_AKA_PRIME=y + +# EAP-PAX for the integrated EAP server +#CONFIG_EAP_PAX=y + +# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK) +#CONFIG_EAP_PSK=y + +# EAP-pwd for the integrated EAP server (secure authentication with a password) +#CONFIG_EAP_PWD=y + +# EAP-SAKE for the integrated EAP server +#CONFIG_EAP_SAKE=y + +# EAP-GPSK for the integrated EAP server +#CONFIG_EAP_GPSK=y +# Include support for optional SHA256 cipher suite in EAP-GPSK +#CONFIG_EAP_GPSK_SHA256=y + +# EAP-FAST for the integrated EAP server +#CONFIG_EAP_FAST=y + +# EAP-TEAP for the integrated EAP server +# Note: The current EAP-TEAP implementation is experimental and should not be +# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number +# of conflicting statements and missing details and the implementation has +# vendor specific workarounds for those and as such, may not interoperate with +# any other implementation. This should not be used for anything else than +# experimentation and interoperability testing until those issues has been +# resolved. +#CONFIG_EAP_TEAP=y + +# Wi-Fi Protected Setup (WPS) +#CONFIG_WPS=y +# Enable UPnP support for external WPS Registrars +#CONFIG_WPS_UPNP=y +# Enable WPS support with NFC config method +#CONFIG_WPS_NFC=y + +# EAP-IKEv2 +#CONFIG_EAP_IKEV2=y + +# Trusted Network Connect (EAP-TNC) +#CONFIG_EAP_TNC=y + +# EAP-EKE for the integrated EAP server +#CONFIG_EAP_EKE=y + +# PKCS#12 (PFX) support (used to read private key and certificate file from +# a file that usually has extension .p12 or .pfx) +#CONFIG_PKCS12=y + +# RADIUS authentication server. This provides access to the integrated EAP +# server from external hosts using RADIUS. +#CONFIG_RADIUS_SERVER=y + +# Build IPv6 support for RADIUS operations +#CONFIG_IPV6=y + +# IEEE Std 802.11r-2008 (Fast BSS Transition) +#CONFIG_IEEE80211R=y + +# Use the hostapd's IEEE 802.11 authentication (ACL), but without +# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211) +#CONFIG_DRIVER_RADIUS_ACL=y + +# IEEE 802.11n (High Throughput) support +CONFIG_IEEE80211N=y + +# Wireless Network Management (IEEE Std 802.11v-2011) +# Note: This is experimental and not complete implementation. +#CONFIG_WNM=y + +# IEEE 802.11ac (Very High Throughput) support +CONFIG_IEEE80211AC=y + +# IEEE 802.11ax HE support +# Note: This is experimental and work in progress. The definitions are still +# subject to change and this should not be expected to interoperate with the +# final IEEE 802.11ax version. +#CONFIG_IEEE80211AX=y + +# Remove debugging code that is printing out debug messages to stdout. +# This can be used to reduce the size of the hostapd considerably if debugging +# code is not needed. +#CONFIG_NO_STDOUT_DEBUG=y + +# Add support for writing debug log to a file: -f /tmp/hostapd.log +# Disabled by default. +#CONFIG_DEBUG_FILE=y + +# Send debug messages to syslog instead of stdout +CONFIG_DEBUG_SYSLOG=y + +# Add support for sending all debug messages (regardless of debug verbosity) +# to the Linux kernel tracing facility. This helps debug the entire stack by +# making it easy to record everything happening from the driver up into the +# same file, e.g., using trace-cmd. +#CONFIG_DEBUG_LINUX_TRACING=y + +# Remove support for RADIUS accounting +CONFIG_NO_ACCOUNTING=y + +# Remove support for RADIUS +CONFIG_NO_RADIUS=y + +# Remove support for VLANs +#CONFIG_NO_VLAN=y + +# Enable support for fully dynamic VLANs. This enables hostapd to +# automatically create bridge and VLAN interfaces if necessary. +#CONFIG_FULL_DYNAMIC_VLAN=y + +# Use netlink-based kernel API for VLAN operations instead of ioctl() +# Note: This requires libnl 3.1 or newer. +#CONFIG_VLAN_NETLINK=y + +# Remove support for dumping internal state through control interface commands +# This can be used to reduce binary size at the cost of disabling a debugging +# option. +CONFIG_NO_DUMP_STATE=y + +# Enable tracing code for developer debugging +# This tracks use of memory allocations and other registrations and reports +# incorrect use with a backtrace of call (or allocation) location. +#CONFIG_WPA_TRACE=y +# For BSD, comment out these. +#LIBS += -lexecinfo +#LIBS_p += -lexecinfo +#LIBS_c += -lexecinfo + +# Use libbfd to get more details for developer debugging +# This enables use of libbfd to get more detailed symbols for the backtraces +# generated by CONFIG_WPA_TRACE=y. +#CONFIG_WPA_TRACE_BFD=y +# For BSD, comment out these. +#LIBS += -lbfd -liberty -lz +#LIBS_p += -lbfd -liberty -lz +#LIBS_c += -lbfd -liberty -lz + +# hostapd depends on strong random number generation being available from the +# operating system. os_get_random() function is used to fetch random data when +# needed, e.g., for key generation. On Linux and BSD systems, this works by +# reading /dev/urandom. It should be noted that the OS entropy pool needs to be +# properly initialized before hostapd is started. This is important especially +# on embedded devices that do not have a hardware random number generator and +# may by default start up with minimal entropy available for random number +# generation. +# +# As a safety net, hostapd is by default trying to internally collect +# additional entropy for generating random data to mix in with the data +# fetched from the OS. This by itself is not considered to be very strong, but +# it may help in cases where the system pool is not initialized properly. +# However, it is very strongly recommended that the system pool is initialized +# with enough entropy either by using hardware assisted random number +# generator or by storing state over device reboots. +# +# hostapd can be configured to maintain its own entropy store over restarts to +# enhance random number generation. This is not perfect, but it is much more +# secure than using the same sequence of random numbers after every reboot. +# This can be enabled with -e command line option. The specified +# file needs to be readable and writable by hostapd. +# +# If the os_get_random() is known to provide strong random data (e.g., on +# Linux/BSD, the board in question is known to have reliable source of random +# data from /dev/urandom), the internal hostapd random pool can be disabled. +# This will save some in binary size and CPU use. However, this should only be +# considered for builds that are known to be used on devices that meet the +# requirements described above. +CONFIG_NO_RANDOM_POOL=y + +# Should we attempt to use the getrandom(2) call that provides more reliable +# yet secure randomness source than /dev/random on Linux 3.17 and newer. +# Requires glibc 2.25 to build, falls back to /dev/random if unavailable. +CONFIG_GETRANDOM=y + +# Should we use poll instead of select? Select is used by default. +#CONFIG_ELOOP_POLL=y + +# Should we use epoll instead of select? Select is used by default. +CONFIG_ELOOP_EPOLL=y + +# Should we use kqueue instead of select? Select is used by default. +#CONFIG_ELOOP_KQUEUE=y + +# Select TLS implementation +# openssl = OpenSSL (default) +# gnutls = GnuTLS +# internal = Internal TLSv1 implementation (experimental) +# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental) +# none = Empty template +CONFIG_TLS=internal + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1) +# can be enabled to get a stronger construction of messages when block ciphers +# are used. +#CONFIG_TLSV11=y + +# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2) +# can be enabled to enable use of stronger crypto algorithms. +#CONFIG_TLSV12=y + +# Select which ciphers to use by default with OpenSSL if the user does not +# specify them. +#CONFIG_TLS_DEFAULT_CIPHERS="DEFAULT:!EXP:!LOW" + +# If CONFIG_TLS=internal is used, additional library and include paths are +# needed for LibTomMath. Alternatively, an integrated, minimal version of +# LibTomMath can be used. See beginning of libtommath.c for details on benefits +# and drawbacks of this option. +#CONFIG_INTERNAL_LIBTOMMATH=y +#ifndef CONFIG_INTERNAL_LIBTOMMATH +#LTM_PATH=/usr/src/libtommath-0.39 +#CFLAGS += -I$(LTM_PATH) +#LIBS += -L$(LTM_PATH) +#LIBS_p += -L$(LTM_PATH) +#endif +# At the cost of about 4 kB of additional binary size, the internal LibTomMath +# can be configured to include faster routines for exptmod, sqr, and div to +# speed up DH and RSA calculation considerably +#CONFIG_INTERNAL_LIBTOMMATH_FAST=y + +# Interworking (IEEE 802.11u) +# This can be used to enable functionality to improve interworking with +# external networks. +#CONFIG_INTERWORKING=y + +# Hotspot 2.0 +#CONFIG_HS20=y + +# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file +#CONFIG_SQLITE=y + +# Enable Fast Session Transfer (FST) +#CONFIG_FST=y + +# Enable CLI commands for FST testing +#CONFIG_FST_TEST=y + +# Testing options +# This can be used to enable some testing options (see also the example +# configuration file) that are really useful only for testing clients that +# connect to this hostapd. These options allow, for example, to drop a +# certain percentage of probe requests or auth/(re)assoc frames. +# +#CONFIG_TESTING_OPTIONS=y + +# Automatic Channel Selection +# This will allow hostapd to pick the channel automatically when channel is set +# to "acs_survey" or "0". Eventually, other ACS algorithms can be added in +# similar way. +# +# Automatic selection is currently only done through initialization, later on +# we hope to do background checks to keep us moving to more ideal channels as +# time goes by. ACS is currently only supported through the nl80211 driver and +# your driver must have survey dump capability that is filled by the driver +# during scanning. +# +# You can customize the ACS survey algorithm with the hostapd.conf variable +# acs_num_scans. +# +# Supported ACS drivers: +# * ath9k +# * ath5k +# * ath10k +# +# For more details refer to: +# http://wireless.kernel.org/en/users/Documentation/acs +# +#CONFIG_ACS=y + +# Multiband Operation support +# These extentions facilitate efficient use of multiple frequency bands +# available to the AP and the devices that may associate with it. +#CONFIG_MBO=y + +# Client Taxonomy +# Has the AP retain the Probe Request and (Re)Association Request frames from +# a client, from which a signature can be produced which can identify the model +# of client device like "Nexus 6P" or "iPhone 5s". +#CONFIG_TAXONOMY=y + +# Fast Initial Link Setup (FILS) (IEEE 802.11ai) +#CONFIG_FILS=y +# FILS shared key authentication with PFS +#CONFIG_FILS_SK_PFS=y + +# Include internal line edit mode in hostapd_cli. This can be used to provide +# limited command line editing and history support. +#CONFIG_WPA_CLI_EDIT=y + +# Opportunistic Wireless Encryption (OWE) +# Experimental implementation of draft-harkins-owe-07.txt +#CONFIG_OWE=y + +# Airtime policy support +#CONFIG_AIRTIME_POLICY=y + +# Override default value for the wpa_disable_eapol_key_retries configuration +# parameter. See that parameter in hostapd.conf for more details. +#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1 + +# uBus IPC/RPC System +# Services can connect to the bus and provide methods +# that can be called by other services or clients. +CONFIG_UBUS=y + +# OpenWrt patch 380-disable-ctrl-iface-mib.patch +# leads to the MIB only being compiled in if +# CONFIG_CTRL_IFACE_MIB is enabled. +#CONFIG_CTRL_IFACE_MIB=y diff --git a/qca/hostapd/files/hostapd.sh b/qca/hostapd/files/hostapd.sh new file mode 100644 index 000000000..9a517cf40 --- /dev/null +++ b/qca/hostapd/files/hostapd.sh @@ -0,0 +1,1609 @@ +. /lib/functions/network.sh +. /lib/functions.sh + +wpa_supplicant_add_rate() { + local var="$1" + local val="$(($2 / 1000))" + local sub="$((($2 / 100) % 10))" + append $var "$val" "," + [ $sub -gt 0 ] && append $var "." +} + +hostapd_add_rate() { + local var="$1" + local val="$(($2 / 100))" + append $var "$val" " " +} + +hostapd_append_wep_key() { + local var="$1" + + wep_keyidx=0 + set_default key 1 + case "$key" in + [1234]) + for idx in 1 2 3 4; do + local zidx + zidx=$(($idx - 1)) + json_get_var ckey "key${idx}" + [ -n "$ckey" ] && \ + append $var "wep_key${zidx}=$(prepare_key_wep "$ckey")" "$N$T" + done + wep_keyidx=$((key - 1)) + ;; + *) + append $var "wep_key0=$(prepare_key_wep "$key")" "$N$T" + ;; + esac +} + +hostapd_append_wpa_key_mgmt() { + local auth_type_l="$(echo $auth_type | tr 'a-z' 'A-Z')" + + case "$auth_type" in + psk|eap) + append wpa_key_mgmt "WPA-$auth_type_l" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-${auth_type_l}" + [ "${ieee80211w:-0}" -gt 0 ] && append wpa_key_mgmt "WPA-${auth_type_l}-SHA256" + ;; + eap192) + append wpa_key_mgmt "WPA-EAP-SUITE-B-192" + append wpa_key_mgmt "WPA-EAP-SHA256" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-EAP" + ;; + eap-eap256) + append wpa_key_mgmt "WPA-EAP" + append wpa_key_mgmt "WPA-EAP-SHA256" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-EAP" + ;; + eap256) + append wpa_key_mgmt "WPA-EAP-SHA256" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-EAP" + ;; + sae) + append wpa_key_mgmt "SAE" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-SAE" + ;; + psk-sae) + append wpa_key_mgmt "WPA-PSK" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-PSK" + [ "${ieee80211w:-0}" -gt 0 ] && append wpa_key_mgmt "WPA-PSK-SHA256" + append wpa_key_mgmt "SAE" + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt "FT-SAE" + ;; + owe) + append wpa_key_mgmt "OWE" + ;; + esac + + [ "$fils" -gt 0 ] && { + case "$auth_type" in + eap*) + append wpa_key_mgmt FILS-SHA256 + [ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt FT-FILS-SHA256 + ;; + esac + } + + [ "$auth_osen" = "1" ] && append wpa_key_mgmt "OSEN" +} + +hostapd_add_log_config() { + config_add_boolean \ + log_80211 \ + log_8021x \ + log_radius \ + log_wpa \ + log_driver \ + log_iapp \ + log_mlme + + config_add_int log_level +} + +hostapd_common_add_device_config() { + config_add_array basic_rate + config_add_array supported_rates + config_add_string beacon_rate + + config_add_string country country3 + config_add_boolean country_ie doth + config_add_boolean spectrum_mgmt_required + config_add_int local_pwr_constraint + config_add_string require_mode + config_add_boolean legacy_rates + config_add_int cell_density + config_add_int rts_threshold + config_add_int rssi_reject_assoc_rssi + config_add_int rssi_ignore_probe_request + config_add_int maxassoc + + config_add_string acs_chan_bias + config_add_boolean acs_exclude_dfs + config_add_array hostapd_options + + config_add_int airtime_mode + + config_add_boolean multiple_bssid rnr_beacon he_co_locate ema + + hostapd_add_log_config +} + +hostapd_prepare_device_config() { + local config="$1" + local driver="$2" + + local base_cfg= + + json_get_vars country country3 country_ie beacon_int:100 dtim_period:2 doth require_mode legacy_rates \ + acs_chan_bias local_pwr_constraint spectrum_mgmt_required airtime_mode cell_density \ + rts_threshold beacon_rate rssi_reject_assoc_rssi rssi_ignore_probe_request maxassoc \ + multiple_bssid he_co_locate rnr_beacon ema acs_exclude_dfs + + hostapd_set_log_options base_cfg + + set_default country_ie 1 + set_default spectrum_mgmt_required 0 + set_default doth 1 + set_default legacy_rates 0 + set_default airtime_mode 0 + set_default cell_density 0 + set_default he_co_locate 0 + set_default rnr_beacon 0 + set_default multiple_bssid 0 + set_default ema 0 + set_default acs_exclude_dfs 0 + + [ "$band" = "6g" ] && multiple_bssid=1 + + [ -n "$country" ] && { + append base_cfg "country_code=$country" "$N" + [ -n "$country3" ] && append base_cfg "country3=$country3" "$N" + + [ "$country_ie" -gt 0 ] && { + append base_cfg "ieee80211d=1" "$N" + [ -n "$local_pwr_constraint" ] && append base_cfg "local_pwr_constraint=$local_pwr_constraint" "$N" + [ "$spectrum_mgmt_required" -gt 0 ] && append base_cfg "spectrum_mgmt_required=$spectrum_mgmt_required" "$N" + } + [ "$hwmode" = "a" -a "$doth" -gt 0 ] && append base_cfg "ieee80211h=1" "$N" + } + + [ -n "$acs_chan_bias" ] && append base_cfg "acs_chan_bias=$acs_chan_bias" "$N" + + local brlist= br + json_get_values basic_rate_list basic_rate + local rlist= r + json_get_values rate_list supported_rates + + [ -n "$hwmode" ] && append base_cfg "hw_mode=$hwmode" "$N" + if [ "$hwmode" = "g" ] || [ "$hwmode" = "a" ]; then + [ -n "$require_mode" ] && legacy_rates=0 + case "$require_mode" in + n) append base_cfg "require_ht=1" "$N";; + ac) append base_cfg "require_vht=1" "$N";; + esac + fi + case "$hwmode" in + b) + if [ "$cell_density" -eq 1 ]; then + set_default rate_list "5500 11000" + set_default basic_rate_list "5500 11000" + elif [ "$cell_density" -ge 2 ]; then + set_default rate_list "11000" + set_default basic_rate_list "11000" + fi + ;; + g) + if [ "$cell_density" -eq 0 ] || [ "$cell_density" -eq 1 ]; then + if [ "$legacy_rates" -eq 0 ]; then + set_default rate_list "6000 9000 12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "6000 12000 24000" + elif [ "$cell_density" -eq 1 ]; then + set_default rate_list "5500 6000 9000 11000 12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "5500 11000" + fi + elif [ "$cell_density" -ge 3 ] && [ "$legacy_rates" -ne 0 ] || [ "$cell_density" -eq 2 ]; then + if [ "$legacy_rates" -eq 0 ]; then + set_default rate_list "12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "12000 24000" + else + set_default rate_list "11000 12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "11000" + fi + elif [ "$cell_density" -ge 3 ]; then + set_default rate_list "24000 36000 48000 54000" + set_default basic_rate_list "24000" + fi + ;; + a) + if [ "$cell_density" -eq 1 ]; then + set_default rate_list "6000 9000 12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "6000 12000 24000" + elif [ "$cell_density" -eq 2 ]; then + set_default rate_list "12000 18000 24000 36000 48000 54000" + set_default basic_rate_list "12000 24000" + elif [ "$cell_density" -ge 3 ]; then + set_default rate_list "24000 36000 48000 54000" + set_default basic_rate_list "24000" + fi + ;; + esac + + for r in $rate_list; do + hostapd_add_rate rlist "$r" + done + + for br in $basic_rate_list; do + hostapd_add_rate brlist "$br" + done + + [ -n "$rssi_reject_assoc_rssi" ] && append base_cfg "rssi_reject_assoc_rssi=$rssi_reject_assoc_rssi" "$N" + [ -n "$rssi_ignore_probe_request" ] && append base_cfg "rssi_ignore_probe_request=$rssi_ignore_probe_request" "$N" + [ -n "$beacon_rate" ] && append base_cfg "beacon_rate=$beacon_rate" "$N" + [ -n "$rlist" ] && append base_cfg "supported_rates=$rlist" "$N" + [ -n "$brlist" ] && append base_cfg "basic_rates=$brlist" "$N" + append base_cfg "beacon_int=$beacon_int" "$N" + [ -n "$rts_threshold" ] && append base_cfg "rts_threshold=$rts_threshold" "$N" + append base_cfg "dtim_period=$dtim_period" "$N" + [ "$airtime_mode" -gt 0 ] && append base_cfg "airtime_mode=$airtime_mode" "$N" + [ -n "$maxassoc" ] && append base_cfg "iface_max_num_sta=$maxassoc" "$N" + [ "$rnr_beacon" -gt 0 ] && append base_cfg "rnr_beacon=$rnr_beacon" "$N" + [ "$he_co_locate" -gt 0 ] && append base_cfg "he_co_locate=$he_co_locate" "$N" + [ "$multiple_bssid" -gt 0 ] && append base_cfg "multiple_bssid=$multiple_bssid" "$N" + [ "$ema" -gt 0 ] && append base_cfg "ema=$ema" "$N" + [ "$acs_exclude_dfs" -gt 0 ] && append base_cfg "acs_exclude_dfs=$acs_exclude_dfs" "$N" + + json_get_values opts hostapd_options + for val in $opts; do + append base_cfg "$val" "$N" + done + + cat > "$config" <