2022-11-18 17:10:38 +00:00
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From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001
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From: Marty Jones <mj8263788@gmail.com>
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Date: Tue, 31 May 2022 00:51:23 -0400
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Subject: [PATCH] uboot: add NanoPi R5S board
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Signed-off-by: Marty Jones <mj8263788@gmail.com>
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 25 +++++
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arch/arm/dts/rk3568-nanopi-r5s.dts | 9 ++
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arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++
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board/friendlyelec/nanopi-r5s-rk3568/Kconfig | 15 +++
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board/friendlyelec/nanopi-r5s-rk3568/Makefile | 4 +
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.../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c | 4 +
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configs/nanopi-r5s-rk3568_defconfig | 97 +++++++++++++++++++
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include/configs/nanopi-r5s-rk3568.h | 17 ++++
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9 files changed, 178 insertions(+)
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create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
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create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig
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create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile
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create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
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create mode 100644 configs/nanopi-r5s-rk3568_defconfig
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create mode 100644 include/configs/nanopi-r5s-rk3568.h
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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2023-04-22 06:07:24 +00:00
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2022-11-18 17:10:38 +00:00
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dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3568-evb.dtb \
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+ rk3568-nanopi-r5s.dtb \
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2023-04-22 06:07:24 +00:00
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rk3566-radxa-cm3-io.dtb \
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rk3568-rock-3a.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
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@@ -0,0 +1,25 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
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+ */
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+
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2023-04-22 06:07:24 +00:00
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+#include "rk356x-u-boot.dtsi"
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2022-11-18 17:10:38 +00:00
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+
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+/ {
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+ chosen {
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+ stdout-path = &uart2;
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+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
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+ };
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+};
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+
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+&sdmmc0 {
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+ bus-width = <4>;
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+ u-boot,dm-spl;
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+ u-boot,spl-fifo-mode;
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+};
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+
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+&uart2 {
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+ clock-frequency = <24000000>;
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+ u-boot,dm-spl;
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+ status = "okay";
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
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@@ -0,0 +1,9 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+#include "rk3568-evb.dts"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R5S";
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+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
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+};
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--- /dev/null
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+++ b/configs/nanopi-r5s-rk3568_defconfig
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@@ -0,0 +1,91 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_TEXT_BASE=0x00a00000
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+CONFIG_SPL_LIBCOMMON_SUPPORT=y
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+CONFIG_SPL_LIBGENERIC_SUPPORT=y
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+CONFIG_NR_DRAM_BANKS=2
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+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
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+CONFIG_ROCKCHIP_RK3568=y
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+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
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+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_SPL_BOARD_INIT=y
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+CONFIG_SPL_MMC=y
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+CONFIG_SPL_SERIAL=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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2023-04-22 06:07:24 +00:00
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+CONFIG_TARGET_EVB_RK3568=y
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+CONFIG_SPL_STACK=0x400000
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+CONFIG_DEBUG_UART_BASE=0xFE660000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SYS_LOAD_ADDR=0xc00800
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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+CONFIG_SPL_BSS_START_ADDR=0x4000000
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+CONFIG_SPL_BSS_MAX_SIZE=0x4000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_ADC=y
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+CONFIG_SPL_ATF=y
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+CONFIG_CMD_ADC=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_I2C=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_REGULATOR=y
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+# CONFIG_CMD_SETEXPR is not set
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+# CONFIG_SPL_DOS_PARTITION is not set
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_OF_LIVE=y
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_SPL_CLK=y
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+CONFIG_CLK_SCMI=y
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+CONFIG_RESET_SCMI=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MISC=y
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+CONFIG_SUPPORT_EMMC_RPMB=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_MMC_SDHCI=y
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+CONFIG_MMC_SDHCI_SDMA=y
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+CONFIG_MMC_SDHCI_ROCKCHIP=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_PMIC_RK8XX=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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+CONFIG_REGULATOR_PWM=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_SPL_RAM=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSRESET=y
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_XHCI_DWC3=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_DWC3=y
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+CONFIG_USB_DWC3_GENERIC=y
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+CONFIG_ERRNO_STR=y
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