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Fix rockchip uboot on 6.1
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
d05bd9be17
commit
1fd3a0d155
35 changed files with 4 additions and 2 deletions
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@ -0,0 +1,144 @@
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From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 20 Feb 2022 07:57:50 -0500
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Subject: [PATCH] rockchip: handle bootrom mode in spl
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/Makefile | 6 +--
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arch/arm/mach-rockchip/boot_mode.c | 4 +-
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arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++-
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3 files changed, 59 insertions(+), 5 deletions(-)
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--- a/arch/arm/mach-rockchip/Makefile
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+++ b/arch/arm/mach-rockchip/Makefile
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@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
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obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
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-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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-
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# Always include boot_mode.o, as we bypass it (i.e. turn it off)
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# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
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# we can have the preprocessor correctly recognise both 0x0 and 0
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# meaning "turn it off".
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-obj-y += boot_mode.o
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+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
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+
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+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
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obj-$(CONFIG_MISC_INIT_R) += misc.o
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endif
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--- a/arch/arm/mach-rockchip/boot_mode.c
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+++ b/arch/arm/mach-rockchip/boot_mode.c
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@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void)
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ret = -ENODEV;
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uclass_foreach_dev(dev, uc) {
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if (!strncmp(dev->name, "saradc", 6)) {
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- ret = adc_channel_single_shot(dev->name, 1, &val);
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+ ret = adc_channel_single_shot(dev->name, 0, &val);
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break;
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}
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}
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@@ -89,6 +89,7 @@ int setup_boot_mode(void)
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boot_mode = readl(reg);
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debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
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+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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/* Clear boot mode */
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writel(BOOT_NORMAL, reg);
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@@ -102,6 +103,7 @@ int setup_boot_mode(void)
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env_set("preboot", "setenv preboot; ums mmc 0");
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break;
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}
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+#endif
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return 0;
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}
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -9,19 +9,30 @@
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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+#include <asm/arch-rockchip/boot_mode.h>
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#include <asm/arch-rockchip/grf_rk3568.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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#define PMUGRF_BASE 0xfdc20000
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#define GRF_BASE 0xfdc60000
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+#define GRF_GPIO1B_IOMUX_H 0x0c
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+#define GRF_GPIO1C_IOMUX_L 0x10
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+#define GRF_GPIO1C_IOMUX_H 0x14
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+#define GRF_GPIO1D_IOMUX_L 0x18
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+#define GRF_GPIO1D_IOMUX_H 0x1c
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+#define GRF_GPIO2A_IOMUX_L 0x20
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#define GRF_GPIO1B_DS_2 0x218
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#define GRF_GPIO1B_DS_3 0x21c
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#define GRF_GPIO1C_DS_0 0x220
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#define GRF_GPIO1C_DS_1 0x224
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#define GRF_GPIO1C_DS_2 0x228
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#define GRF_GPIO1C_DS_3 0x22c
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-#define SGRF_BASE 0xFDD18000
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+#define GRF_GPIO1D_DS_0 0x230
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+#define GRF_GPIO1D_DS_1 0x234
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+#define GRF_GPIO1D_DS_2 0x238
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+#define SGRF_BASE 0xfdd18000
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+#define SGRF_SOC_CON3 0x0c
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#define SGRF_SOC_CON4 0x10
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#define EMMC_HPROT_SECURE_CTRL 0x03
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#define SDMMC0_HPROT_SECURE_CTRL 0x01
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@@ -133,6 +144,24 @@ int arch_cpu_init(void)
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
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+
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+ /* emmc, sfc, and sdmmc iomux */
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
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+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L);
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+
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+ /* set the fspi d0~3 cs0 to level 2 */
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+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
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+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
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+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
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+
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+ /* Set the fspi to secure */
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+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
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+
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#endif
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return 0;
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}
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@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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#endif
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return 0;
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}
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+
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+#ifdef CONFIG_SPL_BUILD
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+
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+void __weak led_setup(void)
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+{
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+}
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+
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+void spl_board_init(void)
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+{
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+ led_setup();
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+
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+#if defined(SPL_DM_REGULATOR)
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+ /*
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+ * Turning the eMMC and SPI back on (if disabled via the Qseven
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+ * BIOS_ENABLE) signal is done through a always-on regulator).
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+ */
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+ if (regulators_enable_boot_on(false))
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+ debug("%s: Cannot enable boot on regulator\n", __func__);
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+#endif
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+
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+ setup_boot_mode();
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+}
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+#endif
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