mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix rockchip uboot on 6.1
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
d05bd9be17
commit
1fd3a0d155
35 changed files with 4 additions and 2 deletions
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@ -1,81 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Copyright (C) 2022 ImmortalWrt.org
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include $(TOPDIR)/rules.mk
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PKG_NAME:=arm-trusted-firmware-rockchip-vendor
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
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PKG_SOURCE_DATE:=2022-08-01
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PKG_SOURCE_VERSION:=b0c100f1a260d807df450019774993c761beb79d
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PKG_MIRROR_HASH:=17723ac8f6ec446c759444ee29ba4fe544cebb3785e26d8e10c91c54b9df3f1a
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PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
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MAKE_PATH:=$(PKG_NAME)
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include $(INCLUDE_DIR)/package.mk
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define Package/arm-trusted-firmware-rockchip-vendor
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SECTION:=boot
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CATEGORY:=Boot Loaders
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TITLE:=ARM Trusted Firmware for Rockchip
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endef
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define Package/arm-trusted-firmware-rk3328
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$(Package/arm-trusted-firmware-rockchip-vendor)
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DEPENDS:=@TARGET_rockchip_armv8
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VARIANT:=rk3328
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endef
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define Package/arm-trusted-firmware-rk3399
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$(Package/arm-trusted-firmware-rockchip-vendor)
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DEPENDS:=@TARGET_rockchip_armv8
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VARIANT:=rk3399
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endef
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define Package/arm-trusted-firmware-rk3566
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$(Package/arm-trusted-firmware-rockchip-vendor)
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DEPENDS:=@TARGET_rockchip_armv8
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VARIANT:=rk3566
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endef
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define Package/arm-trusted-firmware-rk3568
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$(Package/arm-trusted-firmware-rockchip-vendor)
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DEPENDS:=@TARGET_rockchip_armv8
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VARIANT:=rk3568
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endef
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define Build/Configure
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$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini
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$(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini
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$(call Build/Configure/Default)
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endef
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define Build/Compile
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$(CURDIR)/pack-firmware.sh build $(BUILD_VARIANT) '$(PKG_BUILD_DIR)'
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endef
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define Build/InstallDev
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$(CURDIR)/pack-firmware.sh install $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' '$(STAGING_DIR_IMAGE)'
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endef
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define Package/arm-trusted-firmware-rk3328/install
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endef
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define Package/arm-trusted-firmware-rk3399/install
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endef
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define Package/arm-trusted-firmware-rk3566/install
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endef
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define Package/arm-trusted-firmware-rk3568/install
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endef
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$(eval $(call BuildPackage,arm-trusted-firmware-rk3328))
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$(eval $(call BuildPackage,arm-trusted-firmware-rk3399))
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$(eval $(call BuildPackage,arm-trusted-firmware-rk3566))
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$(eval $(call BuildPackage,arm-trusted-firmware-rk3568))
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@ -1,60 +0,0 @@
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#!/bin/bash
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# Copyright (C) 2021 ImmortalWrt.org
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ACTION="$1"
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VARIANT="$2"
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PKG_BUILD_DIR="$3"
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STAGING_DIR_IMAGE="$4"
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case "$VARIANT" in
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"rk3328")
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ATF="rk33/rk322xh_bl31_v1.49.elf"
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DDR="rk33/rk3328_ddr_333MHz_v1.19.bin"
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LOADER="rk33/rk322xh_miniloader_v2.50.bin"
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;;
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"rk3399")
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ATF="rk33/rk3399_bl31_v1.35.elf"
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DDR="rk33/rk3399_ddr_800MHz_v1.27.bin"
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LOADER="rk33/rk3399_miniloader_v1.26.bin"
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;;
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"rk3566")
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ATF="rk35/rk3568_bl31_v1.34.elf"
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DDR="rk35/rk3566_ddr_1056MHz_v1.13.bin"
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;;
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"rk3568")
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ATF="rk35/rk3568_bl31_v1.34.elf"
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DDR="rk35/rk3568_ddr_1560MHz_v1.13.bin"
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;;
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*)
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echo -e "Not compatible with your platform: $VARIANT."
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exit 1
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;;
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esac
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set -x
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if [ "$ACTION" == "build" ]; then
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case "$VARIANT" in
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rk33*)
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"$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
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cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
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"$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini"
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;;
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esac
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elif [ "$ACTION" == "install" ]; then
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mkdir -p "$STAGING_DIR_IMAGE"
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cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/
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case "$VARIANT" in
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rk33*)
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cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/
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cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/
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cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/
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;;
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rk35*)
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cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/
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;;
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esac
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else
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echo -e "Unknown operation: $ACTION."
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exit 1
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fi
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set +x
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@ -1,15 +0,0 @@
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[VERSION]
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MAJOR=1
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MINOR=0
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[BL30_OPTION]
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SEC=0
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[BL31_OPTION]
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SEC=1
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PATH=bl31.elf
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ADDR=0x10000
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[BL32_OPTION]
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SEC=0
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[BL33_OPTION]
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SEC=0
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[OUTPUT]
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PATH=$(PKG_BUILD_DIR)/$(VARIANT)-trust.bin
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@ -1,49 +0,0 @@
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#
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# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de>
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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PKG_NAME:=arm-trusted-firmware-rockchip
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PKG_VERSION:=2.8
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PKG_RELEASE:=1
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PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz
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PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?
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PKG_HASH:=61df69619fd611da9e43abf66be28d6d59722feef559587fad0ca4cd9e499758
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PKG_LICENSE:=BSD-3-Clause
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PKG_LICENSE_FILES:=license.md
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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MAKE_PATH:=$(PKG_NAME)
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include $(INCLUDE_DIR)/package.mk
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define Package/arm-trusted-firmware-rockchip
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SECTION:=boot
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CATEGORY:=Boot Loaders
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TITLE:=ARM Trusted Firmware for Rockchip
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DEPENDS:=@TARGET_rockchip_armv8
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endef
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define Build/Prepare
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$(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE)
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endef
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define Build/Compile
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endef
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define Build/InstallDev
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$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)
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$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/
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endef
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define Package/arm-trusted-firmware-rockchip/install
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endef
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$(eval $(call BuildPackage,arm-trusted-firmware-rockchip))
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@ -1,322 +0,0 @@
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_VERSION:=2023.04
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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include $(INCLUDE_DIR)/u-boot.mk
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include $(INCLUDE_DIR)/package.mk
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define U-Boot/Default
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BUILD_TARGET:=rockchip
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UENV:=default
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HIDDEN:=1
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endef
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# RK3328 boards
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define U-Boot/nanopi-r2c-rk3328
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R2C
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r2c
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.49.elf
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USE_RKBIN:=1
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endef
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define U-Boot/nanopi-r2s-rk3328
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R2S
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r2s \
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friendlyarm_nanopi-neo3
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.49.elf
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USE_RKBIN:=1
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endef
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define U-Boot/orangepi-r1-plus-rk3328
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BUILD_SUBTARGET:=armv8
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NAME:=Orange Pi R1 Plus
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BUILD_DEVICES:= \
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xunlong_orangepi-r1-plus
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.49.elf
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USE_RKBIN:=1
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endef
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define U-Boot/orangepi-r1-plus-lts-rk3328
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BUILD_SUBTARGET:=armv8
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NAME:=Orange Pi R1 Plus LTS
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BUILD_DEVICES:= \
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xunlong_orangepi-r1-plus-lts
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.49.elf
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USE_RKBIN:=1
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endef
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# RK3399 boards
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define U-Boot/guangmiao-g4c-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=GuangMiao G4C
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BUILD_DEVICES:= \
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sharevdi_guangmiao-g4c
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DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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define U-Boot/nanopi-r4s-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R4S
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r4s
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DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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define U-Boot/nanopi-r4se-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R4SE
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r4se
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DEPENDS:=+PACKAGE_u-boot-nanopi-r4se-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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define U-Boot/rock-pi-4-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rock Pi 4
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BUILD_DEVICES:= \
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radxa_rock-pi-4
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DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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define U-Boot/rockpro64-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=RockPro64
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BUILD_DEVICES:= \
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pine64_rockpro64
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DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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define U-Boot/rongpin-king3399-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rongpin King3399
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BUILD_DEVICES:= \
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rongpin_king3399
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DEPENDS:=+PACKAGE_u-boot-rongpin-king3399-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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define U-Boot/rocktech-mpc1903-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rocktech MPC1903
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BUILD_DEVICES:= \
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rocktech_mpc1903
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DEPENDS:=+PACKAGE_u-boot-rocktech-mpc1903-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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define U-Boot/sharevdi-h3399pc-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=SHAREVDI H3399PC
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BUILD_DEVICES:= \
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sharevdi_h3399pc
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DEPENDS:=+PACKAGE_u-boot-sharevdi-h3399pc-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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define U-Boot/dilusense-dlfr100-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Dilusense DLFR100
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BUILD_DEVICES:= \
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dilusense_dlfr100
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DEPENDS:=+PACKAGE_u-boot-dilusense-dlfr100-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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# RK3568 boards
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define U-Boot/mrkaio-m68s-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=Mrkaio M68S
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BUILD_DEVICES:= \
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ezpro_mrkaio-m68s \
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ezpro_mrkaio-m68s-plus
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DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/nanopi-r5s-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R5S
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r5c \
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friendlyarm_nanopi-r5s
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/opc-h68k-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=OPC-H68K Board
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BUILD_DEVICES:= \
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hinlink_opc-h66k \
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hinlink_opc-h68k \
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hinlink_opc-h69k
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DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/photonicat-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=Ariaboard Photonicat
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BUILD_DEVICES:= \
|
||||
ariaboard_photonicat
|
||||
DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:arm-trusted-firmware-rk3568
|
||||
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
|
||||
ATF:=rk3568_bl31_v1.34.elf
|
||||
DDR:=rk3568_ddr_1560MHz_v1.13.bin
|
||||
endef
|
||||
|
||||
define U-Boot/radxa-e25-rk3568
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=Radxa E25
|
||||
BUILD_DEVICES:= \
|
||||
radxa_e25
|
||||
DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:arm-trusted-firmware-rk3568
|
||||
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
|
||||
ATF:=rk3568_bl31_v1.34.elf
|
||||
DDR:=rk3568_ddr_1560MHz_v1.13.bin
|
||||
endef
|
||||
|
||||
define U-Boot/rock-3a-rk3568
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=ROCK3 Model A
|
||||
BUILD_DEVICES:= \
|
||||
radxa_rock-3a
|
||||
DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568
|
||||
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
|
||||
ATF:=rk3568_bl31_v1.34.elf
|
||||
DDR:=rk3568_ddr_1560MHz_v1.13.bin
|
||||
endef
|
||||
|
||||
define U-Boot/r66s-rk3568
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=R66S/R68S
|
||||
BUILD_DEVICES:= \
|
||||
fastrhino_r66s \
|
||||
fastrhino_r68s
|
||||
DEPENDS:=+PACKAGE_u-boot-r66s-rk3568:arm-trusted-firmware-rk3568
|
||||
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
|
||||
ATF:=rk3568_bl31_v1.34.elf
|
||||
DDR:=rk3568_ddr_1560MHz_v1.13.bin
|
||||
endef
|
||||
|
||||
define U-Boot/station-p2-rk3568
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=StationP2
|
||||
BUILD_DEVICES:= \
|
||||
firefly_station-p2
|
||||
DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568
|
||||
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
|
||||
ATF:=rk3568_bl31_v1.34.elf
|
||||
DDR:=rk3568_ddr_1560MHz_v1.13.bin
|
||||
endef
|
||||
|
||||
UBOOT_TARGETS := \
|
||||
mrkaio-m68s-rk3568 \
|
||||
opc-h68k-rk3568 \
|
||||
photonicat-rk3568 \
|
||||
radxa-e25-rk3568 \
|
||||
rock-3a-rk3568 \
|
||||
r66s-rk3568 \
|
||||
station-p2-rk3568 \
|
||||
sharevdi-h3399pc-rk3399 \
|
||||
guangmiao-g4c-rk3399 \
|
||||
nanopi-r4s-rk3399 \
|
||||
nanopi-r4se-rk3399 \
|
||||
nanopi-r5s-rk3568 \
|
||||
rock-pi-4-rk3399 \
|
||||
rockpro64-rk3399 \
|
||||
rongpin-king3399-rk3399 \
|
||||
rocktech-mpc1903-rk3399 \
|
||||
dilusense-dlfr100-rk3399 \
|
||||
nanopi-r2c-rk3328 \
|
||||
nanopi-r2s-rk3328 \
|
||||
orangepi-r1-plus-rk3328 \
|
||||
orangepi-r1-plus-lts-rk3328
|
||||
|
||||
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
|
||||
|
||||
UBOOT_MAKE_FLAGS += \
|
||||
PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
|
||||
BL31=$(STAGING_DIR_IMAGE)/$(ATF)
|
||||
|
||||
ifeq ($(CONFIG_PACKAGE_arm-trusted-firmware-rk3568),y)
|
||||
UBOOT_MAKE_FLAGS += \
|
||||
ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(DDR)
|
||||
endif
|
||||
|
||||
define Build/Configure
|
||||
$(call Build/Configure/U-Boot)
|
||||
|
||||
$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
|
||||
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
|
||||
echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
|
||||
endef
|
||||
|
||||
define Build/InstallDev
|
||||
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
|
||||
ifneq ($(USE_RKBIN),)
|
||||
$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000
|
||||
$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img
|
||||
else
|
||||
$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
|
||||
$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
|
||||
endif
|
||||
endef
|
||||
|
||||
define Package/u-boot/install/default
|
||||
endef
|
||||
|
||||
$(eval $(call BuildPackage/U-Boot))
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From 1ab5d2b9cf1b9c1c7ccb58243992fb163c64a14d Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
Date: Wed, 5 Apr 2023 21:06:19 +0800
|
||||
Subject: [PATCH 1/3] Revert "rockchip: rk3399: Drop altbootcmd"
|
||||
|
||||
This reverts commit d00fb6421c8fad639f608f55f9291305061ffb17.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
include/configs/rk3399_common.h | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/include/configs/rk3399_common.h
|
||||
+++ b/include/configs/rk3399_common.h
|
||||
@@ -52,7 +52,10 @@
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
- "boot_targets=" BOOT_TARGETS "\0"
|
||||
+ "boot_targets=" BOOT_TARGETS "\0" \
|
||||
+ "altbootcmd=" \
|
||||
+ "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
|
||||
+ "run distro_bootcmd\0"
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
From 535b09f84be0660ef5e85431328746e74cc8e6b7 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
Date: Wed, 5 Apr 2023 21:08:21 +0800
|
||||
Subject: [PATCH 2/3] Revert "rockchip: Disable DISTRO_DEFAULTS for rk3399
|
||||
boards"
|
||||
|
||||
This reverts commit 2b9cc7845cf96955db363519faab9a78e166c453.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
arch/arm/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -1955,7 +1955,7 @@ config ARCH_ROCKCHIP
|
||||
imply ADC
|
||||
imply CMD_DM
|
||||
imply DEBUG_UART_BOARD_INIT
|
||||
- imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
|
||||
+ imply DISTRO_DEFAULTS
|
||||
imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS
|
||||
imply FAT_WRITE
|
||||
imply SARADC_ROCKCHIP
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From 93ac12531f7c672ef1fe7689cf8b67ec2372efef Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
Date: Wed, 5 Apr 2023 21:08:27 +0800
|
||||
Subject: [PATCH 3/3] Revert "rockchip: Convert rockpro64-rk3399 to use
|
||||
standard boot"
|
||||
|
||||
This reverts commit 3891c68ef50eda38d78c95ecd03aed030aa6bb53.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
include/configs/rk3399_common.h | 5 ++++-
|
||||
include/configs/rockchip-common.h | 2 --
|
||||
2 files changed, 4 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/include/configs/rk3399_common.h
|
||||
+++ b/include/configs/rk3399_common.h
|
||||
@@ -47,12 +47,15 @@
|
||||
#define ROCKCHIP_DEVICE_SETTINGS
|
||||
#endif
|
||||
|
||||
+#include <config_distro_bootcmd.h>
|
||||
+#include <environment/distro/sf.h>
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
- "boot_targets=" BOOT_TARGETS "\0" \
|
||||
+ BOOTENV \
|
||||
+ BOOTENV_SF \
|
||||
"altbootcmd=" \
|
||||
"setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
|
||||
"run distro_bootcmd\0"
|
||||
--- a/include/configs/rockchip-common.h
|
||||
+++ b/include/configs/rockchip-common.h
|
||||
@@ -67,14 +67,12 @@
|
||||
BOOT_TARGET_PXE(func) \
|
||||
BOOT_TARGET_DHCP(func) \
|
||||
BOOT_TARGET_SF(func)
|
||||
-#define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi"
|
||||
#else
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
BOOT_TARGET_MMC(func) \
|
||||
BOOT_TARGET_USB(func) \
|
||||
BOOT_TARGET_PXE(func) \
|
||||
BOOT_TARGET_DHCP(func)
|
||||
-#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
|
|
@ -1,169 +0,0 @@
|
|||
From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001
|
||||
From: Marty Jones <mj8263788@gmail.com>
|
||||
Date: Tue, 31 May 2022 00:51:23 -0400
|
||||
Subject: [PATCH] uboot: add NanoPi R5S board
|
||||
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
---
|
||||
arch/arm/dts/Makefile | 1 +
|
||||
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 25 +++++
|
||||
arch/arm/dts/rk3568-nanopi-r5s.dts | 9 ++
|
||||
arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++
|
||||
board/friendlyelec/nanopi-r5s-rk3568/Kconfig | 15 +++
|
||||
board/friendlyelec/nanopi-r5s-rk3568/Makefile | 4 +
|
||||
.../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c | 4 +
|
||||
configs/nanopi-r5s-rk3568_defconfig | 97 +++++++++++++++++++
|
||||
include/configs/nanopi-r5s-rk3568.h | 17 ++++
|
||||
9 files changed, 178 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
|
||||
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
|
||||
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig
|
||||
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile
|
||||
create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
|
||||
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
|
||||
create mode 100644 include/configs/nanopi-r5s-rk3568.h
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-nanopi-r5s.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
|
||||
@@ -0,0 +1,25 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,dm-spl;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ clock-frequency = <24000000>;
|
||||
+ u-boot,dm-spl;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
|
||||
@@ -0,0 +1,9 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5S";
|
||||
+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r5s-rk3568_defconfig
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 2d7c904f271ffd19086cafe7cd6548ec5b1a5a83 Mon Sep 17 00:00:00 2001
|
||||
From: Jason Zhu <jason.zhu@rock-chips.com>
|
||||
Date: Thu, 12 Mar 2020 15:04:51 +0800
|
||||
Subject: [PATCH] driver: Makefile: support adc in SPL
|
||||
|
||||
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
|
||||
Change-Id: I915becbf9597aa070001d3368d8daf9079565fc9
|
||||
---
|
||||
common/spl/Kconfig | 6 ++++++
|
||||
drivers/Makefile | 2 +-
|
||||
2 files changed, 7 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/common/spl/Kconfig
|
||||
+++ b/common/spl/Kconfig
|
||||
@@ -587,6 +587,11 @@ config SPL_FIT_IMAGE_TINY
|
||||
ensure this information is available to the next image
|
||||
invoked).
|
||||
|
||||
+config SPL_ADC
|
||||
+ bool "Support ADC drivers in SPL"
|
||||
+ help
|
||||
+ Enable ADC drivers in SPL.
|
||||
+
|
||||
config SPL_CACHE
|
||||
bool "Support CACHE drivers"
|
||||
help
|
||||
--- a/drivers/Makefile
|
||||
+++ b/drivers/Makefile
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
+obj-$(CONFIG_$(SPL_)ADC) += adc/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sun, 20 Feb 2022 07:57:50 -0500
|
||||
Subject: [PATCH] rockchip: handle bootrom mode in spl
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/mach-rockchip/Makefile | 6 +--
|
||||
arch/arm/mach-rockchip/boot_mode.c | 4 +-
|
||||
arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++-
|
||||
3 files changed, 59 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm/mach-rockchip/Makefile
|
||||
+++ b/arch/arm/mach-rockchip/Makefile
|
||||
@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
|
||||
|
||||
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
|
||||
|
||||
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
|
||||
-
|
||||
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
|
||||
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
|
||||
# we can have the preprocessor correctly recognise both 0x0 and 0
|
||||
# meaning "turn it off".
|
||||
-obj-y += boot_mode.o
|
||||
+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
|
||||
+
|
||||
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
|
||||
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
|
||||
obj-$(CONFIG_MISC_INIT_R) += misc.o
|
||||
endif
|
||||
--- a/arch/arm/mach-rockchip/boot_mode.c
|
||||
+++ b/arch/arm/mach-rockchip/boot_mode.c
|
||||
@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void)
|
||||
ret = -ENODEV;
|
||||
uclass_foreach_dev(dev, uc) {
|
||||
if (!strncmp(dev->name, "saradc", 6)) {
|
||||
- ret = adc_channel_single_shot(dev->name, 1, &val);
|
||||
+ ret = adc_channel_single_shot(dev->name, 0, &val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -89,6 +89,7 @@ int setup_boot_mode(void)
|
||||
boot_mode = readl(reg);
|
||||
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
|
||||
|
||||
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
|
||||
/* Clear boot mode */
|
||||
writel(BOOT_NORMAL, reg);
|
||||
|
||||
@@ -102,6 +103,7 @@ int setup_boot_mode(void)
|
||||
env_set("preboot", "setenv preboot; ums mmc 0");
|
||||
break;
|
||||
}
|
||||
+#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
|
||||
@@ -9,19 +9,30 @@
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
+#include <asm/arch-rockchip/boot_mode.h>
|
||||
#include <asm/arch-rockchip/grf_rk3568.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <dt-bindings/clock/rk3568-cru.h>
|
||||
|
||||
#define PMUGRF_BASE 0xfdc20000
|
||||
#define GRF_BASE 0xfdc60000
|
||||
+#define GRF_GPIO1B_IOMUX_H 0x0c
|
||||
+#define GRF_GPIO1C_IOMUX_L 0x10
|
||||
+#define GRF_GPIO1C_IOMUX_H 0x14
|
||||
+#define GRF_GPIO1D_IOMUX_L 0x18
|
||||
+#define GRF_GPIO1D_IOMUX_H 0x1c
|
||||
+#define GRF_GPIO2A_IOMUX_L 0x20
|
||||
#define GRF_GPIO1B_DS_2 0x218
|
||||
#define GRF_GPIO1B_DS_3 0x21c
|
||||
#define GRF_GPIO1C_DS_0 0x220
|
||||
#define GRF_GPIO1C_DS_1 0x224
|
||||
#define GRF_GPIO1C_DS_2 0x228
|
||||
#define GRF_GPIO1C_DS_3 0x22c
|
||||
-#define SGRF_BASE 0xFDD18000
|
||||
+#define GRF_GPIO1D_DS_0 0x230
|
||||
+#define GRF_GPIO1D_DS_1 0x234
|
||||
+#define GRF_GPIO1D_DS_2 0x238
|
||||
+#define SGRF_BASE 0xfdd18000
|
||||
+#define SGRF_SOC_CON3 0x0c
|
||||
#define SGRF_SOC_CON4 0x10
|
||||
#define EMMC_HPROT_SECURE_CTRL 0x03
|
||||
#define SDMMC0_HPROT_SECURE_CTRL 0x01
|
||||
@@ -133,6 +144,24 @@ int arch_cpu_init(void)
|
||||
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
|
||||
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
|
||||
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
|
||||
+
|
||||
+ /* emmc, sfc, and sdmmc iomux */
|
||||
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
|
||||
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
|
||||
+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
|
||||
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
|
||||
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H);
|
||||
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L);
|
||||
+
|
||||
+ /* set the fspi d0~3 cs0 to level 2 */
|
||||
+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
|
||||
+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
|
||||
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
|
||||
+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
|
||||
+
|
||||
+ /* Set the fspi to secure */
|
||||
+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
|
||||
+
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_SPL_BUILD
|
||||
+
|
||||
+void __weak led_setup(void)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
+void spl_board_init(void)
|
||||
+{
|
||||
+ led_setup();
|
||||
+
|
||||
+#if defined(SPL_DM_REGULATOR)
|
||||
+ /*
|
||||
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
|
||||
+ * BIOS_ENABLE) signal is done through a always-on regulator).
|
||||
+ */
|
||||
+ if (regulators_enable_boot_on(false))
|
||||
+ debug("%s: Cannot enable boot on regulator\n", __func__);
|
||||
+#endif
|
||||
+
|
||||
+ setup_boot_mode();
|
||||
+}
|
||||
+#endif
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
--- a/configs/rock-3a-rk3568_defconfig
|
||||
+++ b/configs/rock-3a-rk3568_defconfig
|
||||
@@ -39,6 +39,8 @@
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
@@ -47,6 +49,8 @@
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
@@ -61,7 +65,11 @@
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
@@ -69,5 +77,11 @@
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
-# CONFIG_BINMAN_FDT is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
--- a/tools/Makefile
|
||||
+++ b/tools/Makefile
|
||||
@@ -113,7 +113,6 @@ dumpimage-mkimage-objs := aisimage.o \
|
||||
imximage.o \
|
||||
imx8image.o \
|
||||
imx8mimage.o \
|
||||
- kwbimage.o \
|
||||
lib/md5.o \
|
||||
lpc32xximage.o \
|
||||
mxsimage.o \
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -2000,26 +2000,7 @@ endif
|
||||
# Check dtc and pylibfdt, if DTC is provided, else build them
|
||||
PHONY += scripts_dtc
|
||||
scripts_dtc: scripts_basic
|
||||
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
|
||||
- $(MAKE) $(build)=scripts/dtc; \
|
||||
- else \
|
||||
- if ! $(DTC) -v >/dev/null; then \
|
||||
- echo '*** Failed to check dtc version: $(DTC)'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
|
||||
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
|
||||
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
|
||||
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
|
||||
- false; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi
|
||||
+ $(MAKE) $(build)=scripts/dtc
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
quiet_cmd_cpp_lds = LDS $@
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
--- a/tools/image-host.c
|
||||
+++ b/tools/image-host.c
|
||||
@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
|
||||
* 2) get public key (X509_get_pubkey)
|
||||
* 3) provide der format (d2i_RSAPublicKey)
|
||||
*/
|
||||
+#ifdef CONFIG_TOOLS_LIBCRYPTO
|
||||
static int read_pub_key(const char *keydir, const void *name,
|
||||
unsigned char **pubkey, int *pubkey_len)
|
||||
{
|
||||
@@ -1178,6 +1179,13 @@ err_cert:
|
||||
fclose(f);
|
||||
return ret;
|
||||
}
|
||||
+#else
|
||||
+static int read_pub_key(const char *keydir, const void *name,
|
||||
+ unsigned char **pubkey, int *pubkey_len)
|
||||
+{
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+#endif
|
||||
|
||||
int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
|
||||
{
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
From 734b9d9e33919efbec63b1bfe48f25ce16dbd59a Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Fri, 17 Mar 2023 19:16:45 +0000
|
||||
Subject: [PATCH] clk: scmi: Add Kconfig option for SPL
|
||||
|
||||
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
|
||||
enabled and SPL_FIRMWARE disabled result in the following error.
|
||||
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
|
||||
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
|
||||
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
|
||||
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
|
||||
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
|
||||
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
|
||||
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
|
||||
|
||||
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Link: https://patchwork.ozlabs.org/project/uboot/patch/20230317191638.2558279-2-jonas@kwiboo.se/
|
||||
---
|
||||
drivers/clk/Kconfig | 8 ++++++++
|
||||
drivers/clk/Makefile | 2 +-
|
||||
drivers/firmware/scmi/scmi_agent-uclass.c | 2 +-
|
||||
3 files changed, 10 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/Kconfig
|
||||
+++ b/drivers/clk/Kconfig
|
||||
@@ -166,6 +166,14 @@ config CLK_SCMI
|
||||
by a SCMI agent based on SCMI clock protocol communication
|
||||
with a SCMI server.
|
||||
|
||||
+config SPL_CLK_SCMI
|
||||
+ bool "Enable SCMI clock driver in SPL"
|
||||
+ depends on SCMI_FIRMWARE && SPL_FIRMWARE
|
||||
+ help
|
||||
+ Enable this option if you want to support clock devices exposed
|
||||
+ by a SCMI agent based on SCMI clock protocol communication
|
||||
+ with a SCMI server in SPL.
|
||||
+
|
||||
config CLK_HSDK
|
||||
bool "Enable cgu clock driver for HSDK boards"
|
||||
depends on CLK && TARGET_HSDK
|
||||
--- a/drivers/clk/Makefile
|
||||
+++ b/drivers/clk/Makefile
|
||||
@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/
|
||||
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
|
||||
obj-$(CONFIG_CLK_OWL) += owl/
|
||||
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
||||
-obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
|
||||
+obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
|
||||
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
||||
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
||||
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
|
||||
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
|
||||
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
|
||||
@@ -75,7 +75,7 @@ static int scmi_bind_protocols(struct udevice *dev)
|
||||
name = ofnode_get_name(node);
|
||||
switch (protocol_id) {
|
||||
case SCMI_PROTOCOL_ID_CLOCK:
|
||||
- if (IS_ENABLED(CONFIG_CLK_SCMI))
|
||||
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
|
||||
drv = DM_DRIVER_GET(scmi_clock);
|
||||
break;
|
||||
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
From 7db635cf638dfad08a50e26a6d02e1b6e7a9d7c5 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 18 Mar 2023 23:30:42 +0000
|
||||
Subject: [PATCH] pinctrl: rockchip: Fix IO mux selection on RK3568
|
||||
|
||||
IO mux selection is not working correctly for all pins. Sync mux route
|
||||
data from linux to add any missing and update wrong trigger pins to fix
|
||||
this. Also apply the pull-up fix needed for GPIO0 D3-D6.
|
||||
|
||||
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jonas@kwiboo.se/
|
||||
---
|
||||
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++----------
|
||||
1 file changed, 38 insertions(+), 28 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
@@ -13,6 +13,12 @@
|
||||
#include "pinctrl-rockchip.h"
|
||||
|
||||
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
|
||||
@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
|
||||
@@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
|
||||
@@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
|
||||
@@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
|
||||
@@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
|
||||
+ * where that pull up value becomes 3.
|
||||
+ */
|
||||
+ if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
|
||||
+ if (ret == 1)
|
||||
+ ret = 3;
|
||||
+ }
|
||||
+
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001
|
||||
From: Marty Jones <mj8263788@gmail.com>
|
||||
Date: Sun, 17 Jan 2021 15:26:09 -0500
|
||||
Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT
|
||||
|
||||
On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3
|
||||
CONFIG_USE_PREBOOT was enabled on the RockPro64.
|
||||
|
||||
When the board is booting, U-Boot hangs as soon as it disables the USB
|
||||
controller. This is a workaround until a final solution is deployed
|
||||
upstream.
|
||||
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
---
|
||||
configs/rockpro64-rk3399_defconfig | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/configs/rockpro64-rk3399_defconfig
|
||||
+++ b/configs/rockpro64-rk3399_defconfig
|
||||
@@ -21,7 +21,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
-CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
From c13b8e588bd2da6381a6d337df51acb2a61f03b8 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 21 Mar 2023 21:43:07 +0000
|
||||
Subject: [PATCH] rockchip: rk35xx: Fix boot with a large fdt blob
|
||||
|
||||
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
|
||||
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
|
||||
when it fails to parse the fdt blob being passed as the platform param.
|
||||
An issue that was fixed in atf v2.4.
|
||||
|
||||
The vendor TF-A seem to suffer from a similar issue, and this prevents
|
||||
booting when fdt blob is large enough to trigger this condition.
|
||||
|
||||
Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
|
||||
NULL pointer instead of the fdt blob as the platform param.
|
||||
|
||||
This fixes booting Radxa ROCK 3A after recent sync of device tree.
|
||||
|
||||
Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://patchwork.ozlabs.org/project/uboot/patch/20230321214301.2590326-4-jonas@kwiboo.se/
|
||||
---
|
||||
arch/arm/mach-rockchip/Kconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm/mach-rockchip/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/Kconfig
|
||||
@@ -288,6 +288,7 @@ config ROCKCHIP_RK3568
|
||||
select BOARD_LATE_INIT
|
||||
select DM_REGULATOR_FIXED
|
||||
select DM_RESET
|
||||
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply ROCKCHIP_OTP
|
||||
imply MISC_INIT_R
|
||||
@@ -309,6 +310,7 @@ config ROCKCHIP_RK3588
|
||||
select REGMAP
|
||||
select SYSCON
|
||||
select BOARD_LATE_INIT
|
||||
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply ROCKCHIP_OTP
|
||||
imply MISC_INIT_R
|
||||
|
|
@ -1,740 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399-ficus.dtb \
|
||||
rk3399-firefly.dtb \
|
||||
rk3399-gru-bob.dtb \
|
||||
+ rk3399-guangmiao-g4c.dtb \
|
||||
rk3399-gru-kevin.dtb \
|
||||
rk3399-khadas-edge.dtb \
|
||||
rk3399-khadas-edge-captain.dtb \
|
||||
--- /dev/null
|
||||
+++ b/configs/guangmiao-g4c-rk3399_defconfig
|
||||
@@ -0,0 +1,57 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c"
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM_RK3399_LPDDR4=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-guangmiao-g4c-u-boot.dtsi
|
||||
@@ -0,0 +1,18 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "rk3399-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-lpddr4-100.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+};
|
||||
+
|
||||
+&vdd_log {
|
||||
+ regulator-init-microvolt = <950000>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-guangmiao-g4c.dts
|
||||
@@ -0,0 +1,646 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/input/linux-event-codes.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "SHAREVDI GuangMiao G4C";
|
||||
+ compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
|
||||
+
|
||||
+ /delete-node/ display-subsystem;
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_0v9: vcc-0v9 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-name = "vcc_0v9";
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host0: vcc5v0-host0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc5v0_host0";
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 25000 1>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ autorepeat;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ reset {
|
||||
+ debounce-interval = <100>;
|
||||
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ lan_led: led-lan {
|
||||
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
+ };
|
||||
+
|
||||
+ status_led: led-status {
|
||||
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:status";
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-wan {
|
||||
+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ clock_in_out = "input";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc3v3_s3>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ interrupt-parent = <&gpio3>;
|
||||
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <30000>;
|
||||
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ i2c-scl-rising-time-ns = <160>;
|
||||
+ i2c-scl-falling-time-ns = <30>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cpu_b_sleep>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gpu_sleep>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
|
||||
+ #clock-cells = <1>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+ vcc7-supply = <&vcc_sys>;
|
||||
+ vcc8-supply = <&vcc_3v0>;
|
||||
+ vcc9-supply = <&vcc_sys>;
|
||||
+ vcc10-supply = <&vcc_sys>;
|
||||
+ vcc11-supply = <&vcc_sys>;
|
||||
+ vcc12-supply = <&vcc_sys>;
|
||||
+ vddio-supply = <&vcc_3v0>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_vldo1: LDO_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_vldo1";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_vldo2: LDO_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_vldo2";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v0_sd: LDO_REG5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-name = "vcc3v0_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1500000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_codec: LDO_REG7 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcca1v8_codec";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: SWITCH_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ i2c-scl-rising-time-ns = <450>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ bt656-supply = <&vcc_1v8>;
|
||||
+ audio-supply = <&vcca1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie_phy {
|
||||
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ max-link-speed = <1>;
|
||||
+ num-lanes = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||
+ vpcie0v9-supply = <&vcc_0v9>;
|
||||
+ vpcie1v8-supply = <&vcca_1v8>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac {
|
||||
+ phy_intb: phy-intb {
|
||||
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ phy_pmeb: phy-pmeb {
|
||||
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ phy_rstb: phy-rstb {
|
||||
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ cpu_b_sleep: cpu-b-sleep {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ gpu_sleep: gpu-sleep {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio {
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ /* external pullup to VCC1V8_PMUPLL */
|
||||
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdmmc {
|
||||
+ sdmmc0_det_l: sdmmc0-det-l {
|
||||
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmu1830-supply = <&vcc_3v0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ pinctrl-names = "active";
|
||||
+ pinctrl-0 = <&pwm2_pin_pull_down>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
|
||||
+ vqmmc-supply = <&vcc_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_host0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_host0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
|
@ -1,157 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
|
||||
rk3328-evb.dtb \
|
||||
rk3328-nanopi-r2s.dtb \
|
||||
+ rk3328-orangepi-r1-plus.dtb \
|
||||
rk3328-roc-cc.dtb \
|
||||
rk3328-rock64.dtb \
|
||||
rk3328-rock-pi-e.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
|
||||
@@ -0,0 +1,1 @@
|
||||
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
|
||||
@@ -0,0 +1,25 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus";
|
||||
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+};
|
||||
+
|
||||
+&sys_led_pin {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_SYS_MMC_ENV_DEV=1
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,152 +0,0 @@
|
|||
From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001
|
||||
From: baiywt <baiywt_gj@163.com>
|
||||
Date: Wed, 24 Nov 2021 19:59:38 +0800
|
||||
Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
|
||||
---
|
||||
arch/arm/dts/Makefile | 1 +
|
||||
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++
|
||||
configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++
|
||||
3 files changed, 106 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
|
||||
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
|
||||
rk3328-evb.dtb \
|
||||
rk3328-nanopi-r2s.dtb \
|
||||
rk3328-orangepi-r1-plus.dtb \
|
||||
+ rk3328-orangepi-r1-plus-lts.dtb \
|
||||
rk3328-roc-cc.dtb \
|
||||
rk3328-rock64.dtb \
|
||||
rk3328-rock-pi-e.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
|
||||
@@ -0,0 +1,1 @@
|
||||
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,7 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_SYS_MMC_ENV_DEV=1
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
||||
index d3e89ca3ba..d5f64ac432 100644
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
|
||||
rk3328-evb.dtb \
|
||||
+ rk3328-nanopi-r2c.dtb \
|
||||
rk3328-nanopi-r2s.dtb \
|
||||
rk3328-orangepi-r1-plus.dtb \
|
||||
rk3328-roc-cc.dtb \
|
||||
diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
|
||||
new file mode 100644
|
||||
index 0000000000..c2e86d0f0e
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
|
||||
@@ -0,0 +1,7 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
|
||||
+ * (C) Copyright 2021 Tianling Shen
|
||||
+ */
|
||||
+
|
||||
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
|
||||
diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts
|
||||
new file mode 100644
|
||||
index 0000000000..adf91a0306
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,47 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-id0000.011a",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "nanopi-r2c:green:lan";
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ label = "nanopi-r2c:red:sys";
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "nanopi-r2c:green:wan";
|
||||
+};
|
||||
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
|
||||
new file mode 100644
|
||||
index 0000000000..7bc7a3274f
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r2c-rk3328_defconfig
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_SYS_MMC_ENV_DEV=1
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,121 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -157,6 +157,7 @@
|
||||
rk3399-nanopi-m4b.dtb \
|
||||
rk3399-nanopi-neo4.dtb \
|
||||
rk3399-nanopi-r4s.dtb \
|
||||
+ rk3399-nanopi-r4se.dtb \
|
||||
rk3399-orangepi.dtb \
|
||||
rk3399-pinebook-pro.dtb \
|
||||
rk3399-puma-haikou.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-nanopi-r4se.dts
|
||||
@@ -0,0 +1,32 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * FriendlyElec NanoPC-T4 board device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2018 Collabora Ltd.
|
||||
+ *
|
||||
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-nanopi-r4s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R4SE";
|
||||
+ compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&sdmmc {
|
||||
+ pinctrl-0 = <&sdmmc_cd>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r4se-rk3399_defconfig
|
||||
@@ -0,0 +1,73 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x2e000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
--- /dev/null
|
||||
+++ b/configs/rongpin-king3399-rk3399_defconfig
|
||||
@@ -0,0 +1,73 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x2e000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,793 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399-rock-pi-4b.dtb \
|
||||
rk3399-rock-pi-4c.dtb \
|
||||
rk3399-rock960.dtb \
|
||||
+ rk3399-mpc1903.dtb \
|
||||
rk3399-rockpro64.dtb \
|
||||
rk3399pro-rock-pi-n10.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-mpc1903.dts
|
||||
@@ -0,0 +1,688 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/input/linux-event-codes.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rocktech MPC1903";
|
||||
+ compatible = "rocktech,mpc1903", "rockchip,rk3399";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vcc12v_dcin: dc-12v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc12v_dcin";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc12v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_lan: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_lan";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 25000 1>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+
|
||||
+ status_led: led-status-led {
|
||||
+ label = "status_led";
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hub_control {
|
||||
+ compatible = "rocktech,hub-control";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hub_pwr>;
|
||||
+ hub-pwr-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-supply = <&vcc_lan>;
|
||||
+ phy-mode = "rmgii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ ddc-i2c-bus = <&i2c3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_i2c_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ i2c-scl-rising-time-ns = <168>;
|
||||
+ i2c-scl-falling-time-ns = <4>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk808-clkout2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc5v0_sys>;
|
||||
+ vcc2-supply = <&vcc5v0_sys>;
|
||||
+ vcc3-supply = <&vcc5v0_sys>;
|
||||
+ vcc4-supply = <&vcc5v0_sys>;
|
||||
+ vcc6-supply = <&vcc5v0_sys>;
|
||||
+ vcc7-supply = <&vcc5v0_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc5v0_sys>;
|
||||
+ vcc10-supply = <&vcc5v0_sys>;
|
||||
+ vcc11-supply = <&vcc5v0_sys>;
|
||||
+ vcc12-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc_3v0>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gen_1v8: LDO_REG1 {
|
||||
+ regulator-name = "gen_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gen_3v0: LDO_REG2 {
|
||||
+ regulator-name = "gen_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vcc1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca3v0_codec: LDO_REG5 {
|
||||
+ regulator-name = "vcca3v0_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_codec: LDO_REG7 {
|
||||
+ regulator-name = "vcc1v8_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: SWITCH_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vsel1_pin>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vsel2_pin>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc: pcf85263@51 {
|
||||
+ compatible = "nxp,pcf85263";
|
||||
+ reg = <0x51>;
|
||||
+ pinctrl-0 = <&rtc_int>;
|
||||
+ rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ i2c-scl-rising-time-ns = <300>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ i2c-scl-rising-time-ns = <600>;
|
||||
+ i2c-scl-falling-time-ns = <20>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c6 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ rockchip,i2s-broken-burst-len;
|
||||
+ rockchip,playback-channels = <8>;
|
||||
+ rockchip,capture-channels = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ rockchip,bclk-fs = <128>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bt656-supply = <&vcc_3v0>;
|
||||
+ audio-supply = <&vcc1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ pmu1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ bt {
|
||||
+ uart0_gpios: uart0-gpios {
|
||||
+ rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vsel1_pin: vsel1-pin {
|
||||
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ vsel2_pin: vsel2-pin {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2 {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ hub_pwr: hub-pwr {
|
||||
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc {
|
||||
+ rtc_int: rtc-int {
|
||||
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ led {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ power_key: power-key {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ status = "okay";
|
||||
+ vref-supply = <&vcc_1v8>;
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ bus-width = <4>;
|
||||
+ clock-frequency = <50000000>;
|
||||
+ cap-sdio-irq;
|
||||
+ cap-sd-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ clock-freq-min-max = <400000 150000000>;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ supports-sd;
|
||||
+ disable-wp;
|
||||
+ num-slots = <1>;
|
||||
+ vqmmc-supply = <&vcc_sdio>;
|
||||
+ max-frequency = <150000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ mmc-hs400-enhanced-strobe;
|
||||
+ non-removable;
|
||||
+ supports-emmc;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+ rockchip,hw-tshut-temp = <120000>;
|
||||
+ /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-mpc1903-u-boot.dtsi
|
||||
@@ -0,0 +1,14 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "rk3399-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/rocktech-mpc1903-rk3399_defconfig
|
||||
@@ -0,0 +1,72 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-mpc1903"
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-mpc1903.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x2e000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,933 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -145,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399-gru-bob.dtb \
|
||||
rk3399-guangmiao-g4c.dtb \
|
||||
rk3399-gru-kevin.dtb \
|
||||
+ rk3399-h3399pc.dtb \
|
||||
rk3399-khadas-edge.dtb \
|
||||
rk3399-khadas-edge-captain.dtb \
|
||||
rk3399-khadas-edge-v.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-h3399pc.dts
|
||||
@@ -0,0 +1,828 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/input/linux-event-codes.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "SHAREVDI H3399PC";
|
||||
+ compatible = "sharevdi,h3399pc", "rockchip,rk3399";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdio0;
|
||||
+ mmc1 = &sdmmc;
|
||||
+ mmc2 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ autorepeat;
|
||||
+
|
||||
+ power {
|
||||
+ debounce-interval = <100>;
|
||||
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
+ label = "GPIO Key Power";
|
||||
+ linux,code = <KEY_POWER>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
|
||||
+
|
||||
+ work_led: led-0 {
|
||||
+ label = "work";
|
||||
+ default-state = "on";
|
||||
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ diy_led: led-1 {
|
||||
+ label = "diy";
|
||||
+ default-state = "off";
|
||||
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sound: sound {
|
||||
+ compatible = "audio-graph-card";
|
||||
+ label = "Analog";
|
||||
+ dais = <&i2s0_p0>;
|
||||
+ };
|
||||
+
|
||||
+ sound-dit {
|
||||
+ compatible = "audio-graph-card";
|
||||
+ label = "SPDIF";
|
||||
+ dais = <&spdif_p0>;
|
||||
+ };
|
||||
+
|
||||
+ spdif-dit {
|
||||
+ compatible = "linux,spdif-dit";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+
|
||||
+ port {
|
||||
+ dit_p0_0: endpoint {
|
||||
+ remote-endpoint = <&spdif_p0_0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+
|
||||
+ /*
|
||||
+ * On the module itself this is one of these (depending
|
||||
+ * on the actual card populated):
|
||||
+ * - SDIO_RESET_L_WL_REG_ON
|
||||
+ * - PDN (power down when low)
|
||||
+ */
|
||||
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ sound-dit {
|
||||
+ compatible = "audio-graph-card";
|
||||
+ label = "SPDIF";
|
||||
+ dais = <&spdif_p0>;
|
||||
+ };
|
||||
+
|
||||
+ spdif-dit {
|
||||
+ compatible = "linux,spdif-dit";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+
|
||||
+ port {
|
||||
+ dit_p0_0: endpoint {
|
||||
+ remote-endpoint = <&spdif_p0_0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* switched by pmic_sleep */
|
||||
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc1v8_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8>;
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_sys: vcc1v8-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc1v8_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_pwr_en>;
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_3g: vcc3v3-3g-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_3g_drv>;
|
||||
+ regulator-name = "vcc3v3_3g";
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_hub: vcc5v0-hub-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_hub_en>;
|
||||
+ regulator-name = "vcc5v0_hub";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 25000 1>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1100000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_phy: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_phy";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-supply = <&vcc_lan>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ ddc-i2c-bus = <&i2c3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_cec>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ i2c-scl-rising-time-ns = <168>;
|
||||
+ i2c-scl-falling-time-ns = <4>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk808-clkout2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ vcc10-supply = <&vcc3v3_sys>;
|
||||
+ vcc11-supply = <&vcc3v3_sys>;
|
||||
+ vcc12-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc1v8_pmu>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc2v8_dvp: LDO_REG1 {
|
||||
+ regulator-name = "vcc2v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2800000>;
|
||||
+ regulator-max-microvolt = <2800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+ vcc1v8_dvp: LDO_REG2 {
|
||||
+ regulator-name = "vcc1v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vcc1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca3v0_codec: LDO_REG5 {
|
||||
+ regulator-name = "vcca3v0_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1500000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_codec: LDO_REG7 {
|
||||
+ regulator-name = "vcca1v8_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <0>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ i2c-scl-rising-time-ns = <300>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ es8316: codec@11 {
|
||||
+ compatible = "everest,es8316";
|
||||
+ reg = <0x11>;
|
||||
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
+ clock-names = "mclk";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
+ spk-con-gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ hp-det-gpio = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
+
|
||||
+ port {
|
||||
+ es8316_p0_0: endpoint {
|
||||
+ remote-endpoint = <&i2s0_p0_0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ rockchip,playback-channels = <8>;
|
||||
+ rockchip,capture-channels = <8>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ i2s0_p0: port {
|
||||
+ i2s0_p0_0: endpoint {
|
||||
+ dai-format = "i2s";
|
||||
+ mclk-fs = <256>;
|
||||
+ remote-endpoint = <&es8316_p0_0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s1 {
|
||||
+ rockchip,playback-channels = <2>;
|
||||
+ rockchip,capture-channels = <2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bt656-supply = <&vcc1v8_dvp>;
|
||||
+ audio-supply = <&vcca1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pcie_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ num-lanes = <4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
+ status = "okay";
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmu1830-supply = <&vcc_3v0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ i2s0 {
|
||||
+ i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
+ rockchip,pins = <4 RK_PB4 1 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ work_led_pin: work-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ diy_led_pin: diy-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_pwr_en: pcie-pwr-en {
|
||||
+ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ pcie_3g_drv: pcie-3g-drv {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vsel1_pin: vsel1-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ vsel2_pin: vsel2-pin {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2 {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host3_en: vcc5v0-host3-en {
|
||||
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_hub_en: vcc5v0-hub-en {
|
||||
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca1v8_s3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ /* WiFi & BT combo module Ampak AP6356S */
|
||||
+ bus-width = <4>;
|
||||
+ cap-sdio-irq;
|
||||
+ cap-sd-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+
|
||||
+ /* Power supply */
|
||||
+ vqmmc-supply = <&vcc1v8_s3>; /* IO line */
|
||||
+ vmmc-supply = <&vcc_sdio>; /* card's power */
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ mmc-hs400-enhanced-strobe;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spdif {
|
||||
+ pinctrl-0 = <&spdif_bus_1>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ spdif_p0: port {
|
||||
+ spdif_p0_0: endpoint {
|
||||
+ remote-endpoint = <&dit_p0_0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "otg";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-h3399pc-u-boot.dtsi
|
||||
@@ -0,0 +1,14 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "rk3399-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-ddr3-1600.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/sharevdi-h3399pc-rk3399_defconfig
|
||||
@@ -0,0 +1,72 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-h3399pc"
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-h3399pc.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x2e000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,782 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -139,6 +139,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
|
||||
rk3368-px5-evb.dtb \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
+ rk3399-dlfr100.dtb \
|
||||
rk3399-evb.dtb \
|
||||
rk3399-ficus.dtb \
|
||||
rk3399-firefly.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-dlfr100.dts
|
||||
@@ -0,0 +1,668 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/pwm/pwm.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Dilusense DLFR100";
|
||||
+ compatible = "dilusense,dlfr100", "rockchip,rk3399";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ };
|
||||
+
|
||||
+ vcc_phy: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_phy";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: vcc-sd {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc_sd_h>;
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+
|
||||
+ adc-keys {
|
||||
+ compatible = "adc-keys";
|
||||
+ io-channels = <&saradc 1>;
|
||||
+ io-channel-names = "buttons";
|
||||
+ keyup-threshold-microvolt = <1800000>;
|
||||
+ poll-interval = <100>;
|
||||
+
|
||||
+ button-up {
|
||||
+ label = "Volume Up";
|
||||
+ linux,code = <KEY_VOLUMEUP>;
|
||||
+ press-threshold-microvolt = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ button-down {
|
||||
+ label = "Volume Down";
|
||||
+ linux,code = <KEY_VOLUMEDOWN>;
|
||||
+ press-threshold-microvolt = <300000>;
|
||||
+ };
|
||||
+
|
||||
+ back {
|
||||
+ label = "Back";
|
||||
+ linux,code = <KEY_BACK>;
|
||||
+ press-threshold-microvolt = <985000>;
|
||||
+ };
|
||||
+
|
||||
+ menu {
|
||||
+ label = "Menu";
|
||||
+ linux,code = <KEY_MENU>;
|
||||
+ press-threshold-microvolt = <0x1314000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ autorepeat;
|
||||
+ pinctrl-0 = <&pwr_btn>;
|
||||
+
|
||||
+ power {
|
||||
+ debounce-interval = <100>;
|
||||
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
+ label = "GPIO Key Power";
|
||||
+ linux,code = <KEY_POWER>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-supply = <&vcc_phy>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ vcc10-supply = <&vcc3v3_sys>;
|
||||
+ vcc11-supply = <&vcc3v3_sys>;
|
||||
+ vcc12-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc1v8_pmu>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_dvp: LDO_REG1 {
|
||||
+ regulator-name = "vcc1v8_dvp";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v0_tp: LDO_REG2 {
|
||||
+ regulator-name = "vcc3v0_tp";
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vcc1v8_pmu";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca3v0_codec: LDO_REG5 {
|
||||
+ regulator-name = "vcca3v0_codec";
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1500000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_codec: LDO_REG7 {
|
||||
+ regulator-name = "vcca1v8_codec";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ pinctrl-0 = <&vsel1_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-state = <3>;
|
||||
+ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ pinctrl-0 = <&vsel2_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-state = <3>;
|
||||
+ vsel-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ isl1208@6f {
|
||||
+ compatible = "isil,isl1208";
|
||||
+ reg = <0x6f>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ i2c-scl-rising-time-ns = <300>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ rockchip,playback-channels = <8>;
|
||||
+ rockchip,capture-channels = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bt656-supply = <&vcc_3v0>;
|
||||
+ audio-supply = <&vcca1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ bus-width = <4>;
|
||||
+ disable-wp;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ clock-frequency = <50000000>;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-mmc-highspeed;
|
||||
+ clock-frequency = <150000000>;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ mmc-hs400-enhanced-strobe;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ max-link-speed = <1>;
|
||||
+ num-lanes = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ buttons {
|
||||
+ pwr_btn: pwr-btn {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ i2s0 {
|
||||
+ i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
+ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vsel1_pin: vsel1-pin {
|
||||
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ vsel2_pin: vsel2-pin {
|
||||
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ pmic_dvs2:pmic-dvs2 {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2 {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd {
|
||||
+ vcc_sd_h: vcc-sd-h {
|
||||
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-dlfr100-u-boot.dtsi
|
||||
@@ -0,0 +1,23 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "rk3399-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/dilusense-dlfr100-rk3399_defconfig
|
||||
@@ -0,0 +1,72 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-dlfr100"
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-dlfr100.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x2e000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,399 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts
|
||||
@@ -0,0 +1,268 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "EZPRO Mrkaio M68S";
|
||||
+ compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/mrkaio-m68s-rk3568_defconfig
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,408 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-opc-h68k.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-opc-h68k.dts
|
||||
@@ -0,0 +1,277 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "HINLINK OPC-H68K Board";
|
||||
+ compatible = "hinlink,opc-h68k", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-names = "mclk";
|
||||
+ clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ codec {
|
||||
+ mic-in-differential;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/opc-h68k-rk3568_defconfig
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-r66s.dtb \
|
||||
rk3568-opc-h68k.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-r66s-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-r66s.dts
|
||||
@@ -0,0 +1,2 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+#include "rk3568-evb.dts"
|
||||
--- /dev/null
|
||||
+++ b/configs/r66s-rk3568_defconfig
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001
|
||||
From: huangjf <hjf@t-chip.com.cn>
|
||||
Date: Thu, 7 Apr 2022 16:22:56 +0800
|
||||
Subject: [PATCH] rockchip: rk3568: Add support for Station P2
|
||||
|
||||
---
|
||||
configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++
|
||||
1 file changed, 59 insertions(+)
|
||||
create mode 100644 configs/station-p2-rk3568_defconfig
|
||||
|
||||
--- /dev/null
|
||||
+++ b/configs/station-p2-rk3568_defconfig
|
||||
@@ -0,0 +1,87 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3568-opc-h68k.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
+ rk3568-photonicat.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-photonicat-u-boot.dtsi
|
||||
@@ -0,0 +1,33 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gpio0 {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vcc3v3_sd {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-photonicat.dts
|
||||
@@ -0,0 +1,54 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Ariaboard Photonicat";
|
||||
+ compatible = "ariaboard,photonicat", "rockchip,rk3568";
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: vcc3v3_sd {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc_sd_h>;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ vcc_sd {
|
||||
+ vcc_sd_h: vcc-sd-h {
|
||||
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ max-frequency = <52000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/photonicat-rk3568_defconfig
|
||||
@@ -0,0 +1,94 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-photonicat"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-photonicat.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_IO_VOLTAGE=y
|
||||
+CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -177,7 +177,8 @@ rk3568-evb.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3568-photonicat.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
- rk3568-rock-3a.dtb
|
||||
+ rk3568-rock-3a.dtb \
|
||||
+ rk3568-radxa-e25.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
|
||||
rk3588-edgeble-neu6a-io.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-radxa-e25.dts
|
||||
@@ -0,0 +1,8 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa E25";
|
||||
+ compatible = "radxa,e25", "rockchip,rk3568";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/radxa-e25-rk3568_defconfig
|
||||
@@ -0,0 +1,89 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
Loading…
Add table
Add a link
Reference in a new issue