fix6018

root/target/linux/ipq60xx/base-files/etc/board.d/02_network

@@ -14,6 +14,7 @@ ipq60xx_setup_interfaces()
 	*"GL-AX1800"*)
         ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4" "eth0"
         ;;
+	pangu,l6018|\
 	wf,hr6001)
         ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3" "eth4"
         ;;

root/target/linux/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata

@@ -1,27 +0,0 @@
-#!/bin/sh
-
-[ -e /lib/firmware/$FIRMWARE ] && exit 0
-
-. /lib/functions/caldata.sh
-
-board=$(board_name)
-
-case "$FIRMWARE" in
-"ath10k/cal-pci-0000:01:00.0.bin")
-	case "$board" in
-	xiaomi,ax3600)
-		caldata_extract "0:art" 0x33000 0x844
-		;;
-	esac
-	;;
-"ath10k/cal-pci-0001:01:00.0.bin")
-	case "$board" in
-	xiaomi,ax9000)
-		caldata_extract "0:art" 0x4d000 0x844
-		;;
-	esac
-	;;
-*)
-	exit 1
-	;;
-esac

root/target/linux/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata

@@ -22,7 +22,7 @@ case "$FIRMWARE" in
 	;;
 "ath11k/IPQ6018/hw1.0/caldata.bin")
 	case "$board" in
-	wf,hr6001)
+	panguu,l6018)
 		caldata_extract "0:ART" 0x1000 0x20000
 		;;
 	esac

root/target/linux/ipq60xx/base-files/lib/upgrade/platform.sh

@@ -10,9 +10,9 @@ platform_check_image() {
 
 platform_do_upgrade() {
 	case "$(board_name)" in
-	*GL-AX1800* |\
+	pangu,l6018|\
 	wf,hr6001)
-		CI_UBIPART="rootfs"
+	CI_UBIPART="rootfs"
 		nand_do_upgrade "$1"
 		;;
 	*)

root/target/linux/ipq60xx/config-5.10

@@ -59,6 +59,7 @@ CONFIG_ARM_GIC_V3_ITS=y
 CONFIG_ARM_GIC_V3_ITS_PCI=y
 CONFIG_ARM_PSCI_CPUIDLE=y
 CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_QCOM_CPUFREQ=y
 # CONFIG_ARM_QCOM_CPUFREQ_HW is not set
 # CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
 CONFIG_ARM_SMCCC_SOC_ID=y
@@ -194,7 +195,7 @@ CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_IPQ_APSS_6018=y
 # CONFIG_IPQ_APSS_8074 is not set
-# CONFIG_IPQ_APSS_PLL is not set
+CONFIG_IPQ_APSS_PLL=y
 # CONFIG_IPQ_GCC_4019 is not set
 CONFIG_IPQ_GCC_6018=y
 # CONFIG_IPQ_GCC_806X is not set
@@ -223,8 +224,8 @@ CONFIG_MDIO_IPQ4019=y
 # CONFIG_MDM_LCC_9615 is not set
 CONFIG_MEMFD_CREATE=y
 # CONFIG_MFD_HI6421_SPMI is not set
-# CONFIG_MFD_QCOM_RPM is not set
-CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_QCOM_RPM=y
+# CONFIG_MFD_SPMI_PMIC is not set
 CONFIG_MFD_SYSCON=y
 CONFIG_MHI_BUS=y
 CONFIG_MHI_BUS_DEBUG=y
@@ -254,19 +255,25 @@ CONFIG_MODULES_USE_ELF_RELA=y
 # CONFIG_MSM_MMCC_8996 is not set
 # CONFIG_MSM_MMCC_8998 is not set
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_HYPERBUS is not set
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_NAND_ECC_SW_BCH is not set
+# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
 CONFIG_MTD_NAND_QCOM=y
 CONFIG_MTD_QCOMSMEM_PARTS=y
+# CONFIG_MTD_NAND_QCOM_SERIAL is not set
 CONFIG_MTD_RAW_NAND=y
+# CONFIG_MTD_ROUTERBOOT_PARTS is not set
 CONFIG_MTD_SPI_NOR=y
+# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set
+# CONFIG_MTD_SPLIT_ELF_FW is not set
 CONFIG_MTD_SPLIT_FIRMWARE=y
 CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -352,6 +359,7 @@ CONFIG_POWER_RESET_MSM=y
 # CONFIG_POWER_RESET_QCOM_PON is not set
 CONFIG_POWER_SUPPLY=y
 CONFIG_PRINTK_TIME=y
+CONFIG_QCOM_APM=y
 # CONFIG_QCOM_A53PLL is not set
 # CONFIG_QCOM_AOSS_QMP is not set
 CONFIG_QCOM_APCS_IPC=y
@@ -359,9 +367,11 @@ CONFIG_QCOM_APCS_IPC=y
 CONFIG_QCOM_BAM_DMA=y
 # CONFIG_QCOM_CLK_APCC_MSM8996 is not set
 # CONFIG_QCOM_CLK_APCS_MSM8916 is not set
+# CONFIG_QCOM_CLK_RPM is not set
+# CONFIG_QCOM_CLK_SMD_RPM is not set
 # CONFIG_QCOM_COINCELL is not set
 # CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
+CONFIG_QCOM_CPR=y
 CONFIG_QCOM_EBI2=y
 # CONFIG_QCOM_FASTRPC is not set
 # CONFIG_QCOM_GENI_SE is not set
@@ -382,10 +392,12 @@ CONFIG_QCOM_QFPROM=y
 CONFIG_QCOM_QMI_HELPERS=y
 # CONFIG_QCOM_RMTFS_MEM is not set
 # CONFIG_QCOM_RPMH is not set
+# CONFIG_QCOM_RPMPD is not set
+CONFIG_QCOM_RPM_CLK=y
 CONFIG_QCOM_RPROC_COMMON=y
 CONFIG_QCOM_SCM=y
 # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-# CONFIG_QCOM_SMD_RPM is not set
+CONFIG_QCOM_SMD_RPM=y
 CONFIG_QCOM_SMEM=y
 CONFIG_QCOM_SMEM_STATE=y
 CONFIG_QCOM_SMP2P=y
@@ -410,11 +422,16 @@ CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
 CONFIG_RATIONAL=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPMI=y
+# CONFIG_REGMAP_SPMI is not set
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_CPR3=y
+CONFIG_REGULATOR_CPR3_NPU is not set
+CONFIG_REGULATOR_CPR4_APSS=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 # CONFIG_REGULATOR_QCOM_LABIBB is not set
-CONFIG_REGULATOR_QCOM_SPMI=y
+# CONFIG_REGULATOR_QCOM_RPM is not set
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
 # CONFIG_REGULATOR_QCOM_USB_VBUS is not set
 # CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
 CONFIG_RELOCATABLE=y
@@ -427,10 +444,9 @@ CONFIG_RFS_ACCEL=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 CONFIG_RPMSG=y
 CONFIG_RPMSG_CHAR=y
-CONFIG_RPMSG_QCOM_GLINK=y
 CONFIG_RPMSG_QCOM_GLINK_RPM=y
 CONFIG_RPMSG_QCOM_GLINK_SMEM=y
-CONFIG_RPMSG_QCOM_SMD=y
+# CONFIG_RPMSG_QCOM_SMD is not set
 CONFIG_RPS=y
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_SCHED_MC=y
@@ -467,9 +483,10 @@ CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
 CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
+# CONFIG_SPMI is not set
+# CONFIG_SPMI_MSM_PMIC_ARB is not set
 # CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_MSM_PMIC_ARB is not set
 # CONFIG_SPMI_PMIC_CLKDIV is not set
 CONFIG_SRCU=y
 CONFIG_SWIOTLB=y
@@ -490,6 +507,12 @@ CONFIG_TIMER_PROBE=y
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_XZ=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_ZSTD is not set
 CONFIG_UNMAP_KERNEL_AT_EL0=y
 CONFIG_USB=y
 CONFIG_USB_COMMON=y
@@ -507,4 +530,3 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZONE_DMA32=y
 CONFIG_ZSTD_COMPRESS=y
 CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_IPQ_MEM_PROFILE=0

root/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-cp-cpu.dtsi

@@ -16,18 +16,25 @@
 
 &CPU0 {
 	operating-points-v2 = <&cpu_opp_table>;
+	voltage-tolerance = <1>;
+	cpu-supply = <&apc_vreg>;
 };
 
 &CPU1 {
 	operating-points-v2 = <&cpu_opp_table>;
+	voltage-tolerance = <1>;
+	cpu-supply = <&apc_vreg>;
 };
 
 &CPU2 {
 	operating-points-v2 = <&cpu_opp_table>;
+	voltage-tolerance = <1>;
+	cpu-supply = <&apc_vreg>;
 };
 
 &CPU3 {
 	operating-points-v2 = <&cpu_opp_table>;
+	cpu-supply = <&apc_vreg>;
 };
 
 &cpus {

root/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-cpr-regulator.dtsi

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+&soc {
+	apc_apm: apm@b111000 {
+		compatible = "qcom,ipq807x-apm";
+		reg = <0xb111000 0x1000>;
+		reg-names = "pm-apcc-glb";
+		qcom,apm-post-halt-delay = <0x2>;
+		qcom,apm-halt-clk-delay = <0x11>;
+		qcom,apm-resume-clk-delay = <0x10>;
+		qcom,apm-sel-switch-delay = <0x01>;
+	};
+
+	apc_cpr: cpr4-ctrl@b018000 {
+		compatible = "qcom,cpr4-ipq6018-apss-regulator";
+		reg = <0xb018000 0x4000>, <0xa4000 0x1000>, <0x0193d008 0x4>;
+		reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
+		interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "cpr";
+		qcom,cpr-ctrl-name = "apc";
+		qcom,cpr-sensor-time = <1000>;
+		qcom,cpr-loop-time = <5000000>;
+		qcom,cpr-idle-cycles = <15>;
+		qcom,cpr-step-quot-init-min = <0>;
+		qcom,cpr-step-quot-init-max = <15>;
+		qcom,cpr-count-mode = <0>;		/* All-at-once */
+		qcom,cpr-count-repeat = <1>;
+		qcom,cpr-down-error-step-limit = <1>;
+		qcom,cpr-up-error-step-limit = <1>;
+		qcom,apm-ctrl = <&apc_apm>;
+		qcom,apm-threshold-voltage = <850000>;
+		vdd-supply = <&ipq6018_s2>;
+		qcom,voltage-step = <12500>;
+
+		thread@0 {
+			qcom,cpr-thread-id = <0>;
+			qcom,cpr-consecutive-up = <2>;
+			qcom,cpr-consecutive-down = <2>;
+			qcom,cpr-up-threshold = <2>;
+			qcom,cpr-down-threshold = <2>;
+
+			apc_vreg: regulator {
+				regulator-name = "apc_corner";
+				regulator-min-microvolt = <1>;
+				regulator-max-microvolt = <6>;
+				qcom,cpr-fuse-corners = <4>;
+				qcom,cpr-fuse-combos = <8>;
+				qcom,cpr-corners = <6>;
+				qcom,cpr-speed-bins = <1>;
+				qcom,cpr-speed-bin-corners = <6>;
+				qcom,cpr-corner-fmax-map = <1 3 5 6>;
+				qcom,allow-voltage-interpolation;
+				qcom,allow-quotient-interpolation;
+				qcom,cpr-voltage-ceiling =
+					<725000 787500 862500
+					 925000 987500 1062500>;
+				qcom,cpr-voltage-floor =
+					<587500 650000 712500
+					 750000 787500 850000>;
+				qcom,corner-frequencies =
+					<864000000 1056000000 1320000000
+					1440000000 1608000000 1800000000>;
+				qcom,cpr-ro-sel =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     7      7      7     7>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-open-loop-voltage-fuse-adjustment =
+					/* Speed bin 0; CPR rev 0..7 */
+					/*   SVS  Nominal Turbo Turbo_L1 */
+					<     0      0      0     0>,
+					<     0      0  15000     0>,
+					<     0      0  15000     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-closed-loop-voltage-fuse-adjustment =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					< 13000      0  13000 13000>,
+					< 13000      0  13000 13000>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-ro-scaling-factor =
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >,
+					< 2000 1770 1900 1670 1930 1770 1910 1800
+					  1870 1730 2000 1840 1800 2030 1700 1890 >;
+				regulator-always-on;
+			};
+		};
+	};
+};

root/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-hr6001.dts

@@ -8,11 +8,12 @@
 /dts-v1/;
 
 #include "ipq6018.dtsi"
+#include "ipq6018-cpr-regulator.dtsi"
 #include "ipq6018-cp-cpu.dtsi"
 
 / {
 	model = "WF HR6001";
-	compatible = "qcom,ap-cp01-c3", "qcom,ipq6018";
+	compatible = "wf,hr6001", "qcom,ipq6018";
 
 	aliases {
 		led-boot = &power;
@@ -33,7 +34,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_1 swiotlb=1";
+		bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1";
 	};
 };
 
@@ -278,7 +279,7 @@
 		};
 	};
 
-	dp1 {
+	dp1: dp1 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
 		qcom,id = <1>;
@@ -288,9 +289,10 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <0>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
-	dp2 {
+	dp2: dp2 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
 		qcom,id = <2>;
@@ -300,9 +302,10 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <1>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
-	dp3 {
+	dp3: dp3 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
 		qcom,id = <3>;
@@ -312,9 +315,10 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <2>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
-	dp4 {
+	dp4: dp4 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
 		qcom,id = <4>;
@@ -324,9 +328,10 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <3>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
-	dp5 {
+	dp5: dp5 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
 		qcom,id = <5>;
@@ -336,6 +341,7 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <24>;
 		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
 	};
 
 	ess-switch@3a000000 {
@@ -451,16 +457,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
 		nand-bus-width = <8>;
 
-		partition0@ {
+		partition@0 {
 			label = "rootfs";
 			reg = <0x0 0x3c00000>;
 		};
 
-		partition1@0x8000000 {
+		partition@8000000 {
 			label = "rootfs_1";
 			reg = <0x3c00000 0x3c00000>;
 		};
@@ -483,13 +488,6 @@
 	status = "ok";
 };
 
-&sdhc_2 {
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
-	status = "ok";
-};
-
 &qusb_phy_0 {
 	status = "ok";
 };
@@ -515,9 +513,12 @@
 &sdhc_2 {
 	pinctrl-0 = <&sd_pins>;
 	pinctrl-names = "default";
-	mmc-pwrseq = <&sd_pwrseq>;
-	cd-gpios = <&tlmm 62 1>;
+	cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
 	sd-ldo-gpios = <&tlmm 66 0>;
 	vqmmc-supply = <&ipq6018_l2>;
 	status = "ok";
 };
+
+&wifi {
+	status = "disabled";
+};

root/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-l6018.dts

@@ -0,0 +1,644 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ6018 CP01 board device tree source
+ *
+ * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq6018.dtsi"
+#include "ipq6018-cpr-regulator.dtsi"
+#include "ipq6018-cp-cpu.dtsi"
+
+/ {
+	model = "openmptcprouter5g_618";
+	compatible = "pangu,l6018", "qcom,ipq6018";
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+		serial0 = &blsp1_uart3;
+		/*
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
+		ethernet2 = "/soc/dp3";
+		ethernet3 = "/soc/dp4";
+		ethernet4 = "/soc/dp5";
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1";
+	};
+};
+
+&blsp1_uart3 {
+	pinctrl-0 = <&serial_3_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&i2c_1 {
+	pinctrl-0 = <&i2c_1_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 {
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		spi-max-frequency = <50000000>;
+
+		SBL1@0 {
+			label = "0:SBL1";
+			reg = <0x0 0xc0000>;
+			read-only;
+		};
+
+		MIBIB@c0000 {
+			label = "0:MIBIB";
+			reg = <0xc0000 0x10000>;
+		};
+
+		BOOTCONFIG@d0000 {
+			label = "0:BOOTCONFIG";
+			reg = <0xd0000 0x20000>;
+			read-only;
+		};
+
+		BOOTCONFIG1@f0000 {
+			label = "0:BOOTCONFIG1";
+			reg = <0xf0000 0x20000>;
+			read-only;
+		};
+
+		QSEE@110000 {
+			label = "0:QSEE";
+			reg = <0x110000 0x1a0000>;
+			read-only;
+		};
+
+		QSEE_1@2b0000 {
+			label = "0:QSEE_1";
+			reg = <0x2b0000 0x1a0000>;
+			read-only;
+		};
+
+		DEVCFG@450000 {
+			label = "0:DEVCFG";
+			reg = <0x450000 0x10000>;
+			read-only;
+		};
+
+		DEVCFG_1@460000 {
+			label = "0:DEVCFG_1";
+			reg = <0x460000 0x10000>;
+			read-only;
+		};
+
+		RPM@470000 {
+			label = "0:RPM";
+			reg = <0x4700000 0x40000>;
+		};
+
+		RPM_1@4b0000 {
+			label = "0:RPM_1";
+			reg = <0x4b0000 0x40000>;
+			read-only;
+		};
+
+		CDT@4f0000 {
+			label = "0:CDT";
+			reg = <0x4f0000 0x10000>;
+		};
+
+		CDT_1@500000 {
+			label = "0:CDT_1";
+			reg = <0x500000 0x10000>;
+			read-only;
+		};
+
+		APPSBLENV@510000 {
+			label = "0:APPSBLENV";
+			reg = <0x510000 0x10000>;
+		};
+
+		APPSBL@520000 {
+			label = "0:APPSBL";
+			reg = <0x520000 0xa0000>;
+		};
+
+		APPSBL_1@5c0000 {
+			label = "0:APPSBL_1";
+			reg = <0x5c0000 0xa0000>;
+		};
+
+		ART: ART@660000 {
+			label = "0:ART";
+			reg = <0x660000 0x40000>;
+		};
+	};
+};
+
+&tlmm {
+	spi_0_pins: spi-0-pins {
+		pins = "gpio38", "gpio39", "gpio40", "gpio41";
+		function = "blsp0_spi";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	i2c_1_pins: i2c_1_pins {
+		mux {
+			pins = "gpio42", "gpio43";
+			function = "blsp2_i2c";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	button_pins: button_pins {
+		wps_button {
+			pins = "gpio9";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	rst_usb_hub_pinmux {
+		mux {
+			pins = "gpio66";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-high;
+		};
+	};
+
+	mdio_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio64";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_1 {
+			pins = "gpio65";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_2 {
+			pins = "gpio75";
+			function = "gpio";
+			bias-pull-up;
+		};
+		mux_3 {
+			pins = "gpio77";
+			function = "gpio";
+			bias-pull-up;
+		};
+	};
+
+	pcie0_pins: pcie_pins {
+		pcie0_rst {
+			pins = "gpio60";
+			function = "pcie0_rst";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		pcie0_wake {
+			pins = "gpio36";
+			function = "pcie0_wake";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	leds_pins: leds_pins {
+		power {
+			pins = "gpio25";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		wlan5g {
+			pins = "gpio35";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		wlan2g {
+			pins = "gpio37";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		usb1 {
+			pins = "gpio24";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		usb0 {
+			pins = "gpio50";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte1 {
+			pins = "gpio34";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte2 {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte3 {
+			pins = "gpio30";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte4 {
+			pins = "gpio31";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte5 {
+			pins = "gpio32";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte6 {
+			pins = "gpio23";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte1pwr {
+			pins = "gpio0";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte2pwr {
+			pins = "gpio16";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte3pwr {
+			pins = "gpio18";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte4pwr {
+			pins = "gpio2";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte5pwr {
+			pins = "gpio21";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		lte6pwr {
+			pins = "gpio22";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+};
+
+&soc {
+	mdio: mdio@90000 {
+		pinctrl-0 = <&mdio_pins>;
+		pinctrl-names = "default";
+		phy-reset-gpio = <&tlmm 75 0 &tlmm 77 1>;
+		status = "ok";
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+		phy1: ethernet-phy@1 {
+			reg = <1>;
+		};
+		phy2: ethernet-phy@2 {
+			reg = <2>;
+		};
+		phy3: ethernet-phy@3 {
+			reg = <3>;
+		};
+		phy4: ethernet-phy@4 {
+			reg = <0x30>;
+		};
+	};
+
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <1>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <2>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <3>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a003000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <30>;
+		phy-mode = "sgmii";
+		mdio-bus = <&mdio>;
+	};
+
+	ess-switch@3a000000 {
+		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+		switch_lan_bmp = <0x1e>; /* lan port bitmap */
+		switch_wan_bmp = <0x20>; /* wan port bitmap */
+		switch_inner_bmp = <0xc0>; /*inner port bitmap*/
+		switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+		switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
+		switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+		qcom,port_phyinfo {
+			port@0 {
+				port_id = <1>;
+				phy_address = <0>;
+			};
+			port@1 {
+				port_id = <2>;
+				phy_address = <1>;
+			};
+			port@2 {
+				port_id = <3>;
+				phy_address = <2>;
+			};
+			port@3 {
+				port_id = <4>;
+				phy_address = <3>;
+			};
+			port@4 {
+				port_id = <5>;
+				phy_address = <30>;
+				phy_i2c_address = <30>;
+				phy-i2c-mode; /*i2c access phy */
+				media-type = "sfp"; /* fiber mode */
+			};
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+
+		led@24 {
+			label = "green:usb1";
+			gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@50 {
+			label = "green:usb0";
+			gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+		};
+
+		power: led@25 {
+			label = "green:power";
+			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@35 {
+			label = "green:wlan5g";
+			gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@37 {
+			label = "green:wlan2g";
+			gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@34 {
+			label = "green:lte1";
+			gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@29 {
+			label = "green:lte29";
+			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@30 {
+			label = "green:lte3";
+			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@31 {
+			label = "green:lte4";
+			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@32 {
+			label = "green:lte5";
+			gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@23 {
+			label = "green:lte6";
+			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+		};
+		
+		led@0 {
+			label = "green:lte1pwr";
+			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@16 {
+			label = "green:lte2pwr";
+			gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@18 {
+			label = "green:lte3pwr";
+			gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@2 {
+			label = "green:lte4pwr";
+			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@21 {
+			label = "green:lte5pwr";
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@22 {
+			label = "green:lte6pwr";
+			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&qpic_nand {
+	status = "ok";
+
+	nand@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partition@0 {
+			label = "rootfs";
+			reg = <0x0 0x8000000>;
+		};
+
+		partition@8000000 {
+			label = "rootfs_1";
+			reg = <0x8000000 0x8000000>;
+		};
+	};
+};
+
+&pcie_phy {
+	status = "ok";
+};
+
+&pcie0 {
+	perst-gpio = <&tlmm 60 1>;
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb2 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&usb3 {
+	status = "ok";
+};
+
+&nss_crypto {
+	status = "ok";
+};
+
+&wifi {
+	status = "disabled";
+};

root/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-memory.dtsi

@@ -132,7 +132,7 @@
 			reg = <0x0 0x4d400000 0x0 0x100000>;
 		};
 
-		rpm_msg_ram: rpm_msg_ram@0x60000 {
+		rpm_msg_ram: rpm_msg_ram@60000 {
 			no-map;
 			reg = <0x0 0x60000 0x0 0x6000>;
 		};
@@ -256,7 +256,7 @@
 			reg = <0x0 0x4e300000 0x0 0x100000>;
 		};
 
-		rpm_msg_ram: rpm_msg_ram@0x60000 {
+		rpm_msg_ram: rpm_msg_ram@60000 {
 			no-map;
 			reg = <0x0 0x60000 0x0 0x6000>;
 		};
@@ -383,7 +383,7 @@
 			reg = <0x0 0x50100000 0x0 0x100000>;
 		};
 
-		rpm_msg_ram: rpm_msg_ram@0x60000 {
+		rpm_msg_ram: rpm_msg_ram@60000 {
 			no-map;
 			reg = <0x0 0x60000 0x0 0x6000>;
 		};

root/target/linux/ipq60xx/image/generic.mk

@@ -23,31 +23,30 @@ define Device/UbiFit
 	IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 
-define Device/glinet_gl-ax1800
+define Device/wf_hr6001
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
-	DEVICE_VENDOR := GL.iNet
-	DEVICE_MODEL := GL-AX1800
+	DEVICE_VENDOR := WF
+	DEVICE_MODEL := HR6001
+	KERNEL_LOADADDR := 0x41000000
 	BLOCKSIZE := 128k
 	PAGESIZE := 2048
-	DEVICE_DTS := qcom-ipq6018-gl-ax1800
-	DEVICE_DTS_CONFIG := config@cp03-c1
-	BOARD_NAME := ap-cp03-c1
-	IMAGES += stock-factory.bin
-	IMAGE/stock-factory.bin := append-ubi | qsdk-ipq-factory-nand
+	DEVICE_DTS_CONFIG := config@cp01-c1
+	SOC := ipq6018
+	DEVICE_PACKAGES :=  uboot-envtools
 endef
-TARGET_DEVICES += glinet_gl-ax1800
+TARGET_DEVICES += wf_hr6001
 
-#define Device/wf_hr6001
-#	$(call Device/FitImage)
-#	$(call Device/UbiFit)
-#	DEVICE_VENDOR := WF
-#	DEVICE_MODEL := HR6001
-#	KERNEL_LOADADDR := 0x41000000
-#	BLOCKSIZE := 128k
-#	PAGESIZE := 2048
-#	DEVICE_DTS_CONFIG := config@cp01-c1
-#	SOC := ipq6018
-#	DEVICE_PACKAGES :=  uboot-envtools
-#endef
-#TARGET_DEVICES += wf_hr6001
+define Device/pangu_l6018
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := PANGU
+	DEVICE_MODEL := L6018
+	KERNEL_LOADADDR := 0x41000000
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_DTS_CONFIG := config@cp01-c3
+	SOC := ipq6018
+	DEVICE_PACKAGES :=  uboot-envtools
+endef
+TARGET_DEVICES += pangu_l6018

root/target/linux/ipq60xx/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch

@@ -273,7 +273,7 @@ Cc: linux-tegra@vger.kernel.org
  	ret = pm_runtime_get_sync(dev);
 --- a/drivers/pci/controller/dwc/pcie-uniphier.c
 +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
-@@ -335,12 +335,6 @@ static int uniphier_add_pcie_port(struct
+@@ -341,12 +341,6 @@ static int uniphier_add_pcie_port(struct
  
  	pp->ops = &uniphier_pcie_host_ops;
  

root/target/linux/ipq60xx/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch

@@ -581,7 +581,7 @@ Cc: linux-tegra@vger.kernel.org
  }
  
  static void uniphier_pcie_stop_link(struct dw_pcie *pci)
-@@ -312,10 +309,6 @@ static int uniphier_pcie_host_init(struc
+@@ -318,10 +315,6 @@ static int uniphier_pcie_host_init(struc
  	uniphier_pcie_irq_enable(priv);
  
  	dw_pcie_setup_rc(pp);
@@ -592,7 +592,7 @@ Cc: linux-tegra@vger.kernel.org
  	dw_pcie_msi_init(pp);
  
  	return 0;
-@@ -379,7 +372,7 @@ out_clk_disable:
+@@ -385,7 +378,7 @@ out_clk_disable:
  }
  
  static const struct dw_pcie_ops dw_pcie_ops = {

root/target/linux/ipq60xx/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch

@@ -262,7 +262,7 @@ Cc: linux-tegra@vger.kernel.org
  	val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
 --- a/drivers/pci/controller/dwc/pcie-uniphier.c
 +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
-@@ -309,7 +309,6 @@ static int uniphier_pcie_host_init(struc
+@@ -315,7 +315,6 @@ static int uniphier_pcie_host_init(struc
  	uniphier_pcie_irq_enable(priv);
  
  	dw_pcie_setup_rc(pp);

root/target/linux/ipq60xx/patches-5.10/600-qca-nss-ecm-support-CORE.patch

@@ -1,39 +1,35 @@
 --- a/net/netfilter/nf_conntrack_proto_tcp.c
 +++ b/net/netfilter/nf_conntrack_proto_tcp.c
-@@ -32,20 +32,14 @@
+@@ -32,12 +32,14 @@
  #include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
  
  /* Do not check the TCP window for incoming packets  */
 -static int nf_ct_tcp_no_window_check __read_mostly = 1;
--
--#ifdef CONFIG_SHORTCUT_FE
 +int nf_ct_tcp_no_window_check __read_mostly = 1;
- EXPORT_SYMBOL_GPL(nf_ct_tcp_no_window_check);
--#endif
++EXPORT_SYMBOL_GPL(nf_ct_tcp_no_window_check);
  
  /* "Be conservative in what you do,
      be liberal in what you accept from others."
      If it's non-zero, we mark only out of window RST segments as INVALID. */
 -static int nf_ct_tcp_be_liberal __read_mostly = 0;
--
--#ifdef CONFIG_SHORTCUT_FE
 +int nf_ct_tcp_be_liberal __read_mostly = 0;
- EXPORT_SYMBOL_GPL(nf_ct_tcp_be_liberal);
--#endif
++EXPORT_SYMBOL_GPL(nf_ct_tcp_be_liberal);
  
  /* If it is set to zero, we disable picking up already established
     connections. */
 --- a/include/linux/if_bridge.h
 +++ b/include/linux/if_bridge.h
-@@ -64,6 +64,7 @@ extern void brioctl_set(int (*ioctl_hook
+@@ -61,6 +61,9 @@ struct br_ip_list {
+ #define BR_DEFAULT_AGEING_TIME	(300 * HZ)
  
- extern void br_dev_update_stats(struct net_device *dev,
- 				struct rtnl_link_stats64 *nlstats);
+ extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *));
++extern void br_dev_update_stats(struct net_device *dev,
++				struct rtnl_link_stats64 *nlstats);
 +extern bool br_is_hairpin_enabled(struct net_device *dev);
  
  #if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_BRIDGE_IGMP_SNOOPING)
  int br_multicast_list_adjacent(struct net_device *dev,
-@@ -159,4 +160,41 @@ br_port_flag_is_set(const struct net_dev
+@@ -156,4 +159,41 @@ br_port_flag_is_set(const struct net_dev
  }
  #endif
  
@@ -108,7 +104,7 @@
  		     __be16 vlan_proto, u16 vlan_id)
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2745,6 +2745,10 @@ enum netdev_cmd {
+@@ -2756,6 +2756,10 @@ enum netdev_cmd {
  	NETDEV_CVLAN_FILTER_DROP_INFO,
  	NETDEV_SVLAN_FILTER_PUSH_INFO,
  	NETDEV_SVLAN_FILTER_DROP_INFO,
@@ -135,7 +131,7 @@
  	const struct dst_entry *dst = skb_dst(skb);
 --- a/include/net/neighbour.h
 +++ b/include/net/neighbour.h
-@@ -574,4 +574,15 @@ static inline void neigh_update_is_route
+@@ -568,4 +568,15 @@ static inline void neigh_update_is_route
  		*notify = 1;
  	}
  }
@@ -400,11 +396,35 @@
  	/* Since more than one interface can be attached to a bridge,
  	 * there still maybe an alternate path for netconsole to use;
  	 * therefore there is no reason for a NETDEV_RELEASE event.
-@@ -812,3 +822,74 @@ bool br_port_flag_is_set(const struct ne
+@@ -790,3 +800,98 @@ bool br_port_flag_is_set(const struct ne
  	return p->flags & flag;
  }
  EXPORT_SYMBOL_GPL(br_port_flag_is_set);
 +
++/* QCA NSS ECM support - Start */
++/* Update bridge statistics for bridge packets processed by offload engines */
++void br_dev_update_stats(struct net_device *dev,
++			 struct rtnl_link_stats64 *nlstats)
++{
++	struct net_bridge *br;
++	struct pcpu_sw_netstats *stats;
++
++	/* Is this a bridge? */
++	if (!(dev->priv_flags & IFF_EBRIDGE))
++		return;
++
++	br = netdev_priv(dev);
++	stats = this_cpu_ptr(br->stats);
++
++	u64_stats_update_begin(&stats->syncp);
++	stats->rx_packets += nlstats->rx_packets;
++	stats->rx_bytes += nlstats->rx_bytes;
++	stats->tx_packets += nlstats->tx_packets;
++	stats->tx_bytes += nlstats->tx_bytes;
++	u64_stats_update_end(&stats->syncp);
++}
++EXPORT_SYMBOL_GPL(br_dev_update_stats);
++
 +/* API to know if hairpin feature is enabled/disabled on this bridge port */
 +bool br_is_hairpin_enabled(struct net_device *dev)
 +{
@@ -489,7 +509,7 @@
  #endif
 --- a/net/core/neighbour.c
 +++ b/net/core/neighbour.c
-@@ -1209,7 +1209,21 @@ static void neigh_update_hhs(struct neig
+@@ -1210,7 +1210,21 @@ static void neigh_update_hhs(struct neig
  	}
  }
  
@@ -511,7 +531,7 @@
  
  /* Generic update routine.
     -- lladdr is new lladdr or NULL, if it is not supplied.
-@@ -1240,6 +1254,7 @@ static int __neigh_update(struct neighbo
+@@ -1241,6 +1255,7 @@ static int __neigh_update(struct neighbo
  	int notify = 0;
  	struct net_device *dev;
  	int update_isrouter = 0;
@@ -519,7 +539,7 @@
  
  	trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid);
  
-@@ -1254,6 +1269,8 @@ static int __neigh_update(struct neighbo
+@@ -1255,6 +1270,8 @@ static int __neigh_update(struct neighbo
  		new = old;
  		goto out;
  	}
@@ -528,7 +548,7 @@
  	if (!(flags & NEIGH_UPDATE_F_ADMIN) &&
  	    (old & (NUD_NOARP | NUD_PERMANENT)))
  		goto out;
-@@ -1291,6 +1308,11 @@ static int __neigh_update(struct neighbo
+@@ -1286,6 +1303,11 @@ static int __neigh_update(struct neighbo
  		   - compare new & old
  		   - if they are different, check override flag
  		 */
@@ -540,7 +560,7 @@
  		if ((old & NUD_VALID) &&
  		    !memcmp(lladdr, neigh->ha, dev->addr_len))
  			lladdr = neigh->ha;
-@@ -1413,8 +1435,11 @@ out:
+@@ -1408,8 +1430,11 @@ out:
  	if (((new ^ old) & NUD_PERMANENT) || ext_learn_change)
  		neigh_update_gc_list(neigh);
  
@@ -620,7 +640,7 @@
  #endif
 --- a/net/ipv6/addrconf.c
 +++ b/net/ipv6/addrconf.c
-@@ -7236,3 +7236,35 @@ void addrconf_cleanup(void)
+@@ -7233,3 +7233,35 @@ void addrconf_cleanup(void)
  
  	destroy_workqueue(addrconf_wq);
  }
@@ -668,7 +688,7 @@
  		   const struct in6_addr *daddr)
 --- a/net/ipv6/route.c
 +++ b/net/ipv6/route.c
-@@ -3767,6 +3767,9 @@ out_free:
+@@ -3748,6 +3748,9 @@ out_free:
  	return ERR_PTR(err);
  }
  
@@ -678,7 +698,7 @@
  int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags,
  		  struct netlink_ext_ack *extack)
  {
-@@ -3778,6 +3781,10 @@ int ip6_route_add(struct fib6_config *cf
+@@ -3759,6 +3762,10 @@ int ip6_route_add(struct fib6_config *cf
  		return PTR_ERR(rt);
  
  	err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack);
@@ -689,7 +709,7 @@
  	fib6_info_release(rt);
  
  	return err;
-@@ -3799,6 +3806,9 @@ static int __ip6_del_rt(struct fib6_info
+@@ -3780,6 +3787,9 @@ static int __ip6_del_rt(struct fib6_info
  	err = fib6_del(rt, info);
  	spin_unlock_bh(&table->tb6_lock);
  
@@ -699,7 +719,7 @@
  out:
  	fib6_info_release(rt);
  	return err;
-@@ -6151,6 +6161,20 @@ static int ip6_route_dev_notify(struct n
+@@ -6132,6 +6142,20 @@ static int ip6_route_dev_notify(struct n
  	return NOTIFY_OK;
  }
  

root/target/linux/ipq60xx/patches-5.10/601-netfilter-export-udp_get_timeouts-function.patch

@@ -0,0 +1,38 @@
+From e38488fd0a8a11b4bae4ccad9a7a8cfcf9eb5ab7 Mon Sep 17 00:00:00 2001
+From: Murat Sezgin <msezgin@codeaurora.org>
+Date: Mon, 6 Apr 2020 11:08:09 -0700
+Subject: [PATCH] netfilter: export udp_get_timeouts function
+
+This function is required for acceleration support.
+
+Signed-off-by: Murat Sezgin <msezgin@codeaurora.org>
+Change-Id: Ibca4f402735764e7e6fb3ce2678e670753c6ef9c
+---
+ include/net/netfilter/nf_conntrack_timeout.h | 1 +
+ net/netfilter/nf_conntrack_proto_udp.c       | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/include/net/netfilter/nf_conntrack_timeout.h
++++ b/include/net/netfilter/nf_conntrack_timeout.h
+@@ -123,5 +123,6 @@ static inline void nf_ct_destroy_timeout
+ extern struct nf_ct_timeout *(*nf_ct_timeout_find_get_hook)(struct net *net, const char *name);
+ extern void (*nf_ct_timeout_put_hook)(struct nf_ct_timeout *timeout);
+ #endif
++extern unsigned int *udp_get_timeouts(struct net *net);
+ 
+ #endif /* _NF_CONNTRACK_TIMEOUT_H */
+--- a/net/netfilter/nf_conntrack_proto_udp.c
++++ b/net/netfilter/nf_conntrack_proto_udp.c
+@@ -29,10 +29,11 @@ static const unsigned int udp_timeouts[U
+ 	[UDP_CT_REPLIED]	= 120*HZ,
+ };
+ 
+-static unsigned int *udp_get_timeouts(struct net *net)
++unsigned int *udp_get_timeouts(struct net *net)
+ {
+ 	return nf_udp_pernet(net)->timeouts;
+ }
++EXPORT_SYMBOL(udp_get_timeouts);
+ 
+ static void udp_error_log(const struct sk_buff *skb,
+ 			  const struct nf_hook_state *state,

root/target/linux/ipq60xx/patches-5.10/602-qca-add-pppoe-offload-support.patch

@@ -466,8 +466,8 @@
  #endif /* !(__LINUX_IF_PPPOX_H) */
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1620,6 +1620,24 @@ enum netdev_priv_flags {
- 	IFF_LIVE_RENAME_OK		= 1<<30,
+@@ -1621,6 +1621,24 @@ enum netdev_priv_flags {
+ 	IFF_NO_IP_ALIGN			= 1<<31,
  };
  
 +
@@ -491,7 +491,7 @@
  #define IFF_802_1Q_VLAN			IFF_802_1Q_VLAN
  #define IFF_EBRIDGE			IFF_EBRIDGE
  #define IFF_BONDING			IFF_BONDING
-@@ -1994,6 +2012,7 @@ struct net_device {
+@@ -2001,6 +2019,7 @@ struct net_device {
  
  	unsigned int		flags;
  	unsigned int		priv_flags;

root/target/linux/ipq60xx/patches-5.10/603-net-core-Flag-to-identify-ingress-shaping-done-for-e.patch

@@ -31,7 +31,7 @@ Change-Id: Ib3cd341e5b2d4dcf552e02e38d3f34a4f00351cd
  	__u8			redirected:1;
 --- a/include/net/sch_generic.h
 +++ b/include/net/sch_generic.h
-@@ -754,6 +754,40 @@ static inline bool skb_skip_tc_classify(
+@@ -750,6 +750,40 @@ static inline bool skb_skip_tc_classify(
  	return false;
  }
  

root/target/linux/ipq60xx/patches-5.10/604-net-core-Replace-nss-keyword-with-offload.patch

@@ -35,7 +35,7 @@ Change-Id: Iddb97d6ba0a443b830d1ac23728434a417bc8a92
  	__u8			redirected:1;
 --- a/include/net/sch_generic.h
 +++ b/include/net/sch_generic.h
-@@ -757,31 +757,31 @@ static inline bool skb_skip_tc_classify(
+@@ -753,31 +753,31 @@ static inline bool skb_skip_tc_classify(
  /*
   * Set skb classify bit field.
   */

root/target/linux/ipq60xx/patches-5.10/605-qca-add-add-nss-bridge-mgr-support.patch

@@ -13,7 +13,7 @@ Signed-off-by: Simon Casey <simon501098c@gmail.com>
 
 --- a/include/linux/if_bridge.h
 +++ b/include/linux/if_bridge.h
-@@ -197,4 +197,8 @@ typedef struct net_bridge_port *br_get_d
+@@ -196,4 +196,8 @@ typedef struct net_bridge_port *br_get_d
  extern br_get_dst_hook_t __rcu *br_get_dst_hook;
  /* QCA NSS ECM support - End */
  

root/target/linux/ipq60xx/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch

@@ -17,7 +17,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 +dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-hr6001.dtb
-+dtb-$(CONFIG_ARCH_QCOM)	+= qcom-ipq6018-gl-ax1800.dtb
++dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-l6018.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb
  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb

root/target/linux/ipq60xx/patches-5.10/904-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch

@@ -0,0 +1,49 @@
+From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001
+From: Praveenkumar I <ipkumar@codeaurora.org>
+Date: Mon, 4 Sep 2017 15:00:10 +0530
+Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq
+
+If the parent clock rate is greater than unsigned long max
+divided by 2 then the integer overflow is happening while
+calculating the clock rate. Since RCG2 uses half integer
+dividers, the clock rate is first being multiplied by 2
+followed by division and this multiplication leads to
+overflow.
+
+Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+(cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430)
+Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
+
+Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e
+---
+ drivers/clk/qcom/clk-rcg2.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/qcom/clk-rcg2.c
++++ b/drivers/clk/qcom/clk-rcg2.c
+@@ -145,18 +145,18 @@ static int clk_rcg2_set_parent(struct cl
+  *            hid_div       n
+  */
+ static unsigned long
+-calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
++calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div)
+ {
++	u64 rate = parent_rate;
++
+ 	if (hid_div) {
+ 		rate *= 2;
+-		rate /= hid_div + 1;
++		do_div(rate, hid_div + 1);
+ 	}
+ 
+ 	if (mode) {
+-		u64 tmp = rate;
+-		tmp *= m;
+-		do_div(tmp, n);
+-		rate = tmp;
++		rate *= m;
++		do_div(rate, n);
+ 	}
+ 
+ 	return rate;

root/target/linux/ipq60xx/patches-5.10/905-clk-qcom-add-support-for-hw-controlled-RCG.patch

@@ -0,0 +1,136 @@
+From 0245360f8e118b67f4015533cfc79314f2d848d5 Mon Sep 17 00:00:00 2001
+From: Praveenkumar I <ipkumar@codeaurora.org>
+Date: Tue, 13 Jun 2017 15:30:39 +0530
+Subject: [PATCH 2/3] clk: qcom: add support for hw controlled RCG
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The current driver generates stack trace during RCG update if
+the RCG is off and new parent source is also disabled. For
+hardware controlled RCG’s, clock is forced on during update
+process and goes back to off status once switch is completed.
+Since the new parent is in disabled state so update bit won’t
+be cleared in this case. The check for update bit can be
+skipped in this case.
+
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+(cherry picked from commit 84dd0e12f10eebff44a464eb8455205abc4b4178)
+Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
+
+Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
+---
+ drivers/clk/qcom/clk-rcg.h  |  4 ++++
+ drivers/clk/qcom/clk-rcg2.c | 27 +++++++++++++++++++++------
+ 2 files changed, 25 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/qcom/clk-rcg.h
++++ b/drivers/clk/qcom/clk-rcg.h
+@@ -135,6 +135,7 @@ extern const struct clk_ops clk_dyn_rcg_
+  * @mnd_width: number of bits in m/n/d values
+  * @hid_width: number of bits in half integer divider
+  * @safe_src_index: safe src index value
++ * @flags: RCG2 specific clock flags
+  * @parent_map: map from software's parent index to hardware's src_sel field
+  * @freq_tbl: frequency table
+  * @clkr: regmap clock handle
+@@ -145,6 +146,9 @@ struct clk_rcg2 {
+ 	u8			mnd_width;
+ 	u8			hid_width;
+ 	u8			safe_src_index;
++
++#define CLK_RCG2_HW_CONTROLLED		BIT(0)
++	u8			flags;
+ 	const struct parent_map	*parent_map;
+ 	const struct freq_tbl	*freq_tbl;
+ 	struct clk_regmap	clkr;
+--- a/drivers/clk/qcom/clk-rcg2.c
++++ b/drivers/clk/qcom/clk-rcg2.c
+@@ -97,7 +97,7 @@ err:
+ 	return 0;
+ }
+ 
+-static int update_config(struct clk_rcg2 *rcg)
++static int update_config(struct clk_rcg2 *rcg, bool check_update_clear)
+ {
+ 	int count, ret;
+ 	u32 cmd;
+@@ -109,6 +109,9 @@ static int update_config(struct clk_rcg2
+ 	if (ret)
+ 		return ret;
+ 
++	if (!check_update_clear)
++		return 0;
++
+ 	/* Wait for update to take effect */
+ 	for (count = 500; count > 0; count--) {
+ 		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
+@@ -127,14 +130,19 @@ static int clk_rcg2_set_parent(struct cl
+ {
+ 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+ 	int ret;
++	bool check_update_clear = true;
+ 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
+ 
++	if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) &&
++	    !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index)))
++		check_update_clear = false;
++
+ 	ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
+ 				 CFG_SRC_SEL_MASK, cfg);
+ 	if (ret)
+ 		return ret;
+ 
+-	return update_config(rcg);
++	return update_config(rcg, check_update_clear);
+ }
+ 
+ /*
+@@ -302,12 +310,19 @@ static int __clk_rcg2_configure(struct c
+ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
+ {
+ 	int ret;
++	bool check_update_clear = true;
++	struct clk_hw *hw = &rcg->clkr.hw;
++	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
+ 
+ 	ret = __clk_rcg2_configure(rcg, f);
+ 	if (ret)
+ 		return ret;
+ 
+-	return update_config(rcg);
++	if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) &&
++	    !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index)))
++		check_update_clear = false;
++
++	return update_config(rcg, check_update_clear);
+ }
+ 
+ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
+@@ -786,7 +801,7 @@ static int clk_gfx3d_set_rate_and_parent
+ 	if (ret)
+ 		return ret;
+ 
+-	return update_config(rcg);
++	return update_config(rcg, true);
+ }
+ 
+ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
+@@ -898,7 +913,7 @@ static int clk_rcg2_shared_enable(struct
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = update_config(rcg);
++	ret = update_config(rcg, true);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -929,7 +944,7 @@ static void clk_rcg2_shared_disable(stru
+ 	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+ 		     rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
+ 
+-	update_config(rcg);
++	update_config(rcg, true);
+ 
+ 	clk_rcg2_clear_force_enable(hw);
+ 

root/target/linux/ipq60xx/patches-5.10/906-clk-qcom-ipq8074-add-hw-controlled-flag.patch

@@ -0,0 +1,38 @@
+From 18d04f5cae30725ffa0c1c025f6beb1821c46857 Mon Sep 17 00:00:00 2001
+From: Praveenkumar I <ipkumar@codeaurora.org>
+Date: Tue, 13 Jun 2017 15:31:34 +0530
+Subject: [PATCH 3/3] clk: qcom: ipq8074: add hw controlled flag
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These RCG’s are hw controlled so add the
+CLK_RCG2_HW_CONTROLLED flag.
+
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+(cherry picked from commit 9a025b8271a95a80e9e769b89154b98b263be860)
+Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
+
+Change-Id: Ic5da1551bf46921890955312026b9175a42fe14e
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -648,6 +648,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
+ 	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+ 	.hid_width = 5,
+ 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
++	.flags = CLK_RCG2_HW_CONTROLLED,
+ 	.clkr.hw.init = &(struct clk_init_data){
+ 		.name = "pcnoc_bfdcd_clk_src",
+ 		.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+@@ -1317,6 +1318,7 @@ static struct clk_rcg2 system_noc_bfdcd_
+ 	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+ 	.hid_width = 5,
+ 	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
++	.flags = CLK_RCG2_HW_CONTROLLED,
+ 	.clkr.hw.init = &(struct clk_init_data){
+ 		.name = "system_noc_bfdcd_clk_src",
+ 		.parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,

root/target/linux/ipq60xx/patches-5.10/907-device_tree_cmdline.patch

@@ -0,0 +1,12 @@
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1055,6 +1055,9 @@ int __init early_init_dt_scan_chosen(uns
+ 	p = of_get_flat_dt_prop(node, "bootargs", &l);
+ 	if (p != NULL && l > 0)
+ 		strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
++	p = of_get_flat_dt_prop(node, "bootargs-append", &l);
++	if (p != NULL && l > 0)
++		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+ 
+ 	/*
+ 	 * CONFIG_CMDLINE is meant to be a default in case nothing else

root/target/linux/ipq60xx/patches-5.10/910-add-IPQ_MEM_PROFILE.patch

@@ -0,0 +1,168 @@
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index 0e5a8765e..b92cd9775 100644
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -149,6 +149,11 @@ textofs-$(CONFIG_SA1111) := 0x00208000
+ endif
+ textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
++ifeq ($(CONFIG_ARCH_IPQ6018),y)
++textofs-$(CONFIG_ARCH_IPQ256M) := 0x01008000
++else
++textofs-$(CONFIG_ARCH_IPQ256M) := 0x01208000
++endif
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+ textofs-$(CONFIG_ARCH_MESON) := 0x00208000
+ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 247ce9055..d353e0e02 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -269,7 +269,8 @@ not_angel:
+ 		mov	r4, pc
+ 		and	r4, r4, #0xf8000000
+ 		/* Determine final kernel image address. */
+-		add	r4, r4, #TEXT_OFFSET
++		ldr	r0, =TEXT_OFFSET
++		add	r4, r4, r0
+ #else
+ 		ldr	r4, =zreladdr
+ #endif
+diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
+index 4af5c7679..826eae583 100644
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -48,8 +48,9 @@
+ 	.globl	swapper_pg_dir
+ 	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
+ 
+-	.macro	pgtbl, rd, phys
+-	add	\rd, \phys, #TEXT_OFFSET
++	.macro	pgtbl, rd, phys, scratch
++	ldr     \scratch, =TEXT_OFFSET
++	add	\rd, \phys, \scratch
+ 	sub	\rd, \rd, #PG_DIR_SIZE
+ 	.endm
+ 
+@@ -175,7 +176,7 @@ ENDPROC(stext)
+  *  r4 = physical page table address
+  */
+ __create_page_tables:
+-	pgtbl	r4, r8				@ page table address
++	pgtbl	r4, r8, r0				@ page table address
+ 
+ 	/*
+ 	 * Clear the swapper page table
+diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
+index 1772eccb5..a235a3e3c 100644
+--- a/arch/arm/mach-qcom/Kconfig
++++ b/arch/arm/mach-qcom/Kconfig
+@@ -33,4 +33,34 @@ config ARCH_MDM9615
+ 	bool "Enable support for MDM9615"
+ 	select CLKSRC_QCOM
+ 
++config IPQ_MEM_PROFILE
++	int "Select Memory Profile"
++	range 0 1024
++	default 0
++	---help---
++	This option select memory profile to be used, which defines
++	the reserved memory configuration used in device tree.
++
++	If unsure, say 0
++
++config SKB_FIXED_SIZE_2K
++	bool "SKB size fixed at 2K"
++	default n
++	help
++		This is a hint to the NSS driver that the ‘skbuff’ size might
++		need to be fixed at 2KB, to conserve memory.
++
++config ARCH_IPQ256M
++	bool "Enable 256M config"
++	default n
++	help
++	  This sets the text offset of 256M profile, which makes kernel aware of
++          first 16MB of DDR.
++
++config ARCH_IPQ6018
++	bool "Enable support for IPQ6018"
++	help
++	  This enables support for the IPQ6018 chipset. If you dont
++	  know what do here, say N
++
+ endif
+diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+index 5e5cf3af6..f15ac004e 100644
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -1831,6 +1831,16 @@ config STACKPROTECTOR_PER_TASK
+ 	def_bool y
+ 	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
+ 
++config IPQ_MEM_PROFILE
++	int "Select Memory Profile"
++	range 0 1024
++	default 0
++	help
++	This option select memory profile to be used,which defines
++	the reserved memory configuration used in device tree,
++
++	If unsure, say 0.
++
+ endmenu
+ 
+ menu "Boot options"
+diff --git a/include/linux/memblock.h b/include/linux/memblock.h
+index 1a8d25f2e..2d051c033 100644
+--- a/include/linux/memblock.h
++++ b/include/linux/memblock.h
+@@ -67,6 +67,7 @@ struct memblock_type {
+ 	unsigned long cnt;
+ 	unsigned long max;
+ 	phys_addr_t total_size;
++	phys_addr_t start_base;	/* start of the region */
+ 	struct memblock_region *regions;
+ 	char *name;
+ };
+diff --git a/mm/memblock.c b/mm/memblock.c
+index c337df03b..b0fecc325 100644
+--- a/mm/memblock.c
++++ b/mm/memblock.c
+@@ -578,6 +578,7 @@ static int __init_memblock memblock_add_range(struct memblock_type *type,
+ 	/* special case for empty array */
+ 	if (type->regions[0].size == 0) {
+ 		WARN_ON(type->cnt != 1 || type->total_size);
++		type->start_base = base;
+ 		type->regions[0].base = base;
+ 		type->regions[0].size = size;
+ 		type->regions[0].flags = flags;
+@@ -1611,7 +1612,7 @@ phys_addr_t __init_memblock memblock_reserved_size(void)
+ /* lowest address */
+ phys_addr_t __init_memblock memblock_start_of_DRAM(void)
+ {
+-	return memblock.memory.regions[0].base;
++	return memblock.memory.start_base;
+ }
+ 
+ phys_addr_t __init_memblock memblock_end_of_DRAM(void)
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 8e8c7e527..0ecc7bfe7 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -216,6 +216,15 @@ dtc_cpp_flags  = -Wp,-MMD,$(depfile).pre.tmp -nostdinc                    \
+ 		 $(addprefix -I,$(DTC_INCLUDE))                          \
+ 		 -undef -D__DTS__
+ 
++#Add DDR profiling for different DDR size in dtsi
++ifeq ($(CONFIG_IPQ_MEM_PROFILE),256)
++dtc_cpp_flags += -D __IPQ_MEM_PROFILE_256_MB__
++else ifeq ($(CONFIG_IPQ_FLASH_16M_PROFILE),y)
++dtc_cpp_flags += -D __IPQ_MEM_PROFILE_256_MB__
++else ifeq ($(CONFIG_IPQ_MEM_PROFILE),512)
++dtc_cpp_flags += -D __IPQ_MEM_PROFILE_512_MB__
++endif
++
+ # Useful for describing the dependency of composite objects
+ # Usage:
+ #   $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add)

root/target/linux/ipq60xx/patches-5.10/911-ipq-qcom_q6v5_wcss.patch

@@ -0,0 +1,50 @@
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -91,7 +91,7 @@
+ #define WCNSS_PAS_ID		6
+ 
+ enum {
+-	WCSS_IPQ8074,
++	WCSS_IPQ,
+ 	WCSS_QCS404,
+ };
+ 
+@@ -902,7 +902,7 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
+ 	if (!wcss->reg_base)
+ 		return -ENOMEM;
+ 
+-	if (wcss->version == WCSS_IPQ8074) {
++	if (wcss->version == WCSS_IPQ) {
+ 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
+ 		wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
+ 		if (IS_ERR(wcss->rmb_base))
+@@ -1188,6 +1188,21 @@ static const struct wcss_data wcss_ipq8074_res_init = {
+ 	.need_auto_boot = false,
+ };
+ 
++static const struct wcss_data wcss_ipq6018_res_init = {
++	.init_clock = ipq8074_init_clock,
++	.q6_firmware_name = "IPQ6018/q6_fw.mdt",
++	.m3_firmware_name = "IPQ6018/m3_fw.mdt",
++	.crash_reason_smem = WCSS_CRASH_REASON,
++	.aon_reset_required = true,
++	.wcss_q6_reset_required = true,
++	.bcr_reset_required = false,
++	.ssr_name = "q6wcss",
++	.ops = &q6v5_wcss_ipq8074_ops,
++	.requires_force_stop = true,
++	.need_mem_protection = true,
++	.need_auto_boot = false,
++};
++
+ static const struct wcss_data wcss_qcs404_res_init = {
+ 	.init_clock = qcs404_init_clock,
+ 	.init_regulator = qcs404_init_regulator,
+@@ -1207,6 +1222,7 @@ static const struct wcss_data wcss_qcs404_res_init = {
+ 
+ static const struct of_device_id q6v5_wcss_of_match[] = {
+ 	{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
++	{ .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
+ 	{ .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
+ 	{ },
+ };

root/target/linux/ipq60xx/patches-5.10/915-add-ipq6018-pcie-and-usb-phy.patch

@@ -0,0 +1,401 @@
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
+index 0cda16846..ed1be70bc 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
+@@ -143,6 +143,13 @@ static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ 	[QPHY_PCS_READY_STATUS]		= 0x168,
+ };
+ 
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++	[QPHY_SW_RESET]				= 0x00,
++	[QPHY_START_CTRL]			= 0x44,
++	[QPHY_PCS_STATUS]			= 0x14,
++	[QPHY_PCS_POWER_DOWN_CONTROL]		= 0x40,
++};
++
+ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ 	[QPHY_COM_SW_RESET]		= 0x400,
+ 	[QPHY_COM_POWER_DOWN_CONTROL]	= 0x404,
+@@ -598,6 +605,113 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+ };
+ 
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++	QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++	QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++	QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++	QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++	QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++	QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++	QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++	QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
+ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+@@ -2187,6 +2301,36 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
+ 	.pwrdn_delay_max	= 1005,		/* us */
+ };
+ 
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++	.type			= PHY_TYPE_PCIE,
++	.nlanes			= 1,
++
++	.serdes_tbl		= ipq6018_pcie_serdes_tbl,
++	.serdes_tbl_num		= ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++	.tx_tbl			= ipq6018_pcie_tx_tbl,
++	.tx_tbl_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++	.rx_tbl			= ipq6018_pcie_rx_tbl,
++	.rx_tbl_num		= ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++	.pcs_tbl		= ipq6018_pcie_pcs_tbl,
++	.pcs_tbl_num		= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++	.clk_list		= ipq8074_pciephy_clk_l,
++	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),
++	.reset_list		= ipq8074_pciephy_reset_l,
++	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),
++	.vreg_list		= NULL,
++	.num_vregs		= 0,
++	.regs			= ipq_pciephy_gen3_regs_layout,
++
++	.start_ctrl		= SERDES_START | PCS_START,
++	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
++
++	.has_phy_com_ctrl	= false,
++	.has_lane_rst		= false,
++	.has_pwrdn_delay	= true,
++	.pwrdn_delay_min	= 995,		/* us */
++	.pwrdn_delay_max	= 1005,		/* us */
++};
++
+ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
+ 	.type = PHY_TYPE_PCIE,
+ 	.nlanes = 1,
+@@ -3858,6 +4002,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ 	}, {
+ 		.compatible = "qcom,ipq8074-qmp-pcie-phy",
+ 		.data = &ipq8074_pciephy_cfg,
++	}, {
++		.compatible = "qcom,ipq6018-qmp-pcie-phy",
++		.data = &ipq6018_pciephy_cfg,
++	}, {
++		.compatible = "qcom,ipq6018-qmp-usb3-phy",
++		.data = &ipq8074_usb3phy_cfg,
+ 	}, {
+ 		.compatible = "qcom,sc7180-qmp-usb3-phy",
+ 		.data = &sc7180_usb3phy_cfg,
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
+index b7c530088..3de403f6b 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
++++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
+@@ -6,6 +6,138 @@
+ #ifndef QCOM_PHY_QMP_H_
+ #define QCOM_PHY_QMP_H_
+ 
++/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
++
++#define QSERDES_PLL_BG_TIMER				0x00c
++#define QSERDES_PLL_SSC_PER1				0x01c
++#define QSERDES_PLL_SSC_PER2				0x020
++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0		0x024
++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0		0x028
++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1		0x02c
++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1		0x030
++#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN			0x03c
++#define QSERDES_PLL_CLK_ENABLE1				0x040
++#define QSERDES_PLL_SYS_CLK_CTRL			0x044
++#define QSERDES_PLL_SYSCLK_BUF_ENABLE			0x048
++#define QSERDES_PLL_PLL_IVCO				0x050
++#define QSERDES_PLL_LOCK_CMP1_MODE0			0x054
++#define QSERDES_PLL_LOCK_CMP2_MODE0			0x058
++#define QSERDES_PLL_LOCK_CMP1_MODE1			0x060
++#define QSERDES_PLL_LOCK_CMP2_MODE1			0x064
++#define QSERDES_PLL_BG_TRIM				0x074
++#define QSERDES_PLL_CLK_EP_DIV_MODE0			0x078
++#define QSERDES_PLL_CLK_EP_DIV_MODE1			0x07c
++#define QSERDES_PLL_CP_CTRL_MODE0			0x080
++#define QSERDES_PLL_CP_CTRL_MODE1			0x084
++#define QSERDES_PLL_PLL_RCTRL_MODE0			0x088
++#define QSERDES_PLL_PLL_RCTRL_MODE1			0x08C
++#define QSERDES_PLL_PLL_CCTRL_MODE0			0x090
++#define QSERDES_PLL_PLL_CCTRL_MODE1			0x094
++#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x0a4
++#define QSERDES_PLL_SYSCLK_EN_SEL			0x0a8
++#define QSERDES_PLL_RESETSM_CNTRL			0x0b0
++#define QSERDES_PLL_LOCK_CMP_EN				0x0c4
++#define QSERDES_PLL_DEC_START_MODE0			0x0cc
++#define QSERDES_PLL_DEC_START_MODE1			0x0d0
++#define QSERDES_PLL_DIV_FRAC_START1_MODE0		0x0d8
++#define QSERDES_PLL_DIV_FRAC_START2_MODE0		0x0dc
++#define QSERDES_PLL_DIV_FRAC_START3_MODE0		0x0e0
++#define QSERDES_PLL_DIV_FRAC_START1_MODE1		0x0e4
++#define QSERDES_PLL_DIV_FRAC_START2_MODE1		0x0e8
++#define QSERDES_PLL_DIV_FRAC_START3_MODE1		0x0eC
++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0		0x100
++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0		0x104
++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1		0x108
++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1		0x10c
++#define QSERDES_PLL_VCO_TUNE_MAP			0x120
++#define QSERDES_PLL_VCO_TUNE1_MODE0			0x124
++#define QSERDES_PLL_VCO_TUNE2_MODE0			0x128
++#define QSERDES_PLL_VCO_TUNE1_MODE1			0x12c
++#define QSERDES_PLL_VCO_TUNE2_MODE1			0x130
++#define QSERDES_PLL_VCO_TUNE_TIMER1			0x13c
++#define QSERDES_PLL_VCO_TUNE_TIMER2			0x140
++#define QSERDES_PLL_CLK_SELECT				0x16c
++#define QSERDES_PLL_HSCLK_SEL				0x170
++#define QSERDES_PLL_CORECLK_DIV				0x17c
++#define QSERDES_PLL_CORE_CLK_EN				0x184
++#define QSERDES_PLL_CMN_CONFIG				0x18c
++#define QSERDES_PLL_SVS_MODE_CLK_SEL			0x194
++#define QSERDES_PLL_CORECLK_DIV_MODE1			0x1b4
++
++/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */
++
++#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX		0x03c
++#define QSERDES_TX0_HIGHZ_DRVR_EN			0x058
++#define QSERDES_TX0_LANE_MODE_1				0x084
++#define QSERDES_TX0_RCV_DETECT_LVL_2			0x09c
++
++/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */
++
++#define QSERDES_RX0_UCDR_FO_GAIN			0x008
++#define QSERDES_RX0_UCDR_SO_GAIN			0x014
++#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE	0x034
++#define QSERDES_RX0_UCDR_PI_CONTROLS			0x044
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2		0x0ec
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3		0x0f0
++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4		0x0f4
++#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW			0x0f8
++#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH		0x0fc
++#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x110
++#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2		0x114
++#define QSERDES_RX0_SIGDET_ENABLES			0x118
++#define QSERDES_RX0_SIGDET_CNTRL			0x11c
++#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL		0x124
++#define QSERDES_RX0_RX_MODE_00_LOW			0x170
++#define QSERDES_RX0_RX_MODE_00_HIGH			0x174
++#define QSERDES_RX0_RX_MODE_00_HIGH2			0x178
++#define QSERDES_RX0_RX_MODE_00_HIGH3			0x17c
++#define QSERDES_RX0_RX_MODE_00_HIGH4			0x180
++#define QSERDES_RX0_RX_MODE_01_LOW			0x184
++#define QSERDES_RX0_RX_MODE_01_HIGH			0x188
++#define QSERDES_RX0_RX_MODE_01_HIGH2			0x18c
++#define QSERDES_RX0_RX_MODE_01_HIGH3			0x190
++#define QSERDES_RX0_RX_MODE_01_HIGH4			0x194
++#define QSERDES_RX0_RX_MODE_10_LOW			0x198
++#define QSERDES_RX0_RX_MODE_10_HIGH			0x19c
++#define QSERDES_RX0_RX_MODE_10_HIGH2			0x1a0
++#define QSERDES_RX0_RX_MODE_10_HIGH3			0x1a4
++#define QSERDES_RX0_RX_MODE_10_HIGH4			0x1a8
++#define QSERDES_RX0_DFE_EN_TIMER			0x1b4
++
++/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
++
++#define PCS_COM_FLL_CNTRL1				0x098
++#define PCS_COM_FLL_CNTRL2				0x09c
++#define PCS_COM_FLL_CNT_VAL_L				0x0a0
++#define PCS_COM_FLL_CNT_VAL_H_TOL			0x0a4
++#define PCS_COM_FLL_MAN_CODE				0x0a8
++#define PCS_COM_REFGEN_REQ_CONFIG1			0x0dc
++#define PCS_COM_G12S1_TXDEEMPH_M3P5DB			0x16c
++#define PCS_COM_RX_SIGDET_LVL				0x188
++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4
++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8
++#define PCS_COM_RX_DCC_CAL_CONFIG			0x1d8
++#define PCS_COM_EQ_CONFIG5				0x1ec
++
++/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
++
++#define PCS_PCIE_POWER_STATE_CONFIG2			0x40c
++#define PCS_PCIE_POWER_STATE_CONFIG4			0x414
++#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE			0x41c
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L		0x440
++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H		0x444
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L		0x448
++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H		0x44c
++#define PCS_PCIE_OSC_DTCT_CONFIG2			0x45c
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2			0x478
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4			0x480
++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5			0x484
++#define PCS_PCIE_OSC_DTCT_ACTIONS			0x490
++#define PCS_PCIE_EQ_CONFIG1				0x4a0
++#define PCS_PCIE_EQ_CONFIG2				0x4a4
++#define PCS_PCIE_PRESET_P10_PRE				0x4bc
++#define PCS_PCIE_PRESET_P10_POST			0x4e0
++
+ /* Only for QMP V2 PHY - QSERDES COM registers */
+ #define QSERDES_COM_BG_TIMER				0x00c
+ #define QSERDES_COM_SSC_EN_CENTER			0x010
+diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
+index f531043ec..2192eb6b3 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
++++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
+@@ -22,6 +22,7 @@
+ 
+ #include <dt-bindings/phy/phy-qcom-qusb2.h>
+ 
++#define QUSB2PHY_PLL			0x0
+ #define QUSB2PHY_PLL_TEST		0x04
+ #define CLK_REF_SEL			BIT(7)
+ 
+@@ -135,6 +136,35 @@ enum qusb2phy_reg_layout {
+ 	QUSB2PHY_INTR_CTRL,
+ };
+ 
++static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
++	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
++	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
++};
++
++static const unsigned int ipq6018_regs_layout[] = {
++	[QUSB2PHY_PLL_STATUS]              = 0x38,
++	[QUSB2PHY_PORT_TUNE1]              = 0x80,
++	[QUSB2PHY_PORT_TUNE2]              = 0x84,
++	[QUSB2PHY_PORT_TUNE3]              = 0x88,
++	[QUSB2PHY_PORT_TUNE4]              = 0x8C,
++	[QUSB2PHY_PORT_TUNE5]              = 0x90,
++	[QUSB2PHY_PORT_TEST1]              = 0x98,
++	[QUSB2PHY_PORT_TEST2]              = 0x9C,
++	[QUSB2PHY_PORT_POWERDOWN]          = 0xB4,
++	[QUSB2PHY_INTR_CTRL]               = 0xBC,
++};
++
+ static const unsigned int msm8996_regs_layout[] = {
+ 	[QUSB2PHY_PLL_STATUS]		= 0x38,
+ 	[QUSB2PHY_PORT_TUNE1]		= 0x80,
+@@ -270,6 +300,17 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
+ 	.update_tune1_with_efuse = true,
+ };
+ 
++static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
++	.tbl            = ipq6018_init_tbl,
++	.tbl_num        = ARRAY_SIZE(ipq6018_init_tbl),
++	.regs           = ipq6018_regs_layout,
++
++	.disable_ctrl   = POWER_DOWN,
++	.mask_core_ready = PLL_LOCKED,
++	/* autoresume not used */
++	.autoresume_en   = BIT(0),
++};
++
+ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
+ 	.tbl		= qusb2_v2_init_tbl,
+ 	.tbl_num	= ARRAY_SIZE(qusb2_v2_init_tbl),
+@@ -816,6 +857,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
+ 	{
+ 		.compatible	= "qcom,ipq8074-qusb2-phy",
+ 		.data		= &msm8996_phy_cfg,
++	}, {
++		.compatible	= "qcom,ipq6018-qusb2-phy",
++		.data		= &ipq6018_phy_cfg,
+ 	}, {
+ 		.compatible	= "qcom,msm8996-qusb2-phy",
+ 		.data		= &msm8996_phy_cfg,

root/target/linux/ipq60xx/patches-5.10/916-change-ipq6018-usb3.0-phy-qcom-qmp.patch

@@ -0,0 +1,127 @@
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
+index ed1be70bc..459551b80 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
+@@ -305,6 +305,82 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+ };
+ 
++static const struct qmp_phy_init_tbl ipq6018_usb3_serdes_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL,0x1a),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT,0x30),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM,0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL,0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG,0x06),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO,0x0f),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL,0x06),
++	/* PLL and Loop filter settings */
++	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0,0x68),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0,0xAB),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0,0xAA),
++	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0,0x02),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0,0x09),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0,0x16),
++	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0,0x28),
++	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0xA0),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0,0xAA),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0,0x29),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER,0x0a),
++	/* SSC settings */
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER,0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1,0x7D),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2,0x01),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2,0x00),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1,0x0A),
++	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2,0x05),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_usb3_rx_tbl[] = {
++	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN,0x06),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1,0x77),
++	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2,0x80),
++	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL,0x03),
++	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL,0x16),
++	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES,0x00),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_usb3_pcs_tbl[] = {
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0,0x17),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0,0x0f),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2,0x83),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1,0x02),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L,0x09),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL,0xa2),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE,0x85),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1,0xd1),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2,0x1f),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3,0x47),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2,0x1b),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME,0x75),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME,0x13),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK,0x86),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK,0x04),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME,0x44),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L,0xe7),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H,0x03),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L,0x40),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H,0x00),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL,0x88),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0,0x17),
++	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0,0x0f),
++};
++
+ static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
+ 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+@@ -2183,6 +2259,30 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
+ 	.pwrdn_ctrl		= SW_PWRDN,
+ };
+ 
++static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
++	.type			= PHY_TYPE_USB3,
++	.nlanes			= 1,
++
++	.serdes_tbl		= ipq6018_usb3_serdes_tbl,
++	.serdes_tbl_num		= ARRAY_SIZE(ipq6018_usb3_serdes_tbl),
++	.tx_tbl			= msm8996_usb3_tx_tbl,
++	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
++	.rx_tbl			= ipq6018_usb3_rx_tbl,
++	.rx_tbl_num		= ARRAY_SIZE(ipq6018_usb3_rx_tbl),
++	.pcs_tbl		= ipq6018_usb3_pcs_tbl,
++	.pcs_tbl_num		= ARRAY_SIZE(ipq6018_usb3_pcs_tbl),
++	.clk_list		= msm8996_phy_clk_l,
++	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
++	.reset_list		= msm8996_usb3phy_reset_l,
++	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
++	.vreg_list		= qmp_phy_vreg_l,
++	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
++	.regs			= usb3phy_regs_layout,
++
++	.start_ctrl		= SERDES_START | PCS_START,
++	.pwrdn_ctrl		= SW_PWRDN,
++};
++
+ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
+ 	.type			= PHY_TYPE_PCIE,
+ 	.nlanes			= 3,
+@@ -4007,7 +4107,7 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
+ 		.data = &ipq6018_pciephy_cfg,
+ 	}, {
+ 		.compatible = "qcom,ipq6018-qmp-usb3-phy",
+-		.data = &ipq8074_usb3phy_cfg,
++		.data = &ipq6018_usb3phy_cfg,
+ 	}, {
+ 		.compatible = "qcom,sc7180-qmp-usb3-phy",
+ 		.data = &sc7180_usb3phy_cfg,

root/target/linux/ipq60xx/patches-5.10/917-change-ipq6018-dwc3-core.patch

@@ -0,0 +1,122 @@
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 1580d51ae..3ad86d7ea 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -26,6 +26,7 @@
+ #include <linux/acpi.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/reset.h>
++#include <linux/bitfield.h>
+ 
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
+@@ -335,6 +336,48 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
+ 	}
+ }
+ 
++/**
+++ * dwc3_ref_clk_adjustment - Reference clock settings for SOF and ITP
+++ *		Default reference clock configurations are calculated assuming
+++ *		19.2 MHz clock source. For other clock source, this will set
+++ *		configuration in DWC3_GFLADJ register
+++ * @dwc: Pointer to our controller context structure
+++ */
++static void dwc3_ref_clk_adjustment(struct dwc3 *dwc)
++{
++	u32 reg;
++
++	if (dwc->ref_clk_adj == 0)
++		return;
++
++	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
++	reg &= ~DWC3_GFLADJ_REFCLK_MASK;
++	reg |=  FIELD_PREP(DWC3_GFLADJ_REFCLK_MASK, dwc->ref_clk_adj);
++	dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
++}
++
++/**
++ * dwc3_ref_clk_period - Reference clock period configuration
++ *		Default reference clock period depends on hardware
++ *		configuration. For systems with reference clock that differs
++ *		from the default, this will set clock period in DWC3_GUCTL
++ *		register.
++ * @dwc: Pointer to our controller context structure
++ * @ref_clk_per: reference clock period in ns
++ */
++static void dwc3_ref_clk_period(struct dwc3 *dwc)
++{
++	u32 reg;
++
++	if (dwc->ref_clk_per == 0)
++		return;
++
++	reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
++	reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
++	reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per);
++	dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
++}
++
+ /**
+  * dwc3_free_one_event_buffer - Frees one event buffer
+  * @dwc: Pointer to our controller context structure
+@@ -1004,6 +1047,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
+ 	/* Adjust Frame Length */
+ 	dwc3_frame_length_adjustment(dwc);
+ 
++	/* Adjust Reference Clock Settings */
++	dwc3_ref_clk_adjustment(dwc);
++
++	/* Adjust Reference Clock Period */
++	dwc3_ref_clk_period(dwc);
++
+ 	dwc3_set_incr_burst_type(dwc);
+ 
+ 	usb_phy_set_suspend(dwc->usb2_phy, 0);
+@@ -1375,6 +1424,10 @@ static void dwc3_get_properties(struct dwc3 *dwc)
+ 				    &dwc->hsphy_interface);
+ 	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
+ 				 &dwc->fladj);
++	device_property_read_u32(dev, "snps,ref-clock-adjustment",
++				 &dwc->ref_clk_adj);
++	device_property_read_u32(dev, "snps,ref-clock-period-ns",
++				 &dwc->ref_clk_per);
+ 
+ 	dwc->dis_metastability_quirk = device_property_read_bool(dev,
+ 				"snps,dis_metastability_quirk");
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+index 79e1b82e5..a95b5003f 100644
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -380,6 +380,14 @@
+ #define DWC3_GFLADJ_30MHZ_SDBND_SEL		BIT(7)
+ #define DWC3_GFLADJ_30MHZ_MASK			0x3f
+ 
++/* Global User Control Register*/
++#define DWC3_GUCTL_REFCLKPER_MASK		0xffc00000
++#define DWC3_GUCTL_REFCLKPER_SEL		22
++
++/* Global reference clock Adjustment Register */
++#define DWC3_GFLADJ_REFCLK_MASK			0xffffff00
++#define DWC3_GFLADJ_REFCLK_SEL			8
++
+ /* Global User Control Register 2 */
+ #define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
+ 
+@@ -958,6 +966,8 @@ struct dwc3_scratchpad_array {
+  * @regs: base address for our registers
+  * @regs_size: address space size
+  * @fladj: frame length adjustment
++ * @ref_clk_adj: reference clock adjustment
++ * @ref_clk_per: reference clock period configuration
+  * @irq_gadget: peripheral controller's IRQ number
+  * @otg_irq: IRQ number for OTG IRQs
+  * @current_otg_role: current role of operation while using the OTG block
+@@ -1124,6 +1134,8 @@ struct dwc3 {
+ 	enum usb_dr_mode	role_switch_default_mode;
+ 
+ 	u32			fladj;
++	u32			ref_clk_adj;
++	u32			ref_clk_per;
+ 	u32			irq_gadget;
+ 	u32			otg_irq;
+ 	u32			current_otg_role;

root/target/linux/ipq60xx/patches-5.10/918-bam-dma.patch

@@ -0,0 +1,118 @@
+diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
+index 4eeb8bb27..ad205ea7e 100644
+--- a/drivers/dma/qcom/bam_dma.c
++++ b/drivers/dma/qcom/bam_dma.c
+@@ -391,6 +391,8 @@ struct bam_device {
+ 
+ 	const struct reg_offset_data *layout;
+ 
++	struct clk *iface_clk;
++
+ 	struct clk *bamclk;
+ 	int irq;
+ 
+@@ -1274,10 +1276,26 @@ static int bam_dma_probe(struct platform_device *pdev)
+ 			dev_err(bdev->dev, "num-ees unspecified in dt\n");
+ 	}
+ 
++	bdev->iface_clk = devm_clk_get_optional(bdev->dev, "iface_clk");
++	if (IS_ERR(bdev->iface_clk)) {
++		if (!bdev->controlled_remotely)
++			return PTR_ERR(bdev->iface_clk);
++
++		bdev->iface_clk = NULL;
++	}
++
++	ret = clk_prepare_enable(bdev->iface_clk);
++	if (ret) {
++		dev_err(bdev->dev, "failed to prepare/enable iface clock\n");
++		return ret;
++	}
++
+ 	bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
+ 	if (IS_ERR(bdev->bamclk)) {
+-		if (!bdev->controlled_remotely)
+-			return PTR_ERR(bdev->bamclk);
++		if (!bdev->controlled_remotely) {
++			ret = PTR_ERR(bdev->bamclk);
++			goto err_disable_iface_clk;
++		}
+ 
+ 		bdev->bamclk = NULL;
+ 	}
+@@ -1285,7 +1303,7 @@ static int bam_dma_probe(struct platform_device *pdev)
+ 	ret = clk_prepare_enable(bdev->bamclk);
+ 	if (ret) {
+ 		dev_err(bdev->dev, "failed to prepare/enable clock\n");
+-		return ret;
++		goto err_disable_iface_clk;
+ 	}
+ 
+ 	ret = bam_init(bdev);
+@@ -1377,6 +1395,8 @@ static int bam_dma_probe(struct platform_device *pdev)
+ 	tasklet_kill(&bdev->task);
+ err_disable_clk:
+ 	clk_disable_unprepare(bdev->bamclk);
++err_disable_iface_clk:
++	clk_disable_unprepare(bdev->iface_clk);
+ 
+ 	return ret;
+ }
+@@ -1411,6 +1431,7 @@ static int bam_dma_remove(struct platform_device *pdev)
+ 	tasklet_kill(&bdev->task);
+ 
+ 	clk_disable_unprepare(bdev->bamclk);
++	clk_disable_unprepare(bdev->iface_clk);
+ 
+ 	return 0;
+ }
+@@ -1420,6 +1441,7 @@ static int __maybe_unused bam_dma_runtime_suspend(struct device *dev)
+ 	struct bam_device *bdev = dev_get_drvdata(dev);
+ 
+ 	clk_disable(bdev->bamclk);
++	clk_disable(bdev->iface_clk);
+ 
+ 	return 0;
+ }
+@@ -1429,8 +1451,15 @@ static int __maybe_unused bam_dma_runtime_resume(struct device *dev)
+ 	struct bam_device *bdev = dev_get_drvdata(dev);
+ 	int ret;
+ 
++	ret = clk_enable(bdev->iface_clk);
++	if (ret < 0) {
++		dev_err(dev, "iface clk_enable failed: %d\n", ret);
++		return ret;
++	}
++
+ 	ret = clk_enable(bdev->bamclk);
+ 	if (ret < 0) {
++		clk_disable(bdev->iface_clk);
+ 		dev_err(dev, "clk_enable failed: %d\n", ret);
+ 		return ret;
+ 	}
+@@ -1446,6 +1475,7 @@ static int __maybe_unused bam_dma_suspend(struct device *dev)
+ 		pm_runtime_force_suspend(dev);
+ 
+ 	clk_unprepare(bdev->bamclk);
++	clk_unprepare(bdev->iface_clk);
+ 
+ 	return 0;
+ }
+@@ -1455,10 +1485,16 @@ static int __maybe_unused bam_dma_resume(struct device *dev)
+ 	struct bam_device *bdev = dev_get_drvdata(dev);
+ 	int ret;
+ 
+-	ret = clk_prepare(bdev->bamclk);
++	ret = clk_prepare(bdev->iface_clk);
+ 	if (ret)
+ 		return ret;
+ 
++	ret = clk_prepare(bdev->bamclk);
++	if (ret) {
++		clk_unprepare(bdev->iface_clk);
++		return ret;
++	}
++
+ 	if (!bdev->controlled_remotely)
+ 		pm_runtime_force_resume(dev);
+ 

root/target/linux/ipq60xx/patches-5.10/921-socinfo.patch

@@ -0,0 +1,544 @@
+diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
+index ce7d9acd6..8f3715471 100644
+--- a/drivers/soc/qcom/socinfo.c
++++ b/drivers/soc/qcom/socinfo.c
+@@ -14,6 +14,7 @@
+ #include <linux/string.h>
+ #include <linux/sys_soc.h>
+ #include <linux/types.h>
++#include <soc/qcom/socinfo.h>
+ 
+ /*
+  * SoC version type with major number in the upper 16 bits and minor
+@@ -224,26 +225,26 @@ static const struct soc_id soc_id[] = {
+ 	{ 312, "APQ8096SG" },
+ 	{ 318, "SDM630" },
+ 	{ 321, "SDM845" },
+-	{ 323, "IPQ8074" },
++	{ CPU_IPQ8074, "IPQ8074" },
+ 	{ 341, "SDA845" },
+-	{ 342, "IPQ8072" },
+-	{ 343, "IPQ8076" },
+-	{ 344, "IPQ8078" },
++	{ CPU_IPQ8072, "IPQ8072" },
++	{ CPU_IPQ8076, "IPQ8076" },
++	{ CPU_IPQ8078, "IPQ8078" },
+ 	{ 356, "SM8250" },
+-	{ 375, "IPQ8070" },
+-	{ 376, "IPQ8071" },
+-	{ 389, "IPQ8072A" },
+-	{ 390, "IPQ8074A" },
+-	{ 391, "IPQ8076A" },
+-	{ 392, "IPQ8078A" },
+-	{ 395, "IPQ8070A" },
+-	{ 396, "IPQ8071A" },
+-	{ 402, "IPQ6018" },
+-	{ 403, "IPQ6028" },
+-	{ 421, "IPQ6000" },
+-	{ 422, "IPQ6010" },
++	{ CPU_IPQ8070, "IPQ8070" },
++	{ CPU_IPQ8071, "IPQ8071" },
++	{ CPU_IPQ8072A, "IPQ8072A" },
++	{ CPU_IPQ8074A, "IPQ8074A" },
++	{ CPU_IPQ8076A, "IPQ8076A" },
++	{ CPU_IPQ8078A, "IPQ8078A" },
++	{ CPU_IPQ8070A, "IPQ8070A" },
++	{ CPU_IPQ8071A, "IPQ8071A" },
++	{ CPU_IPQ6018, "IPQ6018" },
++	{ CPU_IPQ6028, "IPQ6028" },
++	{ CPU_IPQ6000, "IPQ6000" },
++	{ CPU_IPQ6010, "IPQ6010" },
+ 	{ 425, "SC7180" },
+-	{ 453, "IPQ6005" },
++	{ CPU_IPQ6005, "IPQ6005" },
+ };
+ 
+ static const char *socinfo_machine(struct device *dev, unsigned int id)
+@@ -515,7 +516,7 @@ static int qcom_socinfo_probe(struct platform_device *pdev)
+ 	if (!qs)
+ 		return -ENOMEM;
+ 
+-	qs->attr.family = "Snapdragon";
++	qs->attr.family = "IPQ";
+ 	qs->attr.machine = socinfo_machine(&pdev->dev,
+ 					   le32_to_cpu(info->id));
+ 	qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
+@@ -534,6 +535,9 @@ static int qcom_socinfo_probe(struct platform_device *pdev)
+ 
+ 	socinfo_debugfs_init(qs, info);
+ 
++	pr_info("CPU: %s, SoC Version: %s\n", qs->attr.machine,
++						qs->attr.revision);
++
+ 	/* Feed the soc specific unique data into entropy pool */
+ 	add_device_randomness(info, item_size);
+ 
+diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h
+new file mode 100644
+index 000000000..db4344616
+--- /dev/null
++++ b/include/soc/qcom/socinfo.h
+@@ -0,0 +1,463 @@
++/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_
++#define _ARCH_ARM_MACH_MSM_SOCINFO_H_
++
++#include <linux/of.h>
++
++#define CPU_IPQ8074 323
++#define CPU_IPQ8072 342
++#define CPU_IPQ8076 343
++#define CPU_IPQ8078 344
++#define CPU_IPQ8070 375
++#define CPU_IPQ8071 376
++
++#define CPU_IPQ8072A 389
++#define CPU_IPQ8074A 390
++#define CPU_IPQ8076A 391
++#define CPU_IPQ8078A 392
++#define CPU_IPQ8070A 395
++#define CPU_IPQ8071A 396
++
++#define CPU_IPQ8172  397
++#define CPU_IPQ8173  398
++#define CPU_IPQ8174  399
++
++#define CPU_IPQ6018 402
++#define CPU_IPQ6028 403
++#define CPU_IPQ6000 421
++#define CPU_IPQ6010 422
++#define CPU_IPQ6005 453
++
++#define CPU_IPQ5010 446
++#define CPU_IPQ5018 447
++#define CPU_IPQ5028 448
++#define CPU_IPQ5000 503
++#define CPU_IPQ0509 504
++#define CPU_IPQ0518 505
++
++#define CPU_IPQ9514 510
++#define CPU_IPQ9554 512
++#define CPU_IPQ9570 513
++#define CPU_IPQ9574 514
++#define CPU_IPQ9550 511
++#define CPU_IPQ9510 521
++
++static inline int read_ipq_soc_version_major(void)
++{
++	const int *prop;
++	prop = of_get_property(of_find_node_by_path("/"), "soc_version_major",
++				NULL);
++
++	if (!prop)
++		return -EINVAL;
++
++	return le32_to_cpu(*prop);
++}
++
++static inline int read_ipq_cpu_type(void)
++{
++	const int *prop;
++	prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL);
++	/*
++	 * Return Default CPU type if "cpu_type" property is not found in DTSI
++	 */
++	if (!prop)
++		return CPU_IPQ8074;
++
++	return le32_to_cpu(*prop);
++}
++
++static inline int cpu_is_ipq8070(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8070;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8071(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8071;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8072(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8072;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8074(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8074;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8076(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8076;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8078(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8078;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8072a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8072A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8074a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8074A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8076a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8076A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8078a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8078A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8070a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8070A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8071a(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8071A;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8172(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8172;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8173(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8173;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq8174(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ8174;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq6018(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ6018;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq6028(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ6028;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq6000(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ6000;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq6010(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ6010;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq6005(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ6005;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq5010(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ5010;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq5018(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ5018;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq5028(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ5028;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq5000(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ5000;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq0509(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ0509;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq0518(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ0518;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9514(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9514;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9554(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9554;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9570(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9570;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9574(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9574;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9550(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9550;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq9510(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return read_ipq_cpu_type() == CPU_IPQ9510;
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq807x(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq8072() || cpu_is_ipq8074() ||
++		cpu_is_ipq8076() || cpu_is_ipq8078() ||
++		cpu_is_ipq8070() || cpu_is_ipq8071() ||
++		cpu_is_ipq8072a() || cpu_is_ipq8074a() ||
++		cpu_is_ipq8076a() || cpu_is_ipq8078a() ||
++		cpu_is_ipq8070a() || cpu_is_ipq8071a() ||
++		cpu_is_ipq8172() || cpu_is_ipq8173() ||
++		cpu_is_ipq8174();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq60xx(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq6018() || cpu_is_ipq6028() ||
++		cpu_is_ipq6000() || cpu_is_ipq6010() ||
++		cpu_is_ipq6005();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq50xx(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq5010() || cpu_is_ipq5018() ||
++		cpu_is_ipq5028() || cpu_is_ipq5000() ||
++		cpu_is_ipq0509() || cpu_is_ipq0518();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_ipq95xx(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq9514() || cpu_is_ipq9554() ||
++		cpu_is_ipq9570() || cpu_is_ipq9574() ||
++		cpu_is_ipq9550() || cpu_is_ipq9510();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_nss_crypto_enabled(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
++		cpu_is_ipq50xx() || cpu_is_ipq9570() ||
++		cpu_is_ipq9550() || cpu_is_ipq9574() ||
++		cpu_is_ipq9554();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_internal_wifi_enabled(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
++		cpu_is_ipq50xx() || cpu_is_ipq9514() ||
++		cpu_is_ipq9554() || cpu_is_ipq9574();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_uniphy1_enabled(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq807x() || cpu_is_ipq60xx() ||
++		cpu_is_ipq9554() || cpu_is_ipq9570() ||
++		cpu_is_ipq9574() || cpu_is_ipq9550();
++#else
++	return 0;
++#endif
++}
++
++static inline int cpu_is_uniphy2_enabled(void)
++{
++#ifdef CONFIG_ARCH_QCOM
++	return  cpu_is_ipq807x() || cpu_is_ipq9570() ||
++		cpu_is_ipq9574();
++#else
++	return 0;
++#endif
++}
++
++#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */