mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add r5s support. From coolsnowwold repo
This commit is contained in:
parent
f2bf060a04
commit
2d9c2e0625
112 changed files with 25981 additions and 75 deletions
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@ -1,5 +1,6 @@
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CONFIG_64BIT=y
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CONFIG_AF_UNIX_OOB=y
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# CONFIG_ARCH_BCM4908 is not set
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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@ -19,7 +20,11 @@ CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_CRYPTO=y
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CONFIG_ARM64_EPAN=y
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# CONFIG_ARM64_ERRATUM_1165522 is not set
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# CONFIG_ARM64_ERRATUM_1286807 is not set
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# CONFIG_ARM64_ERRATUM_1418040 is not set
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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@ -28,6 +33,7 @@ CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_845719=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_ERRATUM_1742098=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
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CONFIG_ARM64_MODULE_PLTS=y
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@ -51,17 +57,20 @@ CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_CPUIDLE=y
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# CONFIG_ARM_FFA_TRANSPORT is not set
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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CONFIG_ARM_MHU_V2=y
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# CONFIG_ARM_MHU_V2 is not set
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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CONFIG_ARM_RK3328_DMC_DEVFREQ=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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CONFIG_ARM_SCMI_PROTOCOL=y
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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@ -74,6 +83,7 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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# CONFIG_BCM_VK is not set
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CONFIG_BINARY_PRINTF=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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@ -89,6 +99,7 @@ CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BLOCK_COMPAT=y
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CONFIG_BRCMSTB_GISB_ARB=y
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# CONFIG_BRIDGE_CFM is not set
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
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@ -104,6 +115,7 @@ CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=5
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@ -113,8 +125,10 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK=y
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# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_ROCKCHIP=y
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CONFIG_COMMON_CLK_SCMI=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPAT=y
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CONFIG_COMPAT_32BIT_TIME=y
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@ -151,13 +165,25 @@ CONFIG_CRC16=y
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AES_ARM64=y
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CONFIG_CRYPTO_AES_ARM64_CE=y
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CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
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CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRCT10DIF=y
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CONFIG_CRYPTO_DEV_ROCKCHIP=y
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CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
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CONFIG_CRYPTO_CRYPTD=y
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CONFIG_CRYPTO_GHASH_ARM64_CE=y
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CONFIG_CRYPTO_GF128MUL=y
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CONFIG_CRYPTO_LIB_SHA256=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_SIMD=y
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# CONFIG_CXL_BUS is not set
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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# CONFIG_DEBUG_IRQFLAGS is not set
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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@ -166,16 +192,21 @@ CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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# CONFIG_DMABUF_DEBUG is not set
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# CONFIG_DMABUF_SYSFS_STATS is not set
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CONFIG_DMADEVICES=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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# CONFIG_DMA_MAP_BENCHMARK is not set
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CONFIG_DMA_OF=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_REMAP=y
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# CONFIG_DMA_RESTRICTED_POOL is not set
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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# CONFIG_DRM_ROCKCHIP is not set
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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@ -189,12 +220,14 @@ CONFIG_ENERGY_MODEL=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXTCON=y
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# CONFIG_EXTCON_USBC_TUSB320 is not set
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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# CONFIG_FORTIFY_SOURCE is not set
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# CONFIG_FUJITSU_ERRATUM_010001 is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_FRAME_WARN=2048
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CONFIG_FS_IOMAP=y
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@ -238,6 +271,7 @@ CONFIG_GPIO_DWAPB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_GPIO_ROCKCHIP=y
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# CONFIG_GUP_TEST is not set
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CONFIG_HANDLE_DOMAIN_IRQ=y
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# CONFIG_HARDENED_USERCOPY is not set
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CONFIG_HARDIRQS_SW_RESEND=y
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@ -256,6 +290,11 @@ CONFIG_HUGETLB_PAGE=y
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CONFIG_HWMON=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HW_CONSOLE=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_ROCKCHIP=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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@ -271,12 +310,11 @@ CONFIG_INPUT_KEYBOARD=y
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CONFIG_INPUT_LEDS=y
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CONFIG_INPUT_MATRIXKMAP=y
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# CONFIG_INPUT_MISC is not set
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# CONFIG_INPUT_RK805_PWRKEY is not set
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CONFIG_IOMMU_API=y
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# CONFIG_IOMMU_DEBUGFS is not set
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# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
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# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
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CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
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CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
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# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
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CONFIG_IOMMU_DMA=y
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CONFIG_IOMMU_IOVA=y
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CONFIG_IOMMU_IO_PGTABLE=y
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@ -299,6 +337,8 @@ CONFIG_JUMP_LABEL=y
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CONFIG_KALLSYMS=y
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CONFIG_KEXEC_CORE=y
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CONFIG_KEXEC_FILE=y
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# CONFIG_KEXEC_SIG is not set
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# CONFIG_KFENCE is not set
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CONFIG_KSM=y
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# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
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CONFIG_LEDS_GPIO=y
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@ -306,10 +346,13 @@ CONFIG_LEDS_PWM=y
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CONFIG_LEDS_SYSCON=y
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CONFIG_LEDS_TRIGGER_CPU=y
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CONFIG_LEDS_TRIGGER_PANIC=y
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# CONFIG_LEDS_TRIGGER_TTY is not set
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=16
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CONFIG_LIBCRC32C=y
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CONFIG_LIBFDT=y
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# CONFIG_LITEX_SOC_CONTROLLER is not set
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CONFIG_LLD_VERSION=0
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CONFIG_LOCALVERSION_AUTO=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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@ -328,6 +371,7 @@ CONFIG_MDIO_DEVRES=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MEMORY_ISOLATION=y
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CONFIG_MFD_CORE=y
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# CONFIG_MFD_INTEL_PMT is not set
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# CONFIG_MFD_KHADAS_MCU is not set
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CONFIG_MFD_RK808=y
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CONFIG_MFD_SYSCON=y
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@ -350,11 +394,16 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MODULES_USE_ELF_RELA=y
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CONFIG_MOTORCOMM_PHY=y
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CONFIG_MQ_IOSCHED_DEADLINE=y
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# CONFIG_MTD_CFI is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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# CONFIG_MTD_COMPLEX_MAPPINGS is not set
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# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
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CONFIG_MTD_SPI_NOR=y
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# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
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CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
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# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
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CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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@ -369,7 +418,9 @@ CONFIG_NOP_USB_XCEIV=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_NR_CPUS=256
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# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
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CONFIG_NVMEM=y
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# CONFIG_NVMEM_RMEM is not set
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CONFIG_NVMEM_SYSFS=y
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CONFIG_NVME_CORE=y
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# CONFIG_NVME_HWMON is not set
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@ -384,6 +435,7 @@ CONFIG_OF_IOMMU=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_NET=y
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CONFIG_OF_OVERLAY=y
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CONFIG_OF_RESOLVE=y
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CONFIG_OLD_SIGSUSPEND3=y
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@ -403,9 +455,12 @@ CONFIG_PCIEASPM_DEFAULT=y
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# CONFIG_PCIEASPM_POWERSAVE is not set
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# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_DW=y
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CONFIG_PCIE_DW_HOST=y
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# CONFIG_PCIE_MICROCHIP_HOST is not set
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CONFIG_PCIE_PME=y
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CONFIG_PCIE_ROCKCHIP=y
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# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
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CONFIG_PCIE_ROCKCHIP_DW_HOST=y
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CONFIG_PCIE_ROCKCHIP_HOST=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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@ -424,10 +479,13 @@ CONFIG_PHY_ROCKCHIP_EMMC=y
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# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
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# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
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CONFIG_PHY_ROCKCHIP_PCIE=y
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CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
|
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CONFIG_PHY_ROCKCHIP_USB=y
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
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# CONFIG_PINCTRL_RK805 is not set
|
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CONFIG_PINCTRL_ROCKCHIP=y
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||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
|
@ -454,6 +512,8 @@ CONFIG_PROC_PAGE_MONITOR=y
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CONFIG_PROC_VMCORE=y
|
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
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CONFIG_PWM=y
|
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# CONFIG_PWM_ATMEL_TCB is not set
|
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# CONFIG_PWM_DWC is not set
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
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|
@ -476,11 +536,14 @@ CONFIG_REGMAP_I2C=y
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CONFIG_REGMAP_IRQ=y
|
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CONFIG_REGMAP_MMIO=y
|
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CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_DA9121 is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
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# CONFIG_REGULATOR_PF8X00 is not set
|
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CONFIG_REGULATOR_PWM=y
|
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CONFIG_REGULATOR_RK808=y
|
||||
# CONFIG_REGULATOR_RTQ6752 is not set
|
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CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
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CONFIG_RFS_ACCEL=y
|
||||
|
@ -492,7 +555,6 @@ CONFIG_ROCKCHIP_MBOX=y
|
|||
# CONFIG_ROCKCHIP_OTP is not set
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
|
@ -513,7 +575,13 @@ CONFIG_SCSI_SAS_ATTRS=y
|
|||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_AHT10 is not set
|
||||
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
# CONFIG_SENSORS_LTC2992 is not set
|
||||
# CONFIG_SENSORS_MAX127 is not set
|
||||
# CONFIG_SENSORS_SBTSI is not set
|
||||
# CONFIG_SENSORS_TPS23861 is not set
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
|
@ -548,7 +616,7 @@ CONFIG_SPI_DYNAMIC=y
|
|||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
# CONFIG_SPI_ROCKCHIP_SFC is not set
|
||||
CONFIG_SPI_ROCKCHIP_SFC=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
|
@ -560,6 +628,8 @@ CONFIG_SRCU=y
|
|||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
|
@ -606,6 +676,7 @@ CONFIG_TYPEC_TCPM=y
|
|||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_USB_CDNS_SUPPORT is not set
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
|
|
|
@ -1,19 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
|
||||
*/
|
||||
|
||||
/* TODO
|
||||
* Delete this file and migrate RockPi 4 to RockPi 4A after
|
||||
* removing Kernel 5.4.
|
||||
*/
|
||||
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-rock-pi-4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK Pi 4";
|
||||
compatible = "radxa,rockpi4", "rockchip,rk3399";
|
||||
};
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rk3328-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr3_odt_dis_freq = <100>;
|
||||
phy_ddr3_odt_dis_freq = <100>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
|
||||
|
||||
lpddr3_odt_dis_freq = <666>;
|
||||
phy_lpddr3_odt_dis_freq = <666>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
/* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
ddr3a1_ddr4a9_de-skew = <7>;
|
||||
ddr3a0_ddr4a10_de-skew = <7>;
|
||||
ddr3a3_ddr4a6_de-skew = <8>;
|
||||
ddr3a2_ddr4a4_de-skew = <8>;
|
||||
ddr3a5_ddr4a8_de-skew = <7>;
|
||||
ddr3a4_ddr4a5_de-skew = <9>;
|
||||
ddr3a7_ddr4a11_de-skew = <7>;
|
||||
ddr3a6_ddr4a7_de-skew = <9>;
|
||||
ddr3a9_ddr4a0_de-skew = <8>;
|
||||
ddr3a8_ddr4a13_de-skew = <7>;
|
||||
ddr3a11_ddr4a3_de-skew = <9>;
|
||||
ddr3a10_ddr4cs0_de-skew = <7>;
|
||||
ddr3a13_ddr4a2_de-skew = <8>;
|
||||
ddr3a12_ddr4ba1_de-skew = <7>;
|
||||
ddr3a15_ddr4odt0_de-skew = <7>;
|
||||
ddr3a14_ddr4a1_de-skew = <8>;
|
||||
ddr3ba1_ddr4a15_de-skew = <7>;
|
||||
ddr3ba0_ddr4bg0_de-skew = <7>;
|
||||
ddr3ras_ddr4cke_de-skew = <7>;
|
||||
ddr3ba2_ddr4ba0_de-skew = <8>;
|
||||
ddr3we_ddr4bg1_de-skew = <8>;
|
||||
ddr3cas_ddr4a12_de-skew = <7>;
|
||||
ddr3ckn_ddr4ckn_de-skew = <8>;
|
||||
ddr3ckp_ddr4ckp_de-skew = <8>;
|
||||
ddr3cke_ddr4a16_de-skew = <8>;
|
||||
ddr3odt0_ddr4a14_de-skew = <7>;
|
||||
ddr3cs0_ddr4act_de-skew = <8>;
|
||||
ddr3reset_ddr4reset_de-skew = <7>;
|
||||
ddr3cs1_ddr4cs1_de-skew = <7>;
|
||||
ddr3odt1_ddr4odt1_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew
|
||||
* RX one step is 25.1ps, range 0-15
|
||||
* TX one step is 47.8ps, range 0-15
|
||||
*/
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dm0_tx_de-skew = <8>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <8>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <8>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <8>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <8>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <8>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <8>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <8>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <8>;
|
||||
cs0_dqs0_rx_de-skew = <6>;
|
||||
cs0_dqs0p_tx_de-skew = <9>;
|
||||
cs0_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <8>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <8>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <8>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <8>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1_rx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <9>;
|
||||
cs0_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dm2_tx_de-skew = <8>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <8>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <8>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <8>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <8>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <8>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <8>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <8>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <8>;
|
||||
cs0_dqs2_rx_de-skew = <6>;
|
||||
cs0_dqs2p_tx_de-skew = <9>;
|
||||
cs0_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <8>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3_rx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <9>;
|
||||
cs0_dqs3n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dm0_tx_de-skew = <8>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <8>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <8>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <8>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <8>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <8>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <8>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <8>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <8>;
|
||||
cs1_dqs0_rx_de-skew = <6>;
|
||||
cs1_dqs0p_tx_de-skew = <9>;
|
||||
cs1_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <8>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <8>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <8>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <8>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1_rx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <9>;
|
||||
cs1_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dm2_tx_de-skew = <8>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <8>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <8>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <8>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <8>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <8>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <8>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <8>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <8>;
|
||||
cs1_dqs2_rx_de-skew = <6>;
|
||||
cs1_dqs2p_tx_de-skew = <9>;
|
||||
cs1_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <8>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3_rx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <9>;
|
||||
cs1_dqs3n_tx_de-skew = <9>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rk3328-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr3_odt_dis_freq = <100>;
|
||||
phy_ddr3_odt_dis_freq = <100>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
|
||||
|
||||
lpddr3_odt_dis_freq = <666>;
|
||||
phy_lpddr3_odt_dis_freq = <666>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
/* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
ddr3a1_ddr4a9_de-skew = <7>;
|
||||
ddr3a0_ddr4a10_de-skew = <7>;
|
||||
ddr3a3_ddr4a6_de-skew = <8>;
|
||||
ddr3a2_ddr4a4_de-skew = <8>;
|
||||
ddr3a5_ddr4a8_de-skew = <7>;
|
||||
ddr3a4_ddr4a5_de-skew = <9>;
|
||||
ddr3a7_ddr4a11_de-skew = <7>;
|
||||
ddr3a6_ddr4a7_de-skew = <9>;
|
||||
ddr3a9_ddr4a0_de-skew = <8>;
|
||||
ddr3a8_ddr4a13_de-skew = <7>;
|
||||
ddr3a11_ddr4a3_de-skew = <9>;
|
||||
ddr3a10_ddr4cs0_de-skew = <7>;
|
||||
ddr3a13_ddr4a2_de-skew = <8>;
|
||||
ddr3a12_ddr4ba1_de-skew = <7>;
|
||||
ddr3a15_ddr4odt0_de-skew = <7>;
|
||||
ddr3a14_ddr4a1_de-skew = <8>;
|
||||
ddr3ba1_ddr4a15_de-skew = <7>;
|
||||
ddr3ba0_ddr4bg0_de-skew = <7>;
|
||||
ddr3ras_ddr4cke_de-skew = <7>;
|
||||
ddr3ba2_ddr4ba0_de-skew = <8>;
|
||||
ddr3we_ddr4bg1_de-skew = <8>;
|
||||
ddr3cas_ddr4a12_de-skew = <7>;
|
||||
ddr3ckn_ddr4ckn_de-skew = <8>;
|
||||
ddr3ckp_ddr4ckp_de-skew = <8>;
|
||||
ddr3cke_ddr4a16_de-skew = <8>;
|
||||
ddr3odt0_ddr4a14_de-skew = <7>;
|
||||
ddr3cs0_ddr4act_de-skew = <8>;
|
||||
ddr3reset_ddr4reset_de-skew = <7>;
|
||||
ddr3cs1_ddr4cs1_de-skew = <7>;
|
||||
ddr3odt1_ddr4odt1_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew
|
||||
* RX one step is 25.1ps, range 0-15
|
||||
* TX one step is 47.8ps, range 0-15
|
||||
*/
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dm0_tx_de-skew = <8>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <8>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <8>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <8>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <8>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <8>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <8>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <8>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <8>;
|
||||
cs0_dqs0_rx_de-skew = <6>;
|
||||
cs0_dqs0p_tx_de-skew = <9>;
|
||||
cs0_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <8>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <8>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <8>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <8>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1_rx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <9>;
|
||||
cs0_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dm2_tx_de-skew = <8>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <8>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <8>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <8>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <8>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <8>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <8>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <8>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <8>;
|
||||
cs0_dqs2_rx_de-skew = <6>;
|
||||
cs0_dqs2p_tx_de-skew = <9>;
|
||||
cs0_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <8>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3_rx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <9>;
|
||||
cs0_dqs3n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dm0_tx_de-skew = <8>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <8>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <8>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <8>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <8>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <8>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <8>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <8>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <8>;
|
||||
cs1_dqs0_rx_de-skew = <6>;
|
||||
cs1_dqs0p_tx_de-skew = <9>;
|
||||
cs1_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <8>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <8>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <8>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <8>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1_rx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <9>;
|
||||
cs1_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dm2_tx_de-skew = <8>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <8>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <8>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <8>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <8>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <8>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <8>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <8>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <8>;
|
||||
cs1_dqs2_rx_de-skew = <6>;
|
||||
cs1_dqs2p_tx_de-skew = <9>;
|
||||
cs1_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <8>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3_rx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <9>;
|
||||
cs1_dqs3n_tx_de-skew = <9>;
|
||||
};
|
||||
};
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,664 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI GuangMiao G4C";
|
||||
compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
|
||||
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
aliases {
|
||||
led-boot = &status_led;
|
||||
led-failsafe = &status_led;
|
||||
led-running = &status_led;
|
||||
led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc_sys";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_0v9: vcc-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vcc_0v9";
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host0: vcc5v0-host0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_host0";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd_log";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
|
||||
|
||||
lan_led: led-lan {
|
||||
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
status_led: led-status {
|
||||
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:status";
|
||||
};
|
||||
|
||||
wan_led: led-wan {
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
|
||||
phy-handle = <&rtl8211e>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc3v3_s3>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpu_b_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpu_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
|
||||
#clock-cells = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_3v0>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_center";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo1: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo1";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo2: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo2";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_sdio";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc3v0_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vcc_1v5";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_codec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc_3v0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bt656-supply = <&vcc_1v8>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||
vpcie0v9-supply = <&vcc_0v9>;
|
||||
vpcie1v8-supply = <&vcca_1v8>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-leds {
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
gpu_sleep: gpu-sleep {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
bt_reg_on_h: bt-reg-on-h {
|
||||
/* external pullup to VCC1V8_PMUPLL */
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc0_det_l: sdmmc0-det-l {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm2_pin_pull_down>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
1127
root/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
1127
root/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-nanopi-r4s.dts"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R4SE";
|
||||
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,530 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>;
|
||||
|
||||
led_work: led-0 {
|
||||
label = "blue:work-led";
|
||||
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
mbi-ranges = <94 31>, <229 31>, <289 31>;
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x4078>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x4078>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
|
@ -0,0 +1,654 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S";
|
||||
compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sata_en>, <&led_sys_en>;
|
||||
|
||||
sata {
|
||||
label = "blue:sata";
|
||||
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
};
|
||||
|
||||
vcc5v0_ahci: vcc5v0-ahci {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata_pwr_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_ahci";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
sata_pwr_en: sata-pwr-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
target-supply = <&vcc5v0_ahci>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
|
@ -0,0 +1,710 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
* Copyright (c) 2022 Marty Jones <mj8263788@gmail.com>
|
||||
* Copyright (c) 2022 Tianling Shen <cnsztl@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5S";
|
||||
compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>,
|
||||
<&sys_led_pin>, <&wan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan1_led: led-0 {
|
||||
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan1";
|
||||
};
|
||||
|
||||
lan2_led: led-1 {
|
||||
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan2";
|
||||
};
|
||||
|
||||
sys_led: led-2 {
|
||||
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-3 {
|
||||
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 15ms, 50ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 15000 50000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@00 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
lan1_led_pin: lan1-led-pin {
|
||||
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan2_led_pin: lan2-led-pin {
|
||||
rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
gmac_int: gmac-int {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
|
@ -0,0 +1,725 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H68K Board";
|
||||
compatible = "hinlink,opc-h68k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
|
||||
|
||||
net {
|
||||
label = "blue:net";
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata {
|
||||
label = "amber:sata";
|
||||
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_work: work {
|
||||
label = "green:work";
|
||||
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: gpio-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
button {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_net_en: led_net_en {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R66S";
|
||||
compatible = "fastrhino,r66s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R68S";
|
||||
compatible = "fastrhino,r68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,797 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Firefly Station P2";
|
||||
compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>, <&led_user_en>;
|
||||
|
||||
led-work {
|
||||
label = "blue:work";
|
||||
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
||||
};
|
||||
|
||||
led-user {
|
||||
label = "yellow:user";
|
||||
gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <100>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe: pcie-pi6c-oe {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie_pi6c_oe_en";
|
||||
regulator-always-on;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pi6c_oe_en>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc_hub_reset: vcc-hub-reset {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_hub_reset";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_hub_reset_en>;
|
||||
};
|
||||
|
||||
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd0_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd1_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&gmac0_clkinout>;
|
||||
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus
|
||||
&gmac1m1_clkinout>;
|
||||
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc_hub_reset_en: vcc-hub-reset-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
fusb0_int {
|
||||
fusb0_int: fusb0-int {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe_en: pcie-pi6c-oe-en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&pcie_pi6c_oe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
|
@ -0,0 +1,766 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK3 Model A";
|
||||
compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub: vcc5v0-usb-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_hub_en>;
|
||||
regulator-name = "vcc5v0_usb_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c_03: vcc3v3-pi6c-03 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pi6c_03";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_cam: vcc-cam {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_cam_en>;
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_mipi_en>;
|
||||
regulator-name = "vcc_mipi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c_03>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
vcc_cam_en: vcc_cam_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
display {
|
||||
vcc_mipi_en: vcc_mipi_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
|
@ -0,0 +1,630 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK Pi E25";
|
||||
compatible = "radxa,rockpi-e25", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
compatible = "pwm-leds-multicolor";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
max-brightness = <255>;
|
||||
|
||||
led-red {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
pwms = <&pwm1 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
pwms = <&pwm2 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-blue {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
pwms = <&pwm12 0 1000000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
typec_5v: typec-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "typec_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc5v0_sys, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie30x1: vcc3v3-pcie30x1 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie30x1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c_05>;
|
||||
};
|
||||
|
||||
vcc3v3_pi6c_05: vcc3v3-pi6c-05 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_minipcie: vcc3v3-minipcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_enable_h>;
|
||||
regulator-name = "vcc3v3_minipcie";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&typec_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&typec_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20_reset_h>;
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie20_reset_h: pcie20-reset-h {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x1_enable_h: pcie30x1-enable-h {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x2_reset_h: pcie30x2-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
minipcie_enable_h: minipcie-enable-h {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm12 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm12m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
/* Also used in pcie30x1_clkreqnm0 */
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,265 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk356x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
sata0: sata@fc000000 {
|
||||
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfc000000 0 0x1000>;
|
||||
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
||||
<&cru CLK_SATA0_RXOOB>;
|
||||
clock-names = "sata", "pmalive", "rxoob";
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&combphy0 PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
ports-implemented = <0x1>;
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pipe_phy_grf0: syscon@fdc70000 {
|
||||
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfdc70000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
qos_pcie3x1: qos@fe190080 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_pcie3x2: qos@fe190100 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190100 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_sata0: qos@fe190200 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
|
||||
pcie30_phy_grf: syscon@fdcb8000 {
|
||||
compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pcie30phy: phy@fe8c0000 {
|
||||
compatible = "rockchip,rk3568-pcie3-phy";
|
||||
reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
||||
<&cru PCLK_PCIE30PHY>;
|
||||
clock-names = "refclk_m", "refclk_n", "pclk";
|
||||
resets = <&cru SRST_PCIE30PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x1: pcie@fe270000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
||||
<0 0 0 2 &pcie3x1_intc 1>,
|
||||
<0 0 0 3 &pcie3x1_intc 2>,
|
||||
<0 0 0 4 &pcie3x1_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
reg = <0x3 0xc0400000 0x0 0x00400000>,
|
||||
<0x0 0xfe270000 0x0 0x00010000>,
|
||||
<0x3 0x7f000000 0x0 0x01000000>;
|
||||
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE30X1_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
/* bifurcation; lane1 when using 1+1 */
|
||||
status = "disabled";
|
||||
|
||||
pcie3x1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3x2: pcie@fe280000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
<0 0 0 2 &pcie3x2_intc 1>,
|
||||
<0 0 0 3 &pcie3x2_intc 2>,
|
||||
<0 0 0 4 &pcie3x2_intc 3>;
|
||||
linux,pci-domain = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
reg = <0x3 0xc0800000 0x0 0x00400000>,
|
||||
<0x0 0xfe280000 0x0 0x00010000>,
|
||||
<0x3 0xbf000000 0x0 0x01000000>;
|
||||
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE30X2_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
/* bifurcation; lane0 when using 1+1 */
|
||||
status = "disabled";
|
||||
|
||||
pcie3x2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@fe2a0000 {
|
||||
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
"clk_mac_speed", "ptp_ref";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
snps,mixed-burst;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
snps,rd_osr_lmt = <8>;
|
||||
snps,wr_osr_lmt = <4>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
};
|
||||
|
||||
combphy0: phy@fe820000 {
|
||||
compatible = "rockchip,rk3568-naneng-combphy";
|
||||
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||
clocks = <&pmucru CLK_PCIEPHY0_REF>,
|
||||
<&cru PCLK_PIPEPHY0>,
|
||||
<&cru PCLK_PIPE>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_PIPEPHY0>;
|
||||
rockchip,pipe-grf = <&pipegrf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
||||
#phy-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
opp-1992000000 {
|
||||
opp-hz = /bits/ 64 <1992000000>;
|
||||
opp-microvolt = <1150000 1150000 1150000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pipegrf {
|
||||
compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||
};
|
||||
|
||||
&power {
|
||||
power-domain@RK3568_PD_PIPE {
|
||||
reg = <RK3568_PD_PIPE>;
|
||||
clocks = <&cru PCLK_PIPE>;
|
||||
pm_qos = <&qos_pcie2x1>,
|
||||
<&qos_pcie3x1>,
|
||||
<&qos_pcie3x2>,
|
||||
<&qos_sata0>,
|
||||
<&qos_sata1>,
|
||||
<&qos_sata2>,
|
||||
<&qos_usb3_0>,
|
||||
<&qos_usb3_1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
|
||||
&vop {
|
||||
compatible = "rockchip,rk3568-vop";
|
||||
};
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,344 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
|
||||
bias-disable;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
|
||||
bias-disable;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
|
||||
bias-disable;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
|
||||
bias-disable;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
|
||||
bias-disable;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
|
||||
bias-disable;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
|
||||
bias-disable;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
|
||||
bias-disable;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
|
||||
bias-disable;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
|
||||
bias-disable;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
|
||||
bias-disable;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
|
||||
bias-disable;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
|
||||
bias-pull-up;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
|
||||
bias-pull-up;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
|
||||
bias-pull-up;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
|
||||
bias-pull-up;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
|
||||
bias-pull-up;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
|
||||
bias-pull-up;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
|
||||
bias-pull-up;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
|
||||
bias-pull-up;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
|
||||
bias-pull-up;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
|
||||
bias-pull-up;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
|
||||
bias-pull-down;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
|
||||
bias-pull-down;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
|
||||
bias-pull-down;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
|
||||
bias-pull-down;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
|
||||
bias-pull-down;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
|
||||
bias-pull-down;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
|
||||
bias-pull-down;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
|
||||
bias-pull-down;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
|
||||
bias-pull-down;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
|
||||
bias-pull-down;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
|
||||
bias-pull-down;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
|
||||
bias-pull-down;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
|
||||
bias-pull-down;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
|
||||
bias-pull-down;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
|
||||
bias-pull-down;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_smt: pcfg-pull-up-smt {
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_smt: pcfg-pull-down-smt {
|
||||
bias-pull-down;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,310 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rockchip-rng.c Random Number Generator driver for the Rockchip
|
||||
*
|
||||
* Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/hw_random.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define _SBF(s, v) ((v) << (s))
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
|
||||
#define ROCKCHIP_POLL_PERIOD_US 100
|
||||
#define ROCKCHIP_POLL_TIMEOUT_US 10000
|
||||
#define RK_MAX_RNG_BYTE (32)
|
||||
|
||||
/* start of CRYPTO V1 register define */
|
||||
#define CRYPTO_V1_CTRL 0x0008
|
||||
#define CRYPTO_V1_RNG_START BIT(8)
|
||||
#define CRYPTO_V1_RNG_FLUSH BIT(9)
|
||||
|
||||
#define CRYPTO_V1_TRNG_CTRL 0x0200
|
||||
#define CRYPTO_V1_OSC_ENABLE BIT(16)
|
||||
#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
|
||||
|
||||
#define CRYPTO_V1_TRNG_DOUT_0 0x0204
|
||||
/* end of CRYPTO V1 register define */
|
||||
|
||||
/* start of CRYPTO V2 register define */
|
||||
#define CRYPTO_V2_RNG_CTL 0x0400
|
||||
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
|
||||
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
|
||||
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
|
||||
#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
|
||||
#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
|
||||
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
|
||||
#define CRYPTO_V2_RNG_ENABLE BIT(1)
|
||||
#define CRYPTO_V2_RNG_START BIT(0)
|
||||
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
|
||||
#define CRYPTO_V2_RNG_DOUT_0 0x0410
|
||||
/* end of CRYPTO V2 register define */
|
||||
|
||||
struct rk_rng_soc_data {
|
||||
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
|
||||
};
|
||||
|
||||
struct rk_rng {
|
||||
struct device *dev;
|
||||
struct hwrng rng;
|
||||
void __iomem *mem;
|
||||
struct rk_rng_soc_data *soc_data;
|
||||
int clk_num;
|
||||
struct clk_bulk_data *clk_bulks;
|
||||
};
|
||||
|
||||
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
|
||||
{
|
||||
__raw_writel(val, rng->mem + offset);
|
||||
}
|
||||
|
||||
static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
|
||||
{
|
||||
return __raw_readl(rng->mem + offset);
|
||||
}
|
||||
|
||||
static int rk_rng_init(struct hwrng *rng)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
|
||||
|
||||
ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
if (ret < 0) {
|
||||
dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk_rng_cleanup(struct hwrng *rng)
|
||||
{
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
|
||||
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
}
|
||||
|
||||
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
|
||||
size_t size)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < size; i += 4)
|
||||
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
|
||||
}
|
||||
|
||||
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
|
||||
|
||||
reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
|
||||
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V1_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
|
||||
CRYPTO_V1_CTRL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
|
||||
|
||||
reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_START;
|
||||
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
|
||||
CRYPTO_V2_RNG_CTL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V2_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
|
||||
.rk_rng_read = rk_rng_v1_read,
|
||||
};
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
|
||||
.rk_rng_read = rk_rng_v2_read,
|
||||
};
|
||||
|
||||
static const struct of_device_id rk_rng_dt_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,cryptov1-rng",
|
||||
.data = (void *)&rk_rng_v1_soc_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,cryptov2-rng",
|
||||
.data = (void *)&rk_rng_v2_soc_data,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
|
||||
|
||||
static int rk_rng_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
|
||||
dev_dbg(&pdev->dev, "probing...\n");
|
||||
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
|
||||
if (!rk_rng)
|
||||
return -ENOMEM;
|
||||
|
||||
match = of_match_node(rk_rng_dt_match, np);
|
||||
rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
|
||||
|
||||
rk_rng->dev = &pdev->dev;
|
||||
rk_rng->rng.name = "rockchip";
|
||||
#ifndef CONFIG_PM
|
||||
rk_rng->rng.init = rk_rng_init;
|
||||
rk_rng->rng.cleanup = rk_rng_cleanup,
|
||||
#endif
|
||||
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
|
||||
rk_rng->rng.quality = 999;
|
||||
|
||||
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
|
||||
if (IS_ERR(rk_rng->mem))
|
||||
return PTR_ERR(rk_rng->mem);
|
||||
|
||||
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
|
||||
if (rk_rng->clk_num < 0) {
|
||||
dev_err(&pdev->dev, "failed to get clks property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, rk_rng);
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
||||
ROCKCHIP_AUTOSUSPEND_DELAY);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
|
||||
if (ret) {
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int rk_rng_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
rk_rng_cleanup(&rk_rng->rng);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_rng_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
return rk_rng_init(&rk_rng->rng);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rk_rng_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
|
||||
rk_rng_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_driver rk_rng_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-rng",
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &rk_rng_pm_ops,
|
||||
#endif
|
||||
.of_match_table = rk_rng_dt_match,
|
||||
},
|
||||
.probe = rk_rng_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rk_rng_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
|
||||
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
852
root/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
852
root/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
|
@ -0,0 +1,852 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iversion.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <soc/rockchip/rockchip_sip.h>
|
||||
|
||||
#define DTS_PAR_OFFSET (4096)
|
||||
|
||||
struct share_params {
|
||||
u32 hz;
|
||||
u32 lcdc_type;
|
||||
u32 vop;
|
||||
u32 vop_dclk_mode;
|
||||
u32 sr_idle_en;
|
||||
u32 addr_mcu_el3;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag1;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag0;
|
||||
u32 complt_hwirq;
|
||||
/* if need, add parameter after */
|
||||
};
|
||||
|
||||
static struct share_params *ddr_psci_param;
|
||||
|
||||
/* hope this define can adapt all future platform */
|
||||
static const char * const rk3328_dts_timing[] = {
|
||||
"ddr3_speed_bin",
|
||||
"ddr4_speed_bin",
|
||||
"pd_idle",
|
||||
"sr_idle",
|
||||
"sr_mc_gate_idle",
|
||||
"srpd_lite_idle",
|
||||
"standby_idle",
|
||||
|
||||
"auto_pd_dis_freq",
|
||||
"auto_sr_dis_freq",
|
||||
"ddr3_dll_dis_freq",
|
||||
"ddr4_dll_dis_freq",
|
||||
"phy_dll_dis_freq",
|
||||
|
||||
"ddr3_odt_dis_freq",
|
||||
"phy_ddr3_odt_dis_freq",
|
||||
"ddr3_drv",
|
||||
"ddr3_odt",
|
||||
"phy_ddr3_ca_drv",
|
||||
"phy_ddr3_ck_drv",
|
||||
"phy_ddr3_dq_drv",
|
||||
"phy_ddr3_odt",
|
||||
|
||||
"lpddr3_odt_dis_freq",
|
||||
"phy_lpddr3_odt_dis_freq",
|
||||
"lpddr3_drv",
|
||||
"lpddr3_odt",
|
||||
"phy_lpddr3_ca_drv",
|
||||
"phy_lpddr3_ck_drv",
|
||||
"phy_lpddr3_dq_drv",
|
||||
"phy_lpddr3_odt",
|
||||
|
||||
"lpddr4_odt_dis_freq",
|
||||
"phy_lpddr4_odt_dis_freq",
|
||||
"lpddr4_drv",
|
||||
"lpddr4_dq_odt",
|
||||
"lpddr4_ca_odt",
|
||||
"phy_lpddr4_ca_drv",
|
||||
"phy_lpddr4_ck_cs_drv",
|
||||
"phy_lpddr4_dq_drv",
|
||||
"phy_lpddr4_odt",
|
||||
|
||||
"ddr4_odt_dis_freq",
|
||||
"phy_ddr4_odt_dis_freq",
|
||||
"ddr4_drv",
|
||||
"ddr4_odt",
|
||||
"phy_ddr4_ca_drv",
|
||||
"phy_ddr4_ck_drv",
|
||||
"phy_ddr4_dq_drv",
|
||||
"phy_ddr4_odt",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_ca_timing[] = {
|
||||
"ddr3a1_ddr4a9_de-skew",
|
||||
"ddr3a0_ddr4a10_de-skew",
|
||||
"ddr3a3_ddr4a6_de-skew",
|
||||
"ddr3a2_ddr4a4_de-skew",
|
||||
"ddr3a5_ddr4a8_de-skew",
|
||||
"ddr3a4_ddr4a5_de-skew",
|
||||
"ddr3a7_ddr4a11_de-skew",
|
||||
"ddr3a6_ddr4a7_de-skew",
|
||||
"ddr3a9_ddr4a0_de-skew",
|
||||
"ddr3a8_ddr4a13_de-skew",
|
||||
"ddr3a11_ddr4a3_de-skew",
|
||||
"ddr3a10_ddr4cs0_de-skew",
|
||||
"ddr3a13_ddr4a2_de-skew",
|
||||
"ddr3a12_ddr4ba1_de-skew",
|
||||
"ddr3a15_ddr4odt0_de-skew",
|
||||
"ddr3a14_ddr4a1_de-skew",
|
||||
"ddr3ba1_ddr4a15_de-skew",
|
||||
"ddr3ba0_ddr4bg0_de-skew",
|
||||
"ddr3ras_ddr4cke_de-skew",
|
||||
"ddr3ba2_ddr4ba0_de-skew",
|
||||
"ddr3we_ddr4bg1_de-skew",
|
||||
"ddr3cas_ddr4a12_de-skew",
|
||||
"ddr3ckn_ddr4ckn_de-skew",
|
||||
"ddr3ckp_ddr4ckp_de-skew",
|
||||
"ddr3cke_ddr4a16_de-skew",
|
||||
"ddr3odt0_ddr4a14_de-skew",
|
||||
"ddr3cs0_ddr4act_de-skew",
|
||||
"ddr3reset_ddr4reset_de-skew",
|
||||
"ddr3cs1_ddr4cs1_de-skew",
|
||||
"ddr3odt1_ddr4odt1_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs0_timing[] = {
|
||||
"cs0_dm0_rx_de-skew",
|
||||
"cs0_dm0_tx_de-skew",
|
||||
"cs0_dq0_rx_de-skew",
|
||||
"cs0_dq0_tx_de-skew",
|
||||
"cs0_dq1_rx_de-skew",
|
||||
"cs0_dq1_tx_de-skew",
|
||||
"cs0_dq2_rx_de-skew",
|
||||
"cs0_dq2_tx_de-skew",
|
||||
"cs0_dq3_rx_de-skew",
|
||||
"cs0_dq3_tx_de-skew",
|
||||
"cs0_dq4_rx_de-skew",
|
||||
"cs0_dq4_tx_de-skew",
|
||||
"cs0_dq5_rx_de-skew",
|
||||
"cs0_dq5_tx_de-skew",
|
||||
"cs0_dq6_rx_de-skew",
|
||||
"cs0_dq6_tx_de-skew",
|
||||
"cs0_dq7_rx_de-skew",
|
||||
"cs0_dq7_tx_de-skew",
|
||||
"cs0_dqs0_rx_de-skew",
|
||||
"cs0_dqs0p_tx_de-skew",
|
||||
"cs0_dqs0n_tx_de-skew",
|
||||
|
||||
"cs0_dm1_rx_de-skew",
|
||||
"cs0_dm1_tx_de-skew",
|
||||
"cs0_dq8_rx_de-skew",
|
||||
"cs0_dq8_tx_de-skew",
|
||||
"cs0_dq9_rx_de-skew",
|
||||
"cs0_dq9_tx_de-skew",
|
||||
"cs0_dq10_rx_de-skew",
|
||||
"cs0_dq10_tx_de-skew",
|
||||
"cs0_dq11_rx_de-skew",
|
||||
"cs0_dq11_tx_de-skew",
|
||||
"cs0_dq12_rx_de-skew",
|
||||
"cs0_dq12_tx_de-skew",
|
||||
"cs0_dq13_rx_de-skew",
|
||||
"cs0_dq13_tx_de-skew",
|
||||
"cs0_dq14_rx_de-skew",
|
||||
"cs0_dq14_tx_de-skew",
|
||||
"cs0_dq15_rx_de-skew",
|
||||
"cs0_dq15_tx_de-skew",
|
||||
"cs0_dqs1_rx_de-skew",
|
||||
"cs0_dqs1p_tx_de-skew",
|
||||
"cs0_dqs1n_tx_de-skew",
|
||||
|
||||
"cs0_dm2_rx_de-skew",
|
||||
"cs0_dm2_tx_de-skew",
|
||||
"cs0_dq16_rx_de-skew",
|
||||
"cs0_dq16_tx_de-skew",
|
||||
"cs0_dq17_rx_de-skew",
|
||||
"cs0_dq17_tx_de-skew",
|
||||
"cs0_dq18_rx_de-skew",
|
||||
"cs0_dq18_tx_de-skew",
|
||||
"cs0_dq19_rx_de-skew",
|
||||
"cs0_dq19_tx_de-skew",
|
||||
"cs0_dq20_rx_de-skew",
|
||||
"cs0_dq20_tx_de-skew",
|
||||
"cs0_dq21_rx_de-skew",
|
||||
"cs0_dq21_tx_de-skew",
|
||||
"cs0_dq22_rx_de-skew",
|
||||
"cs0_dq22_tx_de-skew",
|
||||
"cs0_dq23_rx_de-skew",
|
||||
"cs0_dq23_tx_de-skew",
|
||||
"cs0_dqs2_rx_de-skew",
|
||||
"cs0_dqs2p_tx_de-skew",
|
||||
"cs0_dqs2n_tx_de-skew",
|
||||
|
||||
"cs0_dm3_rx_de-skew",
|
||||
"cs0_dm3_tx_de-skew",
|
||||
"cs0_dq24_rx_de-skew",
|
||||
"cs0_dq24_tx_de-skew",
|
||||
"cs0_dq25_rx_de-skew",
|
||||
"cs0_dq25_tx_de-skew",
|
||||
"cs0_dq26_rx_de-skew",
|
||||
"cs0_dq26_tx_de-skew",
|
||||
"cs0_dq27_rx_de-skew",
|
||||
"cs0_dq27_tx_de-skew",
|
||||
"cs0_dq28_rx_de-skew",
|
||||
"cs0_dq28_tx_de-skew",
|
||||
"cs0_dq29_rx_de-skew",
|
||||
"cs0_dq29_tx_de-skew",
|
||||
"cs0_dq30_rx_de-skew",
|
||||
"cs0_dq30_tx_de-skew",
|
||||
"cs0_dq31_rx_de-skew",
|
||||
"cs0_dq31_tx_de-skew",
|
||||
"cs0_dqs3_rx_de-skew",
|
||||
"cs0_dqs3p_tx_de-skew",
|
||||
"cs0_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs1_timing[] = {
|
||||
"cs1_dm0_rx_de-skew",
|
||||
"cs1_dm0_tx_de-skew",
|
||||
"cs1_dq0_rx_de-skew",
|
||||
"cs1_dq0_tx_de-skew",
|
||||
"cs1_dq1_rx_de-skew",
|
||||
"cs1_dq1_tx_de-skew",
|
||||
"cs1_dq2_rx_de-skew",
|
||||
"cs1_dq2_tx_de-skew",
|
||||
"cs1_dq3_rx_de-skew",
|
||||
"cs1_dq3_tx_de-skew",
|
||||
"cs1_dq4_rx_de-skew",
|
||||
"cs1_dq4_tx_de-skew",
|
||||
"cs1_dq5_rx_de-skew",
|
||||
"cs1_dq5_tx_de-skew",
|
||||
"cs1_dq6_rx_de-skew",
|
||||
"cs1_dq6_tx_de-skew",
|
||||
"cs1_dq7_rx_de-skew",
|
||||
"cs1_dq7_tx_de-skew",
|
||||
"cs1_dqs0_rx_de-skew",
|
||||
"cs1_dqs0p_tx_de-skew",
|
||||
"cs1_dqs0n_tx_de-skew",
|
||||
|
||||
"cs1_dm1_rx_de-skew",
|
||||
"cs1_dm1_tx_de-skew",
|
||||
"cs1_dq8_rx_de-skew",
|
||||
"cs1_dq8_tx_de-skew",
|
||||
"cs1_dq9_rx_de-skew",
|
||||
"cs1_dq9_tx_de-skew",
|
||||
"cs1_dq10_rx_de-skew",
|
||||
"cs1_dq10_tx_de-skew",
|
||||
"cs1_dq11_rx_de-skew",
|
||||
"cs1_dq11_tx_de-skew",
|
||||
"cs1_dq12_rx_de-skew",
|
||||
"cs1_dq12_tx_de-skew",
|
||||
"cs1_dq13_rx_de-skew",
|
||||
"cs1_dq13_tx_de-skew",
|
||||
"cs1_dq14_rx_de-skew",
|
||||
"cs1_dq14_tx_de-skew",
|
||||
"cs1_dq15_rx_de-skew",
|
||||
"cs1_dq15_tx_de-skew",
|
||||
"cs1_dqs1_rx_de-skew",
|
||||
"cs1_dqs1p_tx_de-skew",
|
||||
"cs1_dqs1n_tx_de-skew",
|
||||
|
||||
"cs1_dm2_rx_de-skew",
|
||||
"cs1_dm2_tx_de-skew",
|
||||
"cs1_dq16_rx_de-skew",
|
||||
"cs1_dq16_tx_de-skew",
|
||||
"cs1_dq17_rx_de-skew",
|
||||
"cs1_dq17_tx_de-skew",
|
||||
"cs1_dq18_rx_de-skew",
|
||||
"cs1_dq18_tx_de-skew",
|
||||
"cs1_dq19_rx_de-skew",
|
||||
"cs1_dq19_tx_de-skew",
|
||||
"cs1_dq20_rx_de-skew",
|
||||
"cs1_dq20_tx_de-skew",
|
||||
"cs1_dq21_rx_de-skew",
|
||||
"cs1_dq21_tx_de-skew",
|
||||
"cs1_dq22_rx_de-skew",
|
||||
"cs1_dq22_tx_de-skew",
|
||||
"cs1_dq23_rx_de-skew",
|
||||
"cs1_dq23_tx_de-skew",
|
||||
"cs1_dqs2_rx_de-skew",
|
||||
"cs1_dqs2p_tx_de-skew",
|
||||
"cs1_dqs2n_tx_de-skew",
|
||||
|
||||
"cs1_dm3_rx_de-skew",
|
||||
"cs1_dm3_tx_de-skew",
|
||||
"cs1_dq24_rx_de-skew",
|
||||
"cs1_dq24_tx_de-skew",
|
||||
"cs1_dq25_rx_de-skew",
|
||||
"cs1_dq25_tx_de-skew",
|
||||
"cs1_dq26_rx_de-skew",
|
||||
"cs1_dq26_tx_de-skew",
|
||||
"cs1_dq27_rx_de-skew",
|
||||
"cs1_dq27_tx_de-skew",
|
||||
"cs1_dq28_rx_de-skew",
|
||||
"cs1_dq28_tx_de-skew",
|
||||
"cs1_dq29_rx_de-skew",
|
||||
"cs1_dq29_tx_de-skew",
|
||||
"cs1_dq30_rx_de-skew",
|
||||
"cs1_dq30_tx_de-skew",
|
||||
"cs1_dq31_rx_de-skew",
|
||||
"cs1_dq31_tx_de-skew",
|
||||
"cs1_dqs3_rx_de-skew",
|
||||
"cs1_dqs3p_tx_de-skew",
|
||||
"cs1_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
struct rk3328_ddr_dts_config_timing {
|
||||
unsigned int ddr3_speed_bin;
|
||||
unsigned int ddr4_speed_bin;
|
||||
unsigned int pd_idle;
|
||||
unsigned int sr_idle;
|
||||
unsigned int sr_mc_gate_idle;
|
||||
unsigned int srpd_lite_idle;
|
||||
unsigned int standby_idle;
|
||||
|
||||
unsigned int auto_pd_dis_freq;
|
||||
unsigned int auto_sr_dis_freq;
|
||||
/* for ddr3 only */
|
||||
unsigned int ddr3_dll_dis_freq;
|
||||
/* for ddr4 only */
|
||||
unsigned int ddr4_dll_dis_freq;
|
||||
unsigned int phy_dll_dis_freq;
|
||||
|
||||
unsigned int ddr3_odt_dis_freq;
|
||||
unsigned int phy_ddr3_odt_dis_freq;
|
||||
unsigned int ddr3_drv;
|
||||
unsigned int ddr3_odt;
|
||||
unsigned int phy_ddr3_ca_drv;
|
||||
unsigned int phy_ddr3_ck_drv;
|
||||
unsigned int phy_ddr3_dq_drv;
|
||||
unsigned int phy_ddr3_odt;
|
||||
|
||||
unsigned int lpddr3_odt_dis_freq;
|
||||
unsigned int phy_lpddr3_odt_dis_freq;
|
||||
unsigned int lpddr3_drv;
|
||||
unsigned int lpddr3_odt;
|
||||
unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_ck_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int phy_lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
|
||||
unsigned int ddr4_odt_dis_freq;
|
||||
unsigned int phy_ddr4_odt_dis_freq;
|
||||
unsigned int ddr4_drv;
|
||||
unsigned int ddr4_odt;
|
||||
unsigned int phy_ddr4_ca_drv;
|
||||
unsigned int phy_ddr4_ck_drv;
|
||||
unsigned int phy_ddr4_dq_drv;
|
||||
unsigned int phy_ddr4_odt;
|
||||
|
||||
unsigned int ca_skew[15];
|
||||
unsigned int cs0_skew[44];
|
||||
unsigned int cs1_skew[44];
|
||||
|
||||
unsigned int available;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_de_skew_setting {
|
||||
unsigned int ca_de_skew[30];
|
||||
unsigned int cs0_de_skew[84];
|
||||
unsigned int cs1_de_skew[84];
|
||||
};
|
||||
|
||||
struct rk3328_dmcfreq {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
struct clk *dmc_clk;
|
||||
struct devfreq_event_dev *edev;
|
||||
struct mutex lock;
|
||||
struct regulator *vdd_center;
|
||||
unsigned long rate, target_rate;
|
||||
unsigned long volt, target_volt;
|
||||
|
||||
int (*set_auto_self_refresh)(u32 en);
|
||||
};
|
||||
|
||||
static void
|
||||
rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
|
||||
struct rk3328_ddr_dts_config_timing *tim)
|
||||
{
|
||||
u32 n;
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
|
||||
memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
|
||||
memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
|
||||
memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
|
||||
|
||||
/* CA de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
|
||||
offset = n / 2;
|
||||
shift = n % 2;
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->ca_skew[offset] &= ~(0xf << shift);
|
||||
tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS0 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs0_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS1 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs1_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static void of_get_rk3328_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
struct device_node *np_tim;
|
||||
u32 *p;
|
||||
struct rk3328_ddr_dts_config_timing *dts_timing;
|
||||
struct rk3328_ddr_de_skew_setting *de_skew;
|
||||
int ret = 0;
|
||||
u32 i;
|
||||
|
||||
dts_timing =
|
||||
(struct rk3328_ddr_dts_config_timing *)(timing +
|
||||
DTS_PAR_OFFSET / 4);
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (!np_tim) {
|
||||
ret = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
|
||||
if (!de_skew) {
|
||||
ret = -ENOMEM;
|
||||
goto end;
|
||||
}
|
||||
|
||||
p = (u32 *)dts_timing;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->ca_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs0_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs1_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
|
||||
p + i);
|
||||
}
|
||||
if (!ret)
|
||||
rk3328_de_skew_setting_2_register(de_skew, dts_timing);
|
||||
|
||||
kfree(de_skew);
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
|
||||
ddr_psci_param->sr_idle_en = en;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
return res.a0;
|
||||
}
|
||||
|
||||
static int rk3328_dmc_init(struct platform_device *pdev,
|
||||
struct rk3328_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size, page_num;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 || (res.a1 < 0x101)) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk3328_ddr_dts_config_timing);
|
||||
page_num = DIV_ROUND_UP(size, 4096) + 1;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
page_num, SHARE_PAGE_TYPE_DDR, 0,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ddr_psci_param = ioremap(res.a1, page_num << 12);
|
||||
of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long target_volt, target_rate;
|
||||
int err;
|
||||
|
||||
opp = devfreq_recommended_opp(dev, freq, flags);
|
||||
if (IS_ERR(opp))
|
||||
return PTR_ERR(opp);
|
||||
|
||||
target_rate = dev_pm_opp_get_freq(opp);
|
||||
target_volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (dmcfreq->rate == target_rate)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dmcfreq->lock);
|
||||
|
||||
/*
|
||||
* If frequency scaling from low to high, adjust voltage first.
|
||||
* If frequency scaling from high to low, adjust frequency first.
|
||||
*/
|
||||
if (old_clk_rate < target_rate) {
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n",
|
||||
target_volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
|
||||
err);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check the dpll rate,
|
||||
* There only two result we will get,
|
||||
* 1. Ddr frequency scaling fail, we still get the old rate.
|
||||
* 2. Ddr frequency scaling sucessful, we get the rate we set.
|
||||
*/
|
||||
dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
|
||||
|
||||
/* If get the incorrect rate, set voltage to old value. */
|
||||
if (dmcfreq->rate != target_rate) {
|
||||
dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
|
||||
target_rate, dmcfreq->rate);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
} else if (old_clk_rate > target_rate)
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err)
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
|
||||
|
||||
dmcfreq->rate = target_rate;
|
||||
dmcfreq->volt = target_volt;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dmcfreq->lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_dev_status(struct device *dev,
|
||||
struct devfreq_dev_status *stat)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct devfreq_event_data edata;
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_get_event(dmcfreq->edev, &edata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
stat->current_frequency = dmcfreq->rate;
|
||||
stat->busy_time = edata.load_count;
|
||||
stat->total_time = edata.total_count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
|
||||
*freq = dmcfreq->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {
|
||||
.polling_ms = 200,
|
||||
.target = rk3328_dmcfreq_target,
|
||||
.get_dev_status = rk3328_dmcfreq_get_dev_status,
|
||||
.get_cur_freq = rk3328_dmcfreq_get_cur_freq,
|
||||
};
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_disable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to disable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_suspend_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to suspend the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_enable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_resume_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to resume the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,
|
||||
rk3328_dmcfreq_resume);
|
||||
|
||||
static int rk3328_dmcfreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rk3328_dmcfreq *data;
|
||||
struct dev_pm_opp *opp;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&data->lock);
|
||||
|
||||
data->vdd_center = devm_regulator_get(dev, "center");
|
||||
if (IS_ERR(data->vdd_center)) {
|
||||
if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the regulator \"center\"\n");
|
||||
return PTR_ERR(data->vdd_center);
|
||||
}
|
||||
|
||||
data->dmc_clk = devm_clk_get(dev, "dmc_clk");
|
||||
if (IS_ERR(data->dmc_clk)) {
|
||||
if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->dmc_clk);
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
|
||||
#else
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
|
||||
#endif
|
||||
if (IS_ERR(data->edev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = devfreq_event_enable_edev(data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rk3328_dmc_init(pdev, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* We add a devfreq driver to our parent since it has a device tree node
|
||||
* with operating points.
|
||||
*/
|
||||
if (dev_pm_opp_of_add_table(dev)) {
|
||||
dev_err(dev, "Invalid operating-points in device tree.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "upthreshold",
|
||||
&data->ondemand_data.upthreshold);
|
||||
of_property_read_u32(np, "downdifferential",
|
||||
&data->ondemand_data.downdifferential);
|
||||
|
||||
data->rate = clk_get_rate(data->dmc_clk);
|
||||
|
||||
opp = devfreq_recommended_opp(dev, &data->rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
ret = PTR_ERR(opp);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
data->rate = dev_pm_opp_get_freq(opp);
|
||||
data->volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
rk3328_devfreq_dmc_profile.initial_freq = data->rate;
|
||||
|
||||
data->devfreq = devm_devfreq_add_device(dev,
|
||||
&rk3328_devfreq_dmc_profile,
|
||||
DEVFREQ_GOV_SIMPLE_ONDEMAND,
|
||||
&data->ondemand_data);
|
||||
if (IS_ERR(data->devfreq)) {
|
||||
ret = PTR_ERR(data->devfreq);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
||||
|
||||
data->dev = dev;
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_opp:
|
||||
dev_pm_opp_of_remove_table(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
/*
|
||||
* Before remove the opp table we need to unregister the opp notifier.
|
||||
*/
|
||||
devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
|
||||
dev_pm_opp_of_remove_table(dmcfreq->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk3328dmc_devfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3328-dmc" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);
|
||||
|
||||
static struct platform_driver rk3328_dmcfreq_driver = {
|
||||
.probe = rk3328_dmcfreq_probe,
|
||||
.remove = rk3328_dmcfreq_remove,
|
||||
.driver = {
|
||||
.name = "rk3328-dmc-freq",
|
||||
.pm = &rk3328_dmcfreq_pm,
|
||||
.of_match_table = rk3328dmc_devfreq_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rk3328_dmcfreq_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework");
|
|
@ -0,0 +1,926 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
|
||||
/* pmucru-clocks indices */
|
||||
|
||||
/* pmucru plls */
|
||||
#define PLL_PPLL 1
|
||||
#define PLL_HPLL 2
|
||||
|
||||
/* pmucru clocks */
|
||||
#define XIN_OSC0_DIV 4
|
||||
#define CLK_RTC_32K 5
|
||||
#define CLK_PMU 6
|
||||
#define CLK_I2C0 7
|
||||
#define CLK_RTC32K_FRAC 8
|
||||
#define CLK_UART0_DIV 9
|
||||
#define CLK_UART0_FRAC 10
|
||||
#define SCLK_UART0 11
|
||||
#define DBCLK_GPIO0 12
|
||||
#define CLK_PWM0 13
|
||||
#define CLK_CAPTURE_PWM0_NDFT 14
|
||||
#define CLK_PMUPVTM 15
|
||||
#define CLK_CORE_PMUPVTM 16
|
||||
#define CLK_REF24M 17
|
||||
#define XIN_OSC0_USBPHY0_G 18
|
||||
#define CLK_USBPHY0_REF 19
|
||||
#define XIN_OSC0_USBPHY1_G 20
|
||||
#define CLK_USBPHY1_REF 21
|
||||
#define XIN_OSC0_MIPIDSIPHY0_G 22
|
||||
#define CLK_MIPIDSIPHY0_REF 23
|
||||
#define XIN_OSC0_MIPIDSIPHY1_G 24
|
||||
#define CLK_MIPIDSIPHY1_REF 25
|
||||
#define CLK_WIFI_DIV 26
|
||||
#define CLK_WIFI_OSC0 27
|
||||
#define CLK_WIFI 28
|
||||
#define CLK_PCIEPHY0_DIV 29
|
||||
#define CLK_PCIEPHY0_OSC0 30
|
||||
#define CLK_PCIEPHY0_REF 31
|
||||
#define CLK_PCIEPHY1_DIV 32
|
||||
#define CLK_PCIEPHY1_OSC0 33
|
||||
#define CLK_PCIEPHY1_REF 34
|
||||
#define CLK_PCIEPHY2_DIV 35
|
||||
#define CLK_PCIEPHY2_OSC0 36
|
||||
#define CLK_PCIEPHY2_REF 37
|
||||
#define CLK_PCIE30PHY_REF_M 38
|
||||
#define CLK_PCIE30PHY_REF_N 39
|
||||
#define CLK_HDMI_REF 40
|
||||
#define XIN_OSC0_EDPPHY_G 41
|
||||
#define PCLK_PDPMU 42
|
||||
#define PCLK_PMU 43
|
||||
#define PCLK_UART0 44
|
||||
#define PCLK_I2C0 45
|
||||
#define PCLK_GPIO0 46
|
||||
#define PCLK_PMUPVTM 47
|
||||
#define PCLK_PWM0 48
|
||||
#define CLK_PDPMU 49
|
||||
#define SCLK_32K_IOE 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_VPLL 5
|
||||
#define PLL_NPLL 6
|
||||
|
||||
/* cru clocks */
|
||||
#define CPLL_333M 9
|
||||
#define ARMCLK 10
|
||||
#define USB480M 11
|
||||
#define ACLK_CORE_NIU2BUS 18
|
||||
#define CLK_CORE_PVTM 19
|
||||
#define CLK_CORE_PVTM_CORE 20
|
||||
#define CLK_CORE_PVTPLL 21
|
||||
#define CLK_GPU_SRC 22
|
||||
#define CLK_GPU_PRE_NDFT 23
|
||||
#define CLK_GPU_PRE_MUX 24
|
||||
#define ACLK_GPU_PRE 25
|
||||
#define PCLK_GPU_PRE 26
|
||||
#define CLK_GPU 27
|
||||
#define CLK_GPU_NP5 28
|
||||
#define PCLK_GPU_PVTM 29
|
||||
#define CLK_GPU_PVTM 30
|
||||
#define CLK_GPU_PVTM_CORE 31
|
||||
#define CLK_GPU_PVTPLL 32
|
||||
#define CLK_NPU_SRC 33
|
||||
#define CLK_NPU_PRE_NDFT 34
|
||||
#define CLK_NPU 35
|
||||
#define CLK_NPU_NP5 36
|
||||
#define HCLK_NPU_PRE 37
|
||||
#define PCLK_NPU_PRE 38
|
||||
#define ACLK_NPU_PRE 39
|
||||
#define ACLK_NPU 40
|
||||
#define HCLK_NPU 41
|
||||
#define PCLK_NPU_PVTM 42
|
||||
#define CLK_NPU_PVTM 43
|
||||
#define CLK_NPU_PVTM_CORE 44
|
||||
#define CLK_NPU_PVTPLL 45
|
||||
#define CLK_DDRPHY1X_SRC 46
|
||||
#define CLK_DDRPHY1X_HWFFC_SRC 47
|
||||
#define CLK_DDR1X 48
|
||||
#define CLK_MSCH 49
|
||||
#define CLK24_DDRMON 50
|
||||
#define ACLK_GIC_AUDIO 51
|
||||
#define HCLK_GIC_AUDIO 52
|
||||
#define HCLK_SDMMC_BUFFER 53
|
||||
#define DCLK_SDMMC_BUFFER 54
|
||||
#define ACLK_GIC600 55
|
||||
#define ACLK_SPINLOCK 56
|
||||
#define HCLK_I2S0_8CH 57
|
||||
#define HCLK_I2S1_8CH 58
|
||||
#define HCLK_I2S2_2CH 59
|
||||
#define HCLK_I2S3_2CH 60
|
||||
#define CLK_I2S0_8CH_TX_SRC 61
|
||||
#define CLK_I2S0_8CH_TX_FRAC 62
|
||||
#define MCLK_I2S0_8CH_TX 63
|
||||
#define I2S0_MCLKOUT_TX 64
|
||||
#define CLK_I2S0_8CH_RX_SRC 65
|
||||
#define CLK_I2S0_8CH_RX_FRAC 66
|
||||
#define MCLK_I2S0_8CH_RX 67
|
||||
#define I2S0_MCLKOUT_RX 68
|
||||
#define CLK_I2S1_8CH_TX_SRC 69
|
||||
#define CLK_I2S1_8CH_TX_FRAC 70
|
||||
#define MCLK_I2S1_8CH_TX 71
|
||||
#define I2S1_MCLKOUT_TX 72
|
||||
#define CLK_I2S1_8CH_RX_SRC 73
|
||||
#define CLK_I2S1_8CH_RX_FRAC 74
|
||||
#define MCLK_I2S1_8CH_RX 75
|
||||
#define I2S1_MCLKOUT_RX 76
|
||||
#define CLK_I2S2_2CH_SRC 77
|
||||
#define CLK_I2S2_2CH_FRAC 78
|
||||
#define MCLK_I2S2_2CH 79
|
||||
#define I2S2_MCLKOUT 80
|
||||
#define CLK_I2S3_2CH_TX_SRC 81
|
||||
#define CLK_I2S3_2CH_TX_FRAC 82
|
||||
#define MCLK_I2S3_2CH_TX 83
|
||||
#define I2S3_MCLKOUT_TX 84
|
||||
#define CLK_I2S3_2CH_RX_SRC 85
|
||||
#define CLK_I2S3_2CH_RX_FRAC 86
|
||||
#define MCLK_I2S3_2CH_RX 87
|
||||
#define I2S3_MCLKOUT_RX 88
|
||||
#define HCLK_PDM 89
|
||||
#define MCLK_PDM 90
|
||||
#define HCLK_VAD 91
|
||||
#define HCLK_SPDIF_8CH 92
|
||||
#define MCLK_SPDIF_8CH_SRC 93
|
||||
#define MCLK_SPDIF_8CH_FRAC 94
|
||||
#define MCLK_SPDIF_8CH 95
|
||||
#define HCLK_AUDPWM 96
|
||||
#define SCLK_AUDPWM_SRC 97
|
||||
#define SCLK_AUDPWM_FRAC 98
|
||||
#define SCLK_AUDPWM 99
|
||||
#define HCLK_ACDCDIG 100
|
||||
#define CLK_ACDCDIG_I2C 101
|
||||
#define CLK_ACDCDIG_DAC 102
|
||||
#define CLK_ACDCDIG_ADC 103
|
||||
#define ACLK_SECURE_FLASH 104
|
||||
#define HCLK_SECURE_FLASH 105
|
||||
#define ACLK_CRYPTO_NS 106
|
||||
#define HCLK_CRYPTO_NS 107
|
||||
#define CLK_CRYPTO_NS_CORE 108
|
||||
#define CLK_CRYPTO_NS_PKA 109
|
||||
#define CLK_CRYPTO_NS_RNG 110
|
||||
#define HCLK_TRNG_NS 111
|
||||
#define CLK_TRNG_NS 112
|
||||
#define PCLK_OTPC_NS 113
|
||||
#define CLK_OTPC_NS_SBPI 114
|
||||
#define CLK_OTPC_NS_USR 115
|
||||
#define HCLK_NANDC 116
|
||||
#define NCLK_NANDC 117
|
||||
#define HCLK_SFC 118
|
||||
#define HCLK_SFC_XIP 119
|
||||
#define SCLK_SFC 120
|
||||
#define ACLK_EMMC 121
|
||||
#define HCLK_EMMC 122
|
||||
#define BCLK_EMMC 123
|
||||
#define CCLK_EMMC 124
|
||||
#define TCLK_EMMC 125
|
||||
#define ACLK_PIPE 126
|
||||
#define PCLK_PIPE 127
|
||||
#define PCLK_PIPE_GRF 128
|
||||
#define ACLK_PCIE20_MST 129
|
||||
#define ACLK_PCIE20_SLV 130
|
||||
#define ACLK_PCIE20_DBI 131
|
||||
#define PCLK_PCIE20 132
|
||||
#define CLK_PCIE20_AUX_NDFT 133
|
||||
#define CLK_PCIE20_AUX_DFT 134
|
||||
#define CLK_PCIE20_PIPE_DFT 135
|
||||
#define ACLK_PCIE30X1_MST 136
|
||||
#define ACLK_PCIE30X1_SLV 137
|
||||
#define ACLK_PCIE30X1_DBI 138
|
||||
#define PCLK_PCIE30X1 139
|
||||
#define CLK_PCIE30X1_AUX_NDFT 140
|
||||
#define CLK_PCIE30X1_AUX_DFT 141
|
||||
#define CLK_PCIE30X1_PIPE_DFT 142
|
||||
#define ACLK_PCIE30X2_MST 143
|
||||
#define ACLK_PCIE30X2_SLV 144
|
||||
#define ACLK_PCIE30X2_DBI 145
|
||||
#define PCLK_PCIE30X2 146
|
||||
#define CLK_PCIE30X2_AUX_NDFT 147
|
||||
#define CLK_PCIE30X2_AUX_DFT 148
|
||||
#define CLK_PCIE30X2_PIPE_DFT 149
|
||||
#define ACLK_SATA0 150
|
||||
#define CLK_SATA0_PMALIVE 151
|
||||
#define CLK_SATA0_RXOOB 152
|
||||
#define CLK_SATA0_PIPE_NDFT 153
|
||||
#define CLK_SATA0_PIPE_DFT 154
|
||||
#define ACLK_SATA1 155
|
||||
#define CLK_SATA1_PMALIVE 156
|
||||
#define CLK_SATA1_RXOOB 157
|
||||
#define CLK_SATA1_PIPE_NDFT 158
|
||||
#define CLK_SATA1_PIPE_DFT 159
|
||||
#define ACLK_SATA2 160
|
||||
#define CLK_SATA2_PMALIVE 161
|
||||
#define CLK_SATA2_RXOOB 162
|
||||
#define CLK_SATA2_PIPE_NDFT 163
|
||||
#define CLK_SATA2_PIPE_DFT 164
|
||||
#define ACLK_USB3OTG0 165
|
||||
#define CLK_USB3OTG0_REF 166
|
||||
#define CLK_USB3OTG0_SUSPEND 167
|
||||
#define ACLK_USB3OTG1 168
|
||||
#define CLK_USB3OTG1_REF 169
|
||||
#define CLK_USB3OTG1_SUSPEND 170
|
||||
#define CLK_XPCS_EEE 171
|
||||
#define PCLK_XPCS 172
|
||||
#define ACLK_PHP 173
|
||||
#define HCLK_PHP 174
|
||||
#define PCLK_PHP 175
|
||||
#define HCLK_SDMMC0 176
|
||||
#define CLK_SDMMC0 177
|
||||
#define HCLK_SDMMC1 178
|
||||
#define CLK_SDMMC1 179
|
||||
#define ACLK_GMAC0 180
|
||||
#define PCLK_GMAC0 181
|
||||
#define CLK_MAC0_2TOP 182
|
||||
#define CLK_MAC0_OUT 183
|
||||
#define CLK_MAC0_REFOUT 184
|
||||
#define CLK_GMAC0_PTP_REF 185
|
||||
#define ACLK_USB 186
|
||||
#define HCLK_USB 187
|
||||
#define PCLK_USB 188
|
||||
#define HCLK_USB2HOST0 189
|
||||
#define HCLK_USB2HOST0_ARB 190
|
||||
#define HCLK_USB2HOST1 191
|
||||
#define HCLK_USB2HOST1_ARB 192
|
||||
#define HCLK_SDMMC2 193
|
||||
#define CLK_SDMMC2 194
|
||||
#define ACLK_GMAC1 195
|
||||
#define PCLK_GMAC1 196
|
||||
#define CLK_MAC1_2TOP 197
|
||||
#define CLK_MAC1_OUT 198
|
||||
#define CLK_MAC1_REFOUT 199
|
||||
#define CLK_GMAC1_PTP_REF 200
|
||||
#define ACLK_PERIMID 201
|
||||
#define HCLK_PERIMID 202
|
||||
#define ACLK_VI 203
|
||||
#define HCLK_VI 204
|
||||
#define PCLK_VI 205
|
||||
#define ACLK_VICAP 206
|
||||
#define HCLK_VICAP 207
|
||||
#define DCLK_VICAP 208
|
||||
#define ICLK_VICAP_G 209
|
||||
#define ACLK_ISP 210
|
||||
#define HCLK_ISP 211
|
||||
#define CLK_ISP 212
|
||||
#define PCLK_CSI2HOST1 213
|
||||
#define CLK_CIF_OUT 214
|
||||
#define CLK_CAM0_OUT 215
|
||||
#define CLK_CAM1_OUT 216
|
||||
#define ACLK_VO 217
|
||||
#define HCLK_VO 218
|
||||
#define PCLK_VO 219
|
||||
#define ACLK_VOP_PRE 220
|
||||
#define ACLK_VOP 221
|
||||
#define HCLK_VOP 222
|
||||
#define DCLK_VOP0 223
|
||||
#define DCLK_VOP1 224
|
||||
#define DCLK_VOP2 225
|
||||
#define CLK_VOP_PWM 226
|
||||
#define ACLK_HDCP 227
|
||||
#define HCLK_HDCP 228
|
||||
#define PCLK_HDCP 229
|
||||
#define PCLK_HDMI_HOST 230
|
||||
#define CLK_HDMI_SFR 231
|
||||
#define PCLK_DSITX_0 232
|
||||
#define PCLK_DSITX_1 233
|
||||
#define PCLK_EDP_CTRL 234
|
||||
#define CLK_EDP_200M 235
|
||||
#define ACLK_VPU_PRE 236
|
||||
#define HCLK_VPU_PRE 237
|
||||
#define ACLK_VPU 238
|
||||
#define HCLK_VPU 239
|
||||
#define ACLK_RGA_PRE 240
|
||||
#define HCLK_RGA_PRE 241
|
||||
#define PCLK_RGA_PRE 242
|
||||
#define ACLK_RGA 243
|
||||
#define HCLK_RGA 244
|
||||
#define CLK_RGA_CORE 245
|
||||
#define ACLK_IEP 246
|
||||
#define HCLK_IEP 247
|
||||
#define CLK_IEP_CORE 248
|
||||
#define HCLK_EBC 249
|
||||
#define DCLK_EBC 250
|
||||
#define ACLK_JDEC 251
|
||||
#define HCLK_JDEC 252
|
||||
#define ACLK_JENC 253
|
||||
#define HCLK_JENC 254
|
||||
#define PCLK_EINK 255
|
||||
#define HCLK_EINK 256
|
||||
#define ACLK_RKVENC_PRE 257
|
||||
#define HCLK_RKVENC_PRE 258
|
||||
#define ACLK_RKVENC 259
|
||||
#define HCLK_RKVENC 260
|
||||
#define CLK_RKVENC_CORE 261
|
||||
#define ACLK_RKVDEC_PRE 262
|
||||
#define HCLK_RKVDEC_PRE 263
|
||||
#define ACLK_RKVDEC 264
|
||||
#define HCLK_RKVDEC 265
|
||||
#define CLK_RKVDEC_CA 266
|
||||
#define CLK_RKVDEC_CORE 267
|
||||
#define CLK_RKVDEC_HEVC_CA 268
|
||||
#define ACLK_BUS 269
|
||||
#define PCLK_BUS 270
|
||||
#define PCLK_TSADC 271
|
||||
#define CLK_TSADC_TSEN 272
|
||||
#define CLK_TSADC 273
|
||||
#define PCLK_SARADC 274
|
||||
#define CLK_SARADC 275
|
||||
#define PCLK_SCR 276
|
||||
#define PCLK_WDT_NS 277
|
||||
#define TCLK_WDT_NS 278
|
||||
#define ACLK_DMAC0 279
|
||||
#define ACLK_DMAC1 280
|
||||
#define ACLK_MCU 281
|
||||
#define PCLK_INTMUX 282
|
||||
#define PCLK_MAILBOX 283
|
||||
#define PCLK_UART1 284
|
||||
#define CLK_UART1_SRC 285
|
||||
#define CLK_UART1_FRAC 286
|
||||
#define SCLK_UART1 287
|
||||
#define PCLK_UART2 288
|
||||
#define CLK_UART2_SRC 289
|
||||
#define CLK_UART2_FRAC 290
|
||||
#define SCLK_UART2 291
|
||||
#define PCLK_UART3 292
|
||||
#define CLK_UART3_SRC 293
|
||||
#define CLK_UART3_FRAC 294
|
||||
#define SCLK_UART3 295
|
||||
#define PCLK_UART4 296
|
||||
#define CLK_UART4_SRC 297
|
||||
#define CLK_UART4_FRAC 298
|
||||
#define SCLK_UART4 299
|
||||
#define PCLK_UART5 300
|
||||
#define CLK_UART5_SRC 301
|
||||
#define CLK_UART5_FRAC 302
|
||||
#define SCLK_UART5 303
|
||||
#define PCLK_UART6 304
|
||||
#define CLK_UART6_SRC 305
|
||||
#define CLK_UART6_FRAC 306
|
||||
#define SCLK_UART6 307
|
||||
#define PCLK_UART7 308
|
||||
#define CLK_UART7_SRC 309
|
||||
#define CLK_UART7_FRAC 310
|
||||
#define SCLK_UART7 311
|
||||
#define PCLK_UART8 312
|
||||
#define CLK_UART8_SRC 313
|
||||
#define CLK_UART8_FRAC 314
|
||||
#define SCLK_UART8 315
|
||||
#define PCLK_UART9 316
|
||||
#define CLK_UART9_SRC 317
|
||||
#define CLK_UART9_FRAC 318
|
||||
#define SCLK_UART9 319
|
||||
#define PCLK_CAN0 320
|
||||
#define CLK_CAN0 321
|
||||
#define PCLK_CAN1 322
|
||||
#define CLK_CAN1 323
|
||||
#define PCLK_CAN2 324
|
||||
#define CLK_CAN2 325
|
||||
#define CLK_I2C 326
|
||||
#define PCLK_I2C1 327
|
||||
#define CLK_I2C1 328
|
||||
#define PCLK_I2C2 329
|
||||
#define CLK_I2C2 330
|
||||
#define PCLK_I2C3 331
|
||||
#define CLK_I2C3 332
|
||||
#define PCLK_I2C4 333
|
||||
#define CLK_I2C4 334
|
||||
#define PCLK_I2C5 335
|
||||
#define CLK_I2C5 336
|
||||
#define PCLK_SPI0 337
|
||||
#define CLK_SPI0 338
|
||||
#define PCLK_SPI1 339
|
||||
#define CLK_SPI1 340
|
||||
#define PCLK_SPI2 341
|
||||
#define CLK_SPI2 342
|
||||
#define PCLK_SPI3 343
|
||||
#define CLK_SPI3 344
|
||||
#define PCLK_PWM1 345
|
||||
#define CLK_PWM1 346
|
||||
#define CLK_PWM1_CAPTURE 347
|
||||
#define PCLK_PWM2 348
|
||||
#define CLK_PWM2 349
|
||||
#define CLK_PWM2_CAPTURE 350
|
||||
#define PCLK_PWM3 351
|
||||
#define CLK_PWM3 352
|
||||
#define CLK_PWM3_CAPTURE 353
|
||||
#define DBCLK_GPIO 354
|
||||
#define PCLK_GPIO1 355
|
||||
#define DBCLK_GPIO1 356
|
||||
#define PCLK_GPIO2 357
|
||||
#define DBCLK_GPIO2 358
|
||||
#define PCLK_GPIO3 359
|
||||
#define DBCLK_GPIO3 360
|
||||
#define PCLK_GPIO4 361
|
||||
#define DBCLK_GPIO4 362
|
||||
#define OCC_SCAN_CLK_GPIO 363
|
||||
#define PCLK_TIMER 364
|
||||
#define CLK_TIMER0 365
|
||||
#define CLK_TIMER1 366
|
||||
#define CLK_TIMER2 367
|
||||
#define CLK_TIMER3 368
|
||||
#define CLK_TIMER4 369
|
||||
#define CLK_TIMER5 370
|
||||
#define ACLK_TOP_HIGH 371
|
||||
#define ACLK_TOP_LOW 372
|
||||
#define HCLK_TOP 373
|
||||
#define PCLK_TOP 374
|
||||
#define PCLK_PCIE30PHY 375
|
||||
#define CLK_OPTC_ARB 376
|
||||
#define PCLK_MIPICSIPHY 377
|
||||
#define PCLK_MIPIDSIPHY0 378
|
||||
#define PCLK_MIPIDSIPHY1 379
|
||||
#define PCLK_PIPEPHY0 380
|
||||
#define PCLK_PIPEPHY1 381
|
||||
#define PCLK_PIPEPHY2 382
|
||||
#define PCLK_CPU_BOOST 383
|
||||
#define CLK_CPU_BOOST 384
|
||||
#define PCLK_OTPPHY 385
|
||||
#define SCLK_GMAC0 386
|
||||
#define SCLK_GMAC0_RGMII_SPEED 387
|
||||
#define SCLK_GMAC0_RMII_SPEED 388
|
||||
#define SCLK_GMAC0_RX_TX 389
|
||||
#define SCLK_GMAC1 390
|
||||
#define SCLK_GMAC1_RGMII_SPEED 391
|
||||
#define SCLK_GMAC1_RMII_SPEED 392
|
||||
#define SCLK_GMAC1_RX_TX 393
|
||||
#define SCLK_SDMMC0_DRV 394
|
||||
#define SCLK_SDMMC0_SAMPLE 395
|
||||
#define SCLK_SDMMC1_DRV 396
|
||||
#define SCLK_SDMMC1_SAMPLE 397
|
||||
#define SCLK_SDMMC2_DRV 398
|
||||
#define SCLK_SDMMC2_SAMPLE 399
|
||||
#define SCLK_EMMC_DRV 400
|
||||
#define SCLK_EMMC_SAMPLE 401
|
||||
#define PCLK_EDPPHY_GRF 402
|
||||
#define CLK_HDMI_CEC 403
|
||||
#define CLK_I2S0_8CH_TX 404
|
||||
#define CLK_I2S0_8CH_RX 405
|
||||
#define CLK_I2S1_8CH_TX 406
|
||||
#define CLK_I2S1_8CH_RX 407
|
||||
#define CLK_I2S2_2CH 408
|
||||
#define CLK_I2S3_2CH_TX 409
|
||||
#define CLK_I2S3_2CH_RX 410
|
||||
#define CPLL_500M 411
|
||||
#define CPLL_250M 412
|
||||
#define CPLL_125M 413
|
||||
#define CPLL_62P5M 414
|
||||
#define CPLL_50M 415
|
||||
#define CPLL_25M 416
|
||||
#define CPLL_100M 417
|
||||
#define SCLK_DDRCLK 418
|
||||
|
||||
#define PCLK_CORE_PVTM 450
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
|
||||
|
||||
/* pmu soft-reset indices */
|
||||
/* pmucru_softrst_con0 */
|
||||
#define SRST_P_PDPMU_NIU 0
|
||||
#define SRST_P_PMUCRU 1
|
||||
#define SRST_P_PMUGRF 2
|
||||
#define SRST_P_I2C0 3
|
||||
#define SRST_I2C0 4
|
||||
#define SRST_P_UART0 5
|
||||
#define SRST_S_UART0 6
|
||||
#define SRST_P_PWM0 7
|
||||
#define SRST_PWM0 8
|
||||
#define SRST_P_GPIO0 9
|
||||
#define SRST_GPIO0 10
|
||||
#define SRST_P_PMUPVTM 11
|
||||
#define SRST_PMUPVTM 12
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
#define SRST_NCORERESET0 0
|
||||
#define SRST_NCORERESET1 1
|
||||
#define SRST_NCORERESET2 2
|
||||
#define SRST_NCORERESET3 3
|
||||
#define SRST_NCPUPORESET0 4
|
||||
#define SRST_NCPUPORESET1 5
|
||||
#define SRST_NCPUPORESET2 6
|
||||
#define SRST_NCPUPORESET3 7
|
||||
#define SRST_NSRESET 8
|
||||
#define SRST_NSPORESET 9
|
||||
#define SRST_NATRESET 10
|
||||
#define SRST_NGICRESET 11
|
||||
#define SRST_NPRESET 12
|
||||
#define SRST_NPERIPHRESET 13
|
||||
|
||||
/* cru_softrst_con1 */
|
||||
#define SRST_A_CORE_NIU2DDR 16
|
||||
#define SRST_A_CORE_NIU2BUS 17
|
||||
#define SRST_P_DBG_NIU 18
|
||||
#define SRST_P_DBG 19
|
||||
#define SRST_P_DBG_DAPLITE 20
|
||||
#define SRST_DAP 21
|
||||
#define SRST_A_ADB400_CORE2GIC 22
|
||||
#define SRST_A_ADB400_GIC2CORE 23
|
||||
#define SRST_P_CORE_GRF 24
|
||||
#define SRST_P_CORE_PVTM 25
|
||||
#define SRST_CORE_PVTM 26
|
||||
#define SRST_CORE_PVTPLL 27
|
||||
|
||||
/* cru_softrst_con2 */
|
||||
#define SRST_GPU 32
|
||||
#define SRST_A_GPU_NIU 33
|
||||
#define SRST_P_GPU_NIU 34
|
||||
#define SRST_P_GPU_PVTM 35
|
||||
#define SRST_GPU_PVTM 36
|
||||
#define SRST_GPU_PVTPLL 37
|
||||
#define SRST_A_NPU_NIU 40
|
||||
#define SRST_H_NPU_NIU 41
|
||||
#define SRST_P_NPU_NIU 42
|
||||
#define SRST_A_NPU 43
|
||||
#define SRST_H_NPU 44
|
||||
#define SRST_P_NPU_PVTM 45
|
||||
#define SRST_NPU_PVTM 46
|
||||
#define SRST_NPU_PVTPLL 47
|
||||
|
||||
/* cru_softrst_con3 */
|
||||
#define SRST_A_MSCH 51
|
||||
#define SRST_HWFFC_CTRL 52
|
||||
#define SRST_DDR_ALWAYSON 53
|
||||
#define SRST_A_DDRSPLIT 54
|
||||
#define SRST_DDRDFI_CTL 55
|
||||
#define SRST_A_DMA2DDR 57
|
||||
|
||||
/* cru_softrst_con4 */
|
||||
#define SRST_A_PERIMID_NIU 64
|
||||
#define SRST_H_PERIMID_NIU 65
|
||||
#define SRST_A_GIC_AUDIO_NIU 66
|
||||
#define SRST_H_GIC_AUDIO_NIU 67
|
||||
#define SRST_A_GIC600 68
|
||||
#define SRST_A_GIC600_DEBUG 69
|
||||
#define SRST_A_GICADB_CORE2GIC 70
|
||||
#define SRST_A_GICADB_GIC2CORE 71
|
||||
#define SRST_A_SPINLOCK 72
|
||||
#define SRST_H_SDMMC_BUFFER 73
|
||||
#define SRST_D_SDMMC_BUFFER 74
|
||||
#define SRST_H_I2S0_8CH 75
|
||||
#define SRST_H_I2S1_8CH 76
|
||||
#define SRST_H_I2S2_2CH 77
|
||||
#define SRST_H_I2S3_2CH 78
|
||||
|
||||
/* cru_softrst_con5 */
|
||||
#define SRST_M_I2S0_8CH_TX 80
|
||||
#define SRST_M_I2S0_8CH_RX 81
|
||||
#define SRST_M_I2S1_8CH_TX 82
|
||||
#define SRST_M_I2S1_8CH_RX 83
|
||||
#define SRST_M_I2S2_2CH 84
|
||||
#define SRST_M_I2S3_2CH_TX 85
|
||||
#define SRST_M_I2S3_2CH_RX 86
|
||||
#define SRST_H_PDM 87
|
||||
#define SRST_M_PDM 88
|
||||
#define SRST_H_VAD 89
|
||||
#define SRST_H_SPDIF_8CH 90
|
||||
#define SRST_M_SPDIF_8CH 91
|
||||
#define SRST_H_AUDPWM 92
|
||||
#define SRST_S_AUDPWM 93
|
||||
#define SRST_H_ACDCDIG 94
|
||||
#define SRST_ACDCDIG 95
|
||||
|
||||
/* cru_softrst_con6 */
|
||||
#define SRST_A_SECURE_FLASH_NIU 96
|
||||
#define SRST_H_SECURE_FLASH_NIU 97
|
||||
#define SRST_A_CRYPTO_NS 103
|
||||
#define SRST_H_CRYPTO_NS 104
|
||||
#define SRST_CRYPTO_NS_CORE 105
|
||||
#define SRST_CRYPTO_NS_PKA 106
|
||||
#define SRST_CRYPTO_NS_RNG 107
|
||||
#define SRST_H_TRNG_NS 108
|
||||
#define SRST_TRNG_NS 109
|
||||
|
||||
/* cru_softrst_con7 */
|
||||
#define SRST_H_NANDC 112
|
||||
#define SRST_N_NANDC 113
|
||||
#define SRST_H_SFC 114
|
||||
#define SRST_H_SFC_XIP 115
|
||||
#define SRST_S_SFC 116
|
||||
#define SRST_A_EMMC 117
|
||||
#define SRST_H_EMMC 118
|
||||
#define SRST_B_EMMC 119
|
||||
#define SRST_C_EMMC 120
|
||||
#define SRST_T_EMMC 121
|
||||
|
||||
/* cru_softrst_con8 */
|
||||
#define SRST_A_PIPE_NIU 128
|
||||
#define SRST_P_PIPE_NIU 130
|
||||
#define SRST_P_PIPE_GRF 133
|
||||
#define SRST_A_SATA0 134
|
||||
#define SRST_SATA0_PIPE 135
|
||||
#define SRST_SATA0_PMALIVE 136
|
||||
#define SRST_SATA0_RXOOB 137
|
||||
#define SRST_A_SATA1 138
|
||||
#define SRST_SATA1_PIPE 139
|
||||
#define SRST_SATA1_PMALIVE 140
|
||||
#define SRST_SATA1_RXOOB 141
|
||||
|
||||
/* cru_softrst_con9 */
|
||||
#define SRST_A_SATA2 144
|
||||
#define SRST_SATA2_PIPE 145
|
||||
#define SRST_SATA2_PMALIVE 146
|
||||
#define SRST_SATA2_RXOOB 147
|
||||
#define SRST_USB3OTG0 148
|
||||
#define SRST_USB3OTG1 149
|
||||
#define SRST_XPCS 150
|
||||
#define SRST_XPCS_TX_DIV10 151
|
||||
#define SRST_XPCS_RX_DIV10 152
|
||||
#define SRST_XPCS_XGXS_RX 153
|
||||
|
||||
/* cru_softrst_con10 */
|
||||
#define SRST_P_PCIE20 160
|
||||
#define SRST_PCIE20_POWERUP 161
|
||||
#define SRST_MSTR_ARESET_PCIE20 162
|
||||
#define SRST_SLV_ARESET_PCIE20 163
|
||||
#define SRST_DBI_ARESET_PCIE20 164
|
||||
#define SRST_BRESET_PCIE20 165
|
||||
#define SRST_PERST_PCIE20 166
|
||||
#define SRST_CORE_RST_PCIE20 167
|
||||
#define SRST_NSTICKY_RST_PCIE20 168
|
||||
#define SRST_STICKY_RST_PCIE20 169
|
||||
#define SRST_PWR_RST_PCIE20 170
|
||||
|
||||
/* cru_softrst_con11 */
|
||||
#define SRST_P_PCIE30X1 176
|
||||
#define SRST_PCIE30X1_POWERUP 177
|
||||
#define SRST_M_ARESET_PCIE30X1 178
|
||||
#define SRST_S_ARESET_PCIE30X1 179
|
||||
#define SRST_D_ARESET_PCIE30X1 180
|
||||
#define SRST_BRESET_PCIE30X1 181
|
||||
#define SRST_PERST_PCIE30X1 182
|
||||
#define SRST_CORE_RST_PCIE30X1 183
|
||||
#define SRST_NSTC_RST_PCIE30X1 184
|
||||
#define SRST_STC_RST_PCIE30X1 185
|
||||
#define SRST_PWR_RST_PCIE30X1 186
|
||||
|
||||
/* cru_softrst_con12 */
|
||||
#define SRST_P_PCIE30X2 192
|
||||
#define SRST_PCIE30X2_POWERUP 193
|
||||
#define SRST_M_ARESET_PCIE30X2 194
|
||||
#define SRST_S_ARESET_PCIE30X2 195
|
||||
#define SRST_D_ARESET_PCIE30X2 196
|
||||
#define SRST_BRESET_PCIE30X2 197
|
||||
#define SRST_PERST_PCIE30X2 198
|
||||
#define SRST_CORE_RST_PCIE30X2 199
|
||||
#define SRST_NSTC_RST_PCIE30X2 200
|
||||
#define SRST_STC_RST_PCIE30X2 201
|
||||
#define SRST_PWR_RST_PCIE30X2 202
|
||||
|
||||
/* cru_softrst_con13 */
|
||||
#define SRST_A_PHP_NIU 208
|
||||
#define SRST_H_PHP_NIU 209
|
||||
#define SRST_P_PHP_NIU 210
|
||||
#define SRST_H_SDMMC0 211
|
||||
#define SRST_SDMMC0 212
|
||||
#define SRST_H_SDMMC1 213
|
||||
#define SRST_SDMMC1 214
|
||||
#define SRST_A_GMAC0 215
|
||||
#define SRST_GMAC0_TIMESTAMP 216
|
||||
|
||||
/* cru_softrst_con14 */
|
||||
#define SRST_A_USB_NIU 224
|
||||
#define SRST_H_USB_NIU 225
|
||||
#define SRST_P_USB_NIU 226
|
||||
#define SRST_P_USB_GRF 227
|
||||
#define SRST_H_USB2HOST0 228
|
||||
#define SRST_H_USB2HOST0_ARB 229
|
||||
#define SRST_USB2HOST0_UTMI 230
|
||||
#define SRST_H_USB2HOST1 231
|
||||
#define SRST_H_USB2HOST1_ARB 232
|
||||
#define SRST_USB2HOST1_UTMI 233
|
||||
#define SRST_H_SDMMC2 234
|
||||
#define SRST_SDMMC2 235
|
||||
#define SRST_A_GMAC1 236
|
||||
#define SRST_GMAC1_TIMESTAMP 237
|
||||
|
||||
/* cru_softrst_con15 */
|
||||
#define SRST_A_VI_NIU 240
|
||||
#define SRST_H_VI_NIU 241
|
||||
#define SRST_P_VI_NIU 242
|
||||
#define SRST_A_VICAP 247
|
||||
#define SRST_H_VICAP 248
|
||||
#define SRST_D_VICAP 249
|
||||
#define SRST_I_VICAP 250
|
||||
#define SRST_P_VICAP 251
|
||||
#define SRST_H_ISP 252
|
||||
#define SRST_ISP 253
|
||||
#define SRST_P_CSI2HOST1 255
|
||||
|
||||
/* cru_softrst_con16 */
|
||||
#define SRST_A_VO_NIU 256
|
||||
#define SRST_H_VO_NIU 257
|
||||
#define SRST_P_VO_NIU 258
|
||||
#define SRST_A_VOP_NIU 259
|
||||
#define SRST_A_VOP 260
|
||||
#define SRST_H_VOP 261
|
||||
#define SRST_VOP0 262
|
||||
#define SRST_VOP1 263
|
||||
#define SRST_VOP2 264
|
||||
#define SRST_VOP_PWM 265
|
||||
#define SRST_A_HDCP 266
|
||||
#define SRST_H_HDCP 267
|
||||
#define SRST_P_HDCP 268
|
||||
#define SRST_P_HDMI_HOST 270
|
||||
#define SRST_HDMI_HOST 271
|
||||
|
||||
/* cru_softrst_con17 */
|
||||
#define SRST_P_DSITX_0 272
|
||||
#define SRST_P_DSITX_1 273
|
||||
#define SRST_P_EDP_CTRL 274
|
||||
#define SRST_EDP_24M 275
|
||||
#define SRST_A_VPU_NIU 280
|
||||
#define SRST_H_VPU_NIU 281
|
||||
#define SRST_A_VPU 282
|
||||
#define SRST_H_VPU 283
|
||||
#define SRST_H_EINK 286
|
||||
#define SRST_P_EINK 287
|
||||
|
||||
/* cru_softrst_con18 */
|
||||
#define SRST_A_RGA_NIU 288
|
||||
#define SRST_H_RGA_NIU 289
|
||||
#define SRST_P_RGA_NIU 290
|
||||
#define SRST_A_RGA 292
|
||||
#define SRST_H_RGA 293
|
||||
#define SRST_RGA_CORE 294
|
||||
#define SRST_A_IEP 295
|
||||
#define SRST_H_IEP 296
|
||||
#define SRST_IEP_CORE 297
|
||||
#define SRST_H_EBC 298
|
||||
#define SRST_D_EBC 299
|
||||
#define SRST_A_JDEC 300
|
||||
#define SRST_H_JDEC 301
|
||||
#define SRST_A_JENC 302
|
||||
#define SRST_H_JENC 303
|
||||
|
||||
/* cru_softrst_con19 */
|
||||
#define SRST_A_VENC_NIU 304
|
||||
#define SRST_H_VENC_NIU 305
|
||||
#define SRST_A_RKVENC 307
|
||||
#define SRST_H_RKVENC 308
|
||||
#define SRST_RKVENC_CORE 309
|
||||
|
||||
/* cru_softrst_con20 */
|
||||
#define SRST_A_RKVDEC_NIU 320
|
||||
#define SRST_H_RKVDEC_NIU 321
|
||||
#define SRST_A_RKVDEC 322
|
||||
#define SRST_H_RKVDEC 323
|
||||
#define SRST_RKVDEC_CA 324
|
||||
#define SRST_RKVDEC_CORE 325
|
||||
#define SRST_RKVDEC_HEVC_CA 326
|
||||
|
||||
/* cru_softrst_con21 */
|
||||
#define SRST_A_BUS_NIU 336
|
||||
#define SRST_P_BUS_NIU 338
|
||||
#define SRST_P_CAN0 340
|
||||
#define SRST_CAN0 341
|
||||
#define SRST_P_CAN1 342
|
||||
#define SRST_CAN1 343
|
||||
#define SRST_P_CAN2 344
|
||||
#define SRST_CAN2 345
|
||||
#define SRST_P_GPIO1 346
|
||||
#define SRST_GPIO1 347
|
||||
#define SRST_P_GPIO2 348
|
||||
#define SRST_GPIO2 349
|
||||
#define SRST_P_GPIO3 350
|
||||
#define SRST_GPIO3 351
|
||||
|
||||
/* cru_softrst_con22 */
|
||||
#define SRST_P_GPIO4 352
|
||||
#define SRST_GPIO4 353
|
||||
#define SRST_P_I2C1 354
|
||||
#define SRST_I2C1 355
|
||||
#define SRST_P_I2C2 356
|
||||
#define SRST_I2C2 357
|
||||
#define SRST_P_I2C3 358
|
||||
#define SRST_I2C3 359
|
||||
#define SRST_P_I2C4 360
|
||||
#define SRST_I2C4 361
|
||||
#define SRST_P_I2C5 362
|
||||
#define SRST_I2C5 363
|
||||
#define SRST_P_OTPC_NS 364
|
||||
#define SRST_OTPC_NS_SBPI 365
|
||||
#define SRST_OTPC_NS_USR 366
|
||||
|
||||
/* cru_softrst_con23 */
|
||||
#define SRST_P_PWM1 368
|
||||
#define SRST_PWM1 369
|
||||
#define SRST_P_PWM2 370
|
||||
#define SRST_PWM2 371
|
||||
#define SRST_P_PWM3 372
|
||||
#define SRST_PWM3 373
|
||||
#define SRST_P_SPI0 374
|
||||
#define SRST_SPI0 375
|
||||
#define SRST_P_SPI1 376
|
||||
#define SRST_SPI1 377
|
||||
#define SRST_P_SPI2 378
|
||||
#define SRST_SPI2 379
|
||||
#define SRST_P_SPI3 380
|
||||
#define SRST_SPI3 381
|
||||
|
||||
/* cru_softrst_con24 */
|
||||
#define SRST_P_SARADC 384
|
||||
#define SRST_P_TSADC 385
|
||||
#define SRST_TSADC 386
|
||||
#define SRST_P_TIMER 387
|
||||
#define SRST_TIMER0 388
|
||||
#define SRST_TIMER1 389
|
||||
#define SRST_TIMER2 390
|
||||
#define SRST_TIMER3 391
|
||||
#define SRST_TIMER4 392
|
||||
#define SRST_TIMER5 393
|
||||
#define SRST_P_UART1 394
|
||||
#define SRST_S_UART1 395
|
||||
|
||||
/* cru_softrst_con25 */
|
||||
#define SRST_P_UART2 400
|
||||
#define SRST_S_UART2 401
|
||||
#define SRST_P_UART3 402
|
||||
#define SRST_S_UART3 403
|
||||
#define SRST_P_UART4 404
|
||||
#define SRST_S_UART4 405
|
||||
#define SRST_P_UART5 406
|
||||
#define SRST_S_UART5 407
|
||||
#define SRST_P_UART6 408
|
||||
#define SRST_S_UART6 409
|
||||
#define SRST_P_UART7 410
|
||||
#define SRST_S_UART7 411
|
||||
#define SRST_P_UART8 412
|
||||
#define SRST_S_UART8 413
|
||||
#define SRST_P_UART9 414
|
||||
#define SRST_S_UART9 415
|
||||
|
||||
/* cru_softrst_con26 */
|
||||
#define SRST_P_GRF 416
|
||||
#define SRST_P_GRF_VCCIO12 417
|
||||
#define SRST_P_GRF_VCCIO34 418
|
||||
#define SRST_P_GRF_VCCIO567 419
|
||||
#define SRST_P_SCR 420
|
||||
#define SRST_P_WDT_NS 421
|
||||
#define SRST_T_WDT_NS 422
|
||||
#define SRST_P_DFT2APB 423
|
||||
#define SRST_A_MCU 426
|
||||
#define SRST_P_INTMUX 427
|
||||
#define SRST_P_MAILBOX 428
|
||||
|
||||
/* cru_softrst_con27 */
|
||||
#define SRST_A_TOP_HIGH_NIU 432
|
||||
#define SRST_A_TOP_LOW_NIU 433
|
||||
#define SRST_H_TOP_NIU 434
|
||||
#define SRST_P_TOP_NIU 435
|
||||
#define SRST_P_TOP_CRU 438
|
||||
#define SRST_P_DDRPHY 439
|
||||
#define SRST_DDRPHY 440
|
||||
#define SRST_P_MIPICSIPHY 442
|
||||
#define SRST_P_MIPIDSIPHY0 443
|
||||
#define SRST_P_MIPIDSIPHY1 444
|
||||
#define SRST_P_PCIE30PHY 445
|
||||
#define SRST_PCIE30PHY 446
|
||||
#define SRST_P_PCIE30PHY_GRF 447
|
||||
|
||||
/* cru_softrst_con28 */
|
||||
#define SRST_P_APB2ASB_LEFT 448
|
||||
#define SRST_P_APB2ASB_BOTTOM 449
|
||||
#define SRST_P_ASB2APB_LEFT 450
|
||||
#define SRST_P_ASB2APB_BOTTOM 451
|
||||
#define SRST_P_PIPEPHY0 452
|
||||
#define SRST_PIPEPHY0 453
|
||||
#define SRST_P_PIPEPHY1 454
|
||||
#define SRST_PIPEPHY1 455
|
||||
#define SRST_P_PIPEPHY2 456
|
||||
#define SRST_PIPEPHY2 457
|
||||
#define SRST_P_USB2PHY0_GRF 458
|
||||
#define SRST_P_USB2PHY1_GRF 459
|
||||
#define SRST_P_CPU_BOOST 460
|
||||
#define SRST_CPU_BOOST 461
|
||||
#define SRST_P_OTPPHY 462
|
||||
#define SRST_OTPPHY 463
|
||||
|
||||
/* cru_softrst_con29 */
|
||||
#define SRST_USB2PHY0_POR 464
|
||||
#define SRST_USB2PHY0_USB3OTG0 465
|
||||
#define SRST_USB2PHY0_USB3OTG1 466
|
||||
#define SRST_USB2PHY1_POR 467
|
||||
#define SRST_USB2PHY1_USB2HOST0 468
|
||||
#define SRST_USB2PHY1_USB2HOST1 469
|
||||
#define SRST_P_EDPPHY_GRF 470
|
||||
#define SRST_TSADCPHY 471
|
||||
#define SRST_GMAC0_DELAYLINE 472
|
||||
#define SRST_GMAC1_DELAYLINE 473
|
||||
#define SRST_OTPC_ARB 474
|
||||
#define SRST_P_PIPEPHY0_GRF 475
|
||||
#define SRST_P_PIPEPHY1_GRF 476
|
||||
#define SRST_P_PIPEPHY2_GRF 477
|
||||
|
||||
#endif
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR2_DEFAULT (0)
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
#endif
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3568_PD_CPU_0 0
|
||||
#define RK3568_PD_CPU_1 1
|
||||
#define RK3568_PD_CPU_2 2
|
||||
#define RK3568_PD_CPU_3 3
|
||||
#define RK3568_PD_CORE_ALIVE 4
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3568_PD_PMU 5
|
||||
|
||||
/* VD_NPU */
|
||||
#define RK3568_PD_NPU 6
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3568_PD_GPU 7
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3568_PD_VI 8
|
||||
#define RK3568_PD_VO 9
|
||||
#define RK3568_PD_RGA 10
|
||||
#define RK3568_PD_VPU 11
|
||||
#define RK3568_PD_CENTER 12
|
||||
#define RK3568_PD_RKVDEC 13
|
||||
#define RK3568_PD_RKVENC 14
|
||||
#define RK3568_PD_PIPE 15
|
||||
#define RK3568_PD_LOGIC_ALIVE 16
|
||||
|
||||
#endif
|
82
root/target/linux/rockchip/image/Makefile
Normal file
82
root/target/linux/rockchip/image/Makefile
Normal file
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += UBOOT_DEVICE_NAME
|
||||
|
||||
define Build/Compile
|
||||
$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux
|
||||
endef
|
||||
|
||||
### Image scripts ###
|
||||
define Build/boot-common
|
||||
# This creates a new folder copies the dtb (as rockchip.dtb)
|
||||
# and the kernel image (as kernel.img)
|
||||
rm -fR $@.boot
|
||||
mkdir -p $@.boot
|
||||
|
||||
$(CP) $(DTS_DIR)/$(DEVICE_DTS).dtb $@.boot/rockchip.dtb
|
||||
$(CP) $(IMAGE_KERNEL) $@.boot/kernel.img
|
||||
endef
|
||||
|
||||
define Build/boot-script
|
||||
# Make an U-boot image and copy it to the boot partition
|
||||
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr
|
||||
endef
|
||||
|
||||
define Build/pine64-img
|
||||
# Creates the final SD/eMMC images,
|
||||
# combining boot partition, root partition as well as the u-boot bootloader
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of
|
||||
# alignment padding for the idbloader and u-boot to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
#
|
||||
# U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-idbloader.img of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
|
||||
endef
|
||||
|
||||
define Build/pine64-bin
|
||||
# Typical Rockchip boot flow with Rockchip miniloader
|
||||
# Rockchp idbLoader which is combinded by Rockchip ddr init bin
|
||||
# and miniloader bin from Rockchip rkbin project
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of alignment
|
||||
# padding for the idbloader, uboot and trust image to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-idbloader.bin of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-uboot.img of="$@" seek=16384 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-trust.bin of="$@" seek=24576 conv=notrunc
|
||||
endef
|
||||
|
||||
### Devices ###
|
||||
define Device/Default
|
||||
PROFILES := Default
|
||||
KERNEL := kernel-bin
|
||||
IMAGES := sysupgrade.img.gz
|
||||
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
|
||||
endef
|
||||
|
||||
ifdef CONFIG_LINUX_6_0
|
||||
DTS_CPPFLAGS += -DDTS_NO_LEGACY
|
||||
endif
|
||||
|
||||
include $(SUBTARGET).mk
|
||||
|
||||
$(eval $(call BuildImage))
|
|
@ -2,12 +2,71 @@
|
|||
#
|
||||
# Copyright (C) 2020 Tobias Maedel
|
||||
|
||||
define Device/ezpro_mrkaio-m68s
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform
|
||||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s
|
||||
|
||||
define Device/hinlink_opc-h68k
|
||||
DEVICE_VENDOR := HINLINK
|
||||
DEVICE_MODEL := OPC-H68K
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := opc-h68k-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-mt7921e kmod-r8125
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h68k
|
||||
|
||||
define Device/fastrhino_common
|
||||
DEVICE_VENDOR := FastRhino
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := r66s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125
|
||||
endef
|
||||
|
||||
define Device/fastrhino_r66s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R66S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r66s
|
||||
|
||||
define Device/fastrhino_r68s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R68S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r68s
|
||||
|
||||
define Device/friendlyarm_nanopi-neo3
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi NEO3
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-neo3
|
||||
|
||||
define Device/friendlyarm_nanopi-r2c
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2C
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2c-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2c
|
||||
|
||||
define Device/friendlyarm_nanopi-r2s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2S
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2s
|
||||
|
@ -17,20 +76,61 @@ define Device/friendlyarm_nanopi-r4s
|
|||
DEVICE_MODEL := NanoPi R4S
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4s-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8169
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4s
|
||||
|
||||
define Device/friendlyarm_nanopi-r4se
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R4SE
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4se-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4se
|
||||
|
||||
define Device/friendlyarm_nanopi-r5s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R5S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r5s
|
||||
|
||||
define Device/firefly_station-p2
|
||||
DEVICE_VENDOR := Firefly
|
||||
DEVICE_MODEL := Station P2
|
||||
DEVICE_DTS := rockchip/rk3568-roc-pc
|
||||
UBOOT_DEVICE_NAME := station-p2-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-brcmfmac kmod-ikconfig kmod-ata-ahci-platform station-p2-firmware wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += firefly_station-p2
|
||||
|
||||
define Device/pine64_rockpro64
|
||||
DEVICE_VENDOR := Pine64
|
||||
DEVICE_MODEL := RockPro64
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := rockpro64-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += pine64_rockpro64
|
||||
|
||||
define Device/radxa_rock-3a
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK3 A
|
||||
SOC := rk3568
|
||||
SUPPORTED_DEVICES := radxa,rock3a
|
||||
UBOOT_DEVICE_NAME := rock-3a-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-3a
|
||||
|
||||
define Device/radxa_rock-pi-4
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK Pi 4
|
||||
|
@ -38,5 +138,47 @@ define Device/radxa_rock-pi-4
|
|||
SUPPORTED_DEVICES := radxa,rockpi4
|
||||
UBOOT_DEVICE_NAME := rock-pi-4-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-pi-4
|
||||
|
||||
define Device/radxa_rock-pi-e25
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK Pi E25
|
||||
SOC := rk3568
|
||||
SUPPORTED_DEVICES := radxa,rockpi-e25
|
||||
UBOOT_DEVICE_NAME := rock-pi-e25-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-pi-e25
|
||||
|
||||
define Device/sharevdi_guangmiao-g4c
|
||||
DEVICE_VENDOR := SHAREVDI
|
||||
DEVICE_MODEL := GuangMiao G4C
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := guangmiao-g4c-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += sharevdi_guangmiao-g4c
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus-lts
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus LTS
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-lts-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus-lts
|
||||
|
|
8
root/target/linux/rockchip/image/nanopi-r5s.bootscript
Normal file
8
root/target/linux/rockchip/image/nanopi-r5s.bootscript
Normal file
|
@ -0,0 +1,8 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
|
@ -0,0 +1,25 @@
|
|||
From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Mon, 28 Sep 2020 22:54:52 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
|
||||
|
||||
This adds the compatible property to the NanoPi R2S ethernet PHY node.
|
||||
Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
|
||||
when it is still in reset.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -156,6 +156,8 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c915",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
|
@ -0,0 +1,28 @@
|
|||
From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Thu, 30 Sep 2021 13:05:16 +0200
|
||||
Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc
|
||||
node
|
||||
|
||||
The tsadc node in rk356x.dtsi has more resets then currently supported
|
||||
by the rockchip_thermal.c driver, so use
|
||||
devm_reset_control_array_get() to reset them all.
|
||||
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct
|
||||
if (IS_ERR(thermal->regs))
|
||||
return PTR_ERR(thermal->regs);
|
||||
|
||||
- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
|
||||
+ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
||||
if (IS_ERR(thermal->reset)) {
|
||||
error = PTR_ERR(thermal->reset);
|
||||
dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
|
|
@ -0,0 +1,67 @@
|
|||
From 884d2b845477cd0a18302444dc20fe2d9a01743e Mon Sep 17 00:00:00 2001
|
||||
From: David Wu <david.wu@rock-chips.com>
|
||||
Date: Mon, 13 Dec 2021 19:15:15 +0800
|
||||
Subject: [PATCH] net: stmmac: Add GFP_DMA32 for rx buffers if no 64 capability
|
||||
|
||||
Use page_pool_alloc_pages instead of page_pool_dev_alloc_pages, which
|
||||
can give the gfp parameter, in the case of not supporting 64-bit width,
|
||||
using 32-bit address memory can reduce a copy from swiotlb.
|
||||
|
||||
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 ++++++++++++----
|
||||
1 file changed, 12 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
|
||||
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
|
||||
@@ -1472,16 +1472,20 @@ static int stmmac_init_rx_buffers(struct
|
||||
{
|
||||
struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
|
||||
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
|
||||
+ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
|
||||
+
|
||||
+ if (priv->dma_cap.addr64 <= 32)
|
||||
+ gfp |= GFP_DMA32;
|
||||
|
||||
if (!buf->page) {
|
||||
- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->page)
|
||||
return -ENOMEM;
|
||||
buf->page_offset = stmmac_rx_offset(priv);
|
||||
}
|
||||
|
||||
if (priv->sph && !buf->sec_page) {
|
||||
- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->sec_page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -4618,6 +4622,10 @@ static inline void stmmac_rx_refill(stru
|
||||
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
|
||||
int dirty = stmmac_rx_dirty(priv, queue);
|
||||
unsigned int entry = rx_q->dirty_rx;
|
||||
+ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
|
||||
+
|
||||
+ if (priv->dma_cap.addr64 <= 32)
|
||||
+ gfp |= GFP_DMA32;
|
||||
|
||||
while (dirty-- > 0) {
|
||||
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
|
||||
@@ -4630,13 +4638,13 @@ static inline void stmmac_rx_refill(stru
|
||||
p = rx_q->dma_rx + entry;
|
||||
|
||||
if (!buf->page) {
|
||||
- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->page)
|
||||
break;
|
||||
}
|
||||
|
||||
if (priv->sph && !buf->sec_page) {
|
||||
- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->sec_page)
|
||||
break;
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From 016c0e8a7a6e7820fb54d8ff8a4a2928a3016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 10 Jul 2021 11:10:33 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3566 dtsi
|
||||
|
||||
Add the rk3566 dtsi which includes the soc specific changes for this
|
||||
chip.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210710151034.32857-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
@@ -0,0 +1,20 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "rockchip,rk3566";
|
||||
+};
|
||||
+
|
||||
+&power {
|
||||
+ power-domain@RK3568_PD_PIPE {
|
||||
+ reg = <RK3568_PD_PIPE>;
|
||||
+ clocks = <&cru PCLK_PIPE>;
|
||||
+ pm_qos = <&qos_pcie2x1>,
|
||||
+ <&qos_sata1>,
|
||||
+ <&qos_sata2>,
|
||||
+ <&qos_usb3_0>,
|
||||
+ <&qos_usb3_1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,73 @@
|
|||
From b8d41e5053cd823817344cc5e7a2bfda508effff Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Thu, 29 Jul 2021 11:39:12 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gmac0 node to rk3568
|
||||
|
||||
While both RK3566 and RK3568 feature the gmac1 node, the gmac0
|
||||
node is exclusive to the RK3568.
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 49 ++++++++++++++++++++++++
|
||||
1 file changed, 49 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -22,6 +22,55 @@
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
+
|
||||
+ gmac0: ethernet@fe2a0000 {
|
||||
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq", "eth_wake_irq";
|
||||
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
+ clock-names = "stmmaceth", "mac_clk_rx",
|
||||
+ "mac_clk_tx", "clk_mac_refout",
|
||||
+ "aclk_mac", "pclk_mac",
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
+ resets = <&cru SRST_A_GMAC0>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
+ snps,mixed-burst;
|
||||
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
+ snps,tso;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x0>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
+ snps,blen = <0 0 0 0 16 8 4>;
|
||||
+ snps,rd_osr_lmt = <8>;
|
||||
+ snps,wr_osr_lmt = <4>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_rx_setup: rx-queues-config {
|
||||
+ snps,rx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_tx_setup: tx-queues-config {
|
||||
+ snps,tx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
|
@ -0,0 +1,54 @@
|
|||
From 85a8bccfa945680dc561f06b65ea01341d2033fc Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 23 Jan 2022 14:35:10 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568
|
||||
|
||||
pclk_xpcs is not supported by mainline driver and breaks dtbs_check
|
||||
|
||||
following warnings occour, and many more
|
||||
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
|
||||
[[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
|
||||
[15, 389], [15, 185], [15, 172]] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
|
||||
['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
|
||||
'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
|
||||
after removing it, the clock and other warnings are gone.
|
||||
|
||||
pclk_xpcs on gmac is used to support QSGMII, but this requires a driver
|
||||
supporting it.
|
||||
Once xpcs support is introduced, the clock can be added to the
|
||||
documentation and both controllers.
|
||||
|
||||
Fixes: b8d41e5053cd ("arm64: dts: rockchip: add gmac0 node to rk3568")
|
||||
Co-developed-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220123133510.135651-1-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -32,13 +32,11 @@
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
- <&cru PCLK_XPCS>;
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref",
|
||||
- "pclk_xpcs";
|
||||
+ "clk_mac_speed", "ptp_ref";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
|
@ -0,0 +1,45 @@
|
|||
From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:47 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2
|
||||
|
||||
New Rockchip devices have the usb phy nodes as standalone devices.
|
||||
These nodes have register nodes with #address_cells = 2, but only use 32
|
||||
bit addresses.
|
||||
|
||||
Adjust the driver to check if the returned address is "0", and adjust
|
||||
the index in that case.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++-
|
||||
1 file changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1098,12 +1098,21 @@ static int rockchip_usb2phy_probe(struct
|
||||
rphy->usbgrf = NULL;
|
||||
}
|
||||
|
||||
- if (of_property_read_u32(np, "reg", ®)) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 0, ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ /* support address_cells=2 */
|
||||
+ if (reg == 0) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 1, ®)) {
|
||||
+ dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
+ np);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
|
@ -0,0 +1,44 @@
|
|||
From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:48 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes
|
||||
|
||||
New Rockchip devices have the usb2 phy devices as standalone nodes
|
||||
instead of children of the grf node.
|
||||
Allow the driver to find the grf node from a phandle.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++-----
|
||||
1 file changed, 12 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1081,12 +1081,19 @@ static int rockchip_usb2phy_probe(struct
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- if (!dev->parent || !dev->parent->of_node)
|
||||
- return -EINVAL;
|
||||
+ if (!dev->parent || !dev->parent->of_node) {
|
||||
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
|
||||
+ if (IS_ERR(rphy->grf)) {
|
||||
+ dev_err(dev, "failed to locate usbgrf\n");
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
- if (IS_ERR(rphy->grf))
|
||||
- return PTR_ERR(rphy->grf);
|
||||
+ else {
|
||||
+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(rphy->grf))
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
|
||||
if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
|
||||
rphy->usbgrf =
|
|
@ -0,0 +1,237 @@
|
|||
From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:49 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts
|
||||
|
||||
The rk3568 usb2phy has a single muxed interrupt that handles all
|
||||
interrupts.
|
||||
Allow the driver to plug in only a single interrupt as necessary.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++-----
|
||||
1 file changed, 119 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
|
||||
* @dcd_retries: The retry count used to track Data contact
|
||||
* detection process.
|
||||
* @edev: extcon device for notification registration
|
||||
+ * @irq: muxed interrupt for single irq configuration
|
||||
* @phy_cfg: phy register configuration, assigned by driver data.
|
||||
* @ports: phy port instance.
|
||||
*/
|
||||
@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
|
||||
enum power_supply_type chg_type;
|
||||
u8 dcd_retries;
|
||||
struct extcon_dev *edev;
|
||||
+ int irq;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfg;
|
||||
struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
|
||||
};
|
||||
@@ -934,6 +936,102 @@ static irqreturn_t rockchip_usb2phy_otg_
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy *rphy = data;
|
||||
+ struct rockchip_usb2phy_port *rport;
|
||||
+ irqreturn_t ret = IRQ_NONE;
|
||||
+ unsigned int index;
|
||||
+
|
||||
+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
|
||||
+ rport = &rphy->ports[index];
|
||||
+ if (!rport->phy)
|
||||
+ continue;
|
||||
+
|
||||
+ /* Handle linestate irq for both otg port and host port */
|
||||
+ ret = rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
|
||||
+ struct rockchip_usb2phy_port *rport,
|
||||
+ struct device_node *child_np)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * If the usb2 phy used combined irq for otg and host port,
|
||||
+ * don't need to init otg and host port irq separately.
|
||||
+ */
|
||||
+ if (rphy->irq > 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ switch (rport->port_id) {
|
||||
+ case USB2PHY_PORT_HOST:
|
||||
+ rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
+ if (rport->ls_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
+ return rport->ls_irq;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
+ rockchip_usb2phy_linestate_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy", rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ break;
|
||||
+ case USB2PHY_PORT_OTG:
|
||||
+ /*
|
||||
+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
+ * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
+ * if not found, then look for the regular interrupts one by one.
|
||||
+ */
|
||||
+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
+ if (rport->otg_mux_irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_otg_mux_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_otg",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-mux irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ } else {
|
||||
+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
+ if (rport->bvalid_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
+ ret = rport->bvalid_irq;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_bvalid_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_bvalid",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-bvalid irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
@@ -947,18 +1045,9 @@ static int rockchip_usb2phy_host_port_in
|
||||
mutex_init(&rport->mutex);
|
||||
INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
|
||||
|
||||
- rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
- if (rport->ls_irq < 0) {
|
||||
- dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
- return rport->ls_irq;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
- rockchip_usb2phy_linestate_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy", rport);
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
if (ret) {
|
||||
- dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ dev_err(rphy->dev, "failed to setup host irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1007,44 +1096,10 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
|
||||
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
|
||||
|
||||
- /*
|
||||
- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
- * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
- * if not found, then look for the regular interrupts one by one.
|
||||
- */
|
||||
- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
- if (rport->otg_mux_irq > 0) {
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_otg_mux_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_otg",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-mux irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- } else {
|
||||
- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
- if (rport->bvalid_irq < 0) {
|
||||
- dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
- ret = rport->bvalid_irq;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_bvalid_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_bvalid",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-bvalid irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
+ goto out;
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1124,6 +1179,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
+ rphy->irq = platform_get_irq_optional(pdev, 0);
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
@@ -1203,6 +1259,20 @@ next_child:
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+
|
||||
+ if (rphy->irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
|
||||
+ rockchip_usb2phy_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy",
|
||||
+ rphy);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request usb2phy irq handle\n");
|
||||
+ goto put_child;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
|
@ -0,0 +1,104 @@
|
|||
From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:50 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support
|
||||
|
||||
The rk3568 usb2phy is a standalone device with a single muxed interrupt.
|
||||
Add support for the registers to the usb2phy driver.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++
|
||||
1 file changed, 65 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1100,6 +1100,7 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1511,6 +1512,69 @@ static const struct rockchip_usb2phy_cfg
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
|
||||
+ {
|
||||
+ .reg = 0xfe8a0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
|
||||
+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ /* Select suspend control from controller */
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .opmode = { 0x0000, 3, 0, 5, 1 },
|
||||
+ .cp_det = { 0x00c0, 24, 24, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 23, 23, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 25, 25, 0, 1 },
|
||||
+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
|
||||
+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 9, 9, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
|
||||
+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0xfe8b0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x100,
|
||||
@@ -1560,6 +1624,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
|
||||
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,633 @@
|
|||
From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001
|
||||
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Date: Tue, 8 Feb 2022 17:13:25 +0800
|
||||
Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
|
||||
|
||||
This patch implements a combo phy driver for Rockchip SoCs
|
||||
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
|
||||
sata-phy or sgmii-phy.
|
||||
|
||||
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 8 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++
|
||||
3 files changed, 590 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
|
||||
Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
|
||||
Innosilicon IP block.
|
||||
|
||||
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
|
||||
+ tristate "Rockchip NANENG COMBO PHY Driver"
|
||||
+ depends on ARCH_ROCKCHIP && OF
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
|
||||
+ combo PHY with NaNeng IP block.
|
||||
+
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -0,0 +1,581 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/phy/phy.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/units.h>
|
||||
+
|
||||
+#define BIT_WRITEABLE_SHIFT 16
|
||||
+#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
|
||||
+
|
||||
+/* COMBO PHY REG */
|
||||
+#define PHYREG6 0x14
|
||||
+#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
|
||||
+#define PHYREG6_PLL_DIV_SHIFT 6
|
||||
+#define PHYREG6_PLL_DIV_2 1
|
||||
+
|
||||
+#define PHYREG7 0x18
|
||||
+#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
|
||||
+#define PHYREG7_TX_RTERM_SHIFT 4
|
||||
+#define PHYREG7_TX_RTERM_50OHM 8
|
||||
+#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
|
||||
+#define PHYREG7_RX_RTERM_SHIFT 0
|
||||
+#define PHYREG7_RX_RTERM_44OHM 15
|
||||
+
|
||||
+#define PHYREG8 0x1C
|
||||
+#define PHYREG8_SSC_EN BIT(4)
|
||||
+
|
||||
+#define PHYREG11 0x28
|
||||
+#define PHYREG11_SU_TRIM_0_7 0xF0
|
||||
+
|
||||
+#define PHYREG12 0x2C
|
||||
+#define PHYREG12_PLL_LPF_ADJ_VALUE 4
|
||||
+
|
||||
+#define PHYREG13 0x30
|
||||
+#define PHYREG13_RESISTER_MASK GENMASK(5, 4)
|
||||
+#define PHYREG13_RESISTER_SHIFT 0x4
|
||||
+#define PHYREG13_RESISTER_HIGH_Z 3
|
||||
+#define PHYREG13_CKRCV_AMP0 BIT(7)
|
||||
+
|
||||
+#define PHYREG14 0x34
|
||||
+#define PHYREG14_CKRCV_AMP1 BIT(0)
|
||||
+
|
||||
+#define PHYREG15 0x38
|
||||
+#define PHYREG15_CTLE_EN BIT(0)
|
||||
+#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
|
||||
+#define PHYREG15_SSC_CNT_SHIFT 6
|
||||
+#define PHYREG15_SSC_CNT_VALUE 1
|
||||
+
|
||||
+#define PHYREG16 0x3C
|
||||
+#define PHYREG16_SSC_CNT_VALUE 0x5f
|
||||
+
|
||||
+#define PHYREG18 0x44
|
||||
+#define PHYREG18_PLL_LOOP 0x32
|
||||
+
|
||||
+#define PHYREG32 0x7C
|
||||
+#define PHYREG32_SSC_MASK GENMASK(7, 4)
|
||||
+#define PHYREG32_SSC_DIR_SHIFT 4
|
||||
+#define PHYREG32_SSC_UPWARD 0
|
||||
+#define PHYREG32_SSC_DOWNWARD 1
|
||||
+#define PHYREG32_SSC_OFFSET_SHIFT 6
|
||||
+#define PHYREG32_SSC_OFFSET_500PPM 1
|
||||
+
|
||||
+#define PHYREG33 0x80
|
||||
+#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
|
||||
+#define PHYREG33_PLL_KVCO_SHIFT 2
|
||||
+#define PHYREG33_PLL_KVCO_VALUE 2
|
||||
+
|
||||
+struct rockchip_combphy_priv;
|
||||
+
|
||||
+struct combphy_reg {
|
||||
+ u16 offset;
|
||||
+ u16 bitend;
|
||||
+ u16 bitstart;
|
||||
+ u16 disable;
|
||||
+ u16 enable;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_grfcfg {
|
||||
+ struct combphy_reg pcie_mode_set;
|
||||
+ struct combphy_reg usb_mode_set;
|
||||
+ struct combphy_reg sgmii_mode_set;
|
||||
+ struct combphy_reg qsgmii_mode_set;
|
||||
+ struct combphy_reg pipe_rxterm_set;
|
||||
+ struct combphy_reg pipe_txelec_set;
|
||||
+ struct combphy_reg pipe_txcomp_set;
|
||||
+ struct combphy_reg pipe_clk_25m;
|
||||
+ struct combphy_reg pipe_clk_100m;
|
||||
+ struct combphy_reg pipe_phymode_sel;
|
||||
+ struct combphy_reg pipe_rate_sel;
|
||||
+ struct combphy_reg pipe_rxterm_sel;
|
||||
+ struct combphy_reg pipe_txelec_sel;
|
||||
+ struct combphy_reg pipe_txcomp_sel;
|
||||
+ struct combphy_reg pipe_clk_ext;
|
||||
+ struct combphy_reg pipe_sel_usb;
|
||||
+ struct combphy_reg pipe_sel_qsgmii;
|
||||
+ struct combphy_reg pipe_phy_status;
|
||||
+ struct combphy_reg con0_for_pcie;
|
||||
+ struct combphy_reg con1_for_pcie;
|
||||
+ struct combphy_reg con2_for_pcie;
|
||||
+ struct combphy_reg con3_for_pcie;
|
||||
+ struct combphy_reg con0_for_sata;
|
||||
+ struct combphy_reg con1_for_sata;
|
||||
+ struct combphy_reg con2_for_sata;
|
||||
+ struct combphy_reg con3_for_sata;
|
||||
+ struct combphy_reg pipe_con0_for_sata;
|
||||
+ struct combphy_reg pipe_xpcs_phy_ready;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_cfg {
|
||||
+ const struct rockchip_combphy_grfcfg *grfcfg;
|
||||
+ int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_priv {
|
||||
+ u8 type;
|
||||
+ void __iomem *mmio;
|
||||
+ int num_clks;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ struct device *dev;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct phy *phy;
|
||||
+ struct reset_control *phy_rst;
|
||||
+ const struct rockchip_combphy_cfg *cfg;
|
||||
+ bool enable_ssc;
|
||||
+ bool ext_refclk;
|
||||
+ struct clk *refclk;
|
||||
+};
|
||||
+
|
||||
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
|
||||
+ int mask, int val, int reg)
|
||||
+{
|
||||
+ unsigned int temp;
|
||||
+
|
||||
+ temp = readl(priv->mmio + reg);
|
||||
+ temp = (temp & ~(mask)) | val;
|
||||
+ writel(temp, priv->mmio + reg);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_param_write(struct regmap *base,
|
||||
+ const struct combphy_reg *reg, bool en)
|
||||
+{
|
||||
+ u32 val, mask, tmp;
|
||||
+
|
||||
+ tmp = en ? reg->enable : reg->disable;
|
||||
+ mask = GENMASK(reg->bitend, reg->bitstart);
|
||||
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
|
||||
+
|
||||
+ return regmap_write(base, reg->offset, val);
|
||||
+}
|
||||
+
|
||||
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 mask, val;
|
||||
+
|
||||
+ mask = GENMASK(cfg->pipe_phy_status.bitend,
|
||||
+ cfg->pipe_phy_status.bitstart);
|
||||
+
|
||||
+ regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
|
||||
+ val = (val & mask) >> cfg->pipe_phy_status.bitstart;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 val;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to enable clks\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ if (priv->cfg->combphy_cfg)
|
||||
+ ret = priv->cfg->combphy_cfg(priv);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ ret = -EINVAL;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
|
||||
+ goto err_clk;
|
||||
+ }
|
||||
+
|
||||
+ ret = reset_control_deassert(priv->phy_rst);
|
||||
+ if (ret)
|
||||
+ goto err_clk;
|
||||
+
|
||||
+ if (priv->type == PHY_TYPE_USB3) {
|
||||
+ ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
|
||||
+ priv, val,
|
||||
+ val == cfg->pipe_phy_status.enable,
|
||||
+ 10, 1000);
|
||||
+ if (ret)
|
||||
+ dev_warn(priv->dev, "wait phy status ready timeout\n");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_clk:
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->phy_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_combphy_ops = {
|
||||
+ .init = rockchip_combphy_init,
|
||||
+ .exit = rockchip_combphy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
|
||||
+
|
||||
+ if (args->args_count != 1) {
|
||||
+ dev_err(dev, "invalid number of arguments\n");
|
||||
+ return ERR_PTR(-EINVAL);
|
||||
+ }
|
||||
+
|
||||
+ if (priv->type != PHY_NONE && priv->type != args->args[0])
|
||||
+ dev_warn(dev, "phy type select %d overwriting type %d\n",
|
||||
+ args->args[0], priv->type);
|
||||
+
|
||||
+ priv->type = args->args[0];
|
||||
+
|
||||
+ return priv->phy;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ priv->refclk = NULL;
|
||||
+ for (i = 0; i < priv->num_clks; i++) {
|
||||
+ if (!strncmp(priv->clks[i].id, "ref", 3)) {
|
||||
+ priv->refclk = priv->clks[i].clk;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!priv->refclk) {
|
||||
+ dev_err(dev, "no refclk found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
|
||||
+ return PTR_ERR(priv->pipe_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
|
||||
+
|
||||
+ priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
|
||||
+
|
||||
+ priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
|
||||
+ if (IS_ERR(priv->phy_rst))
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_combphy_priv *priv;
|
||||
+ const struct rockchip_combphy_cfg *phy_cfg;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ phy_cfg = of_device_get_match_data(dev);
|
||||
+ if (!phy_cfg) {
|
||||
+ dev_err(dev, "no OF match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->dev = dev;
|
||||
+ priv->type = PHY_NONE;
|
||||
+ priv->cfg = phy_cfg;
|
||||
+
|
||||
+ ret = rockchip_combphy_parse_dt(dev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = reset_control_assert(priv->phy_rst);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to reset phy\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ unsigned long rate;
|
||||
+ u32 val;
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ /* Enable adaptive CTLE for USB3.0 Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+
|
||||
+ /* Set PLL KVCO fine tuning signals. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
|
||||
+ PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ /* Set PLL input clock divider 1/2. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
|
||||
+ PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ /* Enable adaptive CTLE for SATA Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+ /*
|
||||
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
+ */
|
||||
+ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
+ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
+ writel(val, priv->mmio + PHYREG7);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rate = clk_get_rate(priv->refclk);
|
||||
+
|
||||
+ switch (rate) {
|
||||
+ case REF_CLOCK_24MHz:
|
||||
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
+ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
+ val, PHYREG15);
|
||||
+
|
||||
+ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_25MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_100MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE) {
|
||||
+ /* PLL KVCO fine tuning. */
|
||||
+ val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ val, PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ val, PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+ } else if (priv->type == PHY_TYPE_SATA) {
|
||||
+ /* downward spread spectrum +500ppm */
|
||||
+ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
+ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "unsupported rate: %lu\n", rate);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (priv->ext_refclk) {
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
+ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
+ val |= PHYREG13_CKRCV_AMP0;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
+
|
||||
+ val = readl(priv->mmio + PHYREG14);
|
||||
+ val |= PHYREG14_CKRCV_AMP1;
|
||||
+ writel(val, priv->mmio + PHYREG14);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (priv->enable_ssc) {
|
||||
+ val = readl(priv->mmio + PHYREG8);
|
||||
+ val |= PHYREG8_SSC_EN;
|
||||
+ writel(val, priv->mmio + PHYREG8);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
|
||||
+ /* pipe-phy-grf */
|
||||
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
||||
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
||||
+ .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
|
||||
+ .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
|
||||
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
||||
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
|
||||
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
|
||||
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
||||
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
|
||||
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
|
||||
+ /* pipe-grf */
|
||||
+ .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
|
||||
+ .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
||||
+ .grfcfg = &rk3568_combphy_grfcfgs,
|
||||
+ .combphy_cfg = rk3568_combphy_cfg,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rockchip_combphy_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3568-naneng-combphy",
|
||||
+ .data = &rk3568_combphy_cfgs,
|
||||
+ },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_combphy_driver = {
|
||||
+ .probe = rockchip_combphy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-naneng-combphy",
|
||||
+ .of_match_table = rockchip_combphy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_combphy_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
|
@ -0,0 +1,46 @@
|
|||
From 62b20e6e0dde8d5633e3d94b028f86fb24b31d22 Mon Sep 17 00:00:00 2001
|
||||
From: Bin Yang <yangbin@rock-chips.com>
|
||||
Date: Mon, 28 Feb 2022 08:56:56 -0500
|
||||
Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0
|
||||
mode
|
||||
|
||||
In the 3.0 device core, if the core is programmed to operate in
|
||||
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
|
||||
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
|
||||
clock. Enabling this feature allows the pipe3 clock to be not-running
|
||||
when forcibly operating in 2.0 device mode.
|
||||
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/usb/dwc3/core.c | 5 +++++
|
||||
drivers/usb/dwc3/core.h | 1 +
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -1081,6 +1081,11 @@ static int dwc3_core_init(struct dwc3 *d
|
||||
if (dwc->parkmode_disable_ss_quirk)
|
||||
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
||||
|
||||
+ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
|
||||
+ (dwc->maximum_speed == USB_SPEED_HIGH ||
|
||||
+ dwc->maximum_speed == USB_SPEED_FULL))
|
||||
+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
|
||||
+
|
||||
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||||
}
|
||||
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -258,6 +258,7 @@
|
||||
/* Global User Control 1 Register */
|
||||
#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
|
||||
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||||
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
|
||||
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
||||
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
|
||||
#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
|
|
@ -0,0 +1,54 @@
|
|||
From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:34 -0500
|
||||
Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers
|
||||
|
||||
Host drivers may not be able to support frequencies as low as dw-mmc
|
||||
supports. Unfortunately f_min isn't available when the drv_data->init
|
||||
function is called, as the mmc_host struct hasn't been set up yet.
|
||||
|
||||
Support the host drivers saving the requested minimum frequency, so we
|
||||
can later set f_min when it is available.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc.c | 7 ++++++-
|
||||
drivers/mmc/host/dw_mmc.h | 2 ++
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.c
|
||||
+++ b/drivers/mmc/host/dw_mmc.c
|
||||
@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct
|
||||
if (host->pdata->caps2)
|
||||
mmc->caps2 = host->pdata->caps2;
|
||||
|
||||
- mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+ /* if host has set a minimum_freq, we should respect it */
|
||||
+ if (host->minimum_speed)
|
||||
+ mmc->f_min = host->minimum_speed;
|
||||
+ else
|
||||
+ mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+
|
||||
if (!mmc->f_max)
|
||||
mmc->f_max = DW_MCI_FREQ_MAX;
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.h
|
||||
+++ b/drivers/mmc/host/dw_mmc.h
|
||||
@@ -99,6 +99,7 @@ struct dw_mci_dma_slave {
|
||||
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
||||
* rate and timeout calculations.
|
||||
* @current_speed: Configured rate of the controller.
|
||||
+ * @minimum_speed: Stored minimum rate of the controller.
|
||||
* @fifoth_val: The value of FIFOTH register.
|
||||
* @verid: Denote Version ID.
|
||||
* @dev: Device associated with the MMC controller.
|
||||
@@ -200,6 +201,7 @@ struct dw_mci {
|
||||
|
||||
u32 bus_hz;
|
||||
u32 current_speed;
|
||||
+ u32 minimum_speed;
|
||||
u32 fifoth_val;
|
||||
u16 verid;
|
||||
struct device *dev;
|
|
@ -0,0 +1,79 @@
|
|||
From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:35 -0500
|
||||
Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
|
||||
|
||||
The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
|
||||
hardware supports. This leads to a situation during card initialization
|
||||
where the clock is set lower than the clock driver can support. The
|
||||
dw-mmc-rockchip driver spews errors when this happens.
|
||||
For normal operation this only happens a few times during boot, but when
|
||||
cd-broken is enabled (in cases such as the SoQuartz module) this fires
|
||||
multiple times each poll cycle.
|
||||
|
||||
Fix this by testing the lowest possible frequency that the clock driver
|
||||
can support which is within the mmc specification. Divide that rate by
|
||||
the internal divider and set f_min to this.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
|
||||
1 file changed, 23 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
@@ -15,7 +15,9 @@
|
||||
#include "dw_mmc.h"
|
||||
#include "dw_mmc-pltfm.h"
|
||||
|
||||
-#define RK3288_CLKGEN_DIV 2
|
||||
+#define RK3288_CLKGEN_DIV 2
|
||||
+
|
||||
+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
|
||||
|
||||
struct dw_mci_rockchip_priv_data {
|
||||
struct clk *drv_clk;
|
||||
@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct
|
||||
|
||||
ret = clk_set_rate(host->ciu_clk, cclkin);
|
||||
if (ret)
|
||||
- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
|
||||
+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
|
||||
|
||||
bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
|
||||
if (bus_hz != host->bus_hz) {
|
||||
@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct
|
||||
|
||||
static int dw_mci_rockchip_init(struct dw_mci *host)
|
||||
{
|
||||
+ int ret, i;
|
||||
+
|
||||
/* It is slot 8 on Rockchip SoCs */
|
||||
host->sdio_id0 = 8;
|
||||
|
||||
- if (of_device_is_compatible(host->dev->of_node,
|
||||
- "rockchip,rk3288-dw-mshc"))
|
||||
+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
|
||||
host->bus_hz /= RK3288_CLKGEN_DIV;
|
||||
|
||||
+ /* clock driver will fail if the clock is less than the lowest source clock
|
||||
+ * divided by the internal clock divider. Test for the lowest available
|
||||
+ * clock and set the minimum freq to clock / clock divider.
|
||||
+ */
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(freqs); i++) {
|
||||
+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
|
||||
+ if (ret > 0) {
|
||||
+ host->minimum_speed = ret / RK3288_CLKGEN_DIV;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ if (ret < 0)
|
||||
+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megous@megous.com>
|
||||
Date: Sun, 29 Aug 2021 04:51:53 +0200
|
||||
Subject: [PATCH] mfd: rk808: Add support for power off on RK817
|
||||
|
||||
RK817 has a power-off bit in SYS_CFG3. Add support for powering
|
||||
off the PMIC.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_OFF;
|
||||
+ break;
|
||||
case RK818_ID:
|
||||
reg = RK818_DEVCTRL_REG;
|
||||
bit = DEV_OFF;
|
|
@ -0,0 +1,110 @@
|
|||
From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Tue, 8 Feb 2022 14:40:23 -0500
|
||||
Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c
|
||||
|
||||
This adds reboot support to the rk808 pmic driver and enables it for
|
||||
the rk809 and rk817 devices.
|
||||
This only enables if the rockchip,system-power-controller flag is set.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com
|
||||
---
|
||||
drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++
|
||||
include/linux/mfd/rk808.h | 1 +
|
||||
2 files changed, 45 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/reboot.h>
|
||||
|
||||
struct rk808_reg_data {
|
||||
int addr;
|
||||
@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK809_ID:
|
||||
case RK817_ID:
|
||||
reg = RK817_SYS_CFG(3);
|
||||
bit = DEV_OFF;
|
||||
@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void)
|
||||
dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
|
||||
}
|
||||
|
||||
+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
|
||||
+{
|
||||
+ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
+ unsigned int reg, bit;
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_RST;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ return NOTIFY_DONE;
|
||||
+ }
|
||||
+ ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
+ if (ret)
|
||||
+ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block rk808_restart_handler = {
|
||||
+ .notifier_call = rk808_restart_notify,
|
||||
+ .priority = 192,
|
||||
+};
|
||||
+
|
||||
static void rk8xx_shutdown(struct i2c_client *client)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(client);
|
||||
@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client
|
||||
if (of_property_read_bool(np, "rockchip,system-power-controller")) {
|
||||
rk808_i2c_client = client;
|
||||
pm_power_off = rk808_pm_power_off;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ ret = register_restart_handler(&rk808_restart_handler);
|
||||
+ if (ret)
|
||||
+ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(&client->dev, "pmic controlled board reset not supported\n");
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_clien
|
||||
if (pm_power_off == rk808_pm_power_off)
|
||||
pm_power_off = NULL;
|
||||
|
||||
+ unregister_restart_handler(&rk808_restart_handler);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/include/linux/mfd/rk808.h
|
||||
+++ b/include/linux/mfd/rk808.h
|
||||
@@ -373,6 +373,7 @@ enum rk805_reg {
|
||||
#define SWITCH2_EN BIT(6)
|
||||
#define SWITCH1_EN BIT(5)
|
||||
#define DEV_OFF_RST BIT(3)
|
||||
+#define DEV_RST BIT(2)
|
||||
#define DEV_OFF BIT(0)
|
||||
#define RTC_STOP BIT(0)
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 8 Apr 2022 11:12:34 -0400
|
||||
Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566
|
||||
|
||||
The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
|
||||
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
|
||||
we need to set the clock source to the usb2 phy instead.
|
||||
|
||||
Add handling to the grf driver to handle this on boot.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/drivers/soc/rockchip/grf.c
|
||||
+++ b/drivers/soc/rockchip/grf.c
|
||||
@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk
|
||||
.num_values = ARRAY_SIZE(rk3399_defaults),
|
||||
};
|
||||
|
||||
+#define RK3566_GRF_USB3OTG0_CON1 0x0104
|
||||
+
|
||||
+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
|
||||
+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
|
||||
+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
|
||||
+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
|
||||
+ .values = rk3566_defaults,
|
||||
+ .num_values = ARRAY_SIZE(rk3566_defaults),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
|
||||
{
|
||||
.compatible = "rockchip,rk3036-grf",
|
||||
@@ -130,6 +144,9 @@ static const struct of_device_id rockchi
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-grf",
|
||||
.data = (void *)&rk3399_grf,
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk3566-pipe-grf",
|
||||
+ .data = (void *)&rk3566_pipegrf,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
|
@ -0,0 +1,72 @@
|
|||
From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:28 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe
|
||||
|
||||
The PCIe controller is in an unknown state at driver probe. This can
|
||||
lead to undesireable effects when the driver attempts to configure the
|
||||
controller.
|
||||
|
||||
Prevent issues in the future by resetting the core during probe.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com
|
||||
Tested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++-----------
|
||||
1 file changed, 10 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(st
|
||||
if (IS_ERR(rockchip->rst_gpio))
|
||||
return PTR_ERR(rockchip->rst_gpio);
|
||||
|
||||
+ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
|
||||
+ if (IS_ERR(rockchip->rst))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
|
||||
+ "failed to get reset lines\n");
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(str
|
||||
phy_power_off(rockchip->phy);
|
||||
}
|
||||
|
||||
-static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
|
||||
-{
|
||||
- struct device *dev = rockchip->pci.dev;
|
||||
-
|
||||
- rockchip->rst = devm_reset_control_array_get_exclusive(dev);
|
||||
- if (IS_ERR(rockchip->rst))
|
||||
- return dev_err_probe(dev, PTR_ERR(rockchip->rst),
|
||||
- "failed to get reset lines\n");
|
||||
-
|
||||
- return reset_control_deassert(rockchip->rst);
|
||||
-}
|
||||
-
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = rockchip_pcie_link_up,
|
||||
.start_link = rockchip_pcie_start_link,
|
||||
@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ ret = reset_control_assert(rockchip->rst);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
/* DON'T MOVE ME: must be enable before PHY init */
|
||||
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
|
||||
if (IS_ERR(rockchip->vpcie3v3)) {
|
||||
@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
goto disable_regulator;
|
||||
|
||||
- ret = rockchip_pcie_reset_control_release(rockchip);
|
||||
+ ret = reset_control_deassert(rockchip->rst);
|
||||
if (ret)
|
||||
goto deinit_phy;
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:29 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support
|
||||
|
||||
The legacy interrupts on the rk356x PCIe controller are handled by a
|
||||
single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip
|
||||
driver to support the virtual domain.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Reviewed-by: Marc Zyngier <maz@kernel.org>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++-
|
||||
1 file changed, 94 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -10,9 +10,12 @@
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
+#include <linux/irqchip/chained_irq.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
+#include <linux/of_irq.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
@@ -26,6 +29,7 @@
|
||||
*/
|
||||
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
|
||||
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
|
||||
+#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
|
||||
|
||||
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
|
||||
|
||||
@@ -36,10 +40,12 @@
|
||||
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
|
||||
#define PCIE_L0S_ENTRY 0x11
|
||||
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
|
||||
+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
|
||||
+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
|
||||
#define PCIE_CLIENT_GENERAL_DEBUG 0x104
|
||||
-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
#define PCIE_CLIENT_LTSSM_STATUS 0x300
|
||||
-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
|
||||
|
||||
struct rockchip_pcie {
|
||||
@@ -51,6 +57,7 @@ struct rockchip_pcie {
|
||||
struct reset_control *rst;
|
||||
struct gpio_desc *rst_gpio;
|
||||
struct regulator *vpcie3v3;
|
||||
+ struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
|
||||
@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(str
|
||||
writel_relaxed(val, rockchip->apb_base + reg);
|
||||
}
|
||||
|
||||
+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
|
||||
+ unsigned long reg, hwirq;
|
||||
+
|
||||
+ chained_irq_enter(chip, desc);
|
||||
+
|
||||
+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
|
||||
+
|
||||
+ for_each_set_bit(hwirq, ®, 4)
|
||||
+ generic_handle_domain_irq(rockchip->irq_domain, hwirq);
|
||||
+
|
||||
+ chained_irq_exit(chip, desc);
|
||||
+}
|
||||
+
|
||||
+static void rockchip_intx_mask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_UPDATE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static void rockchip_intx_unmask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_DISABLE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static struct irq_chip rockchip_intx_irq_chip = {
|
||||
+ .name = "INTx",
|
||||
+ .irq_mask = rockchip_intx_mask,
|
||||
+ .irq_unmask = rockchip_intx_unmask,
|
||||
+ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
||||
+ irq_hw_number_t hwirq)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, domain->host_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops intx_domain_ops = {
|
||||
+ .map = rockchip_pcie_intx_map,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
|
||||
+{
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
+ struct device_node *intc;
|
||||
+
|
||||
+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
|
||||
+ if (!intc) {
|
||||
+ dev_err(dev, "missing child interrupt-controller node\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
|
||||
+ &intx_domain_ops, rockchip);
|
||||
+ of_node_put(intc);
|
||||
+ if (!rockchip->irq_domain) {
|
||||
+ dev_err(dev, "failed to get a INTx IRQ domain\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
|
||||
{
|
||||
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
|
||||
@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struc
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
|
||||
+ int irq, ret;
|
||||
+
|
||||
+ irq = of_irq_get_byname(dev->of_node, "legacy");
|
||||
+ if (irq < 0)
|
||||
+ return irq;
|
||||
+
|
||||
+ ret = rockchip_pcie_init_irq_domain(rockchip);
|
||||
+ if (ret < 0)
|
||||
+ dev_err(dev, "failed to init irq domain\n");
|
||||
+
|
||||
+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
|
||||
+ rockchip);
|
||||
|
||||
/* LTSSM enable control mode */
|
||||
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
|
|
@ -0,0 +1,123 @@
|
|||
From d0637c505f8a1d8c4088642f1f3e9e3b22da14f6 Mon Sep 17 00:00:00 2001
|
||||
From: Barry Song <v-songbaohua@oppo.com>
|
||||
Date: Wed, 20 Jul 2022 21:37:37 +1200
|
||||
Subject: [PATCH] arm64: enable THP_SWAP for arm64
|
||||
|
||||
THP_SWAP has been proven to improve the swap throughput significantly
|
||||
on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay
|
||||
splitting THP after swapped out").
|
||||
As long as arm64 uses 4K page size, it is quite similar with x86_64
|
||||
by having 2MB PMD THP. THP_SWAP is architecture-independent, thus,
|
||||
enabling it on arm64 will benefit arm64 as well.
|
||||
A corner case is that MTE has an assumption that only base pages
|
||||
can be swapped. We won't enable THP_SWAP for ARM64 hardware with
|
||||
MTE support until MTE is reworked to coexist with THP_SWAP.
|
||||
|
||||
A micro-benchmark is written to measure thp swapout throughput as
|
||||
below,
|
||||
|
||||
unsigned long long tv_to_ms(struct timeval tv)
|
||||
{
|
||||
return tv.tv_sec * 1000 + tv.tv_usec / 1000;
|
||||
}
|
||||
|
||||
main()
|
||||
{
|
||||
struct timeval tv_b, tv_e;;
|
||||
#define SIZE 400*1024*1024
|
||||
volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE,
|
||||
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
|
||||
if (!p) {
|
||||
perror("fail to get memory");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
madvise(p, SIZE, MADV_HUGEPAGE);
|
||||
memset(p, 0x11, SIZE); /* write to get mem */
|
||||
|
||||
gettimeofday(&tv_b, NULL);
|
||||
madvise(p, SIZE, MADV_PAGEOUT);
|
||||
gettimeofday(&tv_e, NULL);
|
||||
|
||||
printf("swp out bandwidth: %ld bytes/ms\n",
|
||||
SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b)));
|
||||
}
|
||||
|
||||
Testing is done on rk3568 64bit Quad Core Cortex-A55 platform -
|
||||
ROCK 3A.
|
||||
thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests)
|
||||
thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests)
|
||||
|
||||
Cc: "Huang, Ying" <ying.huang@intel.com>
|
||||
Cc: Minchan Kim <minchan@kernel.org>
|
||||
Cc: Johannes Weiner <hannes@cmpxchg.org>
|
||||
Cc: Hugh Dickins <hughd@google.com>
|
||||
Cc: Andrea Arcangeli <aarcange@redhat.com>
|
||||
Cc: Steven Price <steven.price@arm.com>
|
||||
Cc: Yang Shi <shy828301@gmail.com>
|
||||
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
|
||||
Signed-off-by: Barry Song <v-songbaohua@oppo.com>
|
||||
Link: https://lore.kernel.org/r/20220720093737.133375-1-21cnbao@gmail.com
|
||||
Signed-off-by: Will Deacon <will@kernel.org>
|
||||
---
|
||||
arch/arm64/Kconfig | 1 +
|
||||
arch/arm64/include/asm/pgtable.h | 6 ++++++
|
||||
include/linux/huge_mm.h | 12 ++++++++++++
|
||||
mm/swap_slots.c | 2 +-
|
||||
4 files changed, 20 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -95,6 +95,7 @@ config ARM64
|
||||
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_WANTS_NO_INSTR
|
||||
+ select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
|
||||
select ARCH_HAS_UBSAN_SANITIZE_ALL
|
||||
select ARM_AMBA
|
||||
select ARM_ARCH_TIMER
|
||||
--- a/arch/arm64/include/asm/pgtable.h
|
||||
+++ b/arch/arm64/include/asm/pgtable.h
|
||||
@@ -44,6 +44,12 @@
|
||||
__flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
|
||||
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
||||
|
||||
+static inline bool arch_thp_swp_supported(void)
|
||||
+{
|
||||
+ return !system_supports_mte();
|
||||
+}
|
||||
+#define arch_thp_swp_supported arch_thp_swp_supported
|
||||
+
|
||||
/*
|
||||
* Outside of a few very special situations (e.g. hibernation), we always
|
||||
* use broadcast TLB invalidation instructions, therefore a spurious page
|
||||
--- a/include/linux/huge_mm.h
|
||||
+++ b/include/linux/huge_mm.h
|
||||
@@ -495,4 +495,16 @@ static inline unsigned long thp_size(str
|
||||
return PAGE_SIZE << thp_order(page);
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to
|
||||
+ * limitations in the implementation like arm64 MTE can override this to
|
||||
+ * false
|
||||
+ */
|
||||
+#ifndef arch_thp_swp_supported
|
||||
+static inline bool arch_thp_swp_supported(void)
|
||||
+{
|
||||
+ return true;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
#endif /* _LINUX_HUGE_MM_H */
|
||||
--- a/mm/swap_slots.c
|
||||
+++ b/mm/swap_slots.c
|
||||
@@ -308,7 +308,7 @@ swp_entry_t get_swap_page(struct page *p
|
||||
entry.val = 0;
|
||||
|
||||
if (PageTransHuge(page)) {
|
||||
- if (IS_ENABLED(CONFIG_THP_SWAP))
|
||||
+ if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported())
|
||||
get_swap_pages(1, &entry, HPAGE_PMD_NR);
|
||||
goto out;
|
||||
}
|
|
@ -0,0 +1,67 @@
|
|||
From 604be85547ce4d61b89292d2f9a78c721b778c16 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Fri, 22 Apr 2022 09:28:39 +0200
|
||||
Subject: [PATCH] drm/rockchip: Add VOP2 driver
|
||||
|
||||
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
|
||||
It replaces the VOP unit found in the older Rockchip SoCs.
|
||||
|
||||
This driver has been derived from the downstream Rockchip Kernel and
|
||||
heavily modified:
|
||||
|
||||
- All nonstandard DRM properties have been removed
|
||||
- dropped struct vop2_plane_state and pass around less data between
|
||||
functions
|
||||
- Dropped all DRM_FORMAT_* not known on upstream
|
||||
- rework register access to get rid of excessively used macros
|
||||
- Drop all waiting for framesyncs
|
||||
|
||||
The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
|
||||
board. Overlay support is tested with the modetest utility. AFBC support
|
||||
on the cluster windows is tested with weston-simple-dmabuf-egl on
|
||||
weston using the (yet to be upstreamed) panfrost driver support.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Co-Developed-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
[dt-binding-header:]
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
[moved dt-binding header from dt-nodes patch to here
|
||||
and made checkpatch --strict happier]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/Kconfig | 6 +
|
||||
drivers/gpu/drm/rockchip/Makefile | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 6 +-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ++++++++++++++++++
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++
|
||||
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++
|
||||
include/dt-bindings/soc/rockchip,vop2.h | 14 +
|
||||
10 files changed, 3507 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
|
||||
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/soc/rockchip,vop2.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
+
|
||||
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+
|
||||
+#define ROCKCHIP_VOP2_EP_RGB0 1
|
||||
+#define ROCKCHIP_VOP2_EP_HDMI0 2
|
||||
+#define ROCKCHIP_VOP2_EP_EDP0 3
|
||||
+#define ROCKCHIP_VOP2_EP_MIPI0 4
|
||||
+#define ROCKCHIP_VOP2_EP_LVDS0 5
|
||||
+#define ROCKCHIP_VOP2_EP_MIPI1 6
|
||||
+#define ROCKCHIP_VOP2_EP_LVDS1 7
|
||||
+
|
||||
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
|
|
@ -0,0 +1,394 @@
|
|||
From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001
|
||||
From: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Date: Thu, 25 Aug 2022 21:38:34 +0200
|
||||
Subject: [PATCH] phy: rockchip: Support PCIe v3
|
||||
|
||||
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
|
||||
It use a dedicated PCIe-phy. Add support for this.
|
||||
|
||||
Initial support by Shawn Lin, modifications by Peter Geis and Frank
|
||||
Wunderlich.
|
||||
|
||||
Add data-lanes property for splitting pcie-lanes across controllers.
|
||||
|
||||
The data-lanes is an array where x=0 means lane is disabled and x > 0
|
||||
means controller x is assigned to phy lane.
|
||||
|
||||
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Suggested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 9 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++
|
||||
include/linux/phy/pcie.h | 12 +
|
||||
4 files changed, 341 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
create mode 100644 include/linux/phy/pcie.h
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
|
||||
help
|
||||
Enable this to support the Rockchip PCIe PHY.
|
||||
|
||||
+config PHY_ROCKCHIP_SNPS_PCIE3
|
||||
+ tristate "Rockchip Snps PCIe3 PHY Driver"
|
||||
+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
+ depends on HAS_IOMEM
|
||||
+ select GENERIC_PHY
|
||||
+ select MFD_SYSCON
|
||||
+ help
|
||||
+ Enable this to support the Rockchip snps PCIe3 PHY.
|
||||
+
|
||||
config PHY_ROCKCHIP_TYPEC
|
||||
tristate "Rockchip TYPEC PHY Driver"
|
||||
depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) +=
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -0,0 +1,319 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PCIE3.0 phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/iopoll.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/pcie.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+
|
||||
+/* Register for RK3568 */
|
||||
+#define GRF_PCIE30PHY_CON1 0x4
|
||||
+#define GRF_PCIE30PHY_CON6 0x18
|
||||
+#define GRF_PCIE30PHY_CON9 0x24
|
||||
+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
+#define GRF_PCIE30PHY_STATUS0 0x80
|
||||
+#define GRF_PCIE30PHY_WR_EN (0xf << 16)
|
||||
+#define SRAM_INIT_DONE(reg) (reg & BIT(14))
|
||||
+
|
||||
+#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+
|
||||
+/* Register for RK3588 */
|
||||
+#define PHP_GRF_PCIESEL_CON 0x100
|
||||
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
+
|
||||
+#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
+#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
+
|
||||
+struct rockchip_p3phy_ops;
|
||||
+
|
||||
+struct rockchip_p3phy_priv {
|
||||
+ const struct rockchip_p3phy_ops *ops;
|
||||
+ void __iomem *mmio;
|
||||
+ /* mode: RC, EP */
|
||||
+ int mode;
|
||||
+ /* pcie30_phymode: Aggregation, Bifurcation */
|
||||
+ int pcie30_phymode;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct reset_control *p30phy;
|
||||
+ struct phy *phy;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ int num_clks;
|
||||
+ int num_lanes;
|
||||
+ u32 lanes[4];
|
||||
+};
|
||||
+
|
||||
+struct rockchip_p3phy_ops {
|
||||
+ int (*phy_init)(struct rockchip_p3phy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Actually We don't care EP/RC mode, but just record it */
|
||||
+ switch (submode) {
|
||||
+ case PHY_MODE_PCIE_RC:
|
||||
+ priv->mode = PHY_MODE_PCIE_RC;
|
||||
+ break;
|
||||
+ case PHY_MODE_PCIE_EP:
|
||||
+ priv->mode = PHY_MODE_PCIE_EP;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(&phy->dev, "%s, invalid mode\n", __func__);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ struct phy *phy = priv->phy;
|
||||
+ bool bifurcation = false;
|
||||
+ int ret, i;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
|
||||
+
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ bifurcation = true;
|
||||
+ }
|
||||
+
|
||||
+ /* Set bifurcation if needed, and it doesn't care RC/EP */
|
||||
+ if (bifurcation) {
|
||||
+ dev_info(&phy->dev, "bifurcation enabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
|
||||
+ GRF_PCIE30PHY_DA_OCM);
|
||||
+ } else {
|
||||
+ dev_dbg(&phy->dev, "bifurcation disabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ GRF_PCIE30PHY_STATUS0,
|
||||
+ reg, SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ __func__, reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3568_init,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ u32 reg = 0;
|
||||
+ u8 mode = 0;
|
||||
+ int i, ret;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
|
||||
+
|
||||
+ /* Set bifurcation if needed */
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ if (!priv->lanes[i])
|
||||
+ mode |= (BIT(i) << 3);
|
||||
+
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ mode |= (BIT(i) >> 1);
|
||||
+ }
|
||||
+
|
||||
+ if (!mode)
|
||||
+ reg = RK3588_LANE_AGGREGATION;
|
||||
+ else {
|
||||
+ if (mode & (BIT(0) | BIT(1)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_0_1;
|
||||
+
|
||||
+ if (mode & (BIT(2) | BIT(3)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_2_3;
|
||||
+ }
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
|
||||
+
|
||||
+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
|
||||
+ if (!IS_ERR(priv->pipe_grf)) {
|
||||
+ reg = (mode & (BIT(6) | BIT(7))) >> 6;
|
||||
+ if (reg)
|
||||
+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
|
||||
+ (reg << 16) | reg);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ ret |= regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3588_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3588_init,
|
||||
+};
|
||||
+
|
||||
+static int rochchip_p3phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ udelay(1);
|
||||
+
|
||||
+ if (priv->ops->phy_init) {
|
||||
+ ret = priv->ops->phy_init(priv);
|
||||
+ if (ret)
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rochchip_p3phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_p3phy_ops = {
|
||||
+ .init = rochchip_p3phy_init,
|
||||
+ .exit = rochchip_p3phy_exit,
|
||||
+ .set_mode = rockchip_p3phy_set_mode,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_p3phy_priv *priv;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->mmio = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->ops = of_device_get_match_data(&pdev->dev);
|
||||
+ if (!priv->ops) {
|
||||
+ dev_err(dev, "no of match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
+ "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf))
|
||||
+ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
+
|
||||
+ priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
|
||||
+ priv->lanes, 2,
|
||||
+ ARRAY_SIZE(priv->lanes));
|
||||
+
|
||||
+ /* if no data-lanes assume aggregation */
|
||||
+ if (priv->num_lanes == -EINVAL) {
|
||||
+ dev_dbg(dev, "no data-lanes property found\n");
|
||||
+ priv->num_lanes = 1;
|
||||
+ priv->lanes[0] = 1;
|
||||
+ } else if (priv->num_lanes < 0) {
|
||||
+ dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
|
||||
+ return priv->num_lanes;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
|
||||
+ if (IS_ERR(priv->p30phy)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->p30phy),
|
||||
+ "failed to get phy reset control\n");
|
||||
+ }
|
||||
+ if (!priv->p30phy)
|
||||
+ dev_info(dev, "no phy reset control specified\n");
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_p3phy_of_match[] = {
|
||||
+ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
|
||||
+ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_p3phy_driver = {
|
||||
+ .probe = rockchip_p3phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-snps-pcie3-phy",
|
||||
+ .of_match_table = rockchip_p3phy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_p3phy_driver);
|
||||
+MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/include/linux/phy/pcie.h
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+#ifndef __PHY_PCIE_H
|
||||
+#define __PHY_PCIE_H
|
||||
+
|
||||
+#define PHY_MODE_PCIE_RC 20
|
||||
+#define PHY_MODE_PCIE_EP 21
|
||||
+#define PHY_MODE_PCIE_BIFURCATION 22
|
||||
+
|
||||
+#endif
|
|
@ -0,0 +1,146 @@
|
|||
From faedfa5b40f095d09040c3a040e2f8dee4a36b4b Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Thu, 25 Aug 2022 21:38:35 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rk3568
|
||||
|
||||
Add nodes to rk356x devicetree to support PCIe v3.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
|
||||
1 file changed, 122 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -42,6 +42,128 @@
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
|
||||
+ pcie30_phy_grf: syscon@fdcb8000 {
|
||||
+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30phy: phy@fe8c0000 {
|
||||
+ compatible = "rockchip,rk3568-pcie3-phy";
|
||||
+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
||||
+ #phy-cells = <0>;
|
||||
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
||||
+ <&cru PCLK_PCIE30PHY>;
|
||||
+ clock-names = "refclk_m", "refclk_n", "pclk";
|
||||
+ resets = <&cru SRST_PCIE30PHY>;
|
||||
+ reset-names = "phy";
|
||||
+ rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie3x1: pcie@fe270000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
||||
+ <0 0 0 2 &pcie3x1_intc 1>,
|
||||
+ <0 0 0 3 &pcie3x1_intc 2>,
|
||||
+ <0 0 0 4 &pcie3x1_intc 3>;
|
||||
+ linux,pci-domain = <1>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0400000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe270000 0x0 0x00010000>,
|
||||
+ <0x3 0x7f000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane1 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x1_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie3x2: pcie@fe280000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
+ <0 0 0 2 &pcie3x2_intc 1>,
|
||||
+ <0 0 0 3 &pcie3x2_intc 2>,
|
||||
+ <0 0 0 4 &pcie3x2_intc 3>;
|
||||
+ linux,pci-domain = <2>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ num-lanes = <2>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0800000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe280000 0x0 0x00010000>,
|
||||
+ <0x3 0xbf000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane0 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x2_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gmac0: ethernet@fe2a0000 {
|
||||
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
|
@ -1,31 +0,0 @@
|
|||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -13,6 +13,13 @@
|
||||
model = "FriendlyElec NanoPi R2S";
|
||||
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
|
@ -0,0 +1,22 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -96,6 +96,19 @@
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ pcie@0 {
|
||||
+ reg = <0x00000000 0 0 0 0>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ pcie-eth@0,0 {
|
||||
+ compatible = "pci10ec,8168";
|
||||
+ reg = <0x000000 0 0 0 0>;
|
||||
+
|
||||
+ realtek,led-data = <0x870>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pinctrl {
|
|
@ -0,0 +1,35 @@
|
|||
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Wed, 20 Feb 2019 07:38:34 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1358,6 +1358,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
host->ios.clock = 0;
|
||||
host->ios.vdd = 0;
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
From cfb1aa4c805e58287dd0ce292b5c64309e3dba2f Mon Sep 17 00:00:00 2001
|
||||
From: Furkan Kardame <f.kardame@manjaro.org>
|
||||
Date: Sun, 9 Oct 2022 22:24:05 +0300
|
||||
Subject: [PATCH] net: phy: add support for Motorcomm yt8531C phy
|
||||
|
||||
This patch adds support for Motorcomm YT8531C which is
|
||||
used in OrangePi 3 LTS, OrangePi 4 LTS and OrangePi 800
|
||||
Currently being used by Manjaro Arm kernel
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
|
||||
---
|
||||
drivers/net/phy/motorcomm.c | 90 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 90 insertions(+)
|
||||
|
||||
--- a/drivers/net/phy/motorcomm.c
|
||||
+++ b/drivers/net/phy/motorcomm.c
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/phy.h>
|
||||
|
||||
#define PHY_ID_YT8511 0x0000010a
|
||||
+#define PHY_ID_YT8531 0x4f51e91b
|
||||
|
||||
#define YT8511_PAGE_SELECT 0x1e
|
||||
#define YT8511_PAGE 0x1f
|
||||
@@ -38,6 +39,38 @@
|
||||
#define YT8511_DELAY_FE_TX_EN (0xf << 12)
|
||||
#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
|
||||
|
||||
+#define YT8531_RGMII_CONFIG1 0xa003
|
||||
+
|
||||
+/* TX Gig-E Delay is bits 3:0, default 0x1
|
||||
+ * TX Fast-E Delay is bits 7:4, default 0xf
|
||||
+ * RX Delay is bits 13:10, default 0x0
|
||||
+ * Delay = 150ps * N
|
||||
+ * On = 2000ps, off = 50ps
|
||||
+ */
|
||||
+#define YT8531_DELAY_GE_TX_EN (0xd << 0)
|
||||
+#define YT8531_DELAY_GE_TX_DIS (0x0 << 0)
|
||||
+#define YT8531_DELAY_FE_TX_EN (0xd << 4)
|
||||
+#define YT8531_DELAY_FE_TX_DIS (0x0 << 4)
|
||||
+#define YT8531_DELAY_RX_EN (0xd << 10)
|
||||
+#define YT8531_DELAY_RX_DIS (0x0 << 10)
|
||||
+#define YT8531_DELAY_MASK (GENMASK(13, 10) | GENMASK(7, 0))
|
||||
+
|
||||
+#define YT8531_SYNCE_CFG 0xa012
|
||||
+
|
||||
+/* Clk src config is bits 3:1
|
||||
+ * 3b000 src from pll
|
||||
+ * 3b001 src from rx_clk
|
||||
+ * 3b010 src from serdes
|
||||
+ * 3b011 src from ptp_in
|
||||
+ * 3b100 src from 25mhz refclk *default*
|
||||
+ * 3b101 src from 25mhz ssc
|
||||
+ * Clk rate select is bit 4
|
||||
+ * 1b0 25mhz clk output *default*
|
||||
+ * 1b1 125mhz clk output
|
||||
+ * Clkout enable is bit 6
|
||||
+ */
|
||||
+#define YT8531_CLKCFG_125M (BIT(6) | BIT(4) | (0x0 < 1))
|
||||
+
|
||||
static int yt8511_read_page(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_read(phydev, YT8511_PAGE_SELECT);
|
||||
@@ -111,6 +144,51 @@ err_restore_page:
|
||||
return phy_restore_page(phydev, oldpage, ret);
|
||||
}
|
||||
|
||||
+static int yt8531_config_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int oldpage, ret = 0;
|
||||
+ unsigned int val;
|
||||
+
|
||||
+ oldpage = phy_select_page(phydev, YT8531_RGMII_CONFIG1);
|
||||
+ if (oldpage < 0)
|
||||
+ goto err_restore_page;
|
||||
+
|
||||
+ /* set rgmii delay mode */
|
||||
+ switch (phydev->interface) {
|
||||
+ case PHY_INTERFACE_MODE_RGMII:
|
||||
+ val = YT8531_DELAY_RX_DIS | YT8531_DELAY_GE_TX_DIS | YT8531_DELAY_FE_TX_DIS;
|
||||
+ break;
|
||||
+ case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
+ val = YT8531_DELAY_RX_EN | YT8531_DELAY_GE_TX_DIS | YT8531_DELAY_FE_TX_DIS;
|
||||
+ break;
|
||||
+ case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
+ val = YT8531_DELAY_RX_DIS | YT8531_DELAY_GE_TX_EN | YT8531_DELAY_FE_TX_EN;
|
||||
+ break;
|
||||
+ case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
+ val = YT8531_DELAY_RX_EN | YT8531_DELAY_GE_TX_EN | YT8531_DELAY_FE_TX_EN;
|
||||
+ break;
|
||||
+ default: /* do not support other modes */
|
||||
+ ret = -EOPNOTSUPP;
|
||||
+ goto err_restore_page;
|
||||
+ }
|
||||
+
|
||||
+ ret = __phy_modify(phydev, YT8511_PAGE, YT8531_DELAY_MASK, val);
|
||||
+ if (ret < 0)
|
||||
+ goto err_restore_page;
|
||||
+
|
||||
+ /* set clock mode to 125mhz */
|
||||
+ ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8531_SYNCE_CFG);
|
||||
+ if (ret < 0)
|
||||
+ goto err_restore_page;
|
||||
+
|
||||
+ ret = __phy_write(phydev, YT8511_PAGE, YT8531_CLKCFG_125M);
|
||||
+ if (ret < 0)
|
||||
+ goto err_restore_page;
|
||||
+
|
||||
+err_restore_page:
|
||||
+ return phy_restore_page(phydev, oldpage, ret);
|
||||
+}
|
||||
+
|
||||
static struct phy_driver motorcomm_phy_drvs[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
|
||||
@@ -120,7 +198,16 @@ static struct phy_driver motorcomm_phy_d
|
||||
.resume = genphy_resume,
|
||||
.read_page = yt8511_read_page,
|
||||
.write_page = yt8511_write_page,
|
||||
+ }, {
|
||||
+ PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
|
||||
+ .name = "YT8531 Gigabit Ethernet",
|
||||
+ .config_init = yt8531_config_init,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ .read_page = yt8511_read_page,
|
||||
+ .write_page = yt8511_write_page,
|
||||
},
|
||||
+
|
||||
};
|
||||
|
||||
module_phy_driver(motorcomm_phy_drvs);
|
||||
@@ -131,6 +218,7 @@ MODULE_LICENSE("GPL");
|
||||
|
||||
static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
|
||||
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
|
||||
+ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
|
||||
{ /* sentinal */ }
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
|
||||
From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
|
||||
Date: Tue, 4 Aug 2020 20:17:53 +0800
|
||||
Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
|
||||
1 files changed, 4 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -173,6 +173,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -0,0 +1,39 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus";
|
||||
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "orangepi-r1-plus:green:lan";
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ max-freq = <48000000>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "orangepi-r1-plus:red:sys";
|
||||
+};
|
||||
+
|
||||
+&sys_led_pin {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "orangepi-r1-plus:green:wan";
|
||||
+};
|
|
@ -0,0 +1,79 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,66 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&dmc_opp_table {
|
||||
+ opp-798000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-840000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-924000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-1056000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-id4f51.e91b",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "orangepi-r1-plus-lts:green:lan";
|
||||
+};
|
||||
+
|
||||
+&rtl8153 {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ label = "orangepi-r1-plus-lts:red:sys";
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "orangepi-r1-plus-lts:green:wan";
|
||||
+};
|
|
@ -0,0 +1,64 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,51 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-id0000.011a",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "nanopi-r2c:green:lan";
|
||||
+};
|
||||
+
|
||||
+&rtl8153 {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ label = "nanopi-r2c:red:sys";
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "nanopi-r2c:green:wan";
|
||||
+};
|
|
@ -0,0 +1,442 @@
|
|||
From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001
|
||||
From: Julian Pidancet <julian@pidancet.net>
|
||||
Date: Sun, 23 Jan 2022 16:34:08 +0100
|
||||
Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
|
||||
|
||||
This patch adds support for FriendlyARM NanoPi NEO3
|
||||
|
||||
Soc: RockChip RK3328
|
||||
RAM: 1GB/2GB DDR4
|
||||
LAN: 10/100/1000M Ethernet with unique MAC
|
||||
USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header
|
||||
MicroSD: x 1 for system boot and storage
|
||||
LED: Power LED x 1, System LED x 1
|
||||
Key: User Button x 1
|
||||
Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan
|
||||
GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO
|
||||
Power: 5V/1A, via Type-C or GPIO
|
||||
|
||||
Signed-off-by: Julian Pidancet <julian@pidancet.net>
|
||||
---
|
||||
|
||||
This is another shot at previous work submitted by Marty Jones
|
||||
<mj8263788@gmail.com> (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/),
|
||||
which is now a year old.
|
||||
|
||||
v2: Following up on Robin Murphy's comments, the NEO3 DTS is now
|
||||
standalone and no longer includes the nanopi R2S one. The lan_led and
|
||||
wan_len nodes have been removed, and the sys_led node has been renamed
|
||||
to status_led in accordance with the board schematics.
|
||||
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 396 ++++++++++++++++++
|
||||
2 files changed, 397 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
@@ -0,0 +1,394 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi NEO3";
|
||||
+ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ reset {
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ debounce-interval = <50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ status_led: led-0 {
|
||||
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-neo3:green:status";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_sdio: sdmmcio-regulator {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&sdio_vcc_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_io_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-settling-time-us = <5000>;
|
||||
+ regulator-type = "voltage";
|
||||
+ startup-delay-us = <2000>;
|
||||
+ states = <1800000 0x1>,
|
||||
+ <3300000 0x0>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-name = "vcc_rtl8153";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io_33>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rx_delay = <0x18>;
|
||||
+ snps,aal;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vdd_5v>;
|
||||
+ vcc2-supply = <&vdd_5v>;
|
||||
+ vcc3-supply = <&vdd_5v>;
|
||||
+ vcc4-supply = <&vdd_5v>;
|
||||
+ vcc5-supply = <&vcc_io_33>;
|
||||
+ vcc6-supply = <&vdd_5v>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_33: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io_33";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io_33>;
|
||||
+ vccio1-supply = <&vcc_io_33>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io_sdio>;
|
||||
+ vccio4-supply = <&vcc_18>;
|
||||
+ vccio5-supply = <&vcc_io_33>;
|
||||
+ vccio6-supply = <&vcc_io_33>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ button {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,14 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -59,3 +59,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-pi-e25.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h68k.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
|
@ -0,0 +1,45 @@
|
|||
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||
From: wevsty <ty@wevs.org>
|
||||
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||
Subject: [PATCH] char: add support for rockchip hardware random number
|
||||
generator
|
||||
|
||||
This patch provides hardware random number generator support for all rockchip SOC.
|
||||
|
||||
rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c
|
||||
|
||||
Signed-off-by: wevsty <ty@wevs.org>
|
||||
---
|
||||
|
||||
--- a/drivers/char/hw_random/Kconfig
|
||||
+++ b/drivers/char/hw_random/Kconfig
|
||||
@@ -385,6 +385,19 @@ config HW_RANDOM_STM32
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
+config HW_RANDOM_ROCKCHIP
|
||||
+ tristate "Rockchip Random Number Generator support"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ default HW_RANDOM
|
||||
+ help
|
||||
+ This driver provides kernel-side support for the Random Number
|
||||
+ Generator hardware found on Rockchip cpus.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called rockchip-rng.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
config HW_RANDOM_PIC32
|
||||
tristate "Microchip PIC32 Random Number Generator support"
|
||||
depends on HW_RANDOM && MACH_PIC32
|
||||
--- a/drivers/char/hw_random/Makefile
|
||||
+++ b/drivers/char/hw_random/Makefile
|
||||
@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
|
||||
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
|
||||
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
|
|
@ -0,0 +1,69 @@
|
|||
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||
From: wevsty <ty@wevs.org>
|
||||
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator
|
||||
for RK3328 and RK3399
|
||||
|
||||
Adding Hardware Random Number Generator Resources to the RK3328 and RK3399.
|
||||
|
||||
Signed-off-by: wevsty <ty@wevs.org>
|
||||
---
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -279,6 +279,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng: rng@ff060000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff060000 0x0 0x4000>;
|
||||
+
|
||||
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
grf: syscon@ff100000 {
|
||||
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1937,6 +1937,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@ff8b8000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
|
||||
+ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
gpu: gpu@ff9a0000 {
|
||||
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -211,6 +211,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@fe388000 {
|
||||
+ compatible = "rockchip,cryptov2-rng";
|
||||
+ reg = <0x0 0xfe388000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||
+ clock-names = "clk_trng", "hclk_trng";
|
||||
+ resets = <&cru SRST_TRNG_NS>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy0: phy@fe820000 {
|
||||
compatible = "rockchip,rk3568-naneng-combphy";
|
||||
reg = <0x0 0xfe820000 0x0 0x100>;
|
|
@ -0,0 +1,44 @@
|
|||
From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 13:53:25 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/devfreq/Kconfig | 18 +-
|
||||
drivers/devfreq/Makefile | 1 +
|
||||
drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 862 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/devfreq/rk3328_dmc.c
|
||||
|
||||
--- a/drivers/devfreq/Kconfig
|
||||
+++ b/drivers/devfreq/Kconfig
|
||||
@@ -120,6 +120,18 @@ config ARM_TEGRA_DEVFREQ
|
||||
It reads ACTMON counters of memory controllers and adjusts the
|
||||
operating frequencies and voltages with OPP support.
|
||||
|
||||
+config ARM_RK3328_DMC_DEVFREQ
|
||||
+ tristate "ARM RK3328 DMC DEVFREQ Driver"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ select DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||
+ select PM_DEVFREQ_EVENT
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
|
||||
+ It sets the frequency for the memory controller and reads the usage counts
|
||||
+ from hardware.
|
||||
+
|
||||
config ARM_RK3399_DMC_DEVFREQ
|
||||
tristate "ARM RK3399 DMC DEVFREQ Driver"
|
||||
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
|
||||
--- a/drivers/devfreq/Makefile
|
||||
+++ b/drivers/devfreq/Makefile
|
||||
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += gov
|
||||
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
|
||||
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
|
||||
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
||||
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
|
||||
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
|
||||
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yun ping <typ@rock-chips.com>
|
||||
Date: Thu, 4 May 2017 20:49:58 +0800
|
||||
Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
|
||||
APIs
|
||||
|
||||
commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.
|
||||
|
||||
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++
|
||||
drivers/clk/rockchip/clk-rk3328.c | 7 +-
|
||||
drivers/clk/rockchip/clk.h | 3 +-
|
||||
include/soc/rockchip/rockchip_sip.h | 11 +++
|
||||
4 files changed, 147 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-ddr.c
|
||||
+++ b/drivers/clk/rockchip/clk-ddr.c
|
||||
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
|
||||
.get_parent = rockchip_ddrclk_get_parent,
|
||||
};
|
||||
|
||||
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
|
||||
+#define SCREEN_NULL 0
|
||||
+#define SCREEN_HDMI 6
|
||||
+
|
||||
+static inline int rk_drm_get_lcdc_type(void)
|
||||
+{
|
||||
+ return SCREEN_NULL;
|
||||
+}
|
||||
+
|
||||
+struct share_params {
|
||||
+ u32 hz;
|
||||
+ u32 lcdc_type;
|
||||
+ u32 vop;
|
||||
+ u32 vop_dclk_mode;
|
||||
+ u32 sr_idle_en;
|
||||
+ u32 addr_mcu_el3;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag1;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag0;
|
||||
+ u32 complt_hwirq;
|
||||
+ /* if need, add parameter after */
|
||||
+};
|
||||
+
|
||||
+struct rockchip_ddrclk_data {
|
||||
+ u32 inited_flag;
|
||||
+ void __iomem *share_memory;
|
||||
+};
|
||||
+
|
||||
+static struct rockchip_ddrclk_data ddr_data;
|
||||
+
|
||||
+static void rockchip_ddrclk_data_init(void)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
+ 1, SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if (!res.a0) {
|
||||
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
|
||||
+ ddr_data.inited_flag = 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long drate,
|
||||
+ unsigned long prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = drate;
|
||||
+ p->lcdc_type = rk_drm_get_lcdc_type();
|
||||
+ p->wait_flag1 = 1;
|
||||
+ p->wait_flag0 = 1;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if ((int)res.a1 == -6) {
|
||||
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
|
||||
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
|
||||
+ }
|
||||
+
|
||||
+ return res.a0;
|
||||
+}
|
||||
+
|
||||
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
|
||||
+ (struct clk_hw *hw, unsigned long parent_rate)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long rate,
|
||||
+ unsigned long *prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = rate;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
|
||||
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
|
||||
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
|
||||
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
|
||||
+ .get_parent = rockchip_ddrclk_get_parent,
|
||||
+};
|
||||
+
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
u8 num_parents, int mux_offset,
|
||||
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
|
||||
case ROCKCHIP_DDRCLK_SIP:
|
||||
init.ops = &rockchip_ddrclk_sip_ops;
|
||||
break;
|
||||
+ case ROCKCHIP_DDRCLK_SIP_V2:
|
||||
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
|
||||
+ break;
|
||||
default:
|
||||
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
|
||||
kfree(ddrclk);
|
||||
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||
@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||
+
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -399,7 +399,8 @@ struct clk *rockchip_clk_register_mmc(co
|
||||
* DDRCLK flags, including method of setting the rate
|
||||
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
||||
*/
|
||||
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
||||
+#define ROCKCHIP_DDRCLK_SIP 0x01
|
||||
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
|
||||
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
--- a/include/soc/rockchip/rockchip_sip.h
|
||||
+++ b/include/soc/rockchip/rockchip_sip.h
|
||||
@@ -16,5 +16,16 @@
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
+
|
||||
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
|
||||
+
|
||||
+/* Share mem page types */
|
||||
+typedef enum {
|
||||
+ SHARE_PAGE_TYPE_INVALID = 0,
|
||||
+ SHARE_PAGE_TYPE_UARTDBG,
|
||||
+ SHARE_PAGE_TYPE_DDR,
|
||||
+ SHARE_PAGE_TYPE_MAX,
|
||||
+} share_page_type_t;
|
||||
|
||||
#endif
|
|
@ -0,0 +1,662 @@
|
|||
From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 12:49:48 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
|
||||
1 file changed, 505 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -18,25 +18,66 @@
|
||||
#include <linux/list.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
-#include <soc/rockchip/rk3399_grf.h>
|
||||
-
|
||||
-#define RK3399_DMC_NUM_CH 2
|
||||
+#define PX30_PMUGRF_OS_REG2 0x208
|
||||
|
||||
+#define RK3128_GRF_SOC_CON0 0x140
|
||||
+#define RK3128_GRF_OS_REG1 0x1cc
|
||||
+#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
+#define RK3128_GRF_DFI_RDNUM 0x224
|
||||
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
|
||||
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
|
||||
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
|
||||
+
|
||||
+#define RK3288_PMU_SYS_REG2 0x9c
|
||||
+#define RK3288_GRF_SOC_CON4 0x254
|
||||
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
+#define RK3288_DFI_EN (0x30003 << 14)
|
||||
+#define RK3288_DFI_DIS (0x30000 << 14)
|
||||
+#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
+#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||
+
|
||||
+#define RK3328_GRF_OS_REG2 0x5d0
|
||||
+
|
||||
+#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
+#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
+#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
+#define RK3368_GRF_SOC_STATUS8 0x4a0
|
||||
+#define RK3368_GRF_SOC_STATUS9 0x4a4
|
||||
+#define RK3368_GRF_SOC_STATUS10 0x4a8
|
||||
+#define RK3368_DFI_EN (0x30003 << 5)
|
||||
+#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
+
|
||||
+#define MAX_DMC_NUM_CH 2
|
||||
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
/* DDRMON_CTRL */
|
||||
-#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
-#define LPDDR4_EN (0x10001 << 4)
|
||||
-#define HARDWARE_EN (0x10001 << 3)
|
||||
-#define LPDDR3_EN (0x10001 << 2)
|
||||
-#define SOFTWARE_EN (0x10001 << 1)
|
||||
-#define SOFTWARE_DIS (0x10000 << 1)
|
||||
-#define TIME_CNT_EN (0x10001 << 0)
|
||||
+#define DDRMON_CTRL 0x04
|
||||
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
+#define DDR4_EN (0x10001 << 5)
|
||||
+#define LPDDR4_EN (0x10001 << 4)
|
||||
+#define HARDWARE_EN (0x10001 << 3)
|
||||
+#define LPDDR2_3_EN (0x10001 << 2)
|
||||
+#define SOFTWARE_EN (0x10001 << 1)
|
||||
+#define SOFTWARE_DIS (0x10000 << 1)
|
||||
+#define TIME_CNT_EN (0x10001 << 0)
|
||||
|
||||
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
+/* pmu grf */
|
||||
+#define PMUGRF_OS_REG2 0x308
|
||||
+
|
||||
+enum {
|
||||
+ DDR4 = 0,
|
||||
+ DDR3 = 3,
|
||||
+ LPDDR2 = 5,
|
||||
+ LPDDR3 = 6,
|
||||
+ LPDDR4 = 7,
|
||||
+ UNUSED = 0xFF
|
||||
+};
|
||||
+
|
||||
struct dmc_usage {
|
||||
u32 access;
|
||||
u32 total;
|
||||
@@ -50,33 +91,261 @@ struct dmc_usage {
|
||||
struct rockchip_dfi {
|
||||
struct devfreq_event_dev *edev;
|
||||
struct devfreq_event_desc *desc;
|
||||
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
+ struct regmap *regmap_grf;
|
||||
+ struct regmap *regmap_pmugrf;
|
||||
struct clk *clk;
|
||||
+ u32 dram_type;
|
||||
+ /*
|
||||
+ * available mask, 1: available, 0: not available
|
||||
+ * each bit represent a channel
|
||||
+ */
|
||||
+ u32 ch_msk;
|
||||
+};
|
||||
+
|
||||
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_DISB);
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi_wr, dfi_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3128_dfi_ops = {
|
||||
+ .disable = rk3128_dfi_disable,
|
||||
+ .enable = rk3128_dfi_enable,
|
||||
+ .get_event = rk3128_dfi_get_event,
|
||||
+ .set_event = rk3128_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ u32 tmp, max = 0;
|
||||
+ u32 i, busier_ch = 0;
|
||||
+ u32 rd_count, wr_count, total_count;
|
||||
+
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ /* Find out which channel is busier */
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
|
||||
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
|
||||
+ info->ch_usage[i].total = total_count;
|
||||
+ tmp = info->ch_usage[i].access;
|
||||
+ if (tmp > max) {
|
||||
+ busier_ch = i;
|
||||
+ max = tmp;
|
||||
+ }
|
||||
+ }
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return busier_ch;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ int busier_ch;
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ edata->load_count = info->ch_usage[busier_ch].access;
|
||||
+ edata->total_count = info->ch_usage[busier_ch].total;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3288_dfi_ops = {
|
||||
+ .disable = rk3288_dfi_disable,
|
||||
+ .enable = rk3288_dfi_enable,
|
||||
+ .get_event = rk3288_dfi_get_event,
|
||||
+ .set_event = rk3288_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3368_dfi_ops = {
|
||||
+ .disable = rk3368_dfi_disable,
|
||||
+ .enable = rk3368_dfi_enable,
|
||||
+ .get_event = rk3368_dfi_get_event,
|
||||
+ .set_event = rk3368_dfi_set_event,
|
||||
};
|
||||
|
||||
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
- u32 val;
|
||||
- u32 ddr_type;
|
||||
-
|
||||
- /* get ddr type */
|
||||
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
|
||||
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
|
||||
- RK3399_PMUGRF_DDRTYPE_MASK;
|
||||
|
||||
/* clear DDRMON_CTRL setting */
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
|
||||
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
|
||||
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == DDR4)
|
||||
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
- tmp = info->ch_usage[i].access;
|
||||
+
|
||||
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||
+ tmp = readl_relaxed(dfi_regs +
|
||||
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
+ if (info->dram_type == LPDDR4)
|
||||
+ tmp *= 8;
|
||||
+ else
|
||||
+ tmp *= 4;
|
||||
+ info->ch_usage[i].access = tmp;
|
||||
+
|
||||
if (tmp > max) {
|
||||
busier_ch = i;
|
||||
max = tmp;
|
||||
@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
- clk_disable_unprepare(info->clk);
|
||||
+ if (info->clk)
|
||||
+ clk_disable_unprepare(info->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int ret;
|
||||
|
||||
- ret = clk_prepare_enable(info->clk);
|
||||
- if (ret) {
|
||||
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||
- return ret;
|
||||
+ if (info->clk) {
|
||||
+ ret = clk_prepare_enable(info->clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int busier_ch;
|
||||
+ unsigned long flags;
|
||||
|
||||
+ local_irq_save(flags);
|
||||
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
|
||||
edata->load_count = info->ch_usage[busier_ch].access;
|
||||
edata->total_count = info->ch_usage[busier_ch].total;
|
||||
@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
- { .compatible = "rockchip,rk3399-dfi" },
|
||||
- { },
|
||||
-};
|
||||
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+static __init int px30_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
|
||||
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmugrf))
|
||||
+ return PTR_ERR(data->regmap_pmugrf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
{
|
||||
- struct device *dev = &pdev->dev;
|
||||
- struct rockchip_dfi *data;
|
||||
- struct devfreq_event_desc *desc;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
|
||||
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
- if (!data)
|
||||
- return -ENOMEM;
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ desc->ops = &rk3128_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmu))
|
||||
+ return PTR_ERR(data->regmap_pmu);
|
||||
+ }
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ if (data->dram_type == DDR3)
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_DDR3_SEL);
|
||||
+ else
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_LPDDR_SEL);
|
||||
+
|
||||
+ desc->ops = &rk3288_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+
|
||||
+ if (!dev->parent || !dev->parent->of_node)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+
|
||||
+ desc->ops = &rk3368_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla
|
||||
if (IS_ERR(data->regmap_pmu))
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
- data->dev = dev;
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+
|
||||
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_dfi *data;
|
||||
+ struct devfreq_event_desc *desc;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ const struct of_device_id *match;
|
||||
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc);
|
||||
+
|
||||
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
+ if (!data)
|
||||
+ return -ENOMEM;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
- desc->ops = &rockchip_dfi_ops;
|
||||
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
||||
+ if (match) {
|
||||
+ init = match->data;
|
||||
+ if (init) {
|
||||
+ if (init(pdev, data, desc))
|
||||
+ return -EINVAL;
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
desc->driver_data = data;
|
||||
desc->name = np->name;
|
||||
data->desc = desc;
|
||||
+ data->dev = dev;
|
||||
|
||||
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
||||
if (IS_ERR(data->edev)) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to add devfreq-event device\n");
|
||||
+ dev_err(dev, "failed to add devfreq-event device\n");
|
||||
return PTR_ERR(data->edev);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
[adjusted commit title]
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++++++
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -1010,6 +1010,13 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ dfi: dfi@ff790000 {
|
||||
+ reg = <0x00 0xff790000 0x00 0x400>;
|
||||
+ compatible = "rockchip,rk3328-dfi";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@ff811000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
|
@ -0,0 +1,126 @@
|
|||
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||
Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
.../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
|
||||
.../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++-
|
||||
include/dt-bindings/clock/rockchip-ddr.h | 63 ++++
|
||||
include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++
|
||||
4 files changed, 617 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
|
||||
create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
|
||||
create mode 100644 include/dt-bindings/memory/rk3328-dram.h
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -7,6 +7,7 @@
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328-dram-default-timing.dtsi"
|
||||
#include "rk3328.dtsi"
|
||||
|
||||
/ {
|
||||
@@ -119,6 +120,72 @@
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
+
|
||||
+ dmc: dmc {
|
||||
+ compatible = "rockchip,rk3328-dmc";
|
||||
+ devfreq-events = <&dfi>;
|
||||
+ center-supply = <&vdd_log>;
|
||||
+ clocks = <&cru SCLK_DDRCLK>;
|
||||
+ clock-names = "dmc_clk";
|
||||
+ operating-points-v2 = <&dmc_opp_table>;
|
||||
+ ddr_timing = <&ddr_timing>;
|
||||
+ upthreshold = <40>;
|
||||
+ downdifferential = <20>;
|
||||
+ auto-min-freq = <786000>;
|
||||
+ auto-freq-en = <0>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ ddr_power_model: ddr_power_model {
|
||||
+ compatible = "ddr_power_model";
|
||||
+ dynamic-power-coefficient = <120>;
|
||||
+ static-power-coefficient = <200>;
|
||||
+ ts = <32000 4700 (-80) 2>;
|
||||
+ thermal-zone = "soc-thermal";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dmc_opp_table: dmc-opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ rockchip,leakage-voltage-sel = <
|
||||
+ 1 10 0
|
||||
+ 11 254 1
|
||||
+ >;
|
||||
+ nvmem-cells = <&logic_leakage>;
|
||||
+ nvmem-cell-names = "ddr_leakage";
|
||||
+
|
||||
+ opp-786000000 {
|
||||
+ opp-hz = /bits/ 64 <786000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-798000000 {
|
||||
+ opp-hz = /bits/ 64 <798000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-840000000 {
|
||||
+ opp-hz = /bits/ 64 <840000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-924000000 {
|
||||
+ opp-hz = /bits/ 64 <924000000>;
|
||||
+ opp-microvolt = <1100000>;
|
||||
+ opp-microvolt-L0 = <1100000>;
|
||||
+ opp-microvolt-L1 = <1075000>;
|
||||
+ };
|
||||
+ opp-1056000000 {
|
||||
+ opp-hz = /bits/ 64 <1056000000>;
|
||||
+ opp-microvolt = <1175000>;
|
||||
+ opp-microvolt-L0 = <1175000>;
|
||||
+ opp-microvolt-L1 = <1150000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@@ -137,6 +204,10 @@
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
+&dfi {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -206,6 +277,7 @@
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
+ regulator-init-microvolt = <1075000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
@@ -220,6 +292,7 @@
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
+ regulator-init-microvolt = <1225000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-ramp-delay = <12500>;
|
|
@ -0,0 +1,44 @@
|
|||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
Date: Fri, 1 Mar 2019 21:55:53 +0200
|
||||
Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for
|
||||
RK3328
|
||||
|
||||
This allows for greater max frequency on rk3328 boards,
|
||||
increasing performance.
|
||||
|
||||
It has been included in Armbian (a linux distibution for ARM boards)
|
||||
for a while now without any reported issues
|
||||
|
||||
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch
|
||||
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch
|
||||
|
||||
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++
|
||||
1 files changed, 15 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -140,6 +140,21 @@
|
||||
opp-microvolt = <1300000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
+ opp-1392000000 {
|
||||
+ opp-hz = /bits/ 64 <1392000000>;
|
||||
+ opp-microvolt = <1350000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1512000000 {
|
||||
+ opp-hz = /bits/ 64 <1512000000>;
|
||||
+ opp-microvolt = <1400000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <1450000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
analog_sound: analog-sound {
|
|
@ -0,0 +1,46 @@
|
|||
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
Date: Mon, 18 Oct 2021 12:47:30 +0800
|
||||
Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
|
||||
|
||||
It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
|
||||
and for better performance.
|
||||
|
||||
Co-development-by: gzelvis <gzelvis@gmail.com>
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||
@@ -33,6 +33,14 @@
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <1125000 1125000 1250000>;
|
||||
};
|
||||
+ opp06 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <1225000>;
|
||||
+ };
|
||||
+ opp07 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <1275000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table1 {
|
||||
@@ -72,6 +80,14 @@
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <1200000 1200000 1250000>;
|
||||
};
|
||||
+ opp08 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <1250000>;
|
||||
+ };
|
||||
+ opp09 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <1325000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table2 {
|
|
@ -0,0 +1,69 @@
|
|||
From 4f279f9fbca54464173240f7e73b145a136dfa1e Mon Sep 17 00:00:00 2001
|
||||
From: Robin Murphy <robin.murphy@arm.com>
|
||||
Date: Sun, 29 Dec 2019 20:16:17 +0000
|
||||
Subject: arm64: dts: rockchip: Add RK3328 idle state
|
||||
|
||||
Downstream RK3328 DTBs describe a CPU idle state matching that present
|
||||
on other SoCs like RK3399. This works with upstream Trusted Firmware-A
|
||||
too, so let's add it here.
|
||||
|
||||
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Link: https://lore.kernel.org/r/a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -41,6 +41,7 @@
|
||||
reg = <0x0 0x0>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SLEEP>;
|
||||
dynamic-power-coefficient = <120>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
@@ -53,6 +54,7 @@
|
||||
reg = <0x0 0x1>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SLEEP>;
|
||||
dynamic-power-coefficient = <120>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
@@ -65,6 +67,7 @@
|
||||
reg = <0x0 0x2>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SLEEP>;
|
||||
dynamic-power-coefficient = <120>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
@@ -77,12 +80,26 @@
|
||||
reg = <0x0 0x3>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
#cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SLEEP>;
|
||||
dynamic-power-coefficient = <120>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
+ idle-states {
|
||||
+ entry-method = "psci";
|
||||
+
|
||||
+ CPU_SLEEP: cpu-sleep {
|
||||
+ compatible = "arm,idle-state";
|
||||
+ local-timer-stop;
|
||||
+ arm,psci-suspend-param = <0x0010000>;
|
||||
+ entry-latency-us = <120>;
|
||||
+ exit-latency-us = <250>;
|
||||
+ min-residency-us = <900>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
|
@ -0,0 +1,53 @@
|
|||
From d27970b82a0f552f70e76fab154855b3192aac23 Mon Sep 17 00:00:00 2001
|
||||
From: Stefan Schaeckeler <schaecsn@gmx.net>
|
||||
Date: Wed, 11 Dec 2019 22:17:02 -0800
|
||||
Subject: thermal: rockchip: Enable hwmon
|
||||
|
||||
By default, of-based thermal drivers do not enable hwmon.
|
||||
Explicitly enable hwmon for both, the soc and gpu temperature
|
||||
sensor.
|
||||
|
||||
Signed-off-by: Stefan Schaeckeler <schaecsn@gmx.net>
|
||||
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20191212061702.BFE2D6E85603@corona.crabdance.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 12 +++++++++++-
|
||||
1 file changed, 11 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -58,6 +58,8 @@ enum adc_sort_mode {
|
||||
ADC_INCREMENT,
|
||||
};
|
||||
|
||||
+#include "thermal_hwmon.h"
|
||||
+
|
||||
/**
|
||||
* The max sensors is two in rockchip SoCs.
|
||||
* Two sensors: CPU and GPU sensor.
|
||||
@@ -1321,8 +1323,15 @@ static int rockchip_thermal_probe(struct
|
||||
|
||||
thermal->chip->control(thermal->regs, true);
|
||||
|
||||
- for (i = 0; i < thermal->chip->chn_num; i++)
|
||||
+ for (i = 0; i < thermal->chip->chn_num; i++) {
|
||||
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
|
||||
+ thermal->sensors[i].tzd->tzp->no_hwmon = false;
|
||||
+ error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
|
||||
+ if (error)
|
||||
+ dev_warn(&pdev->dev,
|
||||
+ "failed to register sensor %d with hwmon: %d\n",
|
||||
+ i, error);
|
||||
+ }
|
||||
|
||||
platform_set_drvdata(pdev, thermal);
|
||||
|
||||
@@ -1344,6 +1353,7 @@ static int rockchip_thermal_remove(struc
|
||||
for (i = 0; i < thermal->chip->chn_num; i++) {
|
||||
struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
|
||||
|
||||
+ thermal_remove_hwmon_sysfs(sensor->tzd);
|
||||
rockchip_thermal_toggle_sensor(sensor, false);
|
||||
}
|
||||
|
|
@ -31,11 +31,12 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
|
||||
@@ -25,6 +25,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
|
|
@ -1,4 +1,4 @@
|
|||
From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
|
||||
From 43f3999d1836117ab2e601aec9a9e6f292ce4958 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||
|
@ -8,12 +8,12 @@ stores the MAC address.
|
|||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
.../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -68,6 +68,15 @@
|
||||
@@ -68,6 +68,19 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -22,7 +22,11 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
|||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ read-only; /* This holds our MAC */
|
||||
+ size = <256>;
|
||||
+
|
||||
+ mac_address: mac-address@fa {
|
||||
+ reg = <0xfa 0x06>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
|
@ -0,0 +1,28 @@
|
|||
--- a/include/dt-bindings/clock/rk3368-cru.h
|
||||
+++ b/include/dt-bindings/clock/rk3368-cru.h
|
||||
@@ -157,6 +157,8 @@
|
||||
#define PCLK_VIP 367
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_EFUSE256 369
|
||||
+#define PCLK_DPHYRX 370
|
||||
+#define PCLK_DPHYTX0 371
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_SFC 448
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/soc/rockchip,vop2.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
+
|
||||
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+
|
||||
+#define RK3568_VOP2_EP_RGB 0
|
||||
+#define RK3568_VOP2_EP_HDMI 1
|
||||
+#define RK3568_VOP2_EP_EDP 2
|
||||
+#define RK3568_VOP2_EP_MIPI0 3
|
||||
+#define RK3568_VOP2_EP_LVDS0 4
|
||||
+#define RK3568_VOP2_EP_MIPI1 5
|
||||
+#define RK3568_VOP2_EP_LVDS1 6
|
||||
+
|
||||
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
|
|
@ -0,0 +1,39 @@
|
|||
From 016c0e8a7a6e7820fb54d8ff8a4a2928a3016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 10 Jul 2021 11:10:33 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3566 dtsi
|
||||
|
||||
Add the rk3566 dtsi which includes the soc specific changes for this
|
||||
chip.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210710151034.32857-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
@@ -0,0 +1,20 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "rockchip,rk3566";
|
||||
+};
|
||||
+
|
||||
+&power {
|
||||
+ power-domain@RK3568_PD_PIPE {
|
||||
+ reg = <RK3568_PD_PIPE>;
|
||||
+ clocks = <&cru PCLK_PIPE>;
|
||||
+ pm_qos = <&qos_pcie2x1>,
|
||||
+ <&qos_sata1>,
|
||||
+ <&qos_sata2>,
|
||||
+ <&qos_usb3_0>,
|
||||
+ <&qos_usb3_1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,73 @@
|
|||
From b8d41e5053cd823817344cc5e7a2bfda508effff Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Thu, 29 Jul 2021 11:39:12 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gmac0 node to rk3568
|
||||
|
||||
While both RK3566 and RK3568 feature the gmac1 node, the gmac0
|
||||
node is exclusive to the RK3568.
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 49 ++++++++++++++++++++++++
|
||||
1 file changed, 49 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -22,6 +22,55 @@
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
+
|
||||
+ gmac0: ethernet@fe2a0000 {
|
||||
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq", "eth_wake_irq";
|
||||
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
+ clock-names = "stmmaceth", "mac_clk_rx",
|
||||
+ "mac_clk_tx", "clk_mac_refout",
|
||||
+ "aclk_mac", "pclk_mac",
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
+ resets = <&cru SRST_A_GMAC0>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
+ snps,mixed-burst;
|
||||
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
+ snps,tso;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x0>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
+ snps,blen = <0 0 0 0 16 8 4>;
|
||||
+ snps,rd_osr_lmt = <8>;
|
||||
+ snps,wr_osr_lmt = <4>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_rx_setup: rx-queues-config {
|
||||
+ snps,rx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_tx_setup: tx-queues-config {
|
||||
+ snps,tx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
|
@ -0,0 +1,54 @@
|
|||
From 85a8bccfa945680dc561f06b65ea01341d2033fc Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 23 Jan 2022 14:35:10 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568
|
||||
|
||||
pclk_xpcs is not supported by mainline driver and breaks dtbs_check
|
||||
|
||||
following warnings occour, and many more
|
||||
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
|
||||
[[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
|
||||
[15, 389], [15, 185], [15, 172]] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
|
||||
['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
|
||||
'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
|
||||
after removing it, the clock and other warnings are gone.
|
||||
|
||||
pclk_xpcs on gmac is used to support QSGMII, but this requires a driver
|
||||
supporting it.
|
||||
Once xpcs support is introduced, the clock can be added to the
|
||||
documentation and both controllers.
|
||||
|
||||
Fixes: b8d41e5053cd ("arm64: dts: rockchip: add gmac0 node to rk3568")
|
||||
Co-developed-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220123133510.135651-1-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -32,13 +32,11 @@
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
- <&cru PCLK_XPCS>;
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref",
|
||||
- "pclk_xpcs";
|
||||
+ "clk_mac_speed", "ptp_ref";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
|
@ -0,0 +1,45 @@
|
|||
From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:47 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2
|
||||
|
||||
New Rockchip devices have the usb phy nodes as standalone devices.
|
||||
These nodes have register nodes with #address_cells = 2, but only use 32
|
||||
bit addresses.
|
||||
|
||||
Adjust the driver to check if the returned address is "0", and adjust
|
||||
the index in that case.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++-
|
||||
1 file changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1098,12 +1098,21 @@ static int rockchip_usb2phy_probe(struct
|
||||
rphy->usbgrf = NULL;
|
||||
}
|
||||
|
||||
- if (of_property_read_u32(np, "reg", ®)) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 0, ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ /* support address_cells=2 */
|
||||
+ if (reg == 0) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 1, ®)) {
|
||||
+ dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
+ np);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
|
@ -0,0 +1,44 @@
|
|||
From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:48 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes
|
||||
|
||||
New Rockchip devices have the usb2 phy devices as standalone nodes
|
||||
instead of children of the grf node.
|
||||
Allow the driver to find the grf node from a phandle.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++-----
|
||||
1 file changed, 12 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1081,12 +1081,19 @@ static int rockchip_usb2phy_probe(struct
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- if (!dev->parent || !dev->parent->of_node)
|
||||
- return -EINVAL;
|
||||
+ if (!dev->parent || !dev->parent->of_node) {
|
||||
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
|
||||
+ if (IS_ERR(rphy->grf)) {
|
||||
+ dev_err(dev, "failed to locate usbgrf\n");
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
- if (IS_ERR(rphy->grf))
|
||||
- return PTR_ERR(rphy->grf);
|
||||
+ else {
|
||||
+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(rphy->grf))
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
|
||||
if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
|
||||
rphy->usbgrf =
|
|
@ -0,0 +1,237 @@
|
|||
From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:49 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts
|
||||
|
||||
The rk3568 usb2phy has a single muxed interrupt that handles all
|
||||
interrupts.
|
||||
Allow the driver to plug in only a single interrupt as necessary.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++-----
|
||||
1 file changed, 119 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
|
||||
* @dcd_retries: The retry count used to track Data contact
|
||||
* detection process.
|
||||
* @edev: extcon device for notification registration
|
||||
+ * @irq: muxed interrupt for single irq configuration
|
||||
* @phy_cfg: phy register configuration, assigned by driver data.
|
||||
* @ports: phy port instance.
|
||||
*/
|
||||
@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
|
||||
enum power_supply_type chg_type;
|
||||
u8 dcd_retries;
|
||||
struct extcon_dev *edev;
|
||||
+ int irq;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfg;
|
||||
struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
|
||||
};
|
||||
@@ -934,6 +936,102 @@ static irqreturn_t rockchip_usb2phy_otg_
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy *rphy = data;
|
||||
+ struct rockchip_usb2phy_port *rport;
|
||||
+ irqreturn_t ret = IRQ_NONE;
|
||||
+ unsigned int index;
|
||||
+
|
||||
+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
|
||||
+ rport = &rphy->ports[index];
|
||||
+ if (!rport->phy)
|
||||
+ continue;
|
||||
+
|
||||
+ /* Handle linestate irq for both otg port and host port */
|
||||
+ ret = rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
|
||||
+ struct rockchip_usb2phy_port *rport,
|
||||
+ struct device_node *child_np)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * If the usb2 phy used combined irq for otg and host port,
|
||||
+ * don't need to init otg and host port irq separately.
|
||||
+ */
|
||||
+ if (rphy->irq > 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ switch (rport->port_id) {
|
||||
+ case USB2PHY_PORT_HOST:
|
||||
+ rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
+ if (rport->ls_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
+ return rport->ls_irq;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
+ rockchip_usb2phy_linestate_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy", rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ break;
|
||||
+ case USB2PHY_PORT_OTG:
|
||||
+ /*
|
||||
+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
+ * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
+ * if not found, then look for the regular interrupts one by one.
|
||||
+ */
|
||||
+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
+ if (rport->otg_mux_irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_otg_mux_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_otg",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-mux irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ } else {
|
||||
+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
+ if (rport->bvalid_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
+ ret = rport->bvalid_irq;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_bvalid_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_bvalid",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-bvalid irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
@@ -947,18 +1045,9 @@ static int rockchip_usb2phy_host_port_in
|
||||
mutex_init(&rport->mutex);
|
||||
INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
|
||||
|
||||
- rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
- if (rport->ls_irq < 0) {
|
||||
- dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
- return rport->ls_irq;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
- rockchip_usb2phy_linestate_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy", rport);
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
if (ret) {
|
||||
- dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ dev_err(rphy->dev, "failed to setup host irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1007,44 +1096,10 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
|
||||
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
|
||||
|
||||
- /*
|
||||
- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
- * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
- * if not found, then look for the regular interrupts one by one.
|
||||
- */
|
||||
- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
- if (rport->otg_mux_irq > 0) {
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_otg_mux_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_otg",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-mux irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- } else {
|
||||
- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
- if (rport->bvalid_irq < 0) {
|
||||
- dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
- ret = rport->bvalid_irq;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_bvalid_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_bvalid",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-bvalid irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
+ goto out;
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1124,6 +1179,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
+ rphy->irq = platform_get_irq_optional(pdev, 0);
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
@@ -1203,6 +1259,20 @@ next_child:
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+
|
||||
+ if (rphy->irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
|
||||
+ rockchip_usb2phy_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy",
|
||||
+ rphy);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request usb2phy irq handle\n");
|
||||
+ goto put_child;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
|
@ -0,0 +1,104 @@
|
|||
From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:50 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support
|
||||
|
||||
The rk3568 usb2phy is a standalone device with a single muxed interrupt.
|
||||
Add support for the registers to the usb2phy driver.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++
|
||||
1 file changed, 65 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1100,6 +1100,7 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1511,6 +1512,69 @@ static const struct rockchip_usb2phy_cfg
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
|
||||
+ {
|
||||
+ .reg = 0xfe8a0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
|
||||
+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ /* Select suspend control from controller */
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .opmode = { 0x0000, 3, 0, 5, 1 },
|
||||
+ .cp_det = { 0x00c0, 24, 24, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 23, 23, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 25, 25, 0, 1 },
|
||||
+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
|
||||
+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 9, 9, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
|
||||
+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0xfe8b0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x100,
|
||||
@@ -1560,6 +1624,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
|
||||
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,633 @@
|
|||
From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001
|
||||
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Date: Tue, 8 Feb 2022 17:13:25 +0800
|
||||
Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
|
||||
|
||||
This patch implements a combo phy driver for Rockchip SoCs
|
||||
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
|
||||
sata-phy or sgmii-phy.
|
||||
|
||||
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 8 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++
|
||||
3 files changed, 590 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
|
||||
Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
|
||||
Innosilicon IP block.
|
||||
|
||||
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
|
||||
+ tristate "Rockchip NANENG COMBO PHY Driver"
|
||||
+ depends on ARCH_ROCKCHIP && OF
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
|
||||
+ combo PHY with NaNeng IP block.
|
||||
+
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -0,0 +1,581 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/phy/phy.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/units.h>
|
||||
+
|
||||
+#define BIT_WRITEABLE_SHIFT 16
|
||||
+#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
|
||||
+
|
||||
+/* COMBO PHY REG */
|
||||
+#define PHYREG6 0x14
|
||||
+#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
|
||||
+#define PHYREG6_PLL_DIV_SHIFT 6
|
||||
+#define PHYREG6_PLL_DIV_2 1
|
||||
+
|
||||
+#define PHYREG7 0x18
|
||||
+#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
|
||||
+#define PHYREG7_TX_RTERM_SHIFT 4
|
||||
+#define PHYREG7_TX_RTERM_50OHM 8
|
||||
+#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
|
||||
+#define PHYREG7_RX_RTERM_SHIFT 0
|
||||
+#define PHYREG7_RX_RTERM_44OHM 15
|
||||
+
|
||||
+#define PHYREG8 0x1C
|
||||
+#define PHYREG8_SSC_EN BIT(4)
|
||||
+
|
||||
+#define PHYREG11 0x28
|
||||
+#define PHYREG11_SU_TRIM_0_7 0xF0
|
||||
+
|
||||
+#define PHYREG12 0x2C
|
||||
+#define PHYREG12_PLL_LPF_ADJ_VALUE 4
|
||||
+
|
||||
+#define PHYREG13 0x30
|
||||
+#define PHYREG13_RESISTER_MASK GENMASK(5, 4)
|
||||
+#define PHYREG13_RESISTER_SHIFT 0x4
|
||||
+#define PHYREG13_RESISTER_HIGH_Z 3
|
||||
+#define PHYREG13_CKRCV_AMP0 BIT(7)
|
||||
+
|
||||
+#define PHYREG14 0x34
|
||||
+#define PHYREG14_CKRCV_AMP1 BIT(0)
|
||||
+
|
||||
+#define PHYREG15 0x38
|
||||
+#define PHYREG15_CTLE_EN BIT(0)
|
||||
+#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
|
||||
+#define PHYREG15_SSC_CNT_SHIFT 6
|
||||
+#define PHYREG15_SSC_CNT_VALUE 1
|
||||
+
|
||||
+#define PHYREG16 0x3C
|
||||
+#define PHYREG16_SSC_CNT_VALUE 0x5f
|
||||
+
|
||||
+#define PHYREG18 0x44
|
||||
+#define PHYREG18_PLL_LOOP 0x32
|
||||
+
|
||||
+#define PHYREG32 0x7C
|
||||
+#define PHYREG32_SSC_MASK GENMASK(7, 4)
|
||||
+#define PHYREG32_SSC_DIR_SHIFT 4
|
||||
+#define PHYREG32_SSC_UPWARD 0
|
||||
+#define PHYREG32_SSC_DOWNWARD 1
|
||||
+#define PHYREG32_SSC_OFFSET_SHIFT 6
|
||||
+#define PHYREG32_SSC_OFFSET_500PPM 1
|
||||
+
|
||||
+#define PHYREG33 0x80
|
||||
+#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
|
||||
+#define PHYREG33_PLL_KVCO_SHIFT 2
|
||||
+#define PHYREG33_PLL_KVCO_VALUE 2
|
||||
+
|
||||
+struct rockchip_combphy_priv;
|
||||
+
|
||||
+struct combphy_reg {
|
||||
+ u16 offset;
|
||||
+ u16 bitend;
|
||||
+ u16 bitstart;
|
||||
+ u16 disable;
|
||||
+ u16 enable;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_grfcfg {
|
||||
+ struct combphy_reg pcie_mode_set;
|
||||
+ struct combphy_reg usb_mode_set;
|
||||
+ struct combphy_reg sgmii_mode_set;
|
||||
+ struct combphy_reg qsgmii_mode_set;
|
||||
+ struct combphy_reg pipe_rxterm_set;
|
||||
+ struct combphy_reg pipe_txelec_set;
|
||||
+ struct combphy_reg pipe_txcomp_set;
|
||||
+ struct combphy_reg pipe_clk_25m;
|
||||
+ struct combphy_reg pipe_clk_100m;
|
||||
+ struct combphy_reg pipe_phymode_sel;
|
||||
+ struct combphy_reg pipe_rate_sel;
|
||||
+ struct combphy_reg pipe_rxterm_sel;
|
||||
+ struct combphy_reg pipe_txelec_sel;
|
||||
+ struct combphy_reg pipe_txcomp_sel;
|
||||
+ struct combphy_reg pipe_clk_ext;
|
||||
+ struct combphy_reg pipe_sel_usb;
|
||||
+ struct combphy_reg pipe_sel_qsgmii;
|
||||
+ struct combphy_reg pipe_phy_status;
|
||||
+ struct combphy_reg con0_for_pcie;
|
||||
+ struct combphy_reg con1_for_pcie;
|
||||
+ struct combphy_reg con2_for_pcie;
|
||||
+ struct combphy_reg con3_for_pcie;
|
||||
+ struct combphy_reg con0_for_sata;
|
||||
+ struct combphy_reg con1_for_sata;
|
||||
+ struct combphy_reg con2_for_sata;
|
||||
+ struct combphy_reg con3_for_sata;
|
||||
+ struct combphy_reg pipe_con0_for_sata;
|
||||
+ struct combphy_reg pipe_xpcs_phy_ready;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_cfg {
|
||||
+ const struct rockchip_combphy_grfcfg *grfcfg;
|
||||
+ int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_priv {
|
||||
+ u8 type;
|
||||
+ void __iomem *mmio;
|
||||
+ int num_clks;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ struct device *dev;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct phy *phy;
|
||||
+ struct reset_control *phy_rst;
|
||||
+ const struct rockchip_combphy_cfg *cfg;
|
||||
+ bool enable_ssc;
|
||||
+ bool ext_refclk;
|
||||
+ struct clk *refclk;
|
||||
+};
|
||||
+
|
||||
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
|
||||
+ int mask, int val, int reg)
|
||||
+{
|
||||
+ unsigned int temp;
|
||||
+
|
||||
+ temp = readl(priv->mmio + reg);
|
||||
+ temp = (temp & ~(mask)) | val;
|
||||
+ writel(temp, priv->mmio + reg);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_param_write(struct regmap *base,
|
||||
+ const struct combphy_reg *reg, bool en)
|
||||
+{
|
||||
+ u32 val, mask, tmp;
|
||||
+
|
||||
+ tmp = en ? reg->enable : reg->disable;
|
||||
+ mask = GENMASK(reg->bitend, reg->bitstart);
|
||||
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
|
||||
+
|
||||
+ return regmap_write(base, reg->offset, val);
|
||||
+}
|
||||
+
|
||||
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 mask, val;
|
||||
+
|
||||
+ mask = GENMASK(cfg->pipe_phy_status.bitend,
|
||||
+ cfg->pipe_phy_status.bitstart);
|
||||
+
|
||||
+ regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
|
||||
+ val = (val & mask) >> cfg->pipe_phy_status.bitstart;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 val;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to enable clks\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ if (priv->cfg->combphy_cfg)
|
||||
+ ret = priv->cfg->combphy_cfg(priv);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ ret = -EINVAL;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
|
||||
+ goto err_clk;
|
||||
+ }
|
||||
+
|
||||
+ ret = reset_control_deassert(priv->phy_rst);
|
||||
+ if (ret)
|
||||
+ goto err_clk;
|
||||
+
|
||||
+ if (priv->type == PHY_TYPE_USB3) {
|
||||
+ ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
|
||||
+ priv, val,
|
||||
+ val == cfg->pipe_phy_status.enable,
|
||||
+ 10, 1000);
|
||||
+ if (ret)
|
||||
+ dev_warn(priv->dev, "wait phy status ready timeout\n");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_clk:
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->phy_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_combphy_ops = {
|
||||
+ .init = rockchip_combphy_init,
|
||||
+ .exit = rockchip_combphy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
|
||||
+
|
||||
+ if (args->args_count != 1) {
|
||||
+ dev_err(dev, "invalid number of arguments\n");
|
||||
+ return ERR_PTR(-EINVAL);
|
||||
+ }
|
||||
+
|
||||
+ if (priv->type != PHY_NONE && priv->type != args->args[0])
|
||||
+ dev_warn(dev, "phy type select %d overwriting type %d\n",
|
||||
+ args->args[0], priv->type);
|
||||
+
|
||||
+ priv->type = args->args[0];
|
||||
+
|
||||
+ return priv->phy;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ priv->refclk = NULL;
|
||||
+ for (i = 0; i < priv->num_clks; i++) {
|
||||
+ if (!strncmp(priv->clks[i].id, "ref", 3)) {
|
||||
+ priv->refclk = priv->clks[i].clk;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!priv->refclk) {
|
||||
+ dev_err(dev, "no refclk found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
|
||||
+ return PTR_ERR(priv->pipe_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
|
||||
+
|
||||
+ priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
|
||||
+
|
||||
+ priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
|
||||
+ if (IS_ERR(priv->phy_rst))
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_combphy_priv *priv;
|
||||
+ const struct rockchip_combphy_cfg *phy_cfg;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ phy_cfg = of_device_get_match_data(dev);
|
||||
+ if (!phy_cfg) {
|
||||
+ dev_err(dev, "no OF match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->dev = dev;
|
||||
+ priv->type = PHY_NONE;
|
||||
+ priv->cfg = phy_cfg;
|
||||
+
|
||||
+ ret = rockchip_combphy_parse_dt(dev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = reset_control_assert(priv->phy_rst);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to reset phy\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ unsigned long rate;
|
||||
+ u32 val;
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ /* Enable adaptive CTLE for USB3.0 Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+
|
||||
+ /* Set PLL KVCO fine tuning signals. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
|
||||
+ PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ /* Set PLL input clock divider 1/2. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
|
||||
+ PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ /* Enable adaptive CTLE for SATA Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+ /*
|
||||
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
+ */
|
||||
+ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
+ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
+ writel(val, priv->mmio + PHYREG7);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rate = clk_get_rate(priv->refclk);
|
||||
+
|
||||
+ switch (rate) {
|
||||
+ case REF_CLOCK_24MHz:
|
||||
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
+ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
+ val, PHYREG15);
|
||||
+
|
||||
+ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_25MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_100MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE) {
|
||||
+ /* PLL KVCO fine tuning. */
|
||||
+ val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ val, PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ val, PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+ } else if (priv->type == PHY_TYPE_SATA) {
|
||||
+ /* downward spread spectrum +500ppm */
|
||||
+ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
+ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "unsupported rate: %lu\n", rate);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (priv->ext_refclk) {
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
+ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
+ val |= PHYREG13_CKRCV_AMP0;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
+
|
||||
+ val = readl(priv->mmio + PHYREG14);
|
||||
+ val |= PHYREG14_CKRCV_AMP1;
|
||||
+ writel(val, priv->mmio + PHYREG14);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (priv->enable_ssc) {
|
||||
+ val = readl(priv->mmio + PHYREG8);
|
||||
+ val |= PHYREG8_SSC_EN;
|
||||
+ writel(val, priv->mmio + PHYREG8);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
|
||||
+ /* pipe-phy-grf */
|
||||
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
||||
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
||||
+ .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
|
||||
+ .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
|
||||
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
||||
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
|
||||
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
|
||||
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
||||
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
|
||||
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
|
||||
+ /* pipe-grf */
|
||||
+ .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
|
||||
+ .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
||||
+ .grfcfg = &rk3568_combphy_grfcfgs,
|
||||
+ .combphy_cfg = rk3568_combphy_cfg,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rockchip_combphy_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3568-naneng-combphy",
|
||||
+ .data = &rk3568_combphy_cfgs,
|
||||
+ },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_combphy_driver = {
|
||||
+ .probe = rockchip_combphy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-naneng-combphy",
|
||||
+ .of_match_table = rockchip_combphy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_combphy_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
|
@ -0,0 +1,54 @@
|
|||
From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:34 -0500
|
||||
Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers
|
||||
|
||||
Host drivers may not be able to support frequencies as low as dw-mmc
|
||||
supports. Unfortunately f_min isn't available when the drv_data->init
|
||||
function is called, as the mmc_host struct hasn't been set up yet.
|
||||
|
||||
Support the host drivers saving the requested minimum frequency, so we
|
||||
can later set f_min when it is available.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc.c | 7 ++++++-
|
||||
drivers/mmc/host/dw_mmc.h | 2 ++
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.c
|
||||
+++ b/drivers/mmc/host/dw_mmc.c
|
||||
@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct
|
||||
if (host->pdata->caps2)
|
||||
mmc->caps2 = host->pdata->caps2;
|
||||
|
||||
- mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+ /* if host has set a minimum_freq, we should respect it */
|
||||
+ if (host->minimum_speed)
|
||||
+ mmc->f_min = host->minimum_speed;
|
||||
+ else
|
||||
+ mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+
|
||||
if (!mmc->f_max)
|
||||
mmc->f_max = DW_MCI_FREQ_MAX;
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.h
|
||||
+++ b/drivers/mmc/host/dw_mmc.h
|
||||
@@ -99,6 +99,7 @@ struct dw_mci_dma_slave {
|
||||
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
||||
* rate and timeout calculations.
|
||||
* @current_speed: Configured rate of the controller.
|
||||
+ * @minimum_speed: Stored minimum rate of the controller.
|
||||
* @fifoth_val: The value of FIFOTH register.
|
||||
* @verid: Denote Version ID.
|
||||
* @dev: Device associated with the MMC controller.
|
||||
@@ -200,6 +201,7 @@ struct dw_mci {
|
||||
|
||||
u32 bus_hz;
|
||||
u32 current_speed;
|
||||
+ u32 minimum_speed;
|
||||
u32 fifoth_val;
|
||||
u16 verid;
|
||||
struct device *dev;
|
|
@ -0,0 +1,79 @@
|
|||
From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:35 -0500
|
||||
Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
|
||||
|
||||
The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
|
||||
hardware supports. This leads to a situation during card initialization
|
||||
where the clock is set lower than the clock driver can support. The
|
||||
dw-mmc-rockchip driver spews errors when this happens.
|
||||
For normal operation this only happens a few times during boot, but when
|
||||
cd-broken is enabled (in cases such as the SoQuartz module) this fires
|
||||
multiple times each poll cycle.
|
||||
|
||||
Fix this by testing the lowest possible frequency that the clock driver
|
||||
can support which is within the mmc specification. Divide that rate by
|
||||
the internal divider and set f_min to this.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
|
||||
1 file changed, 23 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
@@ -15,7 +15,9 @@
|
||||
#include "dw_mmc.h"
|
||||
#include "dw_mmc-pltfm.h"
|
||||
|
||||
-#define RK3288_CLKGEN_DIV 2
|
||||
+#define RK3288_CLKGEN_DIV 2
|
||||
+
|
||||
+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
|
||||
|
||||
struct dw_mci_rockchip_priv_data {
|
||||
struct clk *drv_clk;
|
||||
@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct
|
||||
|
||||
ret = clk_set_rate(host->ciu_clk, cclkin);
|
||||
if (ret)
|
||||
- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
|
||||
+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
|
||||
|
||||
bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
|
||||
if (bus_hz != host->bus_hz) {
|
||||
@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct
|
||||
|
||||
static int dw_mci_rockchip_init(struct dw_mci *host)
|
||||
{
|
||||
+ int ret, i;
|
||||
+
|
||||
/* It is slot 8 on Rockchip SoCs */
|
||||
host->sdio_id0 = 8;
|
||||
|
||||
- if (of_device_is_compatible(host->dev->of_node,
|
||||
- "rockchip,rk3288-dw-mshc"))
|
||||
+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
|
||||
host->bus_hz /= RK3288_CLKGEN_DIV;
|
||||
|
||||
+ /* clock driver will fail if the clock is less than the lowest source clock
|
||||
+ * divided by the internal clock divider. Test for the lowest available
|
||||
+ * clock and set the minimum freq to clock / clock divider.
|
||||
+ */
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(freqs); i++) {
|
||||
+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
|
||||
+ if (ret > 0) {
|
||||
+ host->minimum_speed = ret / RK3288_CLKGEN_DIV;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ if (ret < 0)
|
||||
+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 8 Apr 2022 11:12:34 -0400
|
||||
Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566
|
||||
|
||||
The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
|
||||
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
|
||||
we need to set the clock source to the usb2 phy instead.
|
||||
|
||||
Add handling to the grf driver to handle this on boot.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/drivers/soc/rockchip/grf.c
|
||||
+++ b/drivers/soc/rockchip/grf.c
|
||||
@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk
|
||||
.num_values = ARRAY_SIZE(rk3399_defaults),
|
||||
};
|
||||
|
||||
+#define RK3566_GRF_USB3OTG0_CON1 0x0104
|
||||
+
|
||||
+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
|
||||
+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
|
||||
+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
|
||||
+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
|
||||
+ .values = rk3566_defaults,
|
||||
+ .num_values = ARRAY_SIZE(rk3566_defaults),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
|
||||
{
|
||||
.compatible = "rockchip,rk3036-grf",
|
||||
@@ -130,6 +144,9 @@ static const struct of_device_id rockchi
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-grf",
|
||||
.data = (void *)&rk3399_grf,
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk3566-pipe-grf",
|
||||
+ .data = (void *)&rk3566_pipegrf,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
|
@ -0,0 +1,394 @@
|
|||
From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001
|
||||
From: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Date: Thu, 25 Aug 2022 21:38:34 +0200
|
||||
Subject: [PATCH] phy: rockchip: Support PCIe v3
|
||||
|
||||
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
|
||||
It use a dedicated PCIe-phy. Add support for this.
|
||||
|
||||
Initial support by Shawn Lin, modifications by Peter Geis and Frank
|
||||
Wunderlich.
|
||||
|
||||
Add data-lanes property for splitting pcie-lanes across controllers.
|
||||
|
||||
The data-lanes is an array where x=0 means lane is disabled and x > 0
|
||||
means controller x is assigned to phy lane.
|
||||
|
||||
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Suggested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 9 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++
|
||||
include/linux/phy/pcie.h | 12 +
|
||||
4 files changed, 341 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
create mode 100644 include/linux/phy/pcie.h
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
|
||||
help
|
||||
Enable this to support the Rockchip PCIe PHY.
|
||||
|
||||
+config PHY_ROCKCHIP_SNPS_PCIE3
|
||||
+ tristate "Rockchip Snps PCIe3 PHY Driver"
|
||||
+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
+ depends on HAS_IOMEM
|
||||
+ select GENERIC_PHY
|
||||
+ select MFD_SYSCON
|
||||
+ help
|
||||
+ Enable this to support the Rockchip snps PCIe3 PHY.
|
||||
+
|
||||
config PHY_ROCKCHIP_TYPEC
|
||||
tristate "Rockchip TYPEC PHY Driver"
|
||||
depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) +=
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -0,0 +1,319 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PCIE3.0 phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/iopoll.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/pcie.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+
|
||||
+/* Register for RK3568 */
|
||||
+#define GRF_PCIE30PHY_CON1 0x4
|
||||
+#define GRF_PCIE30PHY_CON6 0x18
|
||||
+#define GRF_PCIE30PHY_CON9 0x24
|
||||
+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
+#define GRF_PCIE30PHY_STATUS0 0x80
|
||||
+#define GRF_PCIE30PHY_WR_EN (0xf << 16)
|
||||
+#define SRAM_INIT_DONE(reg) (reg & BIT(14))
|
||||
+
|
||||
+#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+
|
||||
+/* Register for RK3588 */
|
||||
+#define PHP_GRF_PCIESEL_CON 0x100
|
||||
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
+
|
||||
+#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
+#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
+
|
||||
+struct rockchip_p3phy_ops;
|
||||
+
|
||||
+struct rockchip_p3phy_priv {
|
||||
+ const struct rockchip_p3phy_ops *ops;
|
||||
+ void __iomem *mmio;
|
||||
+ /* mode: RC, EP */
|
||||
+ int mode;
|
||||
+ /* pcie30_phymode: Aggregation, Bifurcation */
|
||||
+ int pcie30_phymode;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct reset_control *p30phy;
|
||||
+ struct phy *phy;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ int num_clks;
|
||||
+ int num_lanes;
|
||||
+ u32 lanes[4];
|
||||
+};
|
||||
+
|
||||
+struct rockchip_p3phy_ops {
|
||||
+ int (*phy_init)(struct rockchip_p3phy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Actually We don't care EP/RC mode, but just record it */
|
||||
+ switch (submode) {
|
||||
+ case PHY_MODE_PCIE_RC:
|
||||
+ priv->mode = PHY_MODE_PCIE_RC;
|
||||
+ break;
|
||||
+ case PHY_MODE_PCIE_EP:
|
||||
+ priv->mode = PHY_MODE_PCIE_EP;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(&phy->dev, "%s, invalid mode\n", __func__);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ struct phy *phy = priv->phy;
|
||||
+ bool bifurcation = false;
|
||||
+ int ret, i;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
|
||||
+
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ bifurcation = true;
|
||||
+ }
|
||||
+
|
||||
+ /* Set bifurcation if needed, and it doesn't care RC/EP */
|
||||
+ if (bifurcation) {
|
||||
+ dev_info(&phy->dev, "bifurcation enabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
|
||||
+ GRF_PCIE30PHY_DA_OCM);
|
||||
+ } else {
|
||||
+ dev_dbg(&phy->dev, "bifurcation disabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ GRF_PCIE30PHY_STATUS0,
|
||||
+ reg, SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ __func__, reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3568_init,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ u32 reg = 0;
|
||||
+ u8 mode = 0;
|
||||
+ int i, ret;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
|
||||
+
|
||||
+ /* Set bifurcation if needed */
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ if (!priv->lanes[i])
|
||||
+ mode |= (BIT(i) << 3);
|
||||
+
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ mode |= (BIT(i) >> 1);
|
||||
+ }
|
||||
+
|
||||
+ if (!mode)
|
||||
+ reg = RK3588_LANE_AGGREGATION;
|
||||
+ else {
|
||||
+ if (mode & (BIT(0) | BIT(1)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_0_1;
|
||||
+
|
||||
+ if (mode & (BIT(2) | BIT(3)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_2_3;
|
||||
+ }
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
|
||||
+
|
||||
+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
|
||||
+ if (!IS_ERR(priv->pipe_grf)) {
|
||||
+ reg = (mode & (BIT(6) | BIT(7))) >> 6;
|
||||
+ if (reg)
|
||||
+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
|
||||
+ (reg << 16) | reg);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ ret |= regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3588_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3588_init,
|
||||
+};
|
||||
+
|
||||
+static int rochchip_p3phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ udelay(1);
|
||||
+
|
||||
+ if (priv->ops->phy_init) {
|
||||
+ ret = priv->ops->phy_init(priv);
|
||||
+ if (ret)
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rochchip_p3phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_p3phy_ops = {
|
||||
+ .init = rochchip_p3phy_init,
|
||||
+ .exit = rochchip_p3phy_exit,
|
||||
+ .set_mode = rockchip_p3phy_set_mode,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_p3phy_priv *priv;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->mmio = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->ops = of_device_get_match_data(&pdev->dev);
|
||||
+ if (!priv->ops) {
|
||||
+ dev_err(dev, "no of match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
+ "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf))
|
||||
+ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
+
|
||||
+ priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
|
||||
+ priv->lanes, 2,
|
||||
+ ARRAY_SIZE(priv->lanes));
|
||||
+
|
||||
+ /* if no data-lanes assume aggregation */
|
||||
+ if (priv->num_lanes == -EINVAL) {
|
||||
+ dev_dbg(dev, "no data-lanes property found\n");
|
||||
+ priv->num_lanes = 1;
|
||||
+ priv->lanes[0] = 1;
|
||||
+ } else if (priv->num_lanes < 0) {
|
||||
+ dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
|
||||
+ return priv->num_lanes;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
|
||||
+ if (IS_ERR(priv->p30phy)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->p30phy),
|
||||
+ "failed to get phy reset control\n");
|
||||
+ }
|
||||
+ if (!priv->p30phy)
|
||||
+ dev_info(dev, "no phy reset control specified\n");
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_p3phy_of_match[] = {
|
||||
+ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
|
||||
+ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_p3phy_driver = {
|
||||
+ .probe = rockchip_p3phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-snps-pcie3-phy",
|
||||
+ .of_match_table = rockchip_p3phy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_p3phy_driver);
|
||||
+MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/include/linux/phy/pcie.h
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+#ifndef __PHY_PCIE_H
|
||||
+#define __PHY_PCIE_H
|
||||
+
|
||||
+#define PHY_MODE_PCIE_RC 20
|
||||
+#define PHY_MODE_PCIE_EP 21
|
||||
+#define PHY_MODE_PCIE_BIFURCATION 22
|
||||
+
|
||||
+#endif
|
|
@ -0,0 +1,146 @@
|
|||
From faedfa5b40f095d09040c3a040e2f8dee4a36b4b Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Thu, 25 Aug 2022 21:38:35 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rk3568
|
||||
|
||||
Add nodes to rk356x devicetree to support PCIe v3.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
|
||||
1 file changed, 122 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -42,6 +42,128 @@
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
|
||||
+ pcie30_phy_grf: syscon@fdcb8000 {
|
||||
+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30phy: phy@fe8c0000 {
|
||||
+ compatible = "rockchip,rk3568-pcie3-phy";
|
||||
+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
||||
+ #phy-cells = <0>;
|
||||
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
||||
+ <&cru PCLK_PCIE30PHY>;
|
||||
+ clock-names = "refclk_m", "refclk_n", "pclk";
|
||||
+ resets = <&cru SRST_PCIE30PHY>;
|
||||
+ reset-names = "phy";
|
||||
+ rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie3x1: pcie@fe270000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
||||
+ <0 0 0 2 &pcie3x1_intc 1>,
|
||||
+ <0 0 0 3 &pcie3x1_intc 2>,
|
||||
+ <0 0 0 4 &pcie3x1_intc 3>;
|
||||
+ linux,pci-domain = <1>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0400000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe270000 0x0 0x00010000>,
|
||||
+ <0x3 0x7f000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane1 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x1_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie3x2: pcie@fe280000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
+ <0 0 0 2 &pcie3x2_intc 1>,
|
||||
+ <0 0 0 3 &pcie3x2_intc 2>,
|
||||
+ <0 0 0 4 &pcie3x2_intc 3>;
|
||||
+ linux,pci-domain = <2>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <3>;
|
||||
+ msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ num-lanes = <2>;
|
||||
+ phys = <&pcie30phy>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ reg = <0x3 0xc0800000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe280000 0x0 0x00010000>,
|
||||
+ <0x3 0xbf000000 0x0 0x01000000>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ /* bifurcation; lane0 when using 1+1 */
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie3x2_intc: legacy-interrupt-controller {
|
||||
+ interrupt-controller;
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gmac0: ethernet@fe2a0000 {
|
||||
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
|
@ -10,14 +10,19 @@ register to match the blink behavior of the other port on the device.
|
|||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||
1 file changed, 1 insertions(+)
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -404,6 +404,7 @@
|
||||
rtl8153: device@2 {
|
||||
compatible = "usbbda,8153";
|
||||
reg = <2>;
|
||||
@@ -401,4 +401,11 @@
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
+
|
||||
+ usb_eth: usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
+ };
|
||||
};
|
|
@ -0,0 +1,35 @@
|
|||
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Wed, 20 Feb 2019 07:38:34 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
host->ios.clock = 0;
|
||||
host->ios.vdd = 0;
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -96,6 +96,19 @@
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ pcie@0 {
|
||||
+ reg = <0x00000000 0 0 0 0>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ pcie-eth@0,0 {
|
||||
+ compatible = "pci10ec,8168";
|
||||
+ reg = <0x000000 0 0 0 0>;
|
||||
+
|
||||
+ realtek,led-data = <0x870>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pinctrl {
|
|
@ -12,7 +12,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
|||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -121,6 +121,11 @@
|
||||
@@ -145,6 +145,11 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
|
||||
From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
|
||||
Date: Tue, 4 Aug 2020 20:17:53 +0800
|
||||
Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
|
||||
1 files changed, 4 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -165,6 +165,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -2,6 +2,7 @@
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -0,0 +1,39 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus";
|
||||
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "orangepi-r1-plus:green:lan";
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ max-freq = <48000000>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "orangepi-r1-plus:red:sys";
|
||||
+};
|
||||
+
|
||||
+&sys_led_pin {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "orangepi-r1-plus:green:wan";
|
||||
+};
|
|
@ -0,0 +1,79 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,66 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&dmc_opp_table {
|
||||
+ opp-798000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-840000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-924000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ opp-1056000000 {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-id4f51.e91b",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "orangepi-r1-plus-lts:green:lan";
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ label = "orangepi-r1-plus-lts:red:sys";
|
||||
+};
|
||||
+
|
||||
+&usb_eth {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "orangepi-r1-plus-lts:green:wan";
|
||||
+};
|
|
@ -0,0 +1,64 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,51 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-id0000.011a",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&lan_led {
|
||||
+ label = "nanopi-r2c:green:lan";
|
||||
+};
|
||||
+
|
||||
+&sys_led {
|
||||
+ label = "nanopi-r2c:red:sys";
|
||||
+};
|
||||
+
|
||||
+&usb_eth {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
+
|
||||
+&wan_led {
|
||||
+ label = "nanopi-r2c:green:wan";
|
||||
+};
|
|
@ -0,0 +1,444 @@
|
|||
From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001
|
||||
From: Julian Pidancet <julian@pidancet.net>
|
||||
Date: Sun, 23 Jan 2022 16:34:08 +0100
|
||||
Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
|
||||
|
||||
This patch adds support for FriendlyARM NanoPi NEO3
|
||||
|
||||
Soc: RockChip RK3328
|
||||
RAM: 1GB/2GB DDR4
|
||||
LAN: 10/100/1000M Ethernet with unique MAC
|
||||
USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header
|
||||
MicroSD: x 1 for system boot and storage
|
||||
LED: Power LED x 1, System LED x 1
|
||||
Key: User Button x 1
|
||||
Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan
|
||||
GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO
|
||||
Power: 5V/1A, via Type-C or GPIO
|
||||
|
||||
Signed-off-by: Julian Pidancet <julian@pidancet.net>
|
||||
---
|
||||
|
||||
This is another shot at previous work submitted by Marty Jones
|
||||
<mj8263788@gmail.com> (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/),
|
||||
which is now a year old.
|
||||
|
||||
v2: Following up on Robin Murphy's comments, the NEO3 DTS is now
|
||||
standalone and no longer includes the nanopi R2S one. The lan_led and
|
||||
wan_len nodes have been removed, and the sys_led node has been renamed
|
||||
to status_led in accordance with the board schematics.
|
||||
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 396 ++++++++++++++++++
|
||||
2 files changed, 397 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
@@ -0,0 +1,396 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi NEO3";
|
||||
+ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ reset {
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ debounce-interval = <50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ status_led: led-0 {
|
||||
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-neo3:green:status";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_sdio: sdmmcio-regulator {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&sdio_vcc_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_io_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-settling-time-us = <5000>;
|
||||
+ regulator-type = "voltage";
|
||||
+ startup-delay-us = <2000>;
|
||||
+ states = <1800000 0x1>,
|
||||
+ <3300000 0x0>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_gpio>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-name = "vcc_rtl8153";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io_33>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rx_delay = <0x18>;
|
||||
+ snps,aal;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vdd_5v>;
|
||||
+ vcc2-supply = <&vdd_5v>;
|
||||
+ vcc3-supply = <&vdd_5v>;
|
||||
+ vcc4-supply = <&vdd_5v>;
|
||||
+ vcc5-supply = <&vcc_io_33>;
|
||||
+ vcc6-supply = <&vdd_5v>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_33: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io_33";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io_33>;
|
||||
+ vccio1-supply = <&vcc_io_33>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io_sdio>;
|
||||
+ vccio4-supply = <&vcc_18>;
|
||||
+ vccio5-supply = <&vcc_io_33>;
|
||||
+ vccio6-supply = <&vcc_io_33>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ button {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
+};
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue