mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add r5s support. From coolsnowwold repo
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
f2bf060a04
commit
2d9c2e0625
112 changed files with 25981 additions and 75 deletions
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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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||||
* published by the Free Software Foundation; either version 2 of the
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||||
* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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||||
*
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||||
* Or, alternatively,
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||||
*
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||||
* b) Permission is hereby granted, free of charge, to any person
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||||
* obtaining a copy of this software and associated documentation
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||||
* files (the "Software"), to deal in the Software without
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||||
* restriction, including without limitation the rights to use,
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||||
* copy, modify, merge, publish, distribute, sublicense, and/or
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||||
* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk3328-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <DDR3_DEFAULT>;
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ddr4_speed_bin = <DDR4_DEFAULT>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_pd_dis_freq = <1066>;
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auto_sr_dis_freq = <800>;
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ddr3_dll_dis_freq = <300>;
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ddr4_dll_dis_freq = <625>;
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phy_dll_dis_freq = <400>;
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ddr3_odt_dis_freq = <100>;
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phy_ddr3_odt_dis_freq = <100>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
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lpddr3_odt_dis_freq = <666>;
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phy_lpddr3_odt_dis_freq = <666>;
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lpddr3_drv = <LP3_DS_40ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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lpddr4_odt_dis_freq = <800>;
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phy_lpddr4_odt_dis_freq = <800>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
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phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
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ddr4_odt_dis_freq = <666>;
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phy_ddr4_odt_dis_freq = <666>;
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ddr4_drv = <DDR4_DS_34ohm>;
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ddr4_odt = <DDR4_RTT_NOM_240ohm>;
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phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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/* CA de-skew, one step is 47.8ps, range 0-15 */
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ddr3a1_ddr4a9_de-skew = <7>;
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ddr3a0_ddr4a10_de-skew = <7>;
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ddr3a3_ddr4a6_de-skew = <8>;
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ddr3a2_ddr4a4_de-skew = <8>;
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ddr3a5_ddr4a8_de-skew = <7>;
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ddr3a4_ddr4a5_de-skew = <9>;
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ddr3a7_ddr4a11_de-skew = <7>;
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ddr3a6_ddr4a7_de-skew = <9>;
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ddr3a9_ddr4a0_de-skew = <8>;
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ddr3a8_ddr4a13_de-skew = <7>;
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ddr3a11_ddr4a3_de-skew = <9>;
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ddr3a10_ddr4cs0_de-skew = <7>;
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ddr3a13_ddr4a2_de-skew = <8>;
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ddr3a12_ddr4ba1_de-skew = <7>;
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ddr3a15_ddr4odt0_de-skew = <7>;
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ddr3a14_ddr4a1_de-skew = <8>;
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ddr3ba1_ddr4a15_de-skew = <7>;
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ddr3ba0_ddr4bg0_de-skew = <7>;
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ddr3ras_ddr4cke_de-skew = <7>;
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ddr3ba2_ddr4ba0_de-skew = <8>;
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ddr3we_ddr4bg1_de-skew = <8>;
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ddr3cas_ddr4a12_de-skew = <7>;
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ddr3ckn_ddr4ckn_de-skew = <8>;
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ddr3ckp_ddr4ckp_de-skew = <8>;
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ddr3cke_ddr4a16_de-skew = <8>;
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ddr3odt0_ddr4a14_de-skew = <7>;
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ddr3cs0_ddr4act_de-skew = <8>;
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ddr3reset_ddr4reset_de-skew = <7>;
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ddr3cs1_ddr4cs1_de-skew = <7>;
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ddr3odt1_ddr4odt1_de-skew = <7>;
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/* DATA de-skew
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* RX one step is 25.1ps, range 0-15
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* TX one step is 47.8ps, range 0-15
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*/
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cs0_dm0_rx_de-skew = <7>;
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cs0_dm0_tx_de-skew = <8>;
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cs0_dq0_rx_de-skew = <7>;
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cs0_dq0_tx_de-skew = <8>;
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cs0_dq1_rx_de-skew = <7>;
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cs0_dq1_tx_de-skew = <8>;
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cs0_dq2_rx_de-skew = <7>;
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cs0_dq2_tx_de-skew = <8>;
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cs0_dq3_rx_de-skew = <7>;
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cs0_dq3_tx_de-skew = <8>;
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cs0_dq4_rx_de-skew = <7>;
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cs0_dq4_tx_de-skew = <8>;
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cs0_dq5_rx_de-skew = <7>;
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cs0_dq5_tx_de-skew = <8>;
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cs0_dq6_rx_de-skew = <7>;
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cs0_dq6_tx_de-skew = <8>;
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cs0_dq7_rx_de-skew = <7>;
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cs0_dq7_tx_de-skew = <8>;
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cs0_dqs0_rx_de-skew = <6>;
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cs0_dqs0p_tx_de-skew = <9>;
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cs0_dqs0n_tx_de-skew = <9>;
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cs0_dm1_rx_de-skew = <7>;
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cs0_dm1_tx_de-skew = <7>;
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cs0_dq8_rx_de-skew = <7>;
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cs0_dq8_tx_de-skew = <8>;
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cs0_dq9_rx_de-skew = <7>;
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cs0_dq9_tx_de-skew = <7>;
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cs0_dq10_rx_de-skew = <7>;
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cs0_dq10_tx_de-skew = <8>;
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cs0_dq11_rx_de-skew = <7>;
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cs0_dq11_tx_de-skew = <7>;
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cs0_dq12_rx_de-skew = <7>;
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cs0_dq12_tx_de-skew = <8>;
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cs0_dq13_rx_de-skew = <7>;
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cs0_dq13_tx_de-skew = <7>;
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cs0_dq14_rx_de-skew = <7>;
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cs0_dq14_tx_de-skew = <8>;
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cs0_dq15_rx_de-skew = <7>;
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cs0_dq15_tx_de-skew = <7>;
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cs0_dqs1_rx_de-skew = <7>;
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cs0_dqs1p_tx_de-skew = <9>;
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cs0_dqs1n_tx_de-skew = <9>;
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cs0_dm2_rx_de-skew = <7>;
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cs0_dm2_tx_de-skew = <8>;
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cs0_dq16_rx_de-skew = <7>;
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cs0_dq16_tx_de-skew = <8>;
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cs0_dq17_rx_de-skew = <7>;
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cs0_dq17_tx_de-skew = <8>;
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cs0_dq18_rx_de-skew = <7>;
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cs0_dq18_tx_de-skew = <8>;
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cs0_dq19_rx_de-skew = <7>;
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cs0_dq19_tx_de-skew = <8>;
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cs0_dq20_rx_de-skew = <7>;
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cs0_dq20_tx_de-skew = <8>;
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cs0_dq21_rx_de-skew = <7>;
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cs0_dq21_tx_de-skew = <8>;
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cs0_dq22_rx_de-skew = <7>;
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cs0_dq22_tx_de-skew = <8>;
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cs0_dq23_rx_de-skew = <7>;
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cs0_dq23_tx_de-skew = <8>;
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cs0_dqs2_rx_de-skew = <6>;
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cs0_dqs2p_tx_de-skew = <9>;
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cs0_dqs2n_tx_de-skew = <9>;
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cs0_dm3_rx_de-skew = <7>;
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cs0_dm3_tx_de-skew = <7>;
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cs0_dq24_rx_de-skew = <7>;
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cs0_dq24_tx_de-skew = <8>;
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cs0_dq25_rx_de-skew = <7>;
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cs0_dq25_tx_de-skew = <7>;
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cs0_dq26_rx_de-skew = <7>;
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cs0_dq26_tx_de-skew = <7>;
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cs0_dq27_rx_de-skew = <7>;
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cs0_dq27_tx_de-skew = <7>;
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cs0_dq28_rx_de-skew = <7>;
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cs0_dq28_tx_de-skew = <7>;
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cs0_dq29_rx_de-skew = <7>;
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cs0_dq29_tx_de-skew = <7>;
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cs0_dq30_rx_de-skew = <7>;
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cs0_dq30_tx_de-skew = <7>;
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cs0_dq31_rx_de-skew = <7>;
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cs0_dq31_tx_de-skew = <7>;
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cs0_dqs3_rx_de-skew = <7>;
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cs0_dqs3p_tx_de-skew = <9>;
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cs0_dqs3n_tx_de-skew = <9>;
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cs1_dm0_rx_de-skew = <7>;
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cs1_dm0_tx_de-skew = <8>;
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cs1_dq0_rx_de-skew = <7>;
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cs1_dq0_tx_de-skew = <8>;
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cs1_dq1_rx_de-skew = <7>;
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cs1_dq1_tx_de-skew = <8>;
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cs1_dq2_rx_de-skew = <7>;
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cs1_dq2_tx_de-skew = <8>;
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cs1_dq3_rx_de-skew = <7>;
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cs1_dq3_tx_de-skew = <8>;
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cs1_dq4_rx_de-skew = <7>;
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cs1_dq4_tx_de-skew = <8>;
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cs1_dq5_rx_de-skew = <7>;
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cs1_dq5_tx_de-skew = <8>;
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cs1_dq6_rx_de-skew = <7>;
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cs1_dq6_tx_de-skew = <8>;
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cs1_dq7_rx_de-skew = <7>;
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cs1_dq7_tx_de-skew = <8>;
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cs1_dqs0_rx_de-skew = <6>;
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cs1_dqs0p_tx_de-skew = <9>;
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cs1_dqs0n_tx_de-skew = <9>;
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cs1_dm1_rx_de-skew = <7>;
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cs1_dm1_tx_de-skew = <7>;
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cs1_dq8_rx_de-skew = <7>;
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cs1_dq8_tx_de-skew = <8>;
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cs1_dq9_rx_de-skew = <7>;
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cs1_dq9_tx_de-skew = <7>;
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cs1_dq10_rx_de-skew = <7>;
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cs1_dq10_tx_de-skew = <8>;
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cs1_dq11_rx_de-skew = <7>;
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cs1_dq11_tx_de-skew = <7>;
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cs1_dq12_rx_de-skew = <7>;
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cs1_dq12_tx_de-skew = <8>;
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cs1_dq13_rx_de-skew = <7>;
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cs1_dq13_tx_de-skew = <7>;
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cs1_dq14_rx_de-skew = <7>;
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cs1_dq14_tx_de-skew = <8>;
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cs1_dq15_rx_de-skew = <7>;
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cs1_dq15_tx_de-skew = <7>;
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cs1_dqs1_rx_de-skew = <7>;
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cs1_dqs1p_tx_de-skew = <9>;
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cs1_dqs1n_tx_de-skew = <9>;
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cs1_dm2_rx_de-skew = <7>;
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cs1_dm2_tx_de-skew = <8>;
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cs1_dq16_rx_de-skew = <7>;
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cs1_dq16_tx_de-skew = <8>;
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cs1_dq17_rx_de-skew = <7>;
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cs1_dq17_tx_de-skew = <8>;
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cs1_dq18_rx_de-skew = <7>;
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cs1_dq18_tx_de-skew = <8>;
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cs1_dq19_rx_de-skew = <7>;
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cs1_dq19_tx_de-skew = <8>;
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cs1_dq20_rx_de-skew = <7>;
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cs1_dq20_tx_de-skew = <8>;
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cs1_dq21_rx_de-skew = <7>;
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cs1_dq21_tx_de-skew = <8>;
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cs1_dq22_rx_de-skew = <7>;
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cs1_dq22_tx_de-skew = <8>;
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cs1_dq23_rx_de-skew = <7>;
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cs1_dq23_tx_de-skew = <8>;
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cs1_dqs2_rx_de-skew = <6>;
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cs1_dqs2p_tx_de-skew = <9>;
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cs1_dqs2n_tx_de-skew = <9>;
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cs1_dm3_rx_de-skew = <7>;
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cs1_dm3_tx_de-skew = <7>;
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cs1_dq24_rx_de-skew = <7>;
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cs1_dq24_tx_de-skew = <8>;
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cs1_dq25_rx_de-skew = <7>;
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cs1_dq25_tx_de-skew = <7>;
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cs1_dq26_rx_de-skew = <7>;
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cs1_dq26_tx_de-skew = <7>;
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cs1_dq27_rx_de-skew = <7>;
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cs1_dq27_tx_de-skew = <7>;
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cs1_dq28_rx_de-skew = <7>;
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cs1_dq28_tx_de-skew = <7>;
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cs1_dq29_rx_de-skew = <7>;
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cs1_dq29_tx_de-skew = <7>;
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cs1_dq30_rx_de-skew = <7>;
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cs1_dq30_tx_de-skew = <7>;
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cs1_dq31_rx_de-skew = <7>;
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cs1_dq31_tx_de-skew = <7>;
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cs1_dqs3_rx_de-skew = <7>;
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cs1_dqs3p_tx_de-skew = <9>;
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cs1_dqs3n_tx_de-skew = <9>;
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};
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};
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@ -0,0 +1,311 @@
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/*
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||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rk3328-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr3_odt_dis_freq = <100>;
|
||||
phy_ddr3_odt_dis_freq = <100>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
|
||||
|
||||
lpddr3_odt_dis_freq = <666>;
|
||||
phy_lpddr3_odt_dis_freq = <666>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
/* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
ddr3a1_ddr4a9_de-skew = <7>;
|
||||
ddr3a0_ddr4a10_de-skew = <7>;
|
||||
ddr3a3_ddr4a6_de-skew = <8>;
|
||||
ddr3a2_ddr4a4_de-skew = <8>;
|
||||
ddr3a5_ddr4a8_de-skew = <7>;
|
||||
ddr3a4_ddr4a5_de-skew = <9>;
|
||||
ddr3a7_ddr4a11_de-skew = <7>;
|
||||
ddr3a6_ddr4a7_de-skew = <9>;
|
||||
ddr3a9_ddr4a0_de-skew = <8>;
|
||||
ddr3a8_ddr4a13_de-skew = <7>;
|
||||
ddr3a11_ddr4a3_de-skew = <9>;
|
||||
ddr3a10_ddr4cs0_de-skew = <7>;
|
||||
ddr3a13_ddr4a2_de-skew = <8>;
|
||||
ddr3a12_ddr4ba1_de-skew = <7>;
|
||||
ddr3a15_ddr4odt0_de-skew = <7>;
|
||||
ddr3a14_ddr4a1_de-skew = <8>;
|
||||
ddr3ba1_ddr4a15_de-skew = <7>;
|
||||
ddr3ba0_ddr4bg0_de-skew = <7>;
|
||||
ddr3ras_ddr4cke_de-skew = <7>;
|
||||
ddr3ba2_ddr4ba0_de-skew = <8>;
|
||||
ddr3we_ddr4bg1_de-skew = <8>;
|
||||
ddr3cas_ddr4a12_de-skew = <7>;
|
||||
ddr3ckn_ddr4ckn_de-skew = <8>;
|
||||
ddr3ckp_ddr4ckp_de-skew = <8>;
|
||||
ddr3cke_ddr4a16_de-skew = <8>;
|
||||
ddr3odt0_ddr4a14_de-skew = <7>;
|
||||
ddr3cs0_ddr4act_de-skew = <8>;
|
||||
ddr3reset_ddr4reset_de-skew = <7>;
|
||||
ddr3cs1_ddr4cs1_de-skew = <7>;
|
||||
ddr3odt1_ddr4odt1_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew
|
||||
* RX one step is 25.1ps, range 0-15
|
||||
* TX one step is 47.8ps, range 0-15
|
||||
*/
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dm0_tx_de-skew = <8>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <8>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <8>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <8>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <8>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <8>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <8>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <8>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <8>;
|
||||
cs0_dqs0_rx_de-skew = <6>;
|
||||
cs0_dqs0p_tx_de-skew = <9>;
|
||||
cs0_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <8>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <8>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <8>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <8>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1_rx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <9>;
|
||||
cs0_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dm2_tx_de-skew = <8>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <8>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <8>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <8>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <8>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <8>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <8>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <8>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <8>;
|
||||
cs0_dqs2_rx_de-skew = <6>;
|
||||
cs0_dqs2p_tx_de-skew = <9>;
|
||||
cs0_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <8>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3_rx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <9>;
|
||||
cs0_dqs3n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dm0_tx_de-skew = <8>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <8>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <8>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <8>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <8>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <8>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <8>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <8>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <8>;
|
||||
cs1_dqs0_rx_de-skew = <6>;
|
||||
cs1_dqs0p_tx_de-skew = <9>;
|
||||
cs1_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <8>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <8>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <8>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <8>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1_rx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <9>;
|
||||
cs1_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dm2_tx_de-skew = <8>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <8>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <8>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <8>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <8>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <8>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <8>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <8>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <8>;
|
||||
cs1_dqs2_rx_de-skew = <6>;
|
||||
cs1_dqs2p_tx_de-skew = <9>;
|
||||
cs1_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <8>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3_rx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <9>;
|
||||
cs1_dqs3n_tx_de-skew = <9>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,664 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI GuangMiao G4C";
|
||||
compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
|
||||
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
aliases {
|
||||
led-boot = &status_led;
|
||||
led-failsafe = &status_led;
|
||||
led-running = &status_led;
|
||||
led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc_sys";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_0v9: vcc-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vcc_0v9";
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host0: vcc5v0-host0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_host0";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd_log";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
|
||||
|
||||
lan_led: led-lan {
|
||||
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
status_led: led-status {
|
||||
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:status";
|
||||
};
|
||||
|
||||
wan_led: led-wan {
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
|
||||
phy-handle = <&rtl8211e>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc3v3_s3>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpu_b_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpu_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
|
||||
#clock-cells = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_3v0>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_center";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo1: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo1";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo2: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo2";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_sdio";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc3v0_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vcc_1v5";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_codec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc_3v0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bt656-supply = <&vcc_1v8>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||
vpcie0v9-supply = <&vcc_0v9>;
|
||||
vpcie1v8-supply = <&vcca_1v8>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-leds {
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
gpu_sleep: gpu-sleep {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
bt_reg_on_h: bt-reg-on-h {
|
||||
/* external pullup to VCC1V8_PMUPLL */
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc0_det_l: sdmmc0-det-l {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm2_pin_pull_down>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
1127
root/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
1127
root/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-nanopi-r4s.dts"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R4SE";
|
||||
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,530 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>;
|
||||
|
||||
led_work: led-0 {
|
||||
label = "blue:work-led";
|
||||
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
mbi-ranges = <94 31>, <229 31>, <289 31>;
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x4078>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x4078>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,654 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S";
|
||||
compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sata_en>, <&led_sys_en>;
|
||||
|
||||
sata {
|
||||
label = "blue:sata";
|
||||
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
};
|
||||
|
||||
vcc5v0_ahci: vcc5v0-ahci {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata_pwr_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_ahci";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
sata_pwr_en: sata-pwr-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
target-supply = <&vcc5v0_ahci>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,710 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
* Copyright (c) 2022 Marty Jones <mj8263788@gmail.com>
|
||||
* Copyright (c) 2022 Tianling Shen <cnsztl@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5S";
|
||||
compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>,
|
||||
<&sys_led_pin>, <&wan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan1_led: led-0 {
|
||||
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan1";
|
||||
};
|
||||
|
||||
lan2_led: led-1 {
|
||||
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan2";
|
||||
};
|
||||
|
||||
sys_led: led-2 {
|
||||
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-3 {
|
||||
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 15ms, 50ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 15000 50000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@00 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
lan1_led_pin: lan1-led-pin {
|
||||
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan2_led_pin: lan2-led-pin {
|
||||
rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
gmac_int: gmac-int {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,725 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H68K Board";
|
||||
compatible = "hinlink,opc-h68k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
|
||||
|
||||
net {
|
||||
label = "blue:net";
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata {
|
||||
label = "amber:sata";
|
||||
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_work: work {
|
||||
label = "green:work";
|
||||
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: gpio-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
button {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_net_en: led_net_en {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R66S";
|
||||
compatible = "fastrhino,r66s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R68S";
|
||||
compatible = "fastrhino,r68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,797 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Firefly Station P2";
|
||||
compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>, <&led_user_en>;
|
||||
|
||||
led-work {
|
||||
label = "blue:work";
|
||||
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
||||
};
|
||||
|
||||
led-user {
|
||||
label = "yellow:user";
|
||||
gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <100>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe: pcie-pi6c-oe {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie_pi6c_oe_en";
|
||||
regulator-always-on;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pi6c_oe_en>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc_hub_reset: vcc-hub-reset {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_hub_reset";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_hub_reset_en>;
|
||||
};
|
||||
|
||||
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd0_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd1_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&gmac0_clkinout>;
|
||||
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus
|
||||
&gmac1m1_clkinout>;
|
||||
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc_hub_reset_en: vcc-hub-reset-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
fusb0_int {
|
||||
fusb0_int: fusb0-int {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe_en: pcie-pi6c-oe-en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&pcie_pi6c_oe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,766 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK3 Model A";
|
||||
compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub: vcc5v0-usb-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_hub_en>;
|
||||
regulator-name = "vcc5v0_usb_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c_03: vcc3v3-pi6c-03 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pi6c_03";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_cam: vcc-cam {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_cam_en>;
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_mipi_en>;
|
||||
regulator-name = "vcc_mipi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c_03>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
vcc_cam_en: vcc_cam_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
display {
|
||||
vcc_mipi_en: vcc_mipi_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,630 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK Pi E25";
|
||||
compatible = "radxa,rockpi-e25", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
compatible = "pwm-leds-multicolor";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
max-brightness = <255>;
|
||||
|
||||
led-red {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
pwms = <&pwm1 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
pwms = <&pwm2 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-blue {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
pwms = <&pwm12 0 1000000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
typec_5v: typec-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "typec_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc5v0_sys, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie30x1: vcc3v3-pcie30x1 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie30x1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c_05>;
|
||||
};
|
||||
|
||||
vcc3v3_pi6c_05: vcc3v3-pi6c-05 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_minipcie: vcc3v3-minipcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_enable_h>;
|
||||
regulator-name = "vcc3v3_minipcie";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&typec_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&typec_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20_reset_h>;
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie20_reset_h: pcie20-reset-h {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x1_enable_h: pcie30x1-enable-h {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x2_reset_h: pcie30x2-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
minipcie_enable_h: minipcie-enable-h {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm12 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm12m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
/* Also used in pcie30x1_clkreqnm0 */
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk356x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
sata0: sata@fc000000 {
|
||||
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfc000000 0 0x1000>;
|
||||
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
||||
<&cru CLK_SATA0_RXOOB>;
|
||||
clock-names = "sata", "pmalive", "rxoob";
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&combphy0 PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
ports-implemented = <0x1>;
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pipe_phy_grf0: syscon@fdc70000 {
|
||||
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfdc70000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
qos_pcie3x1: qos@fe190080 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_pcie3x2: qos@fe190100 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190100 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_sata0: qos@fe190200 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
|
||||
pcie30_phy_grf: syscon@fdcb8000 {
|
||||
compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfdcb8000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pcie30phy: phy@fe8c0000 {
|
||||
compatible = "rockchip,rk3568-pcie3-phy";
|
||||
reg = <0x0 0xfe8c0000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
|
||||
<&cru PCLK_PCIE30PHY>;
|
||||
clock-names = "refclk_m", "refclk_n", "pclk";
|
||||
resets = <&cru SRST_PCIE30PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x1: pcie@fe270000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
|
||||
<0 0 0 2 &pcie3x1_intc 1>,
|
||||
<0 0 0 3 &pcie3x1_intc 2>,
|
||||
<0 0 0 4 &pcie3x1_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
reg = <0x3 0xc0400000 0x0 0x00400000>,
|
||||
<0x0 0xfe270000 0x0 0x00010000>,
|
||||
<0x3 0x7f000000 0x0 0x01000000>;
|
||||
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE30X1_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
/* bifurcation; lane1 when using 1+1 */
|
||||
status = "disabled";
|
||||
|
||||
pcie3x1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3x2: pcie@fe280000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
<0 0 0 2 &pcie3x2_intc 1>,
|
||||
<0 0 0 3 &pcie3x2_intc 2>,
|
||||
<0 0 0 4 &pcie3x2_intc 3>;
|
||||
linux,pci-domain = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
reg = <0x3 0xc0800000 0x0 0x00400000>,
|
||||
<0x0 0xfe280000 0x0 0x00010000>,
|
||||
<0x3 0xbf000000 0x0 0x01000000>;
|
||||
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE30X2_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
/* bifurcation; lane0 when using 1+1 */
|
||||
status = "disabled";
|
||||
|
||||
pcie3x2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@fe2a0000 {
|
||||
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
"clk_mac_speed", "ptp_ref";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
snps,mixed-burst;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
snps,rd_osr_lmt = <8>;
|
||||
snps,wr_osr_lmt = <4>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
};
|
||||
|
||||
combphy0: phy@fe820000 {
|
||||
compatible = "rockchip,rk3568-naneng-combphy";
|
||||
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||
clocks = <&pmucru CLK_PCIEPHY0_REF>,
|
||||
<&cru PCLK_PIPEPHY0>,
|
||||
<&cru PCLK_PIPE>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_PIPEPHY0>;
|
||||
rockchip,pipe-grf = <&pipegrf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
||||
#phy-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
opp-1992000000 {
|
||||
opp-hz = /bits/ 64 <1992000000>;
|
||||
opp-microvolt = <1150000 1150000 1150000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pipegrf {
|
||||
compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||
};
|
||||
|
||||
&power {
|
||||
power-domain@RK3568_PD_PIPE {
|
||||
reg = <RK3568_PD_PIPE>;
|
||||
clocks = <&cru PCLK_PIPE>;
|
||||
pm_qos = <&qos_pcie2x1>,
|
||||
<&qos_pcie3x1>,
|
||||
<&qos_pcie3x2>,
|
||||
<&qos_sata0>,
|
||||
<&qos_sata1>,
|
||||
<&qos_sata2>,
|
||||
<&qos_usb3_0>,
|
||||
<&qos_usb3_1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
|
||||
&vop {
|
||||
compatible = "rockchip,rk3568-vop";
|
||||
};
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,344 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
|
||||
bias-disable;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
|
||||
bias-disable;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
|
||||
bias-disable;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
|
||||
bias-disable;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
|
||||
bias-disable;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
|
||||
bias-disable;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
|
||||
bias-disable;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
|
||||
bias-disable;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
|
||||
bias-disable;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
|
||||
bias-disable;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
|
||||
bias-disable;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
|
||||
bias-disable;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
|
||||
bias-pull-up;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
|
||||
bias-pull-up;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
|
||||
bias-pull-up;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
|
||||
bias-pull-up;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
|
||||
bias-pull-up;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
|
||||
bias-pull-up;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
|
||||
bias-pull-up;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
|
||||
bias-pull-up;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
|
||||
bias-pull-up;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
|
||||
bias-pull-up;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
|
||||
bias-pull-down;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
|
||||
bias-pull-down;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
|
||||
bias-pull-down;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
|
||||
bias-pull-down;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
|
||||
bias-pull-down;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
|
||||
bias-pull-down;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
|
||||
bias-pull-down;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
|
||||
bias-pull-down;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
|
||||
bias-pull-down;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
|
||||
bias-pull-down;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
|
||||
bias-pull-down;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
|
||||
bias-pull-down;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
|
||||
bias-pull-down;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
|
||||
bias-pull-down;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
|
||||
bias-pull-down;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_smt: pcfg-pull-up-smt {
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_smt: pcfg-pull-down-smt {
|
||||
bias-pull-down;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rockchip-rng.c Random Number Generator driver for the Rockchip
|
||||
*
|
||||
* Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/hw_random.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define _SBF(s, v) ((v) << (s))
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
|
||||
#define ROCKCHIP_POLL_PERIOD_US 100
|
||||
#define ROCKCHIP_POLL_TIMEOUT_US 10000
|
||||
#define RK_MAX_RNG_BYTE (32)
|
||||
|
||||
/* start of CRYPTO V1 register define */
|
||||
#define CRYPTO_V1_CTRL 0x0008
|
||||
#define CRYPTO_V1_RNG_START BIT(8)
|
||||
#define CRYPTO_V1_RNG_FLUSH BIT(9)
|
||||
|
||||
#define CRYPTO_V1_TRNG_CTRL 0x0200
|
||||
#define CRYPTO_V1_OSC_ENABLE BIT(16)
|
||||
#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
|
||||
|
||||
#define CRYPTO_V1_TRNG_DOUT_0 0x0204
|
||||
/* end of CRYPTO V1 register define */
|
||||
|
||||
/* start of CRYPTO V2 register define */
|
||||
#define CRYPTO_V2_RNG_CTL 0x0400
|
||||
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
|
||||
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
|
||||
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
|
||||
#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
|
||||
#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
|
||||
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
|
||||
#define CRYPTO_V2_RNG_ENABLE BIT(1)
|
||||
#define CRYPTO_V2_RNG_START BIT(0)
|
||||
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
|
||||
#define CRYPTO_V2_RNG_DOUT_0 0x0410
|
||||
/* end of CRYPTO V2 register define */
|
||||
|
||||
struct rk_rng_soc_data {
|
||||
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
|
||||
};
|
||||
|
||||
struct rk_rng {
|
||||
struct device *dev;
|
||||
struct hwrng rng;
|
||||
void __iomem *mem;
|
||||
struct rk_rng_soc_data *soc_data;
|
||||
int clk_num;
|
||||
struct clk_bulk_data *clk_bulks;
|
||||
};
|
||||
|
||||
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
|
||||
{
|
||||
__raw_writel(val, rng->mem + offset);
|
||||
}
|
||||
|
||||
static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
|
||||
{
|
||||
return __raw_readl(rng->mem + offset);
|
||||
}
|
||||
|
||||
static int rk_rng_init(struct hwrng *rng)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
|
||||
|
||||
ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
if (ret < 0) {
|
||||
dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk_rng_cleanup(struct hwrng *rng)
|
||||
{
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
|
||||
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
}
|
||||
|
||||
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
|
||||
size_t size)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < size; i += 4)
|
||||
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
|
||||
}
|
||||
|
||||
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
|
||||
|
||||
reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
|
||||
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V1_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
|
||||
CRYPTO_V1_CTRL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
|
||||
|
||||
reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_START;
|
||||
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
|
||||
CRYPTO_V2_RNG_CTL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V2_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
|
||||
.rk_rng_read = rk_rng_v1_read,
|
||||
};
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
|
||||
.rk_rng_read = rk_rng_v2_read,
|
||||
};
|
||||
|
||||
static const struct of_device_id rk_rng_dt_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,cryptov1-rng",
|
||||
.data = (void *)&rk_rng_v1_soc_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,cryptov2-rng",
|
||||
.data = (void *)&rk_rng_v2_soc_data,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
|
||||
|
||||
static int rk_rng_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
|
||||
dev_dbg(&pdev->dev, "probing...\n");
|
||||
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
|
||||
if (!rk_rng)
|
||||
return -ENOMEM;
|
||||
|
||||
match = of_match_node(rk_rng_dt_match, np);
|
||||
rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
|
||||
|
||||
rk_rng->dev = &pdev->dev;
|
||||
rk_rng->rng.name = "rockchip";
|
||||
#ifndef CONFIG_PM
|
||||
rk_rng->rng.init = rk_rng_init;
|
||||
rk_rng->rng.cleanup = rk_rng_cleanup,
|
||||
#endif
|
||||
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
|
||||
rk_rng->rng.quality = 999;
|
||||
|
||||
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
|
||||
if (IS_ERR(rk_rng->mem))
|
||||
return PTR_ERR(rk_rng->mem);
|
||||
|
||||
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
|
||||
if (rk_rng->clk_num < 0) {
|
||||
dev_err(&pdev->dev, "failed to get clks property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, rk_rng);
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
||||
ROCKCHIP_AUTOSUSPEND_DELAY);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
|
||||
if (ret) {
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int rk_rng_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
rk_rng_cleanup(&rk_rng->rng);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_rng_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
return rk_rng_init(&rk_rng->rng);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rk_rng_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
|
||||
rk_rng_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_driver rk_rng_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-rng",
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &rk_rng_pm_ops,
|
||||
#endif
|
||||
.of_match_table = rk_rng_dt_match,
|
||||
},
|
||||
.probe = rk_rng_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rk_rng_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
|
||||
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
852
root/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
852
root/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
|
|
@ -0,0 +1,852 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iversion.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <soc/rockchip/rockchip_sip.h>
|
||||
|
||||
#define DTS_PAR_OFFSET (4096)
|
||||
|
||||
struct share_params {
|
||||
u32 hz;
|
||||
u32 lcdc_type;
|
||||
u32 vop;
|
||||
u32 vop_dclk_mode;
|
||||
u32 sr_idle_en;
|
||||
u32 addr_mcu_el3;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag1;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag0;
|
||||
u32 complt_hwirq;
|
||||
/* if need, add parameter after */
|
||||
};
|
||||
|
||||
static struct share_params *ddr_psci_param;
|
||||
|
||||
/* hope this define can adapt all future platform */
|
||||
static const char * const rk3328_dts_timing[] = {
|
||||
"ddr3_speed_bin",
|
||||
"ddr4_speed_bin",
|
||||
"pd_idle",
|
||||
"sr_idle",
|
||||
"sr_mc_gate_idle",
|
||||
"srpd_lite_idle",
|
||||
"standby_idle",
|
||||
|
||||
"auto_pd_dis_freq",
|
||||
"auto_sr_dis_freq",
|
||||
"ddr3_dll_dis_freq",
|
||||
"ddr4_dll_dis_freq",
|
||||
"phy_dll_dis_freq",
|
||||
|
||||
"ddr3_odt_dis_freq",
|
||||
"phy_ddr3_odt_dis_freq",
|
||||
"ddr3_drv",
|
||||
"ddr3_odt",
|
||||
"phy_ddr3_ca_drv",
|
||||
"phy_ddr3_ck_drv",
|
||||
"phy_ddr3_dq_drv",
|
||||
"phy_ddr3_odt",
|
||||
|
||||
"lpddr3_odt_dis_freq",
|
||||
"phy_lpddr3_odt_dis_freq",
|
||||
"lpddr3_drv",
|
||||
"lpddr3_odt",
|
||||
"phy_lpddr3_ca_drv",
|
||||
"phy_lpddr3_ck_drv",
|
||||
"phy_lpddr3_dq_drv",
|
||||
"phy_lpddr3_odt",
|
||||
|
||||
"lpddr4_odt_dis_freq",
|
||||
"phy_lpddr4_odt_dis_freq",
|
||||
"lpddr4_drv",
|
||||
"lpddr4_dq_odt",
|
||||
"lpddr4_ca_odt",
|
||||
"phy_lpddr4_ca_drv",
|
||||
"phy_lpddr4_ck_cs_drv",
|
||||
"phy_lpddr4_dq_drv",
|
||||
"phy_lpddr4_odt",
|
||||
|
||||
"ddr4_odt_dis_freq",
|
||||
"phy_ddr4_odt_dis_freq",
|
||||
"ddr4_drv",
|
||||
"ddr4_odt",
|
||||
"phy_ddr4_ca_drv",
|
||||
"phy_ddr4_ck_drv",
|
||||
"phy_ddr4_dq_drv",
|
||||
"phy_ddr4_odt",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_ca_timing[] = {
|
||||
"ddr3a1_ddr4a9_de-skew",
|
||||
"ddr3a0_ddr4a10_de-skew",
|
||||
"ddr3a3_ddr4a6_de-skew",
|
||||
"ddr3a2_ddr4a4_de-skew",
|
||||
"ddr3a5_ddr4a8_de-skew",
|
||||
"ddr3a4_ddr4a5_de-skew",
|
||||
"ddr3a7_ddr4a11_de-skew",
|
||||
"ddr3a6_ddr4a7_de-skew",
|
||||
"ddr3a9_ddr4a0_de-skew",
|
||||
"ddr3a8_ddr4a13_de-skew",
|
||||
"ddr3a11_ddr4a3_de-skew",
|
||||
"ddr3a10_ddr4cs0_de-skew",
|
||||
"ddr3a13_ddr4a2_de-skew",
|
||||
"ddr3a12_ddr4ba1_de-skew",
|
||||
"ddr3a15_ddr4odt0_de-skew",
|
||||
"ddr3a14_ddr4a1_de-skew",
|
||||
"ddr3ba1_ddr4a15_de-skew",
|
||||
"ddr3ba0_ddr4bg0_de-skew",
|
||||
"ddr3ras_ddr4cke_de-skew",
|
||||
"ddr3ba2_ddr4ba0_de-skew",
|
||||
"ddr3we_ddr4bg1_de-skew",
|
||||
"ddr3cas_ddr4a12_de-skew",
|
||||
"ddr3ckn_ddr4ckn_de-skew",
|
||||
"ddr3ckp_ddr4ckp_de-skew",
|
||||
"ddr3cke_ddr4a16_de-skew",
|
||||
"ddr3odt0_ddr4a14_de-skew",
|
||||
"ddr3cs0_ddr4act_de-skew",
|
||||
"ddr3reset_ddr4reset_de-skew",
|
||||
"ddr3cs1_ddr4cs1_de-skew",
|
||||
"ddr3odt1_ddr4odt1_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs0_timing[] = {
|
||||
"cs0_dm0_rx_de-skew",
|
||||
"cs0_dm0_tx_de-skew",
|
||||
"cs0_dq0_rx_de-skew",
|
||||
"cs0_dq0_tx_de-skew",
|
||||
"cs0_dq1_rx_de-skew",
|
||||
"cs0_dq1_tx_de-skew",
|
||||
"cs0_dq2_rx_de-skew",
|
||||
"cs0_dq2_tx_de-skew",
|
||||
"cs0_dq3_rx_de-skew",
|
||||
"cs0_dq3_tx_de-skew",
|
||||
"cs0_dq4_rx_de-skew",
|
||||
"cs0_dq4_tx_de-skew",
|
||||
"cs0_dq5_rx_de-skew",
|
||||
"cs0_dq5_tx_de-skew",
|
||||
"cs0_dq6_rx_de-skew",
|
||||
"cs0_dq6_tx_de-skew",
|
||||
"cs0_dq7_rx_de-skew",
|
||||
"cs0_dq7_tx_de-skew",
|
||||
"cs0_dqs0_rx_de-skew",
|
||||
"cs0_dqs0p_tx_de-skew",
|
||||
"cs0_dqs0n_tx_de-skew",
|
||||
|
||||
"cs0_dm1_rx_de-skew",
|
||||
"cs0_dm1_tx_de-skew",
|
||||
"cs0_dq8_rx_de-skew",
|
||||
"cs0_dq8_tx_de-skew",
|
||||
"cs0_dq9_rx_de-skew",
|
||||
"cs0_dq9_tx_de-skew",
|
||||
"cs0_dq10_rx_de-skew",
|
||||
"cs0_dq10_tx_de-skew",
|
||||
"cs0_dq11_rx_de-skew",
|
||||
"cs0_dq11_tx_de-skew",
|
||||
"cs0_dq12_rx_de-skew",
|
||||
"cs0_dq12_tx_de-skew",
|
||||
"cs0_dq13_rx_de-skew",
|
||||
"cs0_dq13_tx_de-skew",
|
||||
"cs0_dq14_rx_de-skew",
|
||||
"cs0_dq14_tx_de-skew",
|
||||
"cs0_dq15_rx_de-skew",
|
||||
"cs0_dq15_tx_de-skew",
|
||||
"cs0_dqs1_rx_de-skew",
|
||||
"cs0_dqs1p_tx_de-skew",
|
||||
"cs0_dqs1n_tx_de-skew",
|
||||
|
||||
"cs0_dm2_rx_de-skew",
|
||||
"cs0_dm2_tx_de-skew",
|
||||
"cs0_dq16_rx_de-skew",
|
||||
"cs0_dq16_tx_de-skew",
|
||||
"cs0_dq17_rx_de-skew",
|
||||
"cs0_dq17_tx_de-skew",
|
||||
"cs0_dq18_rx_de-skew",
|
||||
"cs0_dq18_tx_de-skew",
|
||||
"cs0_dq19_rx_de-skew",
|
||||
"cs0_dq19_tx_de-skew",
|
||||
"cs0_dq20_rx_de-skew",
|
||||
"cs0_dq20_tx_de-skew",
|
||||
"cs0_dq21_rx_de-skew",
|
||||
"cs0_dq21_tx_de-skew",
|
||||
"cs0_dq22_rx_de-skew",
|
||||
"cs0_dq22_tx_de-skew",
|
||||
"cs0_dq23_rx_de-skew",
|
||||
"cs0_dq23_tx_de-skew",
|
||||
"cs0_dqs2_rx_de-skew",
|
||||
"cs0_dqs2p_tx_de-skew",
|
||||
"cs0_dqs2n_tx_de-skew",
|
||||
|
||||
"cs0_dm3_rx_de-skew",
|
||||
"cs0_dm3_tx_de-skew",
|
||||
"cs0_dq24_rx_de-skew",
|
||||
"cs0_dq24_tx_de-skew",
|
||||
"cs0_dq25_rx_de-skew",
|
||||
"cs0_dq25_tx_de-skew",
|
||||
"cs0_dq26_rx_de-skew",
|
||||
"cs0_dq26_tx_de-skew",
|
||||
"cs0_dq27_rx_de-skew",
|
||||
"cs0_dq27_tx_de-skew",
|
||||
"cs0_dq28_rx_de-skew",
|
||||
"cs0_dq28_tx_de-skew",
|
||||
"cs0_dq29_rx_de-skew",
|
||||
"cs0_dq29_tx_de-skew",
|
||||
"cs0_dq30_rx_de-skew",
|
||||
"cs0_dq30_tx_de-skew",
|
||||
"cs0_dq31_rx_de-skew",
|
||||
"cs0_dq31_tx_de-skew",
|
||||
"cs0_dqs3_rx_de-skew",
|
||||
"cs0_dqs3p_tx_de-skew",
|
||||
"cs0_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs1_timing[] = {
|
||||
"cs1_dm0_rx_de-skew",
|
||||
"cs1_dm0_tx_de-skew",
|
||||
"cs1_dq0_rx_de-skew",
|
||||
"cs1_dq0_tx_de-skew",
|
||||
"cs1_dq1_rx_de-skew",
|
||||
"cs1_dq1_tx_de-skew",
|
||||
"cs1_dq2_rx_de-skew",
|
||||
"cs1_dq2_tx_de-skew",
|
||||
"cs1_dq3_rx_de-skew",
|
||||
"cs1_dq3_tx_de-skew",
|
||||
"cs1_dq4_rx_de-skew",
|
||||
"cs1_dq4_tx_de-skew",
|
||||
"cs1_dq5_rx_de-skew",
|
||||
"cs1_dq5_tx_de-skew",
|
||||
"cs1_dq6_rx_de-skew",
|
||||
"cs1_dq6_tx_de-skew",
|
||||
"cs1_dq7_rx_de-skew",
|
||||
"cs1_dq7_tx_de-skew",
|
||||
"cs1_dqs0_rx_de-skew",
|
||||
"cs1_dqs0p_tx_de-skew",
|
||||
"cs1_dqs0n_tx_de-skew",
|
||||
|
||||
"cs1_dm1_rx_de-skew",
|
||||
"cs1_dm1_tx_de-skew",
|
||||
"cs1_dq8_rx_de-skew",
|
||||
"cs1_dq8_tx_de-skew",
|
||||
"cs1_dq9_rx_de-skew",
|
||||
"cs1_dq9_tx_de-skew",
|
||||
"cs1_dq10_rx_de-skew",
|
||||
"cs1_dq10_tx_de-skew",
|
||||
"cs1_dq11_rx_de-skew",
|
||||
"cs1_dq11_tx_de-skew",
|
||||
"cs1_dq12_rx_de-skew",
|
||||
"cs1_dq12_tx_de-skew",
|
||||
"cs1_dq13_rx_de-skew",
|
||||
"cs1_dq13_tx_de-skew",
|
||||
"cs1_dq14_rx_de-skew",
|
||||
"cs1_dq14_tx_de-skew",
|
||||
"cs1_dq15_rx_de-skew",
|
||||
"cs1_dq15_tx_de-skew",
|
||||
"cs1_dqs1_rx_de-skew",
|
||||
"cs1_dqs1p_tx_de-skew",
|
||||
"cs1_dqs1n_tx_de-skew",
|
||||
|
||||
"cs1_dm2_rx_de-skew",
|
||||
"cs1_dm2_tx_de-skew",
|
||||
"cs1_dq16_rx_de-skew",
|
||||
"cs1_dq16_tx_de-skew",
|
||||
"cs1_dq17_rx_de-skew",
|
||||
"cs1_dq17_tx_de-skew",
|
||||
"cs1_dq18_rx_de-skew",
|
||||
"cs1_dq18_tx_de-skew",
|
||||
"cs1_dq19_rx_de-skew",
|
||||
"cs1_dq19_tx_de-skew",
|
||||
"cs1_dq20_rx_de-skew",
|
||||
"cs1_dq20_tx_de-skew",
|
||||
"cs1_dq21_rx_de-skew",
|
||||
"cs1_dq21_tx_de-skew",
|
||||
"cs1_dq22_rx_de-skew",
|
||||
"cs1_dq22_tx_de-skew",
|
||||
"cs1_dq23_rx_de-skew",
|
||||
"cs1_dq23_tx_de-skew",
|
||||
"cs1_dqs2_rx_de-skew",
|
||||
"cs1_dqs2p_tx_de-skew",
|
||||
"cs1_dqs2n_tx_de-skew",
|
||||
|
||||
"cs1_dm3_rx_de-skew",
|
||||
"cs1_dm3_tx_de-skew",
|
||||
"cs1_dq24_rx_de-skew",
|
||||
"cs1_dq24_tx_de-skew",
|
||||
"cs1_dq25_rx_de-skew",
|
||||
"cs1_dq25_tx_de-skew",
|
||||
"cs1_dq26_rx_de-skew",
|
||||
"cs1_dq26_tx_de-skew",
|
||||
"cs1_dq27_rx_de-skew",
|
||||
"cs1_dq27_tx_de-skew",
|
||||
"cs1_dq28_rx_de-skew",
|
||||
"cs1_dq28_tx_de-skew",
|
||||
"cs1_dq29_rx_de-skew",
|
||||
"cs1_dq29_tx_de-skew",
|
||||
"cs1_dq30_rx_de-skew",
|
||||
"cs1_dq30_tx_de-skew",
|
||||
"cs1_dq31_rx_de-skew",
|
||||
"cs1_dq31_tx_de-skew",
|
||||
"cs1_dqs3_rx_de-skew",
|
||||
"cs1_dqs3p_tx_de-skew",
|
||||
"cs1_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
struct rk3328_ddr_dts_config_timing {
|
||||
unsigned int ddr3_speed_bin;
|
||||
unsigned int ddr4_speed_bin;
|
||||
unsigned int pd_idle;
|
||||
unsigned int sr_idle;
|
||||
unsigned int sr_mc_gate_idle;
|
||||
unsigned int srpd_lite_idle;
|
||||
unsigned int standby_idle;
|
||||
|
||||
unsigned int auto_pd_dis_freq;
|
||||
unsigned int auto_sr_dis_freq;
|
||||
/* for ddr3 only */
|
||||
unsigned int ddr3_dll_dis_freq;
|
||||
/* for ddr4 only */
|
||||
unsigned int ddr4_dll_dis_freq;
|
||||
unsigned int phy_dll_dis_freq;
|
||||
|
||||
unsigned int ddr3_odt_dis_freq;
|
||||
unsigned int phy_ddr3_odt_dis_freq;
|
||||
unsigned int ddr3_drv;
|
||||
unsigned int ddr3_odt;
|
||||
unsigned int phy_ddr3_ca_drv;
|
||||
unsigned int phy_ddr3_ck_drv;
|
||||
unsigned int phy_ddr3_dq_drv;
|
||||
unsigned int phy_ddr3_odt;
|
||||
|
||||
unsigned int lpddr3_odt_dis_freq;
|
||||
unsigned int phy_lpddr3_odt_dis_freq;
|
||||
unsigned int lpddr3_drv;
|
||||
unsigned int lpddr3_odt;
|
||||
unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_ck_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int phy_lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
|
||||
unsigned int ddr4_odt_dis_freq;
|
||||
unsigned int phy_ddr4_odt_dis_freq;
|
||||
unsigned int ddr4_drv;
|
||||
unsigned int ddr4_odt;
|
||||
unsigned int phy_ddr4_ca_drv;
|
||||
unsigned int phy_ddr4_ck_drv;
|
||||
unsigned int phy_ddr4_dq_drv;
|
||||
unsigned int phy_ddr4_odt;
|
||||
|
||||
unsigned int ca_skew[15];
|
||||
unsigned int cs0_skew[44];
|
||||
unsigned int cs1_skew[44];
|
||||
|
||||
unsigned int available;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_de_skew_setting {
|
||||
unsigned int ca_de_skew[30];
|
||||
unsigned int cs0_de_skew[84];
|
||||
unsigned int cs1_de_skew[84];
|
||||
};
|
||||
|
||||
struct rk3328_dmcfreq {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
struct clk *dmc_clk;
|
||||
struct devfreq_event_dev *edev;
|
||||
struct mutex lock;
|
||||
struct regulator *vdd_center;
|
||||
unsigned long rate, target_rate;
|
||||
unsigned long volt, target_volt;
|
||||
|
||||
int (*set_auto_self_refresh)(u32 en);
|
||||
};
|
||||
|
||||
static void
|
||||
rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
|
||||
struct rk3328_ddr_dts_config_timing *tim)
|
||||
{
|
||||
u32 n;
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
|
||||
memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
|
||||
memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
|
||||
memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
|
||||
|
||||
/* CA de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
|
||||
offset = n / 2;
|
||||
shift = n % 2;
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->ca_skew[offset] &= ~(0xf << shift);
|
||||
tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS0 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs0_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS1 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs1_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static void of_get_rk3328_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
struct device_node *np_tim;
|
||||
u32 *p;
|
||||
struct rk3328_ddr_dts_config_timing *dts_timing;
|
||||
struct rk3328_ddr_de_skew_setting *de_skew;
|
||||
int ret = 0;
|
||||
u32 i;
|
||||
|
||||
dts_timing =
|
||||
(struct rk3328_ddr_dts_config_timing *)(timing +
|
||||
DTS_PAR_OFFSET / 4);
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (!np_tim) {
|
||||
ret = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
|
||||
if (!de_skew) {
|
||||
ret = -ENOMEM;
|
||||
goto end;
|
||||
}
|
||||
|
||||
p = (u32 *)dts_timing;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->ca_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs0_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs1_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
|
||||
p + i);
|
||||
}
|
||||
if (!ret)
|
||||
rk3328_de_skew_setting_2_register(de_skew, dts_timing);
|
||||
|
||||
kfree(de_skew);
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
|
||||
ddr_psci_param->sr_idle_en = en;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
return res.a0;
|
||||
}
|
||||
|
||||
static int rk3328_dmc_init(struct platform_device *pdev,
|
||||
struct rk3328_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size, page_num;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 || (res.a1 < 0x101)) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk3328_ddr_dts_config_timing);
|
||||
page_num = DIV_ROUND_UP(size, 4096) + 1;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
page_num, SHARE_PAGE_TYPE_DDR, 0,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ddr_psci_param = ioremap(res.a1, page_num << 12);
|
||||
of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long target_volt, target_rate;
|
||||
int err;
|
||||
|
||||
opp = devfreq_recommended_opp(dev, freq, flags);
|
||||
if (IS_ERR(opp))
|
||||
return PTR_ERR(opp);
|
||||
|
||||
target_rate = dev_pm_opp_get_freq(opp);
|
||||
target_volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (dmcfreq->rate == target_rate)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dmcfreq->lock);
|
||||
|
||||
/*
|
||||
* If frequency scaling from low to high, adjust voltage first.
|
||||
* If frequency scaling from high to low, adjust frequency first.
|
||||
*/
|
||||
if (old_clk_rate < target_rate) {
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n",
|
||||
target_volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
|
||||
err);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check the dpll rate,
|
||||
* There only two result we will get,
|
||||
* 1. Ddr frequency scaling fail, we still get the old rate.
|
||||
* 2. Ddr frequency scaling sucessful, we get the rate we set.
|
||||
*/
|
||||
dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
|
||||
|
||||
/* If get the incorrect rate, set voltage to old value. */
|
||||
if (dmcfreq->rate != target_rate) {
|
||||
dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
|
||||
target_rate, dmcfreq->rate);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
} else if (old_clk_rate > target_rate)
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err)
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
|
||||
|
||||
dmcfreq->rate = target_rate;
|
||||
dmcfreq->volt = target_volt;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dmcfreq->lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_dev_status(struct device *dev,
|
||||
struct devfreq_dev_status *stat)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct devfreq_event_data edata;
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_get_event(dmcfreq->edev, &edata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
stat->current_frequency = dmcfreq->rate;
|
||||
stat->busy_time = edata.load_count;
|
||||
stat->total_time = edata.total_count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
|
||||
*freq = dmcfreq->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {
|
||||
.polling_ms = 200,
|
||||
.target = rk3328_dmcfreq_target,
|
||||
.get_dev_status = rk3328_dmcfreq_get_dev_status,
|
||||
.get_cur_freq = rk3328_dmcfreq_get_cur_freq,
|
||||
};
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_disable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to disable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_suspend_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to suspend the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_enable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_resume_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to resume the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,
|
||||
rk3328_dmcfreq_resume);
|
||||
|
||||
static int rk3328_dmcfreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rk3328_dmcfreq *data;
|
||||
struct dev_pm_opp *opp;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&data->lock);
|
||||
|
||||
data->vdd_center = devm_regulator_get(dev, "center");
|
||||
if (IS_ERR(data->vdd_center)) {
|
||||
if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the regulator \"center\"\n");
|
||||
return PTR_ERR(data->vdd_center);
|
||||
}
|
||||
|
||||
data->dmc_clk = devm_clk_get(dev, "dmc_clk");
|
||||
if (IS_ERR(data->dmc_clk)) {
|
||||
if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->dmc_clk);
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
|
||||
#else
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
|
||||
#endif
|
||||
if (IS_ERR(data->edev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = devfreq_event_enable_edev(data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rk3328_dmc_init(pdev, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* We add a devfreq driver to our parent since it has a device tree node
|
||||
* with operating points.
|
||||
*/
|
||||
if (dev_pm_opp_of_add_table(dev)) {
|
||||
dev_err(dev, "Invalid operating-points in device tree.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "upthreshold",
|
||||
&data->ondemand_data.upthreshold);
|
||||
of_property_read_u32(np, "downdifferential",
|
||||
&data->ondemand_data.downdifferential);
|
||||
|
||||
data->rate = clk_get_rate(data->dmc_clk);
|
||||
|
||||
opp = devfreq_recommended_opp(dev, &data->rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
ret = PTR_ERR(opp);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
data->rate = dev_pm_opp_get_freq(opp);
|
||||
data->volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
rk3328_devfreq_dmc_profile.initial_freq = data->rate;
|
||||
|
||||
data->devfreq = devm_devfreq_add_device(dev,
|
||||
&rk3328_devfreq_dmc_profile,
|
||||
DEVFREQ_GOV_SIMPLE_ONDEMAND,
|
||||
&data->ondemand_data);
|
||||
if (IS_ERR(data->devfreq)) {
|
||||
ret = PTR_ERR(data->devfreq);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
||||
|
||||
data->dev = dev;
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_opp:
|
||||
dev_pm_opp_of_remove_table(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
/*
|
||||
* Before remove the opp table we need to unregister the opp notifier.
|
||||
*/
|
||||
devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
|
||||
dev_pm_opp_of_remove_table(dmcfreq->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk3328dmc_devfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3328-dmc" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);
|
||||
|
||||
static struct platform_driver rk3328_dmcfreq_driver = {
|
||||
.probe = rk3328_dmcfreq_probe,
|
||||
.remove = rk3328_dmcfreq_remove,
|
||||
.driver = {
|
||||
.name = "rk3328-dmc-freq",
|
||||
.pm = &rk3328_dmcfreq_pm,
|
||||
.of_match_table = rk3328dmc_devfreq_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rk3328_dmcfreq_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework");
|
||||
|
|
@ -0,0 +1,926 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
|
||||
/* pmucru-clocks indices */
|
||||
|
||||
/* pmucru plls */
|
||||
#define PLL_PPLL 1
|
||||
#define PLL_HPLL 2
|
||||
|
||||
/* pmucru clocks */
|
||||
#define XIN_OSC0_DIV 4
|
||||
#define CLK_RTC_32K 5
|
||||
#define CLK_PMU 6
|
||||
#define CLK_I2C0 7
|
||||
#define CLK_RTC32K_FRAC 8
|
||||
#define CLK_UART0_DIV 9
|
||||
#define CLK_UART0_FRAC 10
|
||||
#define SCLK_UART0 11
|
||||
#define DBCLK_GPIO0 12
|
||||
#define CLK_PWM0 13
|
||||
#define CLK_CAPTURE_PWM0_NDFT 14
|
||||
#define CLK_PMUPVTM 15
|
||||
#define CLK_CORE_PMUPVTM 16
|
||||
#define CLK_REF24M 17
|
||||
#define XIN_OSC0_USBPHY0_G 18
|
||||
#define CLK_USBPHY0_REF 19
|
||||
#define XIN_OSC0_USBPHY1_G 20
|
||||
#define CLK_USBPHY1_REF 21
|
||||
#define XIN_OSC0_MIPIDSIPHY0_G 22
|
||||
#define CLK_MIPIDSIPHY0_REF 23
|
||||
#define XIN_OSC0_MIPIDSIPHY1_G 24
|
||||
#define CLK_MIPIDSIPHY1_REF 25
|
||||
#define CLK_WIFI_DIV 26
|
||||
#define CLK_WIFI_OSC0 27
|
||||
#define CLK_WIFI 28
|
||||
#define CLK_PCIEPHY0_DIV 29
|
||||
#define CLK_PCIEPHY0_OSC0 30
|
||||
#define CLK_PCIEPHY0_REF 31
|
||||
#define CLK_PCIEPHY1_DIV 32
|
||||
#define CLK_PCIEPHY1_OSC0 33
|
||||
#define CLK_PCIEPHY1_REF 34
|
||||
#define CLK_PCIEPHY2_DIV 35
|
||||
#define CLK_PCIEPHY2_OSC0 36
|
||||
#define CLK_PCIEPHY2_REF 37
|
||||
#define CLK_PCIE30PHY_REF_M 38
|
||||
#define CLK_PCIE30PHY_REF_N 39
|
||||
#define CLK_HDMI_REF 40
|
||||
#define XIN_OSC0_EDPPHY_G 41
|
||||
#define PCLK_PDPMU 42
|
||||
#define PCLK_PMU 43
|
||||
#define PCLK_UART0 44
|
||||
#define PCLK_I2C0 45
|
||||
#define PCLK_GPIO0 46
|
||||
#define PCLK_PMUPVTM 47
|
||||
#define PCLK_PWM0 48
|
||||
#define CLK_PDPMU 49
|
||||
#define SCLK_32K_IOE 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_VPLL 5
|
||||
#define PLL_NPLL 6
|
||||
|
||||
/* cru clocks */
|
||||
#define CPLL_333M 9
|
||||
#define ARMCLK 10
|
||||
#define USB480M 11
|
||||
#define ACLK_CORE_NIU2BUS 18
|
||||
#define CLK_CORE_PVTM 19
|
||||
#define CLK_CORE_PVTM_CORE 20
|
||||
#define CLK_CORE_PVTPLL 21
|
||||
#define CLK_GPU_SRC 22
|
||||
#define CLK_GPU_PRE_NDFT 23
|
||||
#define CLK_GPU_PRE_MUX 24
|
||||
#define ACLK_GPU_PRE 25
|
||||
#define PCLK_GPU_PRE 26
|
||||
#define CLK_GPU 27
|
||||
#define CLK_GPU_NP5 28
|
||||
#define PCLK_GPU_PVTM 29
|
||||
#define CLK_GPU_PVTM 30
|
||||
#define CLK_GPU_PVTM_CORE 31
|
||||
#define CLK_GPU_PVTPLL 32
|
||||
#define CLK_NPU_SRC 33
|
||||
#define CLK_NPU_PRE_NDFT 34
|
||||
#define CLK_NPU 35
|
||||
#define CLK_NPU_NP5 36
|
||||
#define HCLK_NPU_PRE 37
|
||||
#define PCLK_NPU_PRE 38
|
||||
#define ACLK_NPU_PRE 39
|
||||
#define ACLK_NPU 40
|
||||
#define HCLK_NPU 41
|
||||
#define PCLK_NPU_PVTM 42
|
||||
#define CLK_NPU_PVTM 43
|
||||
#define CLK_NPU_PVTM_CORE 44
|
||||
#define CLK_NPU_PVTPLL 45
|
||||
#define CLK_DDRPHY1X_SRC 46
|
||||
#define CLK_DDRPHY1X_HWFFC_SRC 47
|
||||
#define CLK_DDR1X 48
|
||||
#define CLK_MSCH 49
|
||||
#define CLK24_DDRMON 50
|
||||
#define ACLK_GIC_AUDIO 51
|
||||
#define HCLK_GIC_AUDIO 52
|
||||
#define HCLK_SDMMC_BUFFER 53
|
||||
#define DCLK_SDMMC_BUFFER 54
|
||||
#define ACLK_GIC600 55
|
||||
#define ACLK_SPINLOCK 56
|
||||
#define HCLK_I2S0_8CH 57
|
||||
#define HCLK_I2S1_8CH 58
|
||||
#define HCLK_I2S2_2CH 59
|
||||
#define HCLK_I2S3_2CH 60
|
||||
#define CLK_I2S0_8CH_TX_SRC 61
|
||||
#define CLK_I2S0_8CH_TX_FRAC 62
|
||||
#define MCLK_I2S0_8CH_TX 63
|
||||
#define I2S0_MCLKOUT_TX 64
|
||||
#define CLK_I2S0_8CH_RX_SRC 65
|
||||
#define CLK_I2S0_8CH_RX_FRAC 66
|
||||
#define MCLK_I2S0_8CH_RX 67
|
||||
#define I2S0_MCLKOUT_RX 68
|
||||
#define CLK_I2S1_8CH_TX_SRC 69
|
||||
#define CLK_I2S1_8CH_TX_FRAC 70
|
||||
#define MCLK_I2S1_8CH_TX 71
|
||||
#define I2S1_MCLKOUT_TX 72
|
||||
#define CLK_I2S1_8CH_RX_SRC 73
|
||||
#define CLK_I2S1_8CH_RX_FRAC 74
|
||||
#define MCLK_I2S1_8CH_RX 75
|
||||
#define I2S1_MCLKOUT_RX 76
|
||||
#define CLK_I2S2_2CH_SRC 77
|
||||
#define CLK_I2S2_2CH_FRAC 78
|
||||
#define MCLK_I2S2_2CH 79
|
||||
#define I2S2_MCLKOUT 80
|
||||
#define CLK_I2S3_2CH_TX_SRC 81
|
||||
#define CLK_I2S3_2CH_TX_FRAC 82
|
||||
#define MCLK_I2S3_2CH_TX 83
|
||||
#define I2S3_MCLKOUT_TX 84
|
||||
#define CLK_I2S3_2CH_RX_SRC 85
|
||||
#define CLK_I2S3_2CH_RX_FRAC 86
|
||||
#define MCLK_I2S3_2CH_RX 87
|
||||
#define I2S3_MCLKOUT_RX 88
|
||||
#define HCLK_PDM 89
|
||||
#define MCLK_PDM 90
|
||||
#define HCLK_VAD 91
|
||||
#define HCLK_SPDIF_8CH 92
|
||||
#define MCLK_SPDIF_8CH_SRC 93
|
||||
#define MCLK_SPDIF_8CH_FRAC 94
|
||||
#define MCLK_SPDIF_8CH 95
|
||||
#define HCLK_AUDPWM 96
|
||||
#define SCLK_AUDPWM_SRC 97
|
||||
#define SCLK_AUDPWM_FRAC 98
|
||||
#define SCLK_AUDPWM 99
|
||||
#define HCLK_ACDCDIG 100
|
||||
#define CLK_ACDCDIG_I2C 101
|
||||
#define CLK_ACDCDIG_DAC 102
|
||||
#define CLK_ACDCDIG_ADC 103
|
||||
#define ACLK_SECURE_FLASH 104
|
||||
#define HCLK_SECURE_FLASH 105
|
||||
#define ACLK_CRYPTO_NS 106
|
||||
#define HCLK_CRYPTO_NS 107
|
||||
#define CLK_CRYPTO_NS_CORE 108
|
||||
#define CLK_CRYPTO_NS_PKA 109
|
||||
#define CLK_CRYPTO_NS_RNG 110
|
||||
#define HCLK_TRNG_NS 111
|
||||
#define CLK_TRNG_NS 112
|
||||
#define PCLK_OTPC_NS 113
|
||||
#define CLK_OTPC_NS_SBPI 114
|
||||
#define CLK_OTPC_NS_USR 115
|
||||
#define HCLK_NANDC 116
|
||||
#define NCLK_NANDC 117
|
||||
#define HCLK_SFC 118
|
||||
#define HCLK_SFC_XIP 119
|
||||
#define SCLK_SFC 120
|
||||
#define ACLK_EMMC 121
|
||||
#define HCLK_EMMC 122
|
||||
#define BCLK_EMMC 123
|
||||
#define CCLK_EMMC 124
|
||||
#define TCLK_EMMC 125
|
||||
#define ACLK_PIPE 126
|
||||
#define PCLK_PIPE 127
|
||||
#define PCLK_PIPE_GRF 128
|
||||
#define ACLK_PCIE20_MST 129
|
||||
#define ACLK_PCIE20_SLV 130
|
||||
#define ACLK_PCIE20_DBI 131
|
||||
#define PCLK_PCIE20 132
|
||||
#define CLK_PCIE20_AUX_NDFT 133
|
||||
#define CLK_PCIE20_AUX_DFT 134
|
||||
#define CLK_PCIE20_PIPE_DFT 135
|
||||
#define ACLK_PCIE30X1_MST 136
|
||||
#define ACLK_PCIE30X1_SLV 137
|
||||
#define ACLK_PCIE30X1_DBI 138
|
||||
#define PCLK_PCIE30X1 139
|
||||
#define CLK_PCIE30X1_AUX_NDFT 140
|
||||
#define CLK_PCIE30X1_AUX_DFT 141
|
||||
#define CLK_PCIE30X1_PIPE_DFT 142
|
||||
#define ACLK_PCIE30X2_MST 143
|
||||
#define ACLK_PCIE30X2_SLV 144
|
||||
#define ACLK_PCIE30X2_DBI 145
|
||||
#define PCLK_PCIE30X2 146
|
||||
#define CLK_PCIE30X2_AUX_NDFT 147
|
||||
#define CLK_PCIE30X2_AUX_DFT 148
|
||||
#define CLK_PCIE30X2_PIPE_DFT 149
|
||||
#define ACLK_SATA0 150
|
||||
#define CLK_SATA0_PMALIVE 151
|
||||
#define CLK_SATA0_RXOOB 152
|
||||
#define CLK_SATA0_PIPE_NDFT 153
|
||||
#define CLK_SATA0_PIPE_DFT 154
|
||||
#define ACLK_SATA1 155
|
||||
#define CLK_SATA1_PMALIVE 156
|
||||
#define CLK_SATA1_RXOOB 157
|
||||
#define CLK_SATA1_PIPE_NDFT 158
|
||||
#define CLK_SATA1_PIPE_DFT 159
|
||||
#define ACLK_SATA2 160
|
||||
#define CLK_SATA2_PMALIVE 161
|
||||
#define CLK_SATA2_RXOOB 162
|
||||
#define CLK_SATA2_PIPE_NDFT 163
|
||||
#define CLK_SATA2_PIPE_DFT 164
|
||||
#define ACLK_USB3OTG0 165
|
||||
#define CLK_USB3OTG0_REF 166
|
||||
#define CLK_USB3OTG0_SUSPEND 167
|
||||
#define ACLK_USB3OTG1 168
|
||||
#define CLK_USB3OTG1_REF 169
|
||||
#define CLK_USB3OTG1_SUSPEND 170
|
||||
#define CLK_XPCS_EEE 171
|
||||
#define PCLK_XPCS 172
|
||||
#define ACLK_PHP 173
|
||||
#define HCLK_PHP 174
|
||||
#define PCLK_PHP 175
|
||||
#define HCLK_SDMMC0 176
|
||||
#define CLK_SDMMC0 177
|
||||
#define HCLK_SDMMC1 178
|
||||
#define CLK_SDMMC1 179
|
||||
#define ACLK_GMAC0 180
|
||||
#define PCLK_GMAC0 181
|
||||
#define CLK_MAC0_2TOP 182
|
||||
#define CLK_MAC0_OUT 183
|
||||
#define CLK_MAC0_REFOUT 184
|
||||
#define CLK_GMAC0_PTP_REF 185
|
||||
#define ACLK_USB 186
|
||||
#define HCLK_USB 187
|
||||
#define PCLK_USB 188
|
||||
#define HCLK_USB2HOST0 189
|
||||
#define HCLK_USB2HOST0_ARB 190
|
||||
#define HCLK_USB2HOST1 191
|
||||
#define HCLK_USB2HOST1_ARB 192
|
||||
#define HCLK_SDMMC2 193
|
||||
#define CLK_SDMMC2 194
|
||||
#define ACLK_GMAC1 195
|
||||
#define PCLK_GMAC1 196
|
||||
#define CLK_MAC1_2TOP 197
|
||||
#define CLK_MAC1_OUT 198
|
||||
#define CLK_MAC1_REFOUT 199
|
||||
#define CLK_GMAC1_PTP_REF 200
|
||||
#define ACLK_PERIMID 201
|
||||
#define HCLK_PERIMID 202
|
||||
#define ACLK_VI 203
|
||||
#define HCLK_VI 204
|
||||
#define PCLK_VI 205
|
||||
#define ACLK_VICAP 206
|
||||
#define HCLK_VICAP 207
|
||||
#define DCLK_VICAP 208
|
||||
#define ICLK_VICAP_G 209
|
||||
#define ACLK_ISP 210
|
||||
#define HCLK_ISP 211
|
||||
#define CLK_ISP 212
|
||||
#define PCLK_CSI2HOST1 213
|
||||
#define CLK_CIF_OUT 214
|
||||
#define CLK_CAM0_OUT 215
|
||||
#define CLK_CAM1_OUT 216
|
||||
#define ACLK_VO 217
|
||||
#define HCLK_VO 218
|
||||
#define PCLK_VO 219
|
||||
#define ACLK_VOP_PRE 220
|
||||
#define ACLK_VOP 221
|
||||
#define HCLK_VOP 222
|
||||
#define DCLK_VOP0 223
|
||||
#define DCLK_VOP1 224
|
||||
#define DCLK_VOP2 225
|
||||
#define CLK_VOP_PWM 226
|
||||
#define ACLK_HDCP 227
|
||||
#define HCLK_HDCP 228
|
||||
#define PCLK_HDCP 229
|
||||
#define PCLK_HDMI_HOST 230
|
||||
#define CLK_HDMI_SFR 231
|
||||
#define PCLK_DSITX_0 232
|
||||
#define PCLK_DSITX_1 233
|
||||
#define PCLK_EDP_CTRL 234
|
||||
#define CLK_EDP_200M 235
|
||||
#define ACLK_VPU_PRE 236
|
||||
#define HCLK_VPU_PRE 237
|
||||
#define ACLK_VPU 238
|
||||
#define HCLK_VPU 239
|
||||
#define ACLK_RGA_PRE 240
|
||||
#define HCLK_RGA_PRE 241
|
||||
#define PCLK_RGA_PRE 242
|
||||
#define ACLK_RGA 243
|
||||
#define HCLK_RGA 244
|
||||
#define CLK_RGA_CORE 245
|
||||
#define ACLK_IEP 246
|
||||
#define HCLK_IEP 247
|
||||
#define CLK_IEP_CORE 248
|
||||
#define HCLK_EBC 249
|
||||
#define DCLK_EBC 250
|
||||
#define ACLK_JDEC 251
|
||||
#define HCLK_JDEC 252
|
||||
#define ACLK_JENC 253
|
||||
#define HCLK_JENC 254
|
||||
#define PCLK_EINK 255
|
||||
#define HCLK_EINK 256
|
||||
#define ACLK_RKVENC_PRE 257
|
||||
#define HCLK_RKVENC_PRE 258
|
||||
#define ACLK_RKVENC 259
|
||||
#define HCLK_RKVENC 260
|
||||
#define CLK_RKVENC_CORE 261
|
||||
#define ACLK_RKVDEC_PRE 262
|
||||
#define HCLK_RKVDEC_PRE 263
|
||||
#define ACLK_RKVDEC 264
|
||||
#define HCLK_RKVDEC 265
|
||||
#define CLK_RKVDEC_CA 266
|
||||
#define CLK_RKVDEC_CORE 267
|
||||
#define CLK_RKVDEC_HEVC_CA 268
|
||||
#define ACLK_BUS 269
|
||||
#define PCLK_BUS 270
|
||||
#define PCLK_TSADC 271
|
||||
#define CLK_TSADC_TSEN 272
|
||||
#define CLK_TSADC 273
|
||||
#define PCLK_SARADC 274
|
||||
#define CLK_SARADC 275
|
||||
#define PCLK_SCR 276
|
||||
#define PCLK_WDT_NS 277
|
||||
#define TCLK_WDT_NS 278
|
||||
#define ACLK_DMAC0 279
|
||||
#define ACLK_DMAC1 280
|
||||
#define ACLK_MCU 281
|
||||
#define PCLK_INTMUX 282
|
||||
#define PCLK_MAILBOX 283
|
||||
#define PCLK_UART1 284
|
||||
#define CLK_UART1_SRC 285
|
||||
#define CLK_UART1_FRAC 286
|
||||
#define SCLK_UART1 287
|
||||
#define PCLK_UART2 288
|
||||
#define CLK_UART2_SRC 289
|
||||
#define CLK_UART2_FRAC 290
|
||||
#define SCLK_UART2 291
|
||||
#define PCLK_UART3 292
|
||||
#define CLK_UART3_SRC 293
|
||||
#define CLK_UART3_FRAC 294
|
||||
#define SCLK_UART3 295
|
||||
#define PCLK_UART4 296
|
||||
#define CLK_UART4_SRC 297
|
||||
#define CLK_UART4_FRAC 298
|
||||
#define SCLK_UART4 299
|
||||
#define PCLK_UART5 300
|
||||
#define CLK_UART5_SRC 301
|
||||
#define CLK_UART5_FRAC 302
|
||||
#define SCLK_UART5 303
|
||||
#define PCLK_UART6 304
|
||||
#define CLK_UART6_SRC 305
|
||||
#define CLK_UART6_FRAC 306
|
||||
#define SCLK_UART6 307
|
||||
#define PCLK_UART7 308
|
||||
#define CLK_UART7_SRC 309
|
||||
#define CLK_UART7_FRAC 310
|
||||
#define SCLK_UART7 311
|
||||
#define PCLK_UART8 312
|
||||
#define CLK_UART8_SRC 313
|
||||
#define CLK_UART8_FRAC 314
|
||||
#define SCLK_UART8 315
|
||||
#define PCLK_UART9 316
|
||||
#define CLK_UART9_SRC 317
|
||||
#define CLK_UART9_FRAC 318
|
||||
#define SCLK_UART9 319
|
||||
#define PCLK_CAN0 320
|
||||
#define CLK_CAN0 321
|
||||
#define PCLK_CAN1 322
|
||||
#define CLK_CAN1 323
|
||||
#define PCLK_CAN2 324
|
||||
#define CLK_CAN2 325
|
||||
#define CLK_I2C 326
|
||||
#define PCLK_I2C1 327
|
||||
#define CLK_I2C1 328
|
||||
#define PCLK_I2C2 329
|
||||
#define CLK_I2C2 330
|
||||
#define PCLK_I2C3 331
|
||||
#define CLK_I2C3 332
|
||||
#define PCLK_I2C4 333
|
||||
#define CLK_I2C4 334
|
||||
#define PCLK_I2C5 335
|
||||
#define CLK_I2C5 336
|
||||
#define PCLK_SPI0 337
|
||||
#define CLK_SPI0 338
|
||||
#define PCLK_SPI1 339
|
||||
#define CLK_SPI1 340
|
||||
#define PCLK_SPI2 341
|
||||
#define CLK_SPI2 342
|
||||
#define PCLK_SPI3 343
|
||||
#define CLK_SPI3 344
|
||||
#define PCLK_PWM1 345
|
||||
#define CLK_PWM1 346
|
||||
#define CLK_PWM1_CAPTURE 347
|
||||
#define PCLK_PWM2 348
|
||||
#define CLK_PWM2 349
|
||||
#define CLK_PWM2_CAPTURE 350
|
||||
#define PCLK_PWM3 351
|
||||
#define CLK_PWM3 352
|
||||
#define CLK_PWM3_CAPTURE 353
|
||||
#define DBCLK_GPIO 354
|
||||
#define PCLK_GPIO1 355
|
||||
#define DBCLK_GPIO1 356
|
||||
#define PCLK_GPIO2 357
|
||||
#define DBCLK_GPIO2 358
|
||||
#define PCLK_GPIO3 359
|
||||
#define DBCLK_GPIO3 360
|
||||
#define PCLK_GPIO4 361
|
||||
#define DBCLK_GPIO4 362
|
||||
#define OCC_SCAN_CLK_GPIO 363
|
||||
#define PCLK_TIMER 364
|
||||
#define CLK_TIMER0 365
|
||||
#define CLK_TIMER1 366
|
||||
#define CLK_TIMER2 367
|
||||
#define CLK_TIMER3 368
|
||||
#define CLK_TIMER4 369
|
||||
#define CLK_TIMER5 370
|
||||
#define ACLK_TOP_HIGH 371
|
||||
#define ACLK_TOP_LOW 372
|
||||
#define HCLK_TOP 373
|
||||
#define PCLK_TOP 374
|
||||
#define PCLK_PCIE30PHY 375
|
||||
#define CLK_OPTC_ARB 376
|
||||
#define PCLK_MIPICSIPHY 377
|
||||
#define PCLK_MIPIDSIPHY0 378
|
||||
#define PCLK_MIPIDSIPHY1 379
|
||||
#define PCLK_PIPEPHY0 380
|
||||
#define PCLK_PIPEPHY1 381
|
||||
#define PCLK_PIPEPHY2 382
|
||||
#define PCLK_CPU_BOOST 383
|
||||
#define CLK_CPU_BOOST 384
|
||||
#define PCLK_OTPPHY 385
|
||||
#define SCLK_GMAC0 386
|
||||
#define SCLK_GMAC0_RGMII_SPEED 387
|
||||
#define SCLK_GMAC0_RMII_SPEED 388
|
||||
#define SCLK_GMAC0_RX_TX 389
|
||||
#define SCLK_GMAC1 390
|
||||
#define SCLK_GMAC1_RGMII_SPEED 391
|
||||
#define SCLK_GMAC1_RMII_SPEED 392
|
||||
#define SCLK_GMAC1_RX_TX 393
|
||||
#define SCLK_SDMMC0_DRV 394
|
||||
#define SCLK_SDMMC0_SAMPLE 395
|
||||
#define SCLK_SDMMC1_DRV 396
|
||||
#define SCLK_SDMMC1_SAMPLE 397
|
||||
#define SCLK_SDMMC2_DRV 398
|
||||
#define SCLK_SDMMC2_SAMPLE 399
|
||||
#define SCLK_EMMC_DRV 400
|
||||
#define SCLK_EMMC_SAMPLE 401
|
||||
#define PCLK_EDPPHY_GRF 402
|
||||
#define CLK_HDMI_CEC 403
|
||||
#define CLK_I2S0_8CH_TX 404
|
||||
#define CLK_I2S0_8CH_RX 405
|
||||
#define CLK_I2S1_8CH_TX 406
|
||||
#define CLK_I2S1_8CH_RX 407
|
||||
#define CLK_I2S2_2CH 408
|
||||
#define CLK_I2S3_2CH_TX 409
|
||||
#define CLK_I2S3_2CH_RX 410
|
||||
#define CPLL_500M 411
|
||||
#define CPLL_250M 412
|
||||
#define CPLL_125M 413
|
||||
#define CPLL_62P5M 414
|
||||
#define CPLL_50M 415
|
||||
#define CPLL_25M 416
|
||||
#define CPLL_100M 417
|
||||
#define SCLK_DDRCLK 418
|
||||
|
||||
#define PCLK_CORE_PVTM 450
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
|
||||
|
||||
/* pmu soft-reset indices */
|
||||
/* pmucru_softrst_con0 */
|
||||
#define SRST_P_PDPMU_NIU 0
|
||||
#define SRST_P_PMUCRU 1
|
||||
#define SRST_P_PMUGRF 2
|
||||
#define SRST_P_I2C0 3
|
||||
#define SRST_I2C0 4
|
||||
#define SRST_P_UART0 5
|
||||
#define SRST_S_UART0 6
|
||||
#define SRST_P_PWM0 7
|
||||
#define SRST_PWM0 8
|
||||
#define SRST_P_GPIO0 9
|
||||
#define SRST_GPIO0 10
|
||||
#define SRST_P_PMUPVTM 11
|
||||
#define SRST_PMUPVTM 12
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
#define SRST_NCORERESET0 0
|
||||
#define SRST_NCORERESET1 1
|
||||
#define SRST_NCORERESET2 2
|
||||
#define SRST_NCORERESET3 3
|
||||
#define SRST_NCPUPORESET0 4
|
||||
#define SRST_NCPUPORESET1 5
|
||||
#define SRST_NCPUPORESET2 6
|
||||
#define SRST_NCPUPORESET3 7
|
||||
#define SRST_NSRESET 8
|
||||
#define SRST_NSPORESET 9
|
||||
#define SRST_NATRESET 10
|
||||
#define SRST_NGICRESET 11
|
||||
#define SRST_NPRESET 12
|
||||
#define SRST_NPERIPHRESET 13
|
||||
|
||||
/* cru_softrst_con1 */
|
||||
#define SRST_A_CORE_NIU2DDR 16
|
||||
#define SRST_A_CORE_NIU2BUS 17
|
||||
#define SRST_P_DBG_NIU 18
|
||||
#define SRST_P_DBG 19
|
||||
#define SRST_P_DBG_DAPLITE 20
|
||||
#define SRST_DAP 21
|
||||
#define SRST_A_ADB400_CORE2GIC 22
|
||||
#define SRST_A_ADB400_GIC2CORE 23
|
||||
#define SRST_P_CORE_GRF 24
|
||||
#define SRST_P_CORE_PVTM 25
|
||||
#define SRST_CORE_PVTM 26
|
||||
#define SRST_CORE_PVTPLL 27
|
||||
|
||||
/* cru_softrst_con2 */
|
||||
#define SRST_GPU 32
|
||||
#define SRST_A_GPU_NIU 33
|
||||
#define SRST_P_GPU_NIU 34
|
||||
#define SRST_P_GPU_PVTM 35
|
||||
#define SRST_GPU_PVTM 36
|
||||
#define SRST_GPU_PVTPLL 37
|
||||
#define SRST_A_NPU_NIU 40
|
||||
#define SRST_H_NPU_NIU 41
|
||||
#define SRST_P_NPU_NIU 42
|
||||
#define SRST_A_NPU 43
|
||||
#define SRST_H_NPU 44
|
||||
#define SRST_P_NPU_PVTM 45
|
||||
#define SRST_NPU_PVTM 46
|
||||
#define SRST_NPU_PVTPLL 47
|
||||
|
||||
/* cru_softrst_con3 */
|
||||
#define SRST_A_MSCH 51
|
||||
#define SRST_HWFFC_CTRL 52
|
||||
#define SRST_DDR_ALWAYSON 53
|
||||
#define SRST_A_DDRSPLIT 54
|
||||
#define SRST_DDRDFI_CTL 55
|
||||
#define SRST_A_DMA2DDR 57
|
||||
|
||||
/* cru_softrst_con4 */
|
||||
#define SRST_A_PERIMID_NIU 64
|
||||
#define SRST_H_PERIMID_NIU 65
|
||||
#define SRST_A_GIC_AUDIO_NIU 66
|
||||
#define SRST_H_GIC_AUDIO_NIU 67
|
||||
#define SRST_A_GIC600 68
|
||||
#define SRST_A_GIC600_DEBUG 69
|
||||
#define SRST_A_GICADB_CORE2GIC 70
|
||||
#define SRST_A_GICADB_GIC2CORE 71
|
||||
#define SRST_A_SPINLOCK 72
|
||||
#define SRST_H_SDMMC_BUFFER 73
|
||||
#define SRST_D_SDMMC_BUFFER 74
|
||||
#define SRST_H_I2S0_8CH 75
|
||||
#define SRST_H_I2S1_8CH 76
|
||||
#define SRST_H_I2S2_2CH 77
|
||||
#define SRST_H_I2S3_2CH 78
|
||||
|
||||
/* cru_softrst_con5 */
|
||||
#define SRST_M_I2S0_8CH_TX 80
|
||||
#define SRST_M_I2S0_8CH_RX 81
|
||||
#define SRST_M_I2S1_8CH_TX 82
|
||||
#define SRST_M_I2S1_8CH_RX 83
|
||||
#define SRST_M_I2S2_2CH 84
|
||||
#define SRST_M_I2S3_2CH_TX 85
|
||||
#define SRST_M_I2S3_2CH_RX 86
|
||||
#define SRST_H_PDM 87
|
||||
#define SRST_M_PDM 88
|
||||
#define SRST_H_VAD 89
|
||||
#define SRST_H_SPDIF_8CH 90
|
||||
#define SRST_M_SPDIF_8CH 91
|
||||
#define SRST_H_AUDPWM 92
|
||||
#define SRST_S_AUDPWM 93
|
||||
#define SRST_H_ACDCDIG 94
|
||||
#define SRST_ACDCDIG 95
|
||||
|
||||
/* cru_softrst_con6 */
|
||||
#define SRST_A_SECURE_FLASH_NIU 96
|
||||
#define SRST_H_SECURE_FLASH_NIU 97
|
||||
#define SRST_A_CRYPTO_NS 103
|
||||
#define SRST_H_CRYPTO_NS 104
|
||||
#define SRST_CRYPTO_NS_CORE 105
|
||||
#define SRST_CRYPTO_NS_PKA 106
|
||||
#define SRST_CRYPTO_NS_RNG 107
|
||||
#define SRST_H_TRNG_NS 108
|
||||
#define SRST_TRNG_NS 109
|
||||
|
||||
/* cru_softrst_con7 */
|
||||
#define SRST_H_NANDC 112
|
||||
#define SRST_N_NANDC 113
|
||||
#define SRST_H_SFC 114
|
||||
#define SRST_H_SFC_XIP 115
|
||||
#define SRST_S_SFC 116
|
||||
#define SRST_A_EMMC 117
|
||||
#define SRST_H_EMMC 118
|
||||
#define SRST_B_EMMC 119
|
||||
#define SRST_C_EMMC 120
|
||||
#define SRST_T_EMMC 121
|
||||
|
||||
/* cru_softrst_con8 */
|
||||
#define SRST_A_PIPE_NIU 128
|
||||
#define SRST_P_PIPE_NIU 130
|
||||
#define SRST_P_PIPE_GRF 133
|
||||
#define SRST_A_SATA0 134
|
||||
#define SRST_SATA0_PIPE 135
|
||||
#define SRST_SATA0_PMALIVE 136
|
||||
#define SRST_SATA0_RXOOB 137
|
||||
#define SRST_A_SATA1 138
|
||||
#define SRST_SATA1_PIPE 139
|
||||
#define SRST_SATA1_PMALIVE 140
|
||||
#define SRST_SATA1_RXOOB 141
|
||||
|
||||
/* cru_softrst_con9 */
|
||||
#define SRST_A_SATA2 144
|
||||
#define SRST_SATA2_PIPE 145
|
||||
#define SRST_SATA2_PMALIVE 146
|
||||
#define SRST_SATA2_RXOOB 147
|
||||
#define SRST_USB3OTG0 148
|
||||
#define SRST_USB3OTG1 149
|
||||
#define SRST_XPCS 150
|
||||
#define SRST_XPCS_TX_DIV10 151
|
||||
#define SRST_XPCS_RX_DIV10 152
|
||||
#define SRST_XPCS_XGXS_RX 153
|
||||
|
||||
/* cru_softrst_con10 */
|
||||
#define SRST_P_PCIE20 160
|
||||
#define SRST_PCIE20_POWERUP 161
|
||||
#define SRST_MSTR_ARESET_PCIE20 162
|
||||
#define SRST_SLV_ARESET_PCIE20 163
|
||||
#define SRST_DBI_ARESET_PCIE20 164
|
||||
#define SRST_BRESET_PCIE20 165
|
||||
#define SRST_PERST_PCIE20 166
|
||||
#define SRST_CORE_RST_PCIE20 167
|
||||
#define SRST_NSTICKY_RST_PCIE20 168
|
||||
#define SRST_STICKY_RST_PCIE20 169
|
||||
#define SRST_PWR_RST_PCIE20 170
|
||||
|
||||
/* cru_softrst_con11 */
|
||||
#define SRST_P_PCIE30X1 176
|
||||
#define SRST_PCIE30X1_POWERUP 177
|
||||
#define SRST_M_ARESET_PCIE30X1 178
|
||||
#define SRST_S_ARESET_PCIE30X1 179
|
||||
#define SRST_D_ARESET_PCIE30X1 180
|
||||
#define SRST_BRESET_PCIE30X1 181
|
||||
#define SRST_PERST_PCIE30X1 182
|
||||
#define SRST_CORE_RST_PCIE30X1 183
|
||||
#define SRST_NSTC_RST_PCIE30X1 184
|
||||
#define SRST_STC_RST_PCIE30X1 185
|
||||
#define SRST_PWR_RST_PCIE30X1 186
|
||||
|
||||
/* cru_softrst_con12 */
|
||||
#define SRST_P_PCIE30X2 192
|
||||
#define SRST_PCIE30X2_POWERUP 193
|
||||
#define SRST_M_ARESET_PCIE30X2 194
|
||||
#define SRST_S_ARESET_PCIE30X2 195
|
||||
#define SRST_D_ARESET_PCIE30X2 196
|
||||
#define SRST_BRESET_PCIE30X2 197
|
||||
#define SRST_PERST_PCIE30X2 198
|
||||
#define SRST_CORE_RST_PCIE30X2 199
|
||||
#define SRST_NSTC_RST_PCIE30X2 200
|
||||
#define SRST_STC_RST_PCIE30X2 201
|
||||
#define SRST_PWR_RST_PCIE30X2 202
|
||||
|
||||
/* cru_softrst_con13 */
|
||||
#define SRST_A_PHP_NIU 208
|
||||
#define SRST_H_PHP_NIU 209
|
||||
#define SRST_P_PHP_NIU 210
|
||||
#define SRST_H_SDMMC0 211
|
||||
#define SRST_SDMMC0 212
|
||||
#define SRST_H_SDMMC1 213
|
||||
#define SRST_SDMMC1 214
|
||||
#define SRST_A_GMAC0 215
|
||||
#define SRST_GMAC0_TIMESTAMP 216
|
||||
|
||||
/* cru_softrst_con14 */
|
||||
#define SRST_A_USB_NIU 224
|
||||
#define SRST_H_USB_NIU 225
|
||||
#define SRST_P_USB_NIU 226
|
||||
#define SRST_P_USB_GRF 227
|
||||
#define SRST_H_USB2HOST0 228
|
||||
#define SRST_H_USB2HOST0_ARB 229
|
||||
#define SRST_USB2HOST0_UTMI 230
|
||||
#define SRST_H_USB2HOST1 231
|
||||
#define SRST_H_USB2HOST1_ARB 232
|
||||
#define SRST_USB2HOST1_UTMI 233
|
||||
#define SRST_H_SDMMC2 234
|
||||
#define SRST_SDMMC2 235
|
||||
#define SRST_A_GMAC1 236
|
||||
#define SRST_GMAC1_TIMESTAMP 237
|
||||
|
||||
/* cru_softrst_con15 */
|
||||
#define SRST_A_VI_NIU 240
|
||||
#define SRST_H_VI_NIU 241
|
||||
#define SRST_P_VI_NIU 242
|
||||
#define SRST_A_VICAP 247
|
||||
#define SRST_H_VICAP 248
|
||||
#define SRST_D_VICAP 249
|
||||
#define SRST_I_VICAP 250
|
||||
#define SRST_P_VICAP 251
|
||||
#define SRST_H_ISP 252
|
||||
#define SRST_ISP 253
|
||||
#define SRST_P_CSI2HOST1 255
|
||||
|
||||
/* cru_softrst_con16 */
|
||||
#define SRST_A_VO_NIU 256
|
||||
#define SRST_H_VO_NIU 257
|
||||
#define SRST_P_VO_NIU 258
|
||||
#define SRST_A_VOP_NIU 259
|
||||
#define SRST_A_VOP 260
|
||||
#define SRST_H_VOP 261
|
||||
#define SRST_VOP0 262
|
||||
#define SRST_VOP1 263
|
||||
#define SRST_VOP2 264
|
||||
#define SRST_VOP_PWM 265
|
||||
#define SRST_A_HDCP 266
|
||||
#define SRST_H_HDCP 267
|
||||
#define SRST_P_HDCP 268
|
||||
#define SRST_P_HDMI_HOST 270
|
||||
#define SRST_HDMI_HOST 271
|
||||
|
||||
/* cru_softrst_con17 */
|
||||
#define SRST_P_DSITX_0 272
|
||||
#define SRST_P_DSITX_1 273
|
||||
#define SRST_P_EDP_CTRL 274
|
||||
#define SRST_EDP_24M 275
|
||||
#define SRST_A_VPU_NIU 280
|
||||
#define SRST_H_VPU_NIU 281
|
||||
#define SRST_A_VPU 282
|
||||
#define SRST_H_VPU 283
|
||||
#define SRST_H_EINK 286
|
||||
#define SRST_P_EINK 287
|
||||
|
||||
/* cru_softrst_con18 */
|
||||
#define SRST_A_RGA_NIU 288
|
||||
#define SRST_H_RGA_NIU 289
|
||||
#define SRST_P_RGA_NIU 290
|
||||
#define SRST_A_RGA 292
|
||||
#define SRST_H_RGA 293
|
||||
#define SRST_RGA_CORE 294
|
||||
#define SRST_A_IEP 295
|
||||
#define SRST_H_IEP 296
|
||||
#define SRST_IEP_CORE 297
|
||||
#define SRST_H_EBC 298
|
||||
#define SRST_D_EBC 299
|
||||
#define SRST_A_JDEC 300
|
||||
#define SRST_H_JDEC 301
|
||||
#define SRST_A_JENC 302
|
||||
#define SRST_H_JENC 303
|
||||
|
||||
/* cru_softrst_con19 */
|
||||
#define SRST_A_VENC_NIU 304
|
||||
#define SRST_H_VENC_NIU 305
|
||||
#define SRST_A_RKVENC 307
|
||||
#define SRST_H_RKVENC 308
|
||||
#define SRST_RKVENC_CORE 309
|
||||
|
||||
/* cru_softrst_con20 */
|
||||
#define SRST_A_RKVDEC_NIU 320
|
||||
#define SRST_H_RKVDEC_NIU 321
|
||||
#define SRST_A_RKVDEC 322
|
||||
#define SRST_H_RKVDEC 323
|
||||
#define SRST_RKVDEC_CA 324
|
||||
#define SRST_RKVDEC_CORE 325
|
||||
#define SRST_RKVDEC_HEVC_CA 326
|
||||
|
||||
/* cru_softrst_con21 */
|
||||
#define SRST_A_BUS_NIU 336
|
||||
#define SRST_P_BUS_NIU 338
|
||||
#define SRST_P_CAN0 340
|
||||
#define SRST_CAN0 341
|
||||
#define SRST_P_CAN1 342
|
||||
#define SRST_CAN1 343
|
||||
#define SRST_P_CAN2 344
|
||||
#define SRST_CAN2 345
|
||||
#define SRST_P_GPIO1 346
|
||||
#define SRST_GPIO1 347
|
||||
#define SRST_P_GPIO2 348
|
||||
#define SRST_GPIO2 349
|
||||
#define SRST_P_GPIO3 350
|
||||
#define SRST_GPIO3 351
|
||||
|
||||
/* cru_softrst_con22 */
|
||||
#define SRST_P_GPIO4 352
|
||||
#define SRST_GPIO4 353
|
||||
#define SRST_P_I2C1 354
|
||||
#define SRST_I2C1 355
|
||||
#define SRST_P_I2C2 356
|
||||
#define SRST_I2C2 357
|
||||
#define SRST_P_I2C3 358
|
||||
#define SRST_I2C3 359
|
||||
#define SRST_P_I2C4 360
|
||||
#define SRST_I2C4 361
|
||||
#define SRST_P_I2C5 362
|
||||
#define SRST_I2C5 363
|
||||
#define SRST_P_OTPC_NS 364
|
||||
#define SRST_OTPC_NS_SBPI 365
|
||||
#define SRST_OTPC_NS_USR 366
|
||||
|
||||
/* cru_softrst_con23 */
|
||||
#define SRST_P_PWM1 368
|
||||
#define SRST_PWM1 369
|
||||
#define SRST_P_PWM2 370
|
||||
#define SRST_PWM2 371
|
||||
#define SRST_P_PWM3 372
|
||||
#define SRST_PWM3 373
|
||||
#define SRST_P_SPI0 374
|
||||
#define SRST_SPI0 375
|
||||
#define SRST_P_SPI1 376
|
||||
#define SRST_SPI1 377
|
||||
#define SRST_P_SPI2 378
|
||||
#define SRST_SPI2 379
|
||||
#define SRST_P_SPI3 380
|
||||
#define SRST_SPI3 381
|
||||
|
||||
/* cru_softrst_con24 */
|
||||
#define SRST_P_SARADC 384
|
||||
#define SRST_P_TSADC 385
|
||||
#define SRST_TSADC 386
|
||||
#define SRST_P_TIMER 387
|
||||
#define SRST_TIMER0 388
|
||||
#define SRST_TIMER1 389
|
||||
#define SRST_TIMER2 390
|
||||
#define SRST_TIMER3 391
|
||||
#define SRST_TIMER4 392
|
||||
#define SRST_TIMER5 393
|
||||
#define SRST_P_UART1 394
|
||||
#define SRST_S_UART1 395
|
||||
|
||||
/* cru_softrst_con25 */
|
||||
#define SRST_P_UART2 400
|
||||
#define SRST_S_UART2 401
|
||||
#define SRST_P_UART3 402
|
||||
#define SRST_S_UART3 403
|
||||
#define SRST_P_UART4 404
|
||||
#define SRST_S_UART4 405
|
||||
#define SRST_P_UART5 406
|
||||
#define SRST_S_UART5 407
|
||||
#define SRST_P_UART6 408
|
||||
#define SRST_S_UART6 409
|
||||
#define SRST_P_UART7 410
|
||||
#define SRST_S_UART7 411
|
||||
#define SRST_P_UART8 412
|
||||
#define SRST_S_UART8 413
|
||||
#define SRST_P_UART9 414
|
||||
#define SRST_S_UART9 415
|
||||
|
||||
/* cru_softrst_con26 */
|
||||
#define SRST_P_GRF 416
|
||||
#define SRST_P_GRF_VCCIO12 417
|
||||
#define SRST_P_GRF_VCCIO34 418
|
||||
#define SRST_P_GRF_VCCIO567 419
|
||||
#define SRST_P_SCR 420
|
||||
#define SRST_P_WDT_NS 421
|
||||
#define SRST_T_WDT_NS 422
|
||||
#define SRST_P_DFT2APB 423
|
||||
#define SRST_A_MCU 426
|
||||
#define SRST_P_INTMUX 427
|
||||
#define SRST_P_MAILBOX 428
|
||||
|
||||
/* cru_softrst_con27 */
|
||||
#define SRST_A_TOP_HIGH_NIU 432
|
||||
#define SRST_A_TOP_LOW_NIU 433
|
||||
#define SRST_H_TOP_NIU 434
|
||||
#define SRST_P_TOP_NIU 435
|
||||
#define SRST_P_TOP_CRU 438
|
||||
#define SRST_P_DDRPHY 439
|
||||
#define SRST_DDRPHY 440
|
||||
#define SRST_P_MIPICSIPHY 442
|
||||
#define SRST_P_MIPIDSIPHY0 443
|
||||
#define SRST_P_MIPIDSIPHY1 444
|
||||
#define SRST_P_PCIE30PHY 445
|
||||
#define SRST_PCIE30PHY 446
|
||||
#define SRST_P_PCIE30PHY_GRF 447
|
||||
|
||||
/* cru_softrst_con28 */
|
||||
#define SRST_P_APB2ASB_LEFT 448
|
||||
#define SRST_P_APB2ASB_BOTTOM 449
|
||||
#define SRST_P_ASB2APB_LEFT 450
|
||||
#define SRST_P_ASB2APB_BOTTOM 451
|
||||
#define SRST_P_PIPEPHY0 452
|
||||
#define SRST_PIPEPHY0 453
|
||||
#define SRST_P_PIPEPHY1 454
|
||||
#define SRST_PIPEPHY1 455
|
||||
#define SRST_P_PIPEPHY2 456
|
||||
#define SRST_PIPEPHY2 457
|
||||
#define SRST_P_USB2PHY0_GRF 458
|
||||
#define SRST_P_USB2PHY1_GRF 459
|
||||
#define SRST_P_CPU_BOOST 460
|
||||
#define SRST_CPU_BOOST 461
|
||||
#define SRST_P_OTPPHY 462
|
||||
#define SRST_OTPPHY 463
|
||||
|
||||
/* cru_softrst_con29 */
|
||||
#define SRST_USB2PHY0_POR 464
|
||||
#define SRST_USB2PHY0_USB3OTG0 465
|
||||
#define SRST_USB2PHY0_USB3OTG1 466
|
||||
#define SRST_USB2PHY1_POR 467
|
||||
#define SRST_USB2PHY1_USB2HOST0 468
|
||||
#define SRST_USB2PHY1_USB2HOST1 469
|
||||
#define SRST_P_EDPPHY_GRF 470
|
||||
#define SRST_TSADCPHY 471
|
||||
#define SRST_GMAC0_DELAYLINE 472
|
||||
#define SRST_GMAC1_DELAYLINE 473
|
||||
#define SRST_OTPC_ARB 474
|
||||
#define SRST_P_PIPEPHY0_GRF 475
|
||||
#define SRST_P_PIPEPHY1_GRF 476
|
||||
#define SRST_P_PIPEPHY2_GRF 477
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR2_DEFAULT (0)
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3568_PD_CPU_0 0
|
||||
#define RK3568_PD_CPU_1 1
|
||||
#define RK3568_PD_CPU_2 2
|
||||
#define RK3568_PD_CPU_3 3
|
||||
#define RK3568_PD_CORE_ALIVE 4
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3568_PD_PMU 5
|
||||
|
||||
/* VD_NPU */
|
||||
#define RK3568_PD_NPU 6
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3568_PD_GPU 7
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3568_PD_VI 8
|
||||
#define RK3568_PD_VO 9
|
||||
#define RK3568_PD_RGA 10
|
||||
#define RK3568_PD_VPU 11
|
||||
#define RK3568_PD_CENTER 12
|
||||
#define RK3568_PD_RKVDEC 13
|
||||
#define RK3568_PD_RKVENC 14
|
||||
#define RK3568_PD_PIPE 15
|
||||
#define RK3568_PD_LOGIC_ALIVE 16
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue