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mvebu (WRT32X and WRT3200ACM) kernel 4.19 support

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Ycarus 2019-04-22 17:11:36 +02:00
parent 151facd559
commit 33aa6b66c1
28 changed files with 3168 additions and 0 deletions
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43
root/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch Normal file
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@ -0,0 +1,43 @@
From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
From: Tomasz Maciej Nowak <tmn505@gmail.com>
Date: Thu, 14 Jun 2018 14:24:40 +0200
Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
Use DT of_pci_get_max_link_speed() facility to allow specifying link
capability. If none or unspecified value is given it falls back to gen2,
which is default for Armada 3700 SoC.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
---
drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -231,6 +231,8 @@
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
{
+ struct device *dev = &pcie->pdev->dev;
+ struct device_node *node = dev->of_node;
u32 reg;
/* Set to Direct mode */
@@ -264,10 +266,15 @@
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
- /* Set GEN2 */
+ /* Set GEN */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~PCIE_GEN_SEL_MSK;
- reg |= SPEED_GEN_2;
+ if (of_pci_get_max_link_speed(node) == 1)
+ reg |= SPEED_GEN_1;
+ else if (of_pci_get_max_link_speed(node) == 3)
+ reg |= SPEED_GEN_3;
+ else
+ reg |= SPEED_GEN_2;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
/* Set lane X1 */