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Add patches and packages needed for BPI-r2
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Ycarus
parent
b105e79652
commit
3406c7d37b
165 changed files with 241259 additions and 29 deletions
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@ -0,0 +1,187 @@
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From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:29 +0800
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Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712
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mt2701/mt2712 has 12bit clock div, which is not compatible with
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mt8135/mt8173. and, some additional features will be added in
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mt2701/mt2712, so that need distinguish it by comatibale name.
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
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1 file changed, 69 insertions(+), 13 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -95,6 +95,9 @@
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#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
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#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
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#define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
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+#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
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+#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
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+#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
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/* MSDC_IOCON mask */
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#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
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@@ -295,6 +298,10 @@ struct msdc_save_para {
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u32 emmc50_cfg0;
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};
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+struct mtk_mmc_compatible {
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+ u8 clk_div_bits;
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+};
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+
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struct msdc_tune_para {
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u32 iocon;
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u32 pad_tune;
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@@ -309,6 +316,7 @@ struct msdc_delay_phase {
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struct msdc_host {
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struct device *dev;
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+ const struct mtk_mmc_compatible *dev_comp;
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struct mmc_host *mmc; /* mmc structure */
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int cmd_rsp;
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@@ -350,6 +358,31 @@ struct msdc_host {
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struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
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};
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+static const struct mtk_mmc_compatible mt8135_compat = {
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+ .clk_div_bits = 8,
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+};
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+
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+static const struct mtk_mmc_compatible mt8173_compat = {
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+ .clk_div_bits = 8,
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+};
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+
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+static const struct mtk_mmc_compatible mt2701_compat = {
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+ .clk_div_bits = 12,
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+};
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+
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+static const struct mtk_mmc_compatible mt2712_compat = {
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+ .clk_div_bits = 12,
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+};
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+
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+static const struct of_device_id msdc_of_ids[] = {
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+ { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
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+ { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
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+ { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
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+ { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, msdc_of_ids);
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+
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static void sdr_set_bits(void __iomem *reg, u32 bs)
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{
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u32 val = readl(reg);
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@@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc
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timeout = (ns + clk_ns - 1) / clk_ns + clks;
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/* in 1048576 sclk cycle unit */
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timeout = (timeout + (0x1 << 20) - 1) >> 20;
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- sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
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+ if (host->dev_comp->clk_div_bits == 8)
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+ sdr_get_field(host->base + MSDC_CFG,
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+ MSDC_CFG_CKMOD, &mode);
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+ else
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+ sdr_get_field(host->base + MSDC_CFG,
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+ MSDC_CFG_CKMOD_EXTRA, &mode);
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/*DDR mode will double the clk cycles for data timeout */
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timeout = mode >= 2 ? timeout * 2 : timeout;
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timeout = timeout > 1 ? timeout - 1 : 0;
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@@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_ho
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flags = readl(host->base + MSDC_INTEN);
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sdr_clr_bits(host->base + MSDC_INTEN, flags);
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- sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
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+ if (host->dev_comp->clk_div_bits == 8)
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+ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
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+ else
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+ sdr_clr_bits(host->base + MSDC_CFG,
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+ MSDC_CFG_HS400_CK_MODE_EXTRA);
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if (timing == MMC_TIMING_UHS_DDR50 ||
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timing == MMC_TIMING_MMC_DDR52 ||
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timing == MMC_TIMING_MMC_HS400) {
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@@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_ho
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if (timing == MMC_TIMING_MMC_HS400 &&
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hz >= (host->src_clk_freq >> 1)) {
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- sdr_set_bits(host->base + MSDC_CFG,
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- MSDC_CFG_HS400_CK_MODE);
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+ if (host->dev_comp->clk_div_bits == 8)
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+ sdr_set_bits(host->base + MSDC_CFG,
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+ MSDC_CFG_HS400_CK_MODE);
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+ else
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+ sdr_set_bits(host->base + MSDC_CFG,
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+ MSDC_CFG_HS400_CK_MODE_EXTRA);
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sclk = host->src_clk_freq >> 1;
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div = 0; /* div is ignore when bit18 is set */
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}
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@@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_ho
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sclk = (host->src_clk_freq >> 2) / div;
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}
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}
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- sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
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- (mode << 8) | div);
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+ if (host->dev_comp->clk_div_bits == 8)
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+ sdr_set_field(host->base + MSDC_CFG,
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+ MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
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+ (mode << 8) | div);
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+ else
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+ sdr_set_field(host->base + MSDC_CFG,
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+ MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
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+ (mode << 12) | div);
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+
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sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
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while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
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cpu_relax();
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@@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platfor
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struct mmc_host *mmc;
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struct msdc_host *host;
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struct resource *res;
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+ const struct of_device_id *of_id;
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int ret;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "No DT found\n");
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return -EINVAL;
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}
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+
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+ of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
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+ if (!of_id)
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+ return -EINVAL;
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/* Allocate MMC host for this device */
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mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
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if (!mmc)
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@@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platfor
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msdc_of_property_parse(pdev, host);
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host->dev = &pdev->dev;
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+ host->dev_comp = of_id->data;
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host->mmc = mmc;
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host->src_clk_freq = clk_get_rate(host->src_clk);
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/* Set host parameters to mmc */
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mmc->ops = &mt_msdc_ops;
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- mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
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+ if (host->dev_comp->clk_div_bits == 8)
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+ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
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+ else
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+ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
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mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
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/* MMC core transfer sizes tunable parameters */
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@@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_
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SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
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};
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-static const struct of_device_id msdc_of_ids[] = {
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- { .compatible = "mediatek,mt8135-mmc", },
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- {}
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-};
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-MODULE_DEVICE_TABLE(of, msdc_of_ids);
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-
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static struct platform_driver mt_msdc_driver = {
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.probe = msdc_drv_probe,
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.remove = msdc_drv_remove,
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