Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport

2025-03-09 15:40:20 +00:00 · 2023-04-22 08:07:24 +02:00 · 2023-04-22 08:07:24 +02:00 · 46837ec4c0
commit 46837ec4c0
parent e910436a7a
9459 changed files with 362648 additions and 116345 deletions
--- a/5.4/package/Makefile
+++ b/5.4/package/Makefile
@ -0,0 +1,114 @@
+#
+# Copyright (C) 2006-2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+curdir:=package
+
+include $(INCLUDE_DIR)/feeds.mk
+include $(INCLUDE_DIR)/rootfs.mk
+
+-include $(TMP_DIR)/.packagedeps
+package-y += kernel/linux
+$(curdir)/autoremove:=1
+$(curdir)/builddirs:=$(sort $(package-) $(package-y) $(package-m))
+$(curdir)/builddirs-default:=. $(sort $(package-y) $(package-m))
+$(curdir)/builddirs-prereq:=. $(sort $(prereq-y) $(prereq-m))
+ifdef CHECK_ALL
+$(curdir)/builddirs-check:=$($(curdir)/builddirs)
+$(curdir)/builddirs-download:=$($(curdir)/builddirs)
+endif
+ifneq ($(IGNORE_ERRORS),)
+  package-y-filter := $(package-y)
+  package-m-filter := $(filter-out $(package-y),$(package-m))
+  package-n-filter := $(filter-out $(package-y) $(package-m),$(package-))
+  package-ignore-errors := $(filter n m y,$(IGNORE_ERRORS))
+  package-ignore-errors := $(if $(package-ignore-errors),$(package-ignore-errors),n m)
+  package-ignore-subdirs := $(sort $(foreach m,$(package-ignore-errors),$(package-$(m)-filter)))
+  $(curdir)/builddirs-ignore-download := $(package-ignore-subdirs)
+  $(curdir)/builddirs-ignore-compile := $(package-ignore-subdirs)
+  $(curdir)/builddirs-ignore-host-download := $(package-ignore-subdirs)
+  $(curdir)/builddirs-ignore-host-compile := $(package-ignore-subdirs)
+endif
+
+PACKAGE_INSTALL_FILES:= \
+	$(foreach pkg,$(sort $(package-y)), \
+		$(foreach variant, \
+			$(if $(strip $(package/$(pkg)/variants)), \
+				$(package/$(pkg)/variants), \
+				$(if $(package/$(pkg)/default-variant), \
+					$(package/$(pkg)/default-variant), \
+					default \
+				) \
+			), \
+			$(PKG_INFO_DIR)/$(lastword $(subst /,$(space),$(pkg))).$(variant).install \
+		) \
+	)
+
+$(curdir)/cleanup: $(TMP_DIR)/.build
+	rm -rf $(STAGING_DIR_ROOT)
+
+$(curdir)/merge:
+	rm -rf $(PACKAGE_DIR_ALL)
+	mkdir -p $(PACKAGE_DIR_ALL)
+	-$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.ipk),ln -s $(pdir)/*.ipk $(PACKAGE_DIR_ALL);))
+
+$(curdir)/merge-index: $(curdir)/merge
+	(cd $(PACKAGE_DIR_ALL) && $(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages; )
+
+ifndef SDK
+  $(curdir)/compile: $(curdir)/system/opkg/host/compile
+endif
+
+$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(if $(CONFIG_TARGET_PER_DEVICE_ROOTFS),$(curdir)/merge-index)
+	- find $(STAGING_DIR_ROOT) -type d | $(XARGS) chmod 0755
+	rm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)
+	mkdir -p $(TARGET_DIR)/tmp
+	$(file >$(TMP_DIR)/opkg_install_list,\
+	  $(call opkg_package_files,\
+	    $(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg)))))
+	$(call opkg,$(TARGET_DIR)) install $$(cat $(TMP_DIR)/opkg_install_list)
+	@for file in $(PACKAGE_INSTALL_FILES); do \
+		[ -s $$file.flags ] || continue; \
+		for flag in `cat $$file.flags`; do \
+			$(call opkg,$(TARGET_DIR)) flag $$flag `cat $$file`; \
+		done; \
+	done || true
+
+	$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
+
+	$(call prepare_rootfs,$(TARGET_DIR),$(TOPDIR)/files)
+
+$(curdir)/index: FORCE
+	@echo Generating package index...
+	@for d in $(PACKAGE_SUBDIRS); do ( \
+		mkdir -p $$d; \
+		cd $$d || continue; \
+		$(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages.manifest; \
+		grep -vE '^(Maintainer|LicenseFiles|Source|SourceName|Require|SourceDateEpoch)' Packages.manifest > Packages; \
+		case "$$(((64 + $$(stat -L -c%s Packages)) % 128))" in 110|111) \
+			$(call ERROR_MESSAGE,WARNING: Applying padding in $$d/Packages to workaround usign SHA-512 bug!); \
+			{ echo ""; echo ""; } >> Packages;; \
+		esac; \
+		gzip -9nc Packages > Packages.gz; \
+	); done
+ifdef CONFIG_SIGNED_PACKAGES
+	@echo Signing package index...
+	@for d in $(PACKAGE_SUBDIRS); do ( \
+		[ -d $$d ] && \
+			cd $$d || continue; \
+		$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY); \
+	); done
+endif
+
+$(curdir)/flags-install:= -j1
+
+$(eval $(call stampfile,$(curdir),package,prereq,.config))
+$(eval $(call stampfile,$(curdir),package,cleanup,$(TMP_DIR)/.build))
+$(eval $(call stampfile,$(curdir),package,compile,$(TMP_DIR)/.build))
+$(eval $(call stampfile,$(curdir),package,install,$(TMP_DIR)/.build))
+$(eval $(call stampfile,$(curdir),package,check,$(TMP_DIR)/.build))
+
+$(eval $(call subdir,$(curdir)))
--- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile
+++ b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile
@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2022 ImmortalWrt.org
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=arm-trusted-firmware-rockchip-vendor
+PKG_RELEASE:=$(AUTORELEASE)
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
+PKG_SOURCE_DATE:=2022-08-01
+PKG_SOURCE_VERSION:=b0c100f1a260d807df450019774993c761beb79d
+PKG_MIRROR_HASH:=17723ac8f6ec446c759444ee29ba4fe544cebb3785e26d8e10c91c54b9df3f1a
+
+PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
+
+MAKE_PATH:=$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/arm-trusted-firmware-rockchip-vendor
+    SECTION:=boot
+    CATEGORY:=Boot Loaders
+    TITLE:=ARM Trusted Firmware for Rockchip
+endef
+
+define Package/arm-trusted-firmware-rk3328
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3328
+endef
+
+define Package/arm-trusted-firmware-rk3399
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3399
+endef
+
+define Package/arm-trusted-firmware-rk3568
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3568
+endef
+
+define Package/arm-trusted-firmware-rk3588
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3588
+endef
+
+define Build/Configure
+	$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini
+	$(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini
+	$(call Build/Configure/Default)
+endef
+
+define Build/Compile
+	$(CURDIR)/pack-firmware.sh build $(BUILD_VARIANT) '$(PKG_BUILD_DIR)'
+endef
+
+define Build/InstallDev
+	$(CURDIR)/pack-firmware.sh install $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' '$(STAGING_DIR_IMAGE)'
+endef
+
+define Package/arm-trusted-firmware-rk3328/install
+endef
+
+define Package/arm-trusted-firmware-rk3399/install
+endef
+
+define Package/arm-trusted-firmware-rk3568/install
+endef
+
+define Package/arm-trusted-firmware-rk3588/install
+endef
+
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3328))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3399))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3568))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3588))
--- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh
+++ b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh
@ -0,0 +1,60 @@
+#!/bin/bash
+# Copyright (C) 2021 ImmortalWrt.org
+
+ACTION="$1"
+VARIANT="$2"
+PKG_BUILD_DIR="$3"
+STAGING_DIR_IMAGE="$4"
+
+case "$VARIANT" in
+"rk3328")
+	ATF="rk33/rk322xh_bl31_v1.49.elf"
+	DDR="rk33/rk3328_ddr_333MHz_v1.19.bin"
+	LOADER="rk33/rk322xh_miniloader_v2.50.bin"
+	;;
+"rk3399")
+	ATF="rk33/rk3399_bl31_v1.35.elf"
+	DDR="rk33/rk3399_ddr_800MHz_v1.27.bin"
+	LOADER="rk33/rk3399_miniloader_v1.26.bin"
+	;;
+"rk3568")
+	ATF="rk35/rk3568_bl31_v1.28.elf"
+	DDR="rk35/rk3568_ddr_1560MHz_v1.13.bin"
+	;;
+"rk3588")
+	ATF="rk35/rk3588_bl31_v1.27.elf"
+	DDR="rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin"
+	;;
+*)
+	echo -e "Not compatible with your platform: $VARIANT."
+	exit 1
+	;;
+esac
+
+set -x
+if [ "$ACTION" == "build" ]; then
+	case "$VARIANT" in
+	rk33*)
+		"$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
+		cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
+		"$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini"
+		;;
+	esac
+elif [ "$ACTION" == "install" ]; then
+	mkdir -p "$STAGING_DIR_IMAGE"
+	cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/
+	case "$VARIANT" in
+	rk33*)
+		cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/
+		cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/
+		cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/
+		;;
+	rk35*)
+		cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/
+		;;
+	esac
+else
+	echo -e "Unknown operation: $ACTION."
+	exit 1
+fi
+set +x
--- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf
+++ b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf
--- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini
+++ b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini
@ -0,0 +1,15 @@
+[VERSION]
+MAJOR=1
+MINOR=0
+[BL30_OPTION]
+SEC=0
+[BL31_OPTION]
+SEC=1
+PATH=bl31.elf
+ADDR=0x10000
+[BL32_OPTION]
+SEC=0
+[BL33_OPTION]
+SEC=0
+[OUTPUT]
+PATH=$(PKG_BUILD_DIR)/$(VARIANT)-trust.bin
--- a/5.4/package/boot/arm-trusted-firmware-rockchip/Makefile
+++ b/5.4/package/boot/arm-trusted-firmware-rockchip/Makefile
@ -0,0 +1,49 @@
+#
+# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=arm-trusted-firmware-rockchip
+PKG_VERSION:=2.3
+PKG_RELEASE:=1
+
+PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?
+PKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1
+
+PKG_LICENSE:=BSD-3-Clause
+PKG_LICENSE_FILES:=license.md
+
+PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
+
+MAKE_PATH:=$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/arm-trusted-firmware-rockchip
+    SECTION:=boot
+    CATEGORY:=Boot Loaders
+    TITLE:=ARM Trusted Firmware for Rockchip
+    DEPENDS:=@TARGET_rockchip_armv8
+endef
+
+define Build/Prepare
+	$(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE)
+endef
+
+define Build/Compile
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)
+	$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/
+endef
+
+define Package/arm-trusted-firmware-rockchip/install
+endef
+
+$(eval $(call BuildPackage,arm-trusted-firmware-rockchip))
--- a/5.4/package/boot/uboot-rockchip/Makefile
+++ b/5.4/package/boot/uboot-rockchip/Makefile
@ -0,0 +1,304 @@
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_VERSION:=2022.07
+PKG_RELEASE:=$(AUTORELEASE)
+
+PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e
+
+PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+define U-Boot/Default
+  BUILD_TARGET:=rockchip
+  UENV:=default
+  HIDDEN:=1
+endef
+
+
+# RK3328 boards
+
+define U-Boot/nanopi-r2c-rk3328
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R2C
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r2c
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk322xh_bl31_v1.49.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/nanopi-r2s-rk3328
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R2S
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r2s \
+    friendlyarm_nanopi-neo3
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk322xh_bl31_v1.49.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/orangepi-r1-plus-rk3328
+  BUILD_SUBTARGET:=armv8
+  NAME:=Orange Pi R1 Plus
+  BUILD_DEVICES:= \
+    xunlong_orangepi-r1-plus
+  DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk322xh_bl31_v1.49.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/orangepi-r1-plus-lts-rk3328
+  BUILD_SUBTARGET:=armv8
+  NAME:=Orange Pi R1 Plus LTS
+  BUILD_DEVICES:= \
+    xunlong_orangepi-r1-plus-lts
+  DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk322xh_bl31_v1.49.elf
+  USE_RKBIN:=1
+endef
+
+
+# RK3399 boards
+
+define U-Boot/guangmiao-g4c-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=GuangMiao G4C
+  BUILD_DEVICES:= \
+    sharevdi_guangmiao-g4c
+  DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
+  ATF:=rk3399_bl31.elf
+endef
+
+define U-Boot/nanopi-r4s-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R4S
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r4s
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rk3399
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3399_bl31_v1.35.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/nanopi-r4se-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R4SE
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r4se
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r4se-rk3399:arm-trusted-firmware-rk3399
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3399_bl31_v1.35.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/rock-pi-4-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=Rock Pi 4
+  BUILD_DEVICES:= \
+    radxa_rock-pi-4
+  DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
+  ATF:=rk3399_bl31.elf
+endef
+
+define U-Boot/rockpro64-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=RockPro64
+  BUILD_DEVICES:= \
+    pine64_rockpro64
+  DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
+  ATF:=rk3399_bl31.elf
+endef
+
+define U-Boot/rongpin-king3399-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=Rongpin King3399
+  BUILD_DEVICES:= \
+    rongpin_king3399
+  DEPENDS:=+PACKAGE_u-boot-rongpin-king3399-rk3399:arm-trusted-firmware-rk3399
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3399_bl31_v1.35.elf
+  USE_RKBIN:=1
+endef
+
+define U-Boot/rocktech-mpc1903-rk3399
+  BUILD_SUBTARGET:=armv8
+  NAME:=Rocktech MPC1903
+  BUILD_DEVICES:= \
+    rocktech_mpc1903
+  DEPENDS:=+PACKAGE_u-boot-rocktech-mpc1903-rk3399:arm-trusted-firmware-rk3399
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3399_bl31_v1.35.elf
+  USE_RKBIN:=1
+endef
+
+# RK3568 boards
+
+define U-Boot/mrkaio-m68s-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=Mrkaio M68S
+  BUILD_DEVICES:= \
+    ezpro_mrkaio-m68s
+  DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/opc-h68k-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=OPC-H68K Board
+  BUILD_DEVICES:= \
+    hinlink_opc-h66k \
+    hinlink_opc-h68k
+  DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/photonicat-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=Ariaboard Photonicat
+  BUILD_DEVICES:= \
+    ariaboard_photonicat
+  DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/radxa-e25-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=Radxa E25
+  BUILD_DEVICES:= \
+    radxa_e25
+  DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/rock-3a-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=ROCK3 Model A
+  BUILD_DEVICES:= \
+    radxa_rock-3a
+  DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/r66s-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=R66S/R68S
+  BUILD_DEVICES:= \
+    fastrhino_r66s \
+    fastrhino_r68s
+  DEPENDS:=+PACKAGE_u-boot-r66s-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/station-p2-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=StationP2
+  BUILD_DEVICES:= \
+       firefly_station-p2
+  DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/nanopi-r5s-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R5S
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r5s
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+define U-Boot/nanopi-r5c-rk3568
+  BUILD_SUBTARGET:=armv8
+  NAME:=NanoPi R5C
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r5c
+  DEPENDS:=+PACKAGE_u-boot-nanopi-r5c-rk3568:arm-trusted-firmware-rk3568
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3568_bl31_v1.28.elf
+  DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
+UBOOT_TARGETS := \
+  mrkaio-m68s-rk3568 \
+  opc-h68k-rk3568 \
+  photonicat-rk3568 \
+  radxa-e25-rk3568 \
+  rock-3a-rk3568 \
+  r66s-rk3568 \
+  station-p2-rk3568 \
+  guangmiao-g4c-rk3399 \
+  nanopi-r4s-rk3399 \
+  nanopi-r4se-rk3399 \
+  nanopi-r5s-rk3568 \
+  nanopi-r5c-rk3568 \
+  rock-pi-4-rk3399 \
+  rockpro64-rk3399 \
+  rongpin-king3399-rk3399 \
+  rocktech-mpc1903-rk3399 \
+  nanopi-r2c-rk3328 \
+  nanopi-r2s-rk3328 \
+  orangepi-r1-plus-rk3328 \
+  orangepi-r1-plus-lts-rk3328
+
+UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
+
+UBOOT_MAKE_FLAGS += \
+  BL31=$(STAGING_DIR_IMAGE)/$(ATF)
+
+define Build/Configure
+	$(call Build/Configure/U-Boot)
+
+	$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
+	$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
+	echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
+ifneq ($(DDR),)
+	$(CP) $(STAGING_DIR_IMAGE)/$(DDR) $(PKG_BUILD_DIR)/ram_init.bin
+endif
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+ifneq ($(USE_RKBIN),)
+	$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000
+	$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img
+else
+	$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
+	$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
+endif
+endef
+
+define Package/u-boot/install/default
+endef
+
+$(eval $(call BuildPackage/U-Boot))
--- a/5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch
@ -0,0 +1,43 @@
+From 9b92a43a4f5acf4cba14fd9d473b3120688532dc Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 19 Dec 2021 08:10:24 -0500
+Subject: [PATCH 01/11] rockchip: rk3568: add boot device detection
+
+Enable spl to detect which device it was booted from.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
+@@ -7,6 +7,7 @@
+ #include <dm.h>
+ #include <asm/armv8/mmu.h>
+ #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+ #include <asm/arch-rockchip/grf_rk3568.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <dt-bindings/clock/rk3568-cru.h>
+@@ -23,6 +24,7 @@
+ #define SGRF_SOC_CON4			0x10
+ #define EMMC_HPROT_SECURE_CTRL		0x03
+ #define SDMMC0_HPROT_SECURE_CTRL	0x01
+
+ /* PMU_GRF_GPIO0D_IOMUX_L */
+ enum {
+ 	GPIO0D1_SHIFT		= 4,
+@@ -43,6 +45,12 @@ enum {
+ 	UART2_IO_SEL_M0		= 0,
+ };
+ 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
+	[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
+	[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
+};
+
+ static struct mm_region rk3568_mem_map[] = {
+ 	{
+ 		.virt = 0x0UL,
--- a/5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch
@ -0,0 +1,52 @@
+From 09d877cf076cbb67c79054e12bbb7c63a91faa71 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 19 Dec 2021 08:11:56 -0500
+Subject: [PATCH 02/11] rockchip: rk3568: enable automatic power savings
+
+Enable automatic clock gating, solves the 7c temperature difference on
+SoQuartz.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
+@@ -25,6 +25,15 @@
+ #define EMMC_HPROT_SECURE_CTRL		0x03
+ #define SDMMC0_HPROT_SECURE_CTRL	0x01
+ 
+#define PMU_BASE_ADDR		0xfdd90000
+#define PMU_NOC_AUTO_CON0	(0x70)
+#define PMU_NOC_AUTO_CON1	(0x74)
+#define EDP_PHY_GRF_BASE	0xfdcb0000
+#define EDP_PHY_GRF_CON0	(EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10	(EDP_PHY_GRF_BASE + 0x28)
+#define CPU_GRF_BASE		0xfdc30000
+#define GRF_CORE_PVTPLL_CON0	(0x10)
+
+ /* PMU_GRF_GPIO0D_IOMUX_L */
+ enum {
+ 	GPIO0D1_SHIFT		= 4,
+@@ -99,6 +108,20 @@ void board_debug_uart_init(void)
+ int arch_cpu_init(void)
+ {
+ #ifdef CONFIG_SPL_BUILD
+	/*
+	 * When perform idle operation, corresponding clock can
+	 * be opened or gated automatically.
+	 */
+	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+	writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+	/* Disable eDP phy by default */
+	writel(0x00070007, EDP_PHY_GRF_CON10);
+	writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+	/* Set core pvtpll ring length */
+	writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
+ 	/* Set the emmc sdmmc0 to secure */
+ 	rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
+ 		| SDMMC0_HPROT_SECURE_CTRL << 4));
--- a/5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch
@ -0,0 +1,47 @@
+From ddbcec939789d1f7264134b3628ffb649ec88168 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 19 Dec 2021 08:20:33 -0500
+Subject: [PATCH 03/11] Makefile: rockchip: HACK: build rk3568 images
+
+This is a hack to build rk3568 images.
+It seems makefile can't cope with the format mkimage expects for
+multiple file entries, so hack around the situation.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ Makefile | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/Makefile
+++ b/Makefile
+@@ -1047,6 +1047,9 @@ quiet_cmd_mkimage = MKIMAGE $@
+ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ 	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
+ 
+cmd_mkimage_combined = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $(COMBINED_FILE):$< $@ \
+	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
+
+ quiet_cmd_mkfitimage = MKIMAGE $@
+ cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) \
+ 	-f $(U_BOOT_ITS) -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@ \
+@@ -1491,6 +1494,7 @@ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_
+ ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
+ 
+ # TPL + SPL
+ifneq ($(CONFIG_SYS_SOC),$(filter $(CONFIG_SYS_SOC),"rk3568" "rk3566"))
+ ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
+ MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
+ tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
+@@ -1502,6 +1506,12 @@ MKIMAGEFLAGS_idbloader.img = -n $(CONFIG
+ idbloader.img: spl/u-boot-spl.bin FORCE
+ 	$(call if_changed,mkimage)
+ endif
+else
+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
+COMBINED_FILE = ram_init.bin
+idbloader.img: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage_combined)
+endif
+ 
+ ifeq ($(CONFIG_ARM64),y)
+ OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \
--- a/5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch
--- a/5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch
@ -0,0 +1,50 @@
+From 01e8a38985a90043abddc5c5bcd049c74bb29a53 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 19 Dec 2021 18:52:18 -0500
+Subject: [PATCH 05/11] rockchip: rk356x: HACK: fix sdmmc support
+
+HACK: lock mmc0 to initial frequency and disable dw-mmc control of power
+line.
+
+The sdmmc on quartz64-a is powered by the sdmmc0 power line, which is
+active low.
+Even though it is set as a gpio, it still seems to be triggered by the
+dw-mmc driver toggling the power line.
+Downstream fixes this by setting this to "0" instead of "1" using
+kconfigs.
+
+Also, for some reason the controller will only operate at initial
+frequencies.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 4 +++-
+ drivers/mmc/dw_mmc.c                       | 3 ++-
+ 2 files changed, 5 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+@@ -13,8 +13,10 @@
+ };
+ 
+ &sdmmc0 {
+	max-frequency = <400000>;
+	bus-width = <4>;
+ 	u-boot,dm-spl;
+-	status = "okay";
+	u-boot,spl-fifo-mode;
+ };
+ 
+ &uart2 {
+--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
+@@ -529,7 +529,8 @@ static int dwmci_init(struct mmc *mmc)
+ 	if (host->board_init)
+ 		host->board_init(host);
+ 
+-	dwmci_writel(host, DWMCI_PWREN, 1);
+//	dwmci_writel(host, DWMCI_PWREN, 1);
+	dwmci_writel(host, DWMCI_PWREN, 0);
+ 
+ 	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
+ 		debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
--- a/5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch
@ -0,0 +1,214 @@
+From 9f623c0e96fc7c3b5c9b7a81f0a3017c47033ec7 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 19 Dec 2021 18:57:36 -0500
+Subject: [PATCH 06/11] rockchip: rk356x: add quartz64-a board
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/mach-rockchip/rk3568/Kconfig         | 12 ++-
+ board/pine64/quartz64-a-rk3566/Kconfig        | 15 ++++
+ board/pine64/quartz64-a-rk3566/Makefile       |  4 +
+ .../quartz64-a-rk3566/quartz64-a-rk3566.c     |  1 +
+ configs/quartz64-a-rk3566_defconfig           | 77 +++++++++++++++++++
+ include/configs/quartz64-a-rk3566.h           | 14 ++++
+ include/dt-bindings/power/rk3568-power.h      | 32 ++++++++
+ 7 files changed, 154 insertions(+), 1 deletion(-)
+ create mode 100644 board/pine64/quartz64-a-rk3566/Kconfig
+ create mode 100644 board/pine64/quartz64-a-rk3566/Makefile
+ create mode 100644 board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
+ create mode 100644 configs/quartz64-a-rk3566_defconfig
+ create mode 100644 include/configs/quartz64-a-rk3566.h
+ create mode 100644 include/dt-bindings/power/rk3568-power.h
+
+--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
+@@ -1,11 +1,20 @@
+ if ROCKCHIP_RK3568
+ 
+choice
+	prompt "RK3568/RK3566 board select"
+
+ config TARGET_EVB_RK3568
+ 	bool "RK3568 evaluation board"
+-	select BOARD_LATE_INIT
+ 	help
+ 	  RK3568 EVB is a evaluation board for Rockchp RK3568.
+ 
+config TARGET_QUARTZ64_A_RK3566
+	bool "Quartz64 Model A RK3566 development board"
+	help
+	  Quartz64 Model A RK3566 is a development board from Pine64.
+
+endchoice
+
+ config ROCKCHIP_BOOT_MODE_REG
+ 	default 0xfdc20200
+ 
+@@ -19,5 +28,6 @@ config SYS_MALLOC_F_LEN
+ 	default 0x2000
+ 
+ source "board/rockchip/evb_rk3568/Kconfig"
+source "board/pine64/quartz64-a-rk3566/Kconfig"
+ 
+ endif
+--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/Kconfig
+@@ -0,0 +1,15 @@
+if TARGET_QUARTZ64_A_RK3566
+
+config SYS_BOARD
+	default "quartz64-a-rk3566"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "quartz64-a-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/Makefile
+@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= quartz64-a-rk3566.o
+--- /dev/null
+++ b/board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
+@@ -0,0 +1 @@
+// SPDX-License-Identifier: GPL-2.0+
+--- /dev/null
+++ b/configs/quartz64-a-rk3566_defconfig
+@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZ64_A_RK3566=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y
+--- /dev/null
+++ b/include/configs/quartz64-a-rk3566.h
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __QUARTZ64_A_RK3566_H
+#define __QUARTZ64_A_RK3566_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#endif
+--- /dev/null
+++ b/include/dt-bindings/power/rk3568-power.h
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
+#define __DT_BINDINGS_POWER_RK3568_POWER_H__
+
+/* VD_CORE */
+#define RK3568_PD_CPU_0		0
+#define RK3568_PD_CPU_1		1
+#define RK3568_PD_CPU_2		2
+#define RK3568_PD_CPU_3		3
+#define RK3568_PD_CORE_ALIVE	4
+
+/* VD_PMU */
+#define RK3568_PD_PMU		5
+
+/* VD_NPU */
+#define RK3568_PD_NPU		6
+
+/* VD_GPU */
+#define RK3568_PD_GPU		7
+
+/* VD_LOGIC */
+#define RK3568_PD_VI		8
+#define RK3568_PD_VO		9
+#define RK3568_PD_RGA		10
+#define RK3568_PD_VPU		11
+#define RK3568_PD_CENTER	12
+#define RK3568_PD_RKVDEC	13
+#define RK3568_PD_RKVENC	14
+#define RK3568_PD_PIPE		15
+#define RK3568_PD_LOGIC_ALIVE	16
+
+#endif
--- a/5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch
@ -0,0 +1,755 @@
+From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001
+From: Jianqun Xu <jay.xu@rock-chips.com>
+Date: Thu, 28 May 2020 11:01:58 +0800
+Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller
+
+The v2 gpio controller add write enable bit for some register,
+such as data register, data direction register and so on.
+
+This patch support v2 gpio controller by redefine the read and
+write operation functions.
+
+Also adds support for the rk3568 pinctrl device.
+
+Squash all fixes into this commit.
+
+Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
+Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/include/asm/arch-rockchip/gpio.h     |  36 ++
+ drivers/gpio/Kconfig                          |  13 +
+ drivers/gpio/rk_gpio.c                        |  89 ++++-
+ drivers/pinctrl/rockchip/Makefile             |   1 +
+ drivers/pinctrl/rockchip/pinctrl-rk3568.c     | 360 ++++++++++++++++++
+ .../pinctrl/rockchip/pinctrl-rockchip-core.c  |  11 +-
+ drivers/pinctrl/rockchip/pinctrl-rockchip.h   |  42 ++
+ 7 files changed, 530 insertions(+), 22 deletions(-)
+ create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
+
+--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
+@@ -6,6 +6,7 @@
+ #ifndef _ASM_ARCH_GPIO_H
+ #define _ASM_ARCH_GPIO_H
+ 
+#ifndef CONFIG_ROCKCHIP_GPIO_V2
+ struct rockchip_gpio_regs {
+ 	u32 swport_dr;
+ 	u32 swport_ddr;
+@@ -23,6 +24,41 @@ struct rockchip_gpio_regs {
+ 	u32 ls_sync;
+ };
+ check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+	u32 swport_dr_l;                        /* ADDRESS OFFSET: 0x0000 */
+	u32 swport_dr_h;                        /* ADDRESS OFFSET: 0x0004 */
+	u32 swport_ddr_l;                       /* ADDRESS OFFSET: 0x0008 */
+	u32 swport_ddr_h;                       /* ADDRESS OFFSET: 0x000c */
+	u32 int_en_l;                           /* ADDRESS OFFSET: 0x0010 */
+	u32 int_en_h;                           /* ADDRESS OFFSET: 0x0014 */
+	u32 int_mask_l;                         /* ADDRESS OFFSET: 0x0018 */
+	u32 int_mask_h;                         /* ADDRESS OFFSET: 0x001c */
+	u32 int_type_l;                         /* ADDRESS OFFSET: 0x0020 */
+	u32 int_type_h;                         /* ADDRESS OFFSET: 0x0024 */
+	u32 int_polarity_l;                     /* ADDRESS OFFSET: 0x0028 */
+	u32 int_polarity_h;                     /* ADDRESS OFFSET: 0x002c */
+	u32 int_bothedge_l;                     /* ADDRESS OFFSET: 0x0030 */
+	u32 int_bothedge_h;                     /* ADDRESS OFFSET: 0x0034 */
+	u32 debounce_l;                         /* ADDRESS OFFSET: 0x0038 */
+	u32 debounce_h;                         /* ADDRESS OFFSET: 0x003c */
+	u32 dbclk_div_en_l;                     /* ADDRESS OFFSET: 0x0040 */
+	u32 dbclk_div_en_h;                     /* ADDRESS OFFSET: 0x0044 */
+	u32 dbclk_div_con;                      /* ADDRESS OFFSET: 0x0048 */
+	u32 reserved004c;                       /* ADDRESS OFFSET: 0x004c */
+	u32 int_status;                         /* ADDRESS OFFSET: 0x0050 */
+	u32 reserved0054;                       /* ADDRESS OFFSET: 0x0054 */
+	u32 int_rawstatus;                      /* ADDRESS OFFSET: 0x0058 */
+	u32 reserved005c;                       /* ADDRESS OFFSET: 0x005c */
+	u32 port_eoi_l;                         /* ADDRESS OFFSET: 0x0060 */
+	u32 port_eoi_h;                         /* ADDRESS OFFSET: 0x0064 */
+	u32 reserved0068[2];                    /* ADDRESS OFFSET: 0x0068 */
+	u32 ext_port;                           /* ADDRESS OFFSET: 0x0070 */
+	u32 reserved0074;                       /* ADDRESS OFFSET: 0x0074 */
+	u32 ver_id;                             /* ADDRESS OFFSET: 0x0078 */
+};
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
+ 
+ enum gpio_pu_pd {
+ 	GPIO_PULL_NORMAL = 0,
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO
+ 	  The GPIOs for a device are defined in the device tree with one node
+ 	  for each bank.
+ 
+config ROCKCHIP_GPIO_V2
+	bool "Rockchip GPIO driver version 2.0"
+	depends on ROCKCHIP_GPIO
+	default n
+	help
+	  Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
+	  a number of banks (different for each SoC type) each with 32 GPIOs.
+	  The GPIOs for a device are defined in the device tree with one node
+	  for each bank.
+
+	  Support version 2.0 GPIO controller, which support write enable bits
+	  for some registers, such as dr, ddr.
+
+ config SANDBOX_GPIO
+ 	bool "Enable sandbox GPIO driver"
+ 	depends on SANDBOX && DM && DM_GPIO
+--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
+@@ -2,12 +2,15 @@
+ /*
+  * (C) Copyright 2015 Google, Inc
+  *
+- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2020 Rockchip Electronics
+  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
+  */
+ 
+ #include <common.h>
+ #include <dm.h>
+#include <dm/of_access.h>
+#include <dm/device_compat.h>
+ #include <syscon.h>
+ #include <linux/errno.h>
+ #include <asm/gpio.h>
+@@ -17,12 +20,34 @@
+ #include <dm/pinctrl.h>
+ #include <dt-bindings/clock/rk3288-cru.h>
+ 
+-enum {
+-	ROCKCHIP_GPIOS_PER_BANK		= 32,
+-};
+#include "../pinctrl/rockchip/pinctrl-rockchip.h"
+ 
+ #define OFFSET_TO_BIT(bit)	(1UL << (bit))
+ 
+#ifdef CONFIG_ROCKCHIP_GPIO_V2
+#define REG_L(R)	(R##_l)
+#define REG_H(R)	(R##_h)
+#define READ_REG(REG)	((readl(REG_L(REG)) & 0xFFFF) | \
+			((readl(REG_H(REG)) & 0xFFFF) << 16))
+#define WRITE_REG(REG, VAL)	\
+{\
+	writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
+	writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK)	WRITE_REG(REG, READ_REG(REG) & ~(MASK))
+#define SETBITS_LE32(REG, MASK)	WRITE_REG(REG, READ_REG(REG) | (MASK))
+#define CLRSETBITS_LE32(REG, MASK, VAL)	WRITE_REG(REG, \
+				(READ_REG(REG) & ~(MASK)) | (VAL))
+
+#else
+#define READ_REG(REG)			readl(REG)
+#define WRITE_REG(REG, VAL)		writel(VAL, REG)
+#define CLRBITS_LE32(REG, MASK)		clrbits_le32(REG, MASK)
+#define SETBITS_LE32(REG, MASK)		setbits_le32(REG, MASK)
+#define CLRSETBITS_LE32(REG, MASK, VAL)	clrsetbits_le32(REG, MASK, VAL)
+#endif
+
+
+ struct rockchip_gpio_priv {
+ 	struct rockchip_gpio_regs *regs;
+ 	struct udevice *pinctrl;
+@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input
+ 	struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ 	struct rockchip_gpio_regs *regs = priv->regs;
+ 
+-	clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+	CLRBITS_LE32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+ 
+ 	return 0;
+ }
+@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu
+ 	struct rockchip_gpio_regs *regs = priv->regs;
+ 	int mask = OFFSET_TO_BIT(offset);
+ 
+-	clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+-	setbits_le32(&regs->swport_ddr, mask);
+	CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
+	SETBITS_LE32(&regs->swport_ddr, mask);
+ 
+ 	return 0;
+ }
+@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc
+ 	struct rockchip_gpio_regs *regs = priv->regs;
+ 	int mask = OFFSET_TO_BIT(offset);
+ 
+-	clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+	CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
+ 
+ 	return 0;
+ }
+@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st
+ 	ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
+ 	if (ret)
+ 		return ret;
+-	is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
+-
+	is_output = READ_REG(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
+	
+ 	return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
+ #endif
+ }
+@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud
+ {
+ 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ 	struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+-	char *end;
+-	int ret;
+	struct rockchip_pinctrl_priv *pctrl_priv;
+	struct rockchip_pin_bank *bank;
+	char *end = NULL;
+	static int gpio;
+	int id = -1, ret;
+ 
+ 	priv->regs = dev_read_addr_ptr(dev);
+ 	ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
+-	if (ret)
+	if (ret) {
+		dev_err(dev, "failed to get pinctrl device %d\n", ret);
+ 		return ret;
+	}
+
+	pctrl_priv = dev_get_priv(priv->pinctrl);
+	if (!pctrl_priv) {
+		dev_err(dev, "failed to get pinctrl priv\n");
+		return -EINVAL;
+	}
+ 
+-	uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
+ 	end = strrchr(dev->name, '@');
+-	priv->bank = trailing_strtoln(dev->name, end);
+-	priv->name[0] = 'A' + priv->bank;
+-	uc_priv->bank_name = priv->name;
+	if (end)
+		id = trailing_strtoln(dev->name, end);
+	else
+		dev_read_alias_seq(dev, &id);
+
+	if (id < 0)
+		id = gpio++;
+
+	if (id >= pctrl_priv->ctrl->nr_banks) {
+		dev_err(dev, "bank id invalid\n");
+		return -EINVAL;
+	}
+
+	bank = &pctrl_priv->ctrl->pin_banks[id];
+	if (bank->bank_num != id) {
+		dev_err(dev, "bank id mismatch with pinctrl\n");
+		return -EINVAL;
+	}
+
+	priv->bank = bank->bank_num;
+	uc_priv->gpio_count = bank->nr_pins;
+	uc_priv->gpio_base = bank->pin_base;
+	uc_priv->bank_name = bank->name;
+ 
+ 	return 0;
+ }
+--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
+@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl
+ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
+ obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
+ obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+ obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
+--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
+@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
+	MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
+	MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
+	MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
+	MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
+	MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
+	MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
+	MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
+	MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
+};
+
+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask;
+	u8 bit;
+	u32 data;
+
+	debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+		regmap = priv->regmap_pmu;
+	else
+		regmap = priv->regmap_base;
+
+	reg = bank->iomux[iomux_num].offset;
+	if ((pin % 8) >= 4)
+		reg += 0x4;
+	bit = (pin % 4) * 4;
+	mask = 0xf;
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
+#define RK3568_PULL_PMU_OFFSET		0x20
+#define RK3568_PULL_GRF_OFFSET		0x80
+#define RK3568_PULL_BITS_PER_PIN	2
+#define RK3568_PULL_PINS_PER_REG	8
+#define RK3568_PULL_BANK_STRIDE		0x10
+
+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					 int pin_num, struct regmap **regmap,
+					 int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *info = bank->priv;
+
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK3568_PULL_PMU_OFFSET;
+		*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
+	} else {
+		*regmap = info->regmap_base;
+		*reg = RK3568_PULL_GRF_OFFSET;
+		*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
+	}
+
+	*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
+	*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
+	*bit *= RK3568_PULL_BITS_PER_PIN;
+}
+
+#define RK3568_DRV_PMU_OFFSET		0x70
+#define RK3568_DRV_GRF_OFFSET		0x200
+#define RK3568_DRV_BITS_PER_PIN		8
+#define RK3568_DRV_PINS_PER_REG		2
+#define RK3568_DRV_BANK_STRIDE		0x40
+
+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *info = bank->priv;
+
+	/* The first 32 pins of the first bank are located in PMU */
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK3568_DRV_PMU_OFFSET;
+	} else {
+		*regmap = info->regmap_base;
+		*reg = RK3568_DRV_GRF_OFFSET;
+		*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
+	}
+
+	*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
+	*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
+	*bit *= RK3568_DRV_BITS_PER_PIN;
+}
+
+#define RK3568_SCHMITT_BITS_PER_PIN		2
+#define RK3568_SCHMITT_PINS_PER_REG		8
+#define RK3568_SCHMITT_BANK_STRIDE		0x10
+#define RK3568_SCHMITT_GRF_OFFSET		0xc0
+#define RK3568_SCHMITT_PMUGRF_OFFSET		0x30
+
+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+					   int pin_num, struct regmap **regmap,
+					   int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *info = bank->priv;
+
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK3568_SCHMITT_PMUGRF_OFFSET;
+	} else {
+		*regmap = info->regmap_base;
+		*reg = RK3568_SCHMITT_GRF_OFFSET;
+		*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
+	}
+
+	*reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
+	*bit *= RK3568_SCHMITT_BITS_PER_PIN;
+
+	return 0;
+}
+
+static int rk3568_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3568_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
+static int rk3568_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data;
+	u8 bit;
+	int drv = (1 << (strength + 1)) - 1;
+	int ret = 0;
+
+	rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (drv << bit);
+
+	ret = regmap_write(regmap, reg, data);
+	if (ret)
+		return ret;
+
+	if (bank->bank_num == 1 && pin_num == 21)
+		reg = 0x0840;
+	else if (bank->bank_num == 2 && pin_num == 2)
+		reg = 0x0844;
+	else if (bank->bank_num == 2 && pin_num == 8)
+		reg = 0x0848;
+	else if (bank->bank_num == 3 && pin_num == 0)
+		reg = 0x084c;
+	else if (bank->bank_num == 3 && pin_num == 6)
+		reg = 0x0850;
+	else if (bank->bank_num == 4 && pin_num == 0)
+		reg = 0x0854;
+	else
+		return 0;
+
+	data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
+	data |= drv;
+
+	return regmap_write(regmap, reg, data);
+}
+
+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data;
+	u8 bit;
+
+	rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (enable << bit);
+
+	return regmap_write(regmap, reg, data);
+}
+static struct rockchip_pin_bank rk3568_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+			     IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+			     IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+			     IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
+	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT),
+	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT),
+	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT),
+	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT,
+			     IOMUX_WIDTH_4BIT),
+};
+
+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
+	.pin_banks		= rk3568_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3568_pin_banks),
+	.nr_pins		= 160,
+	.grf_mux_offset		= 0x0,
+	.pmu_mux_offset		= 0x0,
+	.iomux_routes		= rk3568_mux_route_data,
+	.niomux_routes		= ARRAY_SIZE(rk3568_mux_route_data),
+	.set_mux		= rk3568_set_mux,
+	.set_pull		= rk3568_set_pull,
+	.set_drive		= rk3568_set_drive,
+	.set_schmitt		= rk3568_set_schmitt,
+};
+
+static const struct udevice_id rk3568_pinctrl_ids[] = {
+	{
+		.compatible = "rockchip,rk3568-pinctrl",
+		.data = (ulong)&rk3568_pin_ctrl
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3568) = {
+	.name		= "rockchip_rk3568_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk3568_pinctrl_ids,
+	.priv_auto = sizeof(struct rockchip_pinctrl_priv),
+	.ops		= &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.probe		= rockchip_pinctrl_probe,
+};
+--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st
+ 	int prop_len, param;
+ 	const u32 *data;
+ 	ofnode node;
+-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
+ 	const struct device_node *np;
+ 	struct property *pp;
+ #else
+@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st
+ 		node = ofnode_get_by_phandle(conf);
+ 		if (!ofnode_valid(node))
+ 			return -ENODEV;
+-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
+ 		np = ofnode_to_np(node);
+ 		for (pp = np->properties; pp; pp = pp->next) {
+ 			prop_name = pp->name;
+@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi
+ 
+ 			/* preset iomux offset value, set new start value */
+ 			if (iom->offset >= 0) {
+-				if (iom->type & IOMUX_SOURCE_PMU)
+				if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
+ 					pmu_offs = iom->offset;
+ 				else
+ 					grf_offs = iom->offset;
+ 			} else { /* set current iomux offset */
+-				iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+-							pmu_offs : grf_offs;
+				iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+						(iom->type & IOMUX_L_SOURCE_PMU)) ?
+						pmu_offs : grf_offs;
+ 			}
+ 
+ 			/* preset drv offset value, set new start value */
+--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+@@ -6,9 +6,13 @@
+ #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
+ #define __DRIVERS_PINCTRL_ROCKCHIP_H
+ 
+#include <dt-bindings/pinctrl/rockchip.h>
+ #include <linux/bitops.h>
+ #include <linux/types.h>
+ 
+#define RK_GENMASK_VAL(h, l, v) \
+	(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
+ /**
+  * Encode variants of iomux registers into a type variable
+  */
+@@ -18,6 +22,8 @@
+ #define IOMUX_UNROUTED		BIT(3)
+ #define IOMUX_WIDTH_3BIT	BIT(4)
+ #define IOMUX_8WIDTH_2BIT	BIT(5)
+#define IOMUX_WRITABLE_32BIT	BIT(6)
+#define IOMUX_L_SOURCE_PMU	BIT(7)
+ 
+ /**
+  * Defined some common pins constants
+@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type {
+ };
+ 
+ /**
+ * enum mux route register type, should be invalid/default/topgrf/pmugrf.
+ * INVALID: means do not need to set mux route
+ * DEFAULT: means same regmap as pin iomux
+ * TOPGRF: means mux route setting in topgrf
+ * PMUGRF: means mux route setting in pmugrf
+ */
+enum rockchip_pin_route_type {
+	ROUTE_TYPE_DEFAULT = 0,
+	ROUTE_TYPE_TOPGRF = 1,
+	ROUTE_TYPE_PMUGRF = 2,
+
+	ROUTE_TYPE_INVALID = -1,
+};
+
+/**
+  * @drv_type: drive strength variant using rockchip_perpin_drv_type
+  * @offset: if initialized to -1 it will be autocalculated, by specifying
+  *	    an initial offset value the relevant source offset can be reset
+@@ -220,6 +241,25 @@ struct rockchip_pin_bank {
+ 		.pull_type[3] = pull3,					\
+ 	}
+ 
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)		\
+	{								\
+		.bank_num	= ID,					\
+		.pin		= PIN,					\
+		.func		= FUNC,					\
+		.route_offset	= REG,					\
+		.route_val	= VAL,					\
+		.route_type	= FLAG,					\
+	}
+
+#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL)	\
+	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
+
+#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL)	\
+	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
+
+#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL)	\
+	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
+
+ /**
+  * struct rockchip_mux_recalced_data: recalculate a pin iomux data.
+  * @num: bank number.
+@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data {
+  * @bank_num: bank number.
+  * @pin: index at register or used to calc index.
+  * @func: the min pin.
+ * @route_type: the register type.
+  * @route_offset: the max pin.
+  * @route_val: the register offset.
+  */
+@@ -248,6 +289,7 @@ struct rockchip_mux_route_data {
+ 	u8 bank_num;
+ 	u8 pin;
+ 	u8 func;
+	enum rockchip_pin_route_type route_type : 8;
+ 	u32 route_offset;
+ 	u32 route_val;
+ };
--- a/5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch
@ -0,0 +1,22 @@
+From 16cc17fc2cf2f308f5ac20b829d427114c6e59fa Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Mon, 20 Dec 2021 08:50:48 -0500
+Subject: [PATCH 08/11] rockchip: allow sdmmc at full speed
+
+Adding pinctrl and gpio support fixed quartz64-a sdmmc.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+@@ -13,7 +13,6 @@
+ };
+ 
+ &sdmmc0 {
+-	max-frequency = <400000>;
+ 	bus-width = <4>;
+ 	u-boot,dm-spl;
+ 	u-boot,spl-fifo-mode;
--- a/5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch
@ -0,0 +1,25 @@
+From d3b3e9c1045e9fa0aff987a036b30cf380809e35 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Mon, 20 Dec 2021 10:11:52 -0500
+Subject: [PATCH 09/11] rockchip: defconfig: add gpio-v2 to quartz64
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ configs/quartz64-a-rk3566_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
+@@ -42,10 +42,12 @@ CONFIG_CMD_REGULATOR=y
+ CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_LIVE=y
+ CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+ CONFIG_SPL_REGMAP=y
+ CONFIG_SPL_SYSCON=y
+ CONFIG_SPL_CLK=y
+ CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+ CONFIG_MMC_HS200_SUPPORT=y
--- a/5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch
@ -0,0 +1,97 @@
+From 981df845d960a9078893dad88e1dd82dfcb4a148 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 22 Dec 2021 19:40:32 -0500
+Subject: [PATCH 10/11] rockchip: rk356x: enable usb2 support on quartz64-a
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 22 ++++++++++++++++++++++
+ configs/quartz64-a-rk3566_defconfig        | 17 +++++++++++++++++
+ include/configs/quartz64-a-rk3566.h        |  3 +++
+ 3 files changed, 42 insertions(+)
+
+--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+@@ -12,12 +12,34 @@
+ 	};
+ };
+ 
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+	status = "disabled";
+};
+
+ &sdmmc0 {
+ 	bus-width = <4>;
+ 	u-boot,dm-spl;
+ 	u-boot,spl-fifo-mode;
+ };
+ 
+&usb_host0_ehci {
+	vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host0_ohci {
+	vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host1_ehci {
+	vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+&usb_host1_ohci {
+	vbus-supply = <&vcc5v0_usb20_host>;
+};
+
+ &uart2 {
+ 	clock-frequency = <24000000>;
+ 	u-boot,dm-spl;
+--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
+@@ -22,6 +22,7 @@ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+@@ -35,6 +36,7 @@ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
+@@ -76,4 +78,19 @@ CONFIG_BAUDRATE=1500000
+ CONFIG_DEBUG_UART_SHIFT=2
+ CONFIG_SYSRESET=y
+ CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+ CONFIG_ERRNO_STR=y
+--- a/include/configs/quartz64-a-rk3566.h
+++ b/include/configs/quartz64-a-rk3566.h
+@@ -11,4 +11,7 @@
+ 			"stdout=serial,vidconsole\0" \
+ 			"stderr=serial,vidconsole\0"
+ 
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+
+ #endif
--- a/5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch
@ -0,0 +1,173 @@
+From ea6da572fe3cee637319f1e7e588c059622c815e Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 22 Dec 2021 19:52:38 -0500
+Subject: [PATCH 11/11] rockchip: rk356x: attempt to fix ram detection
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++
+ arch/arm/mach-rockchip/sdram.c         | 31 ++++++++++++++------------
+ common/board_f.c                       |  7 ++++++
+ configs/quartz64-a-rk3566_defconfig    |  1 +
+ include/configs/rk3568_common.h        |  5 +++++
+ 5 files changed, 59 insertions(+), 14 deletions(-)
+
+--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
+@@ -5,6 +5,7 @@
+ 
+ #include <common.h>
+ #include <dm.h>
+#include <fdt_support.h>
+ #include <asm/armv8/mmu.h>
+ #include <asm/io.h>
+ #include <asm/arch-rockchip/bootrom.h>
+@@ -135,3 +136,31 @@ int arch_cpu_init(void)
+ #endif
+ 	return 0;
+ }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	int ret;
+	int areas = 1;
+	u64 start[2], size[2];
+
+	/* Reserve the io address space. */
+	if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) {
+		start[0] = gd->bd->bi_dram[0].start;
+		size[0] = SDRAM_LOWER_ADDR_MAX - gd->bd->bi_dram[0].start;
+
+		/* Add the upper 4GB address space */
+		start[1] = SDRAM_UPPER_ADDR_MIN;
+		size[1] = gd->ram_top - SDRAM_UPPER_ADDR_MIN;
+		areas = 2;
+
+		ret = fdt_set_usable_memory(blob, start, size, areas);
+		if (ret) {
+			printf("Cannot set usable memory\n");
+			return ret;
+		}
+	}
+
+	return 0;
+};
+#endif
+--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
+@@ -3,6 +3,8 @@
+  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+  */
+ 
+#define DEBUG
+
+ #include <common.h>
+ #include <dm.h>
+ #include <init.h>
+@@ -98,8 +100,7 @@ size_t rockchip_sdram_size(phys_addr_t r
+ 			  SYS_REG_COL_MASK);
+ 		cs1_col = cs0_col;
+ 		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+-		if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
+-		     SYS_REG_VERSION_MASK) == 0x2) {
+		if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) >= 0x2) {
+ 			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
+ 				  SYS_REG_CS1_COL_MASK);
+ 			if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
+@@ -136,7 +137,7 @@ size_t rockchip_sdram_size(phys_addr_t r
+ 			SYS_REG_BW_MASK));
+ 		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
+ 			SYS_REG_ROW_3_4_MASK;
+-		if (dram_type == DDR4) {
+		if ((dram_type == DDR4) && (sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) != 0x3){
+ 			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
+ 				SYS_REG_DBW_MASK;
+ 			bg = (dbw == 2) ? 2 : 1;
+@@ -150,15 +151,11 @@ size_t rockchip_sdram_size(phys_addr_t r
+ 			chipsize_mb = chipsize_mb * 3 / 4;
+ 		size_mb += chipsize_mb;
+ 		if (rank > 1)
+-			debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
+-			       cs1_row %d bw %d row_3_4 %d\n",
+-			       rank, cs0_col, cs1_col, bk, cs0_row,
+-			       cs1_row, bw, row_3_4);
+			debug("rank=%d cs0_col=%d cs1_col=%d bk=%d cs0_row=%d cs1_row=%d bg=%d bw=%d row_3_4=%d\n",
+			       rank, cs0_col, cs1_col, bk, cs0_row, cs1_row, bg, bw, row_3_4);
+ 		else
+-			debug("rank %d cs0_col %d bk %d cs0_row %d\
+-			       bw %d row_3_4 %d\n",
+-			       rank, cs0_col, bk, cs0_row,
+-			       bw, row_3_4);
+			debug("rank %d cs0_col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
+			       rank, cs0_col, bk, cs0_row, bw, row_3_4);
+ 	}
+ 
+ 	/*
+@@ -176,9 +173,11 @@ size_t rockchip_sdram_size(phys_addr_t r
+ 	 *   2. update board_get_usable_ram_top() and dram_init_banksize()
+ 	 *   to reserve memory for peripheral space after previous update.
+ 	 */
+
+#ifndef __aarch64__
+ 	if (size_mb > (SDRAM_MAX_SIZE >> 20))
+ 		size_mb = (SDRAM_MAX_SIZE >> 20);
+-
+#endif
+ 	return (size_t)size_mb << 20;
+ }
+ 
+@@ -208,6 +207,10 @@ int dram_init(void)
+ ulong board_get_usable_ram_top(ulong total_size)
+ {
+ 	unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+-
+-	return (gd->ram_top > top) ? top : gd->ram_top;
+#ifdef SDRAM_UPPER_ADDR_MIN
+	if (gd->ram_top > SDRAM_UPPER_ADDR_MIN)
+		return gd->ram_top;
+	else
+#endif
+		return (gd->ram_top > top) ? top : gd->ram_top;
+ }
+--- a/common/board_f.c
+++ b/common/board_f.c
+@@ -345,7 +345,14 @@ static int setup_dest_addr(void)
+ #endif
+ 	gd->ram_top = gd->ram_base + get_effective_memsize();
+ 	gd->ram_top = board_get_usable_ram_top(gd->mon_len);
+#ifdef SDRAM_LOWER_ADDR_MAX
+	if (gd->ram_top > SDRAM_LOWER_ADDR_MAX)
+		gd->relocaddr = SDRAM_LOWER_ADDR_MAX;
+	else
+		gd->relocaddr = gd->ram_top;
+#else
+ 	gd->relocaddr = gd->ram_top;
+#endif
+ 	debug("Ram top: %08lX\n", (ulong)gd->ram_top);
+ #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ 	/*
+--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
+@@ -21,6 +21,7 @@ CONFIG_API=y
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
+ # CONFIG_SYS_DEVICE_NULLDEV is not set
+ # CONFIG_DISPLAY_CPUINFO is not set
+--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
+@@ -24,6 +24,11 @@
+ #define CONFIG_SYS_SDRAM_BASE		0
+ #define SDRAM_MAX_SIZE			0xf0000000
+ 
+#ifdef CONFIG_OF_SYSTEM_SETUP
+#define SDRAM_LOWER_ADDR_MAX		0xf0000000
+#define SDRAM_UPPER_ADDR_MIN		0x100000000
+#endif
+
+ #ifndef CONFIG_SPL_BUILD
+ #define ENV_MEM_LAYOUT_SETTINGS		\
+ 	"scriptaddr=0x00c00000\0"	\
--- a/5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch
--- a/5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch
@ -0,0 +1,795 @@
+From 89d609d74e4ef84e0e3d399d8763b268b60302fc Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sat, 28 May 2022 20:19:38 -0400
+Subject: [PATCH] rockchip: rk356x: add bpi r2 pro board
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm/dts/Makefile                         |   1 +
+ arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi    |  47 ++
+ arch/arm/dts/rk3568-bpi-r2-pro.dts            | 532 ++++++++++++++++++
+ arch/arm/mach-rockchip/rk3568/Kconfig         |   6 +
+ board/rockchip/bpi-r2-pro-rk3568/Kconfig      |  15 +
+ board/rockchip/bpi-r2-pro-rk3568/Makefile     |   7 +
+ .../bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c     |   4 +
+ configs/bpi-r2-pro-rk3568_defconfig           |  97 ++++
+ include/configs/bpi-r2-pro-rk3568.h           |  15 +
+ 9 files changed, 724 insertions(+)
+ create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts
+ create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Kconfig
+ create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Makefile
+ create mode 100644 board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
+ create mode 100644 configs/bpi-r2-pro-rk3568_defconfig
+ create mode 100644 include/configs/bpi-r2-pro-rk3568.h
+
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -164,6 +164,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ 	rk3399pro-rock-pi-n10.dtb
+ 
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+ 	rk3566-quartz64-a.dtb
+ 
+--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	status = "disabled";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,dm-spl;
+	u-boot,spl-fifo-mode;
+};
+
+&usb_host0_ehci {
+	vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host0_ohci {
+	vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host1_ehci {
+	vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&usb_host1_ohci {
+	vbus-supply = <&vcc5v0_usb_host>;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-spl;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
+@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
+	compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&blue_led_pin &green_led_pin>;
+
+		blue_led: led-0 {
+			color = <LED_COLOR_ID_BLUE>;
+			default-state = "off";
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		};
+
+		green_led: led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: vcc5v0_usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&combphy0 {
+	/* used for USB3 */
+	status = "okay";
+};
+
+&combphy1 {
+	/* used for USB3 */
+	status = "okay";
+};
+
+&combphy2 {
+	/* used for SATA */
+	status = "okay";
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	clock_in_out = "input";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x4f>;
+	rx_delay = <0x0f>;
+	status = "okay";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	/* pin 3 (SDA) + 4 (SCL) of header con2 */
+	status = "disabled";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	leds {
+		blue_led_pin: blue-led-pin {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		green_led_pin: green-led-pin {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm8 {
+	/* fan 5v - gnd - pwm */
+	status = "okay";
+};
+
+&pwm10 {
+	/* pin 7 of header con2 */
+	status = "disabled";
+};
+
+&pwm11 {
+	/* pin 15 of header con2 */
+	status = "disabled";
+};
+
+
+&pwm13 {
+	/* pin 24 of header con2 */
+	/* shared with uart9 */
+	pinctrl-0 = <&pwm13m1_pins>;
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart0 {
+	/* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
+	status = "disabled";
+};
+
+&uart2 {
+	/* debug-uart */
+	status = "okay";
+};
+
+&uart7 {
+	/* pin 11 (TX) + 13 (RX) of header con2 */
+	pinctrl-0 = <&uart7m1_xfer>;
+	status = "disabled";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
+@@ -3,6 +3,11 @@ if ROCKCHIP_RK3568
+ choice
+ 	prompt "RK3568/RK3566 board select"
+ 
+config TARGET_BPI_R2_PRO_RK3568
+	bool "Banana Pi R2 Pro RK3566 development board"
+	help
+	  Banana Pi R2 Pro is a development board Rockchp RK3568.
+
+ config TARGET_EVB_RK3568
+ 	bool "RK3568 evaluation board"
+ 	help
+@@ -27,6 +32,7 @@ config SYS_SOC
+ config SYS_MALLOC_F_LEN
+ 	default 0x2000
+ 
+source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
+ source "board/rockchip/evb_rk3568/Kconfig"
+ source "board/pine64/quartz64-a-rk3566/Kconfig"
+ 
+--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/Kconfig
+@@ -0,0 +1,15 @@
+if TARGET_BPI_R2_PRO_RK3568
+
+config SYS_BOARD
+	default "bpi-r2-pro-rk3568"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "bpi-r2-pro-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/Makefile
+@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= bpi-r2-pro-rk3568.o
+--- /dev/null
+++ b/board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
+@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+--- /dev/null
+++ b/configs/bpi-r2-pro-rk3568_defconfig
+@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_BPI_R2_PRO_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
+--- /dev/null
+++ b/include/configs/bpi-r2-pro-rk3568.h
+@@ -0,0 +1,15 @@
+#ifndef __BPI_R2_PRO_RK3568_H
+#define __BPI_R2_PRO_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+
+#endif
--- a/5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch
@ -0,0 +1,690 @@
+From 443eb96a82563a3b38a3c9548853a5a266dfd072 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sun, 29 May 2022 06:09:59 -0400
+Subject: [PATCH] uboot: add Radxa ROCK 3A board
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm/dts/Makefile                       |   3 +-
+ arch/arm/dts/rk3568-rock-3a-u-boot.dtsi     |  25 +
+ arch/arm/dts/rk3568-rock-3a.dts             | 525 ++++++++++++++++++++
+ arch/arm/mach-rockchip/rk3568/Kconfig       |   6 +
+ board/radxa/rock-3a-rk3568/Kconfig          |  15 +
+ board/radxa/rock-3a-rk3568/Makefile         |   4 +
+ board/radxa/rock-3a-rk3568/rock-3a-rk3568.c |   1 +
+ configs/rock-3a-rk3568_defconfig            |  97 ++++
+ include/configs/rock-3a-rk3568.h            |  17 +
+ 9 files changed, 692 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
+ create mode 100644 configs/rock-3a-rk3568_defconfig
+ create mode 100644 include/configs/rock-3a-rk3568.h
+
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -166,7 +166,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+-	rk3566-quartz64-a.dtb
+	rk3566-quartz64-a.dtb \
+	rk3568-rock-3a.dtb
+ 
+ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
+ 	rv1108-elgin-r1.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
+@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Radxa ROCK3 Model A";
+	compatible = "radxa,rock3a", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_user: led-0 {
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_user_en>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_hub_en>;
+		regulator-name = "vcc5v0_usb_hub";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&eth_phy_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	ethernet {
+		eth_phy_rst: eth_phy_rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_user_en: led_user_en {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+--- /dev/null
+++ b/configs/rock-3a-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch
@ -0,0 +1,247 @@
+From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Tue, 31 May 2022 00:51:23 -0400
+Subject: [PATCH] uboot: add NanoPi R5S board
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm/dts/Makefile                         |  1 +
+ arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi    | 25 +++++
+ arch/arm/dts/rk3568-nanopi-r5s.dts            |  9 ++
+ arch/arm/mach-rockchip/rk3568/Kconfig         |  6 ++
+ board/friendlyelec/nanopi-r5s-rk3568/Kconfig   | 15 +++
+ board/friendlyelec/nanopi-r5s-rk3568/Makefile  |  4 +
+ .../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c     |  4 +
+ configs/nanopi-r5s-rk3568_defconfig           | 97 +++++++++++++++++++
+ include/configs/nanopi-r5s-rk3568.h           | 17 ++++
+ 9 files changed, 178 insertions(+)
+ create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
+ create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig
+ create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile
+ create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
+ create mode 100644 configs/nanopi-r5s-rk3568_defconfig
+ create mode 100644 include/configs/nanopi-r5s-rk3568.h
+
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+	rk3568-nanopi-r5s.dtb \
+ 	rk3566-quartz64-a.dtb \
+ 	rk3568-rock-3a.dtb
+ 
+--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,dm-spl;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-spl;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
+@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3568-evb.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R5S";
+	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
+};
+--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
+@@ -13,6 +13,11 @@ config TARGET_EVB_RK3568
+ 	help
+ 	  RK3568 EVB is a evaluation board for Rockchp RK3568.
+ 
+config TARGET_NANOPI_R5S_RK3568
+	bool "NanoPi R5S board"
+	help
+	  NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
+
+ config TARGET_QUARTZ64_A_RK3566
+ 	bool "Quartz64 Model A RK3566 development board"
+ 	help
+@@ -39,6 +44,7 @@ config SYS_MALLOC_F_LEN
+ 
+ source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
+ source "board/rockchip/evb_rk3568/Kconfig"
+source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
+ source "board/pine64/quartz64-a-rk3566/Kconfig"
+ source "board/radxa/rock-3a-rk3568/Kconfig"
+ 
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Kconfig
+@@ -0,0 +1,15 @@
+if TARGET_NANOPI_R5S_RK3568
+
+config SYS_BOARD
+	default "nanopi-r5s-rk3568"
+
+config SYS_VENDOR
+	default "friendlyelec"
+
+config SYS_CONFIG_NAME
+	default "nanopi-r5s-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Makefile
+@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= nanopi-r5s-rk3568.o
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
+@@ -0,0 +1,4 @@
+ // SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ */
+--- /dev/null
+++ b/configs/nanopi-r5s-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_NANOPI_R5S_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
+--- /dev/null
+++ b/include/configs/nanopi-r5s-rk3568.h
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NANOPI_R5S_RK3568_H
+#define __NANOPI_R5S_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#endif
--- a/5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch
@ -0,0 +1,42 @@
+From c9a8a3b5fb4ae210c5a5acb1538b0e961c5d1421 Mon Sep 17 00:00:00 2001
+From: Tang Yun ping <typ@rock-chips.com>
+Date: Wed, 23 Jun 2021 19:48:59 +0800
+Subject: [PATCH] rk356x: ddr: fix dbw detect bug
+
+Signed-off-by: Tang Yun ping <typ@rock-chips.com>
+Change-Id: Ifadad00853eb0ad43a68f12335fd243e6a1bc04b
+---
+ drivers/ram/rockchip/sdram_common.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
+@@ -299,22 +299,22 @@ int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
+ 		bw = cap_info->bw;
+ 		cs_cap = (1 << (row + col + bk + bw - 20));
+ 		if (bw == 2) {
+-			if (cs_cap <= 0x2000000) /* 256Mb */
+			if (cs_cap <= 0x20) /* 256Mb */
+ 				die_bw_0 = (col < 9) ? 2 : 1;
+-			else if (cs_cap <= 0x10000000) /* 2Gb */
+			else if (cs_cap <= 0x100) /* 2Gb */
+ 				die_bw_0 = (col < 10) ? 2 : 1;
+-			else if (cs_cap <= 0x40000000) /* 8Gb */
+			else if (cs_cap <= 0x400) /* 8Gb */
+ 				die_bw_0 = (col < 11) ? 2 : 1;
+ 			else
+ 				die_bw_0 = (col < 12) ? 2 : 1;
+ 			if (cs > 1) {
+ 				row = cap_info->cs1_row;
+ 				cs_cap = (1 << (row + col + bk + bw - 20));
+-				if (cs_cap <= 0x2000000) /* 256Mb */
+				if (cs_cap <= 0x20) /* 256Mb */
+ 					die_bw_0 = (col < 9) ? 2 : 1;
+-				else if (cs_cap <= 0x10000000) /* 2Gb */
+				else if (cs_cap <= 0x100) /* 2Gb */
+ 					die_bw_0 = (col < 10) ? 2 : 1;
+-				else if (cs_cap <= 0x40000000) /* 8Gb */
+				else if (cs_cap <= 0x400) /* 8Gb */
+ 					die_bw_0 = (col < 11) ? 2 : 1;
+ 				else
+ 					die_bw_0 = (col < 12) ? 2 : 1;
--- a/5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch
@ -0,0 +1,44 @@
+From c7496009386dbac8f8d18a94258031f30683d7c6 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 20 Feb 2022 07:59:02 -0500
+Subject: [PATCH] gpio: rockchip: fix building for spl
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/gpio/rk_gpio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
+@@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY
+ 	  ensure this information is available to the next image
+ 	  invoked).
+ 
+config SPL_ADC
+	bool "Support ADC drivers in SPL"
+	help
+	  Enable ADC drivers in SPL.
+
+ config SPL_CACHE
+ 	bool "Support CACHE drivers"
+ 	help
+--- a/drivers/Makefile
+++ b/drivers/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0+
+ 
+obj-$(CONFIG_$(SPL_)ADC) += adc/
+ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
+ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
+ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
+--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
+@@ -118,7 +118,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
+ }
+ 
+ /* Simple SPL interface to GPIOs */
+-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ROCKCHIP_GPIO_V2)
+ 
+ enum {
+ 	PULL_NONE_1V8 = 0,
--- a/5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch
@ -0,0 +1,28 @@
+From 5011ceb0da47f7c3d54d20b45b7df884e6e92ac5 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 20 Feb 2022 07:58:38 -0500
+Subject: [PATCH] clk: rockchip: rk3568: fix reset handler
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/clk/rockchip/clk_rk3568.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
+@@ -14,6 +14,7 @@
+ #include <asm/arch-rockchip/clock.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <asm/io.h>
+#include <dm/device-internal.h>
+ #include <dm/lists.h>
+ #include <dt-bindings/clock/rk3568-cru.h>
+ 
+@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev)
+ 						    glb_srst_fst);
+ 		priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
+ 						    glb_srsr_snd);
+		dev_set_priv(sys_child, priv);
+ 	}
+ 
+ #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
--- a/5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch
@ -0,0 +1,144 @@
+From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sun, 20 Feb 2022 07:57:50 -0500
+Subject: [PATCH] rockchip: handle bootrom mode in spl
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ arch/arm/mach-rockchip/Makefile        |  6 +--
+ arch/arm/mach-rockchip/boot_mode.c     |  4 +-
+ arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++-
+ 3 files changed, 59 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
+@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
+ 
+ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+ 
+-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+-
+ # Always include boot_mode.o, as we bypass it (i.e. turn it off)
+ # inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0.  This way,
+ # we can have the preprocessor correctly recognise both 0x0 and 0
+ # meaning "turn it off".
+-obj-y += boot_mode.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
+ obj-$(CONFIG_MISC_INIT_R) += misc.o
+ endif
+--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
+@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void)
+ 	ret = -ENODEV;
+ 	uclass_foreach_dev(dev, uc) {
+ 		if (!strncmp(dev->name, "saradc", 6)) {
+-			ret = adc_channel_single_shot(dev->name, 1, &val);
+			ret = adc_channel_single_shot(dev->name, 0, &val);
+ 			break;
+ 		}
+ 	}
+@@ -89,6 +89,7 @@ int setup_boot_mode(void)
+ 	boot_mode = readl(reg);
+ 	debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+ 
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+ 	/* Clear boot mode */
+ 	writel(BOOT_NORMAL, reg);
+ 
+@@ -102,6 +103,7 @@ int setup_boot_mode(void)
+ 		env_set("preboot", "setenv preboot; ums mmc 0");
+ 		break;
+ 	}
+#endif
+ 
+ 	return 0;
+ }
+--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
+@@ -9,19 +9,30 @@
+ #include <asm/armv8/mmu.h>
+ #include <asm/io.h>
+ #include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/boot_mode.h>
+ #include <asm/arch-rockchip/grf_rk3568.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <dt-bindings/clock/rk3568-cru.h>
+ 
+ #define PMUGRF_BASE			0xfdc20000
+ #define GRF_BASE			0xfdc60000
+#define GRF_GPIO1B_IOMUX_H		0x0c
+#define GRF_GPIO1C_IOMUX_L		0x10
+#define GRF_GPIO1C_IOMUX_H		0x14
+#define GRF_GPIO1D_IOMUX_L		0x18
+#define GRF_GPIO1D_IOMUX_H		0x1c
+#define GRF_GPIO2A_IOMUX_L		0x20
+ #define GRF_GPIO1B_DS_2			0x218
+ #define GRF_GPIO1B_DS_3			0x21c
+ #define GRF_GPIO1C_DS_0			0x220
+ #define GRF_GPIO1C_DS_1			0x224
+ #define GRF_GPIO1C_DS_2			0x228
+ #define GRF_GPIO1C_DS_3			0x22c
+-#define SGRF_BASE			0xFDD18000
+#define GRF_GPIO1D_DS_0			0x230
+#define GRF_GPIO1D_DS_1			0x234
+#define GRF_GPIO1D_DS_2			0x238
+#define SGRF_BASE			0xfdd18000
+#define SGRF_SOC_CON3			0x0c
+ #define SGRF_SOC_CON4			0x10
+ #define EMMC_HPROT_SECURE_CTRL		0x03
+ #define SDMMC0_HPROT_SECURE_CTRL	0x01
+@@ -133,6 +144,24 @@ int arch_cpu_init(void)
+ 	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+ 	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+ 	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+
+	/* emmc, sfc, and sdmmc iomux */
+	writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
+	writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
+	writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
+	writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
+	writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H);
+	writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L);
+
+	/* set the fspi d0~3 cs0 to level 2 */
+	writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
+	writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
+	writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
+
+	/* Set the fspi to secure */
+	writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
+
+ #endif
+ 	return 0;
+ }
+@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
+ 	return 0;
+ };
+ #endif
+
+#ifdef CONFIG_SPL_BUILD
+
+void __weak led_setup(void)
+{
+}
+
+void spl_board_init(void)
+{
+	led_setup();
+
+#if defined(SPL_DM_REGULATOR)
+	/*
+	 * Turning the eMMC and SPI back on (if disabled via the Qseven
+	 * BIOS_ENABLE) signal is done through a always-on regulator).
+	 */
+	if (regulators_enable_boot_on(false))
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+	setup_boot_mode();
+}
+#endif
--- a/5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch
@ -0,0 +1,282 @@
+From cd6a45a41fb2c19884ac87afade87b4d53601929 Mon Sep 17 00:00:00 2001
+From: Tom Rini <trini@konsulko.com>
+Date: Sat, 25 Jun 2022 11:02:31 -0400
+Subject: [PATCH] Convert CONFIG_USB_OHCI_NEW et al to Kconfig
+
+This converts the following to Kconfig:
+    CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+    CONFIG_SYS_USB_OHCI_CPU_INIT
+    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+    CONFIG_SYS_USB_OHCI_SLOT_NAME
+    CONFIG_USB_ATMEL
+    CONFIG_USB_ATMEL_CLK_SEL_PLLB
+    CONFIG_USB_ATMEL_CLK_SEL_UPLL
+    CONFIG_USB_OHCI_LPC32XX
+    CONFIG_USB_OHCI_NEW
+
+Signed-off-by: Tom Rini <trini@konsulko.com>
+---
+
+diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
+index 4d6d235cb125..c81437300c74 100644
+--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
+@@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
+index 41793ca7e486..15c2e1698c20 100644
+--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
+@@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
+index ab25abc1a031..43b90c7879b7 100644
+--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
+@@ -108,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
+index 1d51a267b93a..7d95e171f7f4 100644
+--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
+@@ -109,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
+index 640fe558d414..bc333a5e2a6a 100644
+--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
+@@ -106,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
+index 78e50dbfbcb7..bb5b2143691d 100644
+--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
+@@ -74,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+ CONFIG_USB_DWC3=y
+ CONFIG_USB_KEYBOARD=y
+ CONFIG_USB_HOST_ETHER=y
+diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
+index 4d2a5b32e31c..ef28fe6a937a 100644
+--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
+@@ -87,6 +87,7 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+ CONFIG_USB_DWC3=y
+ CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_KEYBOARD=y
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 0b82c2fdaf71..31ae9f74e7ac 100644
+--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
+@@ -297,10 +297,17 @@ config USB_EHCI_TXFIFO_THRESH
+	  Enables support for the on-chip EHCI controller on FSL chips.
+ endif # USB_EHCI_HCD
+ 
+config USB_OHCI_NEW
+	bool
+
+config SYS_USB_OHCI_CPU_INIT
+	bool
+
+ config USB_OHCI_HCD
+ 	bool "OHCI HCD (USB 1.1) support"
+ 	depends on DM && OF_CONTROL
+ 	select USB_HOST
+	select USB_OHCI_NEW
+ 	---help---
+ 	  The Open Host Controller Interface (OHCI) is a standard for accessing
+ 	  USB 1.1 host controller hardware.  It does more in hardware than Intel's
+@@ -332,6 +339,19 @@ config USB_OHCI_DA8XX
+ 
+ endif # USB_OHCI_HCD
+ 
+config SYS_USB_OHCI_SLOT_NAME
+	string "Display name for the OHCI controller"
+	depends on USB_OHCI_NEW && !DM_USB
+
+config SYS_USB_OHCI_MAX_ROOT_PORTS
+	int "Maximal number of ports of the root hub"
+	depends on USB_OHCI_NEW
+	default 1 if ARCH_SUNXI
+
+config SYS_OHCI_SWAP_REG_ACCESS
+	bool "Perform byte swapping on OHCI controller register accesses"
+	depends on USB_OHCI_NEW
+
+ config USB_UHCI_HCD
+ 	bool "UHCI HCD (most Intel and VIA) support"
+ 	select USB_HOST
+@@ -381,3 +401,27 @@ config USB_R8A66597_HCD
+ 	---help---
+ 	  This enables support for the on-chip Renesas R8A66597 USB 2.0
+ 	  controller, present in various RZ and SH SoCs.
+
+config USB_ATMEL
+	bool "AT91 OHCI USB support"
+	depends on ARCH_AT91
+	select SYS_USB_OHCI_CPU_INIT
+	select USB_OHCI_NEW
+
+choice
+	prompt "Clock for OHCI"
+	depends on USB_ATMEL
+
+config USB_ATMEL_CLK_SEL_PLLB
+	bool "PLLB"
+
+config USB_ATMEL_CLK_SEL_UPLL
+	bool "UPLL"
+
+endchoice
+
+config USB_OHCI_LPC32XX
+	bool "LPC32xx USB OHCI support"
+	depends on ARCH_LPC32XX
+	select SYS_USB_OHCI_CPU_INIT
+	select USB_OHCI_NEW
+diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
+index 8ceabaf45c1b..9b955c1bd678 100644
+--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
+@@ -5,9 +5,6 @@
+  */
+ 
+ #include <common.h>
+-
+-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+-
+ #include <asm/arch/clk.h>
+ 
+ int usb_cpu_init(void)
+@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void)
+ {
+ 	return usb_cpu_stop();
+ }
+-
+-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
+diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
+index 163f0ef17b11..5d23058aaf6a 100644
+--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
+@@ -14,10 +14,6 @@
+ #include <reset.h>
+ #include "ohci.h"
+ 
+-#if !defined(CONFIG_USB_OHCI_NEW)
+-# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
+-#endif
+-
+ struct generic_ohci {
+ 	ohci_t ohci;
+ 	struct clk *clocks;	/* clock list */
+diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
+index a38cd25eb85f..7699f2e6b15a 100644
+--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
+@@ -151,7 +151,7 @@ struct ohci_hcca {
+  * Maximum number of root hub ports.
+  */
+ #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+ #endif
+ 
+ /*
+diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
+index 492b7b4df128..b7e850370b31 100644
+--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
+@@ -15,7 +15,4 @@
+ 
+ #define SDRAM_BANK_SIZE			(2UL << 30)
+ 
+-#define CONFIG_USB_OHCI_NEW
+-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+-
+ #endif
+diff --git a/include/configs/gru.h b/include/configs/gru.h
+index b1084bb21d4d..be2dc79968c0 100644
+--- a/include/configs/gru.h
+++ b/include/configs/gru.h
+@@ -13,7 +13,4 @@
+ 
+ #include <configs/rk3399_common.h>
+ 
+-#define CONFIG_USB_OHCI_NEW
+-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+-
+ #endif
+diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
+index 90183579202d..165b78ff3309 100644
+--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
+@@ -30,8 +30,4 @@
+ 	"partitions=" PARTS_DEFAULT \
+ 	BOOTENV
+ 
+-/* rockchip ohci host driver */
+-#define CONFIG_USB_OHCI_NEW
+-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+-
+ #endif
+diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h
+index 2edad710284f..6099d2fa55a6 100644
+--- a/include/configs/rock960_rk3399.h
+++ b/include/configs/rock960_rk3399.h
+@@ -14,7 +14,4 @@
+ #include <configs/rk3399_common.h>
+ 
+ #define SDRAM_BANK_SIZE			(2UL << 30)
+-
+-#define CONFIG_USB_OHCI_NEW
+-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+ #endif
+diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h
+index 903e9df527c1..9195b9b99e41 100644
+--- a/include/configs/rockpro64_rk3399.h
+++ b/include/configs/rockpro64_rk3399.h
+@@ -14,7 +14,4 @@
+ #include <configs/rk3399_common.h>
+ 
+ #define SDRAM_BANK_SIZE			(2UL << 30)
+-
+-#define CONFIG_USB_OHCI_NEW
+-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+ #endif
--- a/5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch
@ -0,0 +1,166 @@
+--- a/include/image.h
+++ b/include/image.h
+@@ -1020,21 +1020,6 @@ int fit_image_hash_get_value(const void
+ 
+ int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
+ 
+-/**
+- * fit_pre_load_data() - add public key to fdt blob
+- *
+- * Adds public key to the node pre load.
+- *
+- * @keydir:	Directory containing keys
+- * @keydest:	FDT blob to write public key
+- * @fit:	Pointer to the FIT format image header
+- *
+- * returns:
+- *	0, on success
+- *	< 0, on failure
+- */
+-int fit_pre_load_data(const char *keydir, void *keydest, void *fit);
+-
+ int fit_cipher_data(const char *keydir, void *keydest, void *fit,
+ 		    const char *comment, int require_keys,
+ 		    const char *engine_id, const char *cmdname);
+--- a/tools/fit_image.c
+++ b/tools/fit_image.c
+@@ -59,9 +59,6 @@ static int fit_add_file_data(struct imag
+ 		ret = fit_set_timestamp(ptr, 0, time);
+ 	}
+ 
+-	if (!ret)
+-		ret = fit_pre_load_data(params->keydir, dest_blob, ptr);
+-
+ 	if (!ret) {
+ 		ret = fit_cipher_data(params->keydir, dest_blob, ptr,
+ 				      params->comment,
+--- a/tools/image-host.c
+++ b/tools/image-host.c
+@@ -14,11 +14,6 @@
+ #include <image.h>
+ #include <version.h>
+ 
+-#include <openssl/pem.h>
+-#include <openssl/evp.h>
+-
+-#define IMAGE_PRE_LOAD_PATH                             "/image/pre-load/sig"
+-
+ /**
+  * fit_set_hash_value - set hash value in requested has node
+  * @fit: pointer to the FIT format image header
+@@ -1116,115 +1111,6 @@ static int fit_config_add_verification_d
+ 	return 0;
+ }
+ 
+-/*
+- * 0) open file (open)
+- * 1) read certificate (PEM_read_X509)
+- * 2) get public key (X509_get_pubkey)
+- * 3) provide der format (d2i_RSAPublicKey)
+- */
+-static int read_pub_key(const char *keydir, const void *name,
+-			unsigned char **pubkey, int *pubkey_len)
+-{
+-	char path[1024];
+-	EVP_PKEY *key = NULL;
+-	X509 *cert;
+-	FILE *f;
+-	int ret;
+-
+-	memset(path, 0, 1024);
+-	snprintf(path, sizeof(path), "%s/%s.crt", keydir, (char *)name);
+-
+-	/* Open certificate file */
+-	f = fopen(path, "r");
+-	if (!f) {
+-		fprintf(stderr, "Couldn't open RSA certificate: '%s': %s\n",
+-			path, strerror(errno));
+-		return -EACCES;
+-	}
+-
+-	/* Read the certificate */
+-	cert = NULL;
+-	if (!PEM_read_X509(f, &cert, NULL, NULL)) {
+-		printf("Couldn't read certificate");
+-		ret = -EINVAL;
+-		goto err_cert;
+-	}
+-
+-	/* Get the public key from the certificate. */
+-	key = X509_get_pubkey(cert);
+-	if (!key) {
+-		printf("Couldn't read public key\n");
+-		ret = -EINVAL;
+-		goto err_pubkey;
+-	}
+-
+-	/* Get DER form */
+-	ret = i2d_PublicKey(key, pubkey);
+-	if (ret < 0) {
+-		printf("Couldn't get DER form\n");
+-		ret = -EINVAL;
+-		goto err_pubkey;
+-	}
+-
+-	*pubkey_len = ret;
+-	ret = 0;
+-
+-err_pubkey:
+-	X509_free(cert);
+-err_cert:
+-	fclose(f);
+-	return ret;
+-}
+-
+-int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
+-{
+-	int pre_load_noffset;
+-	const void *algo_name;
+-	const void *key_name;
+-	unsigned char *pubkey = NULL;
+-	int ret, pubkey_len;
+-
+-	if (!keydir || !keydest || !fit)
+-		return 0;
+-
+-	/* Search node pre-load sig */
+-	pre_load_noffset = fdt_path_offset(keydest, IMAGE_PRE_LOAD_PATH);
+-	if (pre_load_noffset < 0) {
+-		ret = 0;
+-		goto out;
+-	}
+-
+-	algo_name = fdt_getprop(keydest, pre_load_noffset, "algo-name", NULL);
+-	key_name  = fdt_getprop(keydest, pre_load_noffset, "key-name", NULL);
+-
+-	/* Check that all mandatory properties are present */
+-	if (!algo_name || !key_name) {
+-		if (!algo_name)
+-			printf("The property algo-name is missing in the node %s\n",
+-			       IMAGE_PRE_LOAD_PATH);
+-		if (!key_name)
+-			printf("The property key-name is missing in the node %s\n",
+-			       IMAGE_PRE_LOAD_PATH);
+-		ret = -EINVAL;
+-		goto out;
+-	}
+-
+-	/* Read public key */
+-	ret = read_pub_key(keydir, key_name, &pubkey, &pubkey_len);
+-	if (ret < 0)
+-		goto out;
+-
+-	/* Add the public key to the device tree */
+-	ret = fdt_setprop(keydest, pre_load_noffset, "public-key",
+-			  pubkey, pubkey_len);
+-	if (ret)
+-		printf("Can't set public-key in node %s (ret = %d)\n",
+-		       IMAGE_PRE_LOAD_PATH, ret);
+-
+- out:
+-	return ret;
+-}
+-
+ int fit_cipher_data(const char *keydir, void *keydest, void *fit,
+ 		    const char *comment, int require_keys,
+ 		    const char *engine_id, const char *cmdname)
--- a/5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch
@ -0,0 +1,125 @@
+--- a/Makefile
+++ b/Makefile
+@@ -413,13 +413,7 @@ PERL		= perl
+ PYTHON		?= python
+ PYTHON2		= python2
+ PYTHON3		?= python3
+-
+-# The devicetree compiler and pylibfdt are automatically built unless DTC is
+-# provided. If DTC is provided, it is assumed the pylibfdt is available too.
+-DTC_INTREE	:= $(objtree)/scripts/dtc/dtc
+-DTC		?= $(DTC_INTREE)
+-DTC_MIN_VERSION	:= 010406
+-
+DTC		?= $(objtree)/scripts/dtc/dtc
+ CHECK		= sparse
+ 
+ CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+@@ -2070,29 +2064,9 @@ endif
+ 
+ endif
+ 
+-# Check dtc and pylibfdt, if DTC is provided, else build them
+ PHONY += scripts_dtc
+ scripts_dtc: scripts_basic
+-	$(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+-		$(MAKE) $(build)=scripts/dtc; \
+-	else \
+-		if ! $(DTC) -v >/dev/null; then \
+-			echo '*** Failed to check dtc version: $(DTC)'; \
+-			false; \
+-		else \
+-			if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+-				echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+-				false; \
+-			else \
+-				if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+-					if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+-						echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+-						false; \
+-					fi; \
+-				fi; \
+-			fi; \
+-		fi; \
+-	fi
+	$(Q)$(MAKE) $(build)=scripts/dtc
+ 
+ # ---------------------------------------------------------------------------
+ quiet_cmd_cpp_lds = LDS     $@
+--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
+@@ -131,27 +131,6 @@ Further important build parameters are
+ * O=<dir> - generate all output files in directory <dir>, including .config
+ * V=1 - verbose build
+ 
+-Devicetree compiler
+-~~~~~~~~~~~~~~~~~~~
+-
+-Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the
+-devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python
+-library for accessing devicetree data. Suitable versions of these are included
+-in the U-Boot tree in `scripts/dtc` and built automatically as needed.
+-
+-To use the system versions of these, use the DTC parameter, for example
+-
+-.. code-block:: bash
+-
+-    DTC=/usr/bin/dtc make
+-
+-In this case, dtc and pylibfdt are not built. The build checks that the version
+-of dtc is new enough. It also makes sure that pylibfdt is present, if needed
+-(see `scripts_dtc` in the Makefile).
+-
+-Note that the :doc:`tools` are always built with the included version of libfdt
+-so it is not possible to build U-Boot tools with a system libfdt, at present.
+-
+ Other build targets
+ ~~~~~~~~~~~~~~~~~~~
+ 
+--- a/dts/Kconfig
+++ b/dts/Kconfig
+@@ -5,6 +5,9 @@
+ config SUPPORT_OF_CONTROL
+ 	bool
+ 
+config DTC
+	bool
+
+ config PYLIBFDT
+ 	bool
+ 
+@@ -21,6 +24,7 @@ menu "Device Tree Control"
+ 
+ config OF_CONTROL
+ 	bool "Run-time configuration via Device Tree"
+	select DTC
+ 	select OF_LIBFDT if !OF_PLATDATA
+ 	select OF_REAL if !OF_PLATDATA
+ 	help
+--- a/scripts/Makefile
+++ b/scripts/Makefile
+@@ -10,3 +10,4 @@ always		:= $(hostprogs-y)
+ 
+ # Let clean descend into subdirs
+ subdir-	+= basic kconfig dtc
+subdir-$(CONFIG_DTC)	+= dtc
+--- a/scripts/dtc-version.sh
+++ b/scripts/dtc-version.sh
+@@ -10,16 +10,11 @@
+ dtc="$*"
+ 
+ if [ ${#dtc} -eq 0 ]; then
+-	echo "Error: No dtc command specified"
+	echo "Error: No dtc command specified."
+ 	printf "Usage:\n\t$0 <dtc-command>\n"
+ 	exit 1
+ fi
+ 
+-if ! which $dtc >/dev/null ; then
+-	echo "Error: Cannot find dtc: $dtc"
+-	exit 1
+-fi
+-
+ MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
+ MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
+ PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
--- a/5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch
@ -0,0 +1,10 @@
+--- a/tools/Makefile
+++ b/tools/Makefile
+@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
+ 			imximage.o \
+ 			imx8image.o \
+ 			imx8mimage.o \
+-			kwbimage.o \
+ 			lib/md5.o \
+ 			lpc32xximage.o \
+ 			mxsimage.o \
--- a/5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch
@ -0,0 +1,27 @@
+From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sun, 17 Jan 2021 15:26:09 -0500
+Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT
+
+On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3
+CONFIG_USE_PREBOOT was enabled on the RockPro64.
+
+When the board is booting, U-Boot hangs as soon as it disables the USB
+controller. This is a workaround until a final solution is deployed
+upstream.
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ configs/rockpro64-rk3399_defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
+@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
+ CONFIG_SPL_SPI_SUPPORT=y
+ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
+ CONFIG_DEBUG_UART=y
+-CONFIG_USE_PREBOOT=y
+ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ CONFIG_MISC_INIT_R=y
--- a/5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch
@ -0,0 +1,740 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ 	rk3399-ficus.dtb \
+ 	rk3399-firefly.dtb \
+ 	rk3399-gru-bob.dtb \
+	rk3399-guangmiao-g4c.dtb \
+ 	rk3399-gru-kevin.dtb \
+ 	rk3399-khadas-edge.dtb \
+ 	rk3399-khadas-edge-captain.dtb \
+--- /dev/null
+++ b/configs/guangmiao-g4c-rk3399_defconfig
+@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+--- /dev/null
+++ b/arch/arm/dts/rk3399-guangmiao-g4c-u-boot.dtsi
+@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+	};
+};
+
+&sdmmc {
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
+
+&vdd_log {
+	regulator-init-microvolt = <950000>;
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3399-guangmiao-g4c.dts
+@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "SHAREVDI GuangMiao G4C";
+	compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
+
+	/delete-node/ display-subsystem;
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc_sys";
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sys";
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_0v9: vcc-0v9 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		regulator-name = "vcc_0v9";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_host0: vcc5v0-host0 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_host0";
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-name = "vdd_log";
+		vin-supply = <&vcc_sys>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&reset_button_pin>;
+
+		reset {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			wakeup-source;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
+
+		lan_led: led-lan {
+			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+			label = "green:lan";
+		};
+
+		status_led: led-status {
+			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+			label = "green:status";
+		};
+
+		wan_led: led-wan {
+			gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+			label = "green:wan";
+		};
+	};
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clock-parents = <&clkin_gmac>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
+	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_s3>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_cpu_b";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_gpu";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
+		#clock-cells = <1>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_3v0>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_center";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_cpu_l";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_vldo1: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_vldo1";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_vldo2: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_vldo2";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_sdio";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v0_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_sd";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vcc_1v5";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_3v0";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&io_domains {
+	bt656-supply = <&vcc_1v8>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pcie_phy {
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>;
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+	max-link-speed = <1>;
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqnb_cpm>;
+	vpcie0v9-supply = <&vcc_0v9>;
+	vpcie1v8-supply = <&vcca_1v8>;
+	vpcie3v3-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-leds {
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		status_led_pin: status-led-pin {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio {
+		bt_reg_on_h: bt-reg-on-h {
+			/* external pullup to VCC1V8_PMUPLL */
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		sdmmc0_det_l: sdmmc0-det-l {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "active";
+	pinctrl-0 = <&pwm2_pin_pull_down>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host0>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host0>;
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
--- a/5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch
@ -0,0 +1,174 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ 	rk3328-evb.dtb \
+ 	rk3328-nanopi-r2s.dtb \
+	rk3328-orangepi-r1-plus.dtb \
+ 	rk3328-roc-cc.dtb \
+ 	rk3328-rock64.dtb \
+ 	rk3328-rock-pi-e.dtb
+--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+@@ -0,0 +1,1 @@
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
+--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
+@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus";
+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+};
+
+&lan_led {
+	label = "orangepi-r1-plus:green:lan";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&sys_led {
+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+	label = "orangepi-r1-plus:red:sys";
+};
+
+&sys_led_pin {
+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&wan_led {
+	label = "orangepi-r1-plus:green:wan";
+};
+--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
+@@ -12,6 +12,13 @@ F:      configs/nanopi-r2s-rk3328_defconfig
+ F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+ F:      arch/arm/dts/rk3328-nanopi-r2s.dts
+ 
+ORANGEPI-R1-PLUS-RK3328
+M:      Shenzhen Xunlong Software CO.,Limited <zhao_steven@263.net>
+S:      Maintained
+F:      configs/orangepi-r1-plus-rk3328_defconfig
+F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+F:      arch/arm/dts/rk3328-orangepi-r1-plus.dts
+
+ ROC-RK3328-CC
+ M:      Loic Devulder <ldevulder@suse.com>
+ M:      Chen-Yu Tsai <wens@csie.org>
+--- /dev/null
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
+@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch
@ -0,0 +1,146 @@
+From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001
+From: baiywt <baiywt_gj@163.com>
+Date: Wed, 24 Nov 2021 19:59:38 +0800
+Subject: [PATCH] Add support for Orangepi R1 Plus LTS
+
+---
+ arch/arm/dts/Makefile                         |  1 +
+ arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts  |  7 ++
+ configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++
+ 3 files changed, 106 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+ create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index adfe6c3f..3d4e0f59 100644
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ 	rk3328-evb.dtb \
+ 	rk3328-nanopi-r2s.dtb \
+ 	rk3328-orangepi-r1-plus.dtb \
+	rk3328-orangepi-r1-plus-lts.dtb \
+ 	rk3328-roc-cc.dtb \
+ 	rk3328-rock64.dtb \
+ 	rk3328-rock-pi-e.dtb
+diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+new file mode 100644
+index 00000000..e6225b0c
+--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus LTS";
+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
+new file mode 100644
+index 00000000..3cb3b5c3
+--- /dev/null
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
+@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+-- 
+2.25.1
--- a/5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
@ -0,0 +1,184 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index d3e89ca3ba..d5f64ac432 100644
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+ 
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ 	rk3328-evb.dtb \
+	rk3328-nanopi-r2c.dtb \
+ 	rk3328-nanopi-r2s.dtb \
+ 	rk3328-orangepi-r1-plus.dtb \
+ 	rk3328-roc-cc.dtb \
+diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+new file mode 100644
+index 0000000000..c2e86d0f0e
+--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2021 Tianling Shen
+ */
+
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
+diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts
+new file mode 100644
+index 0000000000..adf91a0306
+--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
+@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2C";
+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+	phy-handle = <&yt8521s>;
+
+	mdio {
+		/delete-node/ ethernet-phy@1;
+
+		yt8521s: ethernet-phy@3 {
+			compatible = "ethernet-phy-id0000.011a",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&lan_led {
+	label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+	label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {
+	label = "nanopi-r2c:green:wan";
+};
+diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
+new file mode 100644
+index 0000000000..7bc7a3274f
+--- /dev/null
+++ b/configs/nanopi-r2c-rk3328_defconfig
+@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
@ -0,0 +1,113 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -157,6 +157,7 @@
+ 	rk3399-nanopi-m4b.dtb \
+ 	rk3399-nanopi-neo4.dtb \
+ 	rk3399-nanopi-r4s.dtb \
+	rk3399-nanopi-r4se.dtb \
+ 	rk3399-orangepi.dtb \
+ 	rk3399-pinebook-pro.dtb \
+ 	rk3399-puma-haikou.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4se.dts
+@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ *
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi-r4s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R4SE";
+	compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+&sdmmc {
+ pinctrl-0 = <&sdmmc_cd>;
+};
+--- /dev/null
+++ b/configs/nanopi-r4se-rk3399_defconfig
+@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch
@ -0,0 +1,68 @@
+--- /dev/null
+++ b/configs/rongpin-king3399-rk3399_defconfig
+@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch
@ -0,0 +1,784 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ 	rk3399-rock-pi-4b.dtb \
+ 	rk3399-rock-pi-4c.dtb \
+ 	rk3399-rock960.dtb \
+	rk3399-mpc1903.dtb \
+ 	rk3399-rockpro64.dtb \
+ 	rk3399pro-rock-pi-n10.dtb
+ 
+--- /dev/null
+++ b/arch/arm/dts/rk3399-mpc1903.dts
+@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Rocktech MPC1903";
+	compatible = "rocktech,mpc1903", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc12v_dcin: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc5v0_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_lan: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&status_led_pin>;
+
+		status_led: led-status-led {
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	hub_control {
+		compatible = "rocktech,hub-control";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hub_pwr>;
+		hub-pwr-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rmgii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_i2c_xfer>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			gen_1v8: LDO_REG1 {
+				regulator-name = "gen_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			gen_3v0: LDO_REG2 {
+				regulator-name = "gen_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_codec: LDO_REG7 {
+				regulator-name = "vcc1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rtc: pcf85263@51 {
+		compatible = "nxp,pcf85263";
+		reg = <0x51>;
+		pinctrl-0 = <&rtc_int>;
+		rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2s0 {
+	rockchip,i2s-broken-burst-len;
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	status = "okay";
+};
+
+&i2s2 {
+	rockchip,bclk-fs = <128>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcc1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	bt {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		hub_pwr: hub-pwr {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	wifi {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int: rtc-int {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	led {
+		status_led_pin: status-led-pin {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc_1v8>;
+};
+
+&sdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	clock-freq-min-max = <400000 150000000>;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	supports-sd;
+	disable-wp;
+	num-slots = <1>;
+	vqmmc-supply = <&vcc_sdio>;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	keep-power-in-suspend;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	supports-emmc;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+	rockchip,hw-tshut-temp = <120000>;
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3399-mpc1903-u-boot.dtsi
+@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+	};
+};
+
+&sdmmc {
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
+--- /dev/null
+++ b/configs/rocktech-mpc1903-rk3399_defconfig
+@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-mpc1903.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-mpc1903"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch
@ -0,0 +1,406 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+	rk3568-mrkaio-m68s.dtb \
+ 	rk3568-nanopi-r5s.dtb \
+ 	rk3566-quartz64-a.dtb \
+ 	rk3568-rock-3a.dtb
+--- /dev/null
+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi
+@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts
+@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-evb.dts"
+
+/ {
+	model = "EZPRO Mrkaio M68S";
+	compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+--- /dev/null
+++ b/configs/mrkaio-m68s-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch
@ -0,0 +1,415 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+	rk3568-opc-h68k.dtb \
+ 	rk3568-mrkaio-m68s.dtb \
+ 	rk3568-nanopi-r5s.dtb \
+ 	rk3566-quartz64-a.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi
+@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-opc-h68k.dts
+@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-evb.dts"
+
+/ {
+	model = "HINLINK OPC-H68K Board";
+	compatible = "hinlink,opc-h68k", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+--- /dev/null
+++ b/configs/opc-h68k-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch
@ -0,0 +1,140 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-bpi-r2-pro.dtb \
+ 	rk3568-evb.dtb \
+	rk3568-r66s.dtb \
+ 	rk3568-opc-h68k.dtb \
+ 	rk3568-mrkaio-m68s.dtb \
+ 	rk3568-nanopi-r5s.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3568-r66s-u-boot.dtsi
+@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-r66s.dts
+@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3568-evb.dts"
+--- /dev/null
+++ b/configs/r66s-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch
@ -0,0 +1,77 @@
+From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001
+From: huangjf <hjf@t-chip.com.cn>
+Date: Thu, 7 Apr 2022 16:22:56 +0800
+Subject: [PATCH] rockchip: rk3568: Add support for Station P2
+
+---
+ configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+ create mode 100644 configs/station-p2-rk3568_defconfig
+
+diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig
+new file mode 100644
+index 0000000000..435be99edf
+--- /dev/null
+++ b/configs/station-p2-rk3568_defconfig
+@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
+-- 
+2.20.1
--- a/5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch
@ -0,0 +1,154 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -177,7 +177,8 @@ rk3568-evb.dtb \
+ 	rk3568-mrkaio-m68s.dtb \
+ 	rk3568-nanopi-r5s.dtb \
+ 	rk3566-quartz64-a.dtb \
+-	rk3568-rock-3a.dtb
+	rk3568-rock-3a.dtb \
+	rk3568-radxa-e25.dtb
+ 
+ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
+ 	rv1108-elgin-r1.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-e25.dts
+@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3568-evb.dts"
+
+/ {
+	model = "Radxa E25";
+	compatible = "radxa,e25", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+};
+--- /dev/null
+++ b/configs/radxa-e25-rk3568_defconfig
+@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
--- a/5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch
+++ b/5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch
@ -0,0 +1,224 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -179,7 +179,8 @@
+ 	rk3568-photonicat.dtb \
+ 	rk3566-quartz64-a.dtb \
+ 	rk3568-rock-3a.dtb \
+-	rk3568-radxa-e25.dtb
+	rk3568-radxa-e25.dtb \
+	rk3568-nanopi-r5c.dtb
+ 
+ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
+ 	rv1108-elgin-r1.dtb \
+--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
+@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3568-evb.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R5C";
+	compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568";
+};
+--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,dm-spl;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-spl;
+	status = "okay";
+};
+--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
+@@ -18,6 +18,11 @@
+ 	help
+ 	  NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
+ 
+config TARGET_NANOPI_R5C_RK3568
+	bool "NanoPi R5C board"
+	help
+	  NanoPi R5C FriendlyElec is a board for Rockchp RK3568.
+
+ config TARGET_QUARTZ64_A_RK3566
+ 	bool "Quartz64 Model A RK3566 development board"
+ 	help
+@@ -40,6 +45,7 @@
+ source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
+ source "board/rockchip/evb_rk3568/Kconfig"
+ source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
+source "board/friendlyelec/nanopi-r5c-rk3568/Kconfig"
+ source "board/pine64/quartz64-a-rk3566/Kconfig"
+ 
+ endif
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Kconfig
+@@ -0,0 +1,15 @@
+if TARGET_NANOPI_R5C_RK3568
+
+config SYS_BOARD
+	default "nanopi-r5c-rk3568"
+
+config SYS_VENDOR
+	default "friendlyelec"
+
+config SYS_CONFIG_NAME
+	default "nanopi-r5c-rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Makefile
+@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= nanopi-r5c-rk3568.o
+--- /dev/null
+++ b/board/friendlyelec/nanopi-r5c-rk3568/nanopi-r5c-rk3568.c
+@@ -0,0 +1,4 @@
+ // SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ */
+--- /dev/null
+++ b/configs/nanopi-r5c-rk3568_defconfig
+@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_NANOPI_R5C_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
+--- /dev/null
+++ b/include/configs/nanopi-r5c-rk3568.h
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NANOPI_R5C_RK3568_H
+#define __NANOPI_R5C_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#endif
--- a/5.4/package/firmware/cypress-firmware/Makefile
+++ b/5.4/package/firmware/cypress-firmware/Makefile
@ -0,0 +1,486 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=cypress-firmware
+PKG_VERSION:=5.10.9-2022_0909
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=https://github.com/Infineon/ifx-linux-firmware/
+PKG_MIRROR_HASH:=944faae3a80013f1a963b6692d7f50a38c97edcf91fd163de521df755e6922b5
+PKG_SOURCE_VERSION:=release-v$(PKG_VERSION)
+
+PKG_MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>
+PKG_LICENSE_FILES:=LICENCE
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/cypress-firmware-default
+  SECTION:=firmware
+  CATEGORY:=Firmware
+  URL:=https://community.infineon.com/
+endef
+
+define Build/Compile
+	true
+endef
+
+# Cypress 43012 SDIO Firmware
+define Package/cypress-firmware-43012-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43012 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-43012-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43012-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43012-sdio.bin
+	$(LN) \
+		../cypress/cyfmac43012-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac43012-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43012-sdio))
+
+# Cypress 43340 SDIO Firmware
+define Package/cypress-firmware-43340-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43340 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-43340-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43340-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43340-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43340-sdio.bin
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43340-sdio))
+
+# Cypress 43362 SDIO Firmware
+define Package/cypress-firmware-43362-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43362 FullMac SDIO firmware
+  PROVIDES:=brcmfmac-firmware-43362-sdio
+  CONFLICTS:=brcmfmac-firmware-43362-sdio
+endef
+
+define Package/cypress-firmware-43362-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43362-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43362-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43362-sdio.bin
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43362-sdio))
+
+# Cypress 4339 SDIO Firmware
+define Package/cypress-firmware-4339-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4339 FullMac SDIO firmware
+  PROVIDES:=brcmfmac-firmware-4339-sdio
+  CONFLICTS:=brcmfmac-firmware-4339-sdio
+endef
+
+define Package/cypress-firmware-4339-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4339-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4339-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4339-sdio.bin
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4339-sdio))
+
+# Cypress 43430 SDIO Firmware
+define Package/cypress-firmware-43430-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43430 FullMac SDIO firmware
+  PROVIDES:=brcmfmac-firmware-43430-sdio
+  CONFLICTS:=brcmfmac-firmware-43430-sdio
+endef
+
+define Package/cypress-firmware-43430-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43430-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43430-sdio.bin
+	$(LN) \
+		../cypress/cyfmac43430-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac43430-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43430-sdio))
+
+# Cypress 43439 SDIO Firmware
+define Package/cypress-firmware-43439-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43439 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-43439-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43439-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43439-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43439-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43439-sdio.bin
+	$(LN) \
+		../cypress/cyfmac43439-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac43439-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43439-sdio))
+
+# Cypress 43455 SDIO Firmware
+define Package/cypress-firmware-43455-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43455 FullMac SDIO firmware
+  PROVIDES:=brcmfmac-firmware-43455-sdio
+  CONFLICTS:=brcmfmac-firmware-43455-sdio
+endef
+
+define Package/cypress-firmware-43455-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43455-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43455-sdio.bin
+	$(LN) \
+		../cypress/cyfmac43455-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac43455-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43455-sdio))
+
+# Cypress 4354 SDIO Firmware
+define Package/cypress-firmware-4354-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4354 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-4354-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4354-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4354-sdio.bin
+	$(LN) \
+		../cypress/cyfmac4354-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4354-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4354-sdio))
+
+# Cypress 4356 PCIe Firmware
+define Package/cypress-firmware-4356-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4356 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-4356-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4356-pcie.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4356-pcie.bin
+	$(LN) \
+		../cypress/cyfmac4356-pcie.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4356-pcie.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4356-pcie))
+
+# Cypress 4356 SDIO Firmware
+define Package/cypress-firmware-4356-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4356 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-4356-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4356-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4356-sdio.bin
+	$(LN) \
+		../cypress/cyfmac4356-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4356-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4356-sdio))
+
+# Cypress 43570 PCIe Firmware
+define Package/cypress-firmware-43570-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW43570 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-43570-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac43570-pcie.bin \
+		$(1)/lib/firmware/brcm/brcmfmac43570-pcie.bin
+	$(LN) \
+		../cypress/cyfmac43570-pcie.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac43570-pcie.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-43570-pcie))
+
+# Cypress 4373 PCIe Firmware
+define Package/cypress-firmware-4373-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4373 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-4373-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373-pcie.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373-pcie.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4373-pcie.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4373-pcie.bin
+	$(LN) \
+		../cypress/cyfmac4373-pcie.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4373-pcie.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4373-pcie))
+
+# Cypress 4373 SDIO Firmware
+define Package/cypress-firmware-4373-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4373 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-4373-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4373-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4373-sdio.bin
+	$(LN) \
+		../cypress/cyfmac4373-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4373-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4373-sdio))
+
+# Cypress 4373 USB Firmware
+define Package/cypress-firmware-4373-usb
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW4373 FullMac USB firmware
+endef
+
+define Package/cypress-firmware-4373-usb/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373-usb.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac4373.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4373-usb.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4373-usb.bin
+	$(LN) \
+		../cypress/cyfmac4373.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac4373.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-4373-usb))
+
+# Cypress 54591 PCIe Firmware
+define Package/cypress-firmware-54591-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW54591 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-54591-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac54591-pcie.bin \
+		$(1)/lib/firmware/brcm/brcmfmac54591-pcie.bin
+	$(LN) \
+		../cypress/cyfmac54591-pcie.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac54591-pcie.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-54591-pcie))
+
+# Cypress 54591 SDIO Firmware
+define Package/cypress-firmware-54591-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW54591 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-54591-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac54591-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac54591-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac54591-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac54591-sdio.bin
+	$(LN) \
+		../cypress/cyfmac54591-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac54591-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-54591-sdio))
+
+# Cypress 55560 PCIe Firmware
+define Package/cypress-firmware-55560-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW55560 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-55560-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac55560-pcie.trxse \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac55560-pcie.trxse \
+		$(1)/lib/firmware/brcm/brcmfmac55560-pcie.trxse
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-55560-pcie))
+
+# Cypress 55572 PCIe Firmware
+define Package/cypress-firmware-55572-pcie
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW55572 FullMac PCIe firmware
+endef
+
+define Package/cypress-firmware-55572-pcie/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac55572-pcie.trxse \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac55572-pcie.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac55572-pcie.trxse \
+		$(1)/lib/firmware/brcm/brcmfmac55572-pcie.trxse
+	$(LN) \
+		../cypress/cyfmac55572-pcie.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac55572-pcie.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-55572-pcie))
+
+# Cypress 55572 SDIO Firmware
+define Package/cypress-firmware-55572-sdio
+  $(Package/cypress-firmware-default)
+  TITLE:=CYW55572 FullMac SDIO firmware
+endef
+
+define Package/cypress-firmware-55572-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac55572-sdio.trxse \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/firmware/cyfmac55572-sdio.clm_blob \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac55572-sdio.trxse \
+		$(1)/lib/firmware/brcm/brcmfmac55572-sdio.trxse
+	$(LN) \
+		../cypress/cyfmac55572-sdio.clm_blob \
+		$(1)/lib/firmware/brcm/brcmfmac55572-sdio.clm_blob
+endef
+
+$(eval $(call BuildPackage,cypress-firmware-55572-sdio))
--- a/5.4/package/firmware/ipq-wifi/Makefile
+++ b/5.4/package/firmware/ipq-wifi/Makefile
@ -0,0 +1,121 @@
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/version.mk
+
+PKG_NAME:=ipq-wifi
+PKG_RELEASE:=1
+PKG_FLAGS:=nonshared
+
+include $(INCLUDE_DIR)/package.mk
+
+define Build/Prepare
+	mkdir -p $(PKG_BUILD_DIR)
+endef
+
+define Build/Compile
+endef
+
+# Use ath10k-bdencoder from https://github.com/qca/qca-swiss-army-knife.git
+# to generate the board-* files here.
+#
+# This is intended to be used on an interim basis until device-specific
+# board data for new devices is available through the upstream compilation
+#
+# Please send a mail with your device-specific board files upstream.
+# You can find instructions and examples on the linux-wireless wiki:
+# <https://wireless.wiki.kernel.org/en/users/drivers/ath10k/boardfiles>
+
+ALLWIFIBOARDS:= \
+	8dev_habanero-dvk \
+	aruba_ap-303 \
+	avm_fritzrepeater-1200 \
+	buffalo_wtr-m2133hp \
+	cellc_rtl30vw \
+	dlink_dap2610 \
+	engenius_eap2200 \
+	engenius_emd1 \
+	engenius_emr3500 \
+	ezviz_cs-w3-wd1200g-eup \
+	glinet_gl-s1300 \
+	linksys_ea8300 \
+	p2w_r619ac \
+	mobipromo_cm520-79f \
+	qxwlan_e2600ac \
+	teltonika_rutx
+
+ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ipq-wifi-$(BOARD))
+
+define Package/ipq-wifi-default
+  SUBMENU:=ath10k Board-Specific Overrides
+  SECTION:=firmware
+  CATEGORY:=Firmware
+  DEPENDS:=@TARGET_ipq40xx
+  TITLE:=Custom Board
+endef
+
+define ipq-wifi-install-one-to
+  $(INSTALL_DIR)  $(2)/lib/firmware/ath10k/$(3)/
+  $(INSTALL_DATA) $(1) $(2)/lib/firmware/ath10k/$(3)/board-2.bin
+endef
+
+define ipq-wifi-install-one
+  $(if $(filter $(suffix $(1)),.QCA4019 .qca4019),\
+    $(call ipq-wifi-install-one-to,$(1),$(2),QCA4019/hw1.0),\
+  $(if $(filter $(suffix $(1)),.QCA9888 .qca9888),\
+    $(call ipq-wifi-install-one-to,$(1),$(2),QCA9888/hw2.0),\
+  $(if $(filter $(suffix $(1)),.QCA9984 .qca9984),\
+    $(call ipq-wifi-install-one-to,$(1),$(2),QCA9984/hw1.0),\
+    $(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\
+  )))
+
+endef
+# Blank line required at end of above define due to foreach context
+
+define generate-ipq-wifi-package
+  define Package/ipq-wifi-$(1)
+    $(call Package/ipq-wifi-default)
+    TITLE:=board-2.bin Overrides for $(2)
+    CONFLICTS:=$(PREV_BOARD)
+  endef
+
+  define Package/ipq-wifi-$(1)/description
+The $(2) requires board-specific, reference ("cal") data
+that is not yet present in the upstream wireless firmware distribution.
+
+This package supplies board-2.bin file(s) that, in the interim,
+overwrite those supplied by the ath10k-firmware-* packages.
+
+This is package is only necessary for the $(2).
+
+Do not install it for any other device!
+  endef
+
+  define Package/ipq-wifi-$(1)/install-overlay
+    $$$$(foreach IPQ_WIFI_BOARD_FILE,$$$$(wildcard board-$(1).*),\
+      $$$$(call ipq-wifi-install-one,$$$$(IPQ_WIFI_BOARD_FILE),$$(1)))
+  endef
+
+  PREV_BOARD+=ipq-wifi-$(1)
+endef
+
+# Add board name to ALLWIFIBOARDS
+# Place files in this directory as board-<devicename>.<qca4019|qca9888|qca9984>
+# Add $(eval $(call generate-ipq-wifi-package,<devicename>,<display name>))
+
+$(eval $(call generate-ipq-wifi-package,8dev_habanero-dvk,8devices Habanero DVK))
+$(eval $(call generate-ipq-wifi-package,aruba_ap-303,Aruba AP-303))
+$(eval $(call generate-ipq-wifi-package,avm_fritzrepeater-1200,AVM FRITZRepeater 1200))
+$(eval $(call generate-ipq-wifi-package,buffalo_wtr-m2133hp,Buffalo WTR-M2133HP))
+$(eval $(call generate-ipq-wifi-package,cellc_rtl30vw, Cell C RTL30VW))
+$(eval $(call generate-ipq-wifi-package,dlink_dap2610,D-Link DAP-2610))
+$(eval $(call generate-ipq-wifi-package,engenius_eap2200,EnGenius EAP2200))
+$(eval $(call generate-ipq-wifi-package,engenius_emd1,EnGenius EMD1))
+$(eval $(call generate-ipq-wifi-package,engenius_emr3500,EnGenius EMR3500))
+$(eval $(call generate-ipq-wifi-package,ezviz_cs-w3-wd1200g-eup,EZVIZ CS-W3-WD1200G EUP))
+$(eval $(call generate-ipq-wifi-package,glinet_gl-s1300,GL.iNet GL-S1300))
+$(eval $(call generate-ipq-wifi-package,linksys_ea8300,Linksys EA8300))
+$(eval $(call generate-ipq-wifi-package,mobipromo_cm520-79f,MobiPromo CM520-79F))
+$(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac,Qxwlan E2600AC))
+$(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC))
+$(eval $(call generate-ipq-wifi-package,teltonika_rutx,Teltonika RUTX))
+
+$(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE))))
--- a/5.4/package/firmware/ipq-wifi/board-p2w_r619ac.qca4019
+++ b/5.4/package/firmware/ipq-wifi/board-p2w_r619ac.qca4019
--- a/5.4/package/firmware/ipq-wifi/board-teltonika_rutx.qca4019
+++ b/5.4/package/firmware/ipq-wifi/board-teltonika_rutx.qca4019
--- a/5.4/package/kernel/bcm27xx-gpu-fw/Makefile
+++ b/5.4/package/kernel/bcm27xx-gpu-fw/Makefile
@ -0,0 +1,185 @@
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=bcm27xx-gpu-fw
+PKG_VERSION:=2021-08-19
+PKG_RELEASE:=25e2b597ebfb2495eab4816a276758dcc6ea21f1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)/rpi-firmware-$(PKG_RELEASE)
+
+PKG_FLAGS:=nonshared
+
+include $(INCLUDE_DIR)/package.mk
+
+RPI_FIRMWARE_URL:=@GITHUB/raspberrypi/firmware/$(PKG_RELEASE)/boot/
+RPI_FIRMWARE_FILE:=rpi-firmware-$(PKG_RELEASE)
+
+define Download/LICENCE_broadcom
+  FILE:=$(RPI_FIRMWARE_FILE)-LICENCE.broadcom
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=LICENCE.broadcom
+  HASH:=c7283ff51f863d93a275c66e3b4cb08021a5dd4d8c1e7acc47d872fbe52d3d6b
+endef
+$(eval $(call Download,LICENCE_broadcom))
+
+define Download/bootcode_bin
+  FILE:=$(RPI_FIRMWARE_FILE)-bootcode.bin
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=bootcode.bin
+  HASH:=36fba28838867f26670a0cd1de340da62e13171cfdec0e7822737e849b3c0681
+endef
+$(eval $(call Download,bootcode_bin))
+
+define Download/fixup_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup.dat
+  HASH:=b06aa43aa668d6982de66044299d1b0dd6b449ec321dd83742aa1eb68774e15b
+endef
+$(eval $(call Download,fixup_dat))
+
+define Download/fixup_cd_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup_cd.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup_cd.dat
+  HASH:=fff4fd9fbb691100be46269f554acd866eac8cfef39082e03ac12f70fbfe9d95
+endef
+$(eval $(call Download,fixup_cd_dat))
+
+define Download/fixup_x_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup_x.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup_x.dat
+  HASH:=d74f97ae37cd476e6d4c8e466c3013be49e891e63b9aabc0c9b7637d85068cd0
+endef
+$(eval $(call Download,fixup_x_dat))
+
+define Download/fixup4_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup4.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup4.dat
+  HASH:=a607f4dc3000c188f8daaa3417c70a9e5ecc039fae36ba46807c00294f89cd24
+endef
+$(eval $(call Download,fixup4_dat))
+
+define Download/fixup4cd_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup4cd.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup4cd.dat
+  HASH:=fff4fd9fbb691100be46269f554acd866eac8cfef39082e03ac12f70fbfe9d95
+endef
+$(eval $(call Download,fixup4cd_dat))
+
+define Download/fixup4x_dat
+  FILE:=$(RPI_FIRMWARE_FILE)-fixup4x.dat
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=fixup4x.dat
+  HASH:=14ba09cba83d82a158481a7267fad06ada73c26c3a27dfd34694955f11ba6e27
+endef
+$(eval $(call Download,fixup4x_dat))
+
+define Download/start_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start.elf
+  HASH:=8bee170c56529bf1666ad4afdd18ae18c7123e7a2fd30e2992cd0d9a01fa63ee
+endef
+$(eval $(call Download,start_elf))
+
+define Download/start_cd_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start_cd.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start_cd.elf
+  HASH:=27d9354ff1af79a521527a288fe736f7337f91bca12bbc177c80e29dbbef0ffd
+endef
+$(eval $(call Download,start_cd_elf))
+
+define Download/start_x_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start_x.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start_x.elf
+  HASH:=499bfdf3deba7bb0a033d2a4487b7f05bce45de2692c7c6dabc4a456237fd438
+endef
+$(eval $(call Download,start_x_elf))
+
+define Download/start4_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start4.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start4.elf
+  HASH:=158bf783090223626cf45794bf679a3fadbf64bba55b76e3349b94e01be34202
+endef
+$(eval $(call Download,start4_elf))
+
+define Download/start4cd_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start4cd.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start4cd.elf
+  HASH:=c4912701f620cdd9e44bbacbfc4adb4be1b6fb7ccf81f6029ce2115511970cc0
+endef
+$(eval $(call Download,start4cd_elf))
+
+define Download/start4x_elf
+  FILE:=$(RPI_FIRMWARE_FILE)-start4x.elf
+  URL:=$(RPI_FIRMWARE_URL)
+  URL_FILE:=start4x.elf
+  HASH:=3eb1adb5dfef21da0a16679ef65314a64196a67c6fca3422df8bc721d6b6fa94
+endef
+$(eval $(call Download,start4x_elf))
+
+define Package/bcm27xx-gpu-fw
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_bcm27xx
+  TITLE:=bcm27xx-gpu-fw
+  DEFAULT:=y if TARGET_bcm27xx
+endef
+
+define Package/bcm27xx-gpu-fw/description
+ GPU and kernel boot firmware for bcm27xx.
+endef
+
+define Build/Prepare
+	rm -rf $(PKG_BUILD_DIR)
+	mkdir -p $(PKG_BUILD_DIR)
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-LICENCE.broadcom $(PKG_BUILD_DIR)/LICENCE.broadcom
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-bootcode.bin $(PKG_BUILD_DIR)/bootcode.bin
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup.dat $(PKG_BUILD_DIR)/fixup.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup_cd.dat $(PKG_BUILD_DIR)/fixup_cd.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup_x.dat $(PKG_BUILD_DIR)/fixup_x.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4.dat $(PKG_BUILD_DIR)/fixup4.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4cd.dat $(PKG_BUILD_DIR)/fixup4cd.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4x.dat $(PKG_BUILD_DIR)/fixup4x.dat
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start.elf $(PKG_BUILD_DIR)/start.elf
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start_cd.elf $(PKG_BUILD_DIR)/start_cd.elf
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start_x.elf $(PKG_BUILD_DIR)/start_x.elf
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4.elf $(PKG_BUILD_DIR)/start4.elf
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4cd.elf $(PKG_BUILD_DIR)/start4cd.elf
+	$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4x.elf $(PKG_BUILD_DIR)/start4x.elf
+endef
+
+define Build/Compile
+	true
+endef
+
+define Package/bcm27xx-gpu-fw/install
+	true
+endef
+
+define Build/InstallDev
+	$(CP) $(PKG_BUILD_DIR)/bootcode.bin $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/LICENCE.broadcom $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start_cd.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start_x.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start4.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start4cd.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/start4x.elf $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup.dat $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup_cd.dat $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup_x.dat $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup4.dat $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup4cd.dat $(KERNEL_BUILD_DIR)
+	$(CP) $(PKG_BUILD_DIR)/fixup4x.dat $(KERNEL_BUILD_DIR)
+endef
+
+$(eval $(call BuildPackage,bcm27xx-gpu-fw))
--- a/5.4/package/kernel/ksmbd/patches/010-fixes-build-on-6.1.patch
+++ b/5.4/package/kernel/ksmbd/patches/010-fixes-build-on-6.1.patch
@ -0,0 +1,14 @@
+--- a/smb1pdu.c
+++ b/smb1pdu.c
+@@ -5851,7 +5851,11 @@ static int smb_populate_readdir_entry(struct ksmbd_conn *conn, int info_level,
+  *
+  * Return:	0 on success, otherwise -EINVAL
+  */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
+static bool ksmbd_fill_dirent(struct dir_context *ctx, const char *name, int namlen,
+#else
+ static int ksmbd_fill_dirent(struct dir_context *ctx, const char *name, int namlen,
+#endif
+ 		loff_t offset, u64 ino, unsigned int d_type)
+ {
+ 	struct ksmbd_readdir_data *buf =
--- a/5.4/package/kernel/linux/modules/crypto.mk
+++ b/5.4/package/kernel/linux/modules/crypto.mk
@ -0,0 +1,964 @@
+#
+# Copyright (C) 2006-2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+CRYPTO_MENU:=Cryptographic API modules
+
+CRYPTO_MODULES = \
+	ALGAPI2=crypto_algapi \
+	BLKCIPHER2=crypto_blkcipher
+
+CRYPTO_TARGET = $(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)
+
+crypto_confvar=CONFIG_CRYPTO_$(word 1,$(subst =,$(space),$(1)))
+crypto_file=$(LINUX_DIR)/crypto/$(word 2,$(subst =,$(space),$(1))).ko
+crypto_name=$(if $(findstring y,$($(call crypto_confvar,$(1)))),,$(word 2,$(subst =,$(space),$(1))))
+
+define AddDepends/crypto
+  SUBMENU:=$(CRYPTO_MENU)
+  DEPENDS+= $(1)
+endef
+
+
+define KernelPackage/crypto-acompress
+  TITLE:=Asynchronous Compression operations
+  HIDDEN:=1
+  KCONFIG:=CONFIG_CRYPTO_ACOMP2
+  FILES:=$(LINUX_DIR)/crypto/crypto_acompress.ko
+  AUTOLOAD:=$(call AutoLoad,09,crypto_acompress)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-acompress))
+
+
+define KernelPackage/crypto-aead
+  TITLE:=CryptoAPI AEAD support
+  KCONFIG:= \
+	CONFIG_CRYPTO_AEAD \
+	CONFIG_CRYPTO_AEAD2
+  FILES:= \
+	  $(LINUX_DIR)/crypto/aead.ko \
+	  $(LINUX_DIR)/crypto/geniv.ko@ge5.10
+  AUTOLOAD:=$(call AutoLoad,09,aead,1)
+  $(call AddDepends/crypto, +kmod-crypto-null)
+endef
+
+$(eval $(call KernelPackage,crypto-aead))
+
+
+define KernelPackage/crypto-arc4
+  TITLE:=ARC4 cipher CryptoAPI module
+  KCONFIG:= \
+	  CONFIG_CRYPTO_ARC4 \
+	  CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+  FILES:= \
+	  $(LINUX_DIR)/crypto/arc4.ko \
+	  $(LINUX_DIR)/lib/crypto/libarc4.ko
+  AUTOLOAD:=$(call AutoLoad,09,arc4)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-arc4))
+
+
+define KernelPackage/crypto-authenc
+  TITLE:=Combined mode wrapper for IPsec
+  DEPENDS:=+kmod-crypto-manager +kmod-crypto-null
+  KCONFIG:=CONFIG_CRYPTO_AUTHENC
+  FILES:=$(LINUX_DIR)/crypto/authenc.ko
+  AUTOLOAD:=$(call AutoLoad,09,authenc)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-authenc))
+
+
+define KernelPackage/crypto-cbc
+  TITLE:=Cipher Block Chaining CryptoAPI module
+  DEPENDS:=+kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_CBC
+  FILES:=$(LINUX_DIR)/crypto/cbc.ko
+  AUTOLOAD:=$(call AutoLoad,09,cbc)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-cbc))
+
+
+define KernelPackage/crypto-ccm
+ TITLE:=Support for Counter with CBC MAC (CCM)
+ DEPENDS:=+kmod-crypto-ctr +kmod-crypto-aead
+ KCONFIG:=CONFIG_CRYPTO_CCM
+ FILES:=$(LINUX_DIR)/crypto/ccm.ko
+ AUTOLOAD:=$(call AutoLoad,09,ccm)
+ $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-ccm))
+
+
+define KernelPackage/crypto-cmac
+  TITLE:=Support for Cipher-based Message Authentication Code (CMAC)
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_CMAC
+  FILES:=$(LINUX_DIR)/crypto/cmac.ko
+  AUTOLOAD:=$(call AutoLoad,09,cmac)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-cmac))
+
+
+define KernelPackage/crypto-crc32
+  TITLE:=CRC32 CRC module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_CRC32
+  HIDDEN:=1
+  FILES:=$(LINUX_DIR)/crypto/crc32_generic.ko
+  AUTOLOAD:=$(call AutoLoad,04,crc32_generic,1)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-crc32))
+
+
+define KernelPackage/crypto-crc32c
+  TITLE:=CRC32c CRC module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_CRC32C
+  FILES:=$(LINUX_DIR)/crypto/crc32c_generic.ko
+  AUTOLOAD:=$(call AutoLoad,04,crc32c_generic,1)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-crc32c))
+
+
+define KernelPackage/crypto-ctr
+  TITLE:=Counter Mode CryptoAPI module
+  DEPENDS:=+kmod-crypto-manager +kmod-crypto-seqiv
+  KCONFIG:=CONFIG_CRYPTO_CTR
+  FILES:=$(LINUX_DIR)/crypto/ctr.ko
+  AUTOLOAD:=$(call AutoLoad,09,ctr)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-ctr))
+
+
+define KernelPackage/crypto-cts
+  TITLE:=Cipher Text Stealing CryptoAPI module
+  DEPENDS:=+kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_CTS
+  FILES:=$(LINUX_DIR)/crypto/cts.ko
+  AUTOLOAD:=$(call AutoLoad,09,cts)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-cts))
+
+
+define KernelPackage/crypto-deflate
+  TITLE:=Deflate compression CryptoAPI module
+  DEPENDS:=+kmod-lib-zlib-inflate +kmod-lib-zlib-deflate +kmod-crypto-acompress
+  KCONFIG:=CONFIG_CRYPTO_DEFLATE
+  FILES:=$(LINUX_DIR)/crypto/deflate.ko
+  AUTOLOAD:=$(call AutoLoad,09,deflate)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-deflate))
+
+
+define KernelPackage/crypto-des
+  TITLE:=DES/3DES cipher CryptoAPI module
+  KCONFIG:=CONFIG_CRYPTO_DES
+  FILES:= \
+	$(LINUX_DIR)/crypto/des_generic.ko \
+	$(LINUX_DIR)/lib/crypto/libdes.ko
+  AUTOLOAD:=$(call AutoLoad,09,des_generic)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-des))
+
+
+define KernelPackage/crypto-ecb
+  TITLE:=Electronic CodeBook CryptoAPI module
+  DEPENDS:=+kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_ECB
+  FILES:=$(LINUX_DIR)/crypto/ecb.ko
+  AUTOLOAD:=$(call AutoLoad,09,ecb)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-ecb))
+
+
+define KernelPackage/crypto-ecdh
+  TITLE:=ECDH algorithm
+  DEPENDS:=+kmod-crypto-kpp
+  KCONFIG:= CONFIG_CRYPTO_ECDH
+  FILES:= \
+	$(LINUX_DIR)/crypto/ecdh_generic.ko \
+	$(LINUX_DIR)/crypto/ecc.ko
+  AUTOLOAD:=$(call AutoLoad,10,ecdh_generic)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-ecdh))
+
+
+define KernelPackage/crypto-echainiv
+  TITLE:=Encrypted Chain IV Generator
+  DEPENDS:=+kmod-crypto-aead
+  KCONFIG:=CONFIG_CRYPTO_ECHAINIV
+  FILES:=$(LINUX_DIR)/crypto/echainiv.ko
+  AUTOLOAD:=$(call AutoLoad,09,echainiv)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-echainiv))
+
+
+define KernelPackage/crypto-fcrypt
+  TITLE:=FCRYPT cipher CryptoAPI module
+  KCONFIG:=CONFIG_CRYPTO_FCRYPT
+  FILES:=$(LINUX_DIR)/crypto/fcrypt.ko
+  AUTOLOAD:=$(call AutoLoad,09,fcrypt)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-fcrypt))
+
+
+define KernelPackage/crypto-gcm
+  TITLE:=GCM/GMAC CryptoAPI module
+  DEPENDS:=+kmod-crypto-ctr +kmod-crypto-ghash +kmod-crypto-null
+  KCONFIG:=CONFIG_CRYPTO_GCM
+  FILES:=$(LINUX_DIR)/crypto/gcm.ko
+  AUTOLOAD:=$(call AutoLoad,09,gcm)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-gcm))
+
+
+define KernelPackage/crypto-xcbc
+  TITLE:=XCBC CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_XCBC
+  FILES:=$(LINUX_DIR)/crypto/xcbc.ko
+  AUTOLOAD:=$(call AutoLoad,09,xcbc)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-xcbc))
+
+
+define KernelPackage/crypto-gf128
+  TITLE:=GF(2^128) multiplication functions CryptoAPI module
+  KCONFIG:=CONFIG_CRYPTO_GF128MUL
+  FILES:=$(LINUX_DIR)/crypto/gf128mul.ko
+  AUTOLOAD:=$(call AutoLoad,09,gf128mul)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-gf128))
+
+
+define KernelPackage/crypto-ghash
+  TITLE:=GHASH digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-gf128 +kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_GHASH \
+	CONFIG_CRYPTO_GHASH_ARM_CE
+  FILES:=$(LINUX_DIR)/crypto/ghash-generic.ko
+  AUTOLOAD:=$(call AutoLoad,09,ghash-generic)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-ghash/arm-ce
+  FILES+= $(LINUX_DIR)/arch/arm/crypto/ghash-arm-ce.ko
+  AUTOLOAD+=$(call AutoLoad,09,ghash-arm-ce)
+endef
+
+KernelPackage/crypto-ghash/imx6=$(KernelPackage/crypto-ghash/arm-ce)
+KernelPackage/crypto-ghash/ipq40xx=$(KernelPackage/crypto-ghash/arm-ce)
+KernelPackage/crypto-ghash/mvebu/cortexa9=$(KernelPackage/crypto-ghash/arm-ce)
+
+$(eval $(call KernelPackage,crypto-ghash))
+
+
+define KernelPackage/crypto-hash
+  TITLE:=CryptoAPI hash support
+  KCONFIG:=CONFIG_CRYPTO_HASH
+  FILES:=$(LINUX_DIR)/crypto/crypto_hash.ko
+  AUTOLOAD:=$(call AutoLoad,02,crypto_hash,1)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hash))
+
+
+define KernelPackage/crypto-hmac
+  TITLE:=HMAC digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_HMAC
+  FILES:=$(LINUX_DIR)/crypto/hmac.ko
+  AUTOLOAD:=$(call AutoLoad,09,hmac)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hmac))
+
+
+define KernelPackage/crypto-hw-ccp
+  TITLE:=AMD Cryptographic Coprocessor
+  DEPENDS:= \
+	@TARGET_x86 \
+	+kmod-crypto-authenc \
+	+kmod-crypto-hash \
+	+kmod-crypto-manager \
+	+kmod-crypto-rsa \
+	+kmod-crypto-sha1 \
+	+kmod-crypto-sha256 \
+	+kmod-random-core
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_CCP=y \
+	CONFIG_CRYPTO_DEV_CCP_CRYPTO \
+	CONFIG_CRYPTO_DEV_CCP_DD \
+	CONFIG_CRYPTO_DEV_SP_CCP=y
+  FILES:= \
+	$(LINUX_DIR)/drivers/crypto/ccp/ccp.ko \
+	$(LINUX_DIR)/drivers/crypto/ccp/ccp-crypto.ko
+  AUTOLOAD:=$(call AutoLoad,09,ccp ccp-crypto)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hw-ccp))
+
+
+define KernelPackage/crypto-hw-geode
+  TITLE:=AMD Geode hardware crypto module
+  DEPENDS:=@TARGET_x86_geode +kmod-crypto-manager
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_GEODE
+  FILES:=$(LINUX_DIR)/drivers/crypto/geode-aes.ko
+  AUTOLOAD:=$(call AutoLoad,09,geode-aes)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hw-geode))
+
+
+define KernelPackage/crypto-hw-hifn-795x
+  TITLE:=HIFN 795x crypto accelerator
+  DEPENDS:=@PCI_SUPPORT +kmod-random-core +kmod-crypto-manager
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_HIFN_795X \
+	CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+  FILES:=$(LINUX_DIR)/drivers/crypto/hifn_795x.ko
+  AUTOLOAD:=$(call AutoLoad,09,hifn_795x)
+  $(call AddDepends/crypto,+kmod-crypto-des)
+endef
+
+$(eval $(call KernelPackage,crypto-hw-hifn-795x))
+
+
+define KernelPackage/crypto-hw-padlock
+  TITLE:=VIA PadLock ACE with AES/SHA hw crypto module
+  DEPENDS:=+kmod-crypto-manager
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_PADLOCK \
+	CONFIG_CRYPTO_DEV_PADLOCK_AES \
+	CONFIG_CRYPTO_DEV_PADLOCK_SHA
+  FILES:= \
+	$(LINUX_DIR)/drivers/crypto/padlock-aes.ko \
+	$(LINUX_DIR)/drivers/crypto/padlock-sha.ko
+  AUTOLOAD:=$(call AutoLoad,09,padlock-aes padlock-sha)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hw-padlock))
+
+
+define KernelPackage/crypto-hw-safexcel
+  TITLE:= MVEBU SafeXcel Crypto Engine module
+  DEPENDS:=@(TARGET_mvebu_cortexa53||TARGET_mvebu_cortexa72) +eip197-mini-firmware \
+	+kmod-crypto-authenc +kmod-crypto-md5 +kmod-crypto-hmac +kmod-crypto-sha256 +kmod-crypto-sha512
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_SAFEXCEL
+  FILES:=$(LINUX_DIR)/drivers/crypto/inside-secure/crypto_safexcel.ko
+  AUTOLOAD:=$(call AutoLoad,90,crypto_safexcel)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-hw-safexcel/description
+MVEBU's EIP97 and EIP197 Cryptographic Engine driver designed by
+Inside Secure. This is found on Marvell Armada 37xx/7k/8k SoCs.
+
+Particular version of these IP (EIP197B and EIP197D) require firmware.
+The mini firmware package provides limited functionality, for most operations
+a full-featured firmware is required. Unfortunately the "full" firmware is not
+freely available and needs signed Non-Disclosure Agreement (NDA) with Marvell.
+For those who have signed NDA the firmware can be obtained at
+https://extranet.marvell.com.
+endef
+
+$(eval $(call KernelPackage,crypto-hw-safexcel))
+
+
+define KernelPackage/crypto-hw-talitos
+  TITLE:=Freescale integrated security engine (SEC) driver
+  DEPENDS:=@(TARGET_mpc85xx||TARGET_layerscape) +kmod-crypto-manager \
+	+kmod-crypto-hash +kmod-random-core +kmod-crypto-authenc +kmod-crypto-des
+  KCONFIG:= \
+	CONFIG_CRYPTO_HW=y \
+	CONFIG_CRYPTO_DEV_TALITOS \
+	CONFIG_CRYPTO_DEV_TALITOS1=y \
+	CONFIG_CRYPTO_DEV_TALITOS2=y
+  FILES:= \
+	$(LINUX_DIR)/drivers/crypto/talitos.ko
+  AUTOLOAD:=$(call AutoLoad,09,talitos)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-hw-talitos))
+
+
+define KernelPackage/crypto-kpp
+  TITLE:=Key-agreement Protocol Primitives
+  KCONFIG:=CONFIG_CRYPTO_KPP
+  FILES:=$(LINUX_DIR)/crypto/kpp.ko
+  AUTOLOAD:=$(call AutoLoad,09,kpp)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-kpp))
+
+define KernelPackage/crypto-lib-chacha20
+  TITLE:=ChaCha library interface
+  KCONFIG:=CONFIG_CRYPTO_LIB_CHACHA
+  HIDDEN:=1
+  FILES:=$(LINUX_DIR)/lib/crypto/libchacha.ko
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-lib-chacha20/x86_64
+  KCONFIG+=CONFIG_CRYPTO_CHACHA20_X86_64
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/chacha-x86_64.ko
+endef
+
+# Note that a non-neon fallback implementation is available on arm32 when
+# NEON is not supported, hence all arm targets can utilize lib-chacha20/arm
+define KernelPackage/crypto-lib-chacha20/arm
+  KCONFIG+=CONFIG_CRYPTO_CHACHA20_NEON
+  FILES:=$(LINUX_DIR)/arch/arm/crypto/chacha-neon.ko
+endef
+
+define KernelPackage/crypto-lib-chacha20/aarch64
+  KCONFIG+=CONFIG_CRYPTO_CHACHA20_NEON
+  FILES+=$(LINUX_DIR)/arch/arm64/crypto/chacha-neon.ko
+endef
+
+define KernelPackage/crypto-lib-chacha20/mips32r2
+  KCONFIG+=CONFIG_CRYPTO_CHACHA_MIPS
+  FILES:=$(LINUX_DIR)/arch/mips/crypto/chacha-mips.ko
+endef
+
+ifeq ($(CONFIG_CPU_MIPS32_R2),y)
+  KernelPackage/crypto-lib-chacha20/$(ARCH)=\
+	  $(KernelPackage/crypto-lib-chacha20/mips32r2)
+endif
+
+ifdef KernelPackage/crypto-lib-chacha20/$(ARCH)
+  KernelPackage/crypto-lib-chacha20/$(CRYPTO_TARGET)=\
+	  $(KernelPackage/crypto-lib-chacha20/$(ARCH))
+endif
+
+$(eval $(call KernelPackage,crypto-lib-chacha20))
+
+
+define KernelPackage/crypto-lib-chacha20poly1305
+  TITLE:=ChaCha20-Poly1305 AEAD support (8-byte nonce library version)
+  KCONFIG:=CONFIG_CRYPTO_LIB_CHACHA20POLY1305
+  HIDDEN:=1
+  FILES:=$(LINUX_DIR)/lib/crypto/libchacha20poly1305.ko
+  $(call AddDepends/crypto, +kmod-crypto-lib-chacha20 +kmod-crypto-lib-poly1305)
+endef
+
+$(eval $(call KernelPackage,crypto-lib-chacha20poly1305))
+
+
+define KernelPackage/crypto-lib-curve25519
+  TITLE:=Curve25519 scalar multiplication library
+  KCONFIG:=CONFIG_CRYPTO_LIB_CURVE25519
+  HIDDEN:=1
+  FILES:= \
+	$(LINUX_DIR)/lib/crypto/libcurve25519.ko \
+	$(LINUX_DIR)/lib/crypto/libcurve25519-generic.ko
+  $(call AddDepends/crypto,+PACKAGE_kmod-crypto-kpp:kmod-crypto-kpp)
+endef
+
+define KernelPackage/crypto-lib-curve25519/config
+  imply PACKAGE_kmod-crypto-kpp
+endef
+
+define KernelPackage/crypto-lib-curve25519/x86/64
+  KCONFIG+=CONFIG_CRYPTO_CURVE25519_X86
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/curve25519-x86_64.ko
+endef
+
+define KernelPackage/crypto-lib-curve25519/arm-neon
+  KCONFIG+=CONFIG_CRYPTO_CURVE25519_NEON
+  FILES+=$(LINUX_DIR)/arch/arm/crypto/curve25519-neon.ko
+endef
+
+ifeq ($(ARCH)-$(CONFIG_KERNEL_MODE_NEON),arm-y)
+  KernelPackage/crypto-lib-curve25519/$(CRYPTO_TARGET)=\
+	  $(KernelPackage/crypto-lib-curve25519/arm-neon)
+endif
+
+$(eval $(call KernelPackage,crypto-lib-curve25519))
+
+
+define KernelPackage/crypto-lib-poly1305
+  TITLE:=Poly1305 library interface
+  KCONFIG:=CONFIG_CRYPTO_LIB_POLY1305
+  HIDDEN:=1
+  FILES:=$(LINUX_DIR)/lib/crypto/libpoly1305.ko
+  $(call AddDepends/crypto,+PACKAGE_kmod-crypto-hash:kmod-crypto-hash)
+endef
+
+define KernelPackage/crypto-lib-poly1305/config
+  imply PACKAGE_kmod-crypto-hash
+endef
+
+define KernelPackage/crypto-lib-poly1305/x86_64
+  KCONFIG+=CONFIG_CRYPTO_POLY1305_X86_64
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/poly1305-x86_64.ko
+endef
+
+define KernelPackage/crypto-lib-poly1305/arm
+  KCONFIG+=CONFIG_CRYPTO_POLY1305_ARM
+  FILES:=$(LINUX_DIR)/arch/arm/crypto/poly1305-arm.ko
+endef
+
+define KernelPackage/crypto-lib-poly1305/aarch64
+  KCONFIG+=CONFIG_CRYPTO_POLY1305_NEON
+  FILES:=$(LINUX_DIR)/arch/arm64/crypto/poly1305-neon.ko
+endef
+
+define KernelPackage/crypto-lib-poly1305/mips
+  KCONFIG+=CONFIG_CRYPTO_POLY1305_MIPS
+  FILES:=$(LINUX_DIR)/arch/mips/crypto/poly1305-mips.ko
+endef
+
+KernelPackage/crypto-lib-poly1305/mipsel=$(KernelPackage/crypto-lib-poly1305/mips)
+KernelPackage/crypto-lib-poly1305/mips64=$(KernelPackage/crypto-lib-poly1305/mips)
+KernelPackage/crypto-lib-poly1305/mips64el=$(KernelPackage/crypto-lib-poly1305/mips)
+
+ifdef KernelPackage/crypto-lib-poly1305/$(ARCH)
+  KernelPackage/crypto-lib-poly1305/$(CRYPTO_TARGET)=\
+	  $(KernelPackage/crypto-lib-poly1305/$(ARCH))
+endif
+
+$(eval $(call KernelPackage,crypto-lib-poly1305))
+
+
+define KernelPackage/crypto-manager
+  TITLE:=CryptoAPI algorithm manager
+  DEPENDS:=+kmod-crypto-aead +kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_MANAGER \
+	CONFIG_CRYPTO_MANAGER2
+  FILES:=$(LINUX_DIR)/crypto/cryptomgr.ko
+  AUTOLOAD:=$(call AutoLoad,09,cryptomgr,1)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-manager))
+
+
+define KernelPackage/crypto-md4
+  TITLE:=MD4 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_MD4
+  FILES:=$(LINUX_DIR)/crypto/md4.ko
+  AUTOLOAD:=$(call AutoLoad,09,md4)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-md4))
+
+
+define KernelPackage/crypto-md5
+  TITLE:=MD5 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_MD5 \
+	CONFIG_CRYPTO_MD5_OCTEON
+  FILES:=$(LINUX_DIR)/crypto/md5.ko
+  AUTOLOAD:=$(call AutoLoad,09,md5)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-md5/octeon
+  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko
+  AUTOLOAD+=$(call AutoLoad,09,octeon-md5)
+endef
+
+$(eval $(call KernelPackage,crypto-md5))
+
+
+define KernelPackage/crypto-michael-mic
+  TITLE:=Michael MIC keyed digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_MICHAEL_MIC
+  FILES:=$(LINUX_DIR)/crypto/michael_mic.ko
+  AUTOLOAD:=$(call AutoLoad,09,michael_mic)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-michael-mic))
+
+
+define KernelPackage/crypto-misc
+  TITLE:=Other CryptoAPI modules
+  DEPENDS:=+kmod-crypto-xts
+  KCONFIG:= \
+	CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y \
+	CONFIG_CRYPTO_CAMELLIA_X86_64 \
+	CONFIG_CRYPTO_BLOWFISH_X86_64 \
+	CONFIG_CRYPTO_TWOFISH_X86_64 \
+	CONFIG_CRYPTO_TWOFISH_X86_64_3WAY \
+	CONFIG_CRYPTO_SERPENT_SSE2_X86_64 \
+	CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 \
+	CONFIG_CRYPTO_CAST5_AVX_X86_64 \
+	CONFIG_CRYPTO_CAST6_AVX_X86_64 \
+	CONFIG_CRYPTO_TWOFISH_AVX_X86_64 \
+	CONFIG_CRYPTO_SERPENT_AVX_X86_64 \
+	CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 \
+	CONFIG_CRYPTO_SERPENT_AVX2_X86_64 \
+	CONFIG_CRYPTO_SERPENT_SSE2_586 \
+	CONFIG_CRYPTO_ANUBIS \
+	CONFIG_CRYPTO_BLOWFISH \
+	CONFIG_CRYPTO_CAMELLIA \
+	CONFIG_CRYPTO_CAST5 \
+	CONFIG_CRYPTO_CAST6 \
+	CONFIG_CRYPTO_FCRYPT \
+	CONFIG_CRYPTO_KHAZAD \
+	CONFIG_CRYPTO_SERPENT \
+	CONFIG_CRYPTO_TEA \
+	CONFIG_CRYPTO_TGR192 \
+	CONFIG_CRYPTO_TWOFISH \
+	CONFIG_CRYPTO_TWOFISH_COMMON \
+	CONFIG_CRYPTO_TWOFISH_586 \
+	CONFIG_CRYPTO_WP512
+  FILES:= \
+	$(LINUX_DIR)/crypto/anubis.ko \
+	$(LINUX_DIR)/crypto/camellia_generic.ko \
+	$(LINUX_DIR)/crypto/cast_common.ko \
+	$(LINUX_DIR)/crypto/cast5_generic.ko \
+	$(LINUX_DIR)/crypto/cast6_generic.ko \
+	$(LINUX_DIR)/crypto/khazad.ko \
+	$(LINUX_DIR)/crypto/tea.ko \
+	$(LINUX_DIR)/crypto/tgr192.ko@lt5.14 \
+	$(LINUX_DIR)/crypto/twofish_common.ko \
+	$(LINUX_DIR)/crypto/wp512.ko \
+	$(LINUX_DIR)/crypto/twofish_generic.ko \
+	$(LINUX_DIR)/crypto/blowfish_common.ko \
+	$(LINUX_DIR)/crypto/blowfish_generic.ko \
+	$(LINUX_DIR)/crypto/serpent_generic.ko
+  AUTOLOAD:=$(call AutoLoad,10,anubis camellia_generic cast_common \
+	cast5_generic cast6_generic khazad tea tgr192 twofish_common \
+	wp512 blowfish_common serpent_generic)
+  ifndef CONFIG_TARGET_x86
+	AUTOLOAD+= $(call AutoLoad,10,twofish_generic blowfish_generic)
+  endif
+  $(call AddDepends/crypto)
+endef
+
+ifndef CONFIG_TARGET_x86_64
+  define KernelPackage/crypto-misc/x86
+    FILES+= \
+	$(LINUX_DIR)/arch/x86/crypto/twofish-i586.ko \
+	$(LINUX_DIR)/arch/x86/crypto/serpent-sse2-i586.ko \
+	$(LINUX_DIR)/arch/x86/crypto/glue_helper.ko@lt5.14 \
+	$(LINUX_DIR)/crypto/cryptd.ko \
+	$(LINUX_DIR)/crypto/crypto_simd.ko
+    AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper \
+	serpent-sse2-i586 twofish-i586 blowfish_generic)
+  endef
+endif
+
+define KernelPackage/crypto-misc/x86/64
+  FILES+= \
+	$(LINUX_DIR)/arch/x86/crypto/camellia-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/blowfish-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/twofish-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/twofish-x86_64-3way.ko \
+	$(LINUX_DIR)/arch/x86/crypto/serpent-sse2-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/camellia-aesni-avx-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/cast5-avx-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/cast6-avx-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/twofish-avx-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/serpent-avx-x86_64.ko \
+	$(LINUX_DIR)/arch/x86/crypto/camellia-aesni-avx2.ko \
+	$(LINUX_DIR)/arch/x86/crypto/serpent-avx2.ko
+  AUTOLOAD+= $(call AutoLoad,10,camellia-x86_64 \
+	camellia-aesni-avx-x86_64 camellia-aesni-avx2 cast5-avx-x86_64 \
+	cast6-avx-x86_64 twofish-x86_64 twofish-x86_64-3way \
+	twofish-avx-x86_64 blowfish-x86_64 serpent-avx-x86_64 serpent-avx2)
+endef
+
+$(eval $(call KernelPackage,crypto-misc))
+
+
+define KernelPackage/crypto-null
+  TITLE:=Null CryptoAPI module
+  KCONFIG:=CONFIG_CRYPTO_NULL
+  FILES:=$(LINUX_DIR)/crypto/crypto_null.ko
+  AUTOLOAD:=$(call AutoLoad,09,crypto_null)
+  $(call AddDepends/crypto, +kmod-crypto-hash)
+endef
+
+$(eval $(call KernelPackage,crypto-null))
+
+
+define KernelPackage/crypto-pcbc
+  TITLE:=Propagating Cipher Block Chaining CryptoAPI module
+  DEPENDS:=+kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_PCBC
+  FILES:=$(LINUX_DIR)/crypto/pcbc.ko
+  AUTOLOAD:=$(call AutoLoad,09,pcbc)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-pcbc))
+
+
+define KernelPackage/crypto-rsa
+  TITLE:=RSA algorithm
+  DEPENDS:=+kmod-crypto-manager +kmod-asn1-decoder
+  KCONFIG:= CONFIG_CRYPTO_RSA
+  HIDDEN:=1
+  FILES:= \
+	$(LINUX_DIR)/lib/mpi/mpi.ko \
+	$(LINUX_DIR)/crypto/akcipher.ko \
+	$(LINUX_DIR)/crypto/rsa_generic.ko
+  AUTOLOAD:=$(call AutoLoad,10,rsa_generic)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-rsa))
+
+
+define KernelPackage/crypto-rmd160
+  TITLE:=RIPEMD160 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:=CONFIG_CRYPTO_RMD160
+  FILES:=$(LINUX_DIR)/crypto/rmd160.ko
+  AUTOLOAD:=$(call AutoLoad,09,rmd160)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-rmd160))
+
+
+define KernelPackage/crypto-rng
+  TITLE:=CryptoAPI random number generation
+  DEPENDS:=+kmod-crypto-hash +kmod-crypto-hmac +kmod-crypto-sha256
+  KCONFIG:= \
+	CONFIG_CRYPTO_DRBG \
+	CONFIG_CRYPTO_DRBG_HMAC=y \
+	CONFIG_CRYPTO_DRBG_HASH=n \
+	CONFIG_CRYPTO_DRBG_MENU \
+	CONFIG_CRYPTO_JITTERENTROPY \
+	CONFIG_CRYPTO_RNG2
+  FILES:= \
+	$(LINUX_DIR)/crypto/drbg.ko \
+	$(LINUX_DIR)/crypto/jitterentropy_rng.ko \
+	$(LINUX_DIR)/crypto/rng.ko
+  AUTOLOAD:=$(call AutoLoad,09,drbg jitterentropy_rng rng)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-rng))
+
+
+define KernelPackage/crypto-seqiv
+  TITLE:=CryptoAPI Sequence Number IV Generator
+  DEPENDS:=+kmod-crypto-aead +kmod-crypto-rng
+  KCONFIG:=CONFIG_CRYPTO_SEQIV
+  FILES:=$(LINUX_DIR)/crypto/seqiv.ko
+  AUTOLOAD:=$(call AutoLoad,09,seqiv)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-seqiv))
+
+
+define KernelPackage/crypto-sha1
+  TITLE:=SHA1 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_SHA1 \
+	CONFIG_CRYPTO_SHA1_ARM \
+	CONFIG_CRYPTO_SHA1_ARM_NEON \
+	CONFIG_CRYPTO_SHA1_OCTEON \
+	CONFIG_CRYPTO_SHA1_SSSE3
+  FILES:=$(LINUX_DIR)/crypto/sha1_generic.ko
+  AUTOLOAD:=$(call AutoLoad,09,sha1_generic)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-sha1/arm
+  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha1-arm.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha1-arm)
+endef
+
+define KernelPackage/crypto-sha1/arm-neon
+  $(call KernelPackage/crypto-sha1/arm)
+  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha1-arm-neon.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha1-arm-neon)
+endef
+
+KernelPackage/crypto-sha1/imx6=$(KernelPackage/crypto-sha1/arm-neon)
+KernelPackage/crypto-sha1/ipq40xx=$(KernelPackage/crypto-sha1/arm-neon)
+KernelPackage/crypto-sha1/mvebu/cortexa9=$(KernelPackage/crypto-sha1/arm-neon)
+
+define KernelPackage/crypto-sha1/octeon
+  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha1.ko
+  AUTOLOAD+=$(call AutoLoad,09,octeon-sha1)
+endef
+
+KernelPackage/crypto-sha1/tegra=$(KernelPakcage/crypto-sha1/arm)
+
+define KernelPackage/crypto-sha1/x86/64
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha1-ssse3.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha1-ssse3)
+endef
+
+$(eval $(call KernelPackage,crypto-sha1))
+
+
+define KernelPackage/crypto-sha256
+  TITLE:=SHA224 SHA256 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_SHA256 \
+	CONFIG_CRYPTO_SHA256_OCTEON \
+	CONFIG_CRYPTO_SHA256_SSSE3
+  FILES:= \
+	$(LINUX_DIR)/crypto/sha256_generic.ko \
+	$(LINUX_DIR)/lib/crypto/libsha256.ko
+  AUTOLOAD:=$(call AutoLoad,09,sha256_generic)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-sha256/octeon
+  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha256.ko
+  AUTOLOAD+=$(call AutoLoad,09,octeon-sha256)
+endef
+
+define KernelPackage/crypto-sha256/x86/64
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha256-ssse3.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha256-ssse3)
+endef
+
+$(eval $(call KernelPackage,crypto-sha256))
+
+
+define KernelPackage/crypto-sha512
+  TITLE:=SHA512 digest CryptoAPI module
+  DEPENDS:=+kmod-crypto-hash
+  KCONFIG:= \
+	CONFIG_CRYPTO_SHA512 \
+	CONFIG_CRYPTO_SHA512_ARM \
+	CONFIG_CRYPTO_SHA512_OCTEON \
+	CONFIG_CRYPTO_SHA512_SSSE3
+  FILES:=$(LINUX_DIR)/crypto/sha512_generic.ko
+  AUTOLOAD:=$(call AutoLoad,09,sha512_generic)
+  $(call AddDepends/crypto)
+endef
+
+define KernelPackage/crypto-sha512/arm
+  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha512-arm.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha512-arm)
+endef
+
+KernelPackage/crypto-sha512/imx6=$(KernelPackage/crypto-sha512/arm)
+KernelPackage/crypto-sha512/ipq40xx=$(KernelPackage/crypto-sha512/arm)
+KernelPackage/crypto-sha512/mvebu/cortexa9=$(KernelPackage/crypto-sha512/arm)
+
+define KernelPackage/crypto-sha512/octeon
+  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha512.ko
+  AUTOLOAD+=$(call AutoLoad,09,octeon-sha512)
+endef
+
+KernelPackage/crypto-sha512/tegra=$(KernelPackage/crypto-sha512/arm)
+
+define KernelPackage/crypto-sha512/x86/64
+  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha512-ssse3.ko
+  AUTOLOAD+=$(call AutoLoad,09,sha512-ssse3)
+endef
+
+$(eval $(call KernelPackage,crypto-sha512))
+
+
+define KernelPackage/crypto-test
+  TITLE:=Test CryptoAPI module
+  KCONFIG:=CONFIG_CRYPTO_TEST
+  FILES:=$(LINUX_DIR)/crypto/tcrypt.ko
+  $(call AddDepends/crypto,+kmod-crypto-manager)
+endef
+
+$(eval $(call KernelPackage,crypto-test))
+
+
+define KernelPackage/crypto-user
+  TITLE:=CryptoAPI userspace interface
+  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager
+  KCONFIG:= \
+	CONFIG_CRYPTO_USER \
+	CONFIG_CRYPTO_USER_API \
+	CONFIG_CRYPTO_USER_API_AEAD \
+	CONFIG_CRYPTO_USER_API_HASH \
+	CONFIG_CRYPTO_USER_API_RNG \
+	CONFIG_CRYPTO_USER_API_SKCIPHER
+  FILES:= \
+	$(LINUX_DIR)/crypto/af_alg.ko \
+	$(LINUX_DIR)/crypto/algif_aead.ko \
+	$(LINUX_DIR)/crypto/algif_hash.ko \
+	$(LINUX_DIR)/crypto/algif_rng.ko \
+	$(LINUX_DIR)/crypto/algif_skcipher.ko \
+	$(LINUX_DIR)/crypto/crypto_user.ko
+  AUTOLOAD:=$(call AutoLoad,09,af_alg algif_aead algif_hash algif_rng algif_skcipher crypto_user)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-user))
+
+
+define KernelPackage/crypto-xts
+  TITLE:=XTS cipher CryptoAPI module
+  DEPENDS:=+kmod-crypto-gf128 +kmod-crypto-manager
+  KCONFIG:=CONFIG_CRYPTO_XTS
+  FILES:=$(LINUX_DIR)/crypto/xts.ko
+  AUTOLOAD:=$(call AutoLoad,09,xts)
+  $(call AddDepends/crypto)
+endef
+
+$(eval $(call KernelPackage,crypto-xts))
+
--- a/5.4/package/kernel/linux/modules/fs.mk
+++ b/5.4/package/kernel/linux/modules/fs.mk
@ -0,0 +1,598 @@
+#
+# Copyright (C) 2006-2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+FS_MENU:=Filesystems
+
+define KernelPackage/fs-9p
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Plan 9 Resource Sharing Support
+  DEPENDS:=+kmod-9pnet
+  KCONFIG:=\
+	CONFIG_9P_FS \
+	CONFIG_9P_FS_POSIX_ACL=n \
+	CONFIG_9P_FS_SECURITY=n \
+	CONFIG_9P_FSCACHE=n
+  FILES:=$(LINUX_DIR)/fs/9p/9p.ko
+  AUTOLOAD:=$(call AutoLoad,30,9p)
+endef
+
+define KernelPackage/fs-9p/description
+  Kernel module for Plan 9 Resource Sharing Support support
+endef
+
+$(eval $(call KernelPackage,fs-9p))
+
+
+define KernelPackage/fs-afs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Andrew FileSystem client
+  DEFAULT:=n
+  DEPENDS:=+kmod-rxrpc +kmod-dnsresolver +kmod-fs-fscache
+  KCONFIG:=\
+	CONFIG_AFS_FS=m \
+	CONFIG_AFS_DEBUG=n \
+	CONFIG_AFS_FSCACHE=y
+  FILES:=$(LINUX_DIR)/fs/afs/kafs.ko
+  AUTOLOAD:=$(call AutoLoad,30,kafs)
+endef
+
+define KernelPackage/fs-afs/description
+  Kernel module for Andrew FileSystem client support
+endef
+
+$(eval $(call KernelPackage,fs-afs))
+
+define KernelPackage/fs-autofs4
+  SUBMENU:=$(FS_MENU)
+  TITLE:=AUTOFS4 filesystem support
+  KCONFIG:= \
+	CONFIG_AUTOFS4_FS \
+	CONFIG_AUTOFS_FS
+  FILES:= \
+	$(LINUX_DIR)/fs/autofs/autofs4.ko
+  AUTOLOAD:=$(call AutoLoad,30,autofs4)
+endef
+
+define KernelPackage/fs-autofs4/description
+ Kernel module for AutoFS4 support
+endef
+
+$(eval $(call KernelPackage,fs-autofs4))
+
+
+define KernelPackage/fs-btrfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=BTRFS filesystem support
+  DEPENDS:=+kmod-lib-crc32c +kmod-lib-lzo +kmod-lib-zlib-inflate +kmod-lib-zlib-deflate +kmod-lib-raid6 +kmod-lib-xor +kmod-lib-zstd
+  KCONFIG:=\
+	CONFIG_BTRFS_FS \
+	CONFIG_BTRFS_FS_POSIX_ACL=n \
+	CONFIG_BTRFS_FS_CHECK_INTEGRITY=n
+  FILES:=\
+	$(LINUX_DIR)/fs/btrfs/btrfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,btrfs,1)
+endef
+
+define KernelPackage/fs-btrfs/description
+ Kernel module for BTRFS support
+endef
+
+$(eval $(call KernelPackage,fs-btrfs))
+
+
+define KernelPackage/fs-cifs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=CIFS support
+  KCONFIG:= \
+	CONFIG_CIFS \
+	CONFIG_CIFS_DFS_UPCALL=n \
+	CONFIG_CIFS_UPCALL=n
+  FILES:=$(LINUX_DIR)/fs/cifs/cifs.ko
+  AUTOLOAD:=$(call AutoLoad,30,cifs)
+  $(call AddDepends/nls)
+  DEPENDS+= \
+    +kmod-crypto-md4 \
+    +kmod-crypto-md5 \
+    +kmod-crypto-sha256 \
+    +kmod-crypto-sha512 \
+    +kmod-crypto-cmac \
+    +kmod-crypto-hmac \
+    +kmod-crypto-arc4 \
+    +kmod-crypto-aead \
+    +kmod-crypto-ccm \
+    +kmod-crypto-ecb \
+    +kmod-crypto-des
+endef
+
+define KernelPackage/fs-cifs/description
+ Kernel module for CIFS support
+endef
+
+$(eval $(call KernelPackage,fs-cifs))
+
+
+define KernelPackage/fs-configfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Configuration filesystem support
+  KCONFIG:= \
+	CONFIG_CONFIGFS_FS
+  FILES:=$(LINUX_DIR)/fs/configfs/configfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,configfs)
+endef
+
+define KernelPackage/fs-configfs/description
+ Kernel module for configfs support
+endef
+
+$(eval $(call KernelPackage,fs-configfs))
+
+
+define KernelPackage/fs-cramfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Compressed RAM/ROM filesystem support
+  DEPENDS:=+kmod-lib-zlib-inflate
+  KCONFIG:= \
+	CONFIG_CRAMFS
+  FILES:=$(LINUX_DIR)/fs/cramfs/cramfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,cramfs)
+endef
+
+define KernelPackage/fs-cramfs/description
+ Kernel module for cramfs support
+endef
+
+$(eval $(call KernelPackage,fs-cramfs))
+
+
+define KernelPackage/fs-efivarfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=efivar filesystem support
+  KCONFIG:=CONFIG_EFIVAR_FS
+  FILES:=$(LINUX_DIR)/fs/efivarfs/efivarfs.ko
+  DEPENDS:=@(x86_64||x86)
+  AUTOLOAD:=$(call Autoload,90,efivarfs)
+endef
+
+define KernelPackage/fs-efivarfs/description
+  Kernel module to support efivarfs file system mountpoint.
+endef
+
+$(eval $(call KernelPackage,fs-efivarfs))
+
+
+define KernelPackage/fs-exfat
+  SUBMENU:=$(FS_MENU)
+  TITLE:=exFAT filesystem support
+  KCONFIG:= \
+	CONFIG_EXFAT_FS \
+	CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+  FILES:= \
+	$(LINUX_DIR)/drivers/staging/exfat/exfat.ko@lt5.7 \
+	$(LINUX_DIR)/fs/exfat/exfat.ko@ge5.7
+  AUTOLOAD:=$(call AutoLoad,30,exfat,1)
+  DEPENDS:=+kmod-nls-base
+endef
+
+define KernelPackage/fs-exfat/description
+ Kernel module for exFAT filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-exfat))
+
+
+define KernelPackage/fs-exportfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=exportfs kernel server support
+  KCONFIG:=CONFIG_EXPORTFS
+  FILES=$(LINUX_DIR)/fs/exportfs/exportfs.ko
+  AUTOLOAD:=$(call AutoLoad,20,exportfs,1)
+endef
+
+define KernelPackage/fs-exportfs/description
+ Kernel module for exportfs. Needed for some other modules.
+endef
+
+$(eval $(call KernelPackage,fs-exportfs))
+
+
+define KernelPackage/fs-ext4
+  SUBMENU:=$(FS_MENU)
+  TITLE:=EXT4 filesystem support
+  DEPENDS := \
+    +kmod-lib-crc16 \
+    +kmod-crypto-hash \
+    +kmod-crypto-crc32c
+  KCONFIG:= \
+	CONFIG_EXT4_FS \
+	CONFIG_EXT4_ENCRYPTION=n \
+	CONFIG_JBD2
+  FILES:= \
+	$(LINUX_DIR)/fs/ext4/ext4.ko \
+	$(LINUX_DIR)/fs/jbd2/jbd2.ko \
+	$(LINUX_DIR)/fs/mbcache.ko
+  AUTOLOAD:=$(call AutoLoad,30,mbcache jbd2 ext4,1)
+endef
+
+define KernelPackage/fs-ext4/description
+ Kernel module for EXT4 filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-ext4))
+
+
+define KernelPackage/fs-f2fs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=F2FS filesystem support
+  DEPENDS:= +kmod-crypto-hash +kmod-crypto-crc32 +kmod-nls-base
+  KCONFIG:=CONFIG_F2FS_FS
+  FILES:=$(LINUX_DIR)/fs/f2fs/f2fs.ko
+  AUTOLOAD:=$(call AutoLoad,30,f2fs,1)
+endef
+
+define KernelPackage/fs-f2fs/description
+ Kernel module for F2FS filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-f2fs))
+
+
+define KernelPackage/fs-fscache
+  SUBMENU:=$(FS_MENU)
+  TITLE:=General filesystem local cache manager
+  DEPENDS:=
+  KCONFIG:=\
+	CONFIG_FSCACHE=m \
+	CONFIG_FSCACHE_STATS=y \
+	CONFIG_FSCACHE_HISTOGRAM=n \
+	CONFIG_FSCACHE_DEBUG=n \
+	CONFIG_FSCACHE_OBJECT_LIST=n \
+	CONFIG_CACHEFILES=y \
+	CONFIG_CACHEFILES_DEBUG=n \
+	CONFIG_CACHEFILES_HISTOGRAM=n
+  FILES:=$(LINUX_DIR)/fs/fscache/fscache.ko
+  AUTOLOAD:=$(call AutoLoad,29,fscache)
+endef
+
+$(eval $(call KernelPackage,fs-fscache))
+
+
+define KernelPackage/fs-hfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=HFS filesystem support
+  DEPENDS:=+kmod-cdrom
+  KCONFIG:=CONFIG_HFS_FS
+  FILES:=$(LINUX_DIR)/fs/hfs/hfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,hfs)
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-hfs/description
+ Kernel module for HFS filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-hfs))
+
+
+define KernelPackage/fs-hfsplus
+  SUBMENU:=$(FS_MENU)
+  TITLE:=HFS+ filesystem support
+  DEPENDS:=+kmod-cdrom
+  KCONFIG:=CONFIG_HFSPLUS_FS
+  FILES:=$(LINUX_DIR)/fs/hfsplus/hfsplus.ko
+  AUTOLOAD:=$(call AutoLoad,30,hfsplus)
+  $(call AddDepends/nls,utf8)
+endef
+
+define KernelPackage/fs-hfsplus/description
+ Kernel module for HFS+ filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-hfsplus))
+
+
+define KernelPackage/fs-isofs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=ISO9660 filesystem support
+  DEPENDS:=+kmod-lib-zlib-inflate +kmod-cdrom
+  KCONFIG:=CONFIG_ISO9660_FS CONFIG_JOLIET=y CONFIG_ZISOFS=n
+  FILES:=$(LINUX_DIR)/fs/isofs/isofs.ko
+  AUTOLOAD:=$(call AutoLoad,30,isofs)
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-isofs/description
+ Kernel module for ISO9660 filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-isofs))
+
+
+define KernelPackage/fs-jfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=JFS filesystem support
+  KCONFIG:=CONFIG_JFS_FS
+  FILES:=$(LINUX_DIR)/fs/jfs/jfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,jfs,1)
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-jfs/description
+ Kernel module for JFS support
+endef
+
+$(eval $(call KernelPackage,fs-jfs))
+
+define KernelPackage/fs-minix
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Minix filesystem support
+  KCONFIG:=CONFIG_MINIX_FS
+  FILES:=$(LINUX_DIR)/fs/minix/minix.ko
+  AUTOLOAD:=$(call AutoLoad,30,minix)
+endef
+
+define KernelPackage/fs-minix/description
+ Kernel module for Minix filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-minix))
+
+
+define KernelPackage/fs-msdos
+  SUBMENU:=$(FS_MENU)
+  TITLE:=MSDOS filesystem support
+  DEPENDS:=+kmod-fs-vfat
+  KCONFIG:=CONFIG_MSDOS_FS
+  FILES:=$(LINUX_DIR)/fs/fat/msdos.ko
+  AUTOLOAD:=$(call AutoLoad,40,msdos)
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-msdos/description
+ Kernel module for MSDOS filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-msdos))
+
+
+define KernelPackage/fs-nfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NFS filesystem client support
+  DEPENDS:=+kmod-fs-nfs-common +kmod-dnsresolver
+  KCONFIG:= \
+	CONFIG_NFS_FS \
+	CONFIG_NFS_USE_LEGACY_DNS=n \
+	CONFIG_NFS_USE_NEW_IDMAPPER=n
+  FILES:= \
+	$(LINUX_DIR)/fs/nfs/nfs.ko
+  AUTOLOAD:=$(call AutoLoad,40,nfs)
+endef
+
+define KernelPackage/fs-nfs/description
+ Kernel module for NFS client support
+endef
+
+$(eval $(call KernelPackage,fs-nfs))
+
+
+define KernelPackage/fs-nfs-common
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Common NFS filesystem modules
+  KCONFIG:= \
+	CONFIG_LOCKD \
+	CONFIG_SUNRPC \
+	CONFIG_GRACE_PERIOD
+  FILES:= \
+	$(LINUX_DIR)/fs/lockd/lockd.ko \
+	$(LINUX_DIR)/net/sunrpc/sunrpc.ko \
+	$(LINUX_DIR)/fs/nfs_common/grace.ko \
+	$(LINUX_DIR)/fs/nfs_common/nfs_ssc.ko@eq5.10
+  AUTOLOAD:=$(call AutoLoad,30,grace sunrpc lockd)
+endef
+
+$(eval $(call KernelPackage,fs-nfs-common))
+
+
+define KernelPackage/fs-nfs-common-rpcsec
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NFS Secure RPC
+  DEPENDS:= \
+	+kmod-fs-nfs-common \
+	+kmod-crypto-des \
+	+kmod-crypto-cbc \
+	+kmod-crypto-cts \
+	+kmod-crypto-md5 \
+	+kmod-crypto-sha1 \
+	+kmod-crypto-hmac \
+	+kmod-crypto-ecb \
+	+kmod-crypto-arc4
+  KCONFIG:= \
+	CONFIG_SUNRPC_GSS \
+	CONFIG_RPCSEC_GSS_KRB5
+  FILES:= \
+	$(LINUX_DIR)/lib/oid_registry.ko \
+	$(LINUX_DIR)/net/sunrpc/auth_gss/auth_rpcgss.ko \
+	$(LINUX_DIR)/net/sunrpc/auth_gss/rpcsec_gss_krb5.ko
+  AUTOLOAD:=$(call AutoLoad,31,oid_registry auth_rpcgss rpcsec_gss_krb5)
+endef
+
+define KernelPackage/fs-nfs-common-rpcsec/description
+ Kernel modules for NFS Secure RPC
+endef
+
+$(eval $(call KernelPackage,fs-nfs-common-rpcsec))
+
+
+define KernelPackage/fs-nfs-v3
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NFS3 filesystem client support
+  DEPENDS:=+kmod-fs-nfs
+  FILES:= \
+	$(LINUX_DIR)/fs/nfs/nfsv3.ko
+  AUTOLOAD:=$(call AutoLoad,41,nfsv3)
+endef
+
+define KernelPackage/fs-nfs-v3/description
+ Kernel module for NFS v3 client support
+endef
+
+$(eval $(call KernelPackage,fs-nfs-v3))
+
+
+define KernelPackage/fs-nfs-v4
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NFS4 filesystem client support
+  DEPENDS:=+kmod-fs-nfs
+  KCONFIG:= \
+	CONFIG_NFS_V4=y
+  FILES:= \
+	$(LINUX_DIR)/fs/nfs/nfsv4.ko
+  AUTOLOAD:=$(call AutoLoad,41,nfsv4)
+endef
+
+define KernelPackage/fs-nfs-v4/description
+ Kernel module for NFS v4 client support
+endef
+
+$(eval $(call KernelPackage,fs-nfs-v4))
+
+
+define KernelPackage/fs-nfsd
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NFS kernel server support
+  DEPENDS:=+kmod-fs-nfs-common +kmod-fs-exportfs +kmod-fs-nfs-common-rpcsec
+  KCONFIG:= \
+	CONFIG_NFSD \
+	CONFIG_NFSD_V4=y \
+	CONFIG_NFSD_V4_SECURITY_LABEL=n \
+	CONFIG_NFSD_BLOCKLAYOUT=n \
+	CONFIG_NFSD_SCSILAYOUT=n \
+	CONFIG_NFSD_FLEXFILELAYOUT=n \
+	CONFIG_NFSD_FAULT_INJECTION=n
+  FILES:=$(LINUX_DIR)/fs/nfsd/nfsd.ko
+  AUTOLOAD:=$(call AutoLoad,40,nfsd)
+endef
+
+define KernelPackage/fs-nfsd/description
+ Kernel module for NFS kernel server support
+endef
+
+$(eval $(call KernelPackage,fs-nfsd))
+
+
+define KernelPackage/fs-ntfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=NTFS filesystem support
+  KCONFIG:=CONFIG_NTFS_FS
+  FILES:=$(LINUX_DIR)/fs/ntfs/ntfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,ntfs)
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-ntfs/description
+ Kernel module for NTFS filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-ntfs))
+
+
+define KernelPackage/fs-reiserfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=ReiserFS filesystem support
+  KCONFIG:=CONFIG_REISERFS_FS
+  FILES:=$(LINUX_DIR)/fs/reiserfs/reiserfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,reiserfs,1)
+endef
+
+define KernelPackage/fs-reiserfs/description
+ Kernel module for ReiserFS support
+endef
+
+$(eval $(call KernelPackage,fs-reiserfs))
+
+
+define KernelPackage/fs-squashfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=SquashFS 4.0 filesystem support
+  KCONFIG:=CONFIG_SQUASHFS \
+	CONFIG_SQUASHFS_XZ=y
+  FILES:=$(LINUX_DIR)/fs/squashfs/squashfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,squashfs,1)
+endef
+
+define KernelPackage/fs-squashfs/description
+ Kernel module for SquashFS 4.0 support
+endef
+
+$(eval $(call KernelPackage,fs-squashfs))
+
+
+define KernelPackage/fs-udf
+  SUBMENU:=$(FS_MENU)
+  TITLE:=UDF filesystem support
+  KCONFIG:=CONFIG_UDF_FS
+  FILES:=$(LINUX_DIR)/fs/udf/udf.ko
+  AUTOLOAD:=$(call AutoLoad,30,udf)
+  DEPENDS:=+kmod-lib-crc-itu-t +kmod-cdrom
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/fs-udf/description
+ Kernel module for UDF filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-udf))
+
+
+define KernelPackage/fs-vfat
+  SUBMENU:=$(FS_MENU)
+  TITLE:=VFAT filesystem support
+  KCONFIG:= \
+	CONFIG_FAT_FS \
+	CONFIG_VFAT_FS
+  FILES:= \
+	$(LINUX_DIR)/fs/fat/fat.ko \
+	$(LINUX_DIR)/fs/fat/vfat.ko
+  AUTOLOAD:=$(call AutoLoad,30,fat vfat)
+  $(call AddDepends/nls,cp437 iso8859-1 utf8)
+endef
+
+define KernelPackage/fs-vfat/description
+ Kernel module for VFAT filesystem support
+endef
+
+$(eval $(call KernelPackage,fs-vfat))
+
+
+define KernelPackage/fs-xfs
+  SUBMENU:=$(FS_MENU)
+  TITLE:=XFS filesystem support
+  KCONFIG:=CONFIG_XFS_FS
+  DEPENDS:= +kmod-fs-exportfs +kmod-lib-crc32c
+  FILES:=$(LINUX_DIR)/fs/xfs/xfs.ko
+  AUTOLOAD:=$(call AutoLoad,30,xfs,1)
+endef
+
+define KernelPackage/fs-xfs/description
+ Kernel module for XFS support
+endef
+
+$(eval $(call KernelPackage,fs-xfs))
+
+
+define KernelPackage/fuse
+  SUBMENU:=$(FS_MENU)
+  TITLE:=FUSE (Filesystem in Userspace) support
+  KCONFIG:= CONFIG_FUSE_FS
+  FILES:=$(LINUX_DIR)/fs/fuse/fuse.ko
+  AUTOLOAD:=$(call AutoLoad,80,fuse)
+endef
+
+define KernelPackage/fuse/description
+ Kernel module for userspace filesystem support
+endef
+
+$(eval $(call KernelPackage,fuse))
--- a/5.4/package/kernel/linux/modules/input.mk
+++ b/5.4/package/kernel/linux/modules/input.mk
@ -0,0 +1,229 @@
+#
+# Copyright (C) 2006-2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+INPUT_MODULES_MENU:=Input modules
+
+define KernelPackage/hid
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=HID Devices
+  DEPENDS:=+kmod-input-core +kmod-input-evdev
+  KCONFIG:=CONFIG_HID CONFIG_HIDRAW=y CONFIG_HID_BATTERY_STRENGTH=y
+  FILES:=$(LINUX_DIR)/drivers/hid/hid.ko
+  AUTOLOAD:=$(call AutoLoad,61,hid)
+endef
+
+define KernelPackage/hid/description
+ Kernel modules for HID devices
+endef
+
+$(eval $(call KernelPackage,hid))
+
+define KernelPackage/hid-generic
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Generic HID device support
+  DEPENDS:=+kmod-hid
+  KCONFIG:=CONFIG_HID_GENERIC
+  FILES:=$(LINUX_DIR)/drivers/hid/hid-generic.ko
+  AUTOLOAD:=$(call AutoProbe,hid-generic)
+endef
+
+define KernelPackage/hid/description
+ Kernel modules for generic HID device (e.g. keyboards and mice) support
+endef
+
+$(eval $(call KernelPackage,hid-generic))
+
+define KernelPackage/input-core
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Input device core
+  KCONFIG:=CONFIG_INPUT
+  FILES:=$(LINUX_DIR)/drivers/input/input-core.ko
+endef
+
+define KernelPackage/input-core/description
+ Kernel modules for support of input device
+endef
+
+$(eval $(call KernelPackage,input-core))
+
+
+define KernelPackage/input-evdev
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Input event device
+  DEPENDS:=+kmod-input-core
+  KCONFIG:=CONFIG_INPUT_EVDEV
+  FILES:=$(LINUX_DIR)/drivers/input/evdev.ko
+  AUTOLOAD:=$(call AutoLoad,60,evdev)
+endef
+
+define KernelPackage/input-evdev/description
+ Kernel modules for support of input device events
+endef
+
+$(eval $(call KernelPackage,input-evdev))
+
+
+define KernelPackage/input-gpio-keys
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=GPIO key support
+  DEPENDS:= @GPIO_SUPPORT +kmod-input-core
+  KCONFIG:= \
+	CONFIG_KEYBOARD_GPIO \
+	CONFIG_INPUT_KEYBOARD=y
+  FILES:=$(LINUX_DIR)/drivers/input/keyboard/gpio_keys.ko
+  AUTOLOAD:=$(call AutoProbe,gpio_keys,1)
+endef
+
+define KernelPackage/input-gpio-keys/description
+ This driver implements support for buttons connected
+ to GPIO pins of various CPUs (and some other chips).
+
+ See also gpio-button-hotplug which is an alternative, lower overhead
+ implementation that generates uevents instead of kernel input events.
+endef
+
+$(eval $(call KernelPackage,input-gpio-keys))
+
+
+define KernelPackage/input-gpio-keys-polled
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Polled GPIO key support
+  DEPENDS:=@GPIO_SUPPORT +kmod-input-polldev
+  KCONFIG:= \
+	CONFIG_KEYBOARD_GPIO_POLLED \
+	CONFIG_INPUT_KEYBOARD=y
+  FILES:=$(LINUX_DIR)/drivers/input/keyboard/gpio_keys_polled.ko
+  AUTOLOAD:=$(call AutoProbe,gpio_keys_polled,1)
+endef
+
+define KernelPackage/input-gpio-keys-polled/description
+ Kernel module for support polled GPIO keys input device
+
+ See also gpio-button-hotplug which is an alternative, lower overhead
+ implementation that generates uevents instead of kernel input events.
+endef
+
+$(eval $(call KernelPackage,input-gpio-keys-polled))
+
+
+define KernelPackage/input-gpio-encoder
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=GPIO rotary encoder
+  DEPENDS:=@GPIO_SUPPORT +kmod-input-core
+  KCONFIG:=CONFIG_INPUT_GPIO_ROTARY_ENCODER
+  FILES:=$(LINUX_DIR)/drivers/input/misc/rotary_encoder.ko
+  AUTOLOAD:=$(call AutoProbe,rotary_encoder)
+endef
+
+define KernelPackage/input-gpio-encoder/description
+ Kernel module to use rotary encoders connected to GPIO pins
+endef
+
+$(eval $(call KernelPackage,input-gpio-encoder))
+
+
+define KernelPackage/input-joydev
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Joystick device support
+  DEPENDS:=+kmod-input-core
+  KCONFIG:=CONFIG_INPUT_JOYDEV
+  FILES:=$(LINUX_DIR)/drivers/input/joydev.ko
+  AUTOLOAD:=$(call AutoProbe,joydev)
+endef
+
+define KernelPackage/input-joydev/description
+ Kernel module for joystick support
+endef
+
+$(eval $(call KernelPackage,input-joydev))
+
+
+define KernelPackage/input-polldev
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Polled Input device support
+  DEPENDS:=+kmod-input-core
+  KCONFIG:=CONFIG_INPUT_POLLDEV
+  FILES:=$(LINUX_DIR)/drivers/input/input-polldev.ko
+endef
+
+define KernelPackage/input-polldev/description
+ Kernel module for support of polled input devices
+endef
+
+$(eval $(call KernelPackage,input-polldev))
+
+
+define KernelPackage/input-matrixkmap
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Input matrix devices support
+  DEPENDS:=+kmod-input-core
+  KCONFIG:=CONFIG_INPUT_MATRIXKMAP
+  FILES:=$(LINUX_DIR)/drivers/input/matrix-keymap.ko
+  AUTOLOAD:=$(call AutoProbe,matrix-keymap)
+endef
+
+define KernelPackage/input-matrixkmap/description
+ Kernel module support for input matrix devices
+endef
+
+$(eval $(call KernelPackage,input-matrixkmap))
+
+
+define KernelPackage/input-touchscreen-ads7846
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=ADS7846/TSC2046/AD7873 and AD(S)7843 based touchscreens
+  DEPENDS:=+kmod-hwmon-core +kmod-input-core +kmod-spi-bitbang
+  KCONFIG:= \
+	CONFIG_INPUT_TOUCHSCREEN=y \
+	CONFIG_TOUCHSCREEN_PROPERTIES=y \
+	CONFIG_TOUCHSCREEN_ADS7846
+  FILES:=$(LINUX_DIR)/drivers/input/touchscreen/ads7846.ko \
+	$(LINUX_DIR)/drivers/input/touchscreen/of_touchscreen.ko@lt5.14
+  AUTOLOAD:=$(call AutoProbe,ads7846)
+endef
+
+define KernelPackage/input-touchscreen-ads7846/description
+  Kernel module for ADS7846/TSC2046/AD7873 and AD(S)7843 based touchscreens
+endef
+
+$(eval $(call KernelPackage,input-touchscreen-ads7846))
+
+
+define KernelPackage/keyboard-imx
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=IMX keypad support
+  DEPENDS:=@(TARGET_mxs||TARGET_imx6) +kmod-input-matrixkmap
+  KCONFIG:= \
+	CONFIG_KEYBOARD_IMX \
+	CONFIG_INPUT_KEYBOARD=y
+  FILES:=$(LINUX_DIR)/drivers/input/keyboard/imx_keypad.ko
+  AUTOLOAD:=$(call AutoProbe,imx_keypad)
+endef
+
+define KernelPackage/keyboard-imx/description
+ Enable support for IMX keypad port.
+endef
+
+$(eval $(call KernelPackage,keyboard-imx))
+
+
+define KernelPackage/input-uinput
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=user input module
+  DEPENDS:=+kmod-input-core
+  KCONFIG:= \
+	CONFIG_INPUT_MISC=y \
+	CONFIG_INPUT_UINPUT
+  FILES:=$(LINUX_DIR)/drivers/input/misc/uinput.ko
+  AUTOLOAD:=$(call AutoProbe,uinput)
+endef
+
+define KernelPackage/input-uinput/description
+  user input modules needed for bluez
+endef
+
+$(eval $(call KernelPackage,input-uinput))
--- a/5.4/package/kernel/linux/modules/netfilter.mk
+++ b/5.4/package/kernel/linux/modules/netfilter.mk
--- a/5.4/package/kernel/linux/modules/netsupport.mk
+++ b/5.4/package/kernel/linux/modules/netsupport.mk
--- a/5.4/package/kernel/linux/modules/other.mk
+++ b/5.4/package/kernel/linux/modules/other.mk
--- a/5.4/package/kernel/linux/modules/sound.mk
+++ b/5.4/package/kernel/linux/modules/sound.mk
@ -0,0 +1,536 @@
+#
+# Copyright (C) 2006-2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+SOUND_MENU:=Sound Support
+
+# allow targets to override the soundcore stuff
+SOUNDCORE_LOAD ?= \
+	soundcore \
+	snd \
+	snd-hwdep \
+	snd-seq-device \
+	snd-rawmidi \
+	snd-timer \
+	snd-pcm \
+	snd-mixer-oss \
+	snd-pcm-oss \
+	snd-compress
+
+SOUNDCORE_FILES ?= \
+	$(LINUX_DIR)/sound/soundcore.ko \
+	$(LINUX_DIR)/sound/core/snd.ko \
+	$(LINUX_DIR)/sound/core/snd-hwdep.ko \
+	$(LINUX_DIR)/sound/core/snd-seq-device.ko \
+	$(LINUX_DIR)/sound/core/snd-rawmidi.ko \
+	$(LINUX_DIR)/sound/core/snd-timer.ko \
+	$(LINUX_DIR)/sound/core/snd-pcm.ko \
+	$(LINUX_DIR)/sound/core/oss/snd-mixer-oss.ko \
+	$(LINUX_DIR)/sound/core/oss/snd-pcm-oss.ko \
+	$(LINUX_DIR)/sound/core/snd-compress.ko@lt5.14
+
+SOUNDCORE_LOAD += \
+	$(if $(CONFIG_SND_DMAENGINE_PCM),snd-pcm-dmaengine)
+
+SOUNDCORE_FILES += \
+	$(if $(CONFIG_SND_DMAENGINE_PCM),$(LINUX_DIR)/sound/core/snd-pcm-dmaengine.ko)
+
+define KernelPackage/sound-core
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=Sound support
+  DEPENDS:=@AUDIO_SUPPORT +kmod-input-core
+  KCONFIG:= \
+	CONFIG_SOUND \
+	CONFIG_SND \
+	CONFIG_SND_HWDEP \
+	CONFIG_SND_RAWMIDI \
+	CONFIG_SND_TIMER \
+	CONFIG_SND_PCM \
+	CONFIG_SND_PCM_TIMER=y \
+	CONFIG_SND_SEQUENCER \
+	CONFIG_SND_VIRMIDI \
+	CONFIG_SND_SEQ_DUMMY \
+	CONFIG_SND_SEQUENCER_OSS=y \
+	CONFIG_HOSTAUDIO \
+	CONFIG_SND_PCM_OSS \
+	CONFIG_SND_MIXER_OSS \
+	CONFIG_SOUND_OSS_CORE_PRECLAIM=y \
+	CONFIG_SND_COMPRESS_OFFLOAD
+  FILES:=$(SOUNDCORE_FILES)
+  AUTOLOAD:=$(call AutoLoad,30,$(SOUNDCORE_LOAD))
+endef
+
+define KernelPackage/sound-core/uml
+  FILES:= \
+	$(LINUX_DIR)/sound/soundcore.ko \
+	$(LINUX_DIR)/arch/um/drivers/hostaudio.ko
+  AUTOLOAD+=$(call AutoLoad,30,soundcore hostaudio)
+endef
+
+define KernelPackage/sound-core/description
+ Kernel modules for sound support
+endef
+
+$(eval $(call KernelPackage,sound-core))
+
+
+define AddDepends/sound
+  SUBMENU:=$(SOUND_MENU)
+  DEPENDS+=kmod-sound-core $(1) @!TARGET_uml
+endef
+
+
+define KernelPackage/ac97
+  TITLE:=ac97 controller
+  KCONFIG:=CONFIG_SND_AC97_CODEC
+  FILES:= \
+	$(LINUX_DIR)/sound/ac97_bus.ko \
+	$(LINUX_DIR)/sound/pci/ac97/snd-ac97-codec.ko
+  AUTOLOAD:=$(call AutoLoad,35,ac97_bus snd-ac97-codec)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/ac97/description
+ The ac97 controller
+endef
+
+$(eval $(call KernelPackage,ac97))
+
+
+define KernelPackage/sound-mpu401
+  TITLE:=MPU-401 uart driver
+  KCONFIG:=CONFIG_SND_MPU401_UART
+  FILES:= \
+	$(LINUX_DIR)/sound/drivers/mpu401/snd-mpu401-uart.ko
+  AUTOLOAD:=$(call AutoLoad,35,snd-mpu401-uart)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-mpu401/description
+ support for MIDI ports compatible with the Roland MPU-401
+ interface in UART mode.
+endef
+
+$(eval $(call KernelPackage,sound-mpu401))
+
+
+define KernelPackage/sound-seq
+  TITLE:=Sequencer support
+  FILES:= \
+	$(LINUX_DIR)/sound/core/seq/snd-seq.ko \
+	$(LINUX_DIR)/sound/core/seq/snd-seq-midi-event.ko \
+	$(LINUX_DIR)/sound/core/seq/snd-seq-midi.ko
+  AUTOLOAD:=$(call AutoLoad,35,snd-seq snd-seq-midi-event snd-seq-midi)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-seq/description
+ Kernel modules for sequencer support
+endef
+
+$(eval $(call KernelPackage,sound-seq))
+
+
+define KernelPackage/sound-ens1371
+  TITLE:=(Creative) Ensoniq AudioPCI 1371
+  KCONFIG:=CONFIG_SND_ENS1371
+  DEPENDS:=@PCI_SUPPORT +kmod-ac97
+  FILES:=$(LINUX_DIR)/sound/pci/snd-ens1371.ko
+  AUTOLOAD:=$(call AutoLoad,36,snd-ens1371)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-ens1371/description
+ support for (Creative) Ensoniq AudioPCI 1371 chips
+endef
+
+$(eval $(call KernelPackage,sound-ens1371))
+
+
+define KernelPackage/sound-i8x0
+  TITLE:=Intel/SiS/nVidia/AMD/ALi AC97 Controller
+  DEPENDS:=+kmod-ac97
+  KCONFIG:=CONFIG_SND_INTEL8X0
+  FILES:=$(LINUX_DIR)/sound/pci/snd-intel8x0.ko
+  AUTOLOAD:=$(call AutoLoad,36,snd-intel8x0)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-i8x0/description
+ support for the integrated AC97 sound device on motherboards
+ with Intel/SiS/nVidia/AMD chipsets, or ALi chipsets using
+ the M5455 Audio Controller.
+endef
+
+$(eval $(call KernelPackage,sound-i8x0))
+
+
+define KernelPackage/sound-via82xx
+  TITLE:=VIA 82xx AC97 Controller
+  DEPENDS:=+kmod-ac97 +kmod-sound-mpu401
+  KCONFIG:=CONFIG_SND_VIA82XX
+  FILES:=$(LINUX_DIR)/sound/pci/snd-via82xx.ko
+  AUTOLOAD:=$(call AutoLoad,36,snd-via82xx)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-via82xx/description
+ support for the integrated AC97 sound device on motherboards
+ with VIA chipsets.
+endef
+
+$(eval $(call KernelPackage,sound-via82xx))
+
+
+define KernelPackage/sound-soc-core
+  TITLE:=SoC sound support
+  DEPENDS:=+kmod-regmap-core +kmod-ac97
+  KCONFIG:= \
+	CONFIG_SND_SOC \
+	CONFIG_SND_SOC_ADI=n \
+	CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y \
+	CONFIG_SND_SOC_ALL_CODECS=n
+  FILES:=$(LINUX_DIR)/sound/soc/snd-soc-core.ko
+  AUTOLOAD:=$(call AutoLoad,55,snd-soc-core)
+  $(call AddDepends/sound)
+endef
+
+$(eval $(call KernelPackage,sound-soc-core))
+
+
+define KernelPackage/sound-soc-ac97
+  TITLE:=AC97 Codec support
+  KCONFIG:=CONFIG_SND_SOC_AC97_CODEC
+  FILES:=$(LINUX_DIR)/sound/soc/codecs/snd-soc-ac97.ko
+  AUTOLOAD:=$(call AutoLoad,57,snd-soc-ac97)
+  DEPENDS:=+kmod-ac97 +kmod-sound-soc-core
+  $(call AddDepends/sound)
+endef
+
+$(eval $(call KernelPackage,sound-soc-ac97))
+
+
+define KernelPackage/sound-soc-imx
+  TITLE:=IMX SoC support
+  KCONFIG:=\
+	CONFIG_SND_IMX_SOC \
+	CONFIG_SND_SOC_IMX_AUDMUX \
+	CONFIG_SND_SOC_FSL_SSI \
+	CONFIG_SND_SOC_IMX_PCM_DMA
+  FILES:= \
+	$(LINUX_DIR)/sound/soc/fsl/snd-soc-imx-audmux.ko \
+	$(LINUX_DIR)/sound/soc/fsl/snd-soc-fsl-ssi.ko \
+	$(LINUX_DIR)/sound/soc/fsl/imx-pcm-dma.ko
+  AUTOLOAD:=$(call AutoLoad,56,snd-soc-imx-audmux snd-soc-fsl-ssi snd-soc-imx-pcm)
+  DEPENDS:=@TARGET_imx6 +kmod-sound-soc-core
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-soc-imx/description
+ Support for i.MX6 Platform sound (ssi/audmux/pcm)
+endef
+
+$(eval $(call KernelPackage,sound-soc-imx))
+
+
+define KernelPackage/sound-soc-imx-sgtl5000
+  TITLE:=IMX SoC support for SGTL5000
+  KCONFIG:=CONFIG_SND_SOC_IMX_SGTL5000
+  FILES:=\
+	$(LINUX_DIR)/sound/soc/codecs/snd-soc-sgtl5000.ko \
+	$(LINUX_DIR)/sound/soc/fsl/snd-soc-imx-sgtl5000.ko
+  AUTOLOAD:=$(call AutoLoad,57,snd-soc-sgtl5000 snd-soc-imx-sgtl5000)
+  DEPENDS:=@TARGET_imx6 +kmod-sound-soc-imx
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-soc-imx-sgtl5000/description
+ Support for i.MX6 Platform sound SGTL5000 codec
+endef
+
+$(eval $(call KernelPackage,sound-soc-imx-sgtl5000))
+
+
+define KernelPackage/sound-soc-spdif
+  TITLE:=SoC S/PDIF codec support
+  KCONFIG:=CONFIG_SND_SOC_SPDIF
+  FILES:= \
+	$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-tx.ko \
+	$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-rx.ko
+  DEPENDS:=+kmod-sound-soc-core
+  AUTOLOAD:=$(call AutoProbe,snd-soc-spdif-tx snd-soc-spdif-rx)
+  $(call AddDepends/sound)
+endef
+
+$(eval $(call KernelPackage,sound-soc-spdif))
+
+
+define KernelPackage/pcspkr
+  DEPENDS:=@TARGET_x86 +kmod-input-core
+  TITLE:=PC speaker support
+  KCONFIG:= \
+	CONFIG_SND_PCSP
+  FILES:= \
+	$(LINUX_DIR)/sound/drivers/pcsp/snd-pcsp.ko
+  AUTOLOAD:=$(call AutoLoad,50,snd-pcsp)
+  $(call AddDepends/sound)
+endef
+
+define KernelPackage/pcspkr/description
+ This enables sounds (tones) through the pc speaker
+endef
+
+$(eval $(call KernelPackage,pcspkr))
+
+define KernelPackage/sound-dummy
+  $(call AddDepends/sound)
+  TITLE:=Null sound output driver (sink)
+  KCONFIG:= \
+	CONFIG_SND_DUMMY
+  FILES:= \
+	$(LINUX_DIR)/sound/drivers/snd-dummy.ko
+  AUTOLOAD:=$(call AutoLoad,32,snd-dummy)
+endef
+
+define KernelPackage/sound-dummy/description
+ Dummy sound device for Alsa when no hardware present
+endef
+
+$(eval $(call KernelPackage,sound-dummy))
+
+define KernelPackage/sound-hda-core
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Sound Core Support
+  DEPENDS:=+kmod-ledtrig-audio
+  KCONFIG:= \
+	CONFIG_SND_HDA_CORE \
+	CONFIG_SND_HDA_HWDEP=y \
+	CONFIG_SND_HDA_RECONFIG=n \
+	CONFIG_SND_HDA_INPUT_BEEP=n \
+	CONFIG_SND_HDA_PATCH_LOADER=n \
+	CONFIG_SND_HDA_GENERIC
+  FILES:= \
+	$(LINUX_DIR)/sound/hda/snd-hda-core.ko \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec.ko \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-generic.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-core snd-hda-codec snd-hda-codec-generic)
+  $(call AddDepends/sound,+kmod-regmap-core)
+endef
+
+define KernelPackage/sound-hda-core/description
+ Kernel modules for HD Audio sound support
+endef
+
+$(eval $(call KernelPackage,sound-hda-core))
+
+define KernelPackage/sound-hda-codec-realtek
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:= HD Audio Realtek Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_REALTEK
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-realtek.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-realtek)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-realtek/description
+ Kernel modules for Intel HDA Realtek codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-realtek))
+
+define KernelPackage/sound-hda-codec-cmedia
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio C-Media Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_CMEDIA
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-cmedia.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-cmedia)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-cmedia/description
+ Kernel modules for HD Audio C-Media codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-cmedia))
+
+define KernelPackage/sound-hda-codec-analog
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Analog Devices Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_ANALOG
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-analog.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-analog)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-analog/description
+ Kernel modules for HD Audio Analog Devices codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-analog))
+
+define KernelPackage/sound-hda-codec-idt
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Sigmatel IDT Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_SIGMATEL
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-idt.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-idt)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-idt/description
+ Kernel modules for HD Audio Sigmatel IDT codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-idt))
+
+define KernelPackage/sound-hda-codec-si3054
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Silicon Labs 3054 Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_SI3054
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-si3054.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-si3054)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-si3054/description
+ Kernel modules for HD Audio Silicon Labs 3054 codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-si3054))
+
+define KernelPackage/sound-hda-codec-cirrus
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Cirrus Logic Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_CIRRUS
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-cirrus.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-cirrus)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-cirrus/description
+ Kernel modules for HD Audio Cirrus Logic codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-cirrus))
+
+define KernelPackage/sound-hda-codec-ca0110
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Creative CA0110 Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_CA0110
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-ca0110.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-ca0110)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-ca0110/description
+ Kernel modules for HD Audio Creative CA0110 codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-ca0110))
+
+define KernelPackage/sound-hda-codec-ca0132
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Creative CA0132 Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_CA0132 \
+	CONFIG_SND_HDA_CODEC_CA0132_DSP=n
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-ca0132.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-ca0132)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-ca0132/description
+ Kernel modules for HD Audio Creative CA0132 codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-ca0132))
+
+define KernelPackage/sound-hda-codec-conexant
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Conexant Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_CONEXANT
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-conexant.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-conexant)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-conexant/description
+ Kernel modules for HD Audio Conexant codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-conexant))
+
+define KernelPackage/sound-hda-codec-via
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Via Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_VIA
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-via.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-via)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-via/description
+ Kernel modules for HD Audio VIA codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-via))
+
+define KernelPackage/sound-hda-codec-hdmi
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio HDMI/DisplayPort Codec
+  KCONFIG:= \
+	CONFIG_SND_HDA_CODEC_HDMI
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-hdmi.ko
+  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-hdmi)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-codec-hdmi/description
+ Kernel modules for HD Audio HDMI codec support
+endef
+
+$(eval $(call KernelPackage,sound-hda-codec-hdmi))
+
+define KernelPackage/sound-hda-intel
+  SUBMENU:=$(SOUND_MENU)
+  TITLE:=HD Audio Intel Driver
+  DEPENDS:=@TARGET_x86
+  KCONFIG:= \
+	CONFIG_SOUND_PCI \
+	CONFIG_SND_HDA_INTEL
+  FILES:= \
+	$(LINUX_DIR)/sound/pci/hda/snd-hda-intel.ko \
+	$(LINUX_DIR)/sound/hda/snd-intel-nhlt.ko@lt5.5 \
+	$(LINUX_DIR)/sound/hda/snd-intel-dspcfg.ko@ge5.5
+  AUTOLOAD:=$(call AutoProbe,snd-hda-intel)
+  $(call AddDepends/sound,kmod-sound-hda-core)
+endef
+
+define KernelPackage/sound-hda-intel/description
+ Kernel modules for HD Audio Intel driver support
+endef
+
+$(eval $(call KernelPackage,sound-hda-intel))