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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport

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This commit is contained in:
Ycarus (Yannick Chabanois) 2023-04-22 08:07:24 +02:00
parent e910436a7a
commit 46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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21
5.4/target/linux/ipq807x/Makefile Normal file
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include $(TOPDIR)/rules.mk
ARCH:=aarch64
BOARD:=ipq807x
BOARDNAME:=Qualcomm Atheros IPQ807x
FEATURES:=squashfs ramdisk fpu nand rtc emmc
KERNELNAME:=Image dtbs
CPU_TYPE:=cortex-a53
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
kmod-leds-gpio kmod-gpio-button-hotplug \
kmod-phy-aquantia kmod-qca-nss-dp \
ath11k-firmware-ipq8074 kmod-ath11k-ahb \
wpad-basic-mbedtls uboot-envtools
$(eval $(call BuildTarget))

28
5.4/target/linux/ipq807x/base-files/etc/board.d/01_leds Normal file
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. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
edgecore,eap102)
ucidef_set_led_netdev "wan" "WAN" "green:wanpoe" "wan"
;;
redmi,ax6|\
xiaomi,ax3600)
ucidef_set_led_netdev "wan" "WAN" "blue:network" "wan"
;;
qnap,301w)
ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "lan1"
ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "lan2"
ucidef_set_led_netdev "lan3" "LAN3" "green:lan3" "lan3"
ucidef_set_led_netdev "lan4" "LAN4" "green:lan4" "lan4"
ucidef_set_led_netdev "10G_1" "10G_1" "green:10g_1" "10g-1"
ucidef_set_led_netdev "10G_2" "10G_2" "green:10g_2" "10g-2"
;;
esac
board_config_flush
exit 0

46
5.4/target/linux/ipq807x/base-files/etc/board.d/02_network Normal file
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#
# Copyright (c) 2015 The Linux Foundation. All rights reserved.
# Copyright (c) 2011-2015 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
ipq807x_setup_interfaces()
{
local board="$1"
case "$board" in
buffalo,wxr-5950ax12|\
dynalink,dl-wrx36|\
xiaomi,ax9000)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
edgecore,eap102)
ucidef_set_interfaces_lan_wan "lan" "wan"
;;
edimax,cax1800)
ucidef_set_interfaces_lan_wan "lan"
;;
qnap,301w)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 10g-2" "10g-1"
;;
redmi,ax6|\
xiaomi,ax3600)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
zyxel,nbg7815)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 10g" "wan"
;;
*)
echo "Unsupported hardware. Network interfaces not initialized"
;;
esac
}
board_config_update
board=$(board_name)
ipq807x_setup_interfaces $board
board_config_flush
exit 0

35
5.4/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata Normal file
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#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath11k/IPQ8074/hw2.0/cal-ahb-c000000.wifi.bin")
case "$board" in
buffalo,wxr-5950ax12|\
edgecore,eap102|\
edimax,cax1800|\
dynalink,dl-wrx36|\
qnap,301w|\
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000|\
zyxel,nbg7815)
caldata_extract "0:art" 0x1000 0x20000
;;
esac
;;
"ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin")
case "$board" in
xiaomi,ax9000)
caldata_extract "0:art" 0x26800 0x20000
;;
esac
;;
*)
exit 1
;;
esac

13
5.4/target/linux/ipq807x/base-files/etc/init.d/bootcount Executable file
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#!/bin/sh /etc/rc.common
START=99
boot() {
case $(board_name) in
edgecore,eap102)
fw_setenv upgrade_available 0
# Unset changed flag after sysupgrade complete
fw_setenv changed
;;
esac
}

55
5.4/target/linux/ipq807x/base-files/lib/upgrade/buffalo.sh Normal file
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. /lib/functions.sh
# Prepare UBI devices for OpenWrt installation
# - rootfs (mtd22)
# - remove "ubi_rootfs" volume (rootfs on stock)
# - remove "fw_hash" volume (firmware hash)
# - user_property (mtd24)
# - remove "user_property_ubi" volume (user configuration)
# - remove "extra_property" volume (gzipped syslog)
buffalo_upgrade_prepare() {
local ubi_rootdev ubi_propdev
if ! ubi_rootdev="$(nand_attach_ubi rootfs)" || \
! ubi_propdev="$(nand_attach_ubi user_property)"; then
echo "failed to attach UBI volume \"rootfs\" or \"user_property\", rebooting..."
reboot -f
fi
ubirmvol /dev/$ubi_rootdev -N ubi_rootfs &> /dev/null || true
ubirmvol /dev/$ubi_rootdev -N fw_hash &> /dev/null || true
ubirmvol /dev/$ubi_propdev -N user_property_ubi &> /dev/null || true
ubirmvol /dev/$ubi_propdev -N extra_property &> /dev/null || true
}
# Re-create small dummy ubi_rootfs volume and update
# fw_hash volume to pass the checking by U-Boot
# - rootfs (mtd22)
# - re-create "ubi_rootfs" volume
# - re-create and update "fw_hash" volume
# - rootfs_recover (mtd23)
# - update "fw_hash" volume
buffalo_upgrade_optvol() {
local ubi_rootdev ubi_rcvrdev
local hashvol_root hashvol_rcvr
if ! ubi_rootdev="$(nand_attach_ubi rootfs)" || \
! ubi_rcvrdev="$(nand_attach_ubi rootfs_recover)"; then
echo "failed to attach UBI volume \"rootfs\" or \"rootfs_recover\", rebooting..."
reboot -f
fi
ubimkvol /dev/$ubi_rootdev -N ubi_rootfs -S 1
ubimkvol /dev/$ubi_rootdev -N fw_hash -S 1 -t static
if ! hashvol_root="$(nand_find_volume $ubi_rootdev fw_hash)" || \
! hashvol_rcvr="$(nand_find_volume $ubi_rcvrdev fw_hash)"; then
echo "\"fw_hash\" volume in \"rootfs\" or \"rootfs_recover\" not found, rebooting..."
reboot -f
fi
echo -n "00000000000000000000000000000000" > /tmp/dummyhash.txt
ubiupdatevol /dev/$hashvol_root /tmp/dummyhash.txt
ubiupdatevol /dev/$hashvol_rcvr /tmp/dummyhash.txt
}

83
5.4/target/linux/ipq807x/base-files/lib/upgrade/mmc.sh Normal file
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#
# Copyright (C) 2016 lede-project.org
#
# this can be used as a generic mmc upgrade script
# just add a device entry in platform.sh,
# define "kernelname" and "rootfsname" and call mmc_do_upgrade
# after the kernel and rootfs flash a loopdev (as overlay) is
# setup on top of the rootfs partition
# for the proper function a padded rootfs image is needed, basically
# append "pad-to 64k" to the image definition
# this is based on the ipq806x zyxel.sh mmc upgrade
. /lib/functions.sh
mmc_do_upgrade() {
local tar_file="$1"
local rootfs=
local kernel=
[ -z "$kernel" ] && kernel=$(find_mmc_part ${kernelname})
[ -z "$rootfs" ] && rootfs=$(find_mmc_part ${rootfsname})
[ -z "$kernel" ] && echo "Upgrade failed: kernel partition not found! Rebooting..." && reboot -f
[ -z "$rootfs" ] && echo "Upgrade failed: rootfs partition not found! Rebooting..." && reboot -f
mmc_do_flash $tar_file $kernel $rootfs
return 0
}
mmc_do_flash() {
local tar_file=$1
local kernel=$2
local rootfs=$3
# keep sure its unbound
losetup --detach-all || {
echo Failed to detach all loop devices. Skip this try.
reboot -f
}
# use the first found directory in the tar archive
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
echo "flashing kernel to $kernel"
tar xf $tar_file ${board_dir}/kernel -O >$kernel
echo "flashing rootfs to ${rootfs}"
tar xf $tar_file ${board_dir}/root -O >"${rootfs}"
# a padded rootfs is needed for overlay fs creation
local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
[ $offset -lt 65536 ] && {
echo Wrong size for rootfs: $offset
sleep 10
reboot -f
}
# Mount loop for rootfs_data
local loopdev="$(losetup -f)"
losetup -o $offset $loopdev $rootfs || {
echo "Failed to mount looped rootfs_data."
sleep 10
reboot -f
}
echo "Format new rootfs_data at position ${offset}."
mkfs.ext4 -F -L rootfs_data $loopdev
mkdir /tmp/new_root
mount -t ext4 $loopdev /tmp/new_root && {
echo "Saving config to rootfs_data at position ${offset}."
cp -v "$UPGRADE_BACKUP" "/tmp/new_root/$BACKUP_FILE"
umount /tmp/new_root
}
# Cleanup
losetup -d $loopdev >/dev/null 2>&1
sync
umount -a
reboot -f
}

114
5.4/target/linux/ipq807x/base-files/lib/upgrade/platform.sh Normal file
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PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
RAMFS_COPY_BIN='fw_printenv fw_setenv head'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
xiaomi_initramfs_prepare() {
# Wipe UBI if running initramfs
[ "$(rootfs_type)" = "tmpfs" ] || return 0
local rootfs_mtdnum="$( find_mtd_index rootfs )"
if [ ! "$rootfs_mtdnum" ]; then
echo "unable to find mtd partition rootfs"
return 1
fi
local kern_mtdnum="$( find_mtd_index ubi_kernel )"
if [ ! "$kern_mtdnum" ]; then
echo "unable to find mtd partition ubi_kernel"
return 1
fi
ubidetach -m "$rootfs_mtdnum"
ubiformat /dev/mtd$rootfs_mtdnum -y
ubidetach -m "$kern_mtdnum"
ubiformat /dev/mtd$kern_mtdnum -y
}
platform_check_image() {
return 0;
}
platform_pre_upgrade() {
case "$(board_name)" in
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000)
xiaomi_initramfs_prepare
;;
esac
}
platform_do_upgrade() {
case "$(board_name)" in
buffalo,wxr-5950ax12)
CI_KERN_UBIPART="rootfs"
CI_ROOT_UBIPART="user_property"
buffalo_upgrade_prepare
nand_do_flash_file "$1" || nand_do_upgrade_failed
nand_do_restore_config || nand_do_upgrade_failed
buffalo_upgrade_optvol
;;
dynalink,dl-wrx36)
nand_do_upgrade "$1"
;;
edgecore,eap102)
active="$(fw_printenv -n active)"
if [ "$active" -eq "1" ]; then
CI_UBIPART="rootfs2"
else
CI_UBIPART="rootfs1"
fi
# force altbootcmd which handles partition change in u-boot
fw_setenv bootcount 3
fw_setenv upgrade_available 1
nand_do_upgrade "$1"
;;
edimax,cax1800)
nand_do_upgrade "$1"
;;
qnap,301w)
kernelname="0:HLOS"
rootfsname="rootfs"
mmc_do_upgrade "$1"
;;
zyxel,nbg7815)
local config_mtdnum="$(find_mtd_index 0:bootconfig)"
[ -z "$config_mtdnum" ] && reboot
part_num="$(hexdump -e '1/1 "%01x|"' -n 1 -s 168 -C /dev/mtd$config_mtdnum | cut -f 1 -d "|" | head -n1)"
if [ "$part_num" -eq "0" ]; then
kernelname="0:HLOS"
rootfsname="rootfs"
mmc_do_upgrade "$1"
else
kernelname="0:HLOS_1"
rootfsname="rootfs_1"
mmc_do_upgrade "$1"
fi
;;
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000)
# Make sure that UART is enabled
fw_setenv boot_wait on
fw_setenv uart_en 1
# Enforce single partition.
fw_setenv flag_boot_rootfs 0
fw_setenv flag_last_success 0
fw_setenv flag_boot_success 1
fw_setenv flag_try_sys1_failed 8
fw_setenv flag_try_sys2_failed 8
# Kernel and rootfs are placed in 2 different UBI
CI_KERN_UBIPART="ubi_kernel"
CI_ROOT_UBIPART="rootfs"
nand_do_upgrade "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

509
5.4/target/linux/ipq807x/config-5.4 Normal file
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CONFIG_64BIT=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_COREDUMP=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC8=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCE_AEAD=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
CONFIG_CRYPTO_DEV_QCE_SHA=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEV_COREDUMP=y
CONFIG_DMADEVICES=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC_SUPPORT=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_IIO=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_APSS_PLL=y
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
CONFIG_IPQ_GCC_8074=y
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_RELA=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_NVMEM=y
CONFIG_NVMEM_QCOM_QFPROM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_U_BOOT_ENV=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PADATA=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
CONFIG_PHY_QCOM_QMP=y
CONFIG_PHY_QCOM_QUSB2=y
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
CONFIG_PINCTRL_IPQ8074=y
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM=y
# CONFIG_PM8916_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_MSM is not set
# CONFIG_POWER_RESET_QCOM_PON is not set
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_QCOM_A53PLL is not set
# CONFIG_QCOM_AOSS_QMP is not set
CONFIG_QCOM_APCS_IPC=y
CONFIG_QCOM_APM=y
# CONFIG_QCOM_APR is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
# CONFIG_QCOM_CLK_APCS_SDX55 is not set
# CONFIG_QCOM_COINCELL is not set
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_FASTRPC is not set
CONFIG_QCOM_GDSC=y
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IPCC is not set
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_MDT_LOADER=y
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PIL_INFO=y
# CONFIG_QCOM_Q6V5_ADSP is not set
CONFIG_QCOM_Q6V5_COMMON=y
# CONFIG_QCOM_Q6V5_MSS is not set
# CONFIG_QCOM_Q6V5_PAS is not set
CONFIG_QCOM_Q6V5_WCSS=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_RPROC_COMMON=y
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
# CONFIG_QCOM_SMD_RPM is not set
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMEM_STATE=y
CONFIG_QCOM_SMP2P=y
# CONFIG_QCOM_SMSM is not set
CONFIG_QCOM_SOCINFO=y
CONFIG_QCOM_SPMI_ADC5=y
# CONFIG_QCOM_SYSMON is not set
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_VADC_COMMON=y
# CONFIG_QCOM_WCNSS_CTRL is not set
# CONFIG_QCOM_WCNSS_PIL is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_CPR3=y
# CONFIG_REGULATOR_CPR3_NPU is not set
CONFIG_REGULATOR_CPR4_APSS=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
CONFIG_RELOCATABLE=y
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_NS is not set
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SCHED_CORE is not set
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_VIRTIO=y
# CONFIG_VIRTIO_BLK is not set
# CONFIG_VIRTIO_NET is not set
CONFIG_VMAP_STACK=y
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

322
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Edimax CAX1800";
compatible = "edimax,cax1800", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp5;
label-mac-device = &dp5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_system_red: system-red {
label = "red:system";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
};
led_system_green: system-green {
label = "green:system";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
};
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x0000000 0x3400000>;
};
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
use-default-sizes;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x490000 0xa0000>;
read-only;
};
partition@530000 {
label = "0:appsbl_1";
reg = <0x530000 0xa0000>;
read-only;
};
partition@5d0000 {
label = "0:art";
reg = <0x5d0000 0x40000>;
read-only;
};
partition@610000 {
label = "0:ethphyfw";
reg = <0x610000 0x80000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
};
&edma {
status = "okay";
};
&dp5 {
status = "okay";
phy-handle = <&qca8075>;
label = "lan";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Edimax-CAX1800";
qcom,ath11k-fw-memory-mode = <1>;
};

73
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8071-ax3600.dtsi"
/ {
model = "Xiaomi AX3600";
compatible = "xiaomi,ax3600", "qcom,ipq8074";
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
led_system_yellow: system-yellow {
label = "yellow:system";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
network-yellow {
label = "yellow:network";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
network-blue {
label = "blue:network";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
aiot {
label = "blue:aiot";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
};
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
status = "okay";
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
nvmem-cell-names = "calibration";
nvmem-cells = <&caldata_qca9889>;
};
};
};
&wifi {
qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
};

311
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
label-mac-device = &dp2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_0";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:qsee";
reg = <0x200000 0x300000>;
read-only;
};
partition@500000 {
label = "0:devcfg";
reg = <0x500000 0x80000>;
read-only;
};
partition@580000 {
label = "0:rpm";
reg = <0x580000 0x80000>;
read-only;
};
partition@600000 {
label = "0:cdt";
reg = <0x600000 0x80000>;
read-only;
};
partition@680000 {
label = "0:appsblenv";
reg = <0x680000 0x80000>;
};
partition@700000 {
label = "0:appsbl";
reg = <0x700000 0x100000>;
read-only;
};
partition@800000 {
label = "0:art";
reg = <0x800000 0x80000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_dp2: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_dp3: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_dp4: macaddr@12 {
reg = <0x12 0x6>;
};
macaddr_dp5: macaddr@18 {
reg = <0x18 0x6>;
};
caldata_qca9889: caldata@4d000 {
reg = <0x33000 0x844>;
};
};
partition@880000 {
label = "bdata";
reg = <0x880000 0x80000>;
};
partition@900000 {
/* This is crash + crash_syslog parts combined */
label = "pstore";
reg = <0x900000 0x100000>;
};
/* Make the first rootfs a dedicated ubi partition for kernel */
partition@a00000 {
label = "ubi_kernel";
reg = <0xa00000 0x23c0000>;
};
/* Place the real rootfs in the original second rootfs and
* expand it to the end of the nand
*/
rootfs: partition@2dc0000 {
label = "rootfs";
reg = <0x2dc0000 0xd240000>;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8075_4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
};
&edma {
status = "okay";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "wan";
nvmem-cells = <&macaddr_dp2>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan1";
nvmem-cells = <&macaddr_dp3>;
nvmem-cell-names = "mac-address";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan2";
nvmem-cells = <&macaddr_dp4>;
nvmem-cell-names = "mac-address";
};
&dp5 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan3";
nvmem-cells = <&macaddr_dp5>;
nvmem-cell-names = "mac-address";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
/dts-v1/;
#include "ipq8071-ax3600.dtsi"
/ {
model = "Redmi AX6";
compatible = "redmi,ax6", "qcom,ipq8074";
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
led_system_yellow: system-yellow {
label = "yellow:system";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
network-blue {
label = "blue:network";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
network-yellow {
label = "yellow:network";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
};
};
/* AX6 can both have NAND of 256MiB or 128MiB.
* To be on the safe side, assume 128MiB of NAND.
*/
&rootfs {
reg = <0x2dc0000 0x5220000>;
};
&wifi {
qcom,ath11k-calibration-variant = "Redmi-AX6";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Matthew Hagan <mnhagan88@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Edgecore EAP102";
compatible = "edgecore,eap102", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
led-boot = &led_system_green;
led-failsafe = &led_system_green;
led-running = &led_system_green;
led-upgrade = &led_system_green;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp5;
ethernet1 = &dp6;
label-mac-device = &dp5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_wanpoe {
label = "green:wanpoe";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_wlan2g {
label = "green:wlan2g";
gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1radio";
};
led_wlan5g {
label = "green:wlan5g";
gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0radio";
};
led_system_green: led_system {
label = "green:power";
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio66";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_spi1 {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsblenv";
reg = <0x480000 0x10000>;
};
partition@490000 {
label = "0:appsbl";
reg = <0x490000 0xc0000>;
read-only;
};
partition@550000 {
label = "0:appsbl_1";
reg = <0x530000 0xc0000>;
read-only;
};
partition@610000 {
label = "0:art";
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x650000 0x80000>;
read-only;
};
partition@6d0000 {
label = "0:product_info";
reg = <0x6d0000 0x80000>;
read-only;
};
partition@750000 {
label = "priv_data1";
reg = <0x750000 0x10000>;
read-only;
};
partition@760000 {
label = "priv_data2";
reg = <0x760000 0x10000>;
read-only;
};
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&crypto {
status = "okay";
};
&cryptobam {
status = "okay";
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs1";
reg = <0x0000000 0x3400000>;
};
partition@3400000 {
label = "0:wififw";
reg = <0x3400000 0x800000>;
read-only;
};
partition@3c00000 {
label = "rootfs2";
reg = <0x3c00000 0x3400000>;
};
partition@7000000 {
label = "0:wififw_1";
reg = <0x7000000 0x800000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
qca8081_24: ethernet-phy@24 {
compatible = "ethernet-phy-id004d.d101";
reg = <24>;
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
qca8081_28: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0xff>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@4 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp5 {
status = "okay";
phy-handle = <&qca8081_28>;
label = "wan";
};
&dp6 {
status = "okay";
phy-handle = <&qca8081_24>;
label = "lan";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Edgecore-EAP102";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "QNAP 301w";
compatible = "qnap,301w", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_pwr_green;
led-upgrade = &led_system_red;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6_syn;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wps-button {
label = "wps";
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset-button {
label = "reset";
gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_system_green: led-system-green {
label = "green:system";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_system_red: led-system-red {
label = "red:system";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
led_pwr_green: led-pwr-green {
label = "green:pwr";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-wifi-green {
label = "green:wifi";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-lan4-green {
label = "green:lan4";
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-lan4-amber {
label = "amber:lan4";
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led-lan3-green {
label = "green:lan3";
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-lan3-amber {
label = "amber:lan3";
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led-lan2-green {
label = "green:lan2";
gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-lan2-amber {
label = "amber:lan2";
gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led-lan1-green {
label = "green:lan1";
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-lan1-amber {
label = "amber:lan1";
gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led-10g-1-green {
label = "green:10g_1";
gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-10g-1-amber {
label = "amber:10g_1";
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led-10g-2-green {
label = "green:10g_2";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led-10g-2-amber {
label = "amber:10g_2";
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
};
};
&tlmm {
mdio_pins: mdio-state {
mdc-pins {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button-state {
wps-pins {
pins = "gpio57";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
rst-pins {
pins = "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds-state {
pins = "gpio1", "gpio3", "gpio4", "gpio6", "gpio7", "gpio8",
"gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio42",
"gpio51", "gpio52", "gpio54", "gpio56";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
aqr113c_0: ethernet-phy@0 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
};
aqr113c_8: ethernet-phy@8 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
qca8075_16: ethernet-phy@16 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <16>;
};
qca8075_17: ethernet-phy@17 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <17>;
};
qca8075_18: ethernet-phy@18 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <18>;
};
qca8075_19: ethernet-phy@19 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <19>;
};
};
&sdhc_1 {
status = "okay";
/* According to the stock dts from the QNAP gpl drop
* the emmc has a problem with the hs400 > hs200 speed switch.
* Therefore remove the mmc-hs400-1_8v property
*/
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
vqmmc-supply = <&l11>;
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0xc0>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <16>;
};
port@1 {
port_id = <2>;
phy_address = <17>;
};
port@2 {
port_id = <3>;
phy_address = <18>;
};
port@3 {
port_id = <4>;
phy_address = <19>;
};
port@4 {
port_id = <5>;
phy_address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
port@5 {
port_id = <6>;
phy_address = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
};
};
&edma {
status = "okay";
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_16>;
label = "lan4";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_17>;
label = "lan3";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_18>;
label = "lan2";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_19>;
label = "lan1";
};
&dp5 {
status = "okay";
qcom,mactype = <1>;
phy-handle = <&aqr113c_8>;
label = "10g-1";
};
&dp6_syn {
status = "okay";
phy-handle = <&aqr113c_0>;
label = "10g-2";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "QNAP-301w";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Xiaomi AX9000";
compatible = "xiaomi,ax9000", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
label-mac-device = &dp5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_0";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps"; /* Labeled Mesh on the device */
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
led_system_yellow: system-yellow {
label = "yellow:system";
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
};
network-yellow {
label = "yellow:network";
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
};
network-blue {
label = "blue:network";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
top-red {
label = "red:top";
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
default-state = "keep";
};
top-green {
label = "green:top";
gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
default-state = "keep";
};
top-blue {
label = "blue:top";
gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
default-state = "keep";
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
i2c_pins: i2c-pins {
pins = "gpio0", "gpio2";
function = "blsp5_i2c";
drive-strength = <8>;
bias-disable;
};
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_i2c6 {
status = "okay";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "0:mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "0:bootconfig";
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "0:bootconfig1";
reg = <0x280000 0x80000>;
read-only;
};
partition@300000 {
label = "0:qsee";
reg = <0x300000 0x300000>;
read-only;
};
partition@600000 {
label = "0:qsee_1";
reg = <0x600000 0x300000>;
read-only;
};
partition@900000 {
label = "0:devcfg";
reg = <0x900000 0x80000>;
read-only;
};
partition@980000 {
label = "0:devcfg_1";
reg = <0x980000 0x80000>;
read-only;
};
partition@a00000 {
label = "0:apdp";
reg = <0xa00000 0x80000>;
read-only;
};
partition@a80000 {
label = "0:apdp_1";
reg = <0xa80000 0x80000>;
read-only;
};
partition@b00000 {
label = "0:rpm";
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "0:rpm_1";
reg = <0xb80000 0x80000>;
read-only;
};
partition@c00000 {
label = "0:cdt";
reg = <0xc00000 0x80000>;
read-only;
};
partition@c80000 {
label = "0:cdt_1";
reg = <0xc80000 0x80000>;
read-only;
};
partition@d00000 {
label = "0:appsblenv";
reg = <0xd00000 0x80000>;
};
partition@d80000 {
label = "0:appsbl";
reg = <0xd80000 0x100000>;
read-only;
};
partition@e80000 {
label = "0:appsbl_1";
reg = <0xe80000 0x100000>;
read-only;
};
partition@f80000 {
label = "0:art";
reg = <0xf80000 0x80000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_dp1: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_dp2: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_dp3: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_dp4: macaddr@12 {
reg = <0x12 0x6>;
};
macaddr_dp5: macaddr@18 {
reg = <0x18 0x6>;
};
caldata_qca9889: caldata@4d000 {
reg = <0x4d000 0x844>;
};
};
partition@1000000 {
label = "bdata";
reg = <0x1000000 0x80000>;
};
partition@1080000 {
/* This is crash + crash_syslog parts combined */
label = "pstore";
reg = <0x1080000 0x100000>;
};
partition@1180000 {
label = "ubi_kernel";
reg = <0x1180000 0x3800000>;
};
partition@4980000 {
label = "rootfs";
reg = <0x4980000 0xb680000>;
};
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8081: ethernet-phy@24 {
compatible = "ethernet-phy-id004d.d101";
reg = <24>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_0>;
label = "lan4";
nvmem-cells = <&macaddr_dp1>;
nvmem-cell-names = "mac-address";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan3";
nvmem-cells = <&macaddr_dp2>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan2";
nvmem-cells = <&macaddr_dp3>;
nvmem-cell-names = "mac-address";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan1";
nvmem-cells = <&macaddr_dp4>;
nvmem-cell-names = "mac-address";
};
&dp5 {
status = "okay";
phy-handle = <&qca8081>;
label = "wan";
nvmem-cells = <&macaddr_dp5>;
nvmem-cell-names = "mac-address";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
status = "okay";
/* ath11k has no DT compatible for PCI cards */
compatible = "pci17cb,1104";
reg = <0x00010000 0 0 0 0>;
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
};
};
};
&pcie_qmp1 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
bridge@1,0 {
reg = <0x00010000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
status = "okay";
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
nvmem-cell-names = "calibration";
nvmem-cells = <&caldata_qca9889>;
};
};
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Dynalink DL-WRX36";
compatible = "dynalink,dl-wrx36", "qcom,ipq8074";
aliases {
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_blue;
led-upgrade = &led_system_red;
serial0 = &blsp1_uart5;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp6_syn;
ethernet1 = &dp4;
ethernet2 = &dp3;
ethernet3 = &dp2;
ethernet4 = &dp1;
label-mac-device = &dp6_syn;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
led_system_red: system-red {
label = "red:system";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8081: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xc>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
};
&edma {
status = "okay";
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_0>;
label = "lan4";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan3";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan2";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan1";
};
&dp6_syn {
status = "okay";
phy-handle = <&qca8081>;
label = "wan";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Dynalink-DL-WRX36";
};

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// SPDX-License-Identifier: GPL-2.0-only
#include "ipq8074.dtsi"
&tzapp_region {
reg = <0x0 0x4a400000 0x0 0x100000>;
};
&q6_region {
reg = <0x0 0x4b000000 0x0 0x3700000>;
};
&q6_etr_region {
reg = <0x0 0x4e700000 0x0 0x100000>;
};
&m3_dump_region {
reg = <0x0 0x4e800000 0x0 0x100000>;
};

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// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"
&CPU0 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU1 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU2 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU3 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&cpu0_thermal {
trips {
cpu0_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu1_thermal {
trips {
cpu1_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu2_thermal {
trips {
cpu2_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu3_thermal {
trips {
cpu3_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cluster_thermal {
trips {
cluster_passive: cluster-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cluster_crit: cluster_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cluster_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-only
#include "pmp8074.dtsi"
&soc {
apc_apm: apm@b111000 {
compatible = "qcom,ipq807x-apm";
reg = <0xb111000 0x1000>;
reg-names = "pm-apcc-glb";
qcom,apm-post-halt-delay = <0x2>;
qcom,apm-halt-clk-delay = <0x11>;
qcom,apm-resume-clk-delay = <0x10>;
qcom,apm-sel-switch-delay = <0x01>;
};
apc_cpr: cpr4-ctrl@b018000 {
compatible = "qcom,cpr4-ipq807x-apss-regulator";
reg = <0xb018000 0x4000>, <0xa4000 0x1000>, <0x0193d008 0x4>;
reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cpr";
qcom,cpr-ctrl-name = "apc";
qcom,cpr-sensor-time = <1000>;
qcom,cpr-loop-time = <5000000>;
qcom,cpr-idle-cycles = <15>;
qcom,cpr-step-quot-init-min = <12>;
qcom,cpr-step-quot-init-max = <14>;
qcom,cpr-count-mode = <0>; /* All-at-once */
qcom,cpr-count-repeat = <14>;
qcom,cpr-down-error-step-limit = <1>;
qcom,cpr-up-error-step-limit = <1>;
qcom,apm-ctrl = <&apc_apm>;
qcom,apm-threshold-voltage = <848000>;
vdd-supply = <&s3>;
qcom,voltage-step = <8000>;
thread@0 {
qcom,cpr-thread-id = <0>;
qcom,cpr-consecutive-up = <0>;
qcom,cpr-consecutive-down = <0>;
qcom,cpr-up-threshold = <4>;
qcom,cpr-down-threshold = <1>;
apc_vreg: regulator {
regulator-name = "apc_corner";
regulator-min-microvolt = <1>;
regulator-max-microvolt = <6>;
qcom,cpr-part-types = <2>;
qcom,cpr-parts-voltage = <1048000>;
qcom,cpr-parts-voltage-v2 = <992000>;
qcom,cpr-fuse-corners = <4>;
qcom,cpr-fuse-combos = <8>;
qcom,cpr-corners = <6>;
qcom,cpr-speed-bins = <1>;
qcom,cpr-speed-bin-corners = <6>;
qcom,cpr-corner-fmax-map = <1 3 5 6>;
qcom,allow-voltage-interpolation;
qcom,allow-quotient-interpolation;
qcom,cpr-scaled-open-loop-voltage-as-ceiling;
qcom,cpr-voltage-ceiling =
<840000 904000 944000
984000 992000 1064000>;
qcom,cpr-voltage-floor =
<592000 648000 712000
744000 784000 848000>;
qcom,corner-frequencies =
<1017600000 1382400000 1651200000
1843200000 1920000000 2208000000>;
/* TT/FF parts i.e. turbo L1 OL voltage < 1048 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 12000>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
/* SS parts i.e turbo L1 OL voltage >= 1048 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 20000 26000 0 20000>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 7000 36000 4000>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
qcom,cpr-closed-loop-voltage-adjustment-v2-0 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
qcom,cpr-closed-loop-voltage-adjustment-v2-1 =
/* Speed bin 0; CPR rev 0..7 */
< 0 0 0 0>,
< 0 0 19000 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>,
< 0 0 0 0>;
qcom,cpr-ro-scaling-factor =
< 3970 4150 0 2280 2520 2470 2250 2280
2390 2330 2530 2500 850 2900 2510 2170 >,
< 3970 4150 0 2280 2520 2470 2250 2280
2390 2330 2530 2500 850 2900 2510 2170 >,
< 3970 4150 0 2280 2520 2470 2250 2280
2390 2330 2530 2500 850 2900 2510 2170 >,
< 3970 4150 0 2280 2520 2470 2250 2280
2390 2330 2530 2500 850 2900 2510 2170 >;
qcom,cpr-floor-to-ceiling-max-range =
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>,
< 40000 40000 40000 40000 40000 40000>;
regulator-always-on;
};
};
};
npu_cpr: npu-cpr {
compatible = "qcom,cpr3-ipq807x-npu-regulator";
reg = <0xa4000 0x1000>, <0x0193d008 0x4>;
reg-names = "fuse_base", "cpr_tcsr_reg";
qcom,cpr-ctrl-name = "npu";
vdd-supply = <&s4>;
qcom,voltage-step = <8000>;
thread@0 {
qcom,cpr-thread-id = <0>;
qcom,cpr-consecutive-up = <0>;
qcom,cpr-consecutive-down = <2>;
qcom,cpr-up-threshold = <2>;
qcom,cpr-down-threshold = <1>;
npu_vreg: regulator {
regulator-name = "npu_corner";
regulator-min-microvolt = <1>;
regulator-max-microvolt = <3>;
qcom,cpr-part-types = <2>;
qcom,cpr-parts-voltage = <968000>;
qcom,cpr-parts-voltage-v2 = <832001>;
qcom,cpr-cold-temp-threshold-v2 = <30>;
qcom,cpr-fuse-corners = <2>;
qcom,cpr-fuse-combos = <1>;
qcom,cpr-corners = <2>;
qcom,cpr-speed-bins = <1>;
qcom,cpr-speed-bin-corners = <2>;
qcom,allow-voltage-interpolation;
qcom,cpr-corner-fmax-map = <1 2>;
qcom,cpr-voltage-ceiling =
<912000 992000>;
qcom,cpr-voltage-floor =
<752000 792000>;
qcom,corner-frequencies =
<1497600000 1689600000>;
/* TT/FF parts i.e. turbo OL voltage < 968 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
< 40000 40000>;
/* SS parts i.e turbo OL voltage >= 968 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
< 24000 24000>;
/* FF parts i.e. turbo OL voltage <= 832 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0=
<40000 40000>;
/* TT/SS parts i.e turbo OL voltage > 832 mV */
qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1=
<40000 40000>;
/* FF parts i.e. turbo OL voltage <= 832 mV */
qcom,cpr-cold-temp-voltage-adjustment-v2-0 =
<0 0>;
/* TT/SS parts i.e turbo OL voltage > 832 mV */
qcom,cpr-cold-temp-voltage-adjustment-v2-1 =
<35000 27000>;
};
};
};
};

531
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// SPDX-License-Identifier: GPL-2.0-only
&clocks {
bias_pll_cc_clk {
compatible = "fixed-clock";
clock-frequency = <300000000>;
#clock-cells = <0>;
};
bias_pll_nss_noc_clk {
compatible = "fixed-clock";
clock-frequency = <416500000>;
#clock-cells = <0>;
};
};
&soc {
switch: ess-switch@3a000000 {
compatible = "qcom,ess-switch-ipq807x";
reg = <0x3a000000 0x1000000>;
switch_access_mode = "local bus";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_inner_bmp = <0x80>; /*inner port bitmap*/
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
<&gcc GCC_UNIPHY0_SYS_CLK>,
<&gcc GCC_UNIPHY1_AHB_CLK>,
<&gcc GCC_UNIPHY1_SYS_CLK>,
<&gcc GCC_UNIPHY2_AHB_CLK>,
<&gcc GCC_UNIPHY2_SYS_CLK>,
<&gcc GCC_PORT1_MAC_CLK>,
<&gcc GCC_PORT2_MAC_CLK>,
<&gcc GCC_PORT3_MAC_CLK>,
<&gcc GCC_PORT4_MAC_CLK>,
<&gcc GCC_PORT5_MAC_CLK>,
<&gcc GCC_PORT6_MAC_CLK>,
<&gcc GCC_NSS_PPE_CLK>,
<&gcc GCC_NSS_PPE_CFG_CLK>,
<&gcc GCC_NSSNOC_PPE_CLK>,
<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
<&gcc GCC_NSS_EDMA_CLK>,
<&gcc GCC_NSS_EDMA_CFG_CLK>,
<&gcc GCC_NSS_PPE_IPE_CLK>,
<&gcc GCC_NSS_PPE_BTQ_CLK>,
<&gcc GCC_MDIO_AHB_CLK>,
<&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_PORT1_RX_CLK>,
<&gcc GCC_NSS_PORT1_TX_CLK>,
<&gcc GCC_NSS_PORT2_RX_CLK>,
<&gcc GCC_NSS_PORT2_TX_CLK>,
<&gcc GCC_NSS_PORT3_RX_CLK>,
<&gcc GCC_NSS_PORT3_TX_CLK>,
<&gcc GCC_NSS_PORT4_RX_CLK>,
<&gcc GCC_NSS_PORT4_TX_CLK>,
<&gcc GCC_NSS_PORT5_RX_CLK>,
<&gcc GCC_NSS_PORT5_TX_CLK>,
<&gcc GCC_NSS_PORT6_RX_CLK>,
<&gcc GCC_NSS_PORT6_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
<&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
<&gcc NSS_PORT5_RX_CLK_SRC>,
<&gcc NSS_PORT5_TX_CLK_SRC>;
clock-names = "cmn_ahb_clk", "cmn_sys_clk",
"uniphy0_ahb_clk", "uniphy0_sys_clk",
"uniphy1_ahb_clk", "uniphy1_sys_clk",
"uniphy2_ahb_clk", "uniphy2_sys_clk",
"port1_mac_clk", "port2_mac_clk",
"port3_mac_clk", "port4_mac_clk",
"port5_mac_clk", "port6_mac_clk",
"nss_ppe_clk", "nss_ppe_cfg_clk",
"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
"nss_edma_clk", "nss_edma_cfg_clk",
"nss_ppe_ipe_clk", "nss_ppe_btq_clk",
"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
"gcc_nssnoc_snoc_clk",
"gcc_mem_noc_nss_axi_clk",
"gcc_nss_crypto_clk",
"gcc_nss_imem_clk",
"gcc_nss_ptp_ref_clk",
"nss_port1_rx_clk", "nss_port1_tx_clk",
"nss_port2_rx_clk", "nss_port2_tx_clk",
"nss_port3_rx_clk", "nss_port3_tx_clk",
"nss_port4_rx_clk", "nss_port4_tx_clk",
"nss_port5_rx_clk", "nss_port5_tx_clk",
"nss_port6_rx_clk", "nss_port6_tx_clk",
"uniphy0_port1_rx_clk",
"uniphy0_port1_tx_clk",
"uniphy0_port2_rx_clk",
"uniphy0_port2_tx_clk",
"uniphy0_port3_rx_clk",
"uniphy0_port3_tx_clk",
"uniphy0_port4_rx_clk",
"uniphy0_port4_tx_clk",
"uniphy0_port5_rx_clk",
"uniphy0_port5_tx_clk",
"uniphy1_port5_rx_clk",
"uniphy1_port5_tx_clk",
"uniphy2_port6_rx_clk",
"uniphy2_port6_tx_clk",
"nss_port5_rx_clk_src",
"nss_port5_tx_clk_src";
resets = <&gcc GCC_PPE_FULL_RESET>,
<&gcc GCC_UNIPHY0_SOFT_RESET>,
<&gcc GCC_UNIPHY0_XPCS_RESET>,
<&gcc GCC_UNIPHY1_SOFT_RESET>,
<&gcc GCC_UNIPHY1_XPCS_RESET>,
<&gcc GCC_UNIPHY2_SOFT_RESET>,
<&gcc GCC_UNIPHY2_XPCS_RESET>,
<&gcc GCC_NSSPORT1_RESET>,
<&gcc GCC_NSSPORT2_RESET>,
<&gcc GCC_NSSPORT3_RESET>,
<&gcc GCC_NSSPORT4_RESET>,
<&gcc GCC_NSSPORT5_RESET>,
<&gcc GCC_NSSPORT6_RESET>;
reset-names = "ppe_rst", "uniphy0_soft_rst",
"uniphy0_xpcs_rst", "uniphy1_soft_rst",
"uniphy1_xpcs_rst", "uniphy2_soft_rst",
"uniphy2_xpcs_rst", "nss_port1_rst",
"nss_port2_rst", "nss_port3_rst",
"nss_port4_rst", "nss_port5_rst",
"nss_port6_rst";
mdio-bus = <&mdio>;
status = "disabled";
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
ess-uniphy@7a00000 {
compatible = "qcom,ess-uniphy";
reg = <0x7a00000 0x30000>;
uniphy_access_mode = "local bus";
};
edma: edma@3ab00000 {
compatible = "qcom,edma";
reg = <0x3ab00000 0x76900>;
reg-names = "edma-reg-base";
qcom,txdesc-ring-start = <23>;
qcom,txdesc-rings = <1>;
qcom,txcmpl-ring-start = <7>;
qcom,txcmpl-rings = <1>;
qcom,rxfill-ring-start = <7>;
qcom,rxfill-rings = <1>;
qcom,rxdesc-ring-start = <15>;
qcom,rxdesc-rings = <1>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
resets = <&gcc GCC_EDMA_HW_RESET>;
reset-names = "edma_rst";
status = "disabled";
};
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a001a00 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp5_syn: dp5-syn {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a003000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
dp6_syn: dp6-syn {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
status = "disabled";
};
};

218
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// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"
&CPU0 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU1 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU2 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU3 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&cpu0_thermal {
trips {
cpu0_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu1_thermal {
trips {
cpu1_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu2_thermal {
trips {
cpu2_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu3_thermal {
trips {
cpu3_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cluster_thermal {
trips {
cluster_passive_low: cluster-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cluster_passive_high: cluster-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cluster_crit: cluster_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cluster_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cluster_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
* Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
/ {
model = "Zyxel NBG7815";
compatible = "zyxel,nbg7815", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
/* Alias as required by u-boot to patch MAC addresses */
ethernet0 = &dp1;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <0>;
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsbl";
reg = <0x480000 0xc0000>;
read-only;
};
partition@540000 {
label = "0:appsbl_1";
reg = <0x540000 0xc0000>;
read-only;
};
partition@600000 {
compatible = "u-boot,env";
label = "0:appsblenv";
reg = <0x600000 0x10000>;
macaddr_lan: ethaddr {
};
};
partition@610000 {
label = "0:art";
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x650000 0x80000>;
read-only;
};
partition@6d0000 {
label = "0:crt";
reg = <0x6d0000 0x10000>;
read-only;
};
partition@6e0000 {
label = "dual_flag";
reg = <0x6e0000 0x10000>;
};
partition@6f0000 {
label = "reserved";
reg = <0x6f0000 0x110000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
qca8075_2: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_4: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8081: ethernet-phy@4{
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
aqr113c: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>;
switch_lan_bmp = <0x3e>;
switch_wan_bmp = <0x40>;
switch_mac_mode = <0x0>;
switch_mac_mode1 = <0xf>;
switch_mac_mode2 = <0xd>;
bm_tick_mode = <0>;
tm_tick_mode = <0>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
port@5 {
port_id = <6>;
ethernet-phy-ieee802.3-c45;
phy_address = <8>;
};
};
};
&edma {
status = "okay";
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan1";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan2";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan3";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan4";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
};
&dp5 {
status = "okay";
phy-handle = <&qca8081>;
label = "wan";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
mac-address-increment = <1>;
};
&dp6_syn {
status = "okay";
phy-handle = <&aqr113c>;
label = "10g";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address-ascii";
};
&blsp1_i2c2 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tmp103@70 {
compatible = "ti,tmp103";
reg = <0x70>;
};
};
&sdhc_1 {
status = "okay";
/* unstable, problem with the hs400 > h200 speed switch */
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
vqmmc-supply = <&l11>;
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
/ {
model = "Buffalo WXR-5950AX12";
compatible = "buffalo,wxr-5950ax12", "qcom,ipq8074";
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_power_white;
led-failsafe = &led_power_red;
led-running = &led_power_white;
led-upgrade = &led_power_white;
label-mac-device = &dp5_syn;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " ubi.mtd=user_property root=/dev/ubiblock1_0";
};
leds {
compatible = "gpio-leds";
led-0 {
label = "white:router";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
};
led-1 {
label = "red:router";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
led_power_red: led-2 {
label = "red:power";
gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
};
led_power_white: led-3 {
label = "white:power";
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_POWER;
};
led-4 {
label = "white:internet";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
};
led-5 {
label = "red:internet";
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
led-6 {
label = "red:wireless";
gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN;
};
led-7 {
label = "white:wireless";
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WLAN;
};
};
keys {
compatible = "gpio-keys";
/*
* mode: 3x position switch
*
* - ROUTER
* - AP
* - WB (Wireless Bridge)
*/
ap {
label = "mode-ap";
gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
bridge {
label = "mode-wb";
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
};
/*
* op: 2x position switch
*
* - AUTO
* - MANUAL (select Router/AP/WB manually)
*/
manual {
label = "op-manual";
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
linux,code = <BTN_2>;
};
wps {
label = "wps";
gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
reg_usb_vbus: regulator-5v-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tlmm 64 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
partition-0-appsblenv {
compatible = "fixed-partitions";
label = "0:appsblenv";
read-only;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
compatible = "u-boot,env";
label = "env-data";
reg = <0x0 0x40000>;
macaddr_appsblenv_ethaddr: ethaddr {
};
};
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/*
* RESET pins of phy chips
*
* WXR-5950AX12 has 2x RESET pins for QCA8075 and AQR113C.
* The pin of QCA8075 is for the chip and not phys in the chip, the
* pin of AQR113C is for 2x chips. So both pins are not appropriate
* to declare them as reset-gpios in phy nodes.
* Multiple entries in reset-gpios of mdio may not be supported, but
* leave the following as-is to show that the those reset pin exists.
*/
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, /* QCA8075 RESET */
<&tlmm 63 GPIO_ACTIVE_LOW>; /* AQR113C RESET (2x) */
aqr113c_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
aqr113c_2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
};
qca8075_1: ethernet-phy@18 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x18>;
};
qca8075_2: ethernet-phy@19 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x19>;
};
qca8075_3: ethernet-phy@1a {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1a>;
};
qca8075_4: ethernet-phy@1b {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1b>;
};
qca8075_5: ethernet-phy@1c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1c>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>;
switch_lan_bmp = <0x3e>;
switch_wan_bmp = <0x40>;
switch_mac_mode = <0xb>;
switch_mac_mode1 = <0xd>;
switch_mac_mode2 = <0xd>;
bm_tick_mode = <0>;
tm_tick_mode = <0>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0x18>;
};
port@1 {
port_id = <2>;
phy_address = <0x19>;
};
port@2 {
port_id = <3>;
phy_address = <0x1a>;
};
port@3 {
port_id = <4>;
phy_address = <0x1b>;
};
port@4 {
port_id = <5>;
ethernet-phy-ieee802.3-c45;
phy_address = <0x0>;
};
port@5 {
port_id = <6>;
ethernet-phy-ieee802.3-c45;
phy_address = <0x8>;
};
};
};
&edma {
status = "okay";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan4";
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
nvmem-cell-names = "mac-address-ascii";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan3";
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
nvmem-cell-names = "mac-address-ascii";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan2";
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
nvmem-cell-names = "mac-address-ascii";
};
&dp5_syn {
status = "okay";
phy-handle = <&aqr113c_1>;
label = "wan";
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
nvmem-cell-names = "mac-address-ascii";
};
&dp6_syn {
status = "okay";
phy-handle = <&aqr113c_2>;
label = "lan1";
nvmem-cells = <&macaddr_appsblenv_ethaddr>;
nvmem-cell-names = "mac-address-ascii";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
vbus-supply = <&reg_usb_vbus>;
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Buffalo-WXR-5950AX12";
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074";
compatible = "qcom,ipq8074";
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <19200000>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
};
};
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00058000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB1_AUX_CLK>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB1_PHY_BCR>,
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
usb1_ssphy: lane@58200 {
reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc*/
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
};
};
qusb_phy_1: phy@59000 {
compatible = "qcom,ipq8074-qusb2-phy";
reg = <0x00059000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
status = "disabled";
};
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00078000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
usb0_ssphy: lane@78200 {
reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
};
};
qusb_phy_0: phy@79000 {
compatible = "qcom,ipq8074-qusb2-phy";
reg = <0x00079000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
status = "disabled";
};
pcie_phy0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>;
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "pipe_clk";
clock-output-names = "pcie20_phy0_pipe_clk";
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
};
pcie_phy1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x0008e000 0x1000>;
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "pipe_clk";
clock-output-names = "pcie20_phy1_pipe_clk";
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
};
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
status = "disabled";
};
cryptobam: dma@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely = <1>;
status = "disabled";
};
crypto: crypto@73a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x0073a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
status = "disabled";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 70>;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
serial_4_pins: serial4-pinmux {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
i2c_0_pins: i2c-0-pinmux {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
spi_0_pins: spi-0-pins {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
hsuart_pins: hsuart-pins {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
qpic_pins: qpic-pins {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17";
function = "qpic";
drive-strength = <8>;
bias-disable;
};
};
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
#clock-cells = <0x1>;
#reset-cells = <0x1>;
};
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&xo>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "xo", "iface", "core";
max-frequency = <384000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "disabled";
};
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b1000 0x200>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 4>,
<&blsp_dma 5>;
dma-names = "tx", "rx";
pinctrl-0 = <&hsuart_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp1_uart5: serial@78b3000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b3000 0x200>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-0 = <&serial_4_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp1_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
dma-names = "rx", "tx";
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp1_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
dmas = <&blsp_dma 17>, <&blsp_dma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
blsp1_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
dmas = <&blsp_dma 23>, <&blsp_dma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07984000 0x1a000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
qpic_nand: nand@79b0000 {
compatible = "qcom,ipq8074-nand";
reg = <0x079b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>;
clock-names = "core", "aon";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx", "rx", "cmd";
pinctrl-0 = <&qpic_pins>;
pinctrl-names = "default";
status = "disabled";
};
usb_0: usb@8af8800 {
compatible = "qcom,dwc3";
reg = <0x08af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "sys_noc_axi",
"master",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<19200000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
dwc_0: dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
};
};
usb_1: usb@8cf8800 {
compatible = "qcom,dwc3";
reg = <0x08cf8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_SLEEP_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
clock-names = "sys_noc_axi",
"master",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<19200000>;
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
dwc_1: dwc3@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&usb1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt";
reg = <0xb017000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
timeout-sec = <30>;
};
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b128000 0x1000>;
status = "disabled";
};
};
pcie1: pci@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x00088000 0x2000>,
<0x10100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_phy1>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x10200000 0x10200000
0 0x100000 /* downstream I/O */
0x82000000 0 0x10300000 0x10300000
0 0xd00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
<&gcc GCC_PCIE1_AXI_M_CLK>,
<&gcc GCC_PCIE1_AXI_S_CLK>,
<&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_AUX_CLK>;
clock-names = "iface",
"axi_m",
"axi_s",
"ahb",
"aux";
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
<&gcc GCC_PCIE1_SLEEP_ARES>,
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE1_AHB_ARES>,
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky";
status = "disabled";
};
pcie0: pci@20000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x00080000 0x2000>,
<0x20100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_phy0>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0x20200000
0 0x100000 /* downstream I/O */
0x82000000 0 0x20300000 0x20300000
0 0xd00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_AUX_CLK>;
clock-names = "iface",
"axi_m",
"axi_s",
"ahb",
"aux";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky";
status = "disabled";
};
};
};

1
5.4/target/linux/ipq807x/generic/target.mk Normal file
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@ -0,0 +1 @@
BOARDNAME:=Generic

17
5.4/target/linux/ipq807x/image/Makefile Normal file
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@ -0,0 +1,17 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Device/Default
PROFILES := Default
KERNEL_LOADADDR := 0x41000000
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
DEVICE_DTS_DIR := $(DTS_DIR)/qcom
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
IMAGE/sysupgrade.bin/squashfs :=
endef
include $(SUBTARGET).mk
$(eval $(call BuildImage))

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@ -0,0 +1,148 @@
define Device/FitImage
KERNEL_SUFFIX := -uImage.itb
KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/FitImageLzma
KERNEL_SUFFIX := -uImage.itb
KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/UbiFit
KERNEL_IN_UBI := 1
IMAGES := factory.ubi sysupgrade.bin
IMAGE/factory.ubi := append-ubi
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
define Device/buffalo_wxr-5950ax12
$(call Device/FitImage)
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WXR-5950AX12
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@hk01
SOC := ipq8074
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_PACKAGES := ipq-wifi-buffalo_wxr-5950ax12
endef
TARGET_DEVICES += buffalo_wxr-5950ax12
define Device/dynalink_dl-wrx36
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Dynalink
DEVICE_MODEL := DL-WRX36
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@rt5010w-d350-rev0
SOC := ipq8072
DEVICE_PACKAGES := ipq-wifi-dynalink_dl-wrx36
endef
TARGET_DEVICES += dynalink_dl-wrx36
define Device/edgecore_eap102
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edgecore
DEVICE_MODEL := EAP102
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ac02
SOC := ipq8071
DEVICE_PACKAGES := ipq-wifi-edgecore_eap102
IMAGE/factory.ubi := append-ubi | qsdk-ipq-factory-nand
endef
TARGET_DEVICES += edgecore_eap102
define Device/edimax_cax1800
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edimax
DEVICE_MODEL := CAX1800
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ac03
SOC := ipq8070
DEVICE_PACKAGES := ipq-wifi-edimax_cax1800
endef
TARGET_DEVICES += edimax_cax1800
define Device/qnap_301w
$(call Device/FitImage)
DEVICE_VENDOR := QNAP
DEVICE_MODEL := 301w
DEVICE_DTS_CONFIG := config@hk01
KERNEL_SIZE := 16384k
BLOCKSIZE := 512k
SOC := ipq8072
IMAGES += factory.bin sysupgrade.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ipq-wifi-qnap_301w e2fsprogs kmod-fs-ext4 losetup
endef
TARGET_DEVICES += qnap_301w
define Device/redmi_ax6
$(call Device/xiaomi_ax3600)
DEVICE_VENDOR := Redmi
DEVICE_MODEL := AX6
DEVICE_PACKAGES := ipq-wifi-redmi_ax6
endef
TARGET_DEVICES += redmi_ax6
define Device/xiaomi_ax3600
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := AX3600
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ac04
SOC := ipq8071
KERNEL_SIZE := 36608k
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax3600 kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
ARTIFACTS := initramfs-factory.ubi
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-uImage.itb | ubinize-kernel
endif
endef
TARGET_DEVICES += xiaomi_ax3600
define Device/xiaomi_ax9000
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := AX9000
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@hk14
SOC := ipq8072
KERNEL_SIZE := 57344k
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax9000 kmod-ath11k-pci ath11k-firmware-qcn9074 \
kmod-ath10k-ct ath10k-firmware-qca9887-ct
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
ARTIFACTS := initramfs-factory.ubi
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-uImage.itb | ubinize-kernel
endif
endef
TARGET_DEVICES += xiaomi_ax9000
define Device/zyxel_nbg7815
$(call Device/FitImage)
DEVICE_VENDOR := ZYXEL
DEVICE_MODEL := NBG7815
DEVICE_DTS_CONFIG := config@nbg7815
BLOCKSIZE := 128k
PAGESIZE := 2048
SOC := ipq8074
IMAGES += factory.bin sysupgrade.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ipq-wifi-zyxel_nbg7815 kmod-ath11k-pci e2fsprogs kmod-fs-ext4 losetup \
kmod-hwmon-tmp103 kmod-bluetooth
endef
TARGET_DEVICES += zyxel_nbg7815

43
5.4/target/linux/ipq807x/patches-5.4/0001-v5.16-arm64-dts-qcom-ipq8074-add-SPMI-bus.patch Normal file
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From adf62d2727d4aa2b587e2db59eafb5be776a653c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 5 Sep 2021 18:58:16 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add SPMI bus
IPQ8074 uses SPMI for communication with the PMIC, so
since its already supported add the DT node for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210905165816.655275-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -293,6 +293,25 @@
#reset-cells = <0x1>;
};
+ spmi_bus: spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0200f000 0x001000>,
+ <0x02400000 0x800000>,
+ <0x02c00000 0x800000>,
+ <0x03800000 0x200000>,
+ <0x0200a000 0x000700>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;

26
5.4/target/linux/ipq807x/patches-5.4/0002-v5.16-arm64-dts-qcom-Update-BAM-DMA-node-name-per-DT-schem.patch Normal file
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@ -0,0 +1,26 @@
From 94343612f165fc8b4f95fcbe6fd044d6f63d4a28 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Tue, 31 Aug 2021 13:23:25 +0800
Subject: [PATCH] arm64: dts: qcom: Update BAM DMA node name per DT schema
Follow dma-controller.yaml schema to use `dma-controller` as node name
of BAM DMA devices.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -212,7 +212,7 @@
status = "disabled";
};
- cryptobam: dma@704000 {
+ cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;

40
5.4/target/linux/ipq807x/patches-5.4/0003-v5.16-arm64-dts-qcom-ipq8074-Add-QUP5-I2C-node.patch Normal file
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@ -0,0 +1,40 @@
From ccc5b088058bccdf454bd296867c47e56c415cde Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Fri, 1 Oct 2021 22:54:21 +0800
Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
Add node to support the QUP5 I2C controller inside of IPQ8074.
It is exactly the same as QUP2 controllers.
Some routers like ZTE MF269 use this bus.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -430,6 +430,21 @@
status = "disabled";
};
+ blsp1_i2c5: i2c@78b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b9000 0x600>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 21>, <&blsp_dma 20>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
blsp1_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;

53
5.4/target/linux/ipq807x/patches-5.4/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch Normal file
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@ -0,0 +1,53 @@
From 1a82d7080001d395563ad8266d120d4cf63ad0a5 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Wed, 29 Sep 2021 11:42:46 +0800
Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY
child node
'#clock-cells' is a required property of QMP PHY child node, not itself.
Move it to fix the dtbs_check warnings.
There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
child nodes already have the property.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -91,7 +91,6 @@
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00058000 0x1c4>;
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -112,6 +111,7 @@
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc*/
#phy-cells = <0>;
+ #clock-cells = <1>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
@@ -134,7 +134,6 @@
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
reg = <0x00078000 0x1c4>;
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -155,6 +154,7 @@
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
#phy-cells = <0>;
+ #clock-cells = <1>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";

94
5.4/target/linux/ipq807x/patches-5.4/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch Normal file
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@ -0,0 +1,94 @@
From a9ab8f5de2fc752e37918cfd5dcd16d625d9ecb2 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Wed, 29 Sep 2021 11:42:51 +0800
Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
IPQ8074 PCIe PHY nodes are broken in the many ways:
- '#address-cells', '#size-cells' and 'ranges' are missing.
- Child phy/lane node is missing, and the child properties like
'#phy-cells' and 'clocks' are mistakenly put into parent node.
- The clocks properties for parent node are missing.
Fix them to get the nodes comply with the bindings schema.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------
1 file changed, 36 insertions(+), 10 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -174,34 +174,60 @@
status = "disabled";
};
- pcie_phy0: phy@86000 {
+ pcie_qmp0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy0_pipe_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
+
+ pcie_phy0: phy@86200 {
+ reg = <0x86200 0x16c>,
+ <0x86400 0x200>,
+ <0x86800 0x4f4>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "pcie_0_pipe_clk";
+ };
};
- pcie_phy1: phy@8e000 {
+ pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x0008e000 0x1000>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy1_pipe_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
+
+ pcie_phy1: phy@8e200 {
+ reg = <0x8e200 0x16c>,
+ <0x8e400 0x200>,
+ <0x8e800 0x4f4>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "pcie_1_pipe_clk";
+ };
};
prng: rng@e3000 {

36
5.4/target/linux/ipq807x/patches-5.4/0007-v5.17-arm64-dts-qcom-ipq8074-add-MDIO-bus.patch Normal file
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@ -0,0 +1,36 @@
From 036e332e29ee24396ad877cc6a1275d86a1c4b3d Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 7 Oct 2021 13:58:46 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add MDIO bus
IPQ8074 uses an IPQ4019 compatible MDIO controller that is already
supported in the kernel, so add the DT node in order to use it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -230,6 +230,18 @@
};
};
+ mdio: mdio@90000 {
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x00090000 0x64>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+
+ status = "disabled";
+ };
+
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;

51
5.4/target/linux/ipq807x/patches-5.4/0008-v5.18-arm64-dts-qcom-ipq8074-add-SMEM-support.patch Normal file
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@ -0,0 +1,51 @@
From 29e135cf87900ac1da457bb27e98e30ca7f723ea Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 6 Jan 2022 22:25:12 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add SMEM support
IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already
supported by the kernel add the required DT nodes.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -76,6 +76,20 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem@4ab00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x4ab00000 0x0 0x00100000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 0>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
@@ -331,6 +345,12 @@
#reset-cells = <0x1>;
};
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01905000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,

30
5.4/target/linux/ipq807x/patches-5.4/0009-v5.18-arm64-dts-qcom-ipq8074-add-the-reserved-memory-node.patch Normal file
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@ -0,0 +1,30 @@
From 0f1cdeea7f237de21f244c06f2c102f93dbd9c4e Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Fri, 7 Jan 2022 18:24:38 +0530
Subject: [PATCH] arm64: dts: qcom: ipq8074: add the reserved-memory node
On IPQ8074, 4MB of memory is needed for TZ. So mark that region
as reserved.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
[bjorn: Squash with existing reserved-memory node]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -88,6 +88,11 @@
hwlocks = <&tcsr_mutex 0>;
};
+
+ memory@4ac00000 {
+ no-map;
+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ };
};
firmware {

36
5.4/target/linux/ipq807x/patches-5.4/0010-v5.18-arm64-dts-qcom-ipq8074-enable-the-GICv2m-support.patch Normal file
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@ -0,0 +1,36 @@
From a505f23abf0c31f40a2c3070d82e961b7c045664 Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Tue, 8 Feb 2022 21:05:24 +0530
Subject: [PATCH] arm64: dts: qcom: ipq8074: enable the GICv2m support
GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -634,9 +634,18 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ ranges = <0 0xb00a000 0xffd>;
+
+ v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0xffd>;
+ };
};
timer {

25
5.4/target/linux/ipq807x/patches-5.4/0011-v5.18-arm64-dts-qcom-ipq8074-drop-the-clock-frequency-prop.patch Normal file
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@ -0,0 +1,25 @@
From 2a73fa24be1d5a263062696f55dcc90725f9159c Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Wed, 2 Feb 2022 22:05:08 +0530
Subject: [PATCH] arm64: dts: qcom: ipq8074: drop the clock-frequency property
Drop the clock-frequency property from the MMIO timer node, since it
is already configured by the bootloader.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -670,7 +670,6 @@
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
- clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;

61
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@ -0,0 +1,61 @@
From 6f39b05b13e7be39919fd8d235bb0e63ecabf190 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 5 Apr 2022 08:34:43 +0200
Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
The DT schema expects dma channels in tx-rx order. No functional
change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -471,8 +471,8 @@
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "disabled";
@@ -488,8 +488,8 @@
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -503,8 +503,8 @@
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -518,8 +518,8 @@
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
+ dma-names = "tx", "rx";
status = "disabled";
};

68
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@ -0,0 +1,68 @@
From 61d4a1751cfe5a22e5f18478fe16ffb1ee12607d Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 5 Apr 2022 08:34:44 +0200
Subject: [PATCH] arm64: dts: qcom: align clocks in I2C/SPI with DT schema
The DT schema expects clocks core-iface order. No functional change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -467,9 +467,9 @@
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
@@ -484,9 +484,9 @@
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
@@ -499,9 +499,9 @@
#size-cells = <0>;
reg = <0x78b9000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
@@ -514,9 +514,9 @@
#size-cells = <0>;
reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
dma-names = "tx", "rx";

36
5.4/target/linux/ipq807x/patches-5.4/0014-v5.19-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addr.patch Normal file
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@ -0,0 +1,36 @@
From ee9002a825695b5dca76f758a9365ca7f7d18265 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 4 May 2022 15:19:16 +0200
Subject: [PATCH] arm64: dts: qcom: correct DWC3 node names and unit addresses
Align DWC3 USB node names with DT schema ("usb" is expected) and correct
the unit addresses to match the "reg" property. This also implies
overriding nodes by label, instead of full path.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -578,7 +578,7 @@
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
- dwc_0: dwc3@8a00000 {
+ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -618,7 +618,7 @@
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
- dwc_1: dwc3@8c00000 {
+ dwc_1: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

36
5.4/target/linux/ipq807x/patches-5.4/0015-v5.19-arm64-dts-qcom-ipq8074-add-dedicated-qcom-ipq8074-dw.patch Normal file
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@ -0,0 +1,36 @@
From 71061acf1a9343317e4d34a2c4578ed9301112cc Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 4 May 2022 15:19:17 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add dedicated qcom,ipq8074-dwc3
compatible
Add dedicated compatible for DWC3 USB node name to allow more accurate
DT schema matching.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -553,7 +553,7 @@
};
usb_0: usb@8af8800 {
- compatible = "qcom,dwc3";
+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -593,7 +593,7 @@
};
usb_1: usb@8cf8800 {
- compatible = "qcom,dwc3";
+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
reg = <0x08cf8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;

39
5.4/target/linux/ipq807x/patches-5.4/0016-v5.19-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch Normal file
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@ -0,0 +1,39 @@
From 159cbe595c1018a0172c637374ec69af643fa9f5 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 4 May 2022 15:19:22 +0200
Subject: [PATCH] arm64: dts: qcom: align DWC3 USB clocks with DT schema
Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
No functional impact expected.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -563,8 +563,8 @@
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
- clock-names = "sys_noc_axi",
- "master",
+ clock-names = "cfg_noc",
+ "core",
"sleep",
"mock_utmi";
@@ -603,8 +603,8 @@
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_SLEEP_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
- clock-names = "sys_noc_axi",
- "master",
+ clock-names = "cfg_noc",
+ "core",
"sleep",
"mock_utmi";

36
5.4/target/linux/ipq807x/patches-5.4/0017-v6.0-arm64-dts-qcom-adjust-whitespace-around.patch Normal file
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@ -0,0 +1,36 @@
From a9f7dc27469ca9588d7aa572bdfdfd5f0f1aab6a Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 26 May 2022 22:42:47 +0200
Subject: [PATCH] arm64: dts: qcom: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -119,7 +119,7 @@
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
- resets = <&gcc GCC_USB1_PHY_BCR>,
+ resets = <&gcc GCC_USB1_PHY_BCR>,
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
@@ -162,7 +162,7 @@
<&xo>;
clock-names = "aux", "cfg_ahb", "ref";
- resets = <&gcc GCC_USB0_PHY_BCR>,
+ resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";

34
5.4/target/linux/ipq807x/patches-5.4/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch Normal file
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@ -0,0 +1,34 @@
From 2e9703ffe97a1c447c0d00c061526fbeeade6107 Mon Sep 17 00:00:00 2001
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Date: Sun, 15 May 2022 03:24:19 +0530
Subject: [PATCH] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.
Fix the same.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Moved non-arm64 changes to separate commit]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -375,7 +375,7 @@
cell-index = <0>;
};
- sdhc_1: sdhci@7824900 {
+ sdhc_1: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc_mem", "core_mem";

47
5.4/target/linux/ipq807x/patches-5.4/0019-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch Normal file
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@ -0,0 +1,47 @@
From 18363f691e931abf0e9bdc9b5169fb15aa10224d Mon Sep 17 00:00:00 2001
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Date: Sun, 15 May 2022 03:24:22 +0530
Subject: [PATCH] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names'
for sdhci nodes
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'clocks' & 'clock-names' for sdhci nodes:
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:0: 'iface' was expected
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:1: 'core' was expected
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
clock-names:2: 'xo' was expected
Fix the same by updating the offending 'dts' files.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -384,10 +384,10 @@
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&xo>,
- <&gcc GCC_SDCC1_AHB_CLK>,
- <&gcc GCC_SDCC1_APPS_CLK>;
- clock-names = "xo", "iface", "core";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>;
+ clock-names = "iface", "core", "xo";
max-frequency = <384000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;

25
5.4/target/linux/ipq807x/patches-5.4/0020-v6.0-dt-bindings-clock-qcom-ipq8074-add-PPE-crypto-clock.patch Normal file
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@ -0,0 +1,25 @@
From aa14b0c11f6442cd489d33c2855941055a3d4fa6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 15 May 2022 23:00:41 +0200
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock
Add binding for the PPE crypto clock in IPQ8074.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -233,6 +233,7 @@
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
#define GCC_PCIE0_RCHNG_CLK_SRC 225
#define GCC_PCIE0_RCHNG_CLK 226
+#define GCC_CRYPTO_PPE_CLK 227
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1

52
5.4/target/linux/ipq807x/patches-5.4/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch Normal file
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@ -0,0 +1,52 @@
From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 15 May 2022 23:00:42 +0200
Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
The built-in PPE engine has a dedicated clock for the EIP-197 crypto
engine.
So, since the required clock currently missing add support for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref
},
};
+static struct clk_branch gcc_crypto_ppe_clk = {
+ .halt_reg = 0x68310,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x68310,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
.halt_reg = 0x6830c,
.clkr = {
@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {

25
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@ -0,0 +1,25 @@
From f5441c669d5442d247c69bab3eb27c074c0dd19a Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 15 May 2022 23:00:45 +0200
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add USB GDSCs
Add bindings for the USB GDSCs found in IPQ8074 GCC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++
1 file changed, 3 insertions(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -368,4 +368,7 @@
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
+#define USB0_GDSC 0
+#define USB1_GDSC 1
+
#endif

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@ -0,0 +1,79 @@
From ff35d239b7b64f71d7dd9d0ce887647de2cacfcc Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 15 May 2022 23:00:46 +0200
Subject: [PATCH] clk: qcom: ipq8074: add USB GDSCs
Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -166,6 +166,7 @@ config IPQ_LCC_806X
config IPQ_GCC_8074
tristate "IPQ8074 Global Clock Controller"
+ select QCOM_GDSC
help
Support for global clock controller on ipq8074 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -22,6 +22,7 @@
#include "clk-alpha-pll.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
+#include "gdsc.h"
#include "reset.h"
enum {
@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s
},
};
+static struct gdsc usb0_gdsc = {
+ .gdscr = 0x3e078,
+ .pd = {
+ .name = "usb0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb1_gdsc = {
+ .gdscr = 0x3f078,
+ .pd = {
+ .name = "usb1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x4e,
.config_ctl_val = 0x200d4aa8,
@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
};
+static struct gdsc *gcc_ipq8074_gdscs[] = {
+ [USB0_GDSC] = &usb0_gdsc,
+ [USB1_GDSC] = &usb1_gdsc,
+};
+
static const struct of_device_id gcc_ipq8074_match_table[] = {
{ .compatible = "qcom,gcc-ipq8074" },
{ }
@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq
.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
.clk_hws = gcc_ipq8074_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
+ .gdscs = gcc_ipq8074_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
};
static int gcc_ipq8074_probe(struct platform_device *pdev)

43
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@ -0,0 +1,43 @@
From 53211e85006ebb9bf7fb4482288639612f3146e7 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 15 May 2022 23:00:48 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add USB power domains
Add USB power domains provided by GCC GDSCs.
Add the required #power-domain-cells to the GCC as well.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-11-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -347,6 +347,7 @@
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
#clock-cells = <0x1>;
+ #power-domain-cells = <1>;
#reset-cells = <0x1>;
};
@@ -575,6 +576,8 @@
<133330000>,
<19200000>;
+ power-domains = <&gcc USB0_GDSC>;
+
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
@@ -615,6 +618,8 @@
<133330000>,
<19200000>;
+ power-domains = <&gcc USB1_GDSC>;
+
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";

50
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@ -0,0 +1,50 @@
From 85a9cab9b9bb471eae016cdbfabd928585c23cce Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 4 Jul 2022 13:33:18 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC node
The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[bjorn: Moved node after "soc" for alphabetical ordering]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -653,14 +653,6 @@
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt";
reg = <0xb017000 0x1000>;
@@ -852,4 +844,12 @@
status = "disabled";
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
};

27
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@ -0,0 +1,27 @@
From 8e6af077ced3931ac18e37f0eb3fc6f1a20b0e4a Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 4 Jul 2022 16:35:54 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add reset to SDHCI
Add reset to SDHCI controller so it can be reset to avoid timeout issues
after software reset due to bootloader set configuration.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -389,6 +389,7 @@
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
max-frequency = <384000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;

36
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@ -0,0 +1,36 @@
From 0171978734227bdd7813bc6d805f609126e3849e Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan+linaro@kernel.org>
Date: Tue, 5 Jul 2022 13:40:22 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: drop USB PHY clock index
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -130,7 +130,7 @@
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc*/
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
@@ -173,7 +173,7 @@
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";

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@ -0,0 +1,74 @@
From a6e1d17fbfd41113bf47345e65953873e717ca63 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Tue, 14 Sep 2021 09:40:48 +0800
Subject: [PATCH] mailbox: qcom-apcs-ipc: Consolidate msm8994 type apcs_data
The msm8994 type of apcs_data is defined multiple times with different
SoC name encoded. Consolidate them on msm8994 and remove the data
duplication.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 26 +++++--------------------
1 file changed, 5 insertions(+), 21 deletions(-)
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -33,10 +33,6 @@ static const struct qcom_apcs_ipc_data i
.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
};
-static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
- .offset = 8, .clk_name = NULL
-};
-
static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
};
@@ -49,18 +45,6 @@ static const struct qcom_apcs_ipc_data m
.offset = 16, .clk_name = NULL
};
-static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
- .offset = 8, .clk_name = NULL
-};
-
-static const struct qcom_apcs_ipc_data sdm660_apcs_data = {
- .offset = 8, .clk_name = NULL
-};
-
-static const struct qcom_apcs_ipc_data sm6125_apcs_data = {
- .offset = 8, .clk_name = NULL
-};
-
static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
.offset = 12, .clk_name = NULL
};
@@ -160,21 +144,21 @@ static int qcom_apcs_ipc_remove(struct p
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data },
- { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data },
+ { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
- { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },
+ { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
- { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &sm6125_apcs_data },
+ { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
- { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &sdm660_apcs_data },
+ { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
{}
};

30
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@ -0,0 +1,30 @@
From 28e239ecd69a99748181bfdf5d2238ff1a8d0646 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:08:48 +0200
Subject: [PATCH] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock support
IPQ8074 has the APSS clock controller utilizing the same register space as
the APCS, so provide access to the APSS utilizing a child device like
IPQ6018.
IPQ6018 and IPQ8074 use the same controller and driver, so just utilize
IPQ6018 match data for IPQ8074.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -144,7 +144,7 @@ static int qcom_apcs_ipc_remove(struct p
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },

37
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@ -0,0 +1,37 @@
From aea90e172420a062197849d7914b2fa032de0228 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 7 Jul 2022 19:37:33 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add APCS node
APCS now has support for providing the APSS clocks as the child device
for IPQ8074.
So, add the required DT node for it as it will later be used as the CPU
clocksource.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Sorted node based on address]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -662,6 +662,14 @@
timeout-sec = <30>;
};
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq8074-apcs-apps-global";
+ reg = <0x0b111000 0x6000>;
+
+ #clock-cells = <1>;
+ #mbox-cells = <1>;
+ };
+
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;

54
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@ -0,0 +1,54 @@
From a3f36600fd758173c1ec315684e4ae72c6e85654 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 8 Jul 2022 15:38:45 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add #size/address-cells to DTSI
Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating
the same properties in board DTS files.
Remove the mentioned properties from current board DTS files.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 --
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 ---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++
3 files changed, 3 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -5,8 +5,6 @@
#include "ipq8074.dtsi"
/ {
- #address-cells = <0x2>;
- #size-cells = <0x2>;
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
interrupt-parent = <&intc>;
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -7,9 +7,6 @@
#include "ipq8074.dtsi"
/ {
- #address-cells = <0x2>;
- #size-cells = <0x2>;
-
interrupt-parent = <&intc>;
aliases {
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -7,6 +7,9 @@
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
model = "Qualcomm Technologies, Inc. IPQ8074";
compatible = "qcom,ipq8074";

50
5.4/target/linux/ipq807x/patches-5.4/0032-v6.0-arm64-dts-qcom-ipq8074-add-interrupt-parent-to-DTSI.patch Normal file
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@ -0,0 +1,50 @@
From 7d57ca4d56856b7f7b97adda6e97cf5db4dcce93 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 8 Jul 2022 15:38:46 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI
Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board
DTS file.
Remove interrupt-parent from existing board DTS files.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 1 -
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 --
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
3 files changed, 1 insertion(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -7,7 +7,6 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
- interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart5;
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -7,8 +7,6 @@
#include "ipq8074.dtsi"
/ {
- interrupt-parent = <&intc>;
-
aliases {
serial0 = &blsp1_uart5;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -12,6 +12,7 @@
model = "Qualcomm Technologies, Inc. IPQ8074";
compatible = "qcom,ipq8074";
+ interrupt-parent = <&intc>;
clocks {
sleep_clk: sleep_clk {

28
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@ -0,0 +1,28 @@
From a19df563230af392f2e84e57d69367f96b4a8c56 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 12 Jul 2022 16:42:43 +0200
Subject: [PATCH] arm64: dts: qcom: align SDHCI reg-names with DT schema
DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-4-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -383,7 +383,7 @@
sdhc_1: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

37
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@ -0,0 +1,37 @@
From 8f63346a74c8b3e37ffab2c7a2ddb3c08793dcc2 Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan+linaro@kernel.org>
Date: Thu, 15 Sep 2022 16:34:30 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size
The size of the PCIe PHY serdes register region is 0x1c4 and the
corresponding 'reg' property should specifically not include the
adjacent regions that are defined in the child node (e.g. tx and rx).
Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -199,7 +199,7 @@
pcie_qmp0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x00086000 0x1000>;
+ reg = <0x00086000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -227,7 +227,7 @@
pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1000>;
+ reg = <0x0008e000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;

70
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@ -0,0 +1,70 @@
From 7bd608426c407a79debea54b2b243950f330c5b8 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:24 +0200
Subject: [PATCH] clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL
config
Convert the driver to use OF match data for providing the Alpha PLL config
per compatible.
This is required for IPQ8074 support since it uses a different Alpha PLL
config.
While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make
it clear that it is for IPQ6018 only.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-5-robimarko@gmail.com
---
drivers/clk/qcom/apss-ipq-pll.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -2,6 +2,7 @@
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/clk-provider.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -36,7 +37,7 @@ static struct clk_alpha_pll ipq_pll = {
},
};
-static const struct alpha_pll_config ipq_pll_config = {
+static const struct alpha_pll_config ipq6018_pll_config = {
.l = 0x37,
.config_ctl_val = 0x04141200,
.config_ctl_hi_val = 0x0,
@@ -54,6 +55,7 @@ static const struct regmap_config ipq_pl
static int apss_ipq_pll_probe(struct platform_device *pdev)
{
+ const struct alpha_pll_config *ipq_pll_config;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
@@ -67,7 +69,11 @@ static int apss_ipq_pll_probe(struct pla
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
+ ipq_pll_config = of_device_get_match_data(&pdev->dev);
+ if (!ipq_pll_config)
+ return -ENODEV;
+
+ clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
if (ret)
@@ -78,7 +84,7 @@ static int apss_ipq_pll_probe(struct pla
}
static const struct of_device_id apss_ipq_pll_match_table[] = {
- { .compatible = "qcom,ipq6018-a53pll" },
+ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

40
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@ -0,0 +1,40 @@
From d22c8f1bd94602d1bf2b377c3befe54e749b963d Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:25 +0200
Subject: [PATCH] clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL config
Update the IPQ6018 Alpha PLL config to the latest one from the downstream
5.4 kernel[1].
This one should match the production SoC-s.
Tested on IPQ6018 CP01-C1 reference board.
[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-6-robimarko@gmail.com
---
drivers/clk/qcom/apss-ipq-pll.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -39,10 +39,14 @@ static struct clk_alpha_pll ipq_pll = {
static const struct alpha_pll_config ipq6018_pll_config = {
.l = 0x37,
- .config_ctl_val = 0x04141200,
- .config_ctl_hi_val = 0x0,
+ .config_ctl_val = 0x240d4828,
+ .config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
+ .test_ctl_val = 0x1c0000C0,
+ .test_ctl_hi_val = 0x4000,
};
static const struct regmap_config ipq_pll_regmap_config = {

47
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@ -0,0 +1,47 @@
From e0a711bd88ba98f6ab5118d248ec84fcf495d313 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:26 +0200
Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ8074
Add support for IPQ8074 since it uses the same PLL setup, however it uses
slightly different Alpha PLL config.
Alpha PLL config was obtained by dumping PLL registers from a running
device.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com
---
drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -49,6 +49,18 @@ static const struct alpha_pll_config ipq
.test_ctl_hi_val = 0x4000,
};
+static const struct alpha_pll_config ipq8074_pll_config = {
+ .l = 0x48,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x6,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+ .test_ctl_val = 0x1c000000,
+ .test_ctl_hi_val = 0x4000,
+};
+
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -89,6 +101,7 @@ static int apss_ipq_pll_probe(struct pla
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
+ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

51
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@ -0,0 +1,51 @@
From f7fb35d540240889a8f45f3fd42363cbc1a448e2 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 19 Aug 2022 00:06:20 +0200
Subject: [PATCH] clk: qcom: clk-rcg2: add rcg2 mux ops
An RCG may act as a mux that switch between 2 parents.
This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
the CPU cluster clock just switches between XO and the PLL that feeds it.
Add the required ops to add support for this special configuration and use
the generic mux function to determine the rate.
This way we dont have to keep a essentially dummy frequency table to use
RCG2 as a mux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
---
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 7 +++++++
2 files changed, 8 insertions(+)
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
extern const struct clk_ops clk_rcg2_ops;
extern const struct clk_ops clk_rcg2_floor_ops;
+extern const struct clk_ops clk_rcg2_mux_closest_ops;
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
extern const struct clk_ops clk_byte2_ops;
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
};
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
+const struct clk_ops clk_rcg2_mux_closest_ops = {
+ .determine_rate = __clk_mux_determine_rate_closest,
+ .get_parent = clk_rcg2_get_parent,
+ .set_parent = clk_rcg2_set_parent,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
+
struct frac_entry {
int num;
int den;

63
5.4/target/linux/ipq807x/patches-5.4/0039-v6.1-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch Normal file
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@ -0,0 +1,63 @@
From 6b9d5ecd2913758780a0529f9b95392f330b721b Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:21 +0200
Subject: [PATCH] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
currently broken.
More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
clock.
However after debugging why it was always stuck at 800Mhz, it was figured
out that its not regmap_mux compatible at all.
It is a simple mux but it uses RCG2 register layout and control bits, so
utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
having to provide a dummy frequency table.
While we are here, use ARRAY_SIZE for number of parents.
Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
---
drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -16,7 +16,7 @@
#include "clk-regmap.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
-#include "clk-regmap-mux.h"
+#include "clk-rcg.h"
enum {
P_XO,
@@ -33,16 +33,15 @@ static const struct parent_map parents_a
{ P_APSS_PLL_EARLY, 5 },
};
-static struct clk_regmap_mux apcs_alias0_clk_src = {
- .reg = 0x0050,
- .width = 3,
- .shift = 7,
+static struct clk_rcg2 apcs_alias0_clk_src = {
+ .cmd_rcgr = 0x0050,
+ .hid_width = 5,
.parent_map = parents_apcs_alias0_clk_src_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apcs_alias0_clk_src",
.parent_data = parents_apcs_alias0_clk_src,
- .num_parents = 2,
- .ops = &clk_regmap_mux_closest_ops,
+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
+ .ops = &clk_rcg2_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};

32
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@ -0,0 +1,32 @@
From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:28 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
Add the required node for A53 PLL which will be used to provide the CPU
clock via APCS for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -674,6 +674,14 @@
#mbox-cells = <1>;
};
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq8074-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;

32
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@ -0,0 +1,32 @@
From 23c5ff3143ce43a76eebdf60a93436de9db39a7a Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:27 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: correct APCS register space size
APCS DTS addition that was merged, was not supposed to get merged as it
was part of patch series that was superseded by 2 more patch series
that resolved issues with this one and greatly simplified things.
Since it already got merged, start by correcting the register space
size as APCS will not be providing regmap for PLL and it will conflict
with the standalone A53 PLL node.
Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-8-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -668,7 +668,7 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0x6000>;
+ reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
#mbox-cells = <1>;

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@ -0,0 +1,134 @@
From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:42 +0200
Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
signaling both up/low and critical trips.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 1 +
drivers/thermal/qcom/tsens-v0_1.c | 1 +
drivers/thermal/qcom/tsens-v1.c | 1 +
drivers/thermal/qcom/tsens-v2.c | 1 +
drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
drivers/thermal/qcom/tsens.h | 2 ++
6 files changed, 38 insertions(+), 6 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
static struct tsens_features tsens_8960_feat = {
.ver_major = VER_0,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_p
static struct tsens_features tsens_v0_1_feat = {
.ver_major = VER_0_1,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_p
static struct tsens_features tsens_v1_feat = {
.ver_major = VER_1_X,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -31,6 +31,7 @@
static struct tsens_features tsens_v2_feat = {
.ver_major = VER_2_X,
.crit_int = 1,
+ .combo_int = 0,
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -531,6 +531,27 @@ static irqreturn_t tsens_irq_thread(int
return IRQ_HANDLED;
}
+/**
+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
+ * @irq: irq number
+ * @data: tsens controller private data
+ *
+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
+ * critical handler first and then the up/low one.
+ *
+ * Return: IRQ_HANDLED
+ */
+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
+{
+ irqreturn_t ret;
+
+ ret = tsens_critical_irq_thread(irq, data);
+ if (ret != IRQ_HANDLED)
+ return ret;
+
+ return tsens_irq_thread(irq, data);
+}
+
static int tsens_set_trips(void *_sensor, int low, int high)
{
struct tsens_sensor *s = _sensor;
@@ -1075,13 +1096,18 @@ static int tsens_register(struct tsens_p
tsens_mC_to_hw(priv->sensor, 0));
}
- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
- if (ret < 0)
- return ret;
+ if (priv->feat->combo_int) {
+ ret = tsens_register_irq(priv, "combined",
+ tsens_combined_irq_thread);
+ } else {
+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+ if (ret < 0)
+ return ret;
- if (priv->feat->crit_int)
- ret = tsens_register_irq(priv, "critical",
- tsens_critical_irq_thread);
+ if (priv->feat->crit_int)
+ ret = tsens_register_irq(priv, "critical",
+ tsens_critical_irq_thread);
+ }
return ret;
}
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -495,6 +495,7 @@ enum regfield_ids {
* struct tsens_features - Features supported by the IP
* @ver_major: Major number of IP version
* @crit_int: does the IP support critical interrupts?
+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
* @adc: do the sensors only output adc code (instead of temperature)?
* @srot_split: does the IP neatly splits the register space into SROT and TM,
* with SROT only being available to secure boot firmware?
@@ -504,6 +505,7 @@ enum regfield_ids {
struct tsens_features {
unsigned int ver_major;
unsigned int crit_int:1;
+ unsigned int combo_int:1;
unsigned int adc:1;
unsigned int srot_split:1;
unsigned int has_watchdog:1;

101
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@ -0,0 +1,101 @@
From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:43 +0200
Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
IPQ8074 and IPQ6018 dont support negative trip temperatures and support
up to 204 degrees C as the max trip temperature.
So, instead of always setting the -40 as min and 120 degrees C as max
allow it to be configured as part of the features.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 2 ++
drivers/thermal/qcom/tsens-v0_1.c | 2 ++
drivers/thermal/qcom/tsens-v1.c | 2 ++
drivers/thermal/qcom/tsens-v2.c | 2 ++
drivers/thermal/qcom/tsens.c | 4 ++--
drivers/thermal/qcom/tsens.h | 4 ++++
6 files changed, 14 insertions(+), 2 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
struct tsens_plat_data data_8960 = {
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_fe
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
hw_id, __func__, low, high);
- cl_high = clamp_val(high, -40000, 120000);
- cl_low = clamp_val(low, -40000, 120000);
+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
high_val = tsens_mC_to_hw(s, cl_high);
low_val = tsens_mC_to_hw(s, cl_low);
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -501,6 +501,8 @@ enum regfield_ids {
* with SROT only being available to secure boot firmware?
* @has_watchdog: does this IP support watchdog functionality?
* @max_sensors: maximum sensors supported by this version of the IP
+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
*/
struct tsens_features {
unsigned int ver_major;
@@ -510,6 +512,8 @@ struct tsens_features {
unsigned int srot_split:1;
unsigned int has_watchdog:1;
unsigned int max_sensors;
+ int trip_min_temp;
+ int trip_max_temp;
};
/**

74
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@ -0,0 +1,74 @@
From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:44 +0200
Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
it only has one IRQ, that is used for up/low as well as critical.
It also does not support negative trip temperatures.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
drivers/thermal/qcom/tsens.c | 3 +++
drivers/thermal/qcom/tsens.h | 2 +-
3 files changed, 21 insertions(+), 1 deletion(-)
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
.trip_max_temp = 120000,
};
+static struct tsens_features ipq8074_feat = {
+ .ver_major = VER_2_X,
+ .crit_int = 1,
+ .combo_int = 1,
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
+ .trip_min_temp = 0,
+ .trip_max_temp = 204000,
+};
+
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
/* ----- SROT ------ */
/* VERSION */
@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
.fields = tsens_v2_regfields,
};
+struct tsens_plat_data data_ipq8074 = {
+ .ops = &ops_generic_v2,
+ .feat = &ipq8074_feat,
+ .fields = tsens_v2_regfields,
+};
+
/* Kept around for backward compatibility with old msm8996.dtsi */
struct tsens_plat_data data_8996 = {
.num_sensors = 13,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -991,6 +991,9 @@ static const struct of_device_id tsens_t
.compatible = "qcom,ipq8064-tsens",
.data = &data_8960,
}, {
+ .compatible = "qcom,ipq8074-tsens",
+ .data = &data_ipq8074,
+ }, {
.compatible = "qcom,mdm9607-tsens",
.data = &data_9607,
}, {
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916,
extern struct tsens_plat_data data_tsens_v1, data_8976;
/* TSENS v2 targets */
-extern struct tsens_plat_data data_8996, data_tsens_v2;
+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
#endif /* __QCOM_TSENS_H__ */

130
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@ -0,0 +1,130 @@
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:45 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
IPQ8074 has a tsens v2.3.0 peripheral which monitors
temperatures around the various subsystems on the
die.
So lets add the tsens and thermal zone nodes, passive
CPU cooling will come in later patches after CPU frequency
scaling is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -273,6 +273,16 @@
status = "disabled";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq8074-tsens";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
@@ -873,4 +883,90 @@
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+ };
+
+ nss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 5>;
+ };
+
+ nss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+ };
+
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+ };
+
+ cpu2_thermal: cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 11>;
+ };
+
+ cpu3_thermal: cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 12>;
+ };
+
+ cluster_thermal: cluster-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 13>;
+ };
+
+ wcss-phyb0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 14>;
+ };
+
+ wcss-phyb1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 15>;
+ };
+ };
};

29
5.4/target/linux/ipq807x/patches-5.4/0046-v6.2-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch Normal file
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@ -0,0 +1,29 @@
From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:08:49 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
APCS now has support for providing the APSS clocks as the child device
for IPQ8074.
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
clocksource for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -679,6 +679,8 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
+ clocks = <&a53pll>, <&xo>;
+ clock-names = "pll", "xo";
#clock-cells = <1>;
#mbox-cells = <1>;

3601
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File diff suppressed because it is too large Load diff

54
5.4/target/linux/ipq807x/patches-5.4/0048-v6.1-clk-qcom-reset-Allow-specifying-custom-reset-delay.patch Normal file
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@ -0,0 +1,54 @@
From 72bc31aa621e21a7c36a7da8aa6f6a77bb234e0b Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Wed, 6 Jul 2022 15:41:29 +0200
Subject: [PATCH] clk: qcom: reset: Allow specifying custom reset delay
The amount of time required between asserting and deasserting the reset
signal can vary depending on the involved hardware component. Sometimes
1 us might not be enough and a larger delay is necessary to conform to
the specifications.
Usually this is worked around in the consuming drivers, by replacing
reset_control_reset() with a sequence of reset_control_assert(), waiting
for a custom delay, followed by reset_control_deassert().
However, in some cases the driver making use of the reset is generic and
can be used with different reset controllers. In this case the reset
time requirement is better handled directly by the reset controller
driver.
Make this possible by adding an "udelay" field to the qcom_reset_map
that allows setting a different reset delay (in microseconds).
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-4-stephan.gerhold@kernkonzept.com
---
drivers/clk/qcom/reset.c | 4 +++-
drivers/clk/qcom/reset.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/clk/qcom/reset.c
+++ b/drivers/clk/qcom/reset.c
@@ -13,8 +13,10 @@
static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
{
+ struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
+
rcdev->ops->assert(rcdev, id);
- udelay(1);
+ udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
rcdev->ops->deassert(rcdev, id);
return 0;
}
--- a/drivers/clk/qcom/reset.h
+++ b/drivers/clk/qcom/reset.h
@@ -11,6 +11,7 @@
struct qcom_reset_map {
unsigned int reg;
u8 bit;
+ u8 udelay;
};
struct regmap;

59
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@ -0,0 +1,59 @@
From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:28:59 +0100
Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
This patch adds the support for giving the complete bitmask
in reset structure and reset operation will use this bitmask
for all reset operations.
Currently, reset structure only takes a single bit for each reset
and then calculates the bitmask by using the BIT() macro.
However, this is not sufficient anymore for newer SoC-s like IPQ8074,
IPQ6018 and more, since their networking resets require multiple bits
to be asserted in order to properly reset the HW block completely.
So, in order to allow asserting multiple bits add "bitmask" field to
qcom_reset_map, and then use that bitmask value if its populated in the
driver, if its not populated, then we just default to existing behaviour
and calculate the bitmask on the fly.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
---
drivers/clk/qcom/reset.c | 4 ++--
drivers/clk/qcom/reset.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/reset.c
+++ b/drivers/clk/qcom/reset.c
@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
- mask = BIT(map->bit);
+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
}
@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
- mask = BIT(map->bit);
+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
}
--- a/drivers/clk/qcom/reset.h
+++ b/drivers/clk/qcom/reset.h
@@ -12,6 +12,7 @@ struct qcom_reset_map {
unsigned int reg;
u8 bit;
u8 udelay;
+ u32 bitmask;
};
struct regmap;

39
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@ -0,0 +1,39 @@
From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:00 +0100
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
resets
Add bindings for the missing networking resets found in IPQ8074 GCC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -367,6 +367,20 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
+#define GCC_PPE_FULL_RESET 132
+#define GCC_UNIPHY0_SOFT_RESET 133
+#define GCC_UNIPHY0_XPCS_RESET 134
+#define GCC_UNIPHY1_SOFT_RESET 135
+#define GCC_UNIPHY1_XPCS_RESET 136
+#define GCC_UNIPHY2_SOFT_RESET 137
+#define GCC_UNIPHY2_XPCS_RESET 138
+#define GCC_EDMA_HW_RESET 139
+#define GCC_NSSPORT1_RESET 140
+#define GCC_NSSPORT2_RESET 141
+#define GCC_NSSPORT3_RESET 142
+#define GCC_NSSPORT4_RESET 143
+#define GCC_NSSPORT5_RESET 144
+#define GCC_NSSPORT6_RESET 145
#define USB0_GDSC 0
#define USB1_GDSC 1

41
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@ -0,0 +1,41 @@
From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:01 +0100
Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
Downstream QCA 5.4 kernel defines networking resets which are not present
in the mainline kernel but are required for the networking drivers.
So, port the downstream resets and avoid using magic values for mask,
construct mask for resets which require multiple bits to be set/cleared.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4671,6 +4671,20 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
};
static struct gdsc *gcc_ipq8074_gdscs[] = {

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@ -0,0 +1,152 @@
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:46:55 +0100
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
It appears that having only .name populated in parent_data for clocks
which are only globally searchable currently will not work as the clk core
won't copy that name if there is no .fw_name present as well.
So, populate .fw_name for all parent clocks in parent_data.
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
1 file changed, 26 insertions(+), 26 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
- { .name = "pcie20_phy0_pipe_clk" },
+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
- { .name = "pcie20_phy1_pipe_clk" },
+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_rx_clk" },
- { .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_tx_clk" },
- { .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {

36
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@ -0,0 +1,36 @@
From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 30 Oct 2022 18:57:03 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
Pass XO and sleep clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Since we are here, set cell numbers in decimal instead of hex.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -360,9 +360,11 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- #clock-cells = <0x1>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
#power-domain-cells = <1>;
- #reset-cells = <0x1>;
+ #reset-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {

52
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@ -0,0 +1,52 @@
From 0afa47c1b57ba645225b38654869a6e5d2939da5 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Fri, 6 May 2022 18:21:07 +0300
Subject: [PATCH] arm64: dts: qcom: replace deprecated perst-gpio with
perst-gpios
Replace deprecated perst-gpio and wake-gpio properties with up-to-date
perst-gpios and wake-gpios in the Qualcomm device trees.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220506152107.1527552-9-dmitry.baryshkov@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -49,12 +49,12 @@
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 0x1>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 0x1>;
};
&pcie_phy0 {
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -39,12 +39,12 @@
&pcie0 {
status = "ok";
- perst-gpio = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 0x1>;
};
&pcie1 {
status = "ok";
- perst-gpio = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 0x1>;
};
&pcie_phy0 {

57
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@ -0,0 +1,57 @@
From 0eda4c5c7704363f665f4ccf0327349faad245a4 Mon Sep 17 00:00:00 2001
From: Caleb Connolly <caleb.connolly@linaro.org>
Date: Fri, 29 Apr 2022 23:08:56 +0100
Subject: [PATCH] spmi: add a helper to look up an SPMI device from a device
node
The helper function spmi_device_from_of() takes a device node and
returns the SPMI device associated with it.
This is like of_find_device_by_node but for SPMI devices.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220429220904.137297-2-caleb.connolly@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/spmi/spmi.c | 17 +++++++++++++++++
include/linux/spmi.h | 3 +++
2 files changed, 20 insertions(+)
--- a/drivers/spmi/spmi.c
+++ b/drivers/spmi/spmi.c
@@ -387,6 +387,23 @@ static struct bus_type spmi_bus_type = {
};
/**
+ * spmi_device_from_of() - get the associated SPMI device from a device node
+ *
+ * @np: device node
+ *
+ * Returns the struct spmi_device associated with a device node or NULL.
+ */
+struct spmi_device *spmi_device_from_of(struct device_node *np)
+{
+ struct device *dev = bus_find_device_by_of_node(&spmi_bus_type, np);
+
+ if (dev)
+ return to_spmi_device(dev);
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(spmi_device_from_of);
+
+/**
* spmi_controller_alloc() - Allocate a new SPMI device
* @ctrl: associated controller
*
--- a/include/linux/spmi.h
+++ b/include/linux/spmi.h
@@ -164,6 +164,9 @@ static inline void spmi_driver_unregiste
module_driver(__spmi_driver, spmi_driver_register, \
spmi_driver_unregister)
+struct device_node;
+
+struct spmi_device *spmi_device_from_of(struct device_node *np);
int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf);
int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf,
size_t len);

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@ -0,0 +1,60 @@
From 60df90d6829d16338e2971420220395cfc289247 Mon Sep 17 00:00:00 2001
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Date: Sun, 17 Oct 2021 09:12:16 -0700
Subject: [PATCH] mfd: qcom-spmi-pmic: Sort compatibles in the driver
Sort the compatibles in the driver, to make it easier to validate that
the DT binding and driver are in sync.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211017161218.2378176-2-bjorn.andersson@linaro.org
---
drivers/mfd/qcom-spmi-pmic.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -40,27 +40,27 @@
#define PM660_SUBTYPE 0x1B
static const struct of_device_id pmic_spmi_id_table[] = {
- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
+ { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
+ { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
+ { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
+ { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
{ .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
{ .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
+ { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
+ { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
{ .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
+ { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
+ { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
{ .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE },
- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
+ { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
{ .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE },
+ { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
+ { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
+ { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
+ { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
+ { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
{ .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
+ { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
{ }
};

65
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@ -0,0 +1,65 @@
From 18921bfd81c88fb85a19683467f680897672f062 Mon Sep 17 00:00:00 2001
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Date: Sun, 17 Oct 2021 09:12:18 -0700
Subject: [PATCH] mfd: qcom-spmi-pmic: Add missing PMICs supported by socinfo
The Qualcomm socinfo driver has eight more PMICs described, add these to
the SPMI PMIC driver as well.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211017161218.2378176-4-bjorn.andersson@linaro.org
---
drivers/mfd/qcom-spmi-pmic.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -31,6 +31,8 @@
#define PM8916_SUBTYPE 0x0b
#define PM8004_SUBTYPE 0x0c
#define PM8909_SUBTYPE 0x0d
+#define PM8028_SUBTYPE 0x0e
+#define PM8901_SUBTYPE 0x0f
#define PM8950_SUBTYPE 0x10
#define PMI8950_SUBTYPE 0x11
#define PM8998_SUBTYPE 0x14
@@ -38,6 +40,13 @@
#define PM8005_SUBTYPE 0x18
#define PM660L_SUBTYPE 0x1A
#define PM660_SUBTYPE 0x1B
+#define PM8150_SUBTYPE 0x1E
+#define PM8150L_SUBTYPE 0x1f
+#define PM8150B_SUBTYPE 0x20
+#define PMK8002_SUBTYPE 0x21
+#define PM8009_SUBTYPE 0x24
+#define PM8150C_SUBTYPE 0x26
+#define SMB2351_SUBTYPE 0x29
static const struct of_device_id pmic_spmi_id_table[] = {
{ .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
@@ -45,9 +54,15 @@ static const struct of_device_id pmic_sp
{ .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
{ .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
{ .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
+ { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE },
{ .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
+ { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE },
+ { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE },
+ { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE },
+ { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE },
{ .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
{ .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
+ { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE },
{ .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
{ .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
{ .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
@@ -60,6 +75,8 @@ static const struct of_device_id pmic_sp
{ .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
{ .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
{ .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
+ { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
+ { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
{ .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
{ }
};

417
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@ -0,0 +1,417 @@
From 231f6a9f24a5e9b6e7af801ca2377970474cdf59 Mon Sep 17 00:00:00 2001
From: Caleb Connolly <caleb.connolly@linaro.org>
Date: Fri, 29 Apr 2022 23:08:57 +0100
Subject: [PATCH] mfd: qcom-spmi-pmic: expose the PMIC revid information to
clients
Some PMIC functions such as the RRADC need to be aware of the PMIC
chip revision information to implement errata or otherwise adjust
behaviour, export the PMIC information to enable this.
This is specifically required to enable the RRADC to adjust
coefficients based on which chip fab the PMIC was produced in,
this can vary per unique device and therefore has to be read at
runtime.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220429220904.137297-3-caleb.connolly@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/mfd/qcom-spmi-pmic.c | 265 ++++++++++++++++++++----------
include/soc/qcom/qcom-spmi-pmic.h | 60 +++++++
2 files changed, 235 insertions(+), 90 deletions(-)
create mode 100644 include/soc/qcom/qcom-spmi-pmic.h
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -3,11 +3,16 @@
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spmi.h>
+#include <linux/types.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
+#include <soc/qcom/qcom-spmi-pmic.h>
#define PMIC_REV2 0x101
#define PMIC_REV3 0x102
@@ -17,106 +22,140 @@
#define PMIC_TYPE_VALUE 0x51
-#define COMMON_SUBTYPE 0x00
-#define PM8941_SUBTYPE 0x01
-#define PM8841_SUBTYPE 0x02
-#define PM8019_SUBTYPE 0x03
-#define PM8226_SUBTYPE 0x04
-#define PM8110_SUBTYPE 0x05
-#define PMA8084_SUBTYPE 0x06
-#define PMI8962_SUBTYPE 0x07
-#define PMD9635_SUBTYPE 0x08
-#define PM8994_SUBTYPE 0x09
-#define PMI8994_SUBTYPE 0x0a
-#define PM8916_SUBTYPE 0x0b
-#define PM8004_SUBTYPE 0x0c
-#define PM8909_SUBTYPE 0x0d
-#define PM8028_SUBTYPE 0x0e
-#define PM8901_SUBTYPE 0x0f
-#define PM8950_SUBTYPE 0x10
-#define PMI8950_SUBTYPE 0x11
-#define PM8998_SUBTYPE 0x14
-#define PMI8998_SUBTYPE 0x15
-#define PM8005_SUBTYPE 0x18
-#define PM660L_SUBTYPE 0x1A
-#define PM660_SUBTYPE 0x1B
-#define PM8150_SUBTYPE 0x1E
-#define PM8150L_SUBTYPE 0x1f
-#define PM8150B_SUBTYPE 0x20
-#define PMK8002_SUBTYPE 0x21
-#define PM8009_SUBTYPE 0x24
-#define PM8150C_SUBTYPE 0x26
-#define SMB2351_SUBTYPE 0x29
+#define PMIC_REV4_V2 0x02
+
+struct qcom_spmi_dev {
+ int num_usids;
+ struct qcom_spmi_pmic pmic;
+};
+
+#define N_USIDS(n) ((void *)n)
static const struct of_device_id pmic_spmi_id_table[] = {
- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
- { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
- { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE },
- { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
- { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE },
- { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE },
- { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE },
- { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE },
- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
- { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE },
- { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
- { .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE },
- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
- { .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE },
- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
- { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
- { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
- { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
+ { .compatible = "qcom,pm660", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm660l", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8004", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8005", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8019", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8028", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8110", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8150", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8150b", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8150c", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8150l", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8226", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8841", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8901", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8909", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8916", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8941", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8950", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8994", .data = N_USIDS(2) },
+ { .compatible = "qcom,pm8998", .data = N_USIDS(2) },
+ { .compatible = "qcom,pma8084", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmd9635", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmi8950", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmi8962", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmi8994", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmi8998", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmk8002", .data = N_USIDS(2) },
+ { .compatible = "qcom,smb2351", .data = N_USIDS(2) },
+ { .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) },
{ }
};
-static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
+/*
+ * A PMIC can be represented by multiple SPMI devices, but
+ * only the base PMIC device will contain a reference to
+ * the revision information.
+ *
+ * This function takes a pointer to a pmic device and
+ * returns a pointer to the base PMIC device.
+ *
+ * This only supports PMICs with 1 or 2 USIDs.
+ */
+static struct spmi_device *qcom_pmic_get_base_usid(struct device *dev)
{
- unsigned int rev2, minor, major, type, subtype;
- const char *name = "unknown";
- int ret, i;
+ struct spmi_device *sdev;
+ struct qcom_spmi_dev *ctx;
+ struct device_node *spmi_bus;
+ struct device_node *other_usid = NULL;
+ int function_parent_usid, ret;
+ u32 pmic_addr;
- ret = regmap_read(map, PMIC_TYPE, &type);
- if (ret < 0)
- return;
+ sdev = to_spmi_device(dev);
+ ctx = dev_get_drvdata(&sdev->dev);
- if (type != PMIC_TYPE_VALUE)
- return;
+ /*
+ * Quick return if the function device is already in the base
+ * USID. This will always be hit for PMICs with only 1 USID.
+ */
+ if (sdev->usid % ctx->num_usids == 0)
+ return sdev;
- ret = regmap_read(map, PMIC_SUBTYPE, &subtype);
+ function_parent_usid = sdev->usid;
+
+ /*
+ * Walk through the list of PMICs until we find the sibling USID.
+ * The goal is to find the first USID which is less than the
+ * number of USIDs in the PMIC array, e.g. for a PMIC with 2 USIDs
+ * where the function device is under USID 3, we want to find the
+ * device for USID 2.
+ */
+ spmi_bus = of_get_parent(sdev->dev.of_node);
+ do {
+ other_usid = of_get_next_child(spmi_bus, other_usid);
+
+ ret = of_property_read_u32_index(other_usid, "reg", 0, &pmic_addr);
+ if (ret)
+ return ERR_PTR(ret);
+
+ sdev = spmi_device_from_of(other_usid);
+ if (pmic_addr == function_parent_usid - (ctx->num_usids - 1)) {
+ if (!sdev)
+ /*
+ * If the base USID for this PMIC hasn't probed yet
+ * but the secondary USID has, then we need to defer
+ * the function driver so that it will attempt to
+ * probe again when the base USID is ready.
+ */
+ return ERR_PTR(-EPROBE_DEFER);
+ return sdev;
+ }
+ } while (other_usid->sibling);
+
+ return ERR_PTR(-ENODATA);
+}
+
+static int pmic_spmi_load_revid(struct regmap *map, struct device *dev,
+ struct qcom_spmi_pmic *pmic)
+{
+ int ret;
+
+ ret = regmap_read(map, PMIC_TYPE, &pmic->type);
if (ret < 0)
- return;
+ return ret;
- for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) {
- if (subtype == (unsigned long)pmic_spmi_id_table[i].data)
- break;
- }
+ if (pmic->type != PMIC_TYPE_VALUE)
+ return ret;
- if (i != ARRAY_SIZE(pmic_spmi_id_table))
- name = pmic_spmi_id_table[i].compatible;
+ ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype);
+ if (ret < 0)
+ return ret;
- ret = regmap_read(map, PMIC_REV2, &rev2);
+ pmic->name = of_match_device(pmic_spmi_id_table, dev)->compatible;
+
+ ret = regmap_read(map, PMIC_REV2, &pmic->rev2);
if (ret < 0)
- return;
+ return ret;
- ret = regmap_read(map, PMIC_REV3, &minor);
+ ret = regmap_read(map, PMIC_REV3, &pmic->minor);
if (ret < 0)
- return;
+ return ret;
- ret = regmap_read(map, PMIC_REV4, &major);
+ ret = regmap_read(map, PMIC_REV4, &pmic->major);
if (ret < 0)
- return;
+ return ret;
/*
* In early versions of PM8941 and PM8226, the major revision number
@@ -124,15 +163,49 @@ static void pmic_spmi_show_revid(struct
* Increment the major revision number here if the chip is an early
* version of PM8941 or PM8226.
*/
- if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) &&
- major < 0x02)
- major++;
+ if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) &&
+ pmic->major < PMIC_REV4_V2)
+ pmic->major++;
+
+ if (pmic->subtype == PM8110_SUBTYPE)
+ pmic->minor = pmic->rev2;
+
+ dev_dbg(dev, "%x: %s v%d.%d\n",
+ pmic->subtype, pmic->name, pmic->major, pmic->minor);
+
+ return 0;
+}
+
+/**
+ * qcom_pmic_get() - Get a pointer to the base PMIC device
+ *
+ * This function takes a struct device for a driver which is a child of a PMIC.
+ * And locates the PMIC revision information for it.
+ *
+ * @dev: the pmic function device
+ * @return: the struct qcom_spmi_pmic* pointer associated with the function device
+ */
+const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev)
+{
+ struct spmi_device *sdev;
+ struct qcom_spmi_dev *spmi;
+
+ /*
+ * Make sure the device is actually a child of a PMIC
+ */
+ if (!of_match_device(pmic_spmi_id_table, dev->parent))
+ return ERR_PTR(-EINVAL);
+
+ sdev = qcom_pmic_get_base_usid(dev->parent);
- if (subtype == PM8110_SUBTYPE)
- minor = rev2;
+ if (IS_ERR(sdev))
+ return ERR_CAST(sdev);
- dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor);
+ spmi = dev_get_drvdata(&sdev->dev);
+
+ return &spmi->pmic;
}
+EXPORT_SYMBOL(qcom_pmic_get);
static const struct regmap_config spmi_regmap_config = {
.reg_bits = 16,
@@ -144,14 +217,26 @@ static const struct regmap_config spmi_r
static int pmic_spmi_probe(struct spmi_device *sdev)
{
struct regmap *regmap;
+ struct qcom_spmi_dev *ctx;
+ int ret;
regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+ ctx = devm_kzalloc(&sdev->dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->num_usids = (uintptr_t)of_device_get_match_data(&sdev->dev);
+
/* Only the first slave id for a PMIC contains this information */
- if (sdev->usid % 2 == 0)
- pmic_spmi_show_revid(regmap, &sdev->dev);
+ if (sdev->usid % ctx->num_usids == 0) {
+ ret = pmic_spmi_load_revid(regmap, &sdev->dev, &ctx->pmic);
+ if (ret < 0)
+ return ret;
+ }
+ spmi_device_set_drvdata(sdev, ctx);
return devm_of_platform_populate(&sdev->dev);
}
--- /dev/null
+++ b/include/soc/qcom/qcom-spmi-pmic.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2022 Linaro. All rights reserved.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#ifndef __QCOM_SPMI_PMIC_H__
+#define __QCOM_SPMI_PMIC_H__
+
+#include <linux/device.h>
+
+#define COMMON_SUBTYPE 0x00
+#define PM8941_SUBTYPE 0x01
+#define PM8841_SUBTYPE 0x02
+#define PM8019_SUBTYPE 0x03
+#define PM8226_SUBTYPE 0x04
+#define PM8110_SUBTYPE 0x05
+#define PMA8084_SUBTYPE 0x06
+#define PMI8962_SUBTYPE 0x07
+#define PMD9635_SUBTYPE 0x08
+#define PM8994_SUBTYPE 0x09
+#define PMI8994_SUBTYPE 0x0a
+#define PM8916_SUBTYPE 0x0b
+#define PM8004_SUBTYPE 0x0c
+#define PM8909_SUBTYPE 0x0d
+#define PM8028_SUBTYPE 0x0e
+#define PM8901_SUBTYPE 0x0f
+#define PM8950_SUBTYPE 0x10
+#define PMI8950_SUBTYPE 0x11
+#define PM8998_SUBTYPE 0x14
+#define PMI8998_SUBTYPE 0x15
+#define PM8005_SUBTYPE 0x18
+#define PM660L_SUBTYPE 0x1A
+#define PM660_SUBTYPE 0x1B
+#define PM8150_SUBTYPE 0x1E
+#define PM8150L_SUBTYPE 0x1f
+#define PM8150B_SUBTYPE 0x20
+#define PMK8002_SUBTYPE 0x21
+#define PM8009_SUBTYPE 0x24
+#define PM8150C_SUBTYPE 0x26
+#define SMB2351_SUBTYPE 0x29
+
+#define PMI8998_FAB_ID_SMIC 0x11
+#define PMI8998_FAB_ID_GF 0x30
+
+#define PM660_FAB_ID_GF 0x0
+#define PM660_FAB_ID_TSMC 0x2
+#define PM660_FAB_ID_MX 0x3
+
+struct qcom_spmi_pmic {
+ unsigned int type;
+ unsigned int subtype;
+ unsigned int major;
+ unsigned int minor;
+ unsigned int rev2;
+ const char *name;
+};
+
+const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev);
+
+#endif /* __QCOM_SPMI_PMIC_H__ */

52
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@ -0,0 +1,52 @@
From 0c309f4e86c827cd5fd2eb0e36d5d1f19927380d Mon Sep 17 00:00:00 2001
From: Caleb Connolly <caleb.connolly@linaro.org>
Date: Fri, 29 Apr 2022 23:08:58 +0100
Subject: [PATCH] mfd: qcom-spmi-pmic: read fab id on supported PMICs
The PMI8998 and PM660 expose the fab_id, this is needed by drivers like
the RRADC to calibrate ADC values.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220429220904.137297-4-caleb.connolly@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/mfd/qcom-spmi-pmic.c | 7 +++++++
include/soc/qcom/qcom-spmi-pmic.h | 1 +
2 files changed, 8 insertions(+)
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -19,6 +19,7 @@
#define PMIC_REV4 0x103
#define PMIC_TYPE 0x104
#define PMIC_SUBTYPE 0x105
+#define PMIC_FAB_ID 0x1f2
#define PMIC_TYPE_VALUE 0x51
@@ -157,6 +158,12 @@ static int pmic_spmi_load_revid(struct r
if (ret < 0)
return ret;
+ if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) {
+ ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id);
+ if (ret < 0)
+ return ret;
+ }
+
/*
* In early versions of PM8941 and PM8226, the major revision number
* started incrementing from 0 (eg 0 = v1.0, 1 = v2.0).
--- a/include/soc/qcom/qcom-spmi-pmic.h
+++ b/include/soc/qcom/qcom-spmi-pmic.h
@@ -52,6 +52,7 @@ struct qcom_spmi_pmic {
unsigned int major;
unsigned int minor;
unsigned int rev2;
+ unsigned int fab_id;
const char *name;
};

27
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@ -0,0 +1,27 @@
From 46878413ba10170aaa9b7c797816e928a11923e3 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:12 +0200
Subject: [PATCH] mfd: qcom-spmi-pmic: Add support for PMP8074
Add support for PMP8074 PMIC which is a companion PMIC for the Qualcomm
IPQ8074 SoC-s.
It shares the same subtype identifier as PM8901.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-2-robimarko@gmail.com
---
drivers/mfd/qcom-spmi-pmic.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -60,6 +60,7 @@ static const struct of_device_id pmic_sp
{ .compatible = "qcom,pmi8994", .data = N_USIDS(2) },
{ .compatible = "qcom,pmi8998", .data = N_USIDS(2) },
{ .compatible = "qcom,pmk8002", .data = N_USIDS(2) },
+ { .compatible = "qcom,pmp8074", .data = N_USIDS(2) },
{ .compatible = "qcom,smb2351", .data = N_USIDS(2) },
{ .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) },
{ }

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@ -0,0 +1,58 @@
From dedc087d43013ab6043dd1da4cd585dd4242a6bb Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 4 Jul 2022 23:23:54 +0200
Subject: [PATCH] regulator: qcom_spmi: add support for HT_P150
HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout
found in PMP8074 and PMS405 PMIC-s.
Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V
but the actual MAX output voltage depends on the exact LDO in each of
the PMIC-s.
It has a max current of 150mA, voltage step of 8mV.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220704212402.1715182-4-robimarko@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -164,6 +164,7 @@ enum spmi_regulator_subtype {
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
};
enum spmi_common_regulator_registers {
@@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_
SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
};
+static struct spmi_voltage_range ht_p150_ranges[] = {
+ SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
+};
+
static DEFINE_SPMI_SET_POINTS(pldo);
static DEFINE_SPMI_SET_POINTS(nldo1);
static DEFINE_SPMI_SET_POINTS(nldo2);
@@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660);
static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
static DEFINE_SPMI_SET_POINTS(ht_nldo);
static DEFINE_SPMI_SET_POINTS(hfs430);
+static DEFINE_SPMI_SET_POINTS(ht_p150);
static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
int len)
@@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_h
static const struct spmi_regulator_mapping supported_regulators[] = {
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
+ SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),

59
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@ -0,0 +1,59 @@
From 14789f38e03c42857613b69ff0f032e03653b246 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 4 Jul 2022 23:23:55 +0200
Subject: [PATCH] regulator: qcom_spmi: add support for HT_P600
HT_P600 is a LDO PMOS regulator based on LV P600 using HFS430 layout
found in PMP8074 and PMS405 PMIC-s.
Both PMP8074 and PMS405 define the programmable range as 1.704 to 1.896V
but the actual MAX output voltage depends on the exact LDO in each of
the PMIC-s.
Their usual voltage that they are used is 1.8V.
It has a max current of 600mA, voltage step of 8mV.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220704212402.1715182-5-robimarko@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -165,6 +165,7 @@ enum spmi_regulator_subtype {
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
+ SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
};
enum spmi_common_regulator_registers {
@@ -549,6 +550,10 @@ static struct spmi_voltage_range ht_p150
SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
};
+static struct spmi_voltage_range ht_p600_ranges[] = {
+ SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
+};
+
static DEFINE_SPMI_SET_POINTS(pldo);
static DEFINE_SPMI_SET_POINTS(nldo1);
static DEFINE_SPMI_SET_POINTS(nldo2);
@@ -570,6 +575,7 @@ static DEFINE_SPMI_SET_POINTS(ht_lvpldo)
static DEFINE_SPMI_SET_POINTS(ht_nldo);
static DEFINE_SPMI_SET_POINTS(hfs430);
static DEFINE_SPMI_SET_POINTS(ht_p150);
+static DEFINE_SPMI_SET_POINTS(ht_p600);
static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
int len)
@@ -1464,6 +1470,7 @@ static const struct regulator_ops spmi_h
static const struct spmi_regulator_mapping supported_regulators[] = {
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
+ SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),

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@ -0,0 +1,68 @@
From 3e3da8da25f81fa3f0f3a37f60d10b17d1166864 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 4 Jul 2022 23:23:57 +0200
Subject: [PATCH] regulator: qcom_spmi: add support for PMP8074 regulators
PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s.
It features 5 HF-SMPS and 13 LDO regulators.
HF-SMPS regulators are Buck HFS430 regulators.
L1, L2 and L3 are HT_N1200_ST subtype LDO regulators.
L4 is HT_N300_ST subtype LDO regulator.
L5 and L6 are HT_P600 subtype LDO regulators.
L7, L11, L12 and L13 are HT_P150 subtype LDO regulators.
L10 is HT_P50 subtype LDO regulator.
This commit adds support for all of the buck regulators and LDO-s except
for L10 as I dont have documentation on its output voltage range.
S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores
and L11 is the SDIO/eMMC I/O voltage regulator required for high speeds.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220704212402.1715182-7-robimarko@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/regulator/qcom_spmi-regulator.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -2101,6 +2101,28 @@ static const struct spmi_regulator_data
{ }
};
+static const struct spmi_regulator_data pmp8074_regulators[] = {
+ { "s1", 0x1400, "vdd_s1"},
+ { "s2", 0x1700, "vdd_s2"},
+ { "s3", 0x1a00, "vdd_s3"},
+ { "s4", 0x1d00, "vdd_s4"},
+ { "s5", 0x2000, "vdd_s5"},
+ { "l1", 0x4000, "vdd_l1_l2"},
+ { "l2", 0x4100, "vdd_l1_l2"},
+ { "l3", 0x4200, "vdd_l3_l8"},
+ { "l4", 0x4300, "vdd_l4"},
+ { "l5", 0x4400, "vdd_l5_l6_l15"},
+ { "l6", 0x4500, "vdd_l5_l6_l15"},
+ { "l7", 0x4600, "vdd_l7"},
+ { "l8", 0x4700, "vdd_l3_l8"},
+ { "l9", 0x4800, "vdd_l9"},
+ /* l10 is currently unsupported HT_P50 */
+ { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
+ { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
+ { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
+ { }
+};
+
static const struct spmi_regulator_data pms405_regulators[] = {
{ "s3", 0x1a00, "vdd_s3"},
{ }
@@ -2117,6 +2139,7 @@ static const struct of_device_id qcom_sp
{ .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
{ .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
{ .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
+ { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
{ }
};

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@ -0,0 +1,25 @@
From 204cd3516f59eb7040b814429187e674f49ba065 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 11 Jul 2022 22:34:05 +0200
Subject: [PATCH] pinctrl: qcom-pmic-gpio: add support for PMP8074
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -1167,6 +1167,8 @@ static const struct of_device_id pmic_gp
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
+ /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
+ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */

26
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@ -0,0 +1,26 @@
From 41a02abb863edca0de0373bc3deaf0639b18c589 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:13 +0200
Subject: [PATCH] iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2 ADC5
Add support for ADC5_VREF_VADC channel to rev2 ADC5 channel list.
This channel measures the VADC reference LDO output.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220818221815.346233-3-robimarko@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/iio/adc/qcom-spmi-adc5.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/iio/adc/qcom-spmi-adc5.c
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_c
SCALE_HW_CALIB_DEFAULT)
[ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
SCALE_HW_CALIB_DEFAULT)
+ [ADC5_VREF_VADC] = ADC5_CHAN_VOLT("vref_vadc", 0,
+ SCALE_HW_CALIB_DEFAULT)
[ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
SCALE_HW_CALIB_DEFAULT)
[ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,

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@ -0,0 +1,149 @@
From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:14 +0200
Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
controlled via SPMI.
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
RTC is disabled by default as there is no built-in battery so it will
loose time unless board vendor added a battery, so make it optional.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmp8074_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-vadc@2 {
+ reg = <ADC5_VREF_VADC>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmic_die: die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm: xo-temp@76 {
+ reg = <ADC5_XO_THERM_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1: thermistor1@77 {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2: thermistor2@78 {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm3: thermistor3@79 {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@131 {
+ reg = <ADC5_VPH_PWR>;
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
+ pmp8074_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ allow-set-time;
+ status = "disabled";
+ };
+
+ pmp8074_gpios: gpio@c000 {
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulators {
+ compatible = "qcom,pmp8074-regulators";
+
+ s3: s3 {
+ regulator-name = "vdd_s3";
+ regulator-min-microvolt = <592000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ s4: s4 {
+ regulator-name = "vdd_s4";
+ regulator-min-microvolt = <712000>;
+ regulator-max-microvolt = <992000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ l11: l11 {
+ regulator-name = "l11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};

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@ -0,0 +1,37 @@
From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:15 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
Since now we have control over the PMP8074 PMIC providing various system
voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
the SDHCI VQMMC supply.
This allows SDHCI controller to switch to 1.8V I/O mode and support high
speed modes like HS200 and HS400.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -3,6 +3,7 @@
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
+#include "pmp8074.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -82,6 +83,7 @@
&sdhc_1 {
status = "okay";
+ vqmmc-supply = <&l11>;
};
&qusb_phy_0 {

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@ -0,0 +1,42 @@
From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 10:29:30 +0100
Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
harcoding the cell value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -4,6 +4,7 @@
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -50,12 +51,12 @@
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_phy0 {

82
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@ -0,0 +1,82 @@
From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 7 Nov 2022 15:55:17 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Also, fix up some whitespace within comments.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
4 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#include "ipq8074-hk10.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -129,10 +129,10 @@
status = "disabled";
usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
+ reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
@@ -172,10 +172,10 @@
status = "disabled";
usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
+ reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;

60
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From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 8 Nov 2022 15:23:57 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -317,35 +317,35 @@
interrupt-controller;
#interrupt-cells = <0x2>;
- serial_4_pins: serial4-pinmux {
+ serial_4_pins: serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
- i2c_0_pins: i2c-0-pinmux {
+ i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
- hsuart_pins: hsuart-pins {
+ hsuart_pins: hsuart-state {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

50
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From a212eb94fc9f72a126df651c5d7898feaea29526 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 5 Sep 2021 19:11:31 +0200
Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 family ID-s
IPQ8074 family SoC ID-s are missing, so lets add them based on
the downstream driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan T <kathirav@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210905171131.660885-1-robimarko@gmail.com
---
drivers/soc/qcom/socinfo.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -281,19 +281,31 @@ static const struct soc_id soc_id[] = {
{ 319, "APQ8098" },
{ 321, "SDM845" },
{ 322, "MDM9206" },
+ { 323, "IPQ8074" },
{ 324, "SDA660" },
{ 325, "SDM658" },
{ 326, "SDA658" },
{ 327, "SDA630" },
{ 338, "SDM450" },
{ 341, "SDA845" },
+ { 342, "IPQ8072" },
+ { 343, "IPQ8076" },
+ { 344, "IPQ8078" },
{ 345, "SDM636" },
{ 346, "SDA636" },
{ 349, "SDM632" },
{ 350, "SDA632" },
{ 351, "SDA450" },
{ 356, "SM8250" },
+ { 375, "IPQ8070" },
+ { 376, "IPQ8071" },
+ { 389, "IPQ8072A" },
+ { 390, "IPQ8074A" },
+ { 391, "IPQ8076A" },
+ { 392, "IPQ8078A" },
{ 394, "SM6125" },
+ { 395, "IPQ8070A" },
+ { 396, "IPQ8071A" },
{ 402, "IPQ6018" },
{ 403, "IPQ6028" },
{ 421, "IPQ6000" },

47
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From 2b0fe9137aa32d7fc367bf3a1cef4fa97ece6d58 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 23 Aug 2022 22:43:51 +0200
Subject: [PATCH] phy: qcom-qmp-pcie: make pipe clock rate configurable
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
like every other PCIe QMP PHY does, so make it configurable as part of the
qmp_phy_cfg.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+ /* QMP PHY pipe clock interface rate */
+ unsigned long pipe_clock_rate;
+
/* true, if PCS block has no separate SW_RESET register */
bool no_pcs_sw_reset;
};
@@ -5139,8 +5142,15 @@ static int phy_pipe_clk_register(struct
init.ops = &clk_fixed_rate_ops;
- /* controllers using QMP phys use 125MHz pipe clock interface */
- fixed->fixed_rate = 125000000;
+ /*
+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
+ * unless other frequency is specified in the PHY config.
+ */
+ if (qmp->phys[0]->cfg->pipe_clock_rate)
+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
+ else
+ fixed->fixed_rate = 125000000;
+
fixed->hw.init = &init;
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);

200
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@ -0,0 +1,200 @@
From 23bd21d8c05109b57aa9508e88fbdbc2b6d33de7 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 23 Aug 2022 22:47:40 +0200
Subject: [PATCH] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
Gen2 one is already supported, so add the support for the Gen3 one.
It uses the same register layout as IPQ6018.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
};
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
+};
+
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -3168,6 +3295,36 @@ static const struct qmp_phy_cfg ipq8074_
.pwrdn_delay_max = 1005, /* us */
};
+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
+ .tx_tbl = ipq8074_pcie_gen3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
+ .rx_tbl = ipq8074_pcie_gen3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
+ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
+ .clk_list = ipq8074_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = ipq_pciephy_gen3_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 250000000,
+};
+
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.type = PHY_TYPE_PCIE,
.nlanes = 1,
@@ -5571,6 +5728,9 @@ static const struct of_device_id qcom_qm
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
+ .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
+ .data = &ipq8074_pciephy_gen3_cfg,
+ }, {
.compatible = "qcom,ipq6018-qmp-pcie-phy",
.data = &ipq6018_pciephy_cfg,
}, {

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