mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := flea3.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,289 @@
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx35_pins.h>
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#include <asm/arch/iomux.h>
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#include <i2c.h>
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#include <linux/types.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <netdev.h>
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#ifndef CONFIG_BOARD_EARLY_INIT_F
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#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
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#endif
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#define CCM_CCMR_CONFIG 0x003F4208
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#define ESDCTL_DDR2_CONFIG 0x007FFC3F
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#define ESDCTL_0x92220000 0x92220000
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#define ESDCTL_0xA2220000 0xA2220000
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#define ESDCTL_0xB2220000 0xB2220000
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#define ESDCTL_0x82228080 0x82228080
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#define ESDCTL_DDR2_EMR2 0x04000000
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#define ESDCTL_DDR2_EMR3 0x06000000
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#define ESDCTL_PRECHARGE 0x00000400
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#define ESDCTL_DDR2_EN_DLL 0x02000400
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#define ESDCTL_DDR2_RESET_DLL 0x00000333
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#define ESDCTL_DDR2_MR 0x00000233
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#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
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#define ESDCTL_DELAY_LINE5 0x00F49F00
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static inline void dram_wait(unsigned int count)
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{
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volatile unsigned int wait = count;
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while (wait--)
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;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void board_setup_sdram_bank(u32 start_address)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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u32 *cfg_reg, *ctl_reg;
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u32 val;
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switch (start_address) {
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case CSD0_BASE_ADDR:
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cfg_reg = &esdc->esdcfg0;
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ctl_reg = &esdc->esdctl0;
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break;
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case CSD1_BASE_ADDR:
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cfg_reg = &esdc->esdcfg1;
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ctl_reg = &esdc->esdctl1;
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break;
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default:
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return;
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}
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/* Initialize MISC register for DDR2 */
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val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
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ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
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writel(val, &esdc->esdmisc);
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val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
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writel(val, &esdc->esdmisc);
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/*
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* according to DDR2 specs, wait a while before
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* the PRECHARGE_ALL command
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*/
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dram_wait(0x20000);
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/* Load DDR2 config and timing */
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writel(ESDCTL_DDR2_CONFIG, cfg_reg);
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/* Precharge ALL */
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writel(ESDCTL_0x92220000,
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Load mode */
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writel(ESDCTL_0xB2220000,
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
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writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
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/* Precharge ALL */
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writel(ESDCTL_0x92220000,
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Set mode auto refresh : at least two refresh are required */
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writel(ESDCTL_0xA2220000,
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ctl_reg);
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writel(0xda, start_address);
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writel(0xda, start_address);
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writel(ESDCTL_0xB2220000,
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_MR);
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writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
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/* OCD mode exit */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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/* Set normal mode */
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writel(ESDCTL_0x82228080,
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ctl_reg);
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dram_wait(0x20000);
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/* Do not set delay lines, only for MDDR */
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}
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static void board_setup_sdram(void)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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/* Initialize with default values both CSD0/1 */
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writel(0x2000, &esdc->esdctl0);
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writel(0x2000, &esdc->esdctl1);
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board_setup_sdram_bank(CSD0_BASE_ADDR);
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}
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static void setup_iomux_uart3(void)
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{
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mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
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mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
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}
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static void setup_iomux_i2c(void)
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{
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int pad;
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mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
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pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
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| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
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mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
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mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
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mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
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mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
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mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
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}
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static void setup_iomux_spi(void)
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{
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mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
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}
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static void setup_iomux_fec(void)
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{
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/* setup pins for FEC */
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mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
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}
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int board_early_init_f(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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/* setup GPIO3_1 to set HighVCore signal */
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mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
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gpio_direction_output(65, 1);
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/* initialize PLL and clock configuration */
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writel(CCM_CCMR_CONFIG, &ccm->ccmr);
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writel(CCM_MPLL_532_HZ, &ccm->mpctl);
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writel(CCM_PPLL_300_HZ, &ccm->ppctl);
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/* Set the core to run at 532 Mhz */
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writel(0x00001000, &ccm->pdr0);
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/* Set-up RAM */
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board_setup_sdram();
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/* enable clocks */
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writel(readl(&ccm->cgr0) |
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MXC_CCM_CGR0_EMI_MASK |
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MXC_CCM_CGR0_EDI0_MASK |
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MXC_CCM_CGR0_EPIT1_MASK,
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&ccm->cgr0);
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writel(readl(&ccm->cgr1) |
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MXC_CCM_CGR1_FEC_MASK |
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MXC_CCM_CGR1_GPIO1_MASK |
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MXC_CCM_CGR1_GPIO2_MASK |
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MXC_CCM_CGR1_GPIO3_MASK |
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MXC_CCM_CGR1_I2C1_MASK |
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MXC_CCM_CGR1_I2C2_MASK |
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MXC_CCM_CGR1_I2C3_MASK,
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&ccm->cgr1);
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/* Set-up NAND */
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__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
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/* Set pinmux for the required peripherals */
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setup_iomux_uart3();
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setup_iomux_i2c();
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setup_iomux_fec();
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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u32 get_board_rev(void)
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{
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int rev = 0;
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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@ -0,0 +1,79 @@
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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/*
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* Configuration for the flea3 board.
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* These defines are used by the included macros and must
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* be defined first
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*/
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#define AIPS_MPR_CONFIG 0x77777777
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#define AIPS_OPACR_CONFIG 0x00000000
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_MPR_CONFIG 0x00302154
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/* SGPCR - always park on last master */
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#define MAX_SGPCR_CONFIG 0x00000010
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/* MGPCR - restore default values */
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#define MAX_MGPCR_CONFIG 0x00000000
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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#define M3IF_CONFIG 0x00000040
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#define CCM_PDR0_CONFIG 0x00801000
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/*
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* includes MX35 utility macros
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*/
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#include <asm/arch/lowlevel_macro.S>
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.globl lowlevel_init
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lowlevel_init:
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core_init
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init_aips
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init_max
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init_m3if
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mov pc, lr
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