mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,78 @@
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac_addr)
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{
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int ret;
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ushort version;
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/* I2C-0 for on-board EEPROM */
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i2c_set_bus_num(0);
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/* Check layout version for EEPROM data */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uchar *) &version, 2);
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if (ret != 0) {
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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version = be16_to_cpu(version);
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if (version < 1 || version > 3) {
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printf("Error: unknown version %d for EEPROM data\n",
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version);
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return -1;
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}
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/* Read Ethernet MAC address from EEPROM */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
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if (ret != 0)
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _LACIE_COMMON_H
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#define _LACIE_COMMON_H
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr);
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#endif
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac);
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#endif
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#endif /* _LACIE_COMMON_H */
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@ -0,0 +1,50 @@
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#
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# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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#
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# Based on original Kirkwood support which is
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS := edminiv2.o ../common/common.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,28 @@
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#
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# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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# TEXT_BASE must equal the intended FLASH location of u-boot.
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CONFIG_SYS_TEXT_BASE = 0xfff90000
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/orion5x.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
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* which CFI does not properly detect, hence the LEGACY config.
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*/
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#if defined(CONFIG_FLASH_CFI_LEGACY)
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#include <flash.h>
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
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int sect;
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if (base != CONFIG_SYS_FLASH_BASE)
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return 0;
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info->size = 0;
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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/* set each sector's start address and size based */
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for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
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info->start[sect] = base+info->size;
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info->size += sectsz[sect];
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}
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/* This flash must be accessed in 8-bits mode, no buffer. */
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info->flash_id = 0x01000000;
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->buffer_size = 0;
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/* timings are derived from the Macronix datasheet. */
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info->erase_blk_tout = 1000;
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info->write_tout = 10;
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info->buffer_write_tout = 300;
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/* Commands and addresses are for AMD mode 8-bit access. */
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info->vendor = CFI_CMDSET_AMD_LEGACY;
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info->cmd_reset = 0xF0;
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info->interface = FLASH_CFI_X8;
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info->legacy_unlock = 0;
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info->ext_addr = 0;
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info->addr_unlock1 = 0x00000aaa;
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info->addr_unlock2 = 0x00000555;
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/* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
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info->manufacturer_id = 0x22;
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info->device_id = 0xBA;
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info->device_id2 = 0;
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info->cfi_version = 0x3133;
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info->cfi_offset = 0x0000;
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info->name = "MX29LV400CB";
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return 1;
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}
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#endif /* CONFIG_SYS_FLASH_CFI */
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int board_init(void)
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{
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/* arch number of board */
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gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
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/* boot parameter start at 256th byte of RAM base */
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gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
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return 0;
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}
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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mv_phy_88e1116_init("egiga0", 8);
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -0,0 +1,52 @@
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
|
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# Marvell Semiconductor <www.marvell.com>
|
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
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endif
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|
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LIB = $(obj)lib$(BOARD).o
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|
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COBJS := $(BOARD).o ../common/common.o
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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||||
|
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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|
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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|
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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||||
|
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sinclude $(obj).depend
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|
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#########################################################################
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@ -0,0 +1,162 @@
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#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000C30 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000CCCC # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x16
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000662 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000044 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#include "net2big_v2.h"
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* GPIO configuration */
|
||||
kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
|
||||
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO, /* Request power-off */
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP13_GPIO, /* Rear power switch (on|auto) */
|
||||
MPP14_GPIO, /* USB fuse alarm */
|
||||
MPP15_GPIO, /* Rear power switch (auto|off) */
|
||||
MPP16_GPIO, /* SATA HDD1 power */
|
||||
MPP17_GPIO, /* SATA HDD2 power */
|
||||
MPP20_SATA1_ACTn,
|
||||
MPP21_SATA0_ACTn,
|
||||
MPP24_GPIO, /* USB mode select */
|
||||
MPP26_GPIO, /* USB device vbus */
|
||||
MPP28_GPIO, /* USB enable host vbus */
|
||||
MPP29_GPIO, /* GPIO extension ALE */
|
||||
MPP34_GPIO, /* Rear Push button 0=on 1=off */
|
||||
MPP35_GPIO, /* Inhibit switch power-off */
|
||||
MPP36_GPIO, /* SATA HDD1 presence */
|
||||
MPP37_GPIO, /* SATA HDD2 presence */
|
||||
MPP40_GPIO, /* eSATA presence */
|
||||
MPP44_GPIO, /* GPIO extension (data 0) */
|
||||
MPP45_GPIO, /* GPIO extension (data 1) */
|
||||
MPP46_GPIO, /* GPIO extension (data 2) */
|
||||
MPP47_GPIO, /* GPIO extension (addr 0) */
|
||||
MPP48_GPIO, /* GPIO extension (addr 1) */
|
||||
MPP49_GPIO, /* GPIO extension (addr 2) */
|
||||
0
|
||||
};
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Machine number */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
|
||||
|
||||
/* Boot parameters address */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
|
||||
if (!getenv("ethaddr")) {
|
||||
uchar mac[6];
|
||||
if (lacie_read_mac_address(mac) == 0)
|
||||
eth_setenv_enetaddr("ethaddr", mac);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
mv_phy_88e1116_init("egiga0", 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KIRKWOOD_GPIO)
|
||||
/* Return GPIO push button status */
|
||||
static int
|
||||
do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(button, 1, 1, do_read_push_button,
|
||||
"Return GPIO push button status 0=off 1=on", "");
|
||||
#endif
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NET2BIG_V2_H
|
||||
#define NET2BIG_V2_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define NET2BIG_V2_OE_LOW 0x0600E000
|
||||
#define NET2BIG_V2_OE_HIGH 0x00000134
|
||||
#define NET2BIG_V2_OE_VAL_LOW 0x10030000
|
||||
#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
|
||||
|
||||
/* Buttons */
|
||||
#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
|
||||
|
||||
#endif /* NET2BIG_V2_H */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := $(BOARD).o ../common/common.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x00000008 # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=512Mb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000000C # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#include "netspace_v2.h"
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Gpio configuration */
|
||||
kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
|
||||
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO, /* Fan speed (bit 1) */
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO, /* Red led */
|
||||
MPP14_GPIO, /* USB fuse */
|
||||
MPP16_GPIO, /* SATA 0 power */
|
||||
MPP17_GPIO, /* SATA 1 power */
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_SATA1_ACTn,
|
||||
MPP21_SATA0_ACTn,
|
||||
MPP22_GPIO, /* Fan speed (bit 0) */
|
||||
MPP23_GPIO, /* Fan power */
|
||||
MPP24_GPIO, /* USB mode select */
|
||||
MPP25_GPIO, /* Fan rotation fail */
|
||||
MPP26_GPIO, /* USB vbus-in detection */
|
||||
MPP28_GPIO, /* USB enable vbus-out */
|
||||
MPP29_GPIO, /* Blue led (slow register) */
|
||||
MPP30_GPIO, /* Blue led (command register) */
|
||||
MPP31_GPIO, /* Board power off */
|
||||
MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
|
||||
MPP33_GPIO, /* Fan speed (bit 2) */
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Machine number */
|
||||
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
|
||||
|
||||
/* Boot parameters address */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
|
||||
if (!getenv("ethaddr")) {
|
||||
uchar mac[6];
|
||||
if (lacie_read_mac_address(mac) == 0)
|
||||
eth_setenv_enetaddr("ethaddr", mac);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
mv_phy_88e1116_init("egiga0", 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KIRKWOOD_GPIO)
|
||||
/* Return GPIO button status */
|
||||
static int
|
||||
do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(button, 1, 1, do_read_button,
|
||||
"Return GPIO button status 0=off 1=on", "");
|
||||
#endif
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NETSPACE_V2_H
|
||||
#define NETSPACE_V2_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define NETSPACE_V2_OE_LOW 0x06004000
|
||||
#define NETSPACE_V2_OE_HIGH 0x00000031
|
||||
#define NETSPACE_V2_OE_VAL_LOW 0x10030000
|
||||
#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
|
||||
|
||||
#define NETSPACE_V2_GPIO_BUTTON 32
|
||||
|
||||
#endif /* NETSPACE_V2_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue