mptcp/openmptcprouter
1
0
Fork 0
mirror of https://github.com/Ysurac/openmptcprouter.git synced 2025-03-09 15:40:20 +00:00
Code Issues Releases Wiki Activity

Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport

Browse source
This commit is contained in:
Ycarus (Yannick Chabanois) 2023-04-22 08:07:24 +02:00
parent e910436a7a
commit 46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
Download patch file Download diff file Expand all files Collapse all files

44
common/package/utils/sysupgrade-helper/src/board/RPXClassic/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o eccx.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

276
common/package/utils/sysupgrade-helper/src/board/RPXClassic/RPXClassic.c Normal file
View file

@ -0,0 +1,276 @@
/*
* (C) Copyright 2001
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
* U-Boot port on RPXClassic LF (CLLF_BW31) board
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <config.h>
#include <mpc8xx.h>
#include <net.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
static unsigned char aschex_to_byte (unsigned char *cp);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
0x0CFFCC00, 0x33FFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
*/
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: RPXClassic\n");
return (0);
}
/*-----------------------------------------------------------------------------
* board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
*-----------------------------------------------------------------------------
*/
static void board_get_enetaddr(uchar *enet)
{
int i;
char buff[256], *cp;
/* Initialize I2C */
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
i2c_read (0x54, 0, 1, (uchar *)buff, 128);
i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
/* Retrieve MAC address in buffer (key EA) */
for (cp = buff;;) {
if (cp[0] == 'E' && cp[1] == 'A') {
cp += 3;
/* Read MAC address */
for (i = 0; i < 6; i++, cp += 2) {
enet[i] = aschex_to_byte ((unsigned char *)cp);
}
}
/* Scan to the end of the record */
while ((*cp != '\n') && (*cp != (char)0xff)) {
cp++;
}
/* If the next character is a \n, 0 or ff, we are done. */
cp++;
if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
break;
}
#ifdef CONFIG_FEC_ENET
/* The MAC address is the same as normal ethernet except the 3rd byte */
/* (See the E.P. Planet Core Overview manual */
enet[3] |= 0x80;
#endif
printf("MAC address = %pM\n", enet);
}
int misc_init_r(void)
{
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
board_get_enetaddr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
return 0;
}
void rpxclassic_init (void)
{
/* Enable NVRAM */
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
#ifdef CONFIG_FEC_ENET
/* Validate the fast ethernet tranceiver */
*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
#endif
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
*/
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
return (get_ram_size(base, maxsize));
}
/*-----------------------------------------------------------------------------
* aschex_to_byte --
*-----------------------------------------------------------------------------
*/
static unsigned char aschex_to_byte (unsigned char *cp)
{
u_char byte, c;
c = *cp++;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte = c * 16;
c = *cp;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte += c;
return (byte);
}

351
common/package/utils/sysupgrade-helper/src/board/RPXClassic/eccx.c Normal file
View file

@ -0,0 +1,351 @@
/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Video support for the ECCX daughter board */
#include <common.h>
#include <config.h>
#ifdef CONFIG_VIDEO_SED13806
#include <sed13806.h>
/* Screen configurations: the initialization of the SD13806 depends on
screen and on display mode. We handle only 8bpp and 16 bpp modes */
/* ECCX board is supplied with a NEC NL6448BC20 screen */
#ifdef CONFIG_NEC_NL6448BC20
#define DISPLAY_WIDTH 640
#define DISPLAY_HEIGHT 480
#ifdef CONFIG_VIDEO_SED13806_8BPP
static const S1D_REGS init_regs [] =
{
{0x0001,0x00}, /* Miscellaneous Register */
{0x01FC,0x00}, /* Display Mode Register */
{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
{0x0008,0xe5}, /* General IO Pins Control Register 0 */
{0x0009,0x1f}, /* General IO Pins Control Register 1 */
{0x0010,0x02}, /* Memory Clock Configuration Register */
{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
{0x0021,0x04}, /* DRAM Refresh Rate Register */
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
{0x0020,0x80}, /* Memory Configuration Register */
{0x0030,0x25}, /* Panel Type Register */
{0x0031,0x00}, /* MOD Rate Register */
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
{0x0040,0x03}, /* LCD Display Mode Register */
{0x0041,0x02}, /* LCD Miscellaneous Register */
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
{0x0046,0x40}, /* LCD Memory Address Offset Register 0 */
{0x0047,0x01}, /* LCD Memory Address Offset Register 1 */
{0x0048,0x00}, /* LCD Pixel Panning Register */
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
{0x005B,0x00}, /* TV Output Control Register */
{0x0060,0x03}, /* CRT/TV Display Mode Register */
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
{0x0100,0x00}, /* BitBlt Control Register 0 */
{0x0101,0x00}, /* BitBlt Control Register 1 */
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
{0x0103,0x00}, /* BitBlt Operation Register */
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
{0x0110,0x00}, /* BitBlt Width Register 0 */
{0x0111,0x00}, /* BitBlt Width Register 1 */
{0x0112,0x00}, /* BitBlt Height Register 0 */
{0x0113,0x00}, /* BitBlt Height Register 1 */
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
{0x01E0,0x00}, /* Look-Up Table Mode Register */
{0x01E2,0x00}, /* Look-Up Table Address Register */
{0x01E4,0x00}, /* Look-Up Table Data Register */
{0x01F0,0x10}, /* Power Save Configuration Register */
{0x01F1,0x00}, /* Power Save Status Register */
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
{0, 0}
};
#endif /* CONFIG_VIDEO_SED13806_8BPP */
#ifdef CONFIG_VIDEO_SED13806_16BPP
static const S1D_REGS init_regs [] =
{
{0x0001,0x00}, /* Miscellaneous Register */
{0x01FC,0x00}, /* Display Mode Register */
{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
{0x0008,0xe5}, /* General IO Pins Control Register 0 */
{0x0009,0x1f}, /* General IO Pins Control Register 1 */
{0x0010,0x02}, /* Memory Clock Configuration Register */
{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
{0x0021,0x04}, /* DRAM Refresh Rate Register */
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
{0x0020,0x80}, /* Memory Configuration Register */
{0x0030,0x25}, /* Panel Type Register */
{0x0031,0x00}, /* MOD Rate Register */
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
{0x0040,0x05}, /* LCD Display Mode Register */
{0x0041,0x02}, /* LCD Miscellaneous Register */
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
{0x0048,0x00}, /* LCD Pixel Panning Register */
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
{0x005B,0x00}, /* TV Output Control Register */
{0x0060,0x05}, /* CRT/TV Display Mode Register */
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
{0x0100,0x00}, /* BitBlt Control Register 0 */
{0x0101,0x00}, /* BitBlt Control Register 1 */
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
{0x0103,0x00}, /* BitBlt Operation Register */
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
{0x0110,0x00}, /* BitBlt Width Register 0 */
{0x0111,0x00}, /* BitBlt Width Register 1 */
{0x0112,0x00}, /* BitBlt Height Register 0 */
{0x0113,0x00}, /* BitBlt Height Register 1 */
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
{0x01E0,0x01}, /* Look-Up Table Mode Register */
{0x01E2,0x00}, /* Look-Up Table Address Register */
{0x01E4,0x00}, /* Look-Up Table Data Register */
{0x01F0,0x10}, /* Power Save Configuration Register */
{0x01F1,0x00}, /* Power Save Status Register */
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
{0, 0}
};
#endif /* CONFIG_VIDEO_SED13806_16BPP */
#endif /* CONFIG_NEC_NL6448BC20 */
#ifdef CONFIG_CONSOLE_EXTRA_INFO
/*-----------------------------------------------------------------------------
* video_get_info_str -- setup a board string: type, speed, etc.
* line_number= location to place info string beside logo
* info= buffer for info string
*-----------------------------------------------------------------------------
*/
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
strcpy (info, " RPXClassic board");
}
else {
info [0] = '\0';
}
}
#endif
/*-----------------------------------------------------------------------------
* board_video_init -- init de l'EPSON, config du CS
*-----------------------------------------------------------------------------
*/
unsigned int board_video_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* Program ECCX registers */
*(ECCX_CSR12) |= ECCX_860;
*(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
*(ECCX_CSR8) |= ECCX_ENEPSON;
memctl->memc_or2 = SED13806_OR;
memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
return (SED13806_REG_ADDR);
}
/*-----------------------------------------------------------------------------
* board_validate_screen --
*-----------------------------------------------------------------------------
*/
void board_validate_screen (unsigned int base)
{
/* Activate the panel bias power */
*(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
}
/*-----------------------------------------------------------------------------
* board_get_regs --
*-----------------------------------------------------------------------------
*/
const S1D_REGS *board_get_regs (void)
{
return (init_regs);
}
/*-----------------------------------------------------------------------------
* board_get_width --
*-----------------------------------------------------------------------------
*/
int board_get_width (void)
{
return (DISPLAY_WIDTH);
}
/*-----------------------------------------------------------------------------
* board_get_height --
*-----------------------------------------------------------------------------
*/
int board_get_height (void)
{
return (DISPLAY_HEIGHT);
}
#endif /* CONFIG_VIDEO_SED13806 */

447
common/package/utils/sysupgrade-helper/src/board/RPXClassic/flash.c Normal file
View file

@ -0,0 +1,447 @@
/*
* (C) Copyright 2001
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
* U-Boot port on RPXClassic LF (CLLF_BW31) board
*
* RPXClassic uses Am29DL323B flash memory with 2 banks
*
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 ;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000) ;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMDL323B:
printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
/* Reset flash componeny */
addr [0] = 0xf0f0f0f0;
/* Write auto select command: read Manufacturer ID */
addr[0xAAA] = 0xAAAAAAAA ;
addr[0x555] = 0x55555555 ;
addr[0xAAA] = 0x90909090 ;
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[2] ; /* device ID */
switch (value & 0x00FF00FF) {
case (AMD_ID_DL323B & 0x00FF00FF):
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000; /* 16 Mb */
break;
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000) ;
}
/* check for protected sectors */
for (i = 0; i < 23; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[4] & 1 ;
}
/* Check for protected sectors in the 2nd bank */
addr[0x100AAA] = 0xAAAAAAAA ;
addr[0x100555] = 0x55555555 ;
addr[0x100AAA] = 0x90909090 ;
for (i = 23; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[4] & 1 ;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *)info->start[0];
*addr = 0xF0F0F0F0; /* reset bank 1 */
addr = (volatile unsigned long *)info->start[23];
*addr = 0xF0F0F0F0; /* reset bank 2 */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0x80808080;
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long *)(info->start[sect]) ;
addr[0] = 0x30303030 ;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_long *)info->start[0];
addr[0] = 0xF0F0F0F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0xA0A0A0A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

96
common/package/utils/sysupgrade-helper/src/board/RPXClassic/u-boot.lds Normal file
View file

@ -0,0 +1,96 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end__ = . ;
PROVIDE (end = .);
}

135
common/package/utils/sysupgrade-helper/src/board/RPXClassic/u-boot.lds.debug Normal file
View file

@ -0,0 +1,135 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end__ = . ;
PROVIDE (end = .);
}