mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,425 @@
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/*
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* (C) Copyright 2006
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* Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
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* w.wegner@astro-kom.de
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*
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* based on the files by
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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* and
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
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#include <common.h>
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#include <watchdog.h>
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#include <altera.h>
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#include <ACEX1K.h>
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#include <spartan3.h>
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#include <command.h>
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#include <asm/immap_5329.h>
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#include <asm/io.h>
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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int altera_pre_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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unsigned char tmp_char;
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unsigned short tmp_short;
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/* first, set the required pins to GPIO function */
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/* PAR_T0IN -> GPIO */
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tmp_char = readb(&gpiop->par_timer);
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tmp_char &= 0xfc;
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writeb(tmp_char, &gpiop->par_timer);
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/* all QSPI pins -> GPIO */
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writew(0x0000, &gpiop->par_qspi);
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/* U0RTS, U0CTS -> GPIO */
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tmp_short = __raw_readw(&gpiop->par_uart);
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tmp_short &= 0xfff3;
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__raw_writew(tmp_short, &gpiop->par_uart);
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/* all PWM pins -> GPIO */
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writeb(0x00, &gpiop->par_pwm);
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/* next, set data direction registers */
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writeb(0x01, &gpiop->pddr_timer);
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writeb(0x25, &gpiop->pddr_qspi);
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writeb(0x0c, &gpiop->pddr_uart);
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writeb(0x04, &gpiop->pddr_pwm);
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/* ensure other SPI peripherals are deselected */
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writeb(0x08, &gpiop->ppd_uart);
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writeb(0x38, &gpiop->ppd_qspi);
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/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
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writeb(0xFB, &gpiop->pclrr_uart);
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/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
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writeb(0xFE, &gpiop->pclrr_timer);
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writeb(0xDF, &gpiop->pclrr_qspi);
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return FPGA_SUCCESS;
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}
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/* Set the state of CONFIG Pin */
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int altera_config_fn(int assert_config, int flush, int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (assert_config)
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writeb(0x04, &gpiop->ppd_uart);
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else
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writeb(0xFB, &gpiop->pclrr_uart);
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return FPGA_SUCCESS;
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}
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/* Returns the state of STATUS Pin */
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int altera_status_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (readb(&gpiop->ppd_pwm) & 0x08)
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return FPGA_FAIL;
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return FPGA_SUCCESS;
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}
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/* Returns the state of CONF_DONE Pin */
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int altera_done_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (readb(&gpiop->ppd_pwm) & 0x20)
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return FPGA_FAIL;
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return FPGA_SUCCESS;
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}
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/*
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* writes the complete buffer to the FPGA
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* writing the complete buffer in one function is much faster,
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* then calling it for every bit
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*/
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int altera_write_fn(void *buf, size_t len, int flush, int cookie)
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{
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size_t bytecount = 0;
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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unsigned char *data = (unsigned char *)buf;
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unsigned char val = 0;
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int i;
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int len_40 = len / 40;
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while (bytecount < len) {
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val = data[bytecount++];
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i = 8;
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do {
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writeb(0xFB, &gpiop->pclrr_qspi);
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if (val & 0x01)
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writeb(0x01, &gpiop->ppd_qspi);
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else
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writeb(0xFE, &gpiop->pclrr_qspi);
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writeb(0x04, &gpiop->ppd_qspi);
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val >>= 1;
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i--;
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} while (i > 0);
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if (bytecount % len_40 == 0) {
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#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
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WATCHDOG_RESET();
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#endif
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc('.'); /* let them know we are alive */
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#endif
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
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if (ctrlc())
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return FPGA_FAIL;
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#endif
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}
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}
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return FPGA_SUCCESS;
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}
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/* called, when programming is aborted */
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int altera_abort_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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writeb(0x20, &gpiop->ppd_qspi);
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writeb(0x08, &gpiop->ppd_uart);
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return FPGA_SUCCESS;
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}
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/* called, when programming was succesful */
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int altera_post_fn(int cookie)
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{
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return altera_abort_fn(cookie);
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}
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/*
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* Note that these are pointers to code that is in Flash. They will be
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* relocated at runtime.
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* FIXME: relocation not yet working for coldfire, see below!
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*/
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Altera_CYC2_Passive_Serial_fns altera_fns = {
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altera_pre_fn,
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altera_config_fn,
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altera_status_fn,
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altera_done_fn,
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altera_write_fn,
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altera_abort_fn,
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altera_post_fn
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};
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Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
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{Altera_CYC2,
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passive_serial,
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85903,
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(void *)&altera_fns,
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NULL,
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0}
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};
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/* Initialize the fpga. Return 1 on success, 0 on failure. */
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int astro5373l_altera_load(void)
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{
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int i;
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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/*
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* I did not yet manage to get relocation work properly,
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* so set stuff here instead of static initialisation:
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*/
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altera_fns.pre = altera_pre_fn;
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altera_fns.config = altera_config_fn;
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altera_fns.status = altera_status_fn;
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altera_fns.done = altera_done_fn;
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altera_fns.write = altera_write_fn;
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altera_fns.abort = altera_abort_fn;
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altera_fns.post = altera_post_fn;
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altera_fpga[i].iface_fns = (void *)&altera_fns;
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fpga_add(fpga_altera, &altera_fpga[i]);
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}
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return 1;
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}
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/* Set the FPGA's PROG_B line to the specified level */
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int xilinx_pgm_fn(int assert, int flush, int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (assert)
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writeb(0xFB, &gpiop->pclrr_uart);
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else
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writeb(0x04, &gpiop->ppd_uart);
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return assert;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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int xilinx_init_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
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}
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/* Test the state of the active-high FPGA DONE pin */
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int xilinx_done_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
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}
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/* Abort an FPGA operation */
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int xilinx_abort_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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/* ensure all SPI peripherals and FPGAs are deselected */
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writeb(0x08, &gpiop->ppd_uart);
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writeb(0x01, &gpiop->ppd_timer);
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writeb(0x38, &gpiop->ppd_qspi);
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return FPGA_FAIL;
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}
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/*
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* FPGA pre-configuration function. Just make sure that
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* FPGA reset is asserted to keep the FPGA from starting up after
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* configuration.
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*/
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int xilinx_pre_config_fn(int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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unsigned char tmp_char;
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unsigned short tmp_short;
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/* first, set the required pins to GPIO function */
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/* PAR_T0IN -> GPIO */
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tmp_char = readb(&gpiop->par_timer);
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tmp_char &= 0xfc;
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writeb(tmp_char, &gpiop->par_timer);
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/* all QSPI pins -> GPIO */
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writew(0x0000, &gpiop->par_qspi);
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/* U0RTS, U0CTS -> GPIO */
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tmp_short = __raw_readw(&gpiop->par_uart);
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tmp_short &= 0xfff3;
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__raw_writew(tmp_short, &gpiop->par_uart);
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/* all PWM pins -> GPIO */
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writeb(0x00, &gpiop->par_pwm);
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/* next, set data direction registers */
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writeb(0x01, &gpiop->pddr_timer);
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writeb(0x25, &gpiop->pddr_qspi);
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writeb(0x0c, &gpiop->pddr_uart);
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writeb(0x04, &gpiop->pddr_pwm);
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/* ensure other SPI peripherals are deselected */
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writeb(0x08, &gpiop->ppd_uart);
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writeb(0x38, &gpiop->ppd_qspi);
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writeb(0x01, &gpiop->ppd_timer);
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/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
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writeb(0xFB, &gpiop->pclrr_uart);
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/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
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writeb(0xF7, &gpiop->pclrr_uart);
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writeb(0xDF, &gpiop->pclrr_qspi);
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return 0;
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}
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/*
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* FPGA post configuration function. Should perform a test if FPGA is running.
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*/
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int xilinx_post_config_fn(int cookie)
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{
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int rc = 0;
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/*
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* no test yet
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*/
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return rc;
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}
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int xilinx_clk_fn(int assert_clk, int flush, int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (assert_clk)
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writeb(0x04, &gpiop->ppd_qspi);
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else
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writeb(0xFB, &gpiop->pclrr_qspi);
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return assert_clk;
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}
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int xilinx_wr_fn(int assert_write, int flush, int cookie)
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{
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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if (assert_write)
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writeb(0x01, &gpiop->ppd_qspi);
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else
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writeb(0xFE, &gpiop->pclrr_qspi);
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return assert_write;
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}
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int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
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{
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size_t bytecount = 0;
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
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unsigned char *data = (unsigned char *)buf;
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unsigned char val = 0;
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int i;
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int len_40 = len / 40;
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for (bytecount = 0; bytecount < len; bytecount++) {
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val = *(data++);
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for (i = 8; i > 0; i--) {
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writeb(0xFB, &gpiop->pclrr_qspi);
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if (val & 0x80)
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writeb(0x01, &gpiop->ppd_qspi);
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else
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writeb(0xFE, &gpiop->pclrr_qspi);
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writeb(0x04, &gpiop->ppd_qspi);
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val <<= 1;
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}
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if (bytecount % len_40 == 0) {
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#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
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WATCHDOG_RESET();
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#endif
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc('.'); /* let them know we are alive */
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#endif
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
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if (ctrlc())
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return FPGA_FAIL;
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#endif
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}
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}
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return FPGA_SUCCESS;
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}
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/*
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* Note that these are pointers to code that is in Flash. They will be
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* relocated at runtime.
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* FIXME: relocation not yet working for coldfire, see below!
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*/
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Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
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xilinx_pre_config_fn,
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xilinx_pgm_fn,
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xilinx_clk_fn,
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xilinx_init_fn,
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xilinx_done_fn,
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xilinx_wr_fn,
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0,
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xilinx_fastwr_fn
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};
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Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
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{Xilinx_Spartan3,
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slave_serial,
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XILINX_XC3S4000_SIZE,
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(void *)&xilinx_fns,
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0}
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};
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/* Initialize the fpga. Return 1 on success, 0 on failure. */
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int astro5373l_xilinx_load(void)
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{
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int i;
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fpga_init();
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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/*
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* I did not yet manage to get relocation work properly,
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* so set stuff here instead of static initialisation:
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*/
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xilinx_fns.pre = xilinx_pre_config_fn;
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xilinx_fns.pgm = xilinx_pgm_fn;
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xilinx_fns.clk = xilinx_clk_fn;
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xilinx_fns.init = xilinx_init_fn;
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xilinx_fns.done = xilinx_done_fn;
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xilinx_fns.wr = xilinx_wr_fn;
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xilinx_fns.bwr = xilinx_fastwr_fn;
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xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
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fpga_add(fpga_xilinx, &xilinx_fpga[i]);
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}
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return 1;
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}
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