mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,43 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
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COBJS := cm_t35.o leds.o $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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463
common/package/utils/sysupgrade-helper/src/board/cm_t35/cm_t35.c
Normal file
463
common/package/utils/sysupgrade-helper/src/board/cm_t35/cm_t35.c
Normal file
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@ -0,0 +1,463 @@
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/*
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* (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Mike Rapoport <mike@compulab.co.il>
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* Igor Grinberg <grinberg@compulab.co.il>
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*
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* Derived from omap3evm and Beagle Board by
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <status_led.h>
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#include <netdev.h>
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#include <net.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"CM-T3x board",
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"NAND",
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};
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static u32 gpmc_net_config[GPMC_MAX_REG] = {
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NET_GPMC_CONFIG1,
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NET_GPMC_CONFIG2,
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NET_GPMC_CONFIG3,
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NET_GPMC_CONFIG4,
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NET_GPMC_CONFIG5,
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NET_GPMC_CONFIG6,
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0
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};
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static u32 gpmc_nand_config[GPMC_MAX_REG] = {
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SMNAND_GPMC_CONFIG1,
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SMNAND_GPMC_CONFIG2,
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SMNAND_GPMC_CONFIG3,
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SMNAND_GPMC_CONFIG4,
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SMNAND_GPMC_CONFIG5,
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SMNAND_GPMC_CONFIG6,
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0,
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
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CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
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/* board id for Linux */
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if (get_cpu_family() == CPU_OMAP34XX)
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gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
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else
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gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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static u32 cm_t3x_rev;
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/*
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* Routine: get_board_rev
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* Description: read system revision
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*/
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u32 get_board_rev(void)
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{
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if (!cm_t3x_rev)
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cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
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return cm_t3x_rev;
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};
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/*
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* Routine: misc_init_r
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* Description: display die ID
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*/
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int misc_init_r(void)
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{
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u32 board_rev = get_board_rev();
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u32 rev_major = board_rev / 100;
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u32 rev_minor = board_rev - (rev_major * 100);
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if ((rev_minor / 10) * 10 == rev_minor)
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rev_minor = rev_minor / 10;
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printf("PCB: %u.%u\n", rev_major, rev_minor);
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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static void cm_t3x_set_common_muxconf(void)
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{
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/* SDRC */
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
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/* SB-T35 Ethernet */
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
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/* CM-T3x Ethernet */
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
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MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
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MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
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/* DSS */
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
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/* serial interface */
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
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/* mUSB */
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
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/* I2C1 */
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
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MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
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/* I2C2 */
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MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
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MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
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/* I2C3 */
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MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
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MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
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/* control and debug */
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
|
||||
|
||||
/* MMC1 */
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
|
||||
}
|
||||
|
||||
static void cm_t35_set_muxconf(void)
|
||||
{
|
||||
/* DSS */
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
|
||||
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
|
||||
|
||||
/* MMC1 */
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
|
||||
}
|
||||
|
||||
static void cm_t3730_set_muxconf(void)
|
||||
{
|
||||
/* DSS */
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
|
||||
|
||||
MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
|
||||
MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
|
||||
MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
|
||||
MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
|
||||
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
|
||||
}
|
||||
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
cm_t3x_set_common_muxconf();
|
||||
|
||||
if (get_cpu_family() == CPU_OMAP34XX)
|
||||
cm_t35_set_muxconf();
|
||||
else
|
||||
cm_t3730_set_muxconf();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
return omap_mmc_init(0, 0, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: setup_net_chip_gmpc
|
||||
* Description: Setting up the configuration GPMC registers specific to the
|
||||
* Ethernet hardware.
|
||||
*/
|
||||
static void setup_net_chip_gmpc(void)
|
||||
{
|
||||
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
|
||||
|
||||
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
|
||||
CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
|
||||
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
|
||||
SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
|
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
|
||||
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
|
||||
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
|
||||
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
|
||||
&ctrl_base->gpmc_nadv_ale);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
/*
|
||||
* Routine: reset_net_chip
|
||||
* Description: reset the Ethernet controller via TPS65930 GPIO
|
||||
*/
|
||||
static void reset_net_chip(void)
|
||||
{
|
||||
/* Set GPIO1 of TPS65930 as output */
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
|
||||
TWL4030_BASEADD_GPIO + 0x03);
|
||||
/* Send a pulse on the GPIO pin */
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
|
||||
TWL4030_BASEADD_GPIO + 0x0C);
|
||||
udelay(1);
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
|
||||
TWL4030_BASEADD_GPIO + 0x09);
|
||||
mdelay(40);
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
|
||||
TWL4030_BASEADD_GPIO + 0x0C);
|
||||
mdelay(1);
|
||||
}
|
||||
#else
|
||||
static inline void reset_net_chip(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMC911X
|
||||
/*
|
||||
* Routine: handle_mac_address
|
||||
* Description: prepare MAC address for on-board Ethernet.
|
||||
*/
|
||||
static int handle_mac_address(void)
|
||||
{
|
||||
unsigned char enetaddr[6];
|
||||
int rc;
|
||||
|
||||
rc = eth_getenv_enetaddr("ethaddr", enetaddr);
|
||||
if (rc)
|
||||
return 0;
|
||||
|
||||
rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (!is_valid_ether_addr(enetaddr))
|
||||
return -1;
|
||||
|
||||
return eth_setenv_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Routine: board_eth_init
|
||||
* Description: initialize module and base-board Ethernet chips
|
||||
*/
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0, rc1 = 0;
|
||||
|
||||
setup_net_chip_gmpc();
|
||||
reset_net_chip();
|
||||
|
||||
rc1 = handle_mac_address();
|
||||
if (rc1)
|
||||
printf("CM-T3x: No MAC address found\n");
|
||||
|
||||
rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
|
||||
if (rc1 > 0)
|
||||
rc++;
|
||||
|
||||
rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
|
||||
if (rc1 > 0)
|
||||
rc++;
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
||||
void __weak get_board_serial(struct tag_serialnr *serialnr)
|
||||
{
|
||||
/*
|
||||
* This corresponds to what happens when we can communicate with the
|
||||
* eeprom but don't get a valid board serial value.
|
||||
*/
|
||||
serialnr->low = 0;
|
||||
serialnr->high = 0;
|
||||
};
|
||||
130
common/package/utils/sysupgrade-helper/src/board/cm_t35/eeprom.c
Normal file
130
common/package/utils/sysupgrade-helper/src/board/cm_t35/eeprom.c
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
|
||||
*
|
||||
* Authors: Nikita Kiryanov <nikita@compulab.co.il>
|
||||
* Igor Grinberg <grinberg@compulab.co.il>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#define EEPROM_LAYOUT_VER_OFFSET 44
|
||||
#define BOARD_SERIAL_OFFSET 20
|
||||
#define BOARD_SERIAL_OFFSET_LEGACY 8
|
||||
#define BOARD_REV_OFFSET 0
|
||||
#define BOARD_REV_OFFSET_LEGACY 6
|
||||
#define BOARD_REV_SIZE 2
|
||||
#define MAC_ADDR_OFFSET 4
|
||||
#define MAC_ADDR_OFFSET_LEGACY 0
|
||||
|
||||
#define LAYOUT_INVALID 0
|
||||
#define LAYOUT_LEGACY 0xff
|
||||
|
||||
static int eeprom_layout; /* Implicitly LAYOUT_INVALID */
|
||||
|
||||
static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len)
|
||||
{
|
||||
return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
|
||||
}
|
||||
|
||||
static int eeprom_setup_layout(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
if (eeprom_layout != LAYOUT_INVALID)
|
||||
return 0;
|
||||
|
||||
res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
|
||||
(uchar *)&eeprom_layout, 1);
|
||||
if (res) {
|
||||
eeprom_layout = LAYOUT_INVALID;
|
||||
return res;
|
||||
}
|
||||
|
||||
if (eeprom_layout == 0 || eeprom_layout >= 0x20)
|
||||
eeprom_layout = LAYOUT_LEGACY;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void get_board_serial(struct tag_serialnr *serialnr)
|
||||
{
|
||||
u32 serial[2];
|
||||
uint offset;
|
||||
|
||||
memset(serialnr, 0, sizeof(*serialnr));
|
||||
if (eeprom_setup_layout())
|
||||
return;
|
||||
|
||||
offset = (eeprom_layout != LAYOUT_LEGACY) ?
|
||||
BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
|
||||
if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8))
|
||||
return;
|
||||
|
||||
if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
|
||||
serialnr->low = serial[0];
|
||||
serialnr->high = serial[1];
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: cm_t3x_eeprom_read_mac_addr
|
||||
* Description: read mac address and store it in buf.
|
||||
*/
|
||||
int cm_t3x_eeprom_read_mac_addr(uchar *buf)
|
||||
{
|
||||
uint offset;
|
||||
|
||||
if (eeprom_setup_layout())
|
||||
return 0;
|
||||
|
||||
offset = (eeprom_layout != LAYOUT_LEGACY) ?
|
||||
MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
|
||||
return cm_t3x_eeprom_read(offset, buf, 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: cm_t3x_eeprom_get_board_rev
|
||||
* Description: read system revision from eeprom
|
||||
*/
|
||||
u32 cm_t3x_eeprom_get_board_rev(void)
|
||||
{
|
||||
u32 rev = 0;
|
||||
char str[5]; /* Legacy representation can contain at most 4 digits */
|
||||
uint offset = BOARD_REV_OFFSET_LEGACY;
|
||||
|
||||
if (eeprom_setup_layout())
|
||||
return 0;
|
||||
|
||||
if (eeprom_layout != LAYOUT_LEGACY)
|
||||
offset = BOARD_REV_OFFSET;
|
||||
|
||||
if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Convert legacy syntactic representation to semantic
|
||||
* representation. i.e. for rev 1.00: 0x100 --> 0x64
|
||||
*/
|
||||
if (eeprom_layout == LAYOUT_LEGACY) {
|
||||
sprintf(str, "%x", rev);
|
||||
rev = simple_strtoul(str, NULL, 10);
|
||||
}
|
||||
|
||||
return rev;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
|
||||
*
|
||||
* Authors: Nikita Kiryanov <nikita@compulab.co.il>
|
||||
* Igor Grinberg <grinberg@compulab.co.il>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
#ifndef _EEPROM_
|
||||
#define _EEPROM_
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
int cm_t3x_eeprom_read_mac_addr(uchar *buf);
|
||||
u32 cm_t3x_eeprom_get_board_rev(void);
|
||||
#else
|
||||
static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
static inline u32 cm_t3x_eeprom_get_board_rev(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* CompuLab, Ltd. <www.compulab.co.il>
|
||||
*
|
||||
* Author: Igor Grinberg <grinberg@compulab.co.il>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <status_led.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
static unsigned int leds[] = { GREEN_LED_GPIO };
|
||||
|
||||
void __led_init(led_id_t mask, int state)
|
||||
{
|
||||
if (gpio_request(leds[mask], "") != 0) {
|
||||
printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]);
|
||||
return;
|
||||
}
|
||||
|
||||
gpio_direction_output(leds[mask], 0);
|
||||
}
|
||||
|
||||
void __led_set(led_id_t mask, int state)
|
||||
{
|
||||
gpio_set_value(leds[mask], state == STATUS_LED_ON);
|
||||
}
|
||||
|
||||
void __led_toggle(led_id_t mask)
|
||||
{
|
||||
gpio_set_value(leds[mask], !gpio_get_value(leds[mask]));
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue