mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,48 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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||||
#
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||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
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||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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#COBJS = $(BOARD).o flash.o
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#COBJS = $(BOARD).o strataflash.o
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COBJS = $(BOARD).o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $^)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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187
common/package/utils/sysupgrade-helper/src/board/csb272/csb272.c
Normal file
187
common/package/utils/sysupgrade-helper/src/board/csb272/csb272.c
Normal file
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@ -0,0 +1,187 @@
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/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <asm/ppc4xx-emac.h>
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void sdram_init(void);
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/*
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* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
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*
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* CLKA output => Epson LCD Controller
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* CLKB output => Not Connected
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* CLKC output => Ethernet
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* CLKD output => UART external clock
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*
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* Note: these values are obtained from device after init by micromonitor
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*/
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uchar pll_fs6377_regs[16] = {
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0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
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0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
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/*
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* pll_init: Initialize AMIS IC FS6377-01 PLL
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*
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* PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
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*
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*/
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int pll_init(void)
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
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(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
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}
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/*
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* board_early_init_f: do early board initialization
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*
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*/
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int board_early_init_f(void)
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{
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/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
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(void) get_clocks();
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pll_init();
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
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| IRQ 27 (EXT IRQ 2) Not Used
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for Walnut board:
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| An interrupt taken for the FPGA (IRQ 25) indicates that either
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| the Mouse, Keyboard, IRDA, or External Expansion caused the
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| interrupt. The FPGA must be read to determine which device
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| caused the interrupt. The default setting of the FPGA clears
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|
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+-------------------------------------------------------------------------*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
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return 0; /* success */
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}
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/*
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* checkboard: identify/verify the board we are running
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*
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* Remark: we just assume it is correct board here!
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*
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*/
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int checkboard(void)
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{
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printf("BOARD: Cogent CSB272\n");
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return 0; /* success */
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}
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/*
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* initram: Determine the size of mounted DRAM
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*
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* Size is determined by reading SDRAM configuration registers as
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* configured by initialization code
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*
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*/
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phys_size_t initdram (int board_type)
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{
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ulong tot_size;
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ulong bank_size;
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ulong tmp;
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in arch/powerpc/cpu/ppc4xx
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*/
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sdram_init();
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tot_size = 0;
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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return tot_size;
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}
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/*
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* last_stage_init: final configurations (such as PHY etc)
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*
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*/
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int last_stage_init(void)
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{
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/* initialize the PHY */
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miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
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/* AUTO neg */
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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/* LEDs */
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
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return 0; /* success */
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}
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218
common/package/utils/sysupgrade-helper/src/board/csb272/init.S
Normal file
218
common/package/utils/sysupgrade-helper/src/board/csb272/init.S
Normal file
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@ -0,0 +1,218 @@
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/******************************************************************************
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* This source code is dual-licensed. You may use it under the terms of the
|
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* GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
|
||||
* copyrights to use it in any way he or she deems fit, including
|
||||
* copying it, modifying it, compiling it, and redistributing it either
|
||||
* with or without modifications. No license under IBM patents or
|
||||
* patent applications is to be implied by the copyright license.
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||||
*
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||||
* Any user of this software should understand that IBM cannot provide
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||||
* technical support for this software and will not be responsible for
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||||
* any consequences resulting from the use of this software.
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||||
*
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||||
* Any person who transfers this source code or any derivative work
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||||
* must include the IBM copyright notice, this paragraph, and the
|
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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*****************************************************************************/
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#include <config.h>
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#define LI32(reg,val) \
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addis reg,0,val@h;\
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ori reg,reg,val@l
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#define WDCR_EBC(reg,val) \
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addi r4,0,reg;\
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mtdcr EBC0_CFGADDR,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr EBC0_CFGDATA,r4
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#define WDCR_SDRAM(reg,val) \
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addi r4,0,reg;\
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mtdcr SDRAM0_CFGADDR,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr SDRAM0_CFGDATA,r4
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/******************************************************************************
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* Function: ext_bus_cntlr_init
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*
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* Description: Configures EBC Controller and a few basic chip selects.
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*
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* CS0 is setup to get the Boot Flash out of the addresss range
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* so that we may setup a stack. CS7 is setup so that we can
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* access and reset the hardware watchdog.
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*
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* IMPORTANT: For pass1 this code must run from
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* cache since you can not reliably change a peripheral banks
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* timing register (pbxap) while running code from that bank.
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* For ex., since we are running from ROM on bank 0, we can NOT
|
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* execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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*
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* Notes: Does NOT use the stack.
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*****************************************************************************/
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.section ".text"
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.align 2
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.globl ext_bus_cntlr_init
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.type ext_bus_cntlr_init, @function
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ext_bus_cntlr_init:
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mflr r0
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/********************************************************************
|
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* Prefetch entire ext_bus_cntrl_init function into the icache.
|
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* This is necessary because we are going to change the same CS we
|
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* are executing from. Otherwise a CPU lockup may occur.
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*******************************************************************/
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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/* Calculate number of cache lines for this function */
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addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
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mtctr r4
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..ebcloop:
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icbt r0, r3 /* prefetch cache line for addr in r3*/
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
|
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bdnz ..ebcloop /* continue for $CTR cache lines */
|
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|
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/********************************************************************
|
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* Delay to ensure all accesses to ROM are complete before changing
|
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* bank 0 timings. 200usec should be enough.
|
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
|
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*******************************************************************/
|
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addis r3, 0, 0x0
|
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ori r3, r3, 0xA000 /* wait 200us from reset */
|
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mtctr r3
|
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..spinlp:
|
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bdnz ..spinlp /* spin loop */
|
||||
|
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/********************************************************************
|
||||
* SETUP CPC0_CR0
|
||||
*******************************************************************/
|
||||
LI32(r4, 0x007000c0)
|
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mtdcr CPC0_CR0, r4
|
||||
|
||||
/********************************************************************
|
||||
* Setup CPC0_CR1: Change PCIINT signal to PerWE
|
||||
*******************************************************************/
|
||||
mfdcr r4, CPC0_CR1
|
||||
ori r4, r4, 0x4000
|
||||
mtdcr CPC0_CR1, r4
|
||||
|
||||
/********************************************************************
|
||||
* Setup External Bus Controller (EBC).
|
||||
*******************************************************************/
|
||||
WDCR_EBC(EBC0_CFG, 0xd84c0000)
|
||||
/********************************************************************
|
||||
* Memory Bank 0 (Intel 28F128J3 Flash) initialization
|
||||
*******************************************************************/
|
||||
/*WDCR_EBC(PB1AP, 0x02869200)*/
|
||||
WDCR_EBC(PB1AP, 0x07869200)
|
||||
WDCR_EBC(PB0CR, 0xfe0bc000)
|
||||
/********************************************************************
|
||||
* Memory Bank 1 (Holtek HT6542B PS/2) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(PB1AP, 0x1f869200)
|
||||
WDCR_EBC(PB1CR, 0xf0818000)
|
||||
/********************************************************************
|
||||
* Memory Bank 2 (Epson S1D13506) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(PB2AP, 0x05860300)
|
||||
WDCR_EBC(PB2CR, 0xf045a000)
|
||||
/********************************************************************
|
||||
* Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(PB3AP, 0x0387d200)
|
||||
WDCR_EBC(PB3CR, 0xf021c000)
|
||||
/********************************************************************
|
||||
* Memory Bank 4-7 (Unused) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(PB4AP, 0)
|
||||
WDCR_EBC(PB4CR, 0)
|
||||
WDCR_EBC(PB5AP, 0)
|
||||
WDCR_EBC(PB5CR, 0)
|
||||
WDCR_EBC(PB6AP, 0)
|
||||
WDCR_EBC(PB6CR, 0)
|
||||
WDCR_EBC(PB7AP, 0)
|
||||
WDCR_EBC(PB7CR, 0)
|
||||
|
||||
/* We are all done */
|
||||
mtlr r0 /* Restore link register */
|
||||
blr /* Return to calling function */
|
||||
.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
|
||||
/* end ext_bus_cntlr_init() */
|
||||
|
||||
/******************************************************************************
|
||||
* Function: sdram_init
|
||||
*
|
||||
* Description: Configures SDRAM memory banks.
|
||||
*
|
||||
* Notes: Does NOT use the stack.
|
||||
*****************************************************************************/
|
||||
.section ".text"
|
||||
.align 2
|
||||
.globl sdram_init
|
||||
.type sdram_init, @function
|
||||
sdram_init:
|
||||
|
||||
/*
|
||||
* Disable memory controller to allow
|
||||
* values to be changed.
|
||||
*/
|
||||
WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
|
||||
|
||||
/*
|
||||
* Configure Memory Banks
|
||||
*/
|
||||
WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
|
||||
WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
|
||||
WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
|
||||
WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
|
||||
|
||||
/*
|
||||
* Set up SDTR1 (SDRAM Timing Register)
|
||||
*/
|
||||
WDCR_SDRAM(SDRAM0_TR, 0x00854009)
|
||||
|
||||
/*
|
||||
* Set RTR (Refresh Timing Register)
|
||||
*/
|
||||
WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
|
||||
/* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
|
||||
|
||||
/********************************************************************
|
||||
* Delay to ensure 200usec have elapsed since reset. Assume worst
|
||||
* case that the core is running 200Mhz:
|
||||
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
|
||||
*******************************************************************/
|
||||
addis r3, 0, 0x0000
|
||||
ori r3, r3, 0xA000 /* Wait >200us from reset */
|
||||
mtctr r3
|
||||
..spinlp2:
|
||||
bdnz ..spinlp2 /* spin loop */
|
||||
|
||||
/********************************************************************
|
||||
* Set memory controller options reg, MCOPT1.
|
||||
*******************************************************************/
|
||||
WDCR_SDRAM(SDRAM0_CFG,0x80800000)
|
||||
|
||||
..sdri_done:
|
||||
blr /* Return to calling function */
|
||||
.Lfe1: .size sdram_init,.Lfe1-sdram_init
|
||||
/* end sdram_init() */
|
||||
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Add table
Add a link
Reference in a new issue