mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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||||
# This program is free software; you can redistribute it and/or
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||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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||||
#
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||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
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||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y := $(BOARD).o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,195 @@
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/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009 Dave Srl www.dave.eu
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*
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* See file CREDITS for list of people who contributed to this
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||||
* project.
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||||
*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr;
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/*
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* Initialize Local Window for the On Board FPGA access
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*/
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out_be32(&im->sysconf.lpcs2aw,
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CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
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CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
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sync_law(&im->sysconf.lpcs2aw);
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/*
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* Initialize Local Window for the On Board SRAM access
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*/
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out_be32(&im->sysconf.lpcs6aw,
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CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
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CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
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sync_law(&im->sysconf.lpcs6aw);
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/*
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* Configure Flash Speed
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*/
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
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spridr = in_be32(&im->sysconf.spridr);
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if (SVR_MJREV(spridr) >= 2)
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out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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return fixed_sdram(NULL, NULL, 0);
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}
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int misc_init_r(void)
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{
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u32 tmp;
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/* we use I2C-2 for on-board eeprom */
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i2c_set_bus_num(2);
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tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
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printf("FPGA: %u-%u.%u.%u\n",
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(tmp & 0xFF000000) >> 24,
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(tmp & 0x00FF0000) >> 16,
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(tmp & 0x0000FF00) >> 8,
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tmp & 0x000000FF
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);
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/*
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* FEC
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*/
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/* FEC on PSCx_x*/
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* DIU
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*/
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/* FUNC2=DIU CLK */
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{
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offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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{
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offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{
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offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* On board SRAM
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*/
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/* FUNC2=/LPC CS6 */
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{
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offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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};
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int checkboard (void)
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{
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puts("Board: ARIA\n");
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2009
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# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := qong.o fpga.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,94 @@
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de
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*
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
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||||
*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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||||
*
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/gpio.h>
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#include <fpga.h>
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#include <lattice.h>
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#include "qong_fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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static void qong_jtag_init(void)
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{
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return;
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}
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static void qong_fpga_jtag_set_tdi(int value)
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{
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gpio_set_value(QONG_FPGA_TDI_PIN, value);
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}
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static void qong_fpga_jtag_set_tms(int value)
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{
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gpio_set_value(QONG_FPGA_TMS_PIN, value);
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}
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static void qong_fpga_jtag_set_tck(int value)
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{
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gpio_set_value(QONG_FPGA_TCK_PIN, value);
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}
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|
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static int qong_fpga_jtag_get_tdo(void)
|
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{
|
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return gpio_get_value(QONG_FPGA_TDO_PIN);
|
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}
|
||||
|
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lattice_board_specific_func qong_fpga_fns = {
|
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qong_jtag_init,
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qong_fpga_jtag_set_tdi,
|
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qong_fpga_jtag_set_tms,
|
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qong_fpga_jtag_set_tck,
|
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qong_fpga_jtag_get_tdo
|
||||
};
|
||||
|
||||
Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
|
||||
{
|
||||
Lattice_XP2,
|
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lattice_jtag_mode,
|
||||
356519,
|
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(void *) &qong_fpga_fns,
|
||||
NULL,
|
||||
0,
|
||||
"lfxp2_5e_ftbga256"
|
||||
},
|
||||
};
|
||||
|
||||
int qong_fpga_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
fpga_init();
|
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
|
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fpga_add(fpga_lattice, &qong_fpga[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
|
||||
*
|
||||
* Based on board/freescale/mx31ads/lowlevel_init.S
|
||||
* by Guennadi Liakhovetski.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
.macro REG reg, val
|
||||
ldr r2, =\reg
|
||||
ldr r3, =\val
|
||||
str r3, [r2]
|
||||
.endm
|
||||
|
||||
.macro REG8 reg, val
|
||||
ldr r2, =\reg
|
||||
ldr r3, =\val
|
||||
strb r3, [r2]
|
||||
.endm
|
||||
|
||||
.macro DELAY loops
|
||||
ldr r2, =\loops
|
||||
1:
|
||||
subs r2, r2, #1
|
||||
nop
|
||||
bcs 1b
|
||||
.endm
|
||||
|
||||
.macro SETUP_RAM cfg, ctl
|
||||
/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
|
||||
REG 0xB8001010, 0x00000004
|
||||
ldr r3, =\cfg
|
||||
ldr r2, =WEIM_ESDCFG0
|
||||
str r3, [r2]
|
||||
REG 0xB8001000, 0x92100000
|
||||
REG 0x80000f00, 0x12344321
|
||||
REG 0xB8001000, 0xa2100000
|
||||
REG 0x80000000, 0x12344321
|
||||
REG 0x80000000, 0x12344321
|
||||
REG 0xB8001000, 0xb2100000
|
||||
REG8 0x80000033, 0xda
|
||||
REG8 0x81000000, 0xff
|
||||
ldr r3, =\ctl
|
||||
ldr r2, =WEIM_ESDCTL0
|
||||
str r3, [r2]
|
||||
REG 0x80000000, 0xDEADBEEF
|
||||
REG 0xB8001010, 0x0000000c
|
||||
|
||||
.endm
|
||||
/* RedBoot: To support 133MHz DDR */
|
||||
.macro init_drive_strength
|
||||
/*
|
||||
* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
|
||||
* in SW_PAD_CTL registers
|
||||
*/
|
||||
|
||||
/* SDCLK */
|
||||
ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
|
||||
ldr r0, [r1, #0x6C]
|
||||
bic r0, r0, #(1 << 12)
|
||||
str r0, [r1, #0x6C]
|
||||
|
||||
/* CAS */
|
||||
ldr r0, [r1, #0x70]
|
||||
bic r0, r0, #(1 << 22)
|
||||
str r0, [r1, #0x70]
|
||||
|
||||
/* RAS */
|
||||
ldr r0, [r1, #0x74]
|
||||
bic r0, r0, #(1 << 2)
|
||||
str r0, [r1, #0x74]
|
||||
|
||||
/* CS2 (CSD0) */
|
||||
ldr r0, [r1, #0x7C]
|
||||
bic r0, r0, #(1 << 22)
|
||||
str r0, [r1, #0x7C]
|
||||
|
||||
/* DQM3 */
|
||||
ldr r0, [r1, #0x84]
|
||||
bic r0, r0, #(1 << 22)
|
||||
str r0, [r1, #0x84]
|
||||
|
||||
/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
|
||||
ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
|
||||
pad_loop:
|
||||
ldr r0, [r1, #0x88]
|
||||
bic r0, r0, #(1 << 22)
|
||||
bic r0, r0, #(1 << 12)
|
||||
bic r0, r0, #(1 << 2)
|
||||
str r0, [r1, #0x88]
|
||||
add r1, r1, #4
|
||||
subs r2, r2, #0x1
|
||||
bne pad_loop
|
||||
.endm /* init_drive_strength */
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
init_drive_strength
|
||||
|
||||
/* Image Processing Unit: */
|
||||
/* Too early to switch display on? */
|
||||
/* Switch on Display Interface */
|
||||
REG IPU_CONF, IPU_CONF_DI_EN
|
||||
/* Clock Control Module: */
|
||||
REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
|
||||
|
||||
DELAY 0x40000
|
||||
|
||||
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
|
||||
/* Switch to MCU PLL */
|
||||
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
|
||||
|
||||
/* 399-133-66.5 */
|
||||
ldr r0, =CCM_BASE
|
||||
ldr r1, =0xFF871650
|
||||
/* PDR0 */
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, MPCTL_PARAM_399
|
||||
/* MPCTL */
|
||||
str r1, [r0, #0x10]
|
||||
|
||||
/* Set UPLL=240MHz, USB=60MHz */
|
||||
ldr r1, =0x49FCFE7F
|
||||
/* PDR1 */
|
||||
str r1, [r0, #0x8]
|
||||
ldr r1, UPCTL_PARAM_240
|
||||
/* UPCTL */
|
||||
str r1, [r0, #0x14]
|
||||
/* default CLKO to 1/8 of the ARM core */
|
||||
mov r1, #0x00000208
|
||||
/* COSR */
|
||||
str r1, [r0, #0x1c]
|
||||
|
||||
/* Default: 1, 4, 12, 1 */
|
||||
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
|
||||
|
||||
check_ddr_module:
|
||||
/* Set stackpointer in internal RAM to call get_ram_size */
|
||||
ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
|
||||
stmfd sp!, {r0-r11, ip, lr}
|
||||
mov ip, lr /* save link reg across call */
|
||||
|
||||
ldr r0,=0x08000000
|
||||
SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
|
||||
ldr r0,=0x80000000
|
||||
ldr r1,=0x10000000
|
||||
bl get_ram_size
|
||||
ldr r1,=0x10000000
|
||||
cmp r0,r1
|
||||
beq restore_regs
|
||||
SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
|
||||
ldr r0,=0x80000000
|
||||
ldr r1,=0x08000000
|
||||
bl get_ram_size
|
||||
ldr r1,=0x08000000
|
||||
cmp r0,r1
|
||||
beq restore_regs
|
||||
|
||||
restore_regs:
|
||||
ldmfd sp!, {r0-r11, ip, lr}
|
||||
mov lr, ip /* restore link reg */
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
||||
MPCTL_PARAM_399:
|
||||
.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
|
||||
UPCTL_PARAM_240:
|
||||
.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
|
||||
|
||||
.equ ESDCFG0_128MB, \
|
||||
(0 << 21) + /* tXP */ \
|
||||
(1 << 20) + /* tWTR */ \
|
||||
(2 << 18) + /* tRP */ \
|
||||
(1 << 16) + /* tMRD */ \
|
||||
(0 << 15) + /* tWR */ \
|
||||
(5 << 12) + /* tRAS */ \
|
||||
(1 << 10) + /* tRRD */ \
|
||||
(3 << 8) + /* tCAS */ \
|
||||
(2 << 4) + /* tRCD */ \
|
||||
(0x0F << 0) /* tRC */
|
||||
|
||||
.equ ESDCTL0_128MB, \
|
||||
(1 << 31) + /* enable */ \
|
||||
(0 << 28) + /* mode */ \
|
||||
(0 << 27) + /* supervisor protect */ \
|
||||
(2 << 24) + /* 13 rows */ \
|
||||
(2 << 20) + /* 10 cols */ \
|
||||
(2 << 16) + /* 32 bit */ \
|
||||
(3 << 13) + /* 7.81us (64ms/8192) */ \
|
||||
(0 << 10) + /* power down timer */ \
|
||||
(0 << 8) + /* full page */ \
|
||||
(1 << 7) + /* burst length */ \
|
||||
(0 << 0) /* precharge timer */
|
||||
|
||||
.equ ESDCFG0_256MB, \
|
||||
(3 << 21) + /* tXP */ \
|
||||
(0 << 20) + /* tWTR */ \
|
||||
(2 << 18) + /* tRP */ \
|
||||
(1 << 16) + /* tMRD */ \
|
||||
(0 << 15) + /* tWR */ \
|
||||
(5 << 12) + /* tRAS */ \
|
||||
(1 << 10) + /* tRRD */ \
|
||||
(3 << 8) + /* tCAS */ \
|
||||
(2 << 4) + /* tRCD */ \
|
||||
(7 << 0) /* tRC */
|
||||
|
||||
.equ ESDCTL0_256MB, \
|
||||
(1 << 31) + \
|
||||
(0 << 28) + \
|
||||
(0 << 27) + \
|
||||
(3 << 24) + /* 14 rows */ \
|
||||
(2 << 20) + /* 10 cols */ \
|
||||
(2 << 16) + \
|
||||
(4 << 13) + /* 3.91us (64ms/16384) */ \
|
||||
(0 << 10) + \
|
||||
(0 << 8) + \
|
||||
(1 << 7) + \
|
||||
(0 << 0)
|
||||
|
|
@ -0,0 +1,276 @@
|
|||
/*
|
||||
*
|
||||
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <asm/gpio.h>
|
||||
#include "qong_fpga.h"
|
||||
#include <watchdog.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
mxc_hw_watchdog_reset();
|
||||
}
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void qong_fpga_reset(void)
|
||||
{
|
||||
gpio_set_value(QONG_FPGA_RST_PIN, 0);
|
||||
udelay(30);
|
||||
gpio_set_value(QONG_FPGA_RST_PIN, 1);
|
||||
|
||||
udelay(300);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_QONG_FPGA
|
||||
/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
|
||||
static const struct mxc_weimcs cs1 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(1, &cs1);
|
||||
|
||||
/* setup pins for FPGA */
|
||||
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
|
||||
|
||||
/* FPGA reset Pin */
|
||||
/* rstn = 0 */
|
||||
gpio_direction_output(QONG_FPGA_RST_PIN, 0);
|
||||
|
||||
/* set interrupt pin as input */
|
||||
gpio_direction_input(QONG_FPGA_IRQ_PIN);
|
||||
|
||||
/* FPGA JTAG Interface */
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
|
||||
gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
|
||||
gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
|
||||
gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
|
||||
gpio_direction_input(QONG_FPGA_TDO_PIN);
|
||||
#endif
|
||||
|
||||
/* setup pins for UART1 */
|
||||
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
|
||||
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
|
||||
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
|
||||
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
|
||||
|
||||
/* setup pins for SPI (pmic) */
|
||||
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
|
||||
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
|
||||
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
|
||||
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
|
||||
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
|
||||
|
||||
/* Setup pins for USB2 Host */
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
|
||||
|
||||
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
|
||||
|
||||
mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
|
||||
mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
|
||||
mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
|
||||
mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
|
||||
mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
|
||||
mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
|
||||
mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
|
||||
mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
|
||||
mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
|
||||
mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
|
||||
mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
|
||||
mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
|
||||
|
||||
mx31_set_gpr(MUX_PGP_UH2, 1);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Chip selects */
|
||||
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
|
||||
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
|
||||
static const struct mxc_weimcs cs0 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(0, &cs0);
|
||||
|
||||
/* board id for linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_QONG;
|
||||
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
|
||||
|
||||
qong_fpga_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
u32 val;
|
||||
struct pmic *p;
|
||||
|
||||
pmic_init();
|
||||
p = get_pmic();
|
||||
|
||||
/* Enable RTC battery */
|
||||
pmic_reg_read(p, REG_POWER_CTL0, &val);
|
||||
pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
|
||||
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
|
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
mxc_hw_watchdog_enable();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: DAVE/DENX Qong\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_QONG_FPGA
|
||||
u32 tmp;
|
||||
|
||||
tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
|
||||
printf("FPGA: ");
|
||||
printf("version register = %u.%u.%u\n",
|
||||
(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
|
||||
return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
|
||||
static void board_nand_setup(void)
|
||||
{
|
||||
/* CS3: NAND 8-bit */
|
||||
static const struct mxc_weimcs cs3 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(3, &cs3);
|
||||
|
||||
mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
|
||||
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
|
||||
|
||||
/* Make sure to reset the fpga else you cannot access NAND */
|
||||
qong_fpga_reset();
|
||||
|
||||
/* Enable NAND flash */
|
||||
gpio_set_value(15, 1);
|
||||
gpio_set_value(14, 1);
|
||||
gpio_direction_output(15, 0);
|
||||
gpio_direction_input(16);
|
||||
gpio_direction_input(14);
|
||||
|
||||
}
|
||||
|
||||
int qong_nand_rdy(void *chip)
|
||||
{
|
||||
udelay(1);
|
||||
return gpio_get_value(16);
|
||||
}
|
||||
|
||||
void qong_nand_select_chip(struct mtd_info *mtd, int chip)
|
||||
{
|
||||
if (chip >= 0)
|
||||
gpio_set_value(15, 0);
|
||||
else
|
||||
gpio_set_value(15, 1);
|
||||
|
||||
}
|
||||
|
||||
void qong_nand_plat_init(void *chip)
|
||||
{
|
||||
struct nand_chip *nand = (struct nand_chip *)chip;
|
||||
nand->chip_delay = 20;
|
||||
nand->select_chip = qong_nand_select_chip;
|
||||
nand->options &= ~NAND_BUSWIDTH_16;
|
||||
board_nand_setup();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
*
|
||||
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef QONG_FPGA_H
|
||||
#define QONG_FPGA_H
|
||||
|
||||
#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
|
||||
#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
|
||||
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
|
||||
|
||||
#define QONG_FPGA_TCK_PIN 26
|
||||
#define QONG_FPGA_TMS_PIN 25
|
||||
#define QONG_FPGA_TDI_PIN 8
|
||||
#define QONG_FPGA_TDO_PIN 7
|
||||
#define QONG_FPGA_RST_PIN 48
|
||||
#define QONG_FPGA_IRQ_PIN 40
|
||||
|
||||
int qong_fpga_init(void);
|
||||
#endif /* QONG_FPGA_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue