mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o phantom.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,190 @@
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/*
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* (C) Copyright 2000
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* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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||||
*
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* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
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||||
* the License, or (at your option) any later version.
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||||
*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <net.h>
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#include <pci.h>
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#include <i2c.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard (void)
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{
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/*TODO: Check processor type */
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puts ( "Board: Debris "
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#ifdef CONFIG_MPC8240
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"8240"
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#endif
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#ifdef CONFIG_MPC8245
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"8245"
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#endif
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" ##Test not implemented yet##\n");
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return 0;
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}
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#if 0 /* NOT USED */
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int checkflash (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("## Test not implemented yet ##\n");
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return (0);
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}
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#endif
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phys_size_t initdram (int board_type)
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{
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int m, row, col, bank, i;
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unsigned long start, end;
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uint32_t mccr1;
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uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
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uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
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uint8_t mber = 0;
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
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m = i2c_reg_read (0x50, 5); /* # of physical banks */
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row = i2c_reg_read (0x50, 3); /* # of rows */
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col = i2c_reg_read (0x50, 4); /* # of columns */
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bank = i2c_reg_read (0x50, 17); /* # of logical banks */
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CONFIG_READ_WORD(MCCR1, mccr1);
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mccr1 &= 0xffff0000;
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start = CONFIG_SYS_SDRAM_BASE;
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end = start + (1 << (col + row + 3) ) * bank - 1;
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for (i = 0; i < m; i++) {
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mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
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if (i < 4) {
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msar1 |= ((start >> 20) & 0xff) << i * 8;
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emsar1 |= ((start >> 28) & 0xff) << i * 8;
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mear1 |= ((end >> 20) & 0xff) << i * 8;
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emear1 |= ((end >> 28) & 0xff) << i * 8;
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} else {
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msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
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emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
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mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
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emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
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}
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mber |= 1 << i;
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start += (1 << (col + row + 3) ) * bank;
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end += (1 << (col + row + 3) ) * bank;
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}
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for (; i < 8; i++) {
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if (i < 4) {
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msar1 |= 0xff << i * 8;
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emsar1 |= 0x30 << i * 8;
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mear1 |= 0xff << i * 8;
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emear1 |= 0x30 << i * 8;
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} else {
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msar2 |= 0xff << (i-4) * 8;
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emsar2 |= 0x30 << (i-4) * 8;
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mear2 |= 0xff << (i-4) * 8;
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emear2 |= 0x30 << (i-4) * 8;
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}
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}
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CONFIG_WRITE_WORD(MCCR1, mccr1);
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CONFIG_WRITE_WORD(MSAR1, msar1);
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CONFIG_WRITE_WORD(EMSAR1, emsar1);
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CONFIG_WRITE_WORD(MEAR1, mear1);
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CONFIG_WRITE_WORD(EMEAR1, emear1);
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CONFIG_WRITE_WORD(MSAR2, msar2);
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CONFIG_WRITE_WORD(EMSAR2, emsar2);
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CONFIG_WRITE_WORD(MEAR2, mear2);
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CONFIG_WRITE_WORD(EMEAR2, emear2);
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CONFIG_WRITE_BYTE(MBER, mber);
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return (1 << (col + row + 3) ) * bank * m;
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_debris_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_debris_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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void *nvram_read(void *dest, const long src, size_t count)
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{
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volatile uchar *d = (volatile uchar*) dest;
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volatile uchar *s = (volatile uchar*) src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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return dest;
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}
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void nvram_write(long dest, const void *src, size_t count)
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{
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volatile uchar *d = (volatile uchar*)dest;
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volatile uchar *s = (volatile uchar*)src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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}
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int misc_init_r(void)
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{
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uchar ethaddr[6];
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if (eth_getenv_enetaddr("ethaddr", ethaddr))
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/* Write ethernet addr in NVRAM for VxWorks */
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nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
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ethaddr, 6);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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@ -0,0 +1,721 @@
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/*
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* board/eva/flash.c
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*
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* (C) Copyright 2002
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* Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/pci_io.h>
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#include <mpc824x.h>
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#include <asm/mmu.h>
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int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
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int (*write_dword)(flash_info_t*, ulong, uint64_t);
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typedef uint64_t cfi_word;
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#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
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#define cfi_write(flash, val, addr) \
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move64((cfi_word*)&val, \
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(cfi_word*)(flash->start[0] + addr))
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#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
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static void write32(unsigned long addr, uint32_t value)
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{
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*(volatile uint32_t*)(addr) = value;
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asm volatile("sync");
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}
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static uint32_t read32(unsigned long addr)
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{
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uint32_t value;
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value = *(volatile uint32_t*)addr;
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asm volatile("sync");
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return value;
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}
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static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
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{
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uint32_t base = flash->start[0];
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uint32_t val=(cmd << 16) | cmd;
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addr <<= 3;
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write32(base + addr, val);
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return addr;
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}
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static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
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{
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uint32_t base = flash->start[0];
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addr <<= 3;
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return (uint16_t)read32(base + addr);
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}
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static void move64(uint64_t *src, uint64_t *dest)
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{
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asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
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"stfd 0, 0(4)" /* *dest = fpr0 */
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: : : "fr0" ); /* Clobbers fr0 */
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return;
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}
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||||
|
||||
static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
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{
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unsigned long start;
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cfi_word status = 0;
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status = cfi_read(flash, dest);
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data &= status;
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cfi_cmd(flash, 0x40, 0);
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cfi_write(flash, data, dest);
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udelay(10);
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start = get_timer (0);
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for(;;) {
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status = cfi_read(flash, dest);
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status &= CMD(0x80);
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if(status == CMD(0x80))
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break;
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
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cfi_cmd(flash, 0xff, 0);
|
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return 1;
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
|
||||
{
|
||||
ulong start;
|
||||
cfi_word status = 0;
|
||||
|
||||
status = cfi_read(flash, dest);
|
||||
if(status != CMD(0xffff)) return 2;
|
||||
|
||||
cfi_cmd(flash, 0xaa, 0x555);
|
||||
cfi_cmd(flash, 0x55, 0x2aa);
|
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cfi_cmd(flash, 0xa0, 0x555);
|
||||
|
||||
cfi_write(flash, data, dest);
|
||||
|
||||
udelay(10);
|
||||
start = get_timer (0);
|
||||
status = ~data;
|
||||
while(status != data) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
|
||||
return 1;
|
||||
status = cfi_read(flash, dest);
|
||||
udelay(1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ unsigned long get_msr(void)
|
||||
{
|
||||
unsigned long msr;
|
||||
__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
|
||||
return msr;
|
||||
}
|
||||
|
||||
static __inline__ void set_msr(unsigned long msr)
|
||||
{
|
||||
__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
|
||||
}
|
||||
|
||||
int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp;
|
||||
int i, s, l, rc;
|
||||
cfi_word data;
|
||||
uint8_t *t = (uint8_t*)&data;
|
||||
unsigned long base = flash->start[0];
|
||||
uint32_t msr;
|
||||
|
||||
if (flash->flash_id == FLASH_UNKNOWN)
|
||||
return 4;
|
||||
|
||||
if (cnt == 0)
|
||||
return 0;
|
||||
|
||||
addr -= base;
|
||||
|
||||
msr = get_msr();
|
||||
set_msr(msr|MSR_FP);
|
||||
|
||||
wp = (addr & ~7); /* get lower word aligned address */
|
||||
|
||||
if((addr-wp) != 0) {
|
||||
data = cfi_read(flash, wp);
|
||||
s = addr & 7;
|
||||
l = ( cnt < (8-s) ) ? cnt : (8-s);
|
||||
for(i = 0; i < l; i++)
|
||||
t[s+i] = *src++;
|
||||
if ((rc = write_dword(flash, wp, data)) != 0)
|
||||
goto DONE;
|
||||
wp += 8;
|
||||
cnt -= l;
|
||||
}
|
||||
|
||||
while (cnt >= 8) {
|
||||
for (i = 0; i < 8; i++)
|
||||
t[i] = *src++;
|
||||
if ((rc = write_dword(flash, wp, data)) != 0)
|
||||
goto DONE;
|
||||
wp += 8;
|
||||
cnt -= 8;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
rc = 0;
|
||||
goto DONE;
|
||||
}
|
||||
|
||||
data = cfi_read(flash, wp);
|
||||
for(i = 0; i < cnt; i++)
|
||||
t[i] = *src++;
|
||||
rc = write_dword(flash, wp, data);
|
||||
DONE:
|
||||
set_msr(msr);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
|
||||
{
|
||||
int sa;
|
||||
int flag;
|
||||
ulong start, last, now;
|
||||
cfi_word status;
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
sa = (flash->start[sect] - flash->start[0]);
|
||||
write32(flash->start[sect], 0x00200020);
|
||||
write32(flash->start[sect], 0x00d000d0);
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
udelay(1000);
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
|
||||
for (;;) {
|
||||
status = cfi_read(flash, sa);
|
||||
status &= CMD(0x80);
|
||||
if (status == CMD(0x80))
|
||||
break;
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
printf ("Timeout\n");
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
|
||||
if ((now - last) > 1000) {
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
|
||||
{
|
||||
int sect;
|
||||
int rc = ERR_OK;
|
||||
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (flash->protect[sect] == 0) {
|
||||
rc = cfi_erase_oneblock(flash, sect);
|
||||
if (rc != ERR_OK) break;
|
||||
}
|
||||
}
|
||||
printf (" done\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
|
||||
{
|
||||
int sect;
|
||||
cfi_word status;
|
||||
int sa = -1;
|
||||
int flag;
|
||||
ulong start, last, now;
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
cfi_cmd(flash, 0xaa, 0x555);
|
||||
cfi_cmd(flash, 0x55, 0x2aa);
|
||||
cfi_cmd(flash, 0x80, 0x555);
|
||||
cfi_cmd(flash, 0xaa, 0x555);
|
||||
cfi_cmd(flash, 0x55, 0x2aa);
|
||||
for ( sect = s_first; sect <= s_last; sect++) {
|
||||
if (flash->protect[sect] == 0) {
|
||||
sa = flash->start[sect] - flash->start[0];
|
||||
write32(flash->start[sect], 0x00300030);
|
||||
}
|
||||
}
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
if (sa < 0)
|
||||
goto DONE;
|
||||
|
||||
udelay (1000);
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
for(;;) {
|
||||
status = cfi_read(flash, sa);
|
||||
if (status == CMD(0xffff))
|
||||
break;
|
||||
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
|
||||
if ((now - last) > 1000) {
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
DONE:
|
||||
cfi_cmd(flash, 0xf0, 0);
|
||||
|
||||
printf (" done\n");
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
int flash_erase (flash_info_t *flash, int s_first, int s_last)
|
||||
{
|
||||
int sect;
|
||||
int prot;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (flash->flash_id == FLASH_UNKNOWN)
|
||||
printf ("- missing\n");
|
||||
else
|
||||
printf ("- no sectors to erase\n");
|
||||
return ERR_NOT_ERASED;
|
||||
}
|
||||
if (flash->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return ERR_NOT_ERASED;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; sect++)
|
||||
if (flash->protect[sect]) prot++;
|
||||
|
||||
if (prot)
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
else
|
||||
printf ("\n");
|
||||
|
||||
return do_flash_erase(flash, s_first, s_last);
|
||||
}
|
||||
|
||||
struct jedec_flash_info {
|
||||
const uint16_t mfr_id;
|
||||
const uint16_t dev_id;
|
||||
const char *name;
|
||||
const int DevSize;
|
||||
const int InterfaceDesc;
|
||||
const int NumEraseRegions;
|
||||
const ulong regions[4];
|
||||
};
|
||||
|
||||
#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
|
||||
|
||||
#define SIZE_1MiB 20
|
||||
#define SIZE_2MiB 21
|
||||
#define SIZE_4MiB 22
|
||||
|
||||
static const struct jedec_flash_info jedec_table[] = {
|
||||
{
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV800T,
|
||||
name: "AMD AM29LV800T",
|
||||
DevSize: SIZE_1MiB,
|
||||
NumEraseRegions: 4,
|
||||
regions: {ERASEINFO(0x10000,15),
|
||||
ERASEINFO(0x08000,1),
|
||||
ERASEINFO(0x02000,2),
|
||||
ERASEINFO(0x04000,1)
|
||||
}
|
||||
}, {
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV800B,
|
||||
name: "AMD AM29LV800B",
|
||||
DevSize: SIZE_1MiB,
|
||||
NumEraseRegions: 4,
|
||||
regions: {ERASEINFO(0x10000,15),
|
||||
ERASEINFO(0x08000,1),
|
||||
ERASEINFO(0x02000,2),
|
||||
ERASEINFO(0x04000,1)
|
||||
}
|
||||
}, {
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV160T,
|
||||
name: "AMD AM29LV160T",
|
||||
DevSize: SIZE_2MiB,
|
||||
NumEraseRegions: 4,
|
||||
regions: {ERASEINFO(0x10000,31),
|
||||
ERASEINFO(0x08000,1),
|
||||
ERASEINFO(0x02000,2),
|
||||
ERASEINFO(0x04000,1)
|
||||
}
|
||||
}, {
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV160B,
|
||||
name: "AMD AM29LV160B",
|
||||
DevSize: SIZE_2MiB,
|
||||
NumEraseRegions: 4,
|
||||
regions: {ERASEINFO(0x04000,1),
|
||||
ERASEINFO(0x02000,2),
|
||||
ERASEINFO(0x08000,1),
|
||||
ERASEINFO(0x10000,31)
|
||||
}
|
||||
}, {
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV320T,
|
||||
name: "AMD AM29LV320T",
|
||||
DevSize: SIZE_4MiB,
|
||||
NumEraseRegions: 2,
|
||||
regions: {ERASEINFO(0x10000,63),
|
||||
ERASEINFO(0x02000,8)
|
||||
}
|
||||
|
||||
}, {
|
||||
mfr_id: (uint16_t)AMD_MANUFACT,
|
||||
dev_id: (uint16_t)AMD_ID_LV320B,
|
||||
name: "AMD AM29LV320B",
|
||||
DevSize: SIZE_4MiB,
|
||||
NumEraseRegions: 2,
|
||||
regions: {ERASEINFO(0x02000,8),
|
||||
ERASEINFO(0x10000,63)
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static ulong cfi_init(uint32_t base, flash_info_t *flash)
|
||||
{
|
||||
int sector;
|
||||
int block;
|
||||
int block_count;
|
||||
int offset = 0;
|
||||
int reverse = 0;
|
||||
int primary;
|
||||
int mfr_id;
|
||||
int dev_id;
|
||||
|
||||
flash->start[0] = base;
|
||||
cfi_cmd(flash, 0xF0, 0);
|
||||
cfi_cmd(flash, 0x98, 0);
|
||||
if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
|
||||
cfi_read_query(flash, 0x11) == 'R' &&
|
||||
cfi_read_query(flash, 0x12) == 'Y' )) {
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
flash->size = 1 << cfi_read_query(flash, 0x27);
|
||||
flash->size *= 4;
|
||||
block_count = cfi_read_query(flash, 0x2c);
|
||||
primary = cfi_read_query(flash, 0x15);
|
||||
if ( cfi_read_query(flash, primary + 4) == 0x30)
|
||||
reverse = (cfi_read_query(flash, 0x1) & 0x01);
|
||||
else
|
||||
reverse = (cfi_read_query(flash, primary+15) == 3);
|
||||
|
||||
flash->sector_count = 0;
|
||||
|
||||
for ( block = reverse ? block_count - 1 : 0;
|
||||
reverse ? block >= 0 : block < block_count;
|
||||
reverse ? block-- : block ++) {
|
||||
int sector_size =
|
||||
(cfi_read_query(flash, 0x2d + block*4+2) |
|
||||
(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
|
||||
int sector_count =
|
||||
(cfi_read_query(flash, 0x2d + block*4+0) |
|
||||
(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
|
||||
for(sector = 0; sector < sector_count; sector++) {
|
||||
flash->start[flash->sector_count++] = base + offset;
|
||||
offset += sector_size * 4;
|
||||
}
|
||||
}
|
||||
mfr_id = cfi_read_query(flash, 0x00);
|
||||
dev_id = cfi_read_query(flash, 0x01);
|
||||
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
|
||||
flash->flash_id = (mfr_id << 16) | dev_id;
|
||||
|
||||
for (sector = 0; sector < flash->sector_count; sector++) {
|
||||
write32(flash->start[sector], 0x00600060);
|
||||
write32(flash->start[sector], 0x00d000d0);
|
||||
}
|
||||
cfi_cmd(flash, 0xff, 0);
|
||||
|
||||
for (sector = 0; sector < flash->sector_count; sector++)
|
||||
flash->protect[sector] = 0;
|
||||
|
||||
do_flash_erase = cfi_erase;
|
||||
write_dword = cfi_write_dword;
|
||||
|
||||
return flash->size;
|
||||
}
|
||||
|
||||
static ulong jedec_init(unsigned long base, flash_info_t *flash)
|
||||
{
|
||||
int i;
|
||||
int block, block_count;
|
||||
int sector, offset;
|
||||
int mfr_id, dev_id;
|
||||
flash->start[0] = base;
|
||||
cfi_cmd(flash, 0xF0, 0x000);
|
||||
cfi_cmd(flash, 0xAA, 0x555);
|
||||
cfi_cmd(flash, 0x55, 0x2AA);
|
||||
cfi_cmd(flash, 0x90, 0x555);
|
||||
mfr_id = cfi_read_query(flash, 0x000);
|
||||
dev_id = cfi_read_query(flash, 0x0001);
|
||||
cfi_cmd(flash, 0xf0, 0x000);
|
||||
|
||||
for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
|
||||
if((jedec_table[i].mfr_id == mfr_id) &&
|
||||
(jedec_table[i].dev_id == dev_id)) {
|
||||
|
||||
flash->flash_id = (mfr_id << 16) | dev_id;
|
||||
flash->size = 1 << jedec_table[0].DevSize;
|
||||
flash->size *= 4;
|
||||
block_count = jedec_table[i].NumEraseRegions;
|
||||
offset = 0;
|
||||
flash->sector_count = 0;
|
||||
for (block = 0; block < block_count; block++) {
|
||||
int sector_size = jedec_table[i].regions[block];
|
||||
int sector_count = (sector_size & 0xff) + 1;
|
||||
sector_size >>= 8;
|
||||
for (sector=0; sector<sector_count; sector++) {
|
||||
flash->start[flash->sector_count++] =
|
||||
base + offset;
|
||||
offset += sector_size * 4;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (sector = 0; sector < flash->sector_count; sector++)
|
||||
flash->protect[sector] = 0;
|
||||
|
||||
do_flash_erase = jedec_erase;
|
||||
write_dword = jedec_write_dword;
|
||||
|
||||
return flash->size;
|
||||
}
|
||||
|
||||
inline void mtibat1u(unsigned int x)
|
||||
{
|
||||
__asm__ __volatile__ ("mtspr 530, %0" :: "r" (x));
|
||||
}
|
||||
|
||||
inline void mtibat1l(unsigned int x)
|
||||
{
|
||||
__asm__ __volatile__ ("mtspr 531, %0" :: "r" (x));
|
||||
}
|
||||
|
||||
inline void mtdbat1u(unsigned int x)
|
||||
{
|
||||
__asm__ __volatile__ ("mtspr 538, %0" :: "r" (x));
|
||||
}
|
||||
|
||||
inline void mtdbat1l(unsigned int x)
|
||||
{
|
||||
__asm__ __volatile__ ("mtspr 539, %0" :: "r" (x));
|
||||
}
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size = 0;
|
||||
int i;
|
||||
unsigned int msr;
|
||||
|
||||
/* BAT1 */
|
||||
CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
|
||||
CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
|
||||
msr = get_msr();
|
||||
set_msr(msr & ~(MSR_IR | MSR_DR));
|
||||
mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
|
||||
mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
|
||||
mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
|
||||
mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
|
||||
set_msr(msr);
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
if (!size)
|
||||
size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN)
|
||||
printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
|
||||
size, size<<20);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
void flash_print_info (flash_info_t *flash)
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int size;
|
||||
int erased;
|
||||
volatile unsigned long *p;
|
||||
|
||||
if (flash->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
flash_init();
|
||||
}
|
||||
|
||||
if (flash->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (((flash->flash_id) >> 16) & 0xff) {
|
||||
case 0x01:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
case 0x04:
|
||||
printf("FUJITSU ");
|
||||
break;
|
||||
case 0x20:
|
||||
printf("STM ");
|
||||
break;
|
||||
case 0xBF:
|
||||
printf("SST ");
|
||||
break;
|
||||
case 0x89:
|
||||
case 0xB0:
|
||||
printf("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch ((flash->flash_id) & 0xffff) {
|
||||
case (uint16_t)AMD_ID_LV800T:
|
||||
printf ("AM29LV800T\n");
|
||||
break;
|
||||
case (uint16_t)AMD_ID_LV800B:
|
||||
printf ("AM29LV800B\n");
|
||||
break;
|
||||
case (uint16_t)AMD_ID_LV160T:
|
||||
printf ("AM29LV160T\n");
|
||||
break;
|
||||
case (uint16_t)AMD_ID_LV160B:
|
||||
printf ("AM29LV160B\n");
|
||||
break;
|
||||
case (uint16_t)AMD_ID_LV320T:
|
||||
printf ("AM29LV320T\n");
|
||||
break;
|
||||
case (uint16_t)AMD_ID_LV320B:
|
||||
printf ("AM29LV320B\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F800C3T:
|
||||
printf ("28F800C3T\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F800C3B:
|
||||
printf ("28F800C3B\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F160C3T:
|
||||
printf ("28F160C3T\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F160C3B:
|
||||
printf ("28F160C3B\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F320C3T:
|
||||
printf ("28F320C3T\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F320C3B:
|
||||
printf ("28F320C3B\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F640C3T:
|
||||
printf ("28F640C3T\n");
|
||||
break;
|
||||
case (uint16_t)INTEL_ID_28F640C3B:
|
||||
printf ("28F640C3B\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (flash->size >= (1 << 20)) {
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
flash->size >> 20, flash->sector_count);
|
||||
} else {
|
||||
printf (" Size: %ld kB in %d Sectors\n",
|
||||
flash->size >> 10, flash->sector_count);
|
||||
}
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < flash->sector_count; ++i) {
|
||||
/* Check if whole sector is erased*/
|
||||
if (i != (flash->sector_count-1))
|
||||
size = flash->start[i+1] - flash->start[i];
|
||||
else
|
||||
size = flash->start[0] + flash->size - flash->start[i];
|
||||
|
||||
erased = 1;
|
||||
p = (volatile unsigned long *)flash->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k=0; k<size; k++) {
|
||||
if (*p++ != 0xffffffff) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
|
||||
printf (" %08lX%s%s",
|
||||
flash->start[i],
|
||||
erased ? " E" : " ",
|
||||
flash->protect[i] ? "RO " : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* board/eva/phantom.c
|
||||
*
|
||||
* Phantom RTC device driver for EVA
|
||||
*
|
||||
* Author: Sangmoon Kim
|
||||
* dogoil@etinsys.com
|
||||
*
|
||||
* Copyright 2002 Etinsys Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <rtc.h>
|
||||
|
||||
#if defined(CONFIG_CMD_DATE)
|
||||
|
||||
#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
|
||||
|
||||
#define RTC_YEAR ( RTC_BASE + 7 )
|
||||
#define RTC_MONTH ( RTC_BASE + 6 )
|
||||
#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
|
||||
#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
|
||||
#define RTC_HOURS ( RTC_BASE + 3 )
|
||||
#define RTC_MINUTES ( RTC_BASE + 2 )
|
||||
#define RTC_SECONDS ( RTC_BASE + 1 )
|
||||
#define RTC_CENTURY ( RTC_BASE + 0 )
|
||||
|
||||
#define RTC_CONTROLA RTC_CENTURY
|
||||
#define RTC_CONTROLB RTC_SECONDS
|
||||
#define RTC_CONTROLC RTC_DAY_OF_WEEK
|
||||
|
||||
#define RTC_CA_WRITE 0x80
|
||||
#define RTC_CA_READ 0x40
|
||||
|
||||
#define RTC_CB_OSC_DISABLE 0x80
|
||||
|
||||
#define RTC_CC_BATTERY_FLAG 0x80
|
||||
#define RTC_CC_FREQ_TEST 0x40
|
||||
|
||||
|
||||
static int phantom_flag = -1;
|
||||
static int century_flag = -1;
|
||||
|
||||
static uchar rtc_read(unsigned int addr)
|
||||
{
|
||||
return *(volatile unsigned char *)(addr);
|
||||
}
|
||||
|
||||
static void rtc_write(unsigned int addr, uchar val)
|
||||
{
|
||||
*(volatile unsigned char *)(addr) = val;
|
||||
}
|
||||
|
||||
static unsigned char phantom_rtc_sequence[] = {
|
||||
0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
|
||||
};
|
||||
|
||||
static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
|
||||
{
|
||||
int i, j;
|
||||
unsigned char v;
|
||||
unsigned char save = rtc_read(addr);
|
||||
|
||||
for (j = 0; j < 8; j++) {
|
||||
v = phantom_rtc_sequence[j];
|
||||
for (i = 0; i < 8; i++) {
|
||||
rtc_write(addr, v & 1);
|
||||
v >>= 1;
|
||||
}
|
||||
}
|
||||
for (j = 0; j < 8; j++) {
|
||||
v = 0;
|
||||
for (i = 0; i < 8; i++) {
|
||||
if(rtc_read(addr) & 1)
|
||||
v |= 1 << i;
|
||||
}
|
||||
rtc[j] = v;
|
||||
}
|
||||
rtc_write(addr, save);
|
||||
return rtc;
|
||||
}
|
||||
|
||||
static void phantom_rtc_write(int addr, unsigned char rtc[8])
|
||||
{
|
||||
int i, j;
|
||||
unsigned char v;
|
||||
unsigned char save = rtc_read(addr);
|
||||
for (j = 0; j < 8; j++) {
|
||||
v = phantom_rtc_sequence[j];
|
||||
for (i = 0; i < 8; i++) {
|
||||
rtc_write(addr, v & 1);
|
||||
v >>= 1;
|
||||
}
|
||||
}
|
||||
for (j = 0; j < 8; j++) {
|
||||
v = rtc[j];
|
||||
for (i = 0; i < 8; i++) {
|
||||
rtc_write(addr, v & 1);
|
||||
v >>= 1;
|
||||
}
|
||||
}
|
||||
rtc_write(addr, save);
|
||||
}
|
||||
|
||||
static int get_phantom_flag(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char rtc[8];
|
||||
|
||||
phantom_rtc_read(RTC_BASE, rtc);
|
||||
|
||||
for(i = 1; i < 8; i++) {
|
||||
if (rtc[i] != rtc[0])
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtc_reset(void)
|
||||
{
|
||||
if (phantom_flag < 0)
|
||||
phantom_flag = get_phantom_flag();
|
||||
|
||||
if (phantom_flag) {
|
||||
unsigned char rtc[8];
|
||||
phantom_rtc_read(RTC_BASE, rtc);
|
||||
if(rtc[4] & 0x30) {
|
||||
printf( "real-time-clock was stopped. Now starting...\n" );
|
||||
rtc[4] &= 0x07;
|
||||
phantom_rtc_write(RTC_BASE, rtc);
|
||||
}
|
||||
} else {
|
||||
uchar reg_a, reg_b, reg_c;
|
||||
reg_a = rtc_read( RTC_CONTROLA );
|
||||
reg_b = rtc_read( RTC_CONTROLB );
|
||||
|
||||
if ( reg_b & RTC_CB_OSC_DISABLE )
|
||||
{
|
||||
printf( "real-time-clock was stopped. Now starting...\n" );
|
||||
reg_a |= RTC_CA_WRITE;
|
||||
reg_b &= ~RTC_CB_OSC_DISABLE;
|
||||
rtc_write( RTC_CONTROLA, reg_a );
|
||||
rtc_write( RTC_CONTROLB, reg_b );
|
||||
}
|
||||
|
||||
/* make sure read/write clock register bits are cleared */
|
||||
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
|
||||
rtc_write( RTC_CONTROLA, reg_a );
|
||||
|
||||
reg_c = rtc_read( RTC_CONTROLC );
|
||||
if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
|
||||
printf( "RTC battery low. Clock setting may not be reliable.\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int get_century_flag(void)
|
||||
{
|
||||
int flag = 0;
|
||||
int bcd, century;
|
||||
bcd = rtc_read( RTC_CENTURY );
|
||||
century = bcd2bin( bcd & 0x3F );
|
||||
rtc_write( RTC_CENTURY, bin2bcd(century+1));
|
||||
if (bcd == rtc_read( RTC_CENTURY ))
|
||||
flag = 1;
|
||||
rtc_write( RTC_CENTURY, bcd);
|
||||
return flag;
|
||||
}
|
||||
|
||||
int rtc_get( struct rtc_time *tmp)
|
||||
{
|
||||
if (phantom_flag < 0)
|
||||
phantom_flag = get_phantom_flag();
|
||||
|
||||
if (phantom_flag)
|
||||
{
|
||||
unsigned char rtc[8];
|
||||
|
||||
phantom_rtc_read(RTC_BASE, rtc);
|
||||
|
||||
tmp->tm_sec = bcd2bin(rtc[1] & 0x7f);
|
||||
tmp->tm_min = bcd2bin(rtc[2] & 0x7f);
|
||||
tmp->tm_hour = bcd2bin(rtc[3] & 0x1f);
|
||||
tmp->tm_wday = bcd2bin(rtc[4] & 0x7);
|
||||
tmp->tm_mday = bcd2bin(rtc[5] & 0x3f);
|
||||
tmp->tm_mon = bcd2bin(rtc[6] & 0x1f);
|
||||
tmp->tm_year = bcd2bin(rtc[7]) + 1900;
|
||||
tmp->tm_yday = 0;
|
||||
tmp->tm_isdst = 0;
|
||||
|
||||
if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
|
||||
if (tmp->tm_year < 1970) tmp->tm_year += 100;
|
||||
} else {
|
||||
uchar sec, min, hour;
|
||||
uchar mday, wday, mon, year;
|
||||
|
||||
int century;
|
||||
|
||||
uchar reg_a;
|
||||
|
||||
if (century_flag < 0)
|
||||
century_flag = get_century_flag();
|
||||
|
||||
reg_a = rtc_read( RTC_CONTROLA );
|
||||
/* lock clock registers for read */
|
||||
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
|
||||
|
||||
sec = rtc_read( RTC_SECONDS );
|
||||
min = rtc_read( RTC_MINUTES );
|
||||
hour = rtc_read( RTC_HOURS );
|
||||
mday = rtc_read( RTC_DAY_OF_MONTH );
|
||||
wday = rtc_read( RTC_DAY_OF_WEEK );
|
||||
mon = rtc_read( RTC_MONTH );
|
||||
year = rtc_read( RTC_YEAR );
|
||||
century = rtc_read( RTC_CENTURY );
|
||||
|
||||
/* unlock clock registers after read */
|
||||
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
|
||||
|
||||
tmp->tm_sec = bcd2bin( sec & 0x7F );
|
||||
tmp->tm_min = bcd2bin( min & 0x7F );
|
||||
tmp->tm_hour = bcd2bin( hour & 0x3F );
|
||||
tmp->tm_mday = bcd2bin( mday & 0x3F );
|
||||
tmp->tm_mon = bcd2bin( mon & 0x1F );
|
||||
tmp->tm_wday = bcd2bin( wday & 0x07 );
|
||||
|
||||
if (century_flag) {
|
||||
tmp->tm_year = bcd2bin( year ) +
|
||||
( bcd2bin( century & 0x3F ) * 100 );
|
||||
} else {
|
||||
tmp->tm_year = bcd2bin( year ) + 1900;
|
||||
if (tmp->tm_year < 1970) tmp->tm_year += 100;
|
||||
}
|
||||
|
||||
tmp->tm_yday = 0;
|
||||
tmp->tm_isdst= 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_set( struct rtc_time *tmp )
|
||||
{
|
||||
if (phantom_flag < 0)
|
||||
phantom_flag = get_phantom_flag();
|
||||
|
||||
if (phantom_flag) {
|
||||
uint year;
|
||||
unsigned char rtc[8];
|
||||
|
||||
year = tmp->tm_year;
|
||||
year -= (year < 2000) ? 1900 : 2000;
|
||||
|
||||
rtc[0] = bin2bcd(0);
|
||||
rtc[1] = bin2bcd(tmp->tm_sec);
|
||||
rtc[2] = bin2bcd(tmp->tm_min);
|
||||
rtc[3] = bin2bcd(tmp->tm_hour);
|
||||
rtc[4] = bin2bcd(tmp->tm_wday);
|
||||
rtc[5] = bin2bcd(tmp->tm_mday);
|
||||
rtc[6] = bin2bcd(tmp->tm_mon);
|
||||
rtc[7] = bin2bcd(year);
|
||||
|
||||
phantom_rtc_write(RTC_BASE, rtc);
|
||||
} else {
|
||||
uchar reg_a;
|
||||
if (century_flag < 0)
|
||||
century_flag = get_century_flag();
|
||||
|
||||
/* lock clock registers for write */
|
||||
reg_a = rtc_read( RTC_CONTROLA );
|
||||
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
|
||||
|
||||
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
|
||||
|
||||
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
|
||||
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
|
||||
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
|
||||
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
|
||||
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
|
||||
|
||||
/* break year up into century and year in century */
|
||||
if (century_flag) {
|
||||
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
|
||||
rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
|
||||
reg_a &= 0xc0;
|
||||
reg_a |= bin2bcd( tmp->tm_year / 100 );
|
||||
} else {
|
||||
rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
|
||||
((tmp->tm_year < 2000) ? 1900 : 2000)));
|
||||
}
|
||||
|
||||
/* unlock clock registers after read */
|
||||
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for timer 2, ICLK = 10
|
||||
*
|
||||
* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
|
||||
* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
|
||||
*
|
||||
* SPEED_FCOUNT2 timer 2 counting frequency
|
||||
* GCLK CPU clock
|
||||
* SPEED_TMR2_PS prescaler
|
||||
*/
|
||||
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for PIT
|
||||
*
|
||||
* PIT_TIME = SPEED_PITC / PITRTCLK
|
||||
* PITRTCLK = 8192
|
||||
*/
|
||||
#define SPEED_PITC (82 << 16) /* start counting from 82 */
|
||||
|
||||
/*
|
||||
* The new value for PTA is calculated from
|
||||
*
|
||||
* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock !)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
* DFBRG For normal mode (no clock reduction) always 0
|
||||
* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
|
||||
* NCS Number of SDRAM banks (chip selects) on this UPM.
|
||||
*/
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o multiverse.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc824x.h>
|
||||
#include <pci.h>
|
||||
#include <i2c.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts ("Board: KVME080\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long setdram(int m, int row, int col, int bank)
|
||||
{
|
||||
int i;
|
||||
unsigned long start, end;
|
||||
uint32_t mccr1;
|
||||
uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
|
||||
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
|
||||
uint8_t mber = 0;
|
||||
|
||||
CONFIG_READ_WORD(MCCR1, mccr1);
|
||||
mccr1 &= 0xffff0000;
|
||||
|
||||
start = CONFIG_SYS_SDRAM_BASE;
|
||||
end = start + (1 << (col + row + 3) ) * bank - 1;
|
||||
|
||||
for (i = 0; i < m; i++) {
|
||||
mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
|
||||
if (i < 4) {
|
||||
msar1 |= ((start >> 20) & 0xff) << i * 8;
|
||||
emsar1 |= ((start >> 28) & 0xff) << i * 8;
|
||||
mear1 |= ((end >> 20) & 0xff) << i * 8;
|
||||
emear1 |= ((end >> 28) & 0xff) << i * 8;
|
||||
} else {
|
||||
msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
|
||||
emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
|
||||
mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
|
||||
emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
|
||||
}
|
||||
mber |= 1 << i;
|
||||
start += (1 << (col + row + 3) ) * bank;
|
||||
end += (1 << (col + row + 3) ) * bank;
|
||||
}
|
||||
for (; i < 8; i++) {
|
||||
if (i < 4) {
|
||||
msar1 |= 0xff << i * 8;
|
||||
emsar1 |= 0x30 << i * 8;
|
||||
mear1 |= 0xff << i * 8;
|
||||
emear1 |= 0x30 << i * 8;
|
||||
} else {
|
||||
msar2 |= 0xff << (i-4) * 8;
|
||||
emsar2 |= 0x30 << (i-4) * 8;
|
||||
mear2 |= 0xff << (i-4) * 8;
|
||||
emear2 |= 0x30 << (i-4) * 8;
|
||||
}
|
||||
}
|
||||
|
||||
CONFIG_WRITE_WORD(MCCR1, mccr1);
|
||||
CONFIG_WRITE_WORD(MSAR1, msar1);
|
||||
CONFIG_WRITE_WORD(EMSAR1, emsar1);
|
||||
CONFIG_WRITE_WORD(MEAR1, mear1);
|
||||
CONFIG_WRITE_WORD(EMEAR1, emear1);
|
||||
CONFIG_WRITE_WORD(MSAR2, msar2);
|
||||
CONFIG_WRITE_WORD(EMSAR2, emsar2);
|
||||
CONFIG_WRITE_WORD(MEAR2, mear2);
|
||||
CONFIG_WRITE_WORD(EMEAR2, emear2);
|
||||
CONFIG_WRITE_BYTE(MBER, mber);
|
||||
|
||||
return (1 << (col + row + 3) ) * bank * m;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
unsigned int msr;
|
||||
long int size = 0;
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_IR | MSR_DR));
|
||||
mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
|
||||
mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
|
||||
mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
|
||||
mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
|
||||
mtmsr(msr);
|
||||
|
||||
if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
|
||||
size = 0x20000000; /* 512MB */
|
||||
else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
|
||||
size = 0x10000000; /* 256MB */
|
||||
else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
|
||||
size = 0x10000000; /* 256MB */
|
||||
else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
|
||||
size = 0x08000000; /* 128MB */
|
||||
else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
|
||||
size = 0x08000000; /* 128MB */
|
||||
else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
|
||||
size = 0x04000000; /* 64MB */
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_IR | MSR_DR));
|
||||
mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
|
||||
mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
|
||||
mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
|
||||
mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
|
||||
mtmsr(msr);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
struct pci_controller hose;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc824x_init(&hose);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
*(volatile unsigned char *)(0xff080120) = 0xfb;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
unsigned int msr;
|
||||
|
||||
CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
|
||||
CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
|
||||
CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_IR | MSR_DR));
|
||||
mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
|
||||
mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
|
||||
mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
|
||||
mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
|
||||
mtmsr(msr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern int multiverse_init(void);
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
multiverse_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *nvram_read(void *dest, const long src, size_t count)
|
||||
{
|
||||
volatile uchar *d = (volatile uchar*) dest;
|
||||
volatile uchar *s = (volatile uchar*) src;
|
||||
while(count--) {
|
||||
*d++ = *s++;
|
||||
asm volatile("sync");
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
void nvram_write(long dest, const void *src, size_t count)
|
||||
{
|
||||
volatile uchar *d = (volatile uchar*)dest;
|
||||
volatile uchar *s = (volatile uchar*)src;
|
||||
while(count--) {
|
||||
*d++ = *s++;
|
||||
asm volatile("sync");
|
||||
}
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* multiverse.c
|
||||
*
|
||||
* VME driver for Multiverse
|
||||
*
|
||||
* Author : Sangmoon Kim
|
||||
* dogoil@etinsys.com
|
||||
*
|
||||
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#include "multiverse.h"
|
||||
|
||||
static unsigned long vme_asi_addr;
|
||||
static unsigned long vme_iack_addr;
|
||||
static unsigned long pci_reg_addr;
|
||||
static unsigned long vme_reg_addr;
|
||||
|
||||
int multiv_reset(unsigned long base)
|
||||
{
|
||||
writeb(0x09, base + VME_SLAVE32_AM);
|
||||
writeb(0x39, base + VME_SLAVE24_AM);
|
||||
writeb(0x29, base + VME_SLAVE16_AM);
|
||||
writeb(0x2f, base + VME_SLAVE_REG_AM);
|
||||
writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
|
||||
writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
|
||||
writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
|
||||
#ifdef A32_SLV_WINDOW
|
||||
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
|
||||
writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
|
||||
base + VME_SLAVE32_MASK);
|
||||
writeb(0x01, base + VME_SLAVE32_EN);
|
||||
} else {
|
||||
writeb(0xff, base + VME_SLAVE32_MASK);
|
||||
writeb(0x00, base + VME_SLAVE32_EN);
|
||||
}
|
||||
#else
|
||||
writeb(0xff, base + VME_SLAVE32_MASK);
|
||||
writeb(0x00, base + VME_SLAVE32_EN);
|
||||
#endif
|
||||
#ifdef A24_SLV_WINDOW
|
||||
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
|
||||
writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
|
||||
base + VME_SLAVE24_MASK);
|
||||
writeb(0x01, base + VME_SLAVE24_EN);
|
||||
} else {
|
||||
writeb(0xff, base + VME_SLAVE24_MASK);
|
||||
writeb(0x00, base + VME_SLAVE24_EN);
|
||||
}
|
||||
#else
|
||||
writeb(0xff, base + VME_SLAVE24_MASK);
|
||||
writeb(0x00, base + VME_SLAVE24_EN);
|
||||
#endif
|
||||
#ifdef A16_SLV_WINDOW
|
||||
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
|
||||
writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
|
||||
base + VME_SLAVE16_MASK);
|
||||
writeb(0x01, base + VME_SLAVE16_EN);
|
||||
} else {
|
||||
writeb(0xff, base + VME_SLAVE16_MASK);
|
||||
writeb(0x00, base + VME_SLAVE16_EN);
|
||||
}
|
||||
#else
|
||||
writeb(0xff, base + VME_SLAVE16_MASK);
|
||||
writeb(0x00, base + VME_SLAVE16_EN);
|
||||
#endif
|
||||
#ifdef REG_SLV_WINDOW
|
||||
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
|
||||
writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
|
||||
base + VME_SLAVE_REG_MASK);
|
||||
writeb(0x01, base + VME_SLAVE_REG_EN);
|
||||
} else {
|
||||
writeb(0xf8, base + VME_SLAVE_REG_MASK);
|
||||
}
|
||||
#else
|
||||
writeb(0xf8, base + VME_SLAVE_REG_MASK);
|
||||
#endif
|
||||
writeb(0x09, base + VME_MASTER32_AM);
|
||||
writeb(0x39, base + VME_MASTER24_AM);
|
||||
writeb(0x29, base + VME_MASTER16_AM);
|
||||
writeb(0x2f, base + VME_MASTER_REG_AM);
|
||||
writel(0x00000000, base + VME_RMW_ADRS);
|
||||
writeb(0x00, base + VME_IRQ);
|
||||
writeb(0x00, base + VME_INT_EN);
|
||||
writel(0x00000000, base + VME_IRQ1_REG);
|
||||
writel(0x00000000, base + VME_IRQ2_REG);
|
||||
writel(0x00000000, base + VME_IRQ3_REG);
|
||||
writel(0x00000000, base + VME_IRQ4_REG);
|
||||
writel(0x00000000, base + VME_IRQ5_REG);
|
||||
writel(0x00000000, base + VME_IRQ6_REG);
|
||||
writel(0x00000000, base + VME_IRQ7_REG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void multiv_auto_slot_id(unsigned long base)
|
||||
{
|
||||
__maybe_unused unsigned int vector;
|
||||
int slot_id = 1;
|
||||
if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
|
||||
*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
|
||||
writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
|
||||
writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
|
||||
base + VME_CTRL);
|
||||
while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
|
||||
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
|
||||
while (readb(base + VME_INT) & 0x04) {
|
||||
vector = *(volatile unsigned int*)
|
||||
(vme_iack_addr + VME_IACK2);
|
||||
*(unsigned char*)(vme_asi_addr + 0x7ffff)
|
||||
= (slot_id << 3) & 0xff;
|
||||
slot_id ++;
|
||||
if (slot_id > 31)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int multiverse_init(void)
|
||||
{
|
||||
int i;
|
||||
pci_dev_t pdev;
|
||||
unsigned int bar[6];
|
||||
|
||||
pdev = pci_find_device(0x1895, 0x0001, 0);
|
||||
|
||||
if (pdev == 0)
|
||||
return -1;
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
pci_read_config_dword (pdev,
|
||||
PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
|
||||
|
||||
pci_reg_addr = bar[0];
|
||||
vme_reg_addr = bar[1] + 0x00F00000;
|
||||
vme_iack_addr = bar[1] + 0x00200000;
|
||||
vme_asi_addr = bar[3];
|
||||
|
||||
pci_write_config_dword (pdev, PCI_COMMAND,
|
||||
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||||
|
||||
writel(0xFF000000, pci_reg_addr + P_TA1);
|
||||
writel(0x04, pci_reg_addr + P_IMG_CTRL1);
|
||||
writel(0xf0000000, pci_reg_addr + P_TA2);
|
||||
writel(0x04, pci_reg_addr + P_IMG_CTRL2);
|
||||
writel(0xF1000000, pci_reg_addr + P_TA3);
|
||||
writel(0x04, pci_reg_addr + P_IMG_CTRL3);
|
||||
writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
|
||||
writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
|
||||
writel(0x04, pci_reg_addr + P_IMG_CTRL5);
|
||||
|
||||
writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
|
||||
writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
|
||||
writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
|
||||
writel(0x04, pci_reg_addr + W_IMG_CTRL1);
|
||||
|
||||
writel(0xF0000000, pci_reg_addr + W_BA2);
|
||||
writel(0xFF000000, pci_reg_addr + W_AM2);
|
||||
writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
|
||||
writel(0x04, pci_reg_addr + W_IMG_CTRL2);
|
||||
|
||||
writel(0xFF000000, pci_reg_addr + W_BA3);
|
||||
writel(0xFF000000, pci_reg_addr + W_AM3);
|
||||
writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
|
||||
writel(0x04, pci_reg_addr + W_IMG_CTRL3);
|
||||
|
||||
writel(0x00000001, pci_reg_addr + W_ERR_CS);
|
||||
writel(0x00000001, pci_reg_addr + P_ERR_CS);
|
||||
|
||||
multiv_reset(vme_reg_addr);
|
||||
writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
|
||||
vme_reg_addr + VME_CTRL);
|
||||
|
||||
multiv_auto_slot_id(vme_reg_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* multiverse.h
|
||||
*
|
||||
* VME driver for Multiverse
|
||||
*
|
||||
* Author : Sangmoon Kim
|
||||
* dogoil@etinsys.com
|
||||
*
|
||||
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MULTIVERSE_H__
|
||||
#define __MULTIVERSE_H__
|
||||
|
||||
#define VME_A32_MSTR_BUS 0x90000000
|
||||
#define VME_A32_MSTR_SIZE 0x01000000
|
||||
|
||||
#define VME_A32_SLV_SIZE 0x01000000
|
||||
|
||||
#define VME_A32_SLV_BUS 0x90000000
|
||||
#define VME_A24_SLV_BUS 0x00000000
|
||||
#define VME_A16_SLV_BUS 0x00000000
|
||||
|
||||
#define VME_A32_SLV_LOCAL 0x00000000
|
||||
#define VME_A24_SLV_LOCAL 0x00000000
|
||||
#define VME_A16_SLV_LOCAL 0x00000000
|
||||
|
||||
#define A32_SLV_WINDOW
|
||||
#undef A24_SLV_WINDOW
|
||||
#undef A16_SLV_WINDOW
|
||||
#undef REG_SLV_WINDOW
|
||||
|
||||
/* PCI Registers */
|
||||
|
||||
#define P_IMG_CTRL0 0x100
|
||||
#define P_BA0 0x104
|
||||
#define P_AM0 0x108
|
||||
#define P_TA0 0x10C
|
||||
#define P_IMG_CTRL1 0x110
|
||||
#define P_BA1 0x114
|
||||
#define P_AM1 0x118
|
||||
#define P_TA1 0x11C
|
||||
#define P_IMG_CTRL2 0x120
|
||||
#define P_BA2 0x124
|
||||
#define P_AM2 0x128
|
||||
#define P_TA2 0x12C
|
||||
#define P_IMG_CTRL3 0x130
|
||||
#define P_BA3 0x134
|
||||
#define P_AM3 0x138
|
||||
#define P_TA3 0x13C
|
||||
#define P_IMG_CTRL4 0x140
|
||||
#define P_BA4 0x144
|
||||
#define P_AM4 0x148
|
||||
#define P_TA4 0x14C
|
||||
#define P_IMG_CTRL5 0x150
|
||||
#define P_BA5 0x154
|
||||
#define P_AM5 0x158
|
||||
#define P_TA5 0x15C
|
||||
#define P_ERR_CS 0x160
|
||||
#define P_ERR_ADDR 0x164
|
||||
#define P_ERR_DATA 0x168
|
||||
|
||||
#define WB_CONF_SPC_BAR 0x180
|
||||
#define W_IMG_CTRL1 0x184
|
||||
#define W_BA1 0x188
|
||||
#define W_AM1 0x18C
|
||||
#define W_TA1 0x190
|
||||
#define W_IMG_CTRL2 0x194
|
||||
#define W_BA2 0x198
|
||||
#define W_AM2 0x19C
|
||||
#define W_TA2 0x1A0
|
||||
#define W_IMG_CTRL3 0x1A4
|
||||
#define W_BA3 0x1A8
|
||||
#define W_AM3 0x1AC
|
||||
#define W_TA3 0x1B0
|
||||
#define W_IMG_CTRL4 0x1B4
|
||||
#define W_BA4 0x1B8
|
||||
#define W_AM4 0x1BC
|
||||
#define W_TA4 0x1C0
|
||||
#define W_IMG_CTRL5 0x1C4
|
||||
#define W_BA5 0x1C8
|
||||
#define W_AM5 0x1CC
|
||||
#define W_TA5 0x1D0
|
||||
#define W_ERR_CS 0x1D4
|
||||
#define W_ERR_ADDR 0x1D8
|
||||
#define W_ERR_DATA 0x1DC
|
||||
#define CNF_ADDR 0x1E0
|
||||
#define CNF_DATA 0x1E4
|
||||
#define INT_ACK 0x1E8
|
||||
#define ICR 0x1EC
|
||||
#define ISR 0x1F0
|
||||
|
||||
/* VME registers */
|
||||
|
||||
#define VME_SLAVE32_AM 0x03
|
||||
#define VME_SLAVE24_AM 0x02
|
||||
#define VME_SLAVE16_AM 0x01
|
||||
#define VME_SLAVE_REG_AM 0x00
|
||||
#define VME_SLAVE32_A 0x07
|
||||
#define VME_SLAVE24_A 0x06
|
||||
#define VME_SLAVE16_A 0x05
|
||||
#define VME_SLAVE_REG_A 0x04
|
||||
#define VME_SLAVE32_MASK 0x0B
|
||||
#define VME_SLAVE24_MASK 0x0A
|
||||
#define VME_SLAVE16_MASK 0x09
|
||||
#define VME_SLAVE_REG_MASK 0x08
|
||||
#define VME_SLAVE32_EN 0x0F
|
||||
#define VME_SLAVE24_EN 0x0E
|
||||
#define VME_SLAVE16_EN 0x0D
|
||||
#define VME_SLAVE_REG_EN 0x0C
|
||||
#define VME_MASTER32_AM 0x13
|
||||
#define VME_MASTER24_AM 0x12
|
||||
#define VME_MASTER16_AM 0x11
|
||||
#define VME_MASTER_REG_AM 0x10
|
||||
#define VME_RMW_ADRS 0x14
|
||||
#define VME_MBOX 0x18
|
||||
#define VME_STATUS 0x1E
|
||||
#define VME_CTRL 0x1C
|
||||
#define VME_IRQ 0x20
|
||||
#define VME_INT_EN 0x21
|
||||
#define VME_INT 0x22
|
||||
#define VME_IRQ1_REG 0x24
|
||||
#define VME_IRQ2_REG 0x28
|
||||
#define VME_IRQ3_REG 0x2C
|
||||
#define VME_IRQ4_REG 0x30
|
||||
#define VME_IRQ5_REG 0x34
|
||||
#define VME_IRQ6_REG 0x38
|
||||
#define VME_IRQ7_REG 0x3C
|
||||
|
||||
/* VME control register */
|
||||
|
||||
#define VME_CTRL_BRDRST 0x01
|
||||
#define VME_CTRL_SYSRST 0x02
|
||||
#define VME_CTRL_RMW 0x04
|
||||
#define VME_CTRL_SHORT_D 0x08
|
||||
#define VME_CTRL_SYSFAIL 0x10
|
||||
#define VME_CTRL_VOWN 0x20
|
||||
#define VME_CTRL_A16_REG_MODE 0x40
|
||||
|
||||
/* VME status register */
|
||||
|
||||
#define VME_STATUS_SYSCON 0x01
|
||||
#define VME_STATUS_SYSFAIL 0x02
|
||||
#define VME_STATUS_ACFAIL 0x04
|
||||
#define VME_STATUS_SYSRST 0x08
|
||||
#define VME_STATUS_VOWN 0x10
|
||||
|
||||
/* Interrupt types */
|
||||
|
||||
#define LVL1 0x0002
|
||||
#define LVL2 0x0004
|
||||
#define LVL3 0x0008
|
||||
#define LVL4 0x0010
|
||||
#define LVL5 0x0020
|
||||
#define LVL6 0x0040
|
||||
#define LVL7 0x0080
|
||||
#define MULTIVERSE_INTI_INT 0x0100
|
||||
#define MULTIVERSE_WB_INT 0x0200
|
||||
#define MULTIVERSE_PCI_INT 0x0400
|
||||
|
||||
/* interrupt acknowledge */
|
||||
|
||||
#define VME_IACK1 0x04
|
||||
#define VME_IACK2 0x08
|
||||
#define VME_IACK3 0x0c
|
||||
#define VME_IACK4 0x10
|
||||
#define VME_IACK5 0x14
|
||||
#define VME_IACK6 0x18
|
||||
#define VME_IACK7 0x1c
|
||||
|
||||
#endif /* __MULTIVERSE_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue