mirror of
https://github.com/Ysurac/openmptcprouter.git
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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
310
common/package/utils/sysupgrade-helper/src/board/evb64260/i2c.c
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310
common/package/utils/sysupgrade-helper/src/board/evb64260/i2c.c
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#include <common.h>
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#include <mpc8xx.h>
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#include <malloc.h>
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#include <galileo/gt64260R.h>
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#include <galileo/core.h>
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#define MAX_I2C_RETRYS 10
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#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
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#undef DEBUG_I2C
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#ifdef DEBUG_I2C
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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/* Assuming that there is only one master on the bus (us) */
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static void
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i2c_init(int speed, int slaveaddr)
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{
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unsigned int n, m, freq, margin, power;
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unsigned int actualn = 0, actualm = 0;
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unsigned int control, status;
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unsigned int minmargin = 0xffffffff;
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unsigned int tclk = 125000000;
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DP(puts("i2c_init\n"));
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for (n = 0 ; n < 8 ; n++) {
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for (m = 0 ; m < 16 ; m++) {
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power = 2 << n; /* power = 2^(n+1) */
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freq = tclk / (10 * (m + 1) * power);
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if (speed > freq)
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margin = speed - freq;
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else
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margin = freq - speed;
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if (margin < minmargin) {
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minmargin = margin;
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actualn = n;
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actualm = m;
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}
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}
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}
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DP(puts("setup i2c bus\n"));
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/* Setup bus */
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GT_REG_WRITE(I2C_SOFT_RESET, 0);
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DP(puts("udelay...\n"));
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udelay(I2C_DELAY);
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DP(puts("set baudrate\n"));
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GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn);
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
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udelay(I2C_DELAY * 10);
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DP(puts("read control, baudrate\n"));
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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GT_REG_READ(I2C_CONTROL, &control);
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}
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static uchar
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i2c_start(void)
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{
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unsigned int control, status;
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int count = 0;
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DP(puts("i2c_start\n"));
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/* Set the start bit */
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GT_REG_READ(I2C_CONTROL, &control);
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control |= (0x1 << 5);
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GT_REG_WRITE(I2C_CONTROL, control);
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count = 0;
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while ((status & 0xff) != 0x08) {
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udelay(I2C_DELAY);
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if (count > 20) {
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
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return status;
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}
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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return 0;
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}
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static uchar
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i2c_select_device(uchar dev_addr, uchar read, int ten_bit)
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{
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unsigned int status, data, bits = 7;
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int count = 0;
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DP(puts("i2c_select_device\n"));
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/* Output slave address */
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if (ten_bit)
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bits = 10;
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data = (dev_addr << 1);
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/* set the read bit */
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data |= read;
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GT_REG_WRITE(I2C_DATA, data);
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/* assert the address */
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RESET_REG_BITS(I2C_CONTROL, BIT3);
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udelay(I2C_DELAY);
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count = 0;
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while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
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udelay(I2C_DELAY);
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if (count > 20) {
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
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return status;
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}
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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if (bits == 10) {
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printf("10 bit I2C addressing not yet implemented\n");
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return 0xff;
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}
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return 0;
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}
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static uchar
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i2c_get_data(uchar *return_data, int len) {
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unsigned int data, status = 0;
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int count = 0;
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DP(puts("i2c_get_data\n"));
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while (len) {
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/* Get and return the data */
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RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
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udelay(I2C_DELAY * 5);
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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while ((status & 0xff) != 0x50) {
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udelay(I2C_DELAY);
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if (count > 2) {
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
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return 0;
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}
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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GT_REG_READ(I2C_DATA, &data);
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len--;
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*return_data = (uchar)data;
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return_data++;
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}
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RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
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while ((status & 0xff) != 0x58) {
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udelay(I2C_DELAY);
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if (count > 200) {
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
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return status;
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}
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
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return 0;
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}
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static uchar
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i2c_write_data(unsigned int data, int len)
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{
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unsigned int status;
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int count = 0;
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DP(puts("i2c_write_data\n"));
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if (len > 4)
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return -1;
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while (len) {
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/* Set and assert the data */
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GT_REG_WRITE(I2C_DATA, (unsigned int)data);
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RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
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udelay(I2C_DELAY);
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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while ((status & 0xff) != 0x28) {
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udelay(I2C_DELAY);
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if (count > 20) {
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
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return status;
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}
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GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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len--;
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}
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
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GT_REG_WRITE(I2C_CONTROL, (0x1 << 4));
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udelay(I2C_DELAY * 10);
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return 0;
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}
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static uchar
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i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit)
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{
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uchar status;
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DP(puts("i2c_set_dev_offset\n"));
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status = i2c_select_device(dev_addr, 0, ten_bit);
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if (status) {
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#ifdef DEBUG_I2C
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printf("Failed to select device setting offset: 0x%02x\n",
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status);
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#endif
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return status;
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}
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status = i2c_write_data(offset, 1);
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if (status) {
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#ifdef DEBUG_I2C
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printf("Failed to write data: 0x%02x\n", status);
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#endif
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return status;
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}
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return 0;
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}
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uchar
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i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data,
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int ten_bit)
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{
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uchar status = 0;
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unsigned int i2cfreq = 400000;
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DP(puts("i2c_read\n"));
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i2c_init(i2cfreq, 0);
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status = i2c_start();
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if (status) {
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#ifdef DEBUG_I2C
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printf("Transaction start failed: 0x%02x\n", status);
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#endif
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return status;
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}
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status = i2c_set_dev_offset(dev_addr, 0, 0);
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if (status) {
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#ifdef DEBUG_I2C
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printf("Failed to set offset: 0x%02x\n", status);
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#endif
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return status;
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}
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i2c_init(i2cfreq, 0);
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status = i2c_start();
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if (status) {
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#ifdef DEBUG_I2C
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printf("Transaction restart failed: 0x%02x\n", status);
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#endif
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return status;
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}
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status = i2c_select_device(dev_addr, 1, ten_bit);
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if (status) {
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#ifdef DEBUG_I2C
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printf("Address not acknowledged: 0x%02x\n", status);
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#endif
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return status;
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}
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status = i2c_get_data(data, len);
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if (status) {
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#ifdef DEBUG_I2C
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printf("Data not received: 0x%02x\n", status);
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#endif
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return status;
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}
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return 0;
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}
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