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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport

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Ycarus (Yannick Chabanois) 2023-04-22 08:07:24 +02:00
parent e910436a7a
commit 46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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53
common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/Makefile Normal file
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#
# Copyright 2011-2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
#COBJS-y += bsc9131rdb_mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/README Normal file
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Overview
--------
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- It's MAPLE disabled personality is called 9231.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The e500 core subsystem within the Power Architecture consists of the following:
. 32-Kbyte L1 instruction cache
. 32-Kbyte L1 data cache
. 256-Kbyte L2 cache/L2 memory/L2 stash
. programmable interrupt controller (PIC)
. Debug support
. Timers
The SC3850 core subsystem consists of the following:
. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
. 32 Kbyte 8-way level 1 data cache (L1 DCache)
. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
. Memory management unit (MMU)
. Enhanced programmable interrupt controller (EPIC)
. Debug and profiling unit (DPU)
. Two 32-bit timers
BSC9131RDB board Overview
-------------------------
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
USIM connector
Frequency Combinations Supported
--------------------------------
Core MHz/CCB MHz/DDR(MT/s)
1. 1000/500/800
2. 800/400/667
Boot Methods Supported
-----------------------
1. NAND Flash
2. SPI Flash
Default Boot Method
--------------------
NAND boot
Building U-boot
--------------
To build the u-boot for BSC9131RDB:
1. NAND Flash
make BSC9131RDB_NAND
2. SPI Flash
make BSC9131RDB_SPIFLASH
Memory map
-----------
0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
Flashing Images
---------------
To place a new u-boot image in the NAND flash and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot-nand.bin
nand erase 0 100000
nand write 1000000 0 100000
reset
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 bsc9131rdb.dtb
bootm 1000000 2000000 c00000

83
common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/bsc9131rdb.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
MPC85xx_PMUXCR_IFC_AD_GPIO |
MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
return 0;
}
int checkboard(void)
{
struct cpu_type *cpu;
cpu = gd->cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_dr_usb(blob, bd);
}
#endif

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common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/ddr.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{0, 0, NULL}
};
unsigned long get_sdram_size(void)
{
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
}
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0) {
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
return ddr_size;
}
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/* Micron MT41J256M8HX-15E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 1073741824u,
.capacity = 1073741824u,
.primary_sdram_width = 32,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
.tCKmin_X_ps = 1870,
.caslat_X = 0x1e << 4, /* 5,6,7,8 */
.tAA_ps = 13125,
.tWR_ps = 15000,
.tRCD_ps = 13125,
.tRRD_ps = 7500,
.tRP_ps = 13125,
.tRAS_ps = 37500,
.tRC_ps = 50625,
.tRFC_ps = 160000,
.tWTR_ps = 7500,
.tRTP_ps = 7500,
.refresh_rate_ps = 7800000,
.tFAW_ps = 37500,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */

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common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/law.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int num_law_entries = ARRAY_SIZE(law_table);

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common/package/utils/sysupgrade-helper/src/board/freescale/bsc9131rdb/tlb.c Normal file
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/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1M, 1)
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

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common/package/utils/sysupgrade-helper/src/board/freescale/common/Makefile Normal file
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#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/freescale/common)
endif
LIB = $(obj)libfreescale.o
COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FMAN_ENET) += fman.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
COBJS-$(CONFIG_FSL_QIXIS) += qixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
ifndef CONFIG_RAMBOOT_PBL
COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
endif
COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
SUBLIB := $(addprefix $(obj),$(SUBLIB-y))
$(LIB): $(obj).depend $(OBJS) $(SUBLIB)
$(call cmd_link_o_target, $(OBJS) $(SUBLIB))
$(SUBLIB): $(obj).depend
$(MAKE) -C $(dir $(subst $(obj),,$@))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

95
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/*
* Copyright 2004, 2011 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* CADMUS Board System Registers
*/
#ifndef CONFIG_SYS_CADMUS_BASE_REG
#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
#endif
typedef struct cadmus_reg {
u_char cm_ver; /* Board version */
u_char cm_csr; /* General control/status */
u_char cm_rst; /* Reset control */
u_char cm_hsclk; /* High speed clock */
u_char cm_hsxclk; /* High speed clock extended */
u_char cm_led; /* LED data */
u_char cm_pci; /* PCI control/status */
u_char cm_dma; /* DMA control */
u_char cm_reserved[248]; /* Total 256 bytes */
} cadmus_reg_t;
unsigned int
get_board_version(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
return cadmus->cm_ver;
}
unsigned long
get_clock_freq(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
if (pci1_speed == 0) {
return 33333333;
} else if (pci1_speed == 1) {
return 66666666;
} else {
/* Really, unknown. Be safe? */
return 33333333;
}
}
unsigned int
get_pci_slot(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* PCI slot in USER bits CSR[6:7] by convention.
*/
return ((cadmus->cm_csr >> 6) & 0x3) + 1;
}
unsigned int
get_pci_dual(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* PCI DUAL in CM_PCI[3]
*/
return cadmus->cm_pci & 0x10;
}

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/*
* Copyright 2004 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CADMUS_H_
#define __CADMUS_H_
/*
* CADMUS Board System Register interface.
*/
/*
* Returns board version register.
*/
extern unsigned int get_board_version(void);
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
extern unsigned long get_clock_freq(void);
/*
* Returns 1 - 4, as found in the USER CSR[6:7] bits.
*/
extern unsigned int get_pci_slot(void);
/*
* Returns PCI DUAL as found in CM_PCI[3].
*/
extern unsigned int get_pci_dual(void);
#endif /* __CADMUS_H_ */

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/*
* Copyright 2004 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP)
static void cds_pci_fixup(void *blob)
{
int node;
const char *path;
int len, slot, i;
u32 *map = NULL;
node = fdt_path_offset(blob, "/aliases");
if (node >= 0) {
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
node = fdt_path_offset(blob, path);
if (node >= 0) {
map = fdt_getprop_w(blob, node, "interrupt-map", &len);
}
}
}
if (map) {
len /= sizeof(u32);
slot = get_pci_slot();
for (i=0;i<len;i+=7) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
map+=7;
}
}
}
void
ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
}
#endif

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/*
* Copyright 2006 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
/* Config the VIA chip */
void mpc85xx_config_via(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pci_dev_t bridge;
unsigned int cmdstat;
/* Enable USB and IDE functions */
pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/*
* Force the backplane P2P bridge to have a window
* open from 0x00000000-0x00001fff in PCI I/O space.
* This allows legacy I/O (i8259, etc) on the VIA
* southbridge to be accessed.
*/
bridge = PCI_BDF(0,BRIDGE_ID,0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
}
/* Function 1, IDE */
void mpc85xx_config_via_usbide(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pciauto_config_device(hose, dev);
/*
* Since the P2P window was forced to cover the fixed
* legacy I/O addresses, it is necessary to manually
* place the base addresses for the IDE and USB functions
* within this window.
*/
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
}
/* Function 2, USB ports 0-1 */
void mpc85xx_config_via_usb(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pciauto_config_device(hose, dev);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
}
/* Function 3, USB ports 2-3 */
void mpc85xx_config_via_usb2(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pciauto_config_device(hose, dev);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
}
/* Function 5, Power Management */
void mpc85xx_config_via_power(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pciauto_config_device(hose, dev);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
}
/* Function 6, AC97 Interface */
void mpc85xx_config_via_ac97(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pciauto_config_device(hose, dev);
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
}

50
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/*
* Copyright 2004 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EEPROM_H_
#define __EEPROM_H_
/*
* EEPROM Board System Register interface.
*/
/*
* CPU Board Revision
*/
#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
/*
* Returns CPU board revision register as a 16-bit value with
* the Major in the high byte, and Minor in the low byte.
*/
extern unsigned int get_cpu_board_revision(void);
#endif /* __CADMUS_H_ */

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
/*
* Given the following ...
*
* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
* compatible string and 'addr' physical address)
*
* 2) The name of an alias that points to the ethernet-phy node (usually inside
* a virtual MDIO node)
*
* ... update that Ethernet node's phy-handle property to point to the
* ethernet-phy node. This is how we link an Ethernet node to its PHY, so each
* PHY in a virtual MDIO node must have an alias.
*
* Returns 0 on success, or a negative FDT error code on error.
*/
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias)
{
int offset;
unsigned int ph;
const char *path;
/* Get a path to the node that 'alias' points to */
path = fdt_get_alias(fdt, alias);
if (!path)
return -FDT_ERR_BADPATH;
/* Get the offset of that node */
offset = fdt_path_offset(fdt, path);
if (offset < 0)
return offset;
ph = fdt_create_phandle(fdt, offset);
if (!ph)
return -FDT_ERR_BADPHANDLE;
offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
if (offset < 0)
return offset;
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FMAN_BOARD_HELPER__
#define __FMAN_BOARD_HELPER__
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
#endif

162
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/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include "ics307_clk.h"
#if defined(CONFIG_FSL_NGPIXIS)
#include "ngpixis.h"
#define fpga_reg pixis
#elif defined(CONFIG_FSL_QIXIS)
#include "qixis.h"
#define fpga_reg ((struct qixis *)QIXIS_BASE)
#else
#include "pixis.h"
#define fpga_reg pixis
#endif
/* define for SYS CLK or CLK1Frequency */
#define TTL 1
#define CLK2 0
#define CRYSTAL 0
#define MAX_VDW (511 + 8)
#define MAX_RDW (127 + 2)
#define MIN_VDW (4 + 8)
#define MIN_RDW (1 + 2)
#define NUM_OD_SETTING 8
/*
* These defines cover the industrial temperature range part,
* for commercial, change below to 400000 and 55000, respectively
*/
#define MAX_VCO 360000
#define MIN_VCO 60000
/* decode S[0-2] to Output Divider (OD) */
static u8 ics307_s_to_od[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/*
* Find one solution to generate required frequency for SYSCLK
* out_freq: KHz, required frequency to the SYSCLK
* the result will be retuned with component RDW, VDW, OD, TTL,
* CLK2 and crystal
*/
unsigned long ics307_sysclk_calculator(unsigned long out_freq)
{
const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
unsigned long tmp_out, diff, result = 0;
int found = 0;
for (odp = 0; odp < NUM_OD_SETTING; odp++) {
od = ics307_s_to_od[odp];
if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
continue;
for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
/* Calculate the VDW */
vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
if (vdw > MAX_VDW)
vdw = MAX_VDW;
if (vdw < MIN_VDW)
continue;
/* Calculate the temp out frequency */
tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
/*
* calculate the percent, the precision is 1/1000
* If greater than 1/1000, continue
* otherwise, we think the solution is we required
*/
if (diff * 1000 / out_freq > 1)
continue;
else {
s_vdw = vdw;
s_rdw = rdw;
s_odp = odp;
found = 1;
break;
}
}
}
if (found)
result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
ics307_s_to_od[s_odp]);
return result;
}
/*
* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it.
*/
static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
{
const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
unsigned long rdw = cw2 & 0x7F;
unsigned long od = ics307_s_to_od[cw0 & 0x7];
unsigned long freq;
/*
* CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
*
* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*
*/
freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
freq);
return freq;
}
unsigned long get_board_sys_clk(void)
{
return ics307_clk_freq(
in_8(&fpga_reg->sclk[0]),
in_8(&fpga_reg->sclk[1]),
in_8(&fpga_reg->sclk[2]));
}
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
in_8(&fpga_reg->dclk[0]),
in_8(&fpga_reg->dclk[1]),
in_8(&fpga_reg->dclk[2]));
}

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/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ICS_CLK_H_
#define __ICS_CLK_H_ 1
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif
#endif /* __ICS_CLK_H_ */

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common/package/utils/sysupgrade-helper/src/board/freescale/common/ngpixis.c Normal file
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/**
* Copyright 2010-2011 Freescale Semiconductor
* Author: Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*
* A "switch" is black rectangular block on the motherboard. It contains
* eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
* shadow the actual physical switches. There is also another set of
* registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
* used to override the values of the bits in the physical switches.
*
* The following macros need to be defined:
*
* PIXIS_BASE - The virtual address of the base of the PIXIS register map
*
* PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
* is used in the PIXIS_SW() macro to determine which offset in
* the PIXIS register map corresponds to the physical switch that controls
* the boot bank.
*
* PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
*
* PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
*
* PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
* boot from the alternate bank.
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "ngpixis.h"
static u8 __pixis_read(unsigned int reg)
{
void *p = (void *)PIXIS_BASE;
return in_8(p + reg);
}
u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read")));
static void __pixis_write(unsigned int reg, u8 value)
{
void *p = (void *)PIXIS_BASE;
out_8(p + reg, value);
}
void pixis_write(unsigned int reg, u8 value)
__attribute__((weak, alias("__pixis_write")));
/*
* Reset the board. This ignores the ENx registers.
*/
void __pixis_reset(void)
{
PIXIS_WRITE(rst, 0);
while (1);
}
void pixis_reset(void) __attribute__((weak, alias("__pixis_reset")));
/*
* Reset the board. Like pixis_reset(), but it honors the ENx registers.
*/
void __pixis_bank_reset(void)
{
PIXIS_WRITE(vctl, 0);
PIXIS_WRITE(vctl, 1);
while (1);
}
void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset")));
/**
* Set the boot bank to the power-on default bank
*/
void __clear_altbank(void)
{
u8 reg;
/* Tell the ngPIXIS to use this the bits in the physical switch for the
* boot bank value, instead of the SWx register. We need to be careful
* only to set the bits in SWx that correspond to the boot bank.
*/
reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
reg &= ~PIXIS_LBMAP_MASK;
PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
}
void clear_altbank(void) __attribute__((weak, alias("__clear_altbank")));
/**
* Set the boot bank to the alternate bank
*/
void __set_altbank(void)
{
u8 reg;
/* Program the alternate bank number into the SWx register.
*/
reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw);
reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK;
PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg);
/* Tell the ngPIXIS to use this the bits in the SWx register for the
* boot bank value, instead of the physical switch. We need to be
* careful only to set the bits in SWx that correspond to the boot bank.
*/
reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
reg |= PIXIS_LBMAP_MASK;
PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
}
void set_altbank(void) __attribute__((weak, alias("__set_altbank")));
#ifdef DEBUG
static void pixis_dump_regs(void)
{
unsigned int i;
printf("id=%02x\n", PIXIS_READ(id));
printf("arch=%02x\n", PIXIS_READ(arch));
printf("scver=%02x\n", PIXIS_READ(scver));
printf("csr=%02x\n", PIXIS_READ(csr));
printf("rst=%02x\n", PIXIS_READ(rst));
printf("aux=%02x\n", PIXIS_READ(aux));
printf("spd=%02x\n", PIXIS_READ(spd));
printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0));
printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1));
printf("addr=%02x\n", PIXIS_READ(addr));
printf("data=%02x\n", PIXIS_READ(data));
printf("led=%02x\n", PIXIS_READ(led));
printf("vctl=%02x\n", PIXIS_READ(vctl));
printf("vstat=%02x\n", PIXIS_READ(vstat));
printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0));
printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr));
printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg));
printf("gmdbg=%02x\n", PIXIS_READ(gmdbg));
printf("sclk=%02x%02x%02x\n",
PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2]));
printf("dclk=%02x%02x%02x\n",
PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2]));
printf("watch=%02x\n", PIXIS_READ(watch));
for (i = 0; i < 8; i++) {
printf("SW%u=%02x/%02x ", i + 1,
PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en));
}
putc('\n');
}
#endif
void pixis_sysclk_set(unsigned long sysclk)
{
unsigned long freq_word;
u8 sclk0, sclk1, sclk2;
freq_word = ics307_sysclk_calculator(sysclk);
sclk2 = freq_word & 0xff;
sclk1 = (freq_word >> 8) & 0xff;
sclk0 = (freq_word >> 16) & 0xff;
/* set SYSCLK enable bit */
PIXIS_WRITE(vcfgen0, 0x01);
/* SYSCLK to required frequency */
PIXIS_WRITE(sclk[0], sclk0);
PIXIS_WRITE(sclk[1], sclk1);
PIXIS_WRITE(sclk[2], sclk2);
}
int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int i;
unsigned long sysclk;
char *p_altbank = NULL;
#ifdef DEBUG
char *p_dump = NULL;
#endif
char *unknown_param = NULL;
/* No args is a simple reset request.
*/
if (argc <= 1)
pixis_reset();
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "altbank") == 0) {
p_altbank = argv[i];
continue;
}
#ifdef DEBUG
if (strcmp(argv[i], "dump") == 0) {
p_dump = argv[i];
continue;
}
#endif
if (strcmp(argv[i], "sysclk") == 0) {
sysclk = simple_strtoul(argv[i + 1], NULL, 0);
i += 1;
pixis_sysclk_set(sysclk);
continue;
}
unknown_param = argv[i];
}
if (unknown_param) {
printf("Invalid option: %s\n", unknown_param);
return 1;
}
#ifdef DEBUG
if (p_dump) {
pixis_dump_regs();
/* 'dump' ignores other commands */
return 0;
}
#endif
if (p_altbank)
set_altbank();
else
clear_altbank();
pixis_bank_reset();
/* Shouldn't be reached. */
return 0;
}
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"Reset the board using the FPGA sequencer",
"- hard reset to default bank\n"
"pixis_reset altbank - reset to alternate bank\n"
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
);

64
common/package/utils/sysupgrade-helper/src/board/freescale/common/ngpixis.h Normal file
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/**
* Copyright 2010-2011 Freescale Semiconductor
* Author: Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*/
/* ngPIXIS register set. Hopefully, this won't change too much over time.
* Feel free to add board-specific #ifdefs where necessary.
*/
typedef struct ngpixis {
u8 id;
u8 arch;
u8 scver;
u8 csr;
u8 rst;
u8 serclk;
u8 aux;
u8 spd;
u8 brdcfg0;
u8 brdcfg1; /* On some boards, this register is called 'dma' */
u8 addr;
u8 brdcfg2;
u8 gpiodir;
u8 data;
u8 led;
u8 tag;
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 res4;
u8 ocmcsr;
u8 ocmmsg;
u8 gmdbg;
u8 res5[2];
u8 sclk[3];
u8 dclk[3];
u8 watch;
struct {
u8 sw;
u8 en;
} s[8];
} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */
#define pixis ((ngpixis_t *)PIXIS_BASE)
/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
u8 pixis_read(unsigned int reg);
void pixis_write(unsigned int reg, u8 value);
#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg))
#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value)

31
common/package/utils/sysupgrade-helper/src/board/freescale/common/p_corenet/Makefile Normal file
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#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = libp_corenet.o
COBJS-y += law.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += tlb.o
include $(TOPDIR)/post/rules.mk

66
common/package/utils/sysupgrade-helper/src/board/freescale/common/p_corenet/law.c Normal file
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/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
#endif
#ifdef PIXIS_BASE_PHYS
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#endif
#ifdef CPLD_BASE_PHYS
SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

39
common/package/utils/sysupgrade-helper/src/board/freescale/common/p_corenet/pci.c Normal file
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/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

162
common/package/utils/sysupgrade-helper/src/board/freescale/common/p_corenet/tlb.c Normal file
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/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
#ifdef CPLD_BASE
SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
#endif
#ifdef PIXIS_BASE
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
#endif
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIOBOOT_SLAVE)
/*
* SRIOBOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_1M, 1),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
/*
* SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
* and ENV from master
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

556
common/package/utils/sysupgrade-helper/src/board/freescale/common/pixis.c Normal file
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/*
* Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#define pixis_base (u8 *)PIXIS_BASE
/*
* Simple board reset.
*/
void pixis_reset(void)
{
out_8(pixis_base + PIXIS_RST, 0);
while (1);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
static int set_px_sysclk(unsigned long sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
switch (sysclk) {
case 33:
sysclk_s = 0x04;
sysclk_r = 0x04;
sysclk_v = 0x07;
sysclk_aux = 0x00;
break;
case 40:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x20;
sysclk_aux = 0x01;
break;
case 50:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x2A;
sysclk_aux = 0x02;
break;
case 66:
sysclk_s = 0x01;
sysclk_r = 0x04;
sysclk_v = 0x04;
sysclk_aux = 0x03;
break;
case 83:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x4B;
sysclk_aux = 0x04;
break;
case 100:
sysclk_s = 0x01;
sysclk_r = 0x1F;
sysclk_v = 0x5C;
sysclk_aux = 0x05;
break;
case 134:
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x3B;
sysclk_aux = 0x06;
break;
case 166:
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x4B;
sysclk_aux = 0x07;
break;
default:
printf("Unsupported SYSCLK frequency.\n");
return 0;
}
vclkh = (sysclk_s << 5) | sysclk_r;
vclkl = sysclk_v;
out_8(pixis_base + PIXIS_VCLKH, vclkh);
out_8(pixis_base + PIXIS_VCLKL, vclkl);
out_8(pixis_base + PIXIS_AUX, sysclk_aux);
return 1;
}
/* Set the CFG_SYSPLL bits
*
* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
* read_from_px_regs() is called.
*/
static int set_px_mpxpll(unsigned long mpxpll)
{
switch (mpxpll) {
case 2:
case 4:
case 6:
case 8:
case 10:
case 12:
case 14:
case 16:
clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
return 1;
}
printf("Unsupported MPXPLL ratio.\n");
return 0;
}
static int set_px_corepll(unsigned long corepll)
{
u8 val;
switch (corepll) {
case 20:
val = 0x08;
break;
case 25:
val = 0x0C;
break;
case 30:
val = 0x10;
break;
case 35:
val = 0x1C;
break;
case 40:
val = 0x14;
break;
case 45:
val = 0x0E;
break;
default:
printf("Unsupported COREPLL ratio.\n");
return 0;
}
clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
return 1;
}
#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
#endif
/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or various other PIXIS registers to determine the values for COREPLL,
* MPXPLL, and SYSCLK.
*
* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
* register that tells the pixis to use the various PIXIS register.
*/
static void read_from_px_regs(int set)
{
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
else
tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
#endif
/* Configure the source of the boot location
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or the PX_VBOOT[LBMAP] register to determine where we should boot.
*
* If we want to boot from the alternate boot bank, we need to tell the PIXIS
* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
*/
static void read_from_px_regs_altbank(int set)
{
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
else
tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
* tells the PIXIS what the alternate flash bank is.
*
* Note that it's not really a mask. It contains the actual LBMAP bits that
* must be set to select the alternate bank. This code assumes that the
* primary bank has these bits set to 0, and the alternate bank has these
* bits set to 1.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
/* Tell the PIXIS to boot from the default flash bank
*
* Program the default flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void clear_altbank(void)
{
clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
/* Tell the PIXIS to boot from the alternate flash bank
*
* Program the alternate flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void set_altbank(void)
{
setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
/* Reset the board with watchdog disabled.
*
* This respects the altbank setting.
*/
static void set_px_go(void)
{
/* Disable the VELA sequencer and watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
/* Reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x1);
while (1);
}
/* Reset the board with watchdog enabled.
*
* This respects the altbank setting.
*/
static void set_px_go_with_watchdog(void)
{
/* Disable the VELA sequencer */
clrbits_8(pixis_base + PIXIS_VCTL, 1);
/* Enable the watchdog and reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x9);
while (1);
}
/* Disable the watchdog
*
*/
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
/* Disable the VELA sequencer and the watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
return 0;
}
U_BOOT_CMD(
diswd, 1, 0, pixis_disable_watchdog_cmd,
"Disable watchdog timer",
""
);
#ifdef CONFIG_PIXIS_SGMII_CMD
/* Enable or disable SGMII mode for a TSEC
*/
static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int which_tsec = -1;
unsigned char mask;
unsigned char switch_mask;
if ((argc > 2) && (strcmp(argv[1], "all") != 0))
which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
case 1:
mask = PIXIS_VSPEED2_TSEC1SER;
switch_mask = PIXIS_VCFGEN1_TSEC1SER;
break;
#endif
#ifdef CONFIG_TSEC2
case 2:
mask = PIXIS_VSPEED2_TSEC2SER;
switch_mask = PIXIS_VCFGEN1_TSEC2SER;
break;
#endif
#ifdef CONFIG_TSEC3
case 3:
mask = PIXIS_VSPEED2_TSEC3SER;
switch_mask = PIXIS_VCFGEN1_TSEC3SER;
break;
#endif
#ifdef CONFIG_TSEC4
case 4:
mask = PIXIS_VSPEED2_TSEC4SER;
switch_mask = PIXIS_VCFGEN1_TSEC4SER;
break;
#endif
default:
mask = PIXIS_VSPEED2_MASK;
switch_mask = PIXIS_VCFGEN1_MASK;
break;
}
/* Toggle whether the switches or FPGA control the settings */
if (!strcmp(argv[argc - 1], "switch"))
clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
else
setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
/* If it's not the switches, enable or disable SGMII, as specified */
if (!strcmp(argv[argc - 1], "on"))
clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
else if (!strcmp(argv[argc - 1], "off"))
setbits_8(pixis_base + PIXIS_VSPEED2, mask);
return 0;
}
U_BOOT_CMD(
pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
"pixis_set_sgmii"
" - Enable or disable SGMII mode for a given TSEC \n",
"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
" on - enables SGMII\n"
" off - disables SGMII\n"
" switch - use switch settings"
);
#endif
/*
* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign
* FPGA register values.
* input: strptr i.e. argv[2]
*/
static unsigned long strfractoint(char *strptr)
{
int i, j;
int mulconst;
int no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
/* Assign the integer part to intarr[]
* If there is no decimal point i.e.
* if the ratio is an integral value
* simply create the intarr.
*/
i = 0;
while (strptr[i] != '.') {
if (strptr[i] == 0) {
no_dec = 1;
break;
}
intarr[i] = strptr[i];
i++;
}
intarr[i] = '\0';
if (no_dec) {
/* Currently needed only for single digit corepll ratios */
mulconst = 10;
decval = 0;
} else {
j = 0;
i++; /* Skipping the decimal point */
while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
decarr[j] = strptr[i];
i++;
j++;
}
decarr[j] = '\0';
mulconst = 1;
for (i = 0; i < j; i++)
mulconst *= 10;
decval = simple_strtoul(decarr, NULL, 10);
}
intval = simple_strtoul(intarr, NULL, 10);
intval = intval * mulconst;
return intval + decval;
}
static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int i;
char *p_cf = NULL;
char *p_cf_sysclk = NULL;
char *p_cf_corepll = NULL;
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
int unknown_param = 0;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
pixis_reset();
/* not reached */
}
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "cf") == 0) {
p_cf = argv[i];
if (i + 3 >= argc) {
break;
}
p_cf_sysclk = argv[i+1];
p_cf_corepll = argv[i+2];
p_cf_mpxpll = argv[i+3];
i += 3;
continue;
}
if (strcmp(argv[i], "altbank") == 0) {
p_altbank = argv[i];
continue;
}
if (strcmp(argv[i], "wd") == 0) {
p_wd = argv[i];
continue;
}
unknown_param = 1;
}
/*
* Check that cf has all required parms
*/
if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
|| unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
#endif
return 1;
}
/*
* PIXIS seems to be sensitive to the ordering of
* the registers that are touched.
*/
read_from_px_regs(0);
if (p_altbank)
read_from_px_regs_altbank(0);
clear_altbank();
/*
* Clock configuration specified.
*/
if (p_cf) {
unsigned long sysclk;
unsigned long corepll;
unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
corepll = strfractoint(p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk)
&& set_px_corepll(corepll)
&& set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
#endif
return 1;
}
read_from_px_regs(1);
}
/*
* Altbank specified
*
* NOTE CHANGE IN BEHAVIOR: previous code would default
* to enabling watchdog if altbank is specified.
* Now the watchdog must be enabled explicitly using 'wd'.
*/
if (p_altbank) {
set_altbank();
read_from_px_regs_altbank(1);
}
/*
* Reset with watchdog specified.
*/
if (p_wd)
set_px_go_with_watchdog();
else
set_px_go();
/*
* Shouldn't be reached.
*/
return 0;
}
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"Reset the board using the FPGA sequencer",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
);

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/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PIXIS_H_
#define __PIXIS_H_ 1
/* PIXIS register set. */
#if defined(CONFIG_MPC8536DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 rst2;
u8 aux1;
u8 spd;
u8 aux2;
u8 csr2;
u8 watch;
u8 led;
u8 pwr;
u8 res[3];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[3];
u8 sclk[3];
u8 dclk[3];
u8 i2cdacr;
u8 vcoreacc[4];
u8 vcorecnt[3];
u8 vcoremax[2];
u8 vplatacc[4];
u8 vplatcnt[3];
u8 vplatmax[2];
u8 vtempacc[4];
u8 vtempcnt[3];
u8 vtempmax[2];
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8544DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux1;
u8 spd;
u8 res[8];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 vclkh;
u8 vclkl;
u8 watch;
u8 led;
u8 vspeed2;
u8 res2[34];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8572DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr1;
u8 aux1;
u8 spd;
u8 aux2;
u8 res[7];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[3];
u8 res2[2];
u8 sclk[3];
u8 dclk[3];
u8 res3[2];
u8 watch;
u8 led;
u8 res4[25];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8610HPCD)
typedef struct pixis {
u8 id;
u8 ver; /* also called arch */
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux;
u8 spd;
u8 brdcfg0;
u8 brdcfg1;
u8 res[4];
u8 led;
u8 serno;
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 res2;
u8 sclk[3];
u8 res3;
u8 watch;
u8 res4[33];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8641HPCN)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux;
u8 spd;
u8 res[8];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 vclkh;
u8 vclkl;
u8 watch;
u8 res3[36];
} __attribute__ ((packed)) pixis_t;
#else
#error Need to define pixis_t for this board
#endif
/* Pointer to the PIXIS register set */
#define pixis ((pixis_t *)PIXIS_BASE)
#endif /* __PIXIS_H_ */

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/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Tony Li <tony.li@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "pq-mds-pib.h"
int pib_init(void)
{
u8 val8;
u8 orig_i2c_bus;
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
/* Assign PIB PMC slot to desired PCI bus */
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(CONFIG_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
eieio();
#if defined(CONFIG_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x20, 0x2, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x20, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x21, 0x6, 1, &val8, 1);
i2c_write(0x21, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x21, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC1\n");
#endif
#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
}

9
common/package/utils/sysupgrade-helper/src/board/freescale/common/pq-mds-pib.h Normal file
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/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*/
extern int pib_init(void);

151
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/*
* Copyright 2011 Freescale Semiconductor
* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the QIXIS of some Freescale reference boards.
*
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "qixis.h"
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
return in_8(p + reg);
}
void qixis_write(unsigned int reg, u8 value)
{
void *p = (void *)QIXIS_BASE;
out_8(p + reg, value);
}
void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, 0x83);
}
void qixis_bank_reset(void)
{
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
}
/* Set the boot bank to the power-on default bank0 */
void clear_altbank(void)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
reg = reg & ~QIXIS_LBMAP_MASK;
QIXIS_WRITE(brdcfg[0], reg);
}
/* Set the boot bank to the alternate bank */
void set_altbank(void)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
QIXIS_WRITE(brdcfg[0], reg);
}
#ifdef DEBUG
static void qixis_dump_regs(void)
{
int i;
printf("id = %02x\n", QIXIS_READ(id));
printf("arch = %02x\n", QIXIS_READ(arch));
printf("scver = %02x\n", QIXIS_READ(scver));
printf("model = %02x\n", QIXIS_READ(model));
printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
printf("aux = %02x\n", QIXIS_READ(aux));
for (i = 0; i < 16; i++)
printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
for (i = 0; i < 16; i++)
printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
printf("aux = %02x\n", QIXIS_READ(aux));
printf("watch = %02x\n", QIXIS_READ(watch));
printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
printf("present = %02x\n", QIXIS_READ(present));
printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
}
#endif
int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
if (argc <= 1) {
clear_altbank();
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
set_altbank();
qixis_bank_reset();
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
"1min", "2min", "4min", "8min"};
u8 rcfg = QIXIS_READ(rcfg_ctl);
if (argv[2] == NULL) {
printf("qixis watchdog <watchdog_period>\n");
return 0;
}
for (i = 0; i < ARRAY_SIZE(period); i++) {
if (strcmp(argv[2], period[i]) == 0) {
/* disable watchdog */
QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
QIXIS_WRITE(watch, ((i<<2) - 1));
QIXIS_WRITE(rcfg_ctl, rcfg);
return 0;
}
}
}
#ifdef DEBUG
else if (strcmp(argv[1], "dump") == 0) {
qixis_dump_regs();
return 0;
}
#endif
else {
printf("Invalid option: %s\n", argv[1]);
return 1;
}
return 0;
}
U_BOOT_CMD(
qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
"Reset the board using the FPGA sequencer",
"- hard reset to default bank\n"
"qixis_reset altbank - reset to alternate bank\n"
"qixis watchdog <watchdog_period> - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
#ifdef DEBUG
"qixis_reset dump - display the QIXIS registers\n"
#endif
);

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/*
* Copyright 2011 Freescale Semiconductor
* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the QIXIS of some Freescale reference boards.
*/
#ifndef __QIXIS_H_
#define __QIXIS_H_
struct qixis {
u8 id; /* ID value uniquely identifying each QDS board type */
u8 arch; /* Board version information */
u8 scver; /* QIXIS Version Register */
u8 model; /* Information of software programming model version */
u8 tagdata;
u8 ctl_sys;
u8 aux; /* Auxiliary Register,0x06 */
u8 clk_spd;
u8 stat_dut;
u8 stat_sys;
u8 stat_alrm;
u8 present;
u8 ctl_sys2;
u8 rcw_ctl;
u8 ctl_led;
u8 i2cblk;
u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
u8 rcfg_st;
u8 dcm_ad;
u8 dcm_da;
u8 dcmd;
u8 dmsg;
u8 gdc;
u8 gdd; /* DCM Debug Data Register,0x17 */
u8 dmack;
u8 res1[6];
u8 watch; /* Watchdog Register,0x1F */
u8 pwr_ctl[2]; /* Power Control Register,0x20 */
u8 res2[2];
u8 pwr_stat[4]; /* Power Status Register,0x24 */
u8 res3[8];
u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
u8 res4[2];
u8 sclk[3]; /* Clock Configuration Registers,0x34 */
u8 res5;
u8 dclk[3];
u8 res6;
u8 clk_dspd[3];
u8 res7;
u8 rst_ctl; /* Reset Control Register,0x40 */
u8 rst_stat; /* Reset Status Register */
u8 rst_rsn; /* Reset Reason Register */
u8 rst_frc[2]; /* Reset Force Registers,0x43 */
u8 res8[11];
u8 brdcfg[16]; /* Board Configuration Register,0x50 */
u8 dutcfg[16];
u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
u8 rcw_data;
u8 res9[5];
u8 post_ctl;
u8 post_stat;
u8 post_dat[2];
u8 pi_d[4];
u8 gpio_io[4];
u8 gpio_dir[4];
u8 res10[20];
u8 rjtag_ctl;
u8 rjtag_dat;
u8 res11[2];
u8 trig_src[4];
u8 trig_dst[4];
u8 trig_stat;
u8 res12[3];
u8 trig_ctr[4];
u8 res13[48];
u8 aux2[4]; /* Auxiliary Registers,0xE0 */
u8 res14[10];
u8 aux_ad;
u8 aux_da;
u8 res15[16];
};
#define QIXIS_BASE 0xffdf0000
#define QIXIS_LBMAP_SWITCH 7
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_ALTBANK 0x04
u8 qixis_read(unsigned int reg);
void qixis_write(unsigned int reg, u8 value);
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
#endif

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common/package/utils/sysupgrade-helper/src/board/freescale/common/sdhc_boot.c Normal file
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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mmc.h>
#include <malloc.h>
/*
* The environment variables are written to just after the u-boot image
* on SDCard, so we must read the MBR to get the start address and code
* length of the u-boot image, then calculate the address of the env.
*/
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
blklen = mmc->read_bl_len;
tmp_buf = malloc(blklen);
if (!tmp_buf)
return 1;
/* read out the first block, get the config data information */
n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
}
/* Get the Source Address, from offset 0x50 */
code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
*env_addr = code_offset + code_len;
free(tmp_buf);
return 0;
}

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common/package/utils/sysupgrade-helper/src/board/freescale/common/sgmii_riser.c Normal file
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/*
* Freescale SGMII Riser Card
*
* This driver supports the SGMII Riser card found on the
* "DS" style of development board from Freescale.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <libfdt.h>
#include <tsec.h>
void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
{
int i;
for (i = 0; i < num; i++)
if (tsec_info[i].flags & TSEC_SGMII)
tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
}
void fsl_sgmii_riser_fdt_fixup(void *fdt)
{
struct eth_device *dev;
int node;
int i = -1;
int etsec_num = 0;
node = fdt_path_offset(fdt, "/aliases");
if (node < 0)
return;
while ((dev = eth_get_dev_by_index(++i)) != NULL) {
struct tsec_private *priv;
int enet_node;
char enet[16];
const u32 *phyh;
int phynode;
const char *model;
const char *path;
if (!strstr(dev->name, "eTSEC"))
continue;
sprintf(enet, "ethernet%d", etsec_num++);
path = fdt_getprop(fdt, node, enet, NULL);
if (!path) {
debug("No alias for %s\n", enet);
continue;
}
enet_node = fdt_path_offset(fdt, path);
if (enet_node < 0)
continue;
model = fdt_getprop(fdt, enet_node, "model", NULL);
/*
* We only want to do this to eTSECs. On some platforms
* there are more than one type of gianfar-style ethernet
* controller, and as we are creating an implicit connection
* between ethernet nodes and eTSEC devices, it is best to
* make the connection use as much explicit information
* as exists.
*/
if (!strstr(model, "TSEC"))
continue;
phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
if (!phyh)
continue;
phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
priv = dev->priv;
if (priv->flags & TSEC_SGMII)
fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
}
}

16
common/package/utils/sysupgrade-helper/src/board/freescale/common/sgmii_riser.h Normal file
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/*
* Freescale SGMII Riser Card
*
* This driver supports the SGMII Riser card found on the
* "DS" style of development board from Freescale.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
*/
void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
void fsl_sgmii_riser_fdt_fixup(void *fdt);

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common/package/utils/sysupgrade-helper/src/board/freescale/common/sys_eeprom.c Normal file
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/*
* Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
* York Sun (yorksun@freescale.com)
* Haiying Wang (haiying.wang@freescale.com)
* Timur Tabi (timur@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <linux/ctype.h>
#ifdef CONFIG_SYS_I2C_EEPROM_CCID
#include "../common/eeprom.h"
#define MAX_NUM_PORTS 8
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
#define MAX_NUM_PORTS 23
#define NXID_VERSION 1
#endif
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
* See application note AN3638 for details.
*/
static struct __attribute__ ((__packed__)) eeprom {
#ifdef CONFIG_SYS_I2C_EEPROM_CCID
u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */
u8 major; /* 0x04 Board revision, major */
u8 minor; /* 0x05 Board revision, minor */
u8 sn[10]; /* 0x06 - 0x0F Serial Number*/
u8 errata[2]; /* 0x10 - 0x11 Errata Level */
u8 date[6]; /* 0x12 - 0x17 Build Date */
u8 res_0[40]; /* 0x18 - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72 CRC32 checksum */
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
u8 sn[12]; /* 0x04 - 0x0F Serial Number */
u8 errata[5]; /* 0x10 - 0x14 Errata Level */
u8 date[6]; /* 0x15 - 0x1a Build Date */
u8 res_0; /* 0x1b Reserved */
u32 version; /* 0x1c - 0x1f NXID Version */
u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */
u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
u8 tempcalflags; /* 0x2a Temperature Calibration Flags */
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
u32 crc; /* x+1 CRC32 checksum */
#endif
} e;
/* Set to 1 if we've read EEPROM into memory */
static int has_been_read = 0;
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/* Is this a valid NXID EEPROM? */
#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
(e.id[2] == 'I') || (e.id[3] == 'D'))
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_CCID
/* Is this a valid CCID EEPROM? */
#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \
(e.id[2] == 'I') || (e.id[3] == 'D'))
#endif
/**
* show_eeprom - display the contents of the EEPROM
*/
static void show_eeprom(void)
{
int i;
unsigned int crc;
/* EEPROM tag ID, either CCID or NXID */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
be32_to_cpu(e.version));
#else
printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
/* Serial number */
printf("SN: %s\n", e.sn);
/* Errata level. */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("Errata: %s\n", e.errata);
#else
printf("Errata: %c%c\n",
e.errata[0] ? e.errata[0] : '.',
e.errata[1] ? e.errata[1] : '.');
#endif
/* Build date, BCD date values, as YYMMDDhhmmss */
printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
e.date[0], e.date[1], e.date[2],
e.date[3] & 0x7F, e.date[4], e.date[5],
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
u8 *p = e.mac[i];
printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
p[0], p[1], p[2], p[3], p[4], p[5]);
}
crc = crc32(0, (void *)&e, sizeof(e) - 4);
if (crc == be32_to_cpu(e.crc))
printf("CRC: %08x\n", be32_to_cpu(e.crc));
else
printf("CRC: %08x (should be %08x)\n",
be32_to_cpu(e.crc), crc);
#ifdef DEBUG
printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
for (i = 0; i < sizeof(e); i++) {
if ((i % 16) == 0)
printf("%02X: ", i);
printf("%02X ", ((u8 *)&e)[i]);
if (((i % 16) == 15) || (i == sizeof(e) - 1))
printf("\n");
}
#endif
}
/**
* read_eeprom - read the EEPROM into memory
*/
static int read_eeprom(void)
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
if (has_been_read)
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
#ifdef DEBUG
show_eeprom();
#endif
has_been_read = (ret == 0) ? 1 : 0;
return ret;
}
/**
* update_crc - update the CRC
*
* This function should be called after each update to the EEPROM structure,
* to make sure the CRC is always correct.
*/
static void update_crc(void)
{
u32 crc;
crc = crc32(0, (void *)&e, sizeof(e) - 4);
e.crc = cpu_to_be32(crc);
}
/**
* prog_eeprom - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret = 0;
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
/* Set the reserved values to 0xFF */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
e.res_0 = 0xFF;
memset(e.res_1, 0xFF, sizeof(e.res_1));
#else
memset(e.res_0, 0xFF, sizeof(e.res_0));
#endif
update_crc();
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
/*
* The AT24C02 datasheet says that data can only be written in page
* mode, which means 8 bytes at a time, and it takes up to 5ms to
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
}
if (!ret) {
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
has_been_read = 0;
return -1;
}
printf("Programming passed.\n");
return 0;
}
/**
* h2i - converts hex character into a number
*
* This function takes a hexadecimal character (e.g. '7' or 'C') and returns
* the integer equivalent.
*/
static inline u8 h2i(char p)
{
if ((p >= '0') && (p <= '9'))
return p - '0';
if ((p >= 'A') && (p <= 'F'))
return (p - 'A') + 10;
if ((p >= 'a') && (p <= 'f'))
return (p - 'a') + 10;
return 0;
}
/**
* set_date - stores the build date into the EEPROM
*
* This function takes a pointer to a string in the format "YYMMDDhhmmss"
* (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
* and stores it in the build date field of the EEPROM local copy.
*/
static void set_date(const char *string)
{
unsigned int i;
if (strlen(string) != 12) {
printf("Usage: mac date YYMMDDhhmmss\n");
return;
}
for (i = 0; i < 6; i++)
e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
update_crc();
}
/**
* set_mac_address - stores a MAC address into the EEPROM
*
* This function takes a pointer to MAC address string
* (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
* stores it in one of the MAC address fields of the EEPROM local copy.
*/
static void set_mac_address(unsigned int index, const char *string)
{
char *p = (char *) string;
unsigned int i;
if ((index >= MAX_NUM_PORTS) || !string) {
printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
return;
}
for (i = 0; *p && (i < 6); i++) {
e.mac[index][i] = simple_strtoul(p, &p, 16);
if (*p == ':')
p++;
}
update_crc();
}
int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char cmd;
if (argc == 1) {
show_eeprom();
return 0;
}
cmd = argv[1][0];
if (cmd == 'r') {
read_eeprom();
return 0;
}
if (cmd == 'i') {
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memcpy(e.id, "NXID", sizeof(e.id));
e.version = NXID_VERSION;
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
update_crc();
return 0;
}
if (!is_valid) {
printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
return 0;
}
if (argc == 2) {
switch (cmd) {
case 's': /* save */
prog_eeprom();
break;
default:
return cmd_usage(cmdtp);
}
return 0;
}
/* We know we have at least one parameter */
switch (cmd) {
case 'n': /* serial number */
memset(e.sn, 0, sizeof(e.sn));
strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
update_crc();
break;
case 'e': /* errata */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memset(e.errata, 0, 5);
strncpy((char *)e.errata, argv[2], 4);
#else
e.errata[0] = argv[2][0];
e.errata[1] = argv[2][1];
#endif
update_crc();
break;
case 'd': /* date BCD format YYMMDDhhmmss */
set_date(argv[2]);
break;
case 'p': /* MAC table size */
e.mac_count = simple_strtoul(argv[2], NULL, 16);
update_crc();
break;
case '0' ... '9': /* "mac 0" through "mac 22" */
set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
break;
case 'h': /* help */
default:
return cmd_usage(cmdtp);
}
return 0;
}
/**
* mac_read_from_eeprom - read the MAC addresses from EEPROM
*
* This function reads the MAC addresses from EEPROM and sets the
* appropriate environment variables for each one read.
*
* The environment variables are only set if they haven't been set already.
* This ensures that any user-saved variables are never overwritten.
*
* This function must be called after relocation.
*
* For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
* format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is
* located at a different offset.
*/
int mac_read_from_eeprom(void)
{
unsigned int i;
u32 crc, crc_offset = offsetof(struct eeprom, crc);
u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
puts("EEPROM: ");
if (read_eeprom()) {
printf("Read failed.\n");
return -1;
}
if (!is_valid) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.id[0], e.id[1], e.id[2], e.id[3]);
return -1;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/*
* If we've read an NXID v0 EEPROM, then we need to set the CRC offset
* to where it is in v0.
*/
if (e.version == 0)
crc_offset = 0x72;
#endif
crc = crc32(0, (void *)&e, crc_offset);
crcp = (void *)&e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
return -1;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/*
* MAC address #9 in v1 occupies the same position as the CRC in v0.
* Erase it so that it's not mistaken for a MAC address. We'll
* update the CRC later.
*/
if (e.version == 0)
memset(e.mac[8], 0xff, 6);
#endif
for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
char enetvar[9];
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
e.mac[i][0],
e.mac[i][1],
e.mac[i][2],
e.mac[i][3],
e.mac[i][4],
e.mac[i][5]);
sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
/* Only initialize environment variables that are blank
* (i.e. have not yet been set)
*/
if (!getenv(enetvar))
setenv(enetvar, ethaddr);
}
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
be32_to_cpu(e.version));
#else
printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/*
* Now we need to upconvert the data into v1 format. We do this last so
* that at boot time, U-Boot will still say "NXID v0".
*/
if (e.version == 0) {
e.version = NXID_VERSION;
update_crc();
}
#endif
return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_CCID
/**
* get_cpu_board_revision - get the CPU board revision on 85xx boards
*
* Read the EEPROM to determine the board revision.
*
* This function is called before relocation, so we need to read a private
* copy of the EEPROM into a local variable on the stack.
*
* Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global
* variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
* so that the SPD code will work. This means that all pre-relocation I2C
* operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if
* CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
* this function is called. Oh well.
*/
unsigned int get_cpu_board_revision(void)
{
struct board_eeprom {
u32 id; /* 0x00 - 0x03 EEPROM Tag 'CCID' */
u8 major; /* 0x04 Board revision, major */
u8 minor; /* 0x05 Board revision, minor */
} be;
i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
return MPC85XX_CPU_BOARD_REV(0, 0);
if ((be.major == 0xff) && (be.minor == 0xff))
return MPC85XX_CPU_BOARD_REV(0, 0);
return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
}
#endif

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#ifndef _MPC85xx_VIA_H
void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
/* Function 1, IDE */
void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
/* Function 2, USB ports 0-1 */
void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
/* Function 3, USB ports 2-3 */
void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
/* Function 5, Power Management */
void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
/* Function 6, AC97 Interface */
void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
#endif /* _MPC85xx_VIA_H */

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common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/Makefile Normal file
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#
# Copyright 2007-2009 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-$(CONFIG_P3041DS) += eth_hydra.o
COBJS-$(CONFIG_P4080DS) += eth_p4080.o
COBJS-$(CONFIG_P5020DS) += eth_hydra.o
COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o
COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

241
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/corenet_ds.c Normal file
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/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/ngpixis.h"
#include "corenet_ds.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
u8 sw;
struct cpu_type *cpu = gd->cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %sDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("Promjet\n");
else if (sw == 0x9)
puts("NAND\n");
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
u32 rcw = in_be32(&gur->rcwsr[i]);
if ((i % 4) == 0)
printf("\n %08x:", i * 4);
printf(" %08x", rcw);
}
puts("\n");
/* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
* values that the SERDES expects (or vice versa). For now, however,
* we just display both values and hope the user notices when they
* don't match.
*/
puts("SERDES Reference Clocks: ");
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
static const char *freq[] = {"100", "125", "156.25", "212.5" };
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
puts("\n");
#else
sw = in_8(&PIXIS_SW(3));
printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
#endif
return 0;
}
int board_early_init_f(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/*
* P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
* disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
* the noise introduced by these unterminated and unused clock pairs.
*/
setbits_be32(&gur->ddrclkdr, 0x001B001B);
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
return 0;
}
static const char *serdes_clock_to_string(u32 clock)
{
switch(clock) {
case SRDS_PLLCR0_RFCK_SEL_100:
return "100";
case SRDS_PLLCR0_RFCK_SEL_125:
return "125";
case SRDS_PLLCR0_RFCK_SEL_156_25:
return "156.25";
default:
return "150";
}
}
#define NUM_SRDS_BANKS 3
int misc_init_r(void)
{
serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
break;
case 1:
actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
break;
case 2:
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
break;
default:
printf("Warning: SDREFCLK%u switch setting of '11' is "
"unsupported\n", i + 1);
break;
}
}
#else
/* Warn if the expected SERDES reference clocks don't match the
* actual reference clocks. This needs to be done after calling
* p4080_erratum_serdes8(), since that function may modify the clocks.
*/
sw = in_8(&PIXIS_SW(3));
actual[0] = (sw & 0x40) ?
SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
actual[1] = (sw & 0x20) ?
SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
actual[2] = (sw & 0x10) ?
SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
#endif
for (i = 0; i < NUM_SRDS_BANKS; i++) {
u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
printf("Warning: SERDES bank %u expects reference clock"
" %sMHz, but actual is %sMHz\n", i + 1,
serdes_clock_to_string(expected),
serdes_clock_to_string(actual[i]));
}
}
return 0;
}
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
}

26
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/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#endif

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common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/ddr.c Normal file
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/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
extern fixed_ddr_parm_t fixed_ddr_parm_1[];
#endif
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
unsigned int lawbar1_target_id;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
#endif
/*
* setup laws for DDR. If not interleaving, presuming half memory on
* DDR1 and the other half on DDR2
*/
if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
LAW_TRGT_IF_DDR_INTRLV) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
} else {
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
/* We require both controllers have identical DIMMs */
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size / 2,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
lawbar1_target_id = LAW_TRGT_IF_DDR_2;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
ddr_size / 2,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
#else
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
#endif
}
return ddr_size;
}
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 5, 6, 0xff, 2, 0},
{2, 1050, 5, 7, 0xff, 2, 0},
{2, 1250, 4, 6, 0xff, 2, 0},
{2, 1350, 5, 7, 0xff, 2, 0},
{2, 1666, 5, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
/*
* The two slots have slightly different timing. The center values are good
* for both slots. We use identical speed tables for them. In future use, if
* DIMMs have fewer center values that require two separated tables, copy the
* udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
*/
static const struct board_specific_parameters *udimms[] = {
udimm0,
udimm0,
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 4, 6, 0xff, 2, 0},
{2, 1050, 4, 7, 0xff, 2, 0},
{2, 1666, 4, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
/*
* The two slots have slightly different timing. See comments above.
*/
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
rdimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 1) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
if (popts->registered_dimm_en)
pbsp = rdimms[ctrl_num];
else
pbsp = udimms[ctrl_num];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->twoT_en = pbsp->force_2T;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->twoT_en = pbsp_highest->force_2T;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 60 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....");
if (fsl_use_spd()) {
puts("using SPD\n");
dram_size = fsl_ddr_sdram();
} else {
puts("using fixed parameters\n");
dram_size = fixed_sdram();
}
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
debug(" DDR: ");
return dram_size;
}

527
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/eth_hydra.c Normal file
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@ -0,0 +1,527 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Author: Timur Tabi <timur@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file handles the board muxing between the Fman Ethernet MACs and
* the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
* board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
* provided by the standard Freescale four-port SGMII riser card. The 10Gb
* XGMII PHY is provided via the XAUI riser card. Since there is only one
* Fman device on a P3041 and P5020, we only support one SGMII card and one
* RGMII card.
*
* Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
* muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
* always the same (0). The value for SGMII depends on which slot the riser is
* inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
* the value is based on which slot the XAUI is inserted in.
*
* The SERDES configuration is used to determine where the SGMII and XAUI cards
* exist, and also which Fman MACs are routed to which PHYs. So for a given
* Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
* to PHYs dynamically.
*
*
* This file also updates the device tree in three ways:
*
* 1) The status of each virtual MDIO node that is referenced by an Ethernet
* node is set to "okay".
*
* 2) The phy-handle property of each active Ethernet MAC node is set to the
* appropriate PHY node.
*
* 3) The "mux value" for each virtual MDIO node is set to the correct value,
* if necessary. Some virtual MDIO nodes do not have configurable mux
* values, so those values are hard-coded in the DTS. On the HYDRA board,
* the virtual MDIO node for the SGMII card needs to be updated.
*
* For all this to work, the device tree needs to have the following:
*
* 1) An alias for each PHY node that an Ethernet node could be routed to.
*
* 2) An alias for each real and virtual MDIO node that is disabled by default
* and might need to be enabled, and also might need to have its mux-value
* updated.
*/
#include <common.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
#include <asm/fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#ifdef CONFIG_FMAN_ENET
#define BRDCFG1_EMI1_SEL_MASK 0x70
#define BRDCFG1_EMI1_SEL_SLOT1 0x10
#define BRDCFG1_EMI1_SEL_SLOT2 0x20
#define BRDCFG1_EMI1_SEL_SLOT5 0x30
#define BRDCFG1_EMI1_SEL_SLOT6 0x40
#define BRDCFG1_EMI1_SEL_SLOT7 0x50
#define BRDCFG1_EMI1_SEL_RGMII 0x00
#define BRDCFG1_EMI1_EN 0x08
#define BRDCFG1_EMI2_SEL_MASK 0x06
#define BRDCFG1_EMI2_SEL_SLOT1 0x00
#define BRDCFG1_EMI2_SEL_SLOT2 0x02
#define BRDCFG2_REG_GPIO_SEL 0x20
/*
* BRDCFG1 mask and value for each MAC
*
* This array contains the BRDCFG1 values (in mask/val format) that route the
* MDIO bus to a particular RGMII or SGMII PHY.
*/
struct {
u8 mask;
u8 val;
} mdio_mux[NUM_FM_PORTS];
/*
* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
* that the mapping must be determined dynamically, or that the lane maps to
* something other than a board slot
*/
static u8 lane_to_slot[] = {
7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
};
/*
* Set the board muxing for a given MAC
*
* The MDIO layer calls this function every time it wants to talk to a PHY.
*/
void hydra_mux_mdio(u8 mask, u8 val)
{
clrsetbits_8(&pixis->brdcfg1, mask, val);
}
struct hydra_mdio {
u8 mask;
u8 val;
struct mii_dev *realbus;
};
static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct hydra_mdio *priv = bus->priv;
hydra_mux_mdio(priv->mask, priv->val);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct hydra_mdio *priv = bus->priv;
hydra_mux_mdio(priv->mask, priv->val);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int hydra_mdio_reset(struct mii_dev *bus)
{
struct hydra_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
{
struct mii_dev *bus = miiphy_get_dev_by_name(name);
struct hydra_mdio *priv = bus->priv;
priv->mask = mask;
priv->val = val;
}
static int hydra_mdio_init(char *realbusname, char *fakebusname)
{
struct hydra_mdio *hmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate Hydra MDIO bus\n");
return -1;
}
hmdio = malloc(sizeof(*hmdio));
if (!hmdio) {
printf("Failed to allocate Hydra private data\n");
free(bus);
return -1;
}
bus->read = hydra_mdio_read;
bus->write = hydra_mdio_write;
bus->reset = hydra_mdio_reset;
sprintf(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!hmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(hmdio);
return -1;
}
bus->priv = hmdio;
return mdio_register(bus);
}
/*
* Given an alias or a path for a node, set the mux value of that node.
*
* If 'alias' is not a valid alias, then it is treated as a full path to the
* node. No error checking is performed.
*
* This function is normally called to set the fsl,hydra-mdio-muxval property
* of a virtual MDIO node.
*/
static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
{
const char *path = fdt_get_alias(fdt, alias);
if (!path)
path = alias;
do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
&mux, sizeof(mux), 1);
}
/*
* Given the following ...
*
* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
* compatible string and 'addr' physical address)
*
* 2) An Fman port
*
* ... update the phy-handle property of the Ethernet node to point to the
* right PHY. This assumes that we already know the PHY for each port. That
* information is stored in mdio_mux[].
*
* The offset of the Fman Ethernet node is also passed in for convenience, but
* it is not used, and we recalculate the offset anyway.
*
* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
* Inside the Fman, "ports" are things that connect to MACs. We only call them
* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
* and ports are the same thing.
*
* Note that this code would be cleaner if had a function called
* fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
* array. That's because all we're doing is figuring out the PHY address for
* a given Fman MAC and writing it to the device tree. Well, we already did
* the hard work to figure that out in board_eth_init(), so it's silly to
* repeat that here.
*/
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
char phy[16];
if (port == FM1_10GEC1) {
/* XAUI */
int lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
/* The XAUI PHY is identified by the slot */
sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
fdt_set_phy_handle(fdt, compat, addr, phy);
}
return;
}
if (mux == BRDCFG1_EMI1_SEL_RGMII) {
/* RGMII */
/* The RGMII PHY is identified by the MAC connected to it */
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
fdt_set_phy_handle(fdt, compat, addr, phy);
}
/* If it's not RGMII or XGMII, it must be SGMII */
if (mux) {
/* The SGMII PHY is identified by the MAC connected to it */
sprintf(phy, "phy_sgmii_%x",
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
fdt_set_phy_handle(fdt, compat, addr, phy);
}
}
#define PIXIS_SW2_LANE_23_SEL 0x80
#define PIXIS_SW2_LANE_45_SEL 0x40
#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
#define PIXIS_SW2_LANE_67_SEL_5 0x00
#define PIXIS_SW2_LANE_67_SEL_6 0x20
#define PIXIS_SW2_LANE_67_SEL_7 0x10
#define PIXIS_SW2_LANE_8_SEL 0x08
#define PIXIS_SW2_LANE_1617_SEL 0x04
/*
* Initialize the lane_to_slot[] array.
*
* On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
* slots is hard-coded. On the Hydra board, however, the mapping is controlled
* by board switch SW2, so the lane_to_slot[] array needs to be dynamically
* initialized.
*/
static void initialize_lane_to_slot(void)
{
u8 sw2 = in_8(&PIXIS_SW(2));
lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
lane_to_slot[3] = lane_to_slot[2];
lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
lane_to_slot[5] = lane_to_slot[4];
switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
case PIXIS_SW2_LANE_67_SEL_5:
lane_to_slot[6] = 5;
break;
case PIXIS_SW2_LANE_67_SEL_6:
lane_to_slot[6] = 6;
break;
case PIXIS_SW2_LANE_67_SEL_7:
lane_to_slot[6] = 7;
break;
}
lane_to_slot[7] = lane_to_slot[6];
lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
lane_to_slot[17] = lane_to_slot[16];
}
#endif /* #ifdef CONFIG_FMAN_ENET */
/*
* Configure the status for the virtual MDIO nodes
*
* Rather than create the virtual MDIO nodes from scratch for each active
* virtual MDIO, we expect the DTS to have the nodes defined already, and we
* only enable the ones that are actually active.
*
* We assume that the DTS already hard-codes the status for all the
* virtual MDIO nodes to "disabled", so all we need to do is enable the
* active ones.
*
* For SGMII, we also need to set the mux value in the node.
*/
void fdt_fixup_board_enet(void *fdt)
{
#ifdef CONFIG_FMAN_ENET
unsigned int i;
int lane;
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane >= 0) {
fdt_status_okay_by_alias(fdt, "emi1_sgmii");
/* Also set the MUX value */
fdt_set_mdio_mux(fdt, "emi1_sgmii",
mdio_mux[i].val);
}
break;
case PHY_INTERFACE_MODE_RGMII:
fdt_status_okay_by_alias(fdt, "emi1_rgmii");
break;
default:
break;
}
}
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0)
fdt_status_okay_by_alias(fdt, "emi2_xgmii");
#endif
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
printf("Initializing Fman\n");
initialize_lane_to_slot();
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
memset(mdio_mux, 0, sizeof(mdio_mux));
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the three virtual MDIO front-ends */
hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
/*
* Program the DTSEC PHY addresses assuming that they are all SGMII.
* For any DTSEC that's RGMII, we'll override its PHY address later.
* We assume that DTSEC5 is only used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
switch (slot) {
case 1:
/* Always DTSEC5 on Bank 3 */
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* If DTSEC4 is RGMII, then it's routed via via EC1 to
* the first on-board RGMII port. If DTSEC5 is RGMII,
* then it's routed via via EC2 to the second on-board
* RGMII port. The other DTSECs cannot be routed to
* RGMII.
*/
fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
slot = lane_to_slot[lane];
if (slot == 1) {
/* XAUI card is in slot 1 */
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
BRDCFG1_EMI2_SEL_SLOT1);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
} else {
/* XAUI card is in slot 2 */
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
BRDCFG1_EMI2_SEL_SLOT2);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
}
}
fm_info_set_mdio(FM1_10GEC1,
miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}

506
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/eth_p4080.c Normal file
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/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#include <asm/fsl_dtsec.h>
#define EMI_NONE 0xffffffff
#define EMI_MASK 0xf0000000
#define EMI1_RGMII 0x0
#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
#define EMI1_MASK 0xc0000000
#define EMI2_MASK 0x30000000
static int mdio_mux[NUM_FM_PORTS];
static char *mdio_names[16] = {
"P4080DS_MDIO0",
"P4080DS_MDIO1",
NULL,
"P4080DS_MDIO3",
"P4080DS_MDIO4",
NULL, NULL, NULL,
"P4080DS_MDIO8",
NULL, NULL, NULL,
"P4080DS_MDIO12",
NULL, NULL, NULL,
};
static char *p4080ds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[(muxval & EMI_MASK) >> 28];
}
struct mii_dev *mii_dev_for_muxval(u32 muxval)
{
struct mii_dev *bus;
char *name = p4080ds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
if (phydev->drv->uid == PHY_UID_TN2020) {
unsigned long timeout = 1 * 1000; /* 1 seconds */
enum srds_prtcl device;
/*
* Wait for the XAUI to come out of reset. This is when it
* starts transmitting alignment signals.
*/
while (--timeout) {
int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
if (reg < 0) {
printf("TN2020: Error reading from PHY at "
"address %u\n", phydev->addr);
break;
}
/*
* Note that we've never actually seen
* MDIO_CTRL1_RESET set to 1.
*/
if ((reg & MDIO_CTRL1_RESET) == 0)
break;
udelay(1000);
}
if (!timeout) {
printf("TN2020: Timeout waiting for PHY at address %u "
" to reset.\n", phydev->addr);
}
switch (phydev->addr) {
case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
device = XAUI_FM1;
break;
case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
device = XAUI_FM2;
break;
default:
device = NONE;
}
serdes_reset_rx(device);
}
return 0;
}
#endif
struct p4080ds_mdio {
u32 muxval;
struct mii_dev *realbus;
};
static void p4080ds_mux_mdio(u32 muxval)
{
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
gpioval |= muxval;
out_be32(&pgpio->gpdat, gpioval);
}
static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct p4080ds_mdio *priv = bus->priv;
p4080ds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct p4080ds_mdio *priv = bus->priv;
p4080ds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int p4080ds_mdio_reset(struct mii_dev *bus)
{
struct p4080ds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int p4080ds_mdio_init(char *realbusname, u32 muxval)
{
struct p4080ds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate P4080DS MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate P4080DS private data\n");
free(bus);
return -1;
}
bus->read = p4080ds_mdio_read;
bus->write = p4080ds_mdio_write;
bus->reset = p4080ds_mdio_reset;
sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
if (mdio_mux[port] == EMI1_RGMII)
fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
if (mdio_mux[port] == EMI1_SLOT3) {
int idx = port - FM2_DTSEC1 + 5;
char phy[16];
sprintf(phy, "phy%d_slot3", idx);
fdt_set_phy_handle(blob, prop, pa, phy);
}
}
void fdt_fixup_board_enet(void *fdt)
{
int i;
/*
* P4080DS can be configured in many different ways, supporting a number
* of combinations of ethernet devices and phy types. In order to
* have just one device tree for all of those configurations, we fix up
* the tree here. By default, the device tree configures FM1 and FM2
* for SGMII, and configures XAUI on both 10G interfaces. So we have
* a number of different variables to track:
*
* 1) Whether the device is configured at all. Whichever devices are
* not enabled should be disabled by setting the "status" property
* to "disabled".
* 2) What the PHY interface is. If this is an RGMII connection,
* we should change the "phy-connection-type" property to
* "rgmii"
* 3) Which PHY is being used. Because the MDIO buses are muxed,
* we need to redirect the "phy-handle" property to point at the
* PHY on the right slot/bus.
*/
/* We've got six MDIO nodes that may or may not need to exist */
fdt_status_disabled_by_alias(fdt, "emi1_slot3");
fdt_status_disabled_by_alias(fdt, "emi1_slot4");
fdt_status_disabled_by_alias(fdt, "emi1_slot5");
fdt_status_disabled_by_alias(fdt, "emi2_slot4");
fdt_status_disabled_by_alias(fdt, "emi2_slot5");
for (i = 0; i < NUM_FM_PORTS; i++) {
switch (mdio_mux[i]) {
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt, "emi1_slot3");
break;
case EMI1_SLOT4:
fdt_status_okay_by_alias(fdt, "emi1_slot4");
break;
case EMI1_SLOT5:
fdt_status_okay_by_alias(fdt, "emi1_slot5");
break;
case EMI2_SLOT4:
fdt_status_okay_by_alias(fdt, "emi2_slot4");
break;
case EMI2_SLOT5:
fdt_status_okay_by_alias(fdt, "emi2_slot5");
break;
}
}
}
enum board_slots {
SLOT1 = 1,
SLOT2,
SLOT3,
SLOT4,
SLOT5,
SLOT6,
};
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
u8 lane_to_slot[] = {
SLOT1, /* 0 - Bank 1:A */
SLOT1, /* 1 - Bank 1:B */
SLOT2, /* 2 - Bank 1:C */
SLOT2, /* 3 - Bank 1:D */
SLOT3, /* 4 - Bank 1:E */
SLOT3, /* 5 - Bank 1:F */
SLOT3, /* 6 - Bank 1:G */
SLOT3, /* 7 - Bank 1:H */
SLOT6, /* 8 - Bank 1:I */
SLOT6, /* 9 - Bank 1:J */
SLOT4, /* 10 - Bank 2:A */
SLOT4, /* 11 - Bank 2:B */
SLOT4, /* 12 - Bank 2:C */
SLOT4, /* 13 - Bank 2:D */
SLOT5, /* 14 - Bank 3:A */
SLOT5, /* 15 - Bank 3:B */
SLOT5, /* 16 - Bank 3:C */
SLOT5, /* 17 - Bank 3:D */
};
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
/* The first 4 GPIOs are outputs to control MDIO bus muxing */
out_be32(&pgpio->gpdir, EMI_MASK);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the 6 muxing front-ends to the MDIO buses */
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
#if (CONFIG_SYS_NUM_FMAN == 2)
fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
#endif
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(XAUI_FM1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
int idx = i - FM2_10GEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(XAUI_FM2 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
default:
break;
}
}
#endif
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

14
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/p3041ds_ddr.c Normal file
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@ -0,0 +1,14 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
};

350
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/p4080ds_ddr.c Normal file
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/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{850, 950, &ddr_cfg_regs_900},
{950, 1050, &ddr_cfg_regs_1000},
{1050, 1250, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{750, 850, &ddr_cfg_regs_800_2nd},
{850, 950, &ddr_cfg_regs_900_2nd},
{950, 1050, &ddr_cfg_regs_1000_2nd},
{1050, 1250, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};

18
common/package/utils/sysupgrade-helper/src/board/freescale/corenet_ds/p5020ds_ddr.c Normal file
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/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{0, 0, NULL}
};

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5208evbe/Makefile Normal file
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#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5208evbe/config.mk Normal file
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#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0

94
common/package/utils/sysupgrade-helper/src/board/freescale/m5208evbe/m5208evbe.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M5208EVBe\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
#endif
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
asm("nop");
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_MODE;
asm("nop");
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
asm("nop");
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

100
common/package/utils/sysupgrade-helper/src/board/freescale/m5208evbe/u-boot.lds Normal file
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m52277evb/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

27
common/package/utils/sysupgrade-helper/src/board/freescale/m52277evb/config.mk Normal file
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@ -0,0 +1,27 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)

104
common/package/utils/sysupgrade-helper/src/board/freescale/m52277evb/m52277evb.c Normal file
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@ -0,0 +1,104 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M52277 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
/*
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Issue LEMR */
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
__asm__("nop");
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
__asm__("nop");
udelay(1000);
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Perform two refresh cycles */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
udelay(100);
#endif
return (dramsize);
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m52277evb/u-boot.lds Normal file
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@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf5227x/start.o (.text*)
arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*)
arch/m68k/lib/libm68k.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5235evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
common/package/utils/sysupgrade-helper/src/board/freescale/m5235evb/config.mk Normal file
View file

@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)

120
common/package/utils/sysupgrade-helper/src/board/freescale/m5235evb/m5235evb.c Normal file
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@ -0,0 +1,120 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M5235 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
* When booting from external Flash, the port-size is less than
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
gpio->par_ad =
GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
GPIO_PAR_AD_DATAL;
/* Initialize PAR to enable SDRAM signals */
gpio->par_sdram =
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
/* Initialize DACR0 */
sdram->dacr0 =
SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
asm("nop");
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
asm("nop");
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
asm("nop");
}
/* Write to this block to initiate precharge */
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_RE;
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
asm("nop");
}
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5235evb/u-boot.lds Normal file
View file

@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf523x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5249evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5249evb/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xffe00000

109
common/package/utils/sysupgrade-helper/src/board/freescale/m5249evb/m5249evb.c Normal file
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@ -0,0 +1,109 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <asm/immap.h>
int checkboard (void) {
ulong val;
uchar val8;
puts ("Board: ");
puts("Freescale M5249EVB");
val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
printf(" (Switch=%1X)\n", val8);
/*
* Set LED on
*/
val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
};
phys_size_t initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*
* Note:
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
#ifdef CONFIG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
#elif CONFIG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
*/
mbar_writeShort(MCFSIM_DCR, 0x8202);
#else
/*
* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
*/
mbar_writeShort(MCFSIM_DCR, 0x8222);
#endif
/*
* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
* PM=1 (continuous page mode)
*/
/* RE=0 (keep auto-refresh disabled while setting up registers) */
mbar_writeLong(MCFSIM_DACR0, 0x00003324);
/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
/** Precharge sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
udelay(0x10); /* Allow several Precharge cycles */
/** Refresh Sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
udelay(0x7d0); /* Allow gobs of refresh cycles */
/** Mode Register initialization **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5249evb/u-boot.lds Normal file
View file

@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5253demo/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5253demo/config.mk Normal file
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#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xFF800000

467
common/package/utils/sysupgrade-helper/src/board/freescale/m5253demo/flash.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
#ifndef CONFIG_SYS_FLASH_CFI
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x5555
#define FLASH_CYCLE2 0x2aaa
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
* Functions
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info);
int flash_get_offsets(ulong base, flash_info_t * info);
int write_word(flash_info_t * info, FPWV * dest, u16 data);
void inline spin_wheel(void);
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
ulong flash_init(void)
{
ulong size = 0;
ulong fbase = 0;
fbase = (ulong) CONFIG_SYS_FLASH_BASE;
flash_get_size((FPWV *) fbase, &flash_info[0]);
flash_get_offsets((ulong) fbase, &flash_info[0]);
fbase += flash_info[0].size;
size += flash_info[0].size;
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
return size;
}
int flash_get_offsets(ulong base, flash_info_t * info)
{
int j, k;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
info->start[0] = base;
for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
info->protect[k] = 0;
}
}
return ERR_OK;
}
void flash_print_info(flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_SST:
printf("SST ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_SST6401B:
printf("SST39VF6401B\n");
break;
default:
printf("Unknown Chip Type\n");
return;
}
if (info->size > 0x100000) {
int remainder;
printf(" Size: %ld", info->size >> 20);
remainder = (info->size % 0x100000);
if (remainder) {
remainder >>= 10;
remainder = (int)((float)
(((float)remainder / (float)1024) *
10000));
printf(".%d ", remainder);
}
printf("MB in %d Sectors\n", info->sector_count);
} else
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size(FPWV * addr, flash_info_t * info)
{
u16 value;
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
switch (addr[0] & 0xffff) {
case (u8) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
value = addr[1];
break;
default:
printf("Unknown Flash\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
*addr = (FPW) 0x00F000F0;
return (0); /* no or unknown flash */
}
switch (value) {
case (u16) SST_ID_xF6401B:
info->flash_id += FLASH_SST6401B;
break;
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
info->sector_count = 0;
info->size = 0;
info->sector_count = CONFIG_SYS_SST_SECT;
info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
/* reset ID mode */
*addr = (FPWV) 0x00F000F0;
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
return (info->size);
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
FPWV *addr;
int flag, prot, sect, count;
ulong type, start, last;
int rcode = 0, flashtype = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
else
printf("- no sectors to erase\n");
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
switch (type) {
case FLASH_MAN_SST:
flashtype = 1;
break;
default:
type = (info->flash_id & FLASH_VENDMASK);
printf("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf("\n");
flag = disable_interrupts();
start = get_timer(0);
last = start;
if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
if (prot == 0) {
addr = (FPWV *) info->start[0];
addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
addr[FLASH_CYCLE2] = 0x0055; /* unlock */
addr[FLASH_CYCLE1] = 0x0080; /* erase mode */
addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
addr[FLASH_CYCLE2] = 0x0055; /* unlock */
*addr = 0x0030; /* erase chip */
count = 0;
start = get_timer(0);
while ((*addr & 0x0080) != 0x0080) {
if (count++ > 0x10000) {
spin_wheel();
count = 0;
}
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = 0x00F0; /* reset to read mode */
return 1;
}
}
*addr = 0x00F0; /* reset to read mode */
printf("\b. done\n");
if (flag)
enable_interrupts();
return 0;
} else if (prot == CONFIG_SYS_SST_SECT) {
return 1;
}
}
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (FPWV *) (info->start[sect]);
printf(".");
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
switch (flashtype) {
case 1:
{
FPWV *base; /* first address in bank */
flag = disable_interrupts();
base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */
base[FLASH_CYCLE1] = 0x00AA; /* unlock */
base[FLASH_CYCLE2] = 0x0055; /* unlock */
base[FLASH_CYCLE1] = 0x0080; /* erase mode */
base[FLASH_CYCLE1] = 0x00AA; /* unlock */
base[FLASH_CYCLE2] = 0x0055; /* unlock */
*addr = 0x0050; /* erase sector */
if (flag)
enable_interrupts();
while ((*addr & 0x0080) != 0x0080) {
if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = 0x00F0; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = 0x00F0; /* reset to read mode */
break;
}
} /* switch (flashtype) */
}
}
printf(" done\n");
if (flag)
enable_interrupts();
return rcode;
}
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, count;
u16 data;
int rc, port_width;
if (info->flash_id == FLASH_UNKNOWN)
return 4;
/* get lower word aligned address */
wp = addr;
port_width = sizeof(FPW);
/* handle unaligned start bytes */
if (wp & 1) {
data = *((FPWV *) wp);
data = (data << 8) | *src;
if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
return (rc);
wp++;
cnt -= 1;
src++;
}
while (cnt >= 2) {
/*
* handle word aligned part
*/
count = 0;
data = *((FPWV *) src);
if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
return (rc);
wp += 2;
src += 2;
cnt -= 2;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
/* handle word aligned part */
if (cnt) {
/* handle word aligned part */
count = 0;
data = *((FPWV *) wp);
data = (data & 0x00FF) | (*src << 8);
if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
return (rc);
wp++;
src++;
cnt -= 1;
if (count++ > 0x800) {
spin_wheel();
count = 0;
}
}
if (cnt == 0)
return ERR_OK;
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Write a word to Flash
* A word is 16 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_word(flash_info_t * info, FPWV * dest, u16 data)
{
ulong start;
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*dest & (u8) data) != (u8) data) {
return (2);
}
base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (u8) 0x00F000F0; /* reset bank */
res = 1;
}
}
*dest++ = (u8) 0x00F000F0; /* reset bank */
return (res);
}
void inline spin_wheel(void)
{
static int p = 0;
static char w[] = "\\/-";
printf("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}
#endif

153
common/package/utils/sysupgrade-helper/src/board/freescale/m5253demo/m5253demo.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
#include <netdev.h>
#include <asm/io.h>
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5253 DEMO\n");
return 0;
};
phys_size_t initdram(int board_type)
{
u32 dramsize = 0;
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, temp;
RC = (CONFIG_SYS_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
__asm__("nop");
mbar_writeLong(MCFSIM_DACR0, 0x00003224);
__asm__("nop");
/* Initialize DMR0 */
dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
mb();
__asm__("nop");
/* Write to this block to initiate precharge */
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
mb();
__asm__("nop");
/* Set RE bit in DACR */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x8000);
__asm__("nop");
/* Wait for at least 8 auto refresh cycles to occur */
udelay(500);
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
mb();
}
return dramsize;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#ifdef CONFIG_CMD_IDE
#include <ata.h>
int ide_preinit(void)
{
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
};
if (idereset) {
ata->cr = 0; /* control reset */
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(2000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif /* CONFIG_CMD_IDE */
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif

100
common/package/utils/sysupgrade-helper/src/board/freescale/m5253demo/u-boot.lds Normal file
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5253evbe/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5253evbe/config.mk Normal file
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#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xffe00000

137
common/package/utils/sysupgrade-helper/src/board/freescale/m5253evbe/m5253evbe.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5253 EVBE\n");
return 0;
};
phys_size_t initdram(int board_type)
{
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, dramsize;
RC = (CONFIG_SYS_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
asm("nop");
mbar_writeLong(MCFSIM_DACR0, 0x00002320);
asm("nop");
/* Initialize DMR0 */
dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
asm("nop");
mbar_writeLong(MCFSIM_DACR0, 0x00002328);
asm("nop");
/* Write to this block to initiate precharge */
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
asm("nop");
/* Set RE bit in DACR */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x8000);
asm("nop");
/* Wait for at least 8 auto refresh cycles to occur */
udelay(500);
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x0040);
asm("nop");
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#ifdef CONFIG_CMD_IDE
#include <ata.h>
int ide_preinit(void)
{
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
};
if (idereset) {
ata->cr = 0; /* control reset */
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(2000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif /* CONFIG_CMD_IDE */

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5253evbe/u-boot.lds Normal file
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@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5271evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5271evb/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xffe00000

131
common/package/utils/sysupgrade-helper/src/board/freescale/m5271evb/m5271evb.c Normal file
View file

@ -0,0 +1,131 @@
/*
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
int checkboard (void) {
puts ("Board: Freescale M5271EVB\n");
return 0;
};
phys_size_t initdram (int board_type) {
int i;
/* Enable Address lines 23-21 and lower 16bits of data path */
mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
MCF_GPIO_AD_DATAL);
/* Set CS2 pin to be SD_CS0 */
mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
| MCF_GPIO_PAR_CS_PAR_CS2);
/* Configure SDRAM Control Pin Assignemnt Register */
mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
MCF_GPIO_SDRAM_SDCS_11);
asm(" nop");
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCF_SDRAMC_DCR,
MCF_SDRAMC_DCR_RTIM(2)
| MCF_SDRAMC_DCR_RC(0x2E));
asm(" nop");
/*
* Initialize DACR0
*
* CASL: 01
* CBM: cmd at A20, bank select bits 21 and up
* PS: 32bit port size
*/
mbar_writeLong(MCF_SDRAMC_DACR0,
MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
| MCF_SDRAMC_DACRn_CASL(1)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(0));
asm(" nop");
/* Initialize DMR0 */
mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_16M
| MCF_SDRAMC_DMRn_V);
asm(" nop");
/* Set IP bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_IP);
asm(" nop");
/* Wait at least 20ns to allow banks to precharge */
for (i = 0; i < 5; i++)
asm(" nop");
/* Write to this block to initiate precharge */
*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
asm(" nop");
/* Set RE bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_RE);
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 2000; i++)
asm(" nop");
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_MRS);
asm(" nop");
/*
* Write to the SDRAM Mode Register A0-A11 = 0x400
*
* Write Burst Mode = Programmed Burst Length
* Op Mode = Standard Op
* CAS Latency = 2
* Burst Type = Sequential
* Burst Length = 1
*/
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
asm(" nop");
}
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5271evb/u-boot.lds Normal file
View file

@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5272c3/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5272c3/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xffe00000

51
common/package/utils/sysupgrade-helper/src/board/freescale/m5272c3/m5272c3.c Normal file
View file

@ -0,0 +1,51 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
int checkboard (void) {
puts ("Board: ");
puts ("Freescale MCF5272C3 EVB\n");
return 0;
};
phys_size_t initdram (int board_type) {
volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5272c3/u-boot.lds Normal file
View file

@ -0,0 +1,99 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5275evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5275evb/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xffe00000

112
common/package/utils/sysupgrade-helper/src/board/freescale/m5275evb/m5275evb.c Normal file
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@ -0,0 +1,112 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5275 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
/* Set up chip select */
sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
/* Set up timing */
sdp->sdcfg1 = 0x83711630;
sdp->sdcfg2 = 0x46770000;
/* Enable clock */
sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
/* Set precharge */
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
sdp->sdmr = 0x058d0000;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Write mode register, clear reset DLL */
sdp->sdmr = 0x018d0000;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
sdp->sdcr =
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3);
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

99
common/package/utils/sysupgrade-helper/src/board/freescale/m5275evb/u-boot.lds Normal file
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@ -0,0 +1,99 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5282evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5282evb/config.mk Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0xFFE00000

100
common/package/utils/sysupgrade-helper/src/board/freescale/m5282evb/m5282evb.c Normal file
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@ -0,0 +1,100 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
puts ("Board: Freescale M5282EVB Evaluation Board\n");
return 0;
}
phys_size_t initdram (int board_type)
{
u32 dramsize, i, dramclk;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
{
dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
MCFSDRAMC_DCR = (0
| MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
asm("nop");
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
asm("nop");
/* Initialize DMR0 */
MCFSDRAMC_DMR0 = (0
| ((dramsize - 1) & 0xFFFC0000)
| MCFSDRAMC_DMR_V);
asm("nop");
/* Set IP (bit 3) in DACR */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
asm("nop");
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
asm ("nop");
}
/* Write to this block to initiate precharge */
*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
asm("nop");
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 2000; i++) {
asm(" nop");
}
/* Finish the configuration by issuing the IMRS. */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
}

96
common/package/utils/sysupgrade-helper/src/board/freescale/m5282evb/u-boot.lds Normal file
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@ -0,0 +1,96 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m53017evb/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m53017evb/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0

94
common/package/utils/sysupgrade-helper/src/board/freescale/m53017evb/m53017evb.c Normal file
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@ -0,0 +1,94 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M53017EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
#endif
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
asm("nop");
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_MODE;
asm("nop");
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
asm("nop");
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

102
common/package/utils/sysupgrade-helper/src/board/freescale/m53017evb/u-boot.lds Normal file
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@ -0,0 +1,102 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf532x/start.o (.text*)
arch/m68k/cpu/mcf532x/libmcf532x.o (.text*)
arch/m68k/lib/libm68k.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5329evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5329evb/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0

88
common/package/utils/sysupgrade-helper/src/board/freescale/m5329evb/m5329evb.c Normal file
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@ -0,0 +1,88 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale FireEngine 5329 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->mode = CONFIG_SYS_SDRAM_MODE;
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

89
common/package/utils/sysupgrade-helper/src/board/freescale/m5329evb/nand.c Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
#define SET_ALE 0x08
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
if (ctrl & NAND_NCE)
*nCE &= 0xFFFB;
else
*nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0;
gpio->podr_timer = 0;
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
return 0;
}
#endif

100
common/package/utils/sysupgrade-helper/src/board/freescale/m5329evb/u-boot.lds Normal file
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@ -0,0 +1,100 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf532x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m5373evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
common/package/utils/sysupgrade-helper/src/board/freescale/m5373evb/config.mk Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0

88
common/package/utils/sysupgrade-helper/src/board/freescale/m5373evb/m5373evb.c Normal file
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@ -0,0 +1,88 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale FireEngine 5373 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
/* Issue PALL */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->mode = CONFIG_SYS_SDRAM_MODE;
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

93
common/package/utils/sysupgrade-helper/src/board/freescale/m5373evb/nand.c Normal file
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@ -0,0 +1,93 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
#define SET_ALE 0x08
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
if (ctrl & NAND_NCE)
*nCE &= 0xFFFB;
else
*nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0;
gpio->podr_timer = 0;
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
return 0;
}
#endif

100
common/package/utils/sysupgrade-helper/src/board/freescale/m5373evb/u-boot.lds Normal file
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@ -0,0 +1,100 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/m68k/cpu/mcf532x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/utils/sysupgrade-helper/src/board/freescale/m54451evb/Makefile Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

27
common/package/utils/sysupgrade-helper/src/board/freescale/m54451evb/config.mk Normal file
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@ -0,0 +1,27 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)

108
common/package/utils/sysupgrade-helper/src/board/freescale/m54451evb/m54451evb.c Normal file
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@ -0,0 +1,108 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
/*
* need to to:
* Check serial flash size. if 2mb evb, else 8mb demo
*/
puts("Board: ");
puts("Freescale M54451 EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
/*
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
(sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
udelay(200);
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Perform two refresh cycles */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
/* Issue LEMR */
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
__asm__("nop");
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
__asm__("nop");
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
udelay(100);
#endif
return (dramsize);
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

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