mirror of
https://github.com/Ysurac/openmptcprouter.git
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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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$(shell mkdir -p $(OBJTREE)/board/freescale/common)
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LIB = $(obj)lib$(BOARD).o
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COBJS-y := $(BOARD).o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,7 @@
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To configure for the current (Rev 3.x) ADS5121
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make ads5121_config
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This will automatically include PCI, the Real Time CLock, add backup flash
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ability and set the correct frequency and memory configuration.
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To configure for the older Rev 2 ADS5121 type (this will not have PCI)
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make ads5121_rev2_config
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@ -0,0 +1,351 @@
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/*
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* (C) Copyright 2007-2009 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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#include <net.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN | \
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CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_USB1_EN | \
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CLOCK_SCCR2_USB2_EN)
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void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
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/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
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extern int mpc5121_nfc_chip;
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/* Control chips select signal on MPC5121ADS board */
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void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
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{
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unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
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u8 v;
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v = in_8(csreg);
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v |= 0x0F;
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if (chip >= 0) {
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__mpc5121_nfc_select_chip(mtd, 0);
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v &= ~(1 << mpc5121_nfc_chip);
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} else {
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__mpc5121_nfc_select_chip(mtd, -1);
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}
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out_8(csreg, v);
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}
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 spridr;
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/*
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* Initialize Local Window for the CPLD registers access (CS2 selects
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* the CPLD chip)
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*/
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out_be32(&im->sysconf.lpcs2aw,
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CSAW_START(CONFIG_SYS_CPLD_BASE) |
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CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
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sync_law(&im->sysconf.lpcs2aw);
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/*
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* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
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*
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* Without this the flash identification routine fails, as it needs to issue
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* write commands in order to establish the device ID.
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*/
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#ifdef CONFIG_MPC5121ADS_REV2
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out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
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#else
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if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
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out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
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} else {
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/* running from Backup flash */
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out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
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}
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#endif
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/*
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* Configure Flash Speed
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*/
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
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spridr = in_be32(&im->sysconf.spridr);
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if (SVR_MJREV (spridr) >= 2)
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out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
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/*
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* Enable clocks
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*/
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out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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}
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int is_micron(void){
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ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
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uchar macaddr[6];
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u32 brddate, macchk, ismicron;
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/*
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* MAC address has serial number with date of manufacture
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* Boards made before Nov-08 #1180 use Micron memory;
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* 001e59 is the STx vendor #
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* Default is Elpida since it works for both but is slightly slower
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*/
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ismicron = 0;
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if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
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brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
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macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
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debug("brddate = %d\n\t", brddate);
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if (macchk == 0x001e59 && brddate <= 8111180)
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ismicron = 1;
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} else if (brd_rev < 0x400) {
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ismicron = 1;
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}
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debug("Using %s Memory settings\n\t",
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ismicron ? "Micron" : "Elpida");
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return(ismicron);
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}
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phys_size_t initdram(int board_type)
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{
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u32 msize = 0;
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/*
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* Elpida MDDRC and initialization settings are an alternative
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* to the Default Micron ones for all but the earliest Rev 4 boards
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*/
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ddr512x_config_t elpida_mddrc_config = {
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.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
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.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
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.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
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.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
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};
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u32 elpida_init_sequence[] = {
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_EM2,
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CONFIG_SYS_DDRCMD_EM3,
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CONFIG_SYS_DDRCMD_EN_DLL,
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CONFIG_SYS_ELPIDA_RES_DLL,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_ELPIDA_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_OCD_DEFAULT,
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CONFIG_SYS_ELPIDA_OCD_EXIT,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP
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};
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if (is_micron()) {
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msize = fixed_sdram(NULL, NULL, 0);
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} else {
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msize = fixed_sdram(&elpida_mddrc_config,
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elpida_init_sequence,
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sizeof(elpida_init_sequence)/sizeof(u32));
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}
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return msize;
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}
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int misc_init_r(void)
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{
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u8 tmp_val;
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/* Using this for DIU init before the driver in linux takes over
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* Enable the TFP410 Encoder (I2C address 0x38)
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*/
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i2c_set_bus_num(2);
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tmp_val = 0xBF;
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i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02x\n", tmp_val);
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tmp_val = 0x10;
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i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02x\n", tmp_val);
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* Set highest Slew on 9 PATA pins */
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{
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offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=SPDIF_TXCLK */
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{
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offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
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{
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offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU CLK */
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{
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offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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{
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offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{
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offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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}
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};
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static iopin_t rev2_silicon_pci_ioregs_init[] = {
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/* FUNC0=PCI Sets next 54 to PCI pads */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
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}
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};
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int checkboard (void)
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{
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ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
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uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&im->sysconf.spridr);
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printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
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if (SVR_MJREV (spridr) >= 2)
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iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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