mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# Copyright 2010-2011 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,53 @@
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* Authors: Chunhe Lan <b25806@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#ifndef __BCSR_H_
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#define __BCSR_H_
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#include <common.h>
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/*
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* BCSR Bit definitions
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* BCSR 15 *
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0 device insertion oriention
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1 stack processor present
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2 power supply shut down/normal operation
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3 I2C bus0 drive enable
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4 reserved
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5:7 I2C bus0 select
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5 - I2C_BUS_0_SS0
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6 - I2C_BUS_0_SS1
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7 - I2C_BUS_0_SS2
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*/
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/* BCSR register base address is 0xFX000020 */
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#define BCSR_BASE_REG_OFFSET 0x20
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#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET)
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#define BCSR15_DEV_INS_ORI 0x80
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#define BCSR15_STACK_PRO_PRE 0x40
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#define BCSR15_POWER_SUPPLY 0x20
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#define BCSR15_I2C_BUS0_EN 0x10
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#define BCSR15_I2C_BUS0_SEG0 0x00
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#define BCSR15_I2C_BUS0_SEG1 0x04
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#define BCSR15_I2C_BUS0_SEG2 0x02
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#define BCSR15_I2C_BUS0_SEG3 0x06
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#define BCSR15_I2C_BUS0_SEG4 0x01
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#define BCSR15_I2C_BUS0_SEG5 0x05
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#define BCSR15_I2C_BUS0_SEG6 0x03
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#define BCSR15_I2C_BUS0_SEG7 0x07
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#define BCSR15_I2C_BUS0_SEG_CLR 0x07
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#define BCSR19_SGMII_SEL_L 0x01
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/*BCSR Utils functions*/
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void fixup_i2c_bus0_sel_seg0(void);
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#endif /* __BCSR_H_ */
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@ -0,0 +1,35 @@
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
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LAW_TRGT_IF_DPAA_SWP_SRAM),
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/* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */
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SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -0,0 +1,211 @@
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/*
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* Copyright 2010-2012 Freescale Semiconductor, Inc.
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*
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* Authors: Roy Zang <tie-fei.zang@freescale.com>
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* Chunhe Lan <b25806@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_portals.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include "bcsr.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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/* Set ABSWP to implement conversion of addresses in the LBC */
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setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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return 0;
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}
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int checkboard(void)
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{
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u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
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printf("Board: P1023 RDS\n");
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clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
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setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
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return 0;
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}
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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#ifndef CONFIG_SYS_RAMBOOT
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
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out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
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out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + BCSR region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + bcsr */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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setup_portals();
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return 0;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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return gd->bus_clk;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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return gd->mem_clk;
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}
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int board_eth_init(bd_t *bis)
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{
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u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
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ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_pq_mdio_info dtsec_mdio_info;
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/*
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* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
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* is not correct.
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*/
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_mdio(FM1_DTSEC1,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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fm_info_set_mdio(FM1_DTSEC2,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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/* Make SERDES connected to SGMII by cleaing bcsr19[7] */
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if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
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clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);
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#ifdef CONFIG_FMAN_ENET
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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/* By default NOR is on, and NAND is disabled */
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#ifdef CONFIG_NAND_U_BOOT
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do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
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do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
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#endif
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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fdt_fixup_fman_ethernet(blob);
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}
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#endif
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@ -0,0 +1,118 @@
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/*
|
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
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|
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struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
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0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
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0, 0, BOOKE_PAGESZ_4K, 0),
|
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
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0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
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0, 0, BOOKE_PAGESZ_4K, 1),
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||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
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0, 1, BOOKE_PAGESZ_4M, 1),
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||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/* *W*G* - BCSR and NOR flash on local bus*/
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 9, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_1M, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G - NAND */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 12, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 13, BOOKE_PAGESZ_1G, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
Loading…
Add table
Add a link
Reference in a new issue