mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := tt01.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,32 @@
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/*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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* (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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mov pc, lr
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/*
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* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <command.h>
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#include <pmic.h>
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#include <fsl_pmic.h>
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#include <mc13783.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BOARD_STRING "Board: HALE TT-01"
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/* Clock configuration */
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#define CCM_CCMR_SETUP 0x074B0BF5
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static void board_setup_clocks(void)
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{
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struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
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volatile int wait = 0x10000;
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writel(CCM_CCMR_SETUP, &ccm->ccmr);
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while (wait--)
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;
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writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
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writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
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/* Set up clock to 532MHz */
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writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
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PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
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PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
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PDR0_MCU_PODF(0), &ccm->pdr0);
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writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
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&ccm->mpctl);
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writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
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&ccm->spctl);
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}
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/* DRAM configuration */
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#define ESDMISC_MDDR_SETUP 0x00000004
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#define ESDMISC_MDDR_RESET_DL 0x0000000c
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/*
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* decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
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* tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
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* tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
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* tRCD = 011, tRC = 010
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* note: all but tWTR (1), tRC (111) are reset defaults,
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* the same values work in the jtag configuration
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*
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* Bluetechnix setup has 0x75e73a (for 128MB) =
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* 0b 0111 0101 1110 0111 0011 1010
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* tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
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* tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
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* tRCD = 011, tRC = 010
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*/
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#define ESDCFG0_MDDR_SETUP 0x006ac73a
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#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
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#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
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ESDCTL_DSIZ(2) | ESDCTL_BL(1))
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#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
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#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
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#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
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#define ESDCTL_RW ESDCTL_SETTINGS
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static void board_setup_sdram(void)
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{
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u32 *pad;
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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/*
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* setup pad control for the controller pins
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* no loopback, no pull, no keeper, no open drain,
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* standard input, standard drive, slow slew rate
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*/
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for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
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pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
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*pad = 0;
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/* set up MX31 DDR Memory Controller */
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writel(ESDMISC_MDDR_SETUP, &esdc->misc);
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writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
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/* perform DDR init sequence for CSD0 */
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writel(ESDCTL_PRECHARGE, &esdc->ctl0);
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writel(0x12344321, CSD0_BASE+0x0f00);
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writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
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writel(0x12344321, CSD0_BASE);
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writel(0x12344321, CSD0_BASE);
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writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
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writeb(0xda, CSD0_BASE+0x33);
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writeb(0xff, CSD0_BASE+0x1000000);
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writel(ESDCTL_RW, &esdc->ctl0);
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writel(0xDEADBEEF, CSD0_BASE);
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writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
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}
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static void tt01_spi3_hw_init(void)
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{
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/* CSPI3 */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
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/* CSPI3, SS0 = Atlas */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
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/* start CSPI3 clock (3 = always on except if PLL off) */
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setbits_le32(CCM_CGR0, 3 << 16);
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS4: FPGA incl. network controller */
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struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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/* this seems essential, won't start without, but why? */
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writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
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board_setup_clocks();
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board_setup_sdram();
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mxc_setup_weimcs(4, &cs4);
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/* Setup UART2 and SPI3 pins */
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mx31_uart2_hw_init();
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tt01_spi3_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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mxc_hw_watchdog_enable();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts(BOARD_STRING "\n");
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return 0;
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}
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#ifdef CONFIG_MXC_MMC
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int board_mmc_init(bd_t *bis)
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{
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u32 val;
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struct pmic *p;
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/*
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* this is the first driver to use the pmic, so call
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* pmic_init() here. board_late_init() is too late for
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* the MMC driver.
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*/
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pmic_init();
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p = get_pmic();
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/* configure pins for SDHC1 only */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
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/* turn on power V_MMC1 */
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if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
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pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
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return mxc_mmc_init(bis);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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#ifdef CONFIG_CONSOLE_EXTRA_INFO
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void video_get_info_str(int line_number, char *info)
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{
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u32 srev = get_cpu_rev();
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switch (line_number) {
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case 2:
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sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
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(srev & 0xF0) >> 4, (srev & 0x0F),
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((srev & 0x8000) ? " unknown" : ""),
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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break;
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case 3:
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strcpy(info, " " BOARD_STRING);
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break;
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default:
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info[0] = 0;
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}
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}
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#endif
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