mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
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ifdef CONFIG_KM_FPGA_CONFIG
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COBJS += fpga_config.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,255 @@
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/*
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* (C) Copyright 2012
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* Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/errno.h>
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/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
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#define KM_XLX_PROGRAM_B_PIN 39
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#define BOCO_ADDR 0x10
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#define ID_REG 0x00
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#define BOCO2_ID 0x5b
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static int check_boco2(void)
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{
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int ret;
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u8 id;
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ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
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if (ret) {
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printf("%s: error reading the BOCO id !!\n", __func__);
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return ret;
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}
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return (id == BOCO2_ID);
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}
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static int boco_clear_bits(u8 reg, u8 flags)
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{
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int ret;
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u8 regval;
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/* give access to the EEPROM from FPGA */
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ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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regval &= ~flags;
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ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error writing the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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return 0;
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}
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static int boco_set_bits(u8 reg, u8 flags)
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{
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int ret;
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u8 regval;
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/* give access to the EEPROM from FPGA */
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ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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regval |= flags;
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ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
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if (ret) {
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printf("%s: error writing the BOCO @%#x !!\n",
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__func__, reg);
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return ret;
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}
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return 0;
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}
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#define SPI_REG 0x06
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#define CFG_EEPROM 0x02
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#define FPGA_PROG 0x04
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#define FPGA_INIT_B 0x10
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#define FPGA_DONE 0x20
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static int fpga_done(void)
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{
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int ret = 0;
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u8 regval;
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/* this is only supported with the boco2 design */
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if (!check_boco2())
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return 0;
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ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
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if (ret) {
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printf("%s: error reading the BOCO @%#x !!\n",
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__func__, SPI_REG);
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return 0;
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}
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return regval & FPGA_DONE ? 1 : 0;
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}
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int skip;
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int trigger_fpga_config(void)
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{
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int ret = 0;
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/* if the FPGA is already configured, we do not want to
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* reconfigure it */
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skip = 0;
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if (fpga_done()) {
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printf("PCIe FPGA config: skipped\n");
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skip = 1;
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return 0;
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}
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if (check_boco2()) {
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/* we have a BOCO2, this has to be triggered here */
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/* make sure the FPGA_can access the EEPROM */
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ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
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if (ret)
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return ret;
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/* trigger the config start */
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ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
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if (ret)
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return ret;
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/* small delay for the pulse */
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udelay(10);
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/* up signal for pulse end */
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ret = boco_set_bits(SPI_REG, FPGA_PROG);
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if (ret)
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return ret;
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/* finally, raise INIT_B to remove the config delay */
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ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
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if (ret)
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return ret;
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} else {
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/* we do it the old way, with the gpio pin */
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kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
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kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
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/* small delay for the pulse */
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udelay(10);
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kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
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}
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return 0;
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}
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int wait_for_fpga_config(void)
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{
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int ret = 0;
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u8 spictrl;
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u32 timeout = 20000;
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if (skip)
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return 0;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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printf("PCIe FPGA config:");
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do {
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ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
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if (ret) {
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printf("%s: error reading the BOCO spictrl !!\n",
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__func__);
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return ret;
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}
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if (timeout-- == 0) {
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printf(" FPGA_DONE timeout\n");
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return -EFAULT;
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}
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udelay(10);
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} while (!(spictrl & FPGA_DONE));
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printf(" done\n");
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return 0;
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}
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#define PRST1 0x4
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#define PCIE_RST 0x10
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#define TRAFFIC_RST 0x04
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int fpga_reset(void)
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{
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int ret = 0;
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u8 resets;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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/* if we have skipped, we only want to reset the PCIe part */
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resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
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ret = boco_clear_bits(PRST1, resets);
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if (ret)
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return ret;
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/* small delay for the pulse */
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udelay(10);
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ret = boco_set_bits(PRST1, resets);
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if (ret)
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return ret;
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return 0;
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}
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/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
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* is available from the Bobcat SPI bus */
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int toggle_eeprom_spi_bus(void)
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{
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int ret = 0;
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if (!check_boco2()) {
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/* we do not have BOCO2, this is not really used */
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return 0;
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}
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ret = boco_set_bits(SPI_REG, CFG_EEPROM);
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if (ret)
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return ret;
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return 0;
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}
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@ -0,0 +1,530 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <nand.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* BOCO FPGA definitions
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*/
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#define BOCO 0x10
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#define REG_CTRL_H 0x02
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#define MASK_WRL_UNITRUN 0x01
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#define MASK_RBX_PGY_PRESENT 0x40
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#define REG_IRQ_CIRQ2 0x2d
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#define MASK_RBI_DEFECT_16 0x01
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_PEX_RST_OUTn,
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#if defined(CONFIG_SOFT_I2C)
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MPP8_GPIO, /* SDA */
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MPP9_GPIO, /* SCL */
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#endif
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#if defined(CONFIG_HARD_I2C)
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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#endif
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO, /* Reserved */
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MPP13_UART1_TXD,
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MPP14_UART1_RXD,
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MPP15_GPIO, /* Not used */
|
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MPP16_GPIO, /* Not used */
|
||||
MPP17_GPIO, /* Reserved */
|
||||
MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
|
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
|
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MPP26_GPIO,
|
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MPP27_GPIO,
|
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MPP28_GPIO,
|
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MPP29_GPIO,
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MPP30_GPIO,
|
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MPP31_GPIO,
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MPP32_GPIO,
|
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MPP33_GPIO,
|
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MPP34_GPIO, /* CDL1 (input) */
|
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MPP35_GPIO, /* CDL2 (input) */
|
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MPP36_GPIO, /* MAIN_IRQ (input) */
|
||||
MPP37_GPIO, /* BOARD_LED */
|
||||
MPP38_GPIO, /* Piggy3 LED[1] */
|
||||
MPP39_GPIO, /* Piggy3 LED[2] */
|
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MPP40_GPIO, /* Piggy3 LED[3] */
|
||||
MPP41_GPIO, /* Piggy3 LED[4] */
|
||||
MPP42_GPIO, /* Piggy3 LED[5] */
|
||||
MPP43_GPIO, /* Piggy3 LED[6] */
|
||||
MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
|
||||
MPP45_GPIO, /* Piggy3 LED[8] */
|
||||
MPP46_GPIO, /* Reserved */
|
||||
MPP47_GPIO, /* Reserved */
|
||||
MPP48_GPIO, /* Reserved */
|
||||
MPP49_GPIO, /* SW_INTOUTn */
|
||||
0
|
||||
};
|
||||
|
||||
#if defined(CONFIG_KM_MGCOGE3UN)
|
||||
/*
|
||||
* Wait for startup OK from mgcoge3ne
|
||||
*/
|
||||
int startup_allowed(void)
|
||||
{
|
||||
unsigned char buf;
|
||||
|
||||
/*
|
||||
* Read CIRQ16 bit (bit 0)
|
||||
*/
|
||||
if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
|
||||
printf("%s: Error reading Boco\n", __func__);
|
||||
else
|
||||
if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
|
||||
/*
|
||||
* All boards with PIGGY4 connected via a simple switch have ethernet always
|
||||
* present.
|
||||
*/
|
||||
int ethernet_present(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#else
|
||||
int ethernet_present(void)
|
||||
{
|
||||
uchar buf;
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||||
int ret = 0;
|
||||
|
||||
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
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printf("%s: Error reading Boco\n", __func__);
|
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return -1;
|
||||
}
|
||||
if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
|
||||
ret = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
int initialize_unit_leds(void)
|
||||
{
|
||||
/*
|
||||
* Init the unit LEDs per default they all are
|
||||
* ok apart from bootstat
|
||||
*/
|
||||
uchar buf;
|
||||
|
||||
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
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printf("%s: Error reading Boco\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
buf |= MASK_WRL_UNITRUN;
|
||||
if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
||||
printf("%s: Error writing Boco\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
void set_bootcount_addr(void)
|
||||
{
|
||||
uchar buf[32];
|
||||
unsigned int bootcountaddr;
|
||||
bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
|
||||
sprintf((char *)buf, "0x%x", bootcountaddr);
|
||||
setenv("bootcountaddr", (char *)buf);
|
||||
}
|
||||
#endif
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *str;
|
||||
int mach_type;
|
||||
|
||||
str = getenv("mach_type");
|
||||
if (str != NULL) {
|
||||
mach_type = simple_strtoul(str, NULL, 10);
|
||||
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
|
||||
gd->bd->bi_arch_number = mach_type;
|
||||
}
|
||||
#if defined(CONFIG_KM_MGCOGE3UN)
|
||||
char *wait_for_ne;
|
||||
wait_for_ne = getenv("waitforne");
|
||||
if (wait_for_ne != NULL) {
|
||||
if (strcmp(wait_for_ne, "true") == 0) {
|
||||
int cnt = 0;
|
||||
int abort = 0;
|
||||
puts("NE go: ");
|
||||
while (startup_allowed() == 0) {
|
||||
if (tstc()) {
|
||||
(void) getc(); /* consume input */
|
||||
abort = 1;
|
||||
break;
|
||||
}
|
||||
udelay(200000);
|
||||
cnt++;
|
||||
if (cnt == 5)
|
||||
puts("wait\b\b\b\b");
|
||||
if (cnt == 10) {
|
||||
cnt = 0;
|
||||
puts(" \b\b\b\b");
|
||||
}
|
||||
}
|
||||
if (abort == 1)
|
||||
printf("\nAbort waiting for ne\n");
|
||||
else
|
||||
puts("OK\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
initialize_unit_leds();
|
||||
set_km_env();
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
set_bootcount_addr();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
u32 tmp;
|
||||
|
||||
/* set the 2 bitbang i2c pins as output gpios */
|
||||
tmp = readl(KW_GPIO0_BASE + 4);
|
||||
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
|
||||
#endif
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
/*
|
||||
* The KM_FLASH_GPIO_PIN switches between using a
|
||||
* NAND or a SPI FLASH. Set this pin on start
|
||||
* to NAND mode.
|
||||
*/
|
||||
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
|
||||
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
/*
|
||||
* Reinit the GPIO for I2C Bitbang driver so that the now
|
||||
* available gpio framework is consistent. The calls to
|
||||
* direction output in are not necessary, they are already done in
|
||||
* board_early_init_f
|
||||
*/
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
|
||||
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KM_FPGA_CONFIG)
|
||||
trigger_fpga_config();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#if defined(CONFIG_KMCOGE5UN)
|
||||
/* I/O pin to erase flash RGPP09 = MPP43 */
|
||||
#define KM_FLASH_ERASE_ENABLE 43
|
||||
u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
|
||||
|
||||
/* if pin 1 do full erase */
|
||||
if (dip_switch != 0) {
|
||||
/* start bootloader */
|
||||
puts("DIP: Enabled\n");
|
||||
setenv("actual_bank", "0");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KM_FPGA_CONFIG)
|
||||
wait_for_fpga_config();
|
||||
fpga_reset();
|
||||
toggle_eeprom_spi_bus();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
/* Fix this */
|
||||
gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
|
||||
kw_sdram_bs(0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
|
||||
gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
|
||||
kw_sdram_bs(i));
|
||||
}
|
||||
}
|
||||
|
||||
#if (defined(CONFIG_KM_PIGGY4_88E6061))
|
||||
|
||||
#define PHY_LED_SEL_REG 0x18
|
||||
#define PHY_LED0_LINK (0x5)
|
||||
#define PHY_LED1_ACT (0x8<<4)
|
||||
#define PHY_LED2_INT (0xe<<8)
|
||||
#define PHY_SPEC_CTRL_REG 0x1c
|
||||
#define PHY_RGMII_CLK_STABLE (0x1<<10)
|
||||
#define PHY_CLSA (0x1<<1)
|
||||
|
||||
/* Configure and enable MV88E3018 PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
char *name = "egiga0";
|
||||
unsigned short reg;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* RGMII clk transition on data stable */
|
||||
if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
|
||||
printf("Error reading PHY spec ctrl reg\n");
|
||||
if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
|
||||
reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
|
||||
printf("Error writing PHY spec ctrl reg\n");
|
||||
|
||||
/* leds setup */
|
||||
if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
|
||||
PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
|
||||
printf("Error writing PHY LED reg\n");
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
|
||||
}
|
||||
#else
|
||||
/* Configure and enable MV88E1118 PHY on the piggy*/
|
||||
void reset_phy(void)
|
||||
{
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_HUSH_INIT_VAR)
|
||||
int hush_init_var(void)
|
||||
{
|
||||
ivm_read_eeprom();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
const ulong patterns[] = { 0x00000000,
|
||||
0xFFFFFFFF,
|
||||
0xFF00FF00,
|
||||
0x0F0F0F0F,
|
||||
0xF0F0F0F0};
|
||||
const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
|
||||
const ulong OFFS_PATTERN = 3;
|
||||
const ulong REPEAT_PATTERN = 1000;
|
||||
|
||||
void bootcount_store(ulong a)
|
||||
{
|
||||
ulong *save_addr;
|
||||
ulong size = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
size += gd->bd->bi_dram[i].size;
|
||||
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
|
||||
writel(a, save_addr);
|
||||
writel(BOOTCOUNT_MAGIC, &save_addr[1]);
|
||||
|
||||
for (i = 0; i < REPEAT_PATTERN; i++)
|
||||
writel(patterns[i % NBR_OF_PATTERNS],
|
||||
&save_addr[i+OFFS_PATTERN]);
|
||||
|
||||
}
|
||||
|
||||
ulong bootcount_load(void)
|
||||
{
|
||||
ulong *save_addr;
|
||||
ulong size = 0;
|
||||
ulong counter = 0;
|
||||
int i, tmp;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
size += gd->bd->bi_dram[i].size;
|
||||
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
|
||||
|
||||
counter = readl(&save_addr[0]);
|
||||
|
||||
/* Is the counter reliable, check in the big pattern for bit errors */
|
||||
for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
|
||||
tmp = readl(&save_addr[i+OFFS_PATTERN]);
|
||||
if (tmp != patterns[i % NBR_OF_PATTERNS])
|
||||
counter = 0;
|
||||
}
|
||||
return counter;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
void set_sda(int state)
|
||||
{
|
||||
I2C_ACTIVE;
|
||||
I2C_SDA(state);
|
||||
}
|
||||
|
||||
void set_scl(int state)
|
||||
{
|
||||
I2C_SCL(state);
|
||||
}
|
||||
|
||||
int get_sda(void)
|
||||
{
|
||||
I2C_TRISTATE;
|
||||
return I2C_READ;
|
||||
}
|
||||
|
||||
int get_scl(void)
|
||||
{
|
||||
return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
|
||||
#define KM_POST_EN_L 44
|
||||
#define POST_WORD_OFF 8
|
||||
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
#if defined(CONFIG_KM_COGE5UN)
|
||||
return kw_gpio_get_value(KM_POST_EN_L);
|
||||
#else
|
||||
return !kw_gpio_get_value(KM_POST_EN_L);
|
||||
#endif
|
||||
}
|
||||
|
||||
ulong post_word_load(void)
|
||||
{
|
||||
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
||||
return in_le32(addr);
|
||||
|
||||
}
|
||||
void post_word_store(ulong value)
|
||||
{
|
||||
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
||||
out_le32(addr, value);
|
||||
}
|
||||
|
||||
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
||||
{
|
||||
*vstart = CONFIG_SYS_SDRAM_BASE;
|
||||
|
||||
/* we go up to relocation plus a 1 MB margin */
|
||||
*size = CONFIG_SYS_TEXT_BASE - (1<<20);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||
{
|
||||
kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
|
||||
|
||||
return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011
|
||||
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: MPPSel0 2, NF_IO[2]
|
||||
# bit 7-4: MPPSel1 2, NF_IO[3]
|
||||
# bit 12-8: MPPSel2 2, NF_IO[4]
|
||||
# bit 15-12: MPPSel3 2, NF_IO[5]
|
||||
# bit 19-16: MPPSel4 1, NF_IO[6]
|
||||
# bit 23-20: MPPSel5 1, NF_IO[7]
|
||||
# bit 27-24: MPPSel6 1, SYSRST_O
|
||||
# bit 31-28: MPPSel7 0, GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: MPPSel16 0, GPIO[16]
|
||||
# bit 7-4: MPPSel17 0, GPIO[17]
|
||||
# bit 12-8: MPPSel18 1, NF_IO[0]
|
||||
# bit 15-12: MPPSel19 1, NF_IO[1]
|
||||
# bit 19-16: MPPSel20 0, GPIO[20]
|
||||
# bit 23-20: MPPSel21 0, GPIO[21]
|
||||
# bit 27-24: MPPSel22 0, GPIO[22]
|
||||
# bit 31-28: MPPSel23 0, GPIO[23]
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
|
||||
#Dram initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit13-0: 0x4E0 (DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0 reserved
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x00000001 # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x16
|
||||
# bit3-2: 00, Cs0size=2Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd disabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 0, DDR ODT control msb disabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add a sample stage
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit3-0 : 0000, required
|
||||
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
|
||||
# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
|
||||
# bit15-12: 0100, internal ODT assertion 4 cycles after read
|
||||
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
|
||||
# bit31-20: 0 , required
|
||||
|
||||
DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
|
||||
# bit3-0 : 0001, M_ODT assertion same cycle as write
|
||||
# bit7-4 : 0101, M_ODT de-assertion x cycles after write
|
||||
# bit11-8 : 0100, internal ODT assertion x cycles after write
|
||||
# bit15-12: 1000, internal ODT de-assertion x cycles after write
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 00, ODT1 controlled by register
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
|
||||
# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
|
||||
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
|
||||
# bit14 :1, STARTBURST ODT enabled
|
||||
# bit15 :1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: MPPSel0 2, NF_IO[2]
|
||||
# bit 7-4: MPPSel1 2, NF_IO[3]
|
||||
# bit 12-8: MPPSel2 2, NF_IO[4]
|
||||
# bit 15-12: MPPSel3 2, NF_IO[5]
|
||||
# bit 19-16: MPPSel4 1, NF_IO[6]
|
||||
# bit 23-20: MPPSel5 1, NF_IO[7]
|
||||
# bit 27-24: MPPSel6 1, SYSRST_O
|
||||
# bit 31-28: MPPSel7 0, GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: MPPSel16 0, GPIO[16]
|
||||
# bit 7-4: MPPSel17 0, GPIO[17]
|
||||
# bit 12-8: MPPSel18 1, NF_IO[0]
|
||||
# bit 15-12: MPPSel19 1, NF_IO[1]
|
||||
# bit 19-16: MPPSel20 0, GPIO[20]
|
||||
# bit 23-20: MPPSel21 0, GPIO[21]
|
||||
# bit 27-24: MPPSel22 0, GPIO[22]
|
||||
# bit 31-28: MPPSel23 0, GPIO[23]
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
|
||||
#Dram initalization
|
||||
DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
|
||||
# bit13-0: 0x400 (DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0 reserved
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000000D # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x16
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
DATA 0xFFD01420 0x00000044 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 1, DDR ODT control lsd disabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 0 , no sample stage
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
DATA 0xFFD01428 0x00074510
|
||||
DATA 0xFFD0147c 0x00007451
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
|
||||
# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 00, ODT1 controlled by register
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
|
||||
# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit9-8: 1, ODTEn, never active
|
||||
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# (C) Copyright 2012
|
||||
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
|
||||
# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
|
||||
#
|
||||
# (C) Copyright 2012
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
|
||||
# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
|
||||
# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
|
||||
# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
|
||||
# bit 19-16: 1, MPPSel4 NF_IO[6]
|
||||
# bit 23-20: 1, MPPSel5 NF_IO[7]
|
||||
# bit 27-24: 1, MPPSel6 SYSRST_O
|
||||
# bit 31-28: 0, MPPSel7 GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
|
||||
# bit 3-0: 0, MPPSel8 GPIO[8]
|
||||
# bit 7-4: 0, MPPSel9 GPIO[9]
|
||||
# bit 12-8: 3, MPPSel10 UA0_TXD
|
||||
# bit 15-12: 3, MPPSel11 UA0_RXD
|
||||
# bit 19-16: 0, MPPSel12 not connected
|
||||
# bit 23-20: 3, MPPSel13 UA1_TXD
|
||||
# bit 27-24: 3, MPPSel14 UA1_RXD
|
||||
# bit 31-28: 0, MPPSel15 GPIO[15]
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: 0, MPPSel16 GPIO[16]
|
||||
# bit 7-4: 0, MPPSel17 not connected
|
||||
# bit 12-8: 1, MPPSel18 NF_IO[0]
|
||||
# bit 15-12: 1, MPPSel19 NF_IO[1]
|
||||
# bit 19-16: 0, MPPSel20 GPIO[20]
|
||||
# bit 23-20: 0, MPPSel21 GPIO[21]
|
||||
# bit 27-24: 0, MPPSel22 GPIO[22]
|
||||
# bit 31-28: 0, MPPSel23 GPIO[23]
|
||||
|
||||
# MPP Control 3-6 Register untouched (MPP24-49)
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
# bit 2-0: 3, Reserved
|
||||
# bit 5-3: 3, Reserved
|
||||
# bit 6: 0, Reserved
|
||||
# bit 7: 0, RGMII-pads voltage = 3.3V
|
||||
# bit 10-8: 3, Reserved
|
||||
# bit 13-11: 3, Reserved
|
||||
# bit 14: 0, Reserved
|
||||
# bit 15: 0, MPP RGMII-pads voltage = 3.3V
|
||||
# bit 31-16 0x1B1B, Reserved
|
||||
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
# bit 0-1: 2, Tag RAM RTC RAM0
|
||||
# bit 3-2: 1, Tag RAM WTC RAM0
|
||||
# bit 7-4: 6, Reserve
|
||||
# bit 9-8: 2, Valid RAM RTC RAM
|
||||
# bit 11-10: 1, Valid RAM WTC RAM
|
||||
# bit 13-12: 2, Dirty RAM RTC RAM
|
||||
# bit 15-14: 1, Dirty RAM WTC RAM
|
||||
# bit 17-16: 2, Data RAM RTC RAM0
|
||||
# bit 19-18: 1, Data RAM WTC RAM0
|
||||
# bit 21-20: 2, Data RAM RTC RAM1
|
||||
# bit 23-22: 1, Data RAM WTC RAM1
|
||||
# bit 25-24: 2, Data RAM RTC RAM2
|
||||
# bit 27-26: 1, Data RAM WTC RAM2
|
||||
# bit 29-28: 2, Data RAM RTC RAM3
|
||||
# bit 31-30: 1, Data RAM WTC RAM4
|
||||
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
# bit 15-0: ???, Reserve
|
||||
# bit 17-16: 2, ECC RAM RTC RAM0
|
||||
# bit 19-18: 1, ECC RAM WTC RAM0
|
||||
# bit 31-20: ???,Reserve
|
||||
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
# bit 23-0: 0x000200, Addr Config tuning
|
||||
# bit 31-24: 0, Reserved
|
||||
|
||||
# ??? Missing register # CPU RAM Management Control2 Register
|
||||
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
# bit 15-0: 0x1C00, Opmux Tuning
|
||||
# bit 31-16: 0, Pc Dp Tuning
|
||||
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
# bit 1-0: 1, addr clk tune
|
||||
# bit 3-2: 0, reserved
|
||||
# bit 5-4: 0, dtcmp clk tune
|
||||
# bit 7-6: 0, reserved
|
||||
# bit 9-8: 0, macdrv clk tune
|
||||
# bit 11-10: 0, opmuxgm2 clk tune
|
||||
# bit 15-14: 0, rf clk tune
|
||||
# bit 17-16: 0, rfbypass clk tune
|
||||
# bit 19-18: 0, pc dp clk tune
|
||||
# bit 23-20: 0, icache clk tune
|
||||
# bit 27:24: 0, dcache clk tune
|
||||
# bit 31:28: 0, regfile tunin
|
||||
|
||||
# SDRAM initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit 13-0: 0x4E0, DDR2 clks refresh rate
|
||||
# bit 14: 0, reserved
|
||||
# bit 15: 0, reserved
|
||||
# bit 16: 0, CPU to Dram Write buffer policy
|
||||
# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
|
||||
# bit 19-18: 0, reserved
|
||||
# bit 23-20: 0, reserved
|
||||
# bit 24: 1, enable exit self refresh mode on DDR access
|
||||
# bit 25: 1, required
|
||||
# bit 29-26: 0, reserved
|
||||
# bit 31-30: 1, reserved
|
||||
|
||||
DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0, reserved
|
||||
# bit 4: 0, 2T mode =addr/cmd in same cycle
|
||||
# bit 5: 0, clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0, use recommended falling edge of clk for addr/cmd
|
||||
# bit 7-11: 0, reserved
|
||||
# bit 12-13: 1, reserved, required 1
|
||||
# bit 14: 0, input buffer always powered up
|
||||
# bit 17-15: 0, reserved
|
||||
# bit 18: 1, cpu lock transaction enabled
|
||||
# bit 19: 0, reserved
|
||||
# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
|
||||
# bit 30-28: 3, required
|
||||
# bit 31: 0,no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
|
||||
# bit 3-0: 0xE, TRAS, 15 clk (45 ns)
|
||||
# bit 7-4: 0x4, TRCD, 5 clk (15 ns)
|
||||
# bit 11-8: 0x4, TRP, 5 clk (15 ns)
|
||||
# bit 15-12: 0x4, TWR, 5 clk (15 ns)
|
||||
# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
|
||||
# bit 20: 0, extended TRAS msb
|
||||
# bit 23-21: 0, reserved
|
||||
# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
|
||||
# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
|
||||
|
||||
DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
|
||||
# bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
|
||||
# bit 8-7: 0, TR2R
|
||||
# bit 10-9: 0, TR2W
|
||||
# bit 12-11: 0, TW2W
|
||||
# bit 31-13: 0, reserved
|
||||
|
||||
DATA 0xFFD01410 0x00000001 # DDR Address Control
|
||||
# bit 1-0: 1, Cs0width=x16
|
||||
# bit 3-2: 0, Cs0size=2Gb
|
||||
# bit 5-4: 0, Cs1width=nonexistent
|
||||
# bit 7-6: 0, Cs1size =nonexistent
|
||||
# bit 9-8: 0, Cs2width=nonexistent
|
||||
# bit 11-10: 0, Cs2size =nonexistent
|
||||
# bit 13-12: 0, Cs3width=nonexistent
|
||||
# bit 15-14: 0, Cs3size =nonexistent
|
||||
# bit 16: 0, Cs0AddrSel
|
||||
# bit 17: 0, Cs1AddrSel
|
||||
# bit 18: 0, Cs2AddrSel
|
||||
# bit 19: 0, Cs3AddrSel
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit 0: 0, OpenPage enabled
|
||||
# bit 31-1: 0, required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit 3-0: 0, DDR cmd
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
# bit 2-0: 2, Burst Length = 4
|
||||
# bit 3: 0, Burst Type
|
||||
# bit 6-4: 5, CAS Latency = 5
|
||||
# bit 7: 0, Test mode
|
||||
# bit 8: 0, DLL Reset
|
||||
# bit 11-9: 3, Write recovery for auto-precharge must be 3
|
||||
# bit 12: 0, Active power down exit time, fast exit
|
||||
# bit 14-13: 0, reserved
|
||||
# bit 31-15: 0, reserved
|
||||
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit 0: 0, DDR DLL enabled
|
||||
# bit 1: 1, DDR drive strength reduced
|
||||
# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
|
||||
# bit 5-3: 0, required
|
||||
# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
|
||||
# bit 9-7: 0, required
|
||||
# bit 10: 0, differential DQS enabled
|
||||
# bit 11: 0, required
|
||||
# bit 12: 0, DDR output buffer enabled
|
||||
# bit 31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit 2-0: 7, required
|
||||
# bit 3: 1, MBUS Burst Chop disabled
|
||||
# bit 6-4: 7, required
|
||||
# bit 7: 0, reserved
|
||||
# bit 8: 1, add sample stage required for f > 266 MHz
|
||||
# bit 9: 0, no half clock cycle addition to dataout
|
||||
# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit 15-12:0xf, required
|
||||
# bit 31-16: 0, required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit 3-0: 0, required
|
||||
# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
|
||||
# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
|
||||
# (ODT turn off delay 2,5 clk cycles)
|
||||
# bit 15-12: 4, internal ODT time based on bit 7-4
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
|
||||
# bit 3-0: 2, M_ODT assertion same as bit 11-8
|
||||
# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
|
||||
# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
# bit 23-0: 0, reserved
|
||||
# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
|
||||
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit 0: 1, Window enabled
|
||||
# bit 1: 0, Write Protect disabled
|
||||
# bit 3-2: 0, CS0 hit selected
|
||||
# bit 23-4:ones, required
|
||||
# bit 31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
|
||||
# bit 11-8: 0, required
|
||||
# big 15-11: 0, required
|
||||
# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
|
||||
# bit 27-24: 0, required
|
||||
# bit 31-28: 0, required
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
|
||||
# bit 3-2: 0, ODT1 controlled by register
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
|
||||
# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
|
||||
# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
|
||||
# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
|
||||
# bit 14: 1, STARTBURST ODT enabled
|
||||
# bit 15: 1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit 0: 1, enable DDR init upon this register write
|
||||
# bit 31-1: 0, reserved
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
#
|
||||
# (C) Copyright 2012
|
||||
# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
|
||||
# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
|
||||
# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
# This configuration applies to COGE5 design (ARM-part)
|
||||
# Two 8-Bit devices are connected on the 16-Bit bus on the same
|
||||
# chip-select. The supported devices are
|
||||
# MT47H256M8EB-3IT:C
|
||||
# MT47H256M8EB-25EIT:C
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
|
||||
# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
|
||||
# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
|
||||
# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
|
||||
# bit 19-16: 1, MPPSel4 NF_IO[6]
|
||||
# bit 23-20: 1, MPPSel5 NF_IO[7]
|
||||
# bit 27-24: 1, MPPSel6 SYSRST_O
|
||||
# bit 31-28: 0, MPPSel7 GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
|
||||
# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
|
||||
# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
|
||||
# bit 12-8: 3, MPPSel10 UA0_TXD
|
||||
# bit 15-12: 3, MPPSel11 UA0_RXD
|
||||
# bit 19-16: 0, MPPSel12 not connected
|
||||
# bit 23-20: 3, MPPSel13 GPIO[14]
|
||||
# bit 27-24: 3, MPPSel14 GPIO[15]
|
||||
# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: 0, MPPSel16 GPIO[16]
|
||||
# bit 7-4: 0, MPPSel17 not connected
|
||||
# bit 11-8: 1, MPPSel18 NF_IO[0]
|
||||
# bit 15-12: 1, MPPSel19 NF_IO[1]
|
||||
# bit 19-16: 0, MPPSel20 GPIO[20]
|
||||
# bit 23-20: 0, MPPSel21 GPIO[21]
|
||||
# bit 27-24: 0, MPPSel22 GPIO[22]
|
||||
# bit 31-28: 0, MPPSel23 GPIO[23]
|
||||
|
||||
# MPP Control 3-6 Register untouched (MPP24-49)
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
# bit 2-0: 3, Reserved
|
||||
# bit 5-3: 3, Reserved
|
||||
# bit 6: 0, Reserved
|
||||
# bit 7: 0, RGMII-pads voltage = 3.3V
|
||||
# bit 10-8: 3, Reserved
|
||||
# bit 13-11: 3, Reserved
|
||||
# bit 14: 0, Reserved
|
||||
# bit 15: 0, MPP RGMII-pads voltage = 3.3V
|
||||
# bit 31-16 0x1B1B, Reserved
|
||||
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
# bit 0-1: 2, Tag RAM RTC RAM0
|
||||
# bit 3-2: 1, Tag RAM WTC RAM0
|
||||
# bit 7-4: 6, Reserved
|
||||
# bit 9-8: 2, Valid RAM RTC RAM
|
||||
# bit 11-10: 1, Valid RAM WTC RAM
|
||||
# bit 13-12: 2, Dirty RAM RTC RAM
|
||||
# bit 15-14: 1, Dirty RAM WTC RAM
|
||||
# bit 17-16: 2, Data RAM RTC RAM0
|
||||
# bit 19-18: 1, Data RAM WTC RAM0
|
||||
# bit 21-20: 2, Data RAM RTC RAM1
|
||||
# bit 23-22: 1, Data RAM WTC RAM1
|
||||
# bit 25-24: 2, Data RAM RTC RAM2
|
||||
# bit 27-26: 1, Data RAM WTC RAM2
|
||||
# bit 29-28: 2, Data RAM RTC RAM3
|
||||
# bit 31-30: 1, Data RAM WTC RAM4
|
||||
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
# bit 15-0: ?, Reserved
|
||||
# bit 17-16: 2, ECC RAM RTC RAM0
|
||||
# bit 19-18: 1, ECC RAM WTC RAM0
|
||||
# bit 31-20: ?,Reserved
|
||||
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
# bit 23-0: 0x000200, Addr Config tuning
|
||||
# bit 31-24: 0, Reserved
|
||||
|
||||
# ??? Missing register # CPU RAM Management Control2 Register
|
||||
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
# bit 15-0: 0x1C00, Opmux Tuning
|
||||
# bit 31-16: 0, Pc Dp Tuning
|
||||
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
# bit 1-0: 1, addr clk tune
|
||||
# bit 3-2: 0, reserved
|
||||
# bit 5-4: 0, dtcmp clk tune
|
||||
# bit 7-6: 0, reserved
|
||||
# bit 9-8: 0, macdrv clk tune
|
||||
# bit 11-10: 0, opmuxgm2 clk tune
|
||||
# bit 15-14: 0, rf clk tune
|
||||
# bit 17-16: 0, rfbypass clk tune
|
||||
# bit 19-18: 0, pc dp clk tune
|
||||
# bit 23-20: 0, icache clk tune
|
||||
# bit 27:24: 0, dcache clk tune
|
||||
# bit 31:28: 0, regfile tunin
|
||||
|
||||
# SDRAM initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit 13-0: 0x4E0, DDR2 clks refresh rate
|
||||
# bit 14: 0, reserved
|
||||
# bit 15: 0, reserved
|
||||
# bit 16: 0, CPU to Dram Write buffer policy
|
||||
# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
|
||||
# bit 19-18: 0, reserved
|
||||
# bit 23-20: 0, reserved
|
||||
# bit 24: 1, enable exit self refresh mode on DDR access
|
||||
# bit 25: 1, required
|
||||
# bit 29-26: 0, reserved
|
||||
# bit 31-30: 1, reserved
|
||||
|
||||
DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0, reserved
|
||||
# bit 4: 0, 2T mode =addr/cmd in same cycle
|
||||
# bit 5: 0, clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0, use recommended falling edge of clk for addr/cmd
|
||||
# bit 7-11: 0, reserved
|
||||
# bit 12-13: 1, reserved, required 1
|
||||
# bit 14: 0, input buffer always powered up
|
||||
# bit 17-15: 0, reserved
|
||||
# bit 18: 1, cpu lock transaction enabled
|
||||
# bit 19: 0, reserved
|
||||
# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
|
||||
# bit 30-28: 3, required
|
||||
# bit 31: 0, no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
|
||||
# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
|
||||
# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
|
||||
# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
|
||||
# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
|
||||
# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
|
||||
# bit 20: 0, extended TRAS msb
|
||||
# bit 23-21: 0, reserved
|
||||
# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
|
||||
# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
|
||||
|
||||
DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
|
||||
# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
|
||||
# bit 8-7: 0, TR2R
|
||||
# bit 10-9: 0, TR2W
|
||||
# bit 12-11: 0, TW2W
|
||||
# bit 31-13: 0, reserved
|
||||
|
||||
DATA 0xFFD01410 0x00000000 # DDR Address Control
|
||||
# bit 1-0: 0, Cs0width=x8 (2 devices)
|
||||
# bit 3-2: 0, Cs0size=2Gb
|
||||
# bit 5-4: 0, Cs1width=nonexistent
|
||||
# bit 7-6: 0, Cs1size =nonexistent
|
||||
# bit 9-8: 0, Cs2width=nonexistent
|
||||
# bit 11-10: 0, Cs2size =nonexistent
|
||||
# bit 13-12: 0, Cs3width=nonexistent
|
||||
# bit 15-14: 0, Cs3size =nonexistent
|
||||
# bit 16: 0, Cs0AddrSel
|
||||
# bit 17: 0, Cs1AddrSel
|
||||
# bit 18: 0, Cs2AddrSel
|
||||
# bit 19: 0, Cs3AddrSel
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit 0: 0, OpenPage enabled
|
||||
# bit 31-1: 0, required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit 3-0: 0, DDR cmd
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
# bit 2-0: 2, Burst Length = 4
|
||||
# bit 3: 0, Burst Type
|
||||
# bit 6-4: 5, CAS Latency = 5
|
||||
# bit 7: 0, Test mode
|
||||
# bit 8: 0, DLL Reset
|
||||
# bit 11-9: 3, Write recovery for auto-precharge must be 3
|
||||
# bit 12: 0, Active power down exit time, fast exit
|
||||
# bit 14-13: 0, reserved
|
||||
# bit 31-15: 0, reserved
|
||||
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit 0: 0, DDR DLL enabled
|
||||
# bit 1: 1, DDR drive strenght reduced
|
||||
# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
|
||||
# bit 5-3: 0, required
|
||||
# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
|
||||
# bit 9-7: 0, required
|
||||
# bit 10: 0, differential DQS enabled
|
||||
# bit 11: 0, required
|
||||
# bit 12: 0, DDR output buffer enabled
|
||||
# bit 31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit 2-0: 7, required
|
||||
# bit 3: 1, MBUS Burst Chop disabled
|
||||
# bit 6-4: 7, required
|
||||
# bit 7: 0, reserved
|
||||
# bit 8: 1, add sample stage required for > 266Mhz
|
||||
# bit 9: 0, no half clock cycle addition to dataout
|
||||
# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit 15-12:0xf, required
|
||||
# bit 31-16: 0, required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit 3-0: 0, required
|
||||
# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
|
||||
# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
|
||||
# (ODT turn off delay 2,5 clk cycles)
|
||||
# bit 15-12: 4, internal ODT time based on bit 7-4
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
|
||||
# bit 3-0: 2, M_ODT assertion same as bit 11-8
|
||||
# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
|
||||
# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
# bit 23-0: 0, reserved
|
||||
# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
|
||||
|
||||
DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
|
||||
# bit 0: 1, Window enabled
|
||||
# bit 1: 0, Write Protect disabled
|
||||
# bit 3-2: 0, CS0 hit selected
|
||||
# bit 23-4:ones, required
|
||||
# bit 31-24:0x1F, Size (i.e. 512MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
|
||||
# bit 11-8: 0, required
|
||||
# big 15-11: 0, required
|
||||
# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
|
||||
# bit 27-24: 0, required
|
||||
# bit 31-28: 0, required
|
||||
|
||||
DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
|
||||
# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
|
||||
# bit 3-2: 1, ODT1 never active
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
|
||||
# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
|
||||
# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
|
||||
# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
|
||||
# bit 14: 1, STARTBURST ODT enabled
|
||||
# bit 15: 1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit 0: 1, enable DDR init upon this register write
|
||||
# bit 31-1: 0, reserved
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
Loading…
Add table
Add a link
Reference in a new issue