mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,42 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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||||
#
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||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := overo.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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#########################################################################
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sinclude $(obj).depend
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409
common/package/utils/sysupgrade-helper/src/board/overo/overo.c
Normal file
409
common/package/utils/sysupgrade-helper/src/board/overo/overo.c
Normal file
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@ -0,0 +1,409 @@
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/*
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* Maintainer : Steve Sakoman <steve@sakoman.com>
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*
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* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <linux/mtd/nand.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/omap_gpmc.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include "overo.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define TWL4030_I2C_BUS 0
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#define EXPANSION_EEPROM_I2C_BUS 2
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#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
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#define GUMSTIX_SUMMIT 0x01000200
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#define GUMSTIX_TOBI 0x02000200
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#define GUMSTIX_TOBI_DUO 0x03000200
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#define GUMSTIX_PALO35 0x04000200
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#define GUMSTIX_PALO43 0x05000200
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#define GUMSTIX_CHESTNUT43 0x06000200
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#define GUMSTIX_PINTO 0x07000200
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#define GUMSTIX_GALLOP43 0x08000200
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#define ETTUS_USRP_E 0x01000300
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#define GUMSTIX_NO_EEPROM 0xffffffff
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static struct {
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unsigned int device_vendor;
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unsigned char revision;
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unsigned char content;
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char fab_revision[8];
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char env_var[16];
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char env_setting[64];
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} expansion_config;
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#if defined(CONFIG_CMD_NET)
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static void setup_net_chip(void);
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#endif
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/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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/*CONFIG7- computed as params */
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OVERO;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: omap_rev_string
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* Description: For SPL builds output board rev
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*/
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#ifdef CONFIG_SPL_BUILD
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void omap_rev_string(void)
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{
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}
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#endif
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/*
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* Routine: get_board_revision
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* Description: Returns the board revision
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*/
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int get_board_revision(void)
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{
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int revision;
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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unsigned char data;
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/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
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/* these boards should return a revision number of 0 */
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/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
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i2c_set_bus_num(TWL4030_I2C_BUS);
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data = 0x01;
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i2c_write(0x4B, 0x29, 1, &data, 1);
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data = 0x0c;
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i2c_write(0x4B, 0x2b, 1, &data, 1);
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i2c_read(0x4B, 0x2a, 1, &data, 1);
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#endif
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if (!gpio_request(112, "") &&
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!gpio_request(113, "") &&
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!gpio_request(115, "")) {
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gpio_direction_input(112);
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gpio_direction_input(113);
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gpio_direction_input(115);
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revision = gpio_get_value(115) << 2 |
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gpio_get_value(113) << 1 |
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gpio_get_value(112);
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} else {
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puts("Error: unable to acquire board revision GPIOs\n");
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revision = -1;
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}
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return revision;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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*mr = MICRON_V_MR_165;
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switch (get_board_revision()) {
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case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
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*mcfg = MICRON_V_MCFG_165(256 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
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*mcfg = HYNIX_V_MCFG_165(256 << 20);
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*ctrla = HYNIX_V_ACTIMA_165;
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*ctrlb = HYNIX_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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default:
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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#endif
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/*
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* Routine: get_sdio2_config
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* Description: Return information about the wifi module connection
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* Returns 0 if the module connects though a level translator
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* Returns 1 if the module connects directly
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*/
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int get_sdio2_config(void)
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{
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int sdio_direct;
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if (!gpio_request(130, "") && !gpio_request(139, "")) {
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gpio_direction_output(130, 0);
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gpio_direction_input(139);
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sdio_direct = 1;
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gpio_set_value(130, 0);
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if (gpio_get_value(139) == 0) {
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gpio_set_value(130, 1);
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if (gpio_get_value(139) == 1)
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sdio_direct = 0;
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}
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gpio_direction_input(130);
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} else {
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puts("Error: unable to acquire sdio2 clk GPIOs\n");
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sdio_direct = -1;
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}
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return sdio_direct;
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}
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/*
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* Routine: get_expansion_id
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* Description: This function checks for expansion board by checking I2C
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* bus 2 for the availability of an AT24C01B serial EEPROM.
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* returns the device_vendor field from the EEPROM
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*/
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unsigned int get_expansion_id(void)
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{
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i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
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/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
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if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
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i2c_set_bus_num(TWL4030_I2C_BUS);
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return GUMSTIX_NO_EEPROM;
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}
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/* read configuration data */
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i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
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sizeof(expansion_config));
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i2c_set_bus_num(TWL4030_I2C_BUS);
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return expansion_config.device_vendor;
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
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#if defined(CONFIG_CMD_NET)
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setup_net_chip();
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#endif
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printf("Board revision: %d\n", get_board_revision());
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switch (get_sdio2_config()) {
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case 0:
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puts("Tranceiver detected on mmc2\n");
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MUX_OVERO_SDIO2_TRANSCEIVER();
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break;
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case 1:
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puts("Direct connection on mmc2\n");
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MUX_OVERO_SDIO2_DIRECT();
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break;
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default:
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puts("Unable to detect mmc2 connection type\n");
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}
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switch (get_expansion_id()) {
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case GUMSTIX_SUMMIT:
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printf("Recognized Summit expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "dvi");
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break;
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case GUMSTIX_TOBI:
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printf("Recognized Tobi expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "dvi");
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break;
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case GUMSTIX_TOBI_DUO:
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printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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/* second lan chip */
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
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0x2B000000, GPMC_SIZE_16M);
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||||
break;
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||||
case GUMSTIX_PALO35:
|
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printf("Recognized Palo35 expansion board (rev %d %s)\n",
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expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd35");
|
||||
break;
|
||||
case GUMSTIX_PALO43:
|
||||
printf("Recognized Palo43 expansion board (rev %d %s)\n",
|
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expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
break;
|
||||
case GUMSTIX_CHESTNUT43:
|
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printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
|
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expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
break;
|
||||
case GUMSTIX_PINTO:
|
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printf("Recognized Pinto expansion board (rev %d %s)\n",
|
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expansion_config.revision,
|
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expansion_config.fab_revision);
|
||||
break;
|
||||
case GUMSTIX_GALLOP43:
|
||||
printf("Recognized Gallop43 expansion board (rev %d %s)\n",
|
||||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
break;
|
||||
case ETTUS_USRP_E:
|
||||
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
|
||||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
MUX_USRP_E();
|
||||
setenv("defaultdisplay", "dvi");
|
||||
break;
|
||||
case GUMSTIX_NO_EEPROM:
|
||||
puts("No EEPROM on expansion board\n");
|
||||
break;
|
||||
default:
|
||||
puts("Unrecognized expansion board\n");
|
||||
}
|
||||
|
||||
if (expansion_config.content == 1)
|
||||
setenv(expansion_config.env_var, expansion_config.env_setting);
|
||||
|
||||
dieid_num_r();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_OVERO();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
/*
|
||||
* Routine: setup_net_chip
|
||||
* Description: Setting up the configuration GPMC registers specific to the
|
||||
* Ethernet hardware.
|
||||
*/
|
||||
static void setup_net_chip(void)
|
||||
{
|
||||
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
|
||||
|
||||
/* first lan chip */
|
||||
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
|
||||
GPMC_SIZE_16M);
|
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
|
||||
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
|
||||
&ctrl_base->gpmc_nadv_ale);
|
||||
|
||||
/* Make GPIO 64 as output pin and send a magic pulse through it */
|
||||
if (!gpio_request(64, "")) {
|
||||
gpio_direction_output(64, 0);
|
||||
gpio_set_value(64, 1);
|
||||
udelay(1);
|
||||
gpio_set_value(64, 0);
|
||||
udelay(1);
|
||||
gpio_set_value(64, 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_SMC911X
|
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
omap_mmc_init(0, 0, 0);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
422
common/package/utils/sysupgrade-helper/src/board/overo/overo.h
Normal file
422
common/package/utils/sysupgrade-helper/src/board/overo/overo.h
Normal file
|
|
@ -0,0 +1,422 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Steve Sakoman <steve@sakoman.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _OVERO_H_
|
||||
#define _OVERO_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
DDR_STACKED,
|
||||
"Gumstix Overo board",
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
"OneNAND",
|
||||
#else
|
||||
"NAND",
|
||||
#endif
|
||||
};
|
||||
|
||||
/* overo revisions */
|
||||
#define REVISION_0 0x0
|
||||
#define REVISION_1 0x1
|
||||
#define REVISION_2 0x2
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_OVERO() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
|
||||
/* - MMC1_WP*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
|
||||
/* - SMSC911X_NRES*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
|
||||
/* - PEN_DOWN*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/*Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
|
||||
/* BT_NRESET*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
/* - USBH_CPEN*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
/* - USBH_RESET*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
|
||||
/* - LAN_INTR */\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
|
||||
/* - W2W_NRESET*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
|
||||
/* die to die */\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
|
||||
|
||||
#define MUX_OVERO_SDIO2_DIRECT() \
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
|
||||
|
||||
#define MUX_OVERO_SDIO2_TRANSCEIVER() \
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
|
||||
|
||||
#define MUX_USRP_E() \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue