mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o fpga.o nand.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,231 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <asm/ppc4xx-emac.h>
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#include <miiphy.h>
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#include <asm/processor.h>
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#include <asm/4xx_pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int alpr_fpga_init(void);
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG
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*-------------------------------------------------------------------------*/
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mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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/*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC1ER, 0x00000000); /* disable all */
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mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (UIC1PR, 0xfffffe03); /* per manual */
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mtdcr (UIC1TR, 0x01c00000); /* per manual */
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mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC2ER, 0x00000000); /* disable all */
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mtdcr (UIC2CR, 0x00000000); /* all non-critical */
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mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
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mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC3ER, 0x00000000); /* disable all */
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mtdcr (UIC3CR, 0x00000000); /* all non-critical */
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mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC0SR, 0xfc000000); /* clear all */
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mtdcr (UIC0ER, 0x00000000); /* disable all */
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mtdcr (UIC0CR, 0x00000000); /* all non-critical */
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mtdcr (UIC0PR, 0xfc000000); /* */
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mtdcr (UIC0TR, 0x00000000); /* */
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mtdcr (UIC0VR, 0x00000001); /* */
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/* Setup shutdown/SSD empty interrupt as inputs */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
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/* Setup GPIO/IRQ multiplexing */
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mtsdr(SDR0_PFC0, 0x01a33e00);
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return 0;
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}
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int last_stage_init(void)
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{
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unsigned short reg;
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/*
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* Configure LED's of both Marvell 88E1111 PHY's
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*
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* This has to be done after the 4xx ethernet driver is loaded,
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* so "last_stage_init()" is the right place.
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*/
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miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
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miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
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return 0;
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}
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static int board_rev(void)
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{
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/* Setup as input */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
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return (in32(GPIO0_IR) >> 16) & 0x3;
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}
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int checkboard (void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf ("Board: ALPR");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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printf(" (Rev. %d)\n", board_rev());
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return (0);
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}
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#if defined(CONFIG_PCI)
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/*
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* Override weak pci_pre_init()
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*/
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int pci_pre_init(struct pci_controller *hose)
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{
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if (__pci_pre_init(hose) == 0)
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return 0;
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/* FPGA Init */
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alpr_fpga_init();
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return 1;
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}
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/*************************************************************************
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* Override weak is_pci_host()
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
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return;
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}
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}
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int is_pci_host(struct pci_controller *hose)
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{
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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| PowerPC440 PCI Master configuration.
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| Map PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r( PCIL0_POM0SA, 0 ); /* disable */
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out32r( PCIL0_POM1SA, 0 ); /* disable */
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out32r( PCIL0_POM2SA, 0 ); /* disable */
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out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
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@ -0,0 +1,32 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif
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@ -0,0 +1,256 @@
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/*
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*
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*/
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/*
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* Altera FPGA configuration support for the ALPR computer from prodrive
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*/
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#include <common.h>
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#include <altera.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/ppc440.h>
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt, args...) printf(fmt , ##args)
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#else
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#define PRINTF(fmt, args...)
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#endif
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static unsigned long regval;
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#define SET_GPIO_REG_0(reg, bit) do { \
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regval = in32(reg); \
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regval &= ~(0x80000000 >> bit); \
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out32(reg, regval); \
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} while (0)
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|
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#define SET_GPIO_REG_1(reg, bit) do { \
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regval = in32(reg); \
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regval |= (0x80000000 >> bit); \
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out32(reg, regval); \
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} while (0)
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#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
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#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
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#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
|
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#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
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#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
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#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
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#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
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|
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#define SET_FPGA(data) out32(GPIO0_OR, data)
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|
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#define FPGA_WRITE_1 do { \
|
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SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
|
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SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \
|
||||
} while (0)
|
||||
|
||||
#define FPGA_WRITE_0 do { \
|
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SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \
|
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SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \
|
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} while (0)
|
||||
|
||||
/* Plattforminitializations */
|
||||
/* Here we have to set the FPGA Chain */
|
||||
/* PROGRAM_PROG_EN = HIGH */
|
||||
/* PROGRAM_SEL_DPR = LOW */
|
||||
int fpga_pre_fn(int cookie)
|
||||
{
|
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/* Enable the FPGA Chain */
|
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
|
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SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
|
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
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SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
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/* initialize the GPIO Pins */
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/* output */
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SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
|
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|
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/* output */
|
||||
SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
|
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|
||||
/* First we set STATUS to 0 then as an input */
|
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
|
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SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
|
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SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
|
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|
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/* output */
|
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SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
|
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SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
|
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SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
|
||||
|
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/* input */
|
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SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
|
||||
SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
|
||||
|
||||
/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
|
||||
SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Set the state of CONFIG Pin */
|
||||
int fpga_config_fn(int assert_config, int flush, int cookie)
|
||||
{
|
||||
if (assert_config)
|
||||
SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
|
||||
else
|
||||
SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
|
||||
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Returns the state of STATUS Pin */
|
||||
int fpga_status_fn(int cookie)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
reg = in32(GPIO0_IR);
|
||||
if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
|
||||
PRINTF("STATUS = HIGH\n");
|
||||
return FPGA_FAIL;
|
||||
}
|
||||
PRINTF("STATUS = LOW\n");
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Returns the state of CONF_DONE Pin */
|
||||
int fpga_done_fn(int cookie)
|
||||
{
|
||||
unsigned long reg;
|
||||
reg = in32(GPIO0_IR);
|
||||
if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
|
||||
PRINTF("CONF_DON = HIGH\n");
|
||||
return FPGA_FAIL;
|
||||
}
|
||||
PRINTF("CONF_DON = LOW\n");
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* writes the complete buffer to the FPGA
|
||||
writing the complete buffer in one function is much faster,
|
||||
then calling it for every bit */
|
||||
int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
|
||||
{
|
||||
size_t bytecount = 0;
|
||||
unsigned char *data = (unsigned char *) buf;
|
||||
unsigned char val = 0;
|
||||
int i;
|
||||
int len_40 = len / 40;
|
||||
|
||||
while (bytecount < len) {
|
||||
val = data[bytecount++];
|
||||
i = 8;
|
||||
do {
|
||||
if (val & 0x01)
|
||||
FPGA_WRITE_1;
|
||||
else
|
||||
FPGA_WRITE_0;
|
||||
|
||||
val >>= 1;
|
||||
i--;
|
||||
} while (i > 0);
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
if (bytecount % len_40 == 0) {
|
||||
putc('.'); /* let them know we are alive */
|
||||
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
|
||||
if (ctrlc())
|
||||
return FPGA_FAIL;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming is aborted */
|
||||
int fpga_abort_fn(int cookie)
|
||||
{
|
||||
SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming was succesful */
|
||||
int fpga_post_fn(int cookie)
|
||||
{
|
||||
return fpga_abort_fn(cookie);
|
||||
}
|
||||
|
||||
/* Note that these are pointers to code that is in Flash. They will be
|
||||
* relocated at runtime.
|
||||
*/
|
||||
Altera_CYC2_Passive_Serial_fns fpga_fns = {
|
||||
fpga_pre_fn,
|
||||
fpga_config_fn,
|
||||
fpga_status_fn,
|
||||
fpga_done_fn,
|
||||
fpga_write_fn,
|
||||
fpga_abort_fn,
|
||||
fpga_post_fn
|
||||
};
|
||||
|
||||
Altera_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
{Altera_CYC2,
|
||||
passive_serial,
|
||||
Altera_EP2C35_SIZE,
|
||||
(void *) &fpga_fns,
|
||||
NULL,
|
||||
0}
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||
*/
|
||||
int alpr_fpga_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__);
|
||||
fpga_init();
|
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
|
||||
PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
|
||||
fpga_add(fpga_altera, &fpga[i]);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm-offsets.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
|
||||
#else
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
|
||||
#endif
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
||||
|
||||
/* PCI */
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
|
||||
|
||||
/* NAND */
|
||||
tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <nand.h>
|
||||
|
||||
struct alpr_ndfc_regs {
|
||||
u8 cmd[4];
|
||||
u8 addr_wait;
|
||||
u8 term;
|
||||
u8 dummy;
|
||||
u8 dummy2;
|
||||
u8 data;
|
||||
};
|
||||
|
||||
static u8 hwctl;
|
||||
static struct alpr_ndfc_regs *alpr_ndfc = NULL;
|
||||
|
||||
#define readb(addr) (u8)(*(volatile u8 *)(addr))
|
||||
#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
|
||||
|
||||
/*
|
||||
* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
|
||||
* the NAND devices. The NDFC has command, address and data registers that
|
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the
|
||||
* hwcontrol function to save the configuration in a global variable.
|
||||
* We can then use this information in the read and write functions to
|
||||
* determine which NDFC register to access.
|
||||
*
|
||||
* There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
|
||||
*/
|
||||
static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
hwctl |= 0x1;
|
||||
else
|
||||
hwctl &= ~0x1;
|
||||
if ( ctrl & NAND_ALE )
|
||||
hwctl |= 0x2;
|
||||
else
|
||||
hwctl &= ~0x2;
|
||||
if ( (ctrl & NAND_NCE) != NAND_NCE)
|
||||
writeb(0x00, &(alpr_ndfc->term));
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static u_char alpr_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
return readb(&(alpr_ndfc->data));
|
||||
}
|
||||
|
||||
static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand = mtd->priv;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (hwctl & 0x1)
|
||||
/*
|
||||
* IO_ADDR_W used as CMD[i] reg to support multiple NAND
|
||||
* chips.
|
||||
*/
|
||||
writeb(buf[i], nand->IO_ADDR_W);
|
||||
else if (hwctl & 0x2)
|
||||
writeb(buf[i], &(alpr_ndfc->addr_wait));
|
||||
else
|
||||
writeb(buf[i], &(alpr_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = readb(&(alpr_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
if (buf[i] != readb(&(alpr_ndfc->data)))
|
||||
return i;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int alpr_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
/*
|
||||
* Blocking read to wait for NAND to be ready
|
||||
*/
|
||||
(void)readb(&(alpr_ndfc->addr_wait));
|
||||
|
||||
/*
|
||||
* Return always true
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
|
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Reference hardware control function */
|
||||
nand->cmd_ctrl = alpr_nand_hwcontrol;
|
||||
nand->read_byte = alpr_nand_read_byte;
|
||||
nand->write_buf = alpr_nand_write_buf;
|
||||
nand->read_buf = alpr_nand_read_buf;
|
||||
nand->verify_buf = alpr_nand_verify_buf;
|
||||
nand->dev_ready = alpr_nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,560 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
static int write_word(flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
void flash_print_info(flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int size;
|
||||
int erased;
|
||||
volatile unsigned long *flash;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
case FLASH_MAN_SST: printf ("SST "); break;
|
||||
case FLASH_MAN_STM: printf ("ST "); break;
|
||||
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
if (i != (info->sector_count-1))
|
||||
size = info->start[i+1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
erased = 1;
|
||||
flash = (volatile unsigned long *)info->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k=0; k<size; k++) {
|
||||
if (*flash++ != 0xffffffff) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
/* print empty and read-only info */
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " ");
|
||||
#else
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
#endif
|
||||
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size(vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
short n;
|
||||
CONFIG_SYS_FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong)addr;
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
|
||||
|
||||
value = addr2[CONFIG_SYS_FLASH_READ0];
|
||||
|
||||
switch (value) {
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_STM;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_EXCEL;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
|
||||
info->flash_id += FLASH_AMDL322T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
|
||||
info->flash_id += FLASH_AMDL322B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
|
||||
info->flash_id += FLASH_AMDL323T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
|
||||
info->flash_id += FLASH_SST020;
|
||||
info->sector_count = 64;
|
||||
info->size = 0x00040000;
|
||||
break; /* => 256 kB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
|
||||
info->flash_id += FLASH_SST040;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 512 kB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00001000);
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
while (i < info->sector_count) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
|
||||
/* set sector offsets for top boot block type */
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
|
||||
*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
printf ("- missing\n");
|
||||
else
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect)
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
|
||||
if (prot)
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
|
||||
else
|
||||
printf ("\n");
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag) {
|
||||
enable_interrupts();
|
||||
flag = 0;
|
||||
}
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
|
||||
(CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
|
||||
return (1);
|
||||
}
|
||||
} else {
|
||||
if (sect == s_first) {
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
}
|
||||
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
|
||||
while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i)
|
||||
data = (data << 8) | *src++;
|
||||
if ((rc = write_word(info, wp, data)) != 0)
|
||||
return (rc);
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word(flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data)
|
||||
return (2);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2001-2004
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
#define DBG(x...) printf(x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
#define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
|
||||
#define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */
|
||||
#define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */
|
||||
#define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */
|
||||
#define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */
|
||||
|
||||
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
|
||||
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
|
||||
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
|
||||
|
||||
#ifndef OLD_VAL
|
||||
# define OLD_VAL 0
|
||||
#endif
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define FPGA_WRITE_1 { \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
|
||||
|
||||
#define FPGA_WRITE_0 { \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 ); /* set clock to 1 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
|
||||
#else
|
||||
#define FPGA_WRITE_1 { \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
|
||||
|
||||
#define FPGA_WRITE_0 { \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \
|
||||
SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 );} /* set data to 1 */
|
||||
#endif
|
||||
|
||||
static int fpga_boot(unsigned char *fpgadata, int size)
|
||||
{
|
||||
int i,index,len;
|
||||
int count;
|
||||
int j;
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i=0; i<4; i++) {
|
||||
len = fpgadata[index];
|
||||
DBG("FPGA: %s\n", &(fpgadata[index+1]));
|
||||
index += len+3;
|
||||
}
|
||||
|
||||
/* search for preamble 0xFFFFFFFF */
|
||||
while (1) {
|
||||
if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
|
||||
(fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
|
||||
break; /* preamble found */
|
||||
else
|
||||
index++;
|
||||
}
|
||||
|
||||
DBG("FPGA: configdata starts at position 0x%x\n",index);
|
||||
DBG("FPGA: length of fpga-data %d\n", size-index);
|
||||
|
||||
/*
|
||||
* Setup port pins for fpga programming
|
||||
*/
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
|
||||
|
||||
DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
|
||||
DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
|
||||
|
||||
/*
|
||||
* Init fpga by asserting and deasserting PROGRAM*
|
||||
*/
|
||||
SET_FPGA(0 | FPGA_CLK | FPGA_DATA); /* set prog active */
|
||||
|
||||
/* Wait for FPGA init line low */
|
||||
count = 0;
|
||||
while (FPGA_INIT_STATE) {
|
||||
udelay(1000); /* wait 1ms */
|
||||
/* Check for timeout - 100us max, so use 3ms */
|
||||
if (count++ > 3) {
|
||||
DBG("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
|
||||
DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
|
||||
|
||||
/* deassert PROGRAM* */
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set prog inactive */
|
||||
|
||||
/* Wait for FPGA end of init period . */
|
||||
count = 0;
|
||||
while (!(FPGA_INIT_STATE)) {
|
||||
udelay(1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_HIGH;
|
||||
}
|
||||
}
|
||||
|
||||
DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
|
||||
DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
|
||||
|
||||
DBG("write configuration data into fpga\n");
|
||||
/* write configuration-data into fpga... */
|
||||
|
||||
/*
|
||||
* Load uncompressed image into fpga
|
||||
*/
|
||||
for (i=index; i<size; i++) {
|
||||
for (j=0; j<8; j++) {
|
||||
if ((fpgadata[i] & 0x80) == 0x80) {
|
||||
FPGA_WRITE_1;
|
||||
} else {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
fpgadata[i] <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
|
||||
DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
|
||||
|
||||
/*
|
||||
* Check if fpga's DONE signal - correctly booted ?
|
||||
*/
|
||||
|
||||
/* Wait for FPGA end of programming period . */
|
||||
count = 0;
|
||||
while (!(FPGA_DONE_STATE)) {
|
||||
udelay(1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
DBG("FPGA: Booting successful!\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* main board support/init for the Galileo Eval board DB64460.
|
||||
*/
|
||||
|
||||
#ifndef __64460_H__
|
||||
#define __64460_H__
|
||||
|
||||
/* CPU Configuration bits */
|
||||
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
|
||||
#define CPU_CONF_SINGLE_CPU (1 << 11)
|
||||
#define CPU_CONF_ENDIANESS (1 << 12)
|
||||
#define CPU_CONF_PIPELINE (1 << 13)
|
||||
#define CPU_CONF_STOP_RETRY (1 << 17)
|
||||
#define CPU_CONF_MULTI_DECODE (1 << 18)
|
||||
#define CPU_CONF_DP_VALID (1 << 19)
|
||||
#define CPU_CONF_PERR_PROP (1 << 22)
|
||||
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
|
||||
#define CPU_CONF_AP_VALID (1 << 26)
|
||||
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
|
||||
|
||||
/* CPU Master Control bits */
|
||||
#define CPU_MAST_CTL_ARB_EN (1 << 8)
|
||||
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
|
||||
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
|
||||
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
|
||||
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
|
||||
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
|
||||
|
||||
#endif /* __64460_H__ */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../../Marvell/common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
SOBJS = misc.o
|
||||
COBJS = $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
|
||||
../../Marvell/common/i2c.o ../../Marvell/common/memory.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __EVB64360_ETH_H__
|
||||
#define __EVB64360_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
|
||||
|
||||
int db64360_eth0_poll(void);
|
||||
int db64360_eth0_transmit(unsigned int s, volatile char *p);
|
||||
void db64360_eth0_disable(void);
|
||||
bool network_start(bd_t *bis);
|
||||
|
||||
int mv6446x_eth_initialize(bd_t *);
|
||||
|
||||
#endif /* __EVB64360_ETH_H__ */
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
#include <config.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "version.h"
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
#ifdef CONFIG_ECC
|
||||
/* Galileo specific asm code for initializing ECC */
|
||||
.globl board_relocate_rom
|
||||
board_relocate_rom:
|
||||
mflr r7
|
||||
/* update the location of the GT registers */
|
||||
lis r11, CONFIG_SYS_GT_REGS@h
|
||||
/* if we're using ECC, we must use the DMA engine to copy ourselves */
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
.globl board_init_ecc
|
||||
board_init_ecc:
|
||||
mflr r7
|
||||
/* NOTE: r10 still contains the location we've been relocated to
|
||||
* which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
|
||||
|
||||
/* now that we're running from ram, init the rest of main memory
|
||||
* for ECC use */
|
||||
lis r8, CONFIG_SYS_MONITOR_LEN@h
|
||||
ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
|
||||
|
||||
divw r3, r10, r8
|
||||
|
||||
/* set up the counter, and init the starting address */
|
||||
mtctr r3
|
||||
li r12, 0
|
||||
|
||||
/* bytes per transfer */
|
||||
mr r5, r8
|
||||
about_to_init_ecc:
|
||||
1: mr r3, r12
|
||||
mr r4, r12
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
add r12, r12, r8
|
||||
bdnz 1b
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
/* r3: dest addr
|
||||
* r4: source addr
|
||||
* r5: byte count
|
||||
* r11: gt regbase
|
||||
* trashes: r6, r5
|
||||
*/
|
||||
start_idma_transfer_0:
|
||||
/* set the byte count, including the OWN bit */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the source address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
|
||||
stwbrx r4, 0, (r6)
|
||||
|
||||
/* set the dest address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
|
||||
stwbrx r3, 0, (r6)
|
||||
|
||||
/* set the next record pointer */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the low control register */
|
||||
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
|
||||
bit 12 is channel enable */
|
||||
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
|
||||
/* 15 shifted by 16 (oris) == bit 31 */
|
||||
oris r5, r5, (1 << 15)
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
|
||||
/* this waits for the bytecount to return to zero, indicating
|
||||
* that the trasfer is complete */
|
||||
wait_for_idma_0:
|
||||
mr r5, r11
|
||||
lis r6, 0xff
|
||||
ori r6, r6, 0xffff
|
||||
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
|
||||
1: lwbrx r4, 0, (r5)
|
||||
and. r4, r4, r6
|
||||
bne 1b
|
||||
|
||||
blr
|
||||
|
||||
/* this turns off channel 0 of the idma engine */
|
||||
stop_idma_engine_0:
|
||||
/* shut off the DMA engine */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_BOARD_ASM_INIT
|
||||
/* NOTE: trashes r3-r7 */
|
||||
.globl board_asm_init
|
||||
board_asm_init:
|
||||
/* just move the GT registers to where they belong */
|
||||
lis r3, CONFIG_SYS_DFL_GT_REGS@h
|
||||
ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
|
||||
lis r4, CONFIG_SYS_GT_REGS@h
|
||||
ori r4, r4, CONFIG_SYS_GT_REGS@l
|
||||
li r5, INTERNAL_SPACE_DECODE
|
||||
|
||||
/* test to see if we've already moved */
|
||||
lwbrx r6, r5, r4
|
||||
andi. r6, r6, 0xffff
|
||||
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
|
||||
/* rlwinm r7, r4, 8, 16, 31
|
||||
rlwinm r7, r4, 12, 16, 31 */ /* original */
|
||||
rlwinm r7, r4, 16, 16, 31
|
||||
/* -----------------------------------------------------*/
|
||||
cmp cr0, r7, r6
|
||||
beqlr
|
||||
|
||||
/* nope, have to move the registers */
|
||||
lwbrx r6, r5, r3
|
||||
andis. r6, r6, 0xffff
|
||||
or r6, r6, r7
|
||||
stwbrx r6, r5, r3
|
||||
|
||||
/* now, poll for the change */
|
||||
1: lwbrx r7, r5, r4
|
||||
cmp cr0, r7, r6
|
||||
bne 1b
|
||||
|
||||
lis r3, CONFIG_SYS_INT_SRAM_BASE@h
|
||||
ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
|
||||
rlwinm r3, r3, 16, 16, 31
|
||||
lis r4, CONFIG_SYS_GT_REGS@h
|
||||
ori r4, r4, CONFIG_SYS_GT_REGS@l
|
||||
li r5, INTEGRATED_SRAM_BASE_ADDR
|
||||
stwbrx r3, r5, r4
|
||||
|
||||
2: lwbrx r6, r5, r4
|
||||
cmp cr0, r3, r6
|
||||
bne 2b
|
||||
|
||||
/* done! */
|
||||
blr
|
||||
#endif
|
||||
|
||||
/* For use of the debug LEDs */
|
||||
.global led_on0_relocated
|
||||
led_on0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0_relocated
|
||||
led_off0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on0
|
||||
led_on0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0
|
||||
led_off0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on1
|
||||
led_on1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off1
|
||||
led_off1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on2
|
||||
led_on2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x0000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off2
|
||||
led_off2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* mpsc.h - header file for MPSC in uart mode (console driver)
|
||||
*/
|
||||
|
||||
#ifndef __MPSC_H__
|
||||
#define __MPSC_H__
|
||||
|
||||
/* include actual Galileo defines */
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
/* driver related defines */
|
||||
|
||||
int mpsc_init(int baud);
|
||||
void mpsc_sdma_init(void);
|
||||
void mpsc_init2(void);
|
||||
int galbrg_set_baudrate(int channel, int rate);
|
||||
|
||||
int mpsc_putchar_early(char ch);
|
||||
char mpsc_getchar_debug(void);
|
||||
int mpsc_test_char_debug(void);
|
||||
|
||||
int mpsc_test_char_sdma(void);
|
||||
|
||||
extern int (*mpsc_putchar)(char ch);
|
||||
extern char (*mpsc_getchar)(void);
|
||||
extern int (*mpsc_test_char)(void);
|
||||
|
||||
#define CHANNEL CONFIG_MPSC_PORT
|
||||
|
||||
#define TX_DESC 5
|
||||
#define RX_DESC 20
|
||||
|
||||
#define DESC_FIRST 0x00010000
|
||||
#define DESC_LAST 0x00020000
|
||||
#define DESC_OWNER_BIT 0x80000000
|
||||
|
||||
#define TX_DEMAND 0x00800000
|
||||
#define TX_STOP 0x00010000
|
||||
#define RX_ENABLE 0x00000080
|
||||
|
||||
#define SDMA_RX_ABORT (1 << 15)
|
||||
#define SDMA_TX_ABORT (1 << 31)
|
||||
#define MPSC_TX_ABORT (1 << 7)
|
||||
#define MPSC_RX_ABORT (1 << 23)
|
||||
#define MPSC_ENTER_HUNT (1 << 31)
|
||||
|
||||
/* MPSC defines */
|
||||
|
||||
#define GALMPSC_CONNECT 0x1
|
||||
#define GALMPSC_DISCONNECT 0x0
|
||||
|
||||
#define GALMPSC_UART 0x1
|
||||
|
||||
#define GALMPSC_STOP_BITS_1 0x0
|
||||
#define GALMPSC_STOP_BITS_2 0x1
|
||||
#define GALMPSC_CHAR_LENGTH_8 0x3
|
||||
#define GALMPSC_CHAR_LENGTH_7 0x2
|
||||
|
||||
#define GALMPSC_PARITY_ODD 0x0
|
||||
#define GALMPSC_PARITY_EVEN 0x2
|
||||
#define GALMPSC_PARITY_MARK 0x3
|
||||
#define GALMPSC_PARITY_SPACE 0x1
|
||||
#define GALMPSC_PARITY_NONE -1
|
||||
|
||||
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
|
||||
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
|
||||
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
|
||||
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
|
||||
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
|
||||
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
|
||||
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
|
||||
|
||||
#define GALMPSC_REG_GAP 0x1000
|
||||
|
||||
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
|
||||
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
|
||||
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
|
||||
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
|
||||
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
|
||||
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
|
||||
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
|
||||
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
|
||||
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
|
||||
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
|
||||
|
||||
#define GALSDMA_COMMAND_FIRST (1 << 16)
|
||||
#define GALSDMA_COMMAND_LAST (1 << 17)
|
||||
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
|
||||
#define GALSDMA_COMMAND_AUTO (1 << 30)
|
||||
#define GALSDMA_COMMAND_OWNER (1 << 31)
|
||||
|
||||
#define GALSDMA_RX 0
|
||||
#define GALSDMA_TX 1
|
||||
|
||||
/* CHANNEL2 should be CHANNEL1, according to documentation,
|
||||
* but to work with the current GTREGS file...
|
||||
*/
|
||||
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
|
||||
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
|
||||
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
|
||||
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
|
||||
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
|
||||
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
|
||||
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
|
||||
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
|
||||
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
|
||||
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
|
||||
#define GALSDMA_REG_DIFF 0x2000
|
||||
|
||||
/* WRONG in gt64260R.h */
|
||||
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
|
||||
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
|
||||
#define GALMPSC_0_INT_CAUSE 0xb804
|
||||
#define GALMPSC_0_INT_MASK 0xb884
|
||||
|
||||
#define GALSDMA_MODE_UART 0
|
||||
#define GALSDMA_MODE_BISYNC 1
|
||||
#define GALSDMA_MODE_HDLC 2
|
||||
#define GALSDMA_MODE_TRANSPARENT 3
|
||||
|
||||
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
|
||||
#define GALBRG_REG_GAP 0x0008
|
||||
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
|
||||
|
||||
#endif /* __MPSC_H__ */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,838 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* based on - Driver for MV64460X ethernet ports
|
||||
* Copyright (C) 2002 rabeeh@galileo.co.il
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* mv_eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __DB64460_ETH_H__
|
||||
#define __DB64460_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include "mv_regs.h"
|
||||
#include <asm/errno.h>
|
||||
#include "../../Marvell/include/core.h"
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The first part is the high level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
|
||||
#ifndef MAX_SKB_FRAGS
|
||||
#define MAX_SKB_FRAGS 0
|
||||
#endif
|
||||
|
||||
/* Port attributes */
|
||||
/*#define MAX_RX_QUEUE_NUM 8*/
|
||||
/*#define MAX_TX_QUEUE_NUM 8*/
|
||||
#define MAX_RX_QUEUE_NUM 1
|
||||
#define MAX_TX_QUEUE_NUM 1
|
||||
|
||||
|
||||
/* Use one TX queue and one RX queue */
|
||||
#define MV64460_TX_QUEUE_NUM 1
|
||||
#define MV64460_RX_QUEUE_NUM 1
|
||||
|
||||
/*
|
||||
* Number of RX / TX descriptors on RX / TX rings.
|
||||
* Note that allocating RX descriptors is done by allocating the RX
|
||||
* ring AND a preallocated RX buffers (skb's) for each descriptor.
|
||||
* The TX descriptors only allocates the TX descriptors ring,
|
||||
* with no pre allocated TX buffers (skb's are allocated by higher layers.
|
||||
*/
|
||||
|
||||
/* Default TX ring size is 10 descriptors */
|
||||
#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
|
||||
#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64460_TX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
/* Default RX ring size is 4 descriptors */
|
||||
#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
|
||||
#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64460_RX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RX_BUFFER_SIZE
|
||||
#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64460_RX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TX_BUFFER_SIZE
|
||||
#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64460_TX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Network device statistics. Akin to the 2.0 ether stats but
|
||||
* with byte counters.
|
||||
*/
|
||||
|
||||
struct net_device_stats
|
||||
{
|
||||
unsigned long rx_packets; /* total packets received */
|
||||
unsigned long tx_packets; /* total packets transmitted */
|
||||
unsigned long rx_bytes; /* total bytes received */
|
||||
unsigned long tx_bytes; /* total bytes transmitted */
|
||||
unsigned long rx_errors; /* bad packets received */
|
||||
unsigned long tx_errors; /* packet transmit problems */
|
||||
unsigned long rx_dropped; /* no space in linux buffers */
|
||||
unsigned long tx_dropped; /* no space available in linux */
|
||||
unsigned long multicast; /* multicast packets received */
|
||||
unsigned long collisions;
|
||||
|
||||
/* detailed rx_errors: */
|
||||
unsigned long rx_length_errors;
|
||||
unsigned long rx_over_errors; /* receiver ring buff overflow */
|
||||
unsigned long rx_crc_errors; /* recved pkt with crc error */
|
||||
unsigned long rx_frame_errors; /* recv'd frame alignment error */
|
||||
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
|
||||
unsigned long rx_missed_errors; /* receiver missed packet */
|
||||
|
||||
/* detailed tx_errors */
|
||||
unsigned long tx_aborted_errors;
|
||||
unsigned long tx_carrier_errors;
|
||||
unsigned long tx_fifo_errors;
|
||||
unsigned long tx_heartbeat_errors;
|
||||
unsigned long tx_window_errors;
|
||||
|
||||
/* for cslip etc */
|
||||
unsigned long rx_compressed;
|
||||
unsigned long tx_compressed;
|
||||
};
|
||||
|
||||
|
||||
/* Private data structure used for ethernet device */
|
||||
struct mv64460_eth_priv {
|
||||
unsigned int port_num;
|
||||
struct net_device_stats *stats;
|
||||
|
||||
/* to buffer area aligned */
|
||||
char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
|
||||
char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
|
||||
|
||||
/* Size of Tx Ring per queue */
|
||||
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
|
||||
|
||||
/* Size of Rx Ring per queue */
|
||||
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Magic Number for Ethernet running */
|
||||
unsigned int eth_running;
|
||||
|
||||
int first_init;
|
||||
};
|
||||
|
||||
int mv64460_eth_init (struct eth_device *dev);
|
||||
int mv64460_eth_stop (struct eth_device *dev);
|
||||
int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
|
||||
int mv64460_eth_open (struct eth_device *dev);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The second part is the low level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
* Header File for : MV-643xx network interface header
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This header file contains macros typedefs and function declaration for
|
||||
* the Marvell Gig Bit Ethernet Controller.
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
|
||||
#ifdef CONFIG_MV64460_SRAM_CACHEABLE
|
||||
/* In case SRAM is cacheable but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case SRAM is cache coherent or non-cacheable */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif
|
||||
#else
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
/* In case of descriptors on DDR but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case of descriptors on DDR and cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif /* CONFIG_NOT_COHERENT_CACHE */
|
||||
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
|
||||
|
||||
|
||||
#define CPU_PIPE_FLUSH \
|
||||
{ \
|
||||
__asm__ __volatile__ ("eieio"); \
|
||||
}
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
/* Default port configuration value */
|
||||
#define PORT_CONFIG_VALUE \
|
||||
ETH_UNICAST_NORMAL_MODE | \
|
||||
ETH_DEFAULT_RX_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
|
||||
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
|
||||
ETH_RECEIVE_BC_IF_IP | \
|
||||
ETH_RECEIVE_BC_IF_ARP | \
|
||||
ETH_CAPTURE_TCP_FRAMES_DIS | \
|
||||
ETH_CAPTURE_UDP_FRAMES_DIS | \
|
||||
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_BPDU_QUEUE_0
|
||||
|
||||
/* Default port extend configuration value */
|
||||
#define PORT_CONFIG_EXTEND_VALUE \
|
||||
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
|
||||
ETH_PARTITION_DISABLE
|
||||
|
||||
|
||||
/* Default sdma control value */
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_16_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_16_64BIT;
|
||||
#else
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_4_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_4_64BIT;
|
||||
#endif
|
||||
|
||||
#define GT_ETH_IPG_INT_RX(value) \
|
||||
((value & 0x3fff) << 8)
|
||||
|
||||
/* Default port serial control value */
|
||||
#define PORT_SERIAL_CONTROL_VALUE \
|
||||
ETH_FORCE_LINK_PASS | \
|
||||
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
|
||||
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
|
||||
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
|
||||
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
|
||||
ETH_FORCE_BP_MODE_NO_JAM | \
|
||||
BIT9 | \
|
||||
ETH_DO_NOT_FORCE_LINK_FAIL | \
|
||||
ETH_RETRANSMIT_16_ETTEMPTS | \
|
||||
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
|
||||
ETH_DTE_ADV_0 | \
|
||||
ETH_DISABLE_AUTO_NEG_BYPASS | \
|
||||
ETH_AUTO_NEG_NO_CHANGE | \
|
||||
ETH_MAX_RX_PACKET_1552BYTE | \
|
||||
ETH_CLR_EXT_LOOPBACK | \
|
||||
ETH_SET_FULL_DUPLEX_MODE | \
|
||||
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
|
||||
|
||||
#define RX_BUFFER_MAX_SIZE 0xFFFF
|
||||
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
|
||||
|
||||
#define RX_BUFFER_MIN_SIZE 0x8
|
||||
#define TX_BUFFER_MIN_SIZE 0x8
|
||||
|
||||
/* Tx WRR confoguration macros */
|
||||
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
|
||||
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
|
||||
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
|
||||
|
||||
/* MAC accepet/reject macros */
|
||||
#define ACCEPT_MAC_ADDR 0
|
||||
#define REJECT_MAC_ADDR 1
|
||||
|
||||
/* Size of a Tx/Rx descriptor used in chain list data structure */
|
||||
#define RX_DESC_ALIGNED_SIZE 0x20
|
||||
#define TX_DESC_ALIGNED_SIZE 0x20
|
||||
|
||||
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
|
||||
#define TX_BUF_OFFSET_IN_DESC 0x18
|
||||
/* Buffer offset from buffer pointer */
|
||||
#define RX_BUF_OFFSET 0x2
|
||||
|
||||
/* Gap define */
|
||||
#define ETH_BAR_GAP 0x8
|
||||
#define ETH_SIZE_REG_GAP 0x8
|
||||
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
|
||||
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
|
||||
|
||||
/* Gigabit Ethernet Unit Global Registers */
|
||||
|
||||
/* MIB Counters register definitions */
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
|
||||
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
|
||||
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
|
||||
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
|
||||
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
|
||||
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
|
||||
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
|
||||
#define ETH_MIB_FRAMES_64_OCTETS 0x20
|
||||
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
|
||||
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
|
||||
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
|
||||
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
|
||||
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
|
||||
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
|
||||
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
|
||||
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
|
||||
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
|
||||
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
|
||||
#define ETH_MIB_FC_SENT 0x54
|
||||
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
|
||||
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
|
||||
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
|
||||
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
|
||||
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
|
||||
#define ETH_MIB_JABBER_RECEIVED 0x6c
|
||||
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
|
||||
#define ETH_MIB_BAD_CRC_EVENT 0x74
|
||||
#define ETH_MIB_COLLISION 0x78
|
||||
#define ETH_MIB_LATE_COLLISION 0x7c
|
||||
|
||||
/* Port serial status reg (PSR) */
|
||||
#define ETH_INTERFACE_GMII_MII 0
|
||||
#define ETH_INTERFACE_PCM BIT0
|
||||
#define ETH_LINK_IS_DOWN 0
|
||||
#define ETH_LINK_IS_UP BIT1
|
||||
#define ETH_PORT_AT_HALF_DUPLEX 0
|
||||
#define ETH_PORT_AT_FULL_DUPLEX BIT2
|
||||
#define ETH_RX_FLOW_CTRL_DISABLED 0
|
||||
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
|
||||
#define ETH_GMII_SPEED_100_10 0
|
||||
#define ETH_GMII_SPEED_1000 BIT4
|
||||
#define ETH_MII_SPEED_10 0
|
||||
#define ETH_MII_SPEED_100 BIT5
|
||||
#define ETH_NO_TX 0
|
||||
#define ETH_TX_IN_PROGRESS BIT7
|
||||
#define ETH_BYPASS_NO_ACTIVE 0
|
||||
#define ETH_BYPASS_ACTIVE BIT8
|
||||
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
|
||||
#define ETH_PORT_AT_PARTITION_STATE BIT9
|
||||
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
|
||||
#define ETH_PORT_TX_FIFO_EMPTY BIT10
|
||||
|
||||
|
||||
/* These macros describes the Port configuration reg (Px_cR) bits */
|
||||
#define ETH_UNICAST_NORMAL_MODE 0
|
||||
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
|
||||
#define ETH_DEFAULT_RX_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
|
||||
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
|
||||
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
|
||||
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
|
||||
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
|
||||
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
|
||||
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
|
||||
#define ETH_RECEIVE_BC_IF_IP 0
|
||||
#define ETH_REJECT_BC_IF_IP BIT8
|
||||
#define ETH_RECEIVE_BC_IF_ARP 0
|
||||
#define ETH_REJECT_BC_IF_ARP BIT9
|
||||
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
|
||||
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
|
||||
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
|
||||
|
||||
|
||||
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
|
||||
#define ETH_CLASSIFY_EN BIT0
|
||||
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
|
||||
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
|
||||
#define ETH_PARTITION_DISABLE 0
|
||||
#define ETH_PARTITION_ENABLE BIT2
|
||||
|
||||
|
||||
/* Tx/Rx queue command reg (RQCR/TQCR)*/
|
||||
#define ETH_QUEUE_0_ENABLE BIT0
|
||||
#define ETH_QUEUE_1_ENABLE BIT1
|
||||
#define ETH_QUEUE_2_ENABLE BIT2
|
||||
#define ETH_QUEUE_3_ENABLE BIT3
|
||||
#define ETH_QUEUE_4_ENABLE BIT4
|
||||
#define ETH_QUEUE_5_ENABLE BIT5
|
||||
#define ETH_QUEUE_6_ENABLE BIT6
|
||||
#define ETH_QUEUE_7_ENABLE BIT7
|
||||
#define ETH_QUEUE_0_DISABLE BIT8
|
||||
#define ETH_QUEUE_1_DISABLE BIT9
|
||||
#define ETH_QUEUE_2_DISABLE BIT10
|
||||
#define ETH_QUEUE_3_DISABLE BIT11
|
||||
#define ETH_QUEUE_4_DISABLE BIT12
|
||||
#define ETH_QUEUE_5_DISABLE BIT13
|
||||
#define ETH_QUEUE_6_DISABLE BIT14
|
||||
#define ETH_QUEUE_7_DISABLE BIT15
|
||||
|
||||
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
|
||||
#define ETH_RIFB BIT0
|
||||
#define ETH_RX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
|
||||
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
|
||||
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
|
||||
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
|
||||
#define ETH_BLM_RX_NO_SWAP BIT4
|
||||
#define ETH_BLM_RX_BYTE_SWAP 0
|
||||
#define ETH_BLM_TX_NO_SWAP BIT5
|
||||
#define ETH_BLM_TX_BYTE_SWAP 0
|
||||
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
|
||||
#define ETH_DESCRIPTORS_NO_SWAP 0
|
||||
#define ETH_TX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
|
||||
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
|
||||
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
|
||||
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
|
||||
|
||||
/* These macros describes the Port serial control reg (PSCR) bits */
|
||||
#define ETH_SERIAL_PORT_DISABLE 0
|
||||
#define ETH_SERIAL_PORT_ENABLE BIT0
|
||||
#define ETH_FORCE_LINK_PASS BIT1
|
||||
#define ETH_DO_NOT_FORCE_LINK_PASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
|
||||
#define ETH_ADV_NO_FLOW_CTRL 0
|
||||
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
|
||||
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
|
||||
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
|
||||
#define ETH_FORCE_BP_MODE_NO_JAM 0
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
|
||||
#define ETH_FORCE_LINK_FAIL 0
|
||||
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
|
||||
#define ETH_RETRANSMIT_16_ETTEMPTS 0
|
||||
#define ETH_RETRANSMIT_FOREVER BIT11
|
||||
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
|
||||
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
|
||||
#define ETH_DTE_ADV_0 0
|
||||
#define ETH_DTE_ADV_1 BIT14
|
||||
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
|
||||
#define ETH_AUTO_NEG_NO_CHANGE 0
|
||||
#define ETH_RESTART_AUTO_NEG BIT16
|
||||
#define ETH_MAX_RX_PACKET_1518BYTE 0
|
||||
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
|
||||
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
|
||||
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
|
||||
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
|
||||
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
|
||||
#define ETH_SET_EXT_LOOPBACK BIT20
|
||||
#define ETH_CLR_EXT_LOOPBACK 0
|
||||
#define ETH_SET_FULL_DUPLEX_MODE BIT21
|
||||
#define ETH_SET_HALF_DUPLEX_MODE 0
|
||||
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
|
||||
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
|
||||
#define ETH_SET_GMII_SPEED_TO_10_100 0
|
||||
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
|
||||
#define ETH_SET_MII_SPEED_TO_10 0
|
||||
#define ETH_SET_MII_SPEED_TO_100 BIT24
|
||||
|
||||
|
||||
/* SMI reg */
|
||||
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
|
||||
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
|
||||
|
||||
/* SDMA command status fields macros */
|
||||
|
||||
/* Tx & Rx descriptors status */
|
||||
#define ETH_ERROR_SUMMARY (BIT0)
|
||||
|
||||
/* Tx & Rx descriptors command */
|
||||
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
|
||||
|
||||
/* Tx descriptors status */
|
||||
#define ETH_LC_ERROR (0 )
|
||||
#define ETH_UR_ERROR (BIT1 )
|
||||
#define ETH_RL_ERROR (BIT2 )
|
||||
#define ETH_LLC_SNAP_FORMAT (BIT9 )
|
||||
|
||||
/* Rx descriptors status */
|
||||
#define ETH_CRC_ERROR (0 )
|
||||
#define ETH_OVERRUN_ERROR (BIT1 )
|
||||
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
|
||||
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
|
||||
#define ETH_VLAN_TAGGED (BIT19)
|
||||
#define ETH_BPDU_FRAME (BIT20)
|
||||
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
|
||||
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
|
||||
#define ETH_OTHER_FRAME_TYPE (BIT22)
|
||||
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
|
||||
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
|
||||
#define ETH_FRAME_HEADER_OK (BIT25)
|
||||
#define ETH_RX_LAST_DESC (BIT26)
|
||||
#define ETH_RX_FIRST_DESC (BIT27)
|
||||
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
|
||||
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
|
||||
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
|
||||
|
||||
/* Rx descriptors byte count */
|
||||
#define ETH_FRAME_FRAGMENTED (BIT2)
|
||||
|
||||
/* Tx descriptors command */
|
||||
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
|
||||
#define ETH_FRAME_SET_TO_VLAN (BIT15)
|
||||
#define ETH_TCP_FRAME (0 )
|
||||
#define ETH_UDP_FRAME (BIT16)
|
||||
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
|
||||
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
|
||||
#define ETH_ZERO_PADDING (BIT19)
|
||||
#define ETH_TX_LAST_DESC (BIT20)
|
||||
#define ETH_TX_FIRST_DESC (BIT21)
|
||||
#define ETH_GEN_CRC (BIT22)
|
||||
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
|
||||
#define ETH_AUTO_MODE (BIT30)
|
||||
|
||||
/* Address decode parameters */
|
||||
/* Ethernet Base Address Register bits */
|
||||
#define EBAR_TARGET_DRAM 0x00000000
|
||||
#define EBAR_TARGET_DEVICE 0x00000001
|
||||
#define EBAR_TARGET_CBS 0x00000002
|
||||
#define EBAR_TARGET_PCI0 0x00000003
|
||||
#define EBAR_TARGET_PCI1 0x00000004
|
||||
#define EBAR_TARGET_CUNIT 0x00000005
|
||||
#define EBAR_TARGET_AUNIT 0x00000006
|
||||
#define EBAR_TARGET_GUNIT 0x00000007
|
||||
|
||||
/* Window attributes */
|
||||
#define EBAR_ATTR_DRAM_CS0 0x00000E00
|
||||
#define EBAR_ATTR_DRAM_CS1 0x00000D00
|
||||
#define EBAR_ATTR_DRAM_CS2 0x00000B00
|
||||
#define EBAR_ATTR_DRAM_CS3 0x00000700
|
||||
|
||||
/* DRAM Target interface */
|
||||
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
|
||||
|
||||
/* Device Bus Target interface */
|
||||
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
|
||||
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
|
||||
|
||||
/* PCI Target interface */
|
||||
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
|
||||
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
|
||||
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
|
||||
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
|
||||
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
|
||||
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
|
||||
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
|
||||
|
||||
/* CPU 60x bus or internal SRAM interface */
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
|
||||
#define EBAR_ATTR_CBS_SRAM 0x00000000
|
||||
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
|
||||
|
||||
/* Window access control */
|
||||
#define EWIN_ACCESS_NOT_ALLOWED 0
|
||||
#define EWIN_ACCESS_READ_ONLY BIT0
|
||||
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
|
||||
#define EWIN0_ACCESS_MASK 0x0003
|
||||
#define EWIN1_ACCESS_MASK 0x000C
|
||||
#define EWIN2_ACCESS_MASK 0x0030
|
||||
#define EWIN3_ACCESS_MASK 0x00C0
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef enum _eth_port
|
||||
{
|
||||
ETH_0 = 0,
|
||||
ETH_1 = 1,
|
||||
ETH_2 = 2
|
||||
}ETH_PORT;
|
||||
|
||||
typedef enum _eth_func_ret_status
|
||||
{
|
||||
ETH_OK, /* Returned as expected. */
|
||||
ETH_ERROR, /* Fundamental error. */
|
||||
ETH_RETRY, /* Could not process request. Try later. */
|
||||
ETH_END_OF_JOB, /* Ring has nothing to process. */
|
||||
ETH_QUEUE_FULL, /* Ring resource error. */
|
||||
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
|
||||
}ETH_FUNC_RET_STATUS;
|
||||
|
||||
typedef enum _eth_queue
|
||||
{
|
||||
ETH_Q0 = 0,
|
||||
ETH_Q1 = 1,
|
||||
ETH_Q2 = 2,
|
||||
ETH_Q3 = 3,
|
||||
ETH_Q4 = 4,
|
||||
ETH_Q5 = 5,
|
||||
ETH_Q6 = 6,
|
||||
ETH_Q7 = 7
|
||||
} ETH_QUEUE;
|
||||
|
||||
typedef enum _addr_win
|
||||
{
|
||||
ETH_WIN0,
|
||||
ETH_WIN1,
|
||||
ETH_WIN2,
|
||||
ETH_WIN3,
|
||||
ETH_WIN4,
|
||||
ETH_WIN5
|
||||
} ETH_ADDR_WIN;
|
||||
|
||||
typedef enum _eth_target
|
||||
{
|
||||
ETH_TARGET_DRAM ,
|
||||
ETH_TARGET_DEVICE,
|
||||
ETH_TARGET_CBS ,
|
||||
ETH_TARGET_PCI0 ,
|
||||
ETH_TARGET_PCI1
|
||||
}ETH_TARGET;
|
||||
|
||||
typedef struct _eth_rx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short buf_size ; /* Buffer size */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_RX_DESC;
|
||||
|
||||
|
||||
typedef struct _eth_tx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_TX_DESC;
|
||||
|
||||
/* Unified struct for Rx and Tx operations. The user is not required to */
|
||||
/* be familier with neither Tx nor Rx descriptors. */
|
||||
typedef struct _pkt_info
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} PKT_INFO;
|
||||
|
||||
|
||||
typedef struct _eth_win_param
|
||||
{
|
||||
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
|
||||
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
|
||||
unsigned short attributes; /* BAR attributes. See above macros. */
|
||||
unsigned int base_addr; /* Window base address in unsigned int form */
|
||||
unsigned int high_addr; /* Window high address in unsigned int form */
|
||||
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
|
||||
bool enable; /* Enable/disable access to the window. */
|
||||
unsigned short access_ctrl; /* Access ctrl register. see above macros */
|
||||
} ETH_WIN_PARAM;
|
||||
|
||||
|
||||
/* Ethernet port specific infomation */
|
||||
|
||||
typedef struct _eth_port_ctrl
|
||||
{
|
||||
ETH_PORT port_num; /* User Ethernet port number */
|
||||
int port_phy_addr; /* User phy address of Ethrnet port */
|
||||
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
|
||||
unsigned int port_config; /* User port configuration value */
|
||||
unsigned int port_config_extend; /* User port config extend value */
|
||||
unsigned int port_sdma_config; /* User port SDMA config value */
|
||||
unsigned int port_serial_control; /* User port serial control value */
|
||||
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
|
||||
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
|
||||
|
||||
/* User function to cast virtual address to CPU bus address */
|
||||
unsigned int (*port_virt_to_phys)(unsigned int addr);
|
||||
/* User scratch pad for user specific data structures */
|
||||
void *port_private;
|
||||
|
||||
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
|
||||
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
|
||||
|
||||
/* Tx/Rx rings managment indexes fields. For driver use */
|
||||
|
||||
/* Next available Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
|
||||
/* Returning Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Next available Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* Returning Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* An extra Tx index to support transmit of multiple buffers per packet */
|
||||
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
|
||||
|
||||
/* Tx/Rx rings size and base variables fields. For driver use */
|
||||
|
||||
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
|
||||
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
|
||||
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
|
||||
|
||||
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
|
||||
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
|
||||
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
|
||||
|
||||
} ETH_PORT_INFO;
|
||||
|
||||
|
||||
/* ethernet.h API list */
|
||||
|
||||
/* Port operation control routines */
|
||||
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
static void eth_port_reset(ETH_PORT eth_port_num);
|
||||
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
|
||||
|
||||
/* Port MAC address routines */
|
||||
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue);
|
||||
#if 0 /* FIXME */
|
||||
static void eth_port_mc_addr (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue,
|
||||
int option);
|
||||
#endif
|
||||
|
||||
/* PHY and MIB routines */
|
||||
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
|
||||
|
||||
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int value);
|
||||
|
||||
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int* value);
|
||||
|
||||
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
|
||||
|
||||
/* Port data flow control routines */
|
||||
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
|
||||
|
||||
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
int tx_desc_num,
|
||||
int tx_buff_size,
|
||||
unsigned int tx_desc_base_addr,
|
||||
unsigned int tx_buff_base_addr);
|
||||
|
||||
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
int rx_desc_num,
|
||||
int rx_buff_size,
|
||||
unsigned int rx_desc_base_addr,
|
||||
unsigned int rx_buff_base_addr);
|
||||
|
||||
#endif /* MV64460_ETH_ */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,858 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on original work by
|
||||
* Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
|
||||
* Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
|
||||
* modifications for the cpci750 by reinhard.arlt@esd-electronics.com
|
||||
* modifications for the P3M750 by roel.loeffen@prodrive.nl
|
||||
*/
|
||||
|
||||
/*
|
||||
* p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "../../Marvell/include/pci.h"
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
#include <net.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include "eth.h"
|
||||
#include "mpsc.h"
|
||||
#include "64460.h"
|
||||
#include "mv_regs.h"
|
||||
#include "p3mx.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef DEBUG
|
||||
/*#define DEBUG */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define MAP_PCI
|
||||
#endif /* of CONFIG_PCI */
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DP(x) x
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
extern flash_info_t flash_info[];
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* this is the current GT register space location */
|
||||
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
|
||||
|
||||
/* Unfortunately, we cant change it while we are in flash, so we initialize it
|
||||
* to the "final" value. This means that any debug_led calls before
|
||||
* board_early_init_f wont work right (like in cpu_init_f).
|
||||
* See also my_remap_gt_regs below. (NTL)
|
||||
*/
|
||||
|
||||
void board_prebootm_init (void);
|
||||
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
|
||||
int display_mem_map (void);
|
||||
void set_led(int);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* This is a version of the GT register space remapping function that
|
||||
* doesn't touch globals (meaning, it's ok to run from flash.)
|
||||
*
|
||||
* Unfortunately, this has the side effect that a writable
|
||||
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
|
||||
*/
|
||||
|
||||
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
/* check and see if it's already moved */
|
||||
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
|
||||
if ((temp & 0xffff) == new_loc >> 16)
|
||||
return;
|
||||
|
||||
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
|
||||
0xffff0000) | (new_loc >> 16);
|
||||
|
||||
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
|
||||
|
||||
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
static void gt_pci_config (void)
|
||||
{
|
||||
unsigned int stat;
|
||||
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */
|
||||
/* FuncNum 10:8, RegNum 7:2 */
|
||||
|
||||
/*
|
||||
* In PCIX mode devices provide their own bus and device numbers.
|
||||
* We query the Discovery II's
|
||||
* config registers by writing ones to the bus and device.
|
||||
* We then update the Virtual register with the correct value for the
|
||||
* bus and device.
|
||||
*/
|
||||
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
|
||||
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
|
||||
|
||||
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
|
||||
|
||||
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
|
||||
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
|
||||
|
||||
}
|
||||
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
|
||||
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
|
||||
|
||||
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
|
||||
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
|
||||
}
|
||||
|
||||
/* Enable master */
|
||||
PCI_MASTER_ENABLE (0, SELF);
|
||||
PCI_MASTER_ENABLE (1, SELF);
|
||||
|
||||
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
|
||||
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
|
||||
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
|
||||
(1 << 18);
|
||||
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
|
||||
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
|
||||
|
||||
/* ronen:
|
||||
* add write to pci remap registers for 64460.
|
||||
* in 64360 when writing to pci base go and overide remap automaticaly,
|
||||
* in 64460 it doesn't
|
||||
*/
|
||||
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
|
||||
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
|
||||
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
|
||||
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
|
||||
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
|
||||
|
||||
/* PCI interface settings */
|
||||
/* Timeout set to retry forever */
|
||||
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
|
||||
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
|
||||
|
||||
/* ronen - enable only CS0 and Internal reg!! */
|
||||
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
|
||||
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
|
||||
|
||||
/* ronen:
|
||||
* update the pci internal registers base address.
|
||||
*/
|
||||
#ifdef MAP_PCI
|
||||
for (stat = 0; stat <= PCI_HOST1; stat++)
|
||||
pciWriteConfigReg (stat,
|
||||
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
|
||||
SELF, CONFIG_SYS_GT_REGS);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Setup CPU interface paramaters */
|
||||
static void gt_cpu_config (void)
|
||||
{
|
||||
cpu_t cpu = get_cpu_type ();
|
||||
ulong tmp;
|
||||
|
||||
/* cpu configuration register */
|
||||
tmp = GTREGREAD (CPU_CONFIGURATION);
|
||||
/* set the SINGLE_CPU bit see MV64460 */
|
||||
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
|
||||
tmp |= CPU_CONF_SINGLE_CPU;
|
||||
#endif
|
||||
tmp &= ~CPU_CONF_AACK_DELAY_2;
|
||||
tmp |= CPU_CONF_DP_VALID;
|
||||
tmp |= CPU_CONF_AP_VALID;
|
||||
tmp |= CPU_CONF_PIPELINE;
|
||||
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
|
||||
|
||||
/* CPU master control register */
|
||||
tmp = GTREGREAD (CPU_MASTER_CONTROL);
|
||||
tmp |= CPU_MAST_CTL_ARB_EN;
|
||||
|
||||
if ((cpu == CPU_7400) ||
|
||||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
|
||||
|
||||
tmp |= CPU_MAST_CTL_CLEAN_BLK;
|
||||
tmp |= CPU_MAST_CTL_FLUSH_BLK;
|
||||
|
||||
} else {
|
||||
/* cleanblock must be cleared for CPUs
|
||||
* that do not support this command (603e, 750)
|
||||
* see Res#1 */
|
||||
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
|
||||
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
|
||||
}
|
||||
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
|
||||
}
|
||||
|
||||
/*
|
||||
* board_early_init_f.
|
||||
*
|
||||
* set up gal. device mappings, etc.
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/* set up the GT the way the kernel wants it
|
||||
* the call to move the GT register space will obviously
|
||||
* fail if it has already been done, but we're going to assume
|
||||
* that if it's not at the power-on location, it's where we put
|
||||
* it last time. (huber)
|
||||
*/
|
||||
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
gt_pci_config ();
|
||||
#endif
|
||||
/* mask all external interrupt sources */
|
||||
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
|
||||
/* new in >MV6436x */
|
||||
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
|
||||
/* --------------------- */
|
||||
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
|
||||
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
|
||||
|
||||
/* Device and Boot bus settings
|
||||
*/
|
||||
memoryMapDeviceSpace(DEVICE0, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE1, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE2, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE3, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
|
||||
|
||||
GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
|
||||
|
||||
gt_cpu_config();
|
||||
|
||||
/* MPP setup */
|
||||
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
|
||||
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
|
||||
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
|
||||
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
|
||||
|
||||
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
|
||||
|
||||
set_led(LED_RED);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* various things to do after relocation */
|
||||
|
||||
int misc_init_r ()
|
||||
{
|
||||
u8 val;
|
||||
|
||||
icache_enable ();
|
||||
#ifdef CONFIG_SYS_L2
|
||||
l2cache_enable ();
|
||||
#endif
|
||||
#ifdef CONFIG_MPSC
|
||||
mpsc_sdma_init ();
|
||||
mpsc_init2 ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable trickle changing in RTC upon powerup
|
||||
* No diode, 250 ohm series resistor
|
||||
*/
|
||||
val = 0xa5;
|
||||
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void after_reloc (ulong dest_addr, gd_t * gd)
|
||||
{
|
||||
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
|
||||
|
||||
/* display_mem_map(); */
|
||||
|
||||
/* now, jump to the main U-Boot board init code */
|
||||
set_led(LED_GREEN);
|
||||
board_init_r (gd, dest_addr);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
* right now, assume borad type. (there is just one...after all)
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
printf("Board: %s", CONFIG_SYS_BOARD_NAME);
|
||||
|
||||
if (i > 0) {
|
||||
puts(", serial# ");
|
||||
puts(buf);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void set_led(int col)
|
||||
{
|
||||
int tmp;
|
||||
int on_pin;
|
||||
int off_pin;
|
||||
|
||||
/* Program Mpp[22] as Gpp[22]
|
||||
* Program Mpp[23] as Gpp[23]
|
||||
*/
|
||||
tmp = GTREGREAD(MPP_CONTROL2);
|
||||
tmp &= 0x00ffffff;
|
||||
GT_REG_WRITE(MPP_CONTROL2,tmp);
|
||||
|
||||
/* Program Gpp[22] and Gpp[23] as output
|
||||
*/
|
||||
tmp = GTREGREAD(GPP_IO_CONTROL);
|
||||
tmp |= 0x00C00000;
|
||||
GT_REG_WRITE(GPP_IO_CONTROL, tmp);
|
||||
|
||||
/* Program Gpp[22] and Gpp[23] as active high
|
||||
*/
|
||||
tmp = GTREGREAD(GPP_LEVEL_CONTROL);
|
||||
tmp &= 0xff3fffff;
|
||||
GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
|
||||
|
||||
switch(col) {
|
||||
default:
|
||||
case LED_OFF :
|
||||
on_pin = 0;
|
||||
off_pin = ((1 << 23) | (1 << 22));
|
||||
break;
|
||||
case LED_RED :
|
||||
on_pin = (1 << 23);
|
||||
off_pin = (1 << 22);
|
||||
break;
|
||||
case LED_GREEN :
|
||||
on_pin = (1 << 22);
|
||||
off_pin = (1 << 23);
|
||||
break;
|
||||
case LED_ORANGE :
|
||||
on_pin = ((1 << 23) | (1 << 22));
|
||||
off_pin = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Set output Gpp[22] and Gpp[23]
|
||||
*/
|
||||
tmp = GTREGREAD(GPP_VALUE);
|
||||
tmp |= on_pin;
|
||||
tmp &= ~off_pin;
|
||||
GT_REG_WRITE(GPP_VALUE, tmp);
|
||||
}
|
||||
|
||||
int display_mem_map (void)
|
||||
{
|
||||
int i;
|
||||
unsigned int base, size, width;
|
||||
#ifdef CONFIG_PCI
|
||||
int j;
|
||||
#endif
|
||||
|
||||
/* SDRAM */
|
||||
printf ("SD (DDR) RAM\n");
|
||||
for (i = 0; i <= BANK3; i++) {
|
||||
base = memoryGetBankBaseAddress (i);
|
||||
size = memoryGetBankSize (i);
|
||||
if (size != 0)
|
||||
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
|
||||
i, base, size >> 20);
|
||||
}
|
||||
#ifdef CONFIG_PCI
|
||||
/* CPU's PCI windows */
|
||||
for (i = 0; i <= PCI_HOST1; i++) {
|
||||
printf ("\nCPU's PCI %d windows\n", i);
|
||||
base = pciGetSpaceBase (i, PCI_IO);
|
||||
size = pciGetSpaceSize (i, PCI_IO);
|
||||
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
|
||||
size >> 20);
|
||||
/* ronen currently only first PCI MEM is used 3 */
|
||||
for (j = 0; j <= PCI_REGION0; j++) {
|
||||
base = pciGetSpaceBase (i, j);
|
||||
size = pciGetSpaceSize (i, j);
|
||||
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
|
||||
j, base, size >> 20);
|
||||
}
|
||||
}
|
||||
#endif /* of CONFIG_PCI */
|
||||
|
||||
/* Bootrom */
|
||||
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
|
||||
size = memoryGetDeviceSize (BOOT_DEVICE);
|
||||
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
|
||||
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
|
||||
base, size >> 20, width);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* DRAM check routines copied from gw8260 */
|
||||
|
||||
#if defined (CONFIG_SYS_DRAM_TEST)
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: move64() - moves a double word (64-bit) */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* this function performs a double word move from the data at */
|
||||
/* the source pointer to the location at the destination pointer. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* unsigned long long *src - pointer to data to move */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* unsigned long long *dest - pointer to locate to move data */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* None */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* May cloober fr0. */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
static void move64 (unsigned long long *src, unsigned long long *dest)
|
||||
{
|
||||
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
|
||||
"stfd 0, 0(4)" /* *dest = fpr0 */
|
||||
: : : "fr0"); /* Clobbers fr0 */
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
|
||||
|
||||
unsigned long long pattern[] = {
|
||||
0xaaaaaaaaaaaaaaaaULL,
|
||||
0xccccccccccccccccULL,
|
||||
0xf0f0f0f0f0f0f0f0ULL,
|
||||
0xff00ff00ff00ff00ULL,
|
||||
0xffff0000ffff0000ULL,
|
||||
0xffffffff00000000ULL,
|
||||
0x00000000ffffffffULL,
|
||||
0x0000ffff0000ffffULL,
|
||||
0x00ff00ff00ff00ffULL,
|
||||
0x0f0f0f0f0f0f0f0fULL,
|
||||
0x3333333333333333ULL,
|
||||
0x5555555555555555ULL
|
||||
};
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_data() - test data lines for shorts and opens */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Tests data lines for shorts and opens by forcing adjacent data */
|
||||
/* to opposite states. Because the data lines could be routed in */
|
||||
/* an arbitrary manner the must ensure test patterns ensure that */
|
||||
/* every case is tested. By using the following series of binary */
|
||||
/* patterns every combination of adjacent bits is test regardless */
|
||||
/* of routing. */
|
||||
/* */
|
||||
/* ...101010101010101010101010 */
|
||||
/* ...110011001100110011001100 */
|
||||
/* ...111100001111000011110000 */
|
||||
/* ...111111110000000011111111 */
|
||||
/* */
|
||||
/* Carrying this out, gives us six hex patterns as follows: */
|
||||
/* */
|
||||
/* 0xaaaaaaaaaaaaaaaa */
|
||||
/* 0xcccccccccccccccc */
|
||||
/* 0xf0f0f0f0f0f0f0f0 */
|
||||
/* 0xff00ff00ff00ff00 */
|
||||
/* 0xffff0000ffff0000 */
|
||||
/* 0xffffffff00000000 */
|
||||
/* */
|
||||
/* The number test patterns will always be given by: */
|
||||
/* */
|
||||
/* log(base 2)(number data bits) = log2 (64) = 6 */
|
||||
/* */
|
||||
/* To test for short and opens to other signals on our boards. we */
|
||||
/* simply */
|
||||
/* test with the 1's complemnt of the paterns as well. */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* Assumes only one one SDRAM bank */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_data (void)
|
||||
{
|
||||
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
|
||||
unsigned long long temp64 = 0;
|
||||
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
|
||||
int i;
|
||||
unsigned int hi, lo;
|
||||
|
||||
for (i = 0; i < num_patterns; i++) {
|
||||
move64 (&(pattern[i]), pmem);
|
||||
move64 (pmem, &temp64);
|
||||
|
||||
/* hi = (temp64>>32) & 0xffffffff; */
|
||||
/* lo = temp64 & 0xffffffff; */
|
||||
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
|
||||
|
||||
hi = (pattern[i] >> 32) & 0xffffffff;
|
||||
lo = pattern[i] & 0xffffffff;
|
||||
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
|
||||
|
||||
if (temp64 != pattern[i]) {
|
||||
printf ("\n Data Test Failed, pattern 0x%08x%08x",
|
||||
hi, lo);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
|
||||
|
||||
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_address() - test address lines */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* This function performs a test to verify that each word im */
|
||||
/* memory is uniquly addressable. The test sequence is as follows: */
|
||||
/* */
|
||||
/* 1) write the address of each word to each word. */
|
||||
/* 2) verify that each location equals its address */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern and address */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_address (void)
|
||||
{
|
||||
volatile unsigned int *pmem =
|
||||
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
|
||||
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
|
||||
unsigned int i;
|
||||
|
||||
/* write address to each location */
|
||||
for (i = 0; i < size; i++)
|
||||
pmem[i] = i;
|
||||
|
||||
/* verify each loaction */
|
||||
for (i = 0; i < size; i++) {
|
||||
if (pmem[i] != i) {
|
||||
printf ("\n Address Test Failed at 0x%x", i);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
|
||||
|
||||
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_march() - memory march */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Marches up through memory. At each location verifies rmask if */
|
||||
/* read = 1. At each location write wmask if write = 1. Displays */
|
||||
/* failing address and pattern. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* volatile unsigned long long * base - start address of test */
|
||||
/* unsigned int size - number of dwords(64-bit) to test */
|
||||
/* unsigned long long rmask - read verify mask */
|
||||
/* unsigned long long wmask - wrtie verify mask */
|
||||
/* short read - verifies rmask if read = 1 */
|
||||
/* short write - writes wmask if write = 1 */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern and address */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_march (volatile unsigned long long *base,
|
||||
unsigned int size,
|
||||
unsigned long long rmask,
|
||||
unsigned long long wmask, short read, short write)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned long long temp = 0;
|
||||
unsigned int hitemp, lotemp, himask, lomask;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (read != 0) {
|
||||
/* temp = base[i]; */
|
||||
move64 ((unsigned long long *) &(base[i]), &temp);
|
||||
if (rmask != temp) {
|
||||
hitemp = (temp >> 32) & 0xffffffff;
|
||||
lotemp = temp & 0xffffffff;
|
||||
himask = (rmask >> 32) & 0xffffffff;
|
||||
lomask = rmask & 0xffffffff;
|
||||
|
||||
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
if (write != 0) {
|
||||
/* base[i] = wmask; */
|
||||
move64 (&wmask, (unsigned long long *) &(base[i]));
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_walk() - a simple walking ones test */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Performs a walking ones through entire physical memory. The */
|
||||
/* test uses as series of memory marches, mem_march(), to verify */
|
||||
/* and write the test patterns to memory. The test sequence is as */
|
||||
/* follows: */
|
||||
/* 1) march writing 0000...0001 */
|
||||
/* 2) march verifying 0000...0001 , writing 0000...0010 */
|
||||
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
|
||||
/* the write mask equals 1000...0000 */
|
||||
/* 4) march verifying 1000...0000 */
|
||||
/* The test fails if any of the memory marches return a failure. */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays which pass on the memory test is executing */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_walk (void)
|
||||
{
|
||||
unsigned long long mask;
|
||||
volatile unsigned long long *pmem =
|
||||
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
|
||||
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
mask = 0x01;
|
||||
|
||||
printf ("Initial Pass");
|
||||
mem_march (pmem, size, 0x0, 0x1, 0, 1);
|
||||
|
||||
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
||||
printf (" ");
|
||||
printf (" ");
|
||||
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
||||
|
||||
for (i = 0; i < 63; i++) {
|
||||
printf ("Pass %2d", i + 2);
|
||||
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
|
||||
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
|
||||
return 1;
|
||||
}
|
||||
mask = mask << 1;
|
||||
printf ("\b\b\b\b\b\b\b");
|
||||
}
|
||||
|
||||
printf ("Last Pass");
|
||||
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
|
||||
/* printf("mask: 0x%x", mask); */
|
||||
return 1;
|
||||
}
|
||||
printf ("\b\b\b\b\b\b\b\b\b");
|
||||
printf (" ");
|
||||
printf ("\b\b\b\b\b\b\b\b\b");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: testdram() - calls any enabled memory tests */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Runs memory tests if the environment test variables are set to */
|
||||
/* 'y'. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* testdramdata - If set to 'y', data test is run. */
|
||||
/* testdramaddress - If set to 'y', address test is run. */
|
||||
/* testdramwalk - If set to 'y', walking ones test is run */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* None */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int testdram (void)
|
||||
{
|
||||
char *s;
|
||||
int rundata = 0;
|
||||
int runaddress = 0;
|
||||
int runwalk = 0;
|
||||
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_DATA
|
||||
s = getenv ("testdramdata");
|
||||
rundata = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
|
||||
s = getenv ("testdramaddress");
|
||||
runaddress = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_WALK
|
||||
s = getenv ("testdramwalk");
|
||||
runwalk = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("Testing RAM from 0x%08x to 0x%08x ... "
|
||||
"(don't panic... that will take a moment !!!!)\n",
|
||||
CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_DATA
|
||||
if (rundata == 1) {
|
||||
printf ("Test DATA ... ");
|
||||
if (mem_test_data () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
|
||||
if (runaddress == 1) {
|
||||
printf ("Test ADDRESS ... ");
|
||||
if (mem_test_address () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DRAM_TEST_WALK
|
||||
if (runwalk == 1) {
|
||||
printf ("Test WALKING ONEs ... ");
|
||||
if (mem_test_walk () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("passed\n");
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif /* CONFIG_SYS_DRAM_TEST */
|
||||
|
||||
/* ronen - the below functions are used by the bootm function */
|
||||
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
|
||||
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
|
||||
/* the kernel data areas. */
|
||||
/* - we diable and invalidate the icache and dcache. */
|
||||
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
|
||||
if ((temp & 0xffff) == new_loc >> 16)
|
||||
return;
|
||||
|
||||
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
|
||||
0xffff0000) | (new_loc >> 16);
|
||||
|
||||
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
|
||||
|
||||
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
|
||||
new_loc |
|
||||
(INTERNAL_SPACE_DECODE)))))
|
||||
!= temp);
|
||||
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return mv6446x_eth_initialize(bis);
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
*
|
||||
* Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __P3MX_H__
|
||||
#define __P3MX_H__
|
||||
|
||||
#define LED_OFF 1
|
||||
#define LED_GREEN 2
|
||||
#define LED_RED 3
|
||||
#define LED_ORANGE 4
|
||||
|
||||
#endif /* __P3MX_H__ */
|
||||
1020
common/package/utils/sysupgrade-helper/src/board/prodrive/p3mx/pci.c
Normal file
1020
common/package/utils/sysupgrade-helper/src/board/prodrive/p3mx/pci.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
|
||||
*/
|
||||
#ifndef _MV_PPC_ERRNO_H
|
||||
#define _MV_PPC_ERRNO_H
|
||||
|
||||
#define EPERM 1 /* Operation not permitted */
|
||||
#define ENOENT 2 /* No such file or directory */
|
||||
#define ESRCH 3 /* No such process */
|
||||
#define EINTR 4 /* Interrupted system call */
|
||||
#define EIO 5 /* I/O error */
|
||||
#define ENXIO 6 /* No such device or address */
|
||||
#define E2BIG 7 /* Arg list too long */
|
||||
#define ENOEXEC 8 /* Exec format error */
|
||||
#define EBADF 9 /* Bad file number */
|
||||
#define ECHILD 10 /* No child processes */
|
||||
#define EAGAIN 11 /* Try again */
|
||||
#define ENOMEM 12 /* Out of memory */
|
||||
#define EACCES 13 /* Permission denied */
|
||||
#define EFAULT 14 /* Bad address */
|
||||
#define ENOTBLK 15 /* Block device required */
|
||||
#define EBUSY 16 /* Device or resource busy */
|
||||
#define EEXIST 17 /* File exists */
|
||||
#define EXDEV 18 /* Cross-device link */
|
||||
#define ENODEV 19 /* No such device */
|
||||
#define ENOTDIR 20 /* Not a directory */
|
||||
#define EISDIR 21 /* Is a directory */
|
||||
#define EINVAL 22 /* Invalid argument */
|
||||
#define ENFILE 23 /* File table overflow */
|
||||
#define EMFILE 24 /* Too many open files */
|
||||
#define ENOTTY 25 /* Not a typewriter */
|
||||
#define ETXTBSY 26 /* Text file busy */
|
||||
#define EFBIG 27 /* File too large */
|
||||
#define ENOSPC 28 /* No space left on device */
|
||||
#define ESPIPE 29 /* Illegal seek */
|
||||
#define EROFS 30 /* Read-only file system */
|
||||
#define EMLINK 31 /* Too many links */
|
||||
#define EPIPE 32 /* Broken pipe */
|
||||
#define EDOM 33 /* Math argument out of domain of func */
|
||||
#define ERANGE 34 /* Math result not representable */
|
||||
#define EDEADLK 35 /* Resource deadlock would occur */
|
||||
#define ENAMETOOLONG 36 /* File name too long */
|
||||
#define ENOLCK 37 /* No record locks available */
|
||||
#define ENOSYS 38 /* Function not implemented */
|
||||
#define ENOTEMPTY 39 /* Directory not empty */
|
||||
#define ELOOP 40 /* Too many symbolic links encountered */
|
||||
#define EWOULDBLOCK EAGAIN /* Operation would block */
|
||||
#define ENOMSG 42 /* No message of desired type */
|
||||
#define EIDRM 43 /* Identifier removed */
|
||||
#define ECHRNG 44 /* Channel number out of range */
|
||||
#define EL2NSYNC 45 /* Level 2 not synchronized */
|
||||
#define EL3HLT 46 /* Level 3 halted */
|
||||
#define EL3RST 47 /* Level 3 reset */
|
||||
#define ELNRNG 48 /* Link number out of range */
|
||||
#define EUNATCH 49 /* Protocol driver not attached */
|
||||
#define ENOCSI 50 /* No CSI structure available */
|
||||
#define EL2HLT 51 /* Level 2 halted */
|
||||
#define EBADE 52 /* Invalid exchange */
|
||||
#define EBADR 53 /* Invalid request descriptor */
|
||||
#define EXFULL 54 /* Exchange full */
|
||||
#define ENOANO 55 /* No anode */
|
||||
#define EBADRQC 56 /* Invalid request code */
|
||||
#define EBADSLT 57 /* Invalid slot */
|
||||
#define EDEADLOCK 58 /* File locking deadlock error */
|
||||
#define EBFONT 59 /* Bad font file format */
|
||||
#define ENOSTR 60 /* Device not a stream */
|
||||
#define ENODATA 61 /* No data available */
|
||||
#define ETIME 62 /* Timer expired */
|
||||
#define ENOSR 63 /* Out of streams resources */
|
||||
#define ENONET 64 /* Machine is not on the network */
|
||||
#define ENOPKG 65 /* Package not installed */
|
||||
#define EREMOTE 66 /* Object is remote */
|
||||
#define ENOLINK 67 /* Link has been severed */
|
||||
#define EADV 68 /* Advertise error */
|
||||
#define ESRMNT 69 /* Srmount error */
|
||||
#define ECOMM 70 /* Communication error on send */
|
||||
#define EPROTO 71 /* Protocol error */
|
||||
#define EMULTIHOP 72 /* Multihop attempted */
|
||||
#define EDOTDOT 73 /* RFS specific error */
|
||||
#define EBADMSG 74 /* Not a data message */
|
||||
#define EOVERFLOW 75 /* Value too large for defined data type */
|
||||
#define ENOTUNIQ 76 /* Name not unique on network */
|
||||
#define EBADFD 77 /* File descriptor in bad state */
|
||||
#define EREMCHG 78 /* Remote address changed */
|
||||
#define ELIBACC 79 /* Can not access a needed shared library */
|
||||
#define ELIBBAD 80 /* Accessing a corrupted shared library */
|
||||
#define ELIBSCN 81 /* .lib section in a.out corrupted */
|
||||
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
|
||||
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
|
||||
#define EILSEQ 84 /* Illegal byte sequence */
|
||||
#define ERESTART 85 /* Interrupted system call should be restarted */
|
||||
#define ESTRPIPE 86 /* Streams pipe error */
|
||||
#define EUSERS 87 /* Too many users */
|
||||
#define ENOTSOCK 88 /* Socket operation on non-socket */
|
||||
#define EDESTADDRREQ 89 /* Destination address required */
|
||||
#define EMSGSIZE 90 /* Message too long */
|
||||
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
|
||||
#define ENOPROTOOPT 92 /* Protocol not available */
|
||||
#define EPROTONOSUPPORT 93 /* Protocol not supported */
|
||||
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
|
||||
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define EPFNOSUPPORT 96 /* Protocol family not supported */
|
||||
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
|
||||
#define EADDRINUSE 98 /* Address already in use */
|
||||
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
|
||||
#define ENETDOWN 100 /* Network is down */
|
||||
#define ENETUNREACH 101 /* Network is unreachable */
|
||||
#define ENETRESET 102 /* Network dropped connection because of reset */
|
||||
#define ECONNABORTED 103 /* Software caused connection abort */
|
||||
#define ECONNRESET 104 /* Connection reset by peer */
|
||||
#define ENOBUFS 105 /* No buffer space available */
|
||||
#define EISCONN 106 /* Transport endpoint is already connected */
|
||||
#define ENOTCONN 107 /* Transport endpoint is not connected */
|
||||
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
|
||||
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
|
||||
#define ETIMEDOUT 110 /* Connection timed out */
|
||||
#define ECONNREFUSED 111 /* Connection refused */
|
||||
#define EHOSTDOWN 112 /* Host is down */
|
||||
#define EHOSTUNREACH 113 /* No route to host */
|
||||
#define EALREADY 114 /* Operation already in progress */
|
||||
#define EINPROGRESS 115 /* Operation now in progress */
|
||||
#define ESTALE 116 /* Stale NFS file handle */
|
||||
#define EUCLEAN 117 /* Structure needs cleaning */
|
||||
#define ENOTNAM 118 /* Not a XENIX named type file */
|
||||
#define ENAVAIL 119 /* No XENIX semaphores available */
|
||||
#define EISNAM 120 /* Is a named type file */
|
||||
#define EREMOTEIO 121 /* Remote I/O error */
|
||||
#define EDQUOT 122 /* Quota exceeded */
|
||||
|
||||
#define ENOMEDIUM 123 /* No medium found */
|
||||
#define EMEDIUMTYPE 124 /* Wrong medium type */
|
||||
|
||||
/* Should never be seen by user programs */
|
||||
#define ERESTARTSYS 512
|
||||
#define ERESTARTNOINTR 513
|
||||
#define ERESTARTNOHAND 514 /* restart if no handler.. */
|
||||
#define ENOIOCTLCMD 515 /* No ioctl command */
|
||||
|
||||
#define _LAST_ERRNO 515
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,434 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
* adaption for the Marvell DB64460 Board
|
||||
* Ingo Assmus (ingo.assmus@keymile.com)
|
||||
*************************************************************************/
|
||||
|
||||
/* sdram_init.c - automatic memory sizing */
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "../../Marvell/include/pci.h"
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
#include <net.h>
|
||||
|
||||
#include "eth.h"
|
||||
#include "mpsc.h"
|
||||
#include "../../Marvell/common/i2c.h"
|
||||
#include "64460.h"
|
||||
#include "mv_regs.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef DEBUG
|
||||
#define MAP_PCI
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DP(x) x
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
int set_dfcdlInit (void); /* setup delay line of Mv64460 */
|
||||
int mvDmaIsChannelActive (int);
|
||||
int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
|
||||
int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
|
||||
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
|
||||
int memory_map_bank (unsigned int bankNo,
|
||||
unsigned int bankBase, unsigned int bankLength)
|
||||
{
|
||||
#if defined (MAP_PCI) && defined (CONFIG_PCI)
|
||||
PCI_HOST host;
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
if (bankLength > 0) {
|
||||
printf ("mapping bank %d at %08x - %08x\n",
|
||||
bankNo, bankBase, bankBase + bankLength - 1);
|
||||
} else {
|
||||
printf ("unmapping bank %d\n", bankNo);
|
||||
}
|
||||
#endif
|
||||
|
||||
memoryMapBank (bankNo, bankBase, bankLength);
|
||||
|
||||
#if defined (MAP_PCI) && defined (CONFIG_PCI)
|
||||
for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
|
||||
const int features =
|
||||
PREFETCH_ENABLE |
|
||||
DELAYED_READ_ENABLE |
|
||||
AGGRESSIVE_PREFETCH |
|
||||
READ_LINE_AGGRESSIVE_PREFETCH |
|
||||
READ_MULTI_AGGRESSIVE_PREFETCH |
|
||||
MAX_BURST_4 | PCI_NO_SWAP;
|
||||
|
||||
pciMapMemoryBank (host, bankNo, bankBase, bankLength);
|
||||
|
||||
pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
|
||||
bankLength);
|
||||
|
||||
pciSetRegionFeatures (host, bankNo, features, bankBase,
|
||||
bankLength);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
long int dram_size (long int *base, long int maxsize)
|
||||
{
|
||||
volatile long int *addr, *b = base;
|
||||
long int cnt, val, save1, save2;
|
||||
|
||||
#define STARTVAL (1<<20) /* start test at 1M */
|
||||
for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
|
||||
cnt <<= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
save1 = *addr; /* save contents of addr */
|
||||
save2 = *b; /* save contents of base */
|
||||
|
||||
*addr = cnt; /* write cnt to addr */
|
||||
*b = 0; /* put null at base */
|
||||
|
||||
/* check at base address */
|
||||
if ((*b) != 0) {
|
||||
*addr = save1; /* restore *addr */
|
||||
*b = save2; /* restore *b */
|
||||
return (0);
|
||||
}
|
||||
val = *addr; /* read *addr */
|
||||
val = *addr; /* read *addr */
|
||||
|
||||
*addr = save1;
|
||||
*b = save2;
|
||||
|
||||
if (val != cnt) {
|
||||
DP (printf
|
||||
("Found %08x at Address %08x (failure)\n",
|
||||
(unsigned int) val, (unsigned int) addr));
|
||||
/* fix boundary condition.. STARTVAL means zero */
|
||||
if (cnt == STARTVAL / sizeof (long))
|
||||
cnt = 0;
|
||||
return (cnt * sizeof (long));
|
||||
}
|
||||
}
|
||||
|
||||
return maxsize;
|
||||
}
|
||||
|
||||
#define SDRAM_NORMAL 0x0
|
||||
#define SDRAM_PRECHARGE_ALL 0x1
|
||||
#define SDRAM_REFRESH_ALL 0x2
|
||||
#define SDRAM_MODE_REG_SETUP 0x3
|
||||
#define SDRAM_XTEN_MODE_REG_SETUP 0x4
|
||||
#define SDRAM_NOP 0x5
|
||||
#define SDRAM_SELF_REFRESH 0x7
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
int tmp;
|
||||
int start;
|
||||
ulong size;
|
||||
ulong memSpaceAttr;
|
||||
ulong dest;
|
||||
|
||||
/* first disable all banks */
|
||||
memory_map_bank(0, 0, 0);
|
||||
memory_map_bank(1, 0, 0);
|
||||
memory_map_bank(2, 0, 0);
|
||||
memory_map_bank(3, 0, 0);
|
||||
|
||||
/* calibrate delay lines */
|
||||
set_dfcdlInit();
|
||||
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* SDRAM controller configuration */
|
||||
#ifdef CONFIG_MV64460_ECC
|
||||
GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */
|
||||
#else
|
||||
GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */
|
||||
#endif
|
||||
GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */
|
||||
GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */
|
||||
|
||||
/* SDRAM drive strength */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */
|
||||
|
||||
/* setup SDRAM device registers */
|
||||
|
||||
/* precharge all */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* enable DLL */
|
||||
GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* reset DLL */
|
||||
GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* precharge all */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* wait for 2 auto refresh commands */
|
||||
udelay(20);
|
||||
|
||||
/* un-reset DLL */
|
||||
GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* wait 200 cycles */
|
||||
udelay(2); /* FIXME make this dynamic for the system clock */
|
||||
|
||||
/* SDRAM init done */
|
||||
memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20));
|
||||
#ifdef CONFIG_SYS_SDRAM1_BASE
|
||||
memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
|
||||
#endif
|
||||
|
||||
/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
|
||||
*/
|
||||
tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */
|
||||
GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
|
||||
|
||||
start = (0 << 20);
|
||||
#ifdef CONFIG_P3M750
|
||||
size = (512 << 20);
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
size = (128 << 20);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MV64460_ECC
|
||||
memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
|
||||
mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
|
||||
for (dest = start; dest < start + size; dest += _8M) {
|
||||
mvDmaTransfer (0, start, dest, _8M,
|
||||
BIT8 /*DMA_DTL_128BYTES */ |
|
||||
BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
|
||||
BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
|
||||
while (mvDmaIsChannelActive (0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
puts(" (CL=");
|
||||
switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
|
||||
case 0x2:
|
||||
puts("2");
|
||||
break;
|
||||
case 0x3:
|
||||
puts("3");
|
||||
break;
|
||||
case 0x5:
|
||||
puts("1.5");
|
||||
break;
|
||||
case 0x6:
|
||||
puts("2.5");
|
||||
break;
|
||||
}
|
||||
|
||||
val = GTREGREAD(MV64460_SDRAM_CONFIG);
|
||||
|
||||
puts(", ECC ");
|
||||
if (val & 0x00001000)
|
||||
puts("enabled)");
|
||||
else
|
||||
puts("not enabled)");
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaIsChannelActive - Check if IDMA channel is active
|
||||
*
|
||||
* channel = IDMA channel number from 0 to 7
|
||||
*/
|
||||
int mvDmaIsChannelActive (int channel)
|
||||
{
|
||||
ulong data;
|
||||
|
||||
data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
|
||||
if (data & BIT14) /* activity status */
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
|
||||
* map.
|
||||
*
|
||||
* memSpace = IDMA memory window number from 0 to 7
|
||||
* trg_if = Target interface:
|
||||
* 0x0 DRAM
|
||||
* 0x1 Device Bus
|
||||
* 0x2 Integrated SDRAM (or CPU bus 60x only)
|
||||
* 0x3 PCI0
|
||||
* 0x4 PCI1
|
||||
* attr = IDMA attributes (see MV datasheet)
|
||||
* base_addr = Sets up memory window for transfers
|
||||
*
|
||||
*/
|
||||
int mvDmaSetMemorySpace (ulong memSpace,
|
||||
ulong trg_if,
|
||||
ulong attr, ulong base_addr, ulong size)
|
||||
{
|
||||
ulong temp;
|
||||
|
||||
/* The base address must be aligned to the size. */
|
||||
if (base_addr % size != 0)
|
||||
return 0;
|
||||
|
||||
if (size >= 0x10000) { /* 64K */
|
||||
size &= 0xffff0000;
|
||||
base_addr = (base_addr & 0xffff0000);
|
||||
/* Set the new attributes */
|
||||
GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
|
||||
(base_addr | trg_if | attr));
|
||||
GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
|
||||
(size - 1) & 0xffff0000);
|
||||
temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
|
||||
GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
|
||||
(temp & ~(BIT0 << memSpace)));
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
|
||||
* DMA channels.
|
||||
*
|
||||
* channel = IDMA channel number from 0 to 3
|
||||
* destAddr = Destination address
|
||||
* sourceAddr = Source address
|
||||
* size = Size in bytes
|
||||
* command = See MV datasheet
|
||||
*
|
||||
*/
|
||||
int mvDmaTransfer (int channel, ulong sourceAddr,
|
||||
ulong destAddr, ulong size, ulong command)
|
||||
{
|
||||
ulong engOffReg = 0; /* Engine Offset Register */
|
||||
|
||||
if (size > 0xffff)
|
||||
command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
|
||||
command = command | ((command >> 6) & 0x7);
|
||||
engOffReg = channel * 4;
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
|
||||
command = command |
|
||||
BIT12 | /* DMA_CHANNEL_ENABLE */
|
||||
BIT9; /* DMA_NON_CHAIN_MODE */
|
||||
/* Activate DMA channel By writting to mvDmaControlRegister */
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/****************************************************************************************
|
||||
* SDRAM INIT *
|
||||
* This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
|
||||
* This procedure fits only the Atlantis *
|
||||
* *
|
||||
***************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* DFCDL initialize MV643xx Design Considerations *
|
||||
* *
|
||||
***************************************************************************************/
|
||||
int set_dfcdlInit (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Values from MV64460 User Manual */
|
||||
unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
|
||||
0x000000c4, 0x00000105, 0x00000146, 0x00000187,
|
||||
0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
|
||||
0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
|
||||
0x000003d0, 0x00000411, 0x00000452, 0x00000493,
|
||||
0x000004d4, 0x00000515, 0x00000556, 0x00000597,
|
||||
0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
|
||||
0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
|
||||
0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
|
||||
0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
|
||||
0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
|
||||
0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
|
||||
0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
|
||||
0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
|
||||
0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
|
||||
0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
|
||||
GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* modified for cpci750 board by
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* serial.c - serial support for esd cpci750 board
|
||||
*/
|
||||
|
||||
/* supports the MPSC */
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "serial.h"
|
||||
|
||||
#include "mpsc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int serial_init (void)
|
||||
{
|
||||
mpsc_init (gd->baudrate);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
mpsc_putchar ('\r');
|
||||
|
||||
mpsc_putchar (c);
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
return mpsc_getchar ();
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
return mpsc_test_char ();
|
||||
}
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
|
||||
}
|
||||
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
void kgdb_serial_init (void)
|
||||
{
|
||||
}
|
||||
|
||||
void putDebugChar (int c)
|
||||
{
|
||||
serial_putc (c);
|
||||
}
|
||||
|
||||
void putDebugStr (const char *str)
|
||||
{
|
||||
serial_puts (str);
|
||||
}
|
||||
|
||||
int getDebugChar (void)
|
||||
{
|
||||
return serial_getc ();
|
||||
}
|
||||
|
||||
void kgdb_interruptible (int yes)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* serial.h - mostly useful for DUART serial_init in serial.c */
|
||||
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#if 0
|
||||
|
||||
#define B230400 1
|
||||
#define B115200 2
|
||||
#define B57600 4
|
||||
#define B38400 82
|
||||
#define B19200 163
|
||||
#define B9600 24
|
||||
#define B4800 651
|
||||
#define B2400 1302
|
||||
#define B1200 2604
|
||||
#define B600 5208
|
||||
#define B300 10417
|
||||
#define B150 20833
|
||||
#define B110 28409
|
||||
#define BDEFAULT B115200
|
||||
|
||||
/* this stuff is important to initialize
|
||||
the DUART channels */
|
||||
|
||||
#define Scale 0x01L /* distance between port addresses */
|
||||
#define COM1 0x000003f8 /* Keyboard */
|
||||
#define COM2 0x000002f8 /* Host */
|
||||
|
||||
|
||||
/* Port Definitions relative to base COM port addresses */
|
||||
#define DataIn (0x00*Scale) /* data input port */
|
||||
#define DataOut (0x00*Scale) /* data output port */
|
||||
#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
|
||||
#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
|
||||
#define Ier (0x01*Scale) /* interrupt enable register */
|
||||
#define Iir (0x02*Scale) /* interrupt identification register */
|
||||
#define Lcr (0x03*Scale) /* line control register */
|
||||
#define Mcr (0x04*Scale) /* modem control register */
|
||||
#define Lsr (0x05*Scale) /* line status register */
|
||||
#define Msr (0x06*Scale) /* modem status register */
|
||||
|
||||
/* Bit Definitions for above ports */
|
||||
#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
|
||||
#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
|
||||
|
||||
#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
|
||||
#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
|
||||
#define McrDflt (McrRts|McrDtr)
|
||||
|
||||
#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
|
||||
/* b6: transmitter empty */
|
||||
#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
|
||||
|
||||
#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
|
||||
#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
|
||||
#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
|
||||
|
||||
#define IerRda 0xf /* b0: Enable received data available interrupt */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_H__ */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
|
||||
#include "p3p440.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void set_led(int color)
|
||||
{
|
||||
switch (color) {
|
||||
case LED_OFF:
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
|
||||
break;
|
||||
|
||||
case LED_GREEN:
|
||||
out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
|
||||
break;
|
||||
|
||||
case LED_RED:
|
||||
out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
|
||||
break;
|
||||
|
||||
case LED_ORANGE:
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int is_monarch(void)
|
||||
{
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
|
||||
udelay(1000);
|
||||
|
||||
if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void wait_for_pci_ready(void)
|
||||
{
|
||||
/*
|
||||
* Configure EREADY_IO as input
|
||||
*/
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
|
||||
udelay(1000);
|
||||
|
||||
for (;;) {
|
||||
if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
uint reg;
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(EBC0_CFGADDR, EBC0_CFG);
|
||||
reg = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup pin multiplexing (GPIO/IRQ...)
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(CPC0_GPIO, 0x03F01F80);
|
||||
|
||||
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
|
||||
out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all */
|
||||
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
|
||||
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
|
||||
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
|
||||
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
||||
mtdcr(UIC1ER, 0x00000000); /* disable all */
|
||||
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
|
||||
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
|
||||
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
|
||||
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
printf("Board: P3P440");
|
||||
if (i > 0) {
|
||||
puts(", serial# ");
|
||||
puts(buf);
|
||||
}
|
||||
|
||||
if (is_monarch()) {
|
||||
puts(", Monarch");
|
||||
} else {
|
||||
puts(", None-Monarch");
|
||||
}
|
||||
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
/*
|
||||
* Adjust flash start and offset to detected values
|
||||
*/
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
/*
|
||||
* Check if only one FLASH bank is available
|
||||
*/
|
||||
if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
|
||||
mtebc(PB1CR, 0); /* disable cs */
|
||||
mtebc(PB1AP, 0);
|
||||
mtebc(PB2CR, 0); /* disable cs */
|
||||
mtebc(PB2AP, 0);
|
||||
mtebc(PB3CR, 0); /* disable cs */
|
||||
mtebc(PB3AP, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* Override weak is_pci_host()
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
if (is_monarch()) {
|
||||
wait_for_pci_ready();
|
||||
return 1; /* return 1 for host controller */
|
||||
} else {
|
||||
return 0; /* return 0 for adapter controller */
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __P3P440_H__
|
||||
#define __P3P440_H__
|
||||
|
||||
#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11)
|
||||
#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18)
|
||||
#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20)
|
||||
#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21)
|
||||
#define CONFIG_SYS_LED_RED (0x80000000 >> 22)
|
||||
|
||||
#define LED_OFF 1
|
||||
#define LED_GREEN 2
|
||||
#define LED_RED 3
|
||||
#define LED_ORANGE 4
|
||||
|
||||
long int fixed_sdram(void);
|
||||
|
||||
#endif /* __P3P440_H__ */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := flash.o pdnb3.o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/ixp425.h>
|
||||
|
||||
#if !defined(CONFIG_FLASH_CFI_DRIVER)
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*
|
||||
* Prototypes
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
|
||||
static inline ulong ld(ulong x)
|
||||
{
|
||||
ulong k = 0;
|
||||
|
||||
while (x >>= 1)
|
||||
++k;
|
||||
|
||||
return k;
|
||||
}
|
||||
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long size;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
|
||||
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN)
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size, size<<20);
|
||||
|
||||
/* Reconfigure CS0 to actual FLASH size */
|
||||
*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
/* Environment protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
/* Redundant environment protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR_REDUND,
|
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
flash_info[0].size = size;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_FLASH_CFI_DRIVER */
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
#include <nand.h>
|
||||
|
||||
struct pdnb3_ndfc_regs {
|
||||
uchar cmd;
|
||||
uchar wait;
|
||||
uchar addr;
|
||||
uchar term;
|
||||
uchar data;
|
||||
};
|
||||
|
||||
static u8 hwctl;
|
||||
static struct pdnb3_ndfc_regs *pdnb3_ndfc;
|
||||
|
||||
#define readb(addr) *(volatile u_char *)(addr)
|
||||
#define readl(addr) *(volatile u_long *)(addr)
|
||||
#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
|
||||
|
||||
/*
|
||||
* The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
|
||||
* the NAND devices. The NDFC has command, address and data registers that
|
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the
|
||||
* hwcontrol function to save the configuration in a global variable.
|
||||
* We can then use this information in the read and write functions to
|
||||
* determine which NDFC register to access.
|
||||
*
|
||||
* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
|
||||
*/
|
||||
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
hwctl |= 0x1;
|
||||
else
|
||||
hwctl &= ~0x1;
|
||||
if ( ctrl & NAND_ALE )
|
||||
hwctl |= 0x2;
|
||||
else
|
||||
hwctl &= ~0x2;
|
||||
if ( (ctrl & NAND_NCE) != NAND_NCE)
|
||||
writeb(0x00, &(pdnb3_ndfc->term));
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
|
||||
static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
return readb(&(pdnb3_ndfc->data));
|
||||
}
|
||||
|
||||
static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (hwctl & 0x1)
|
||||
writeb(buf[i], &(pdnb3_ndfc->cmd));
|
||||
else if (hwctl & 0x2)
|
||||
writeb(buf[i], &(pdnb3_ndfc->addr));
|
||||
else
|
||||
writeb(buf[i], &(pdnb3_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
buf[i] = readb(&(pdnb3_ndfc->data));
|
||||
}
|
||||
|
||||
static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
if (buf[i] != readb(&(pdnb3_ndfc->data)))
|
||||
return i;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
/*
|
||||
* Blocking read to wait for NAND to be ready
|
||||
*/
|
||||
readb(&(pdnb3_ndfc->wait));
|
||||
|
||||
/*
|
||||
* Return always true
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
|
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Set address of NAND IO lines (Using Linear Data Access Region) */
|
||||
nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
|
||||
nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
|
||||
/* Reference hardware control function */
|
||||
nand->cmd_ctrl = pdnb3_nand_hwcontrol;
|
||||
nand->read_byte = pdnb3_nand_read_byte;
|
||||
nand->write_buf = pdnb3_nand_write_buf;
|
||||
nand->read_buf = pdnb3_nand_read_buf;
|
||||
nand->verify_buf = pdnb3_nand_verify_buf;
|
||||
nand->dev_ready = pdnb3_nand_dev_ready;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/arch/ixp425.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* predefine these here for FPGA programming (before including fpga.c) */
|
||||
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
|
||||
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
|
||||
#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
|
||||
#define OLD_VAL old_val
|
||||
|
||||
static unsigned long old_val = 0;
|
||||
|
||||
/*
|
||||
* include common fpga code (for prodrive boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0x00000100;
|
||||
|
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
|
||||
|
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
|
||||
|
||||
/*
|
||||
* Setup GPIO's for FPGA programming
|
||||
*/
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
|
||||
|
||||
/*
|
||||
* Setup GPIO's for interrupts
|
||||
*/
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
|
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
|
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
|
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
|
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
|
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
|
||||
|
||||
/*
|
||||
* Setup GPIO's for 33MHz clock output
|
||||
*/
|
||||
*IXP425_GPIO_GPCLKR = 0x01FF0000;
|
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
|
||||
|
||||
/*
|
||||
* Setup other chip select's
|
||||
*/
|
||||
*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity
|
||||
*/
|
||||
int checkboard(void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
puts("Board: PDNB3");
|
||||
|
||||
if (i > 0) {
|
||||
puts(", serial# ");
|
||||
puts(buf);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_fpga_boot(unsigned char *fpgadata)
|
||||
{
|
||||
unsigned char *dst;
|
||||
int status;
|
||||
int index;
|
||||
int i;
|
||||
ulong len = CONFIG_SYS_MALLOC_LEN;
|
||||
|
||||
/*
|
||||
* Setup GPIO's for FPGA programming
|
||||
*/
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
|
||||
|
||||
/*
|
||||
* Save value so no readback is required upon programming
|
||||
*/
|
||||
old_val = *IXP425_GPIO_GPOUTR;
|
||||
|
||||
/*
|
||||
* First try to decompress fpga image (gzip compressed?)
|
||||
*/
|
||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
|
||||
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
|
||||
printf("Error: Image has to be gzipp'ed!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
status = fpga_boot(dst, len);
|
||||
if (status != 0) {
|
||||
printf("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i=0; i<4; i++) {
|
||||
len = dst[index];
|
||||
printf("FPGA: %s\n", &(dst[index+1]));
|
||||
index += len+3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i=5; i>0; i--) {
|
||||
printf("Rebooting in %2d seconds \r",i);
|
||||
for (index=0;index<1000;index++)
|
||||
udelay(1000);
|
||||
}
|
||||
putc('\n');
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
puts("FPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i=0; i<4; i++) {
|
||||
len = dst[index];
|
||||
printf("%s ", &(dst[index+1]));
|
||||
index += len+3;
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
free(dst);
|
||||
|
||||
/*
|
||||
* Reset FPGA
|
||||
*/
|
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
|
||||
udelay(10);
|
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr;
|
||||
|
||||
if (argc < 2)
|
||||
return cmd_usage(cmdtp);
|
||||
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
return do_fpga_boot((unsigned char *)addr);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
fpga, 2, 0, do_fpga,
|
||||
"boot FPGA",
|
||||
"address size\n - boot FPGA with gzipped image at <address>"
|
||||
);
|
||||
|
||||
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
|
||||
extern struct pci_controller hose;
|
||||
extern void pci_ixp_init(struct pci_controller * hose);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
extern void pci_ixp_init (struct pci_controller *hose);
|
||||
|
||||
pci_ixp_init(&hose);
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue