mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := pxa_idp.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,11 @@
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Tested:
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- MMC
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- Ethernet
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- BL console (on serial port connector J5)
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- flash support
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Todo:
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- display support
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- PCMCIA support
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@ -0,0 +1,46 @@
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Notes on the Vibren PXA255 IDP.
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Chip select usage:
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CS0 - flash
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CS1 - alt flash (Mdoc or main flash)
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CS2 - high speed expansion bus
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CS3 - Media Q, low speed exp bus
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CS4 - low speed exp bus
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CS5 - low speed exp bus
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- IDE: offset 0x03000000 (abs: 0x17000000)
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- Eth: offset 0x03400000 (abs: 0x17400000)
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- core voltage latch: offset 0x03800000 (abs: 0x17800000)
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- CPLD: offset 0x03C00000 (abs: 0x17C00000)
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PCMCIA Power control
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MAX1602EE w/ code pulled high (Cirrus code)
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vx = 5v
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vy = 3v
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Bit pattern
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PWR 3,2,1,0
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vcc vpp A1VCC A0VCC A1VPP A0VPP
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=====================================================
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0 0 0 0 0 0 0x0
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3 (vy) 0 1 0 1 1 0xB
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3 (vy) 3 (vy) 1 0 0 1 0x9
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3 (vy) 12(12in) 1 0 1 0 0xA
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5 (vx) 0 0 1 1 1 0x7
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5 (vx) 5 (vx) 0 1 0 1 0x5
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5 (vx 12(12in) 0 1 1 0 0x6
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Display power sequencing:
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- VDD applied
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- within 1sec, activate scanning signals
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- wait at least 50mS - scanning signals must be active before activating DISP
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Signal mapping:
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Schematic LV8V31 signal name
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=========================================
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LCD_ENAVLCD DISP
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LCD_PWR Applies VDD to board
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Both of the above signals are controlled by the CPLD
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@ -0,0 +1,147 @@
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/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2004
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* BEC Systems <http://bec-systems.com>
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* Cliff Brake <cliff.brake@gmail.com>
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* Support for Accelent/Vibren PXA255 IDP
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/arch/pxa.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of Lubbock-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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/* turn on serial ports */
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*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
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/* set PWM for LCD */
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/* a value that works is 60Hz, 77% duty cycle */
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writel(readl(CKEN) | CKEN0_PWM0, CKEN);
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writel(0x3f, PWM_CTRL0);
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writel(0x3ff, PWM_PERVAL0);
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writel(792, PWM_PWDUTY0);
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/* clear reset to AC97 codec */
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writel(readl(CKEN) | CKEN2_AC97, CKEN);
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writel(GCR_COLD_RST, GCR);
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/* enable LCD backlight */
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/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
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/* test display */
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/* lcd_puts("This is a test\nTest #2\n"); */
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return 0;
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}
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int board_late_init(void)
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{
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef DEBUG_BLINKC_ENABLE
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void delay_c(void)
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{
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/* reset OSCR to 0 */
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writel(0, OSCR);
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while (readl(OSCR) > 0x10000)
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;
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while (readl(OSCR) < 0xd4000)
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;
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}
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void blink_c(void)
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{
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int led_bit = (1<<10);
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writel(led_bit, GPDR0);
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writel(led_bit, GPCR0);
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delay_c();
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writel(led_bit, GPSR0);
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delay_c();
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writel(led_bit, GPCR0);
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}
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int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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printf("IDPCMD started\n");
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return 0;
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}
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U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
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"custom IDP command",
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"no args at this time"
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);
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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@ -0,0 +1,119 @@
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gafr0_l: 0x80001005
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gafr0_u: 0xa5128012
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gafr1_l: 0x699a9558
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gafr1_u: 0xaaa5aa6a
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gafr2_l: 0xaaaaaaaa
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gafr2_u: 0x2
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gpcr0: 0x1800400
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gpcr1: 0x0
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gpcr2: 0x0
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gpdr0: 0xc1818440
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gpdr1: 0xfcffab82
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gpdr2: 0x1ffff
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gpsr0: 0x8000
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gpsr1: 0x3f0002
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gpsr2: 0x1c000
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#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
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#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x2
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#define CONFIG_SYS_GPCR0_VAL 0x1800400
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#define CONFIG_SYS_GPCR1_VAL 0x0
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#define CONFIG_SYS_GPCR2_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xc1818440
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#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
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#define CONFIG_SYS_GPDR2_VAL 0x1ffff
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#define CONFIG_SYS_GPSR0_VAL 0x8000
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#define CONFIG_SYS_GPSR1_VAL 0x3f0002
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#define CONFIG_SYS_GPSR2_VAL 0x1c000
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GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
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GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
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GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
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GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
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GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
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GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
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GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
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GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
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GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
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GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
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GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
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GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
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GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
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GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
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GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
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GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
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GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
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GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
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GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
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GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
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GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
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GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
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GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
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GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
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GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
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GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
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GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
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GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
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GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
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GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
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GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
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GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
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GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
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GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
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GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
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GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
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GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
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GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
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GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
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GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
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GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
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GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
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GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
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GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
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GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
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GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
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GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
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GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
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GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
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GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
|
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GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
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GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
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GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
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GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
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GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
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GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
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GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
|
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GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
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||||
GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
|
||||
GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
|
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GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
|
||||
GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
|
||||
GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
|
||||
GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
|
||||
GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
|
||||
GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
|
||||
GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
|
||||
GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
|
||||
GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
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||||
GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
|
||||
GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
|
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GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
|
||||
GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
|
||||
GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
|
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GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
|
||||
GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
|
||||
GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
|
||||
GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
|
||||
GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
|
||||
GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
|
||||
GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
|
||||
GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
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||||
GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
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GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
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GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
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||||
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@ -0,0 +1,311 @@
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#!/usr/bin/python
|
||||
|
||||
# (C) Copyright 2004
|
||||
# BEC Systems <http://bec-systems.com>
|
||||
# Cliff Brake <cliff.brake@gmail.com>
|
||||
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
|
||||
# calculations for PXA255 registers
|
||||
|
||||
class gpio:
|
||||
dir = '0'
|
||||
set = '0'
|
||||
clr = '0'
|
||||
alt = '0'
|
||||
desc = ''
|
||||
|
||||
def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
|
||||
self.dir = dir
|
||||
self.set = set
|
||||
self.clr = clr
|
||||
self.alt = alt
|
||||
self.desc = desc
|
||||
|
||||
|
||||
# the following is a dictionary of all GPIOs in the system
|
||||
# the key is the GPIO number
|
||||
|
||||
|
||||
pxa255_alt_func = {
|
||||
0: ['gpio', 'none', 'none', 'none'],
|
||||
1: ['gpio', 'gpio reset', 'none', 'none'],
|
||||
2: ['gpio', 'none', 'none', 'none'],
|
||||
3: ['gpio', 'none', 'none', 'none'],
|
||||
4: ['gpio', 'none', 'none', 'none'],
|
||||
5: ['gpio', 'none', 'none', 'none'],
|
||||
6: ['gpio', 'MMC clk', 'none', 'none'],
|
||||
7: ['gpio', '48MHz clock', 'none', 'none'],
|
||||
8: ['gpio', 'MMC CS0', 'none', 'none'],
|
||||
9: ['gpio', 'MMC CS1', 'none', 'none'],
|
||||
10: ['gpio', 'RTC Clock', 'none', 'none'],
|
||||
11: ['gpio', '3.6MHz', 'none', 'none'],
|
||||
12: ['gpio', '32KHz', 'none', 'none'],
|
||||
13: ['gpio', 'none', 'MBGNT', 'none'],
|
||||
14: ['gpio', 'MBREQ', 'none', 'none'],
|
||||
15: ['gpio', 'none', 'nCS_1', 'none'],
|
||||
16: ['gpio', 'none', 'PWM0', 'none'],
|
||||
17: ['gpio', 'none', 'PWM1', 'none'],
|
||||
18: ['gpio', 'RDY', 'none', 'none'],
|
||||
19: ['gpio', 'DREQ[1]', 'none', 'none'],
|
||||
20: ['gpio', 'DREQ[0]', 'none', 'none'],
|
||||
21: ['gpio', 'none', 'none', 'none'],
|
||||
22: ['gpio', 'none', 'none', 'none'],
|
||||
23: ['gpio', 'none', 'SSP SCLK', 'none'],
|
||||
24: ['gpio', 'none', 'SSP SFRM', 'none'],
|
||||
25: ['gpio', 'none', 'SSP TXD', 'none'],
|
||||
26: ['gpio', 'SSP RXD', 'none', 'none'],
|
||||
27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
|
||||
28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
|
||||
29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
|
||||
30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
|
||||
31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
|
||||
32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
|
||||
33: ['gpio', 'none', 'nCS_5', 'none'],
|
||||
34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
|
||||
35: ['gpio', 'FF CTS', 'none', 'none'],
|
||||
36: ['gpio', 'FF DCD', 'none', 'none'],
|
||||
37: ['gpio', 'FF DSR', 'none', 'none'],
|
||||
38: ['gpio', 'FF RI', 'none', 'none'],
|
||||
39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
|
||||
40: ['gpio', 'none', 'FF DTR', 'none'],
|
||||
41: ['gpio', 'none', 'FF RTS', 'none'],
|
||||
42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
|
||||
43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
|
||||
44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
|
||||
45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
|
||||
46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
|
||||
47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
|
||||
48: ['gpio', 'HW TXD', 'nPOE', 'none'],
|
||||
49: ['gpio', 'HW RXD', 'nPWE', 'none'],
|
||||
50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
|
||||
51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
|
||||
52: ['gpio', 'none', 'nPCE[1]', 'none'],
|
||||
53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
|
||||
54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
|
||||
55: ['gpio', 'none', 'nPREG', 'none'],
|
||||
56: ['gpio', 'nPWAIT', 'none', 'none'],
|
||||
57: ['gpio', 'nIOIS16', 'none', 'none'],
|
||||
58: ['gpio', 'none', 'LDD[0]', 'none'],
|
||||
59: ['gpio', 'none', 'LDD[1]', 'none'],
|
||||
60: ['gpio', 'none', 'LDD[2]', 'none'],
|
||||
61: ['gpio', 'none', 'LDD[3]', 'none'],
|
||||
62: ['gpio', 'none', 'LDD[4]', 'none'],
|
||||
63: ['gpio', 'none', 'LDD[5]', 'none'],
|
||||
64: ['gpio', 'none', 'LDD[6]', 'none'],
|
||||
65: ['gpio', 'none', 'LDD[7]', 'none'],
|
||||
66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
|
||||
67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
|
||||
68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
|
||||
69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
|
||||
70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
|
||||
71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
|
||||
72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
|
||||
73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
|
||||
74: ['gpio', 'none', 'LCD_FCLK', 'none'],
|
||||
75: ['gpio', 'none', 'LCD_LCLK', 'none'],
|
||||
76: ['gpio', 'none', 'LCD_PCLK', 'none'],
|
||||
77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
|
||||
78: ['gpio', 'none', 'nCS_2', 'none'],
|
||||
79: ['gpio', 'none', 'nCS_3', 'none'],
|
||||
80: ['gpio', 'none', 'nCS_4', 'none'],
|
||||
81: ['gpio', 'NSSPSCLK', 'none', 'none'],
|
||||
82: ['gpio', 'NSSPSFRM', 'none', 'none'],
|
||||
83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
|
||||
84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
|
||||
}
|
||||
|
||||
|
||||
#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
|
||||
|
||||
gpio_list = []
|
||||
|
||||
for i in range(0,85):
|
||||
gpio_list.append(gpio())
|
||||
|
||||
#chip select GPIOs
|
||||
gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
|
||||
gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
|
||||
gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
|
||||
gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
|
||||
gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
|
||||
gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
|
||||
gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
|
||||
gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
|
||||
gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
|
||||
gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
|
||||
gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
|
||||
gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
|
||||
gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
|
||||
|
||||
# PCMCIA stuff
|
||||
gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
|
||||
gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
|
||||
gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
|
||||
gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
|
||||
gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
|
||||
gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
|
||||
gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
|
||||
gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
|
||||
gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
|
||||
gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
|
||||
|
||||
# SSP port
|
||||
gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
|
||||
gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
|
||||
gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
|
||||
gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
|
||||
gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
|
||||
|
||||
# audio codec
|
||||
gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
|
||||
gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
|
||||
gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
|
||||
gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
|
||||
gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
|
||||
|
||||
# serial ports
|
||||
gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
|
||||
gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
|
||||
gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
|
||||
gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
|
||||
gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
|
||||
gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
|
||||
gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
|
||||
gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
|
||||
|
||||
gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
|
||||
gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
|
||||
gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
|
||||
gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
|
||||
|
||||
gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
|
||||
gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
|
||||
|
||||
# misc GPIO signals
|
||||
gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
|
||||
gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
|
||||
gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
|
||||
gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
|
||||
gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
|
||||
gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
|
||||
gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
|
||||
gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
|
||||
gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
|
||||
gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
|
||||
gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
|
||||
gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
|
||||
gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
|
||||
gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
|
||||
gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
|
||||
|
||||
# LCD GPIOs
|
||||
gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
|
||||
gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
|
||||
gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
|
||||
gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
|
||||
gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
|
||||
gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
|
||||
gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
|
||||
gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
|
||||
gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
|
||||
gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
|
||||
gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
|
||||
gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
|
||||
gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
|
||||
gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
|
||||
gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
|
||||
gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
|
||||
gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
|
||||
gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
|
||||
gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
|
||||
gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
|
||||
|
||||
# calculate registers
|
||||
pxa_regs = {
|
||||
'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
|
||||
'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
|
||||
'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
|
||||
'gafr0_l':0, 'gafr0_u':0,
|
||||
'gafr1_l':0, 'gafr1_u':0,
|
||||
'gafr2_l':0, 'gafr2_u':0,
|
||||
}
|
||||
|
||||
# U-boot define names
|
||||
uboot_reg_names = {
|
||||
'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
|
||||
'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
|
||||
'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
|
||||
'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
|
||||
'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
|
||||
'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
|
||||
}
|
||||
|
||||
# bit mappings
|
||||
|
||||
bit_mappings = [
|
||||
|
||||
{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
|
||||
{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
|
||||
{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
|
||||
{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
|
||||
{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
|
||||
{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
|
||||
{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
|
||||
{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
|
||||
{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
|
||||
|
||||
]
|
||||
|
||||
def stuff_bits(bit_mapping, gpio_list):
|
||||
gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
|
||||
|
||||
for gpio in gpios:
|
||||
for reg in bit_mapping['regs'].keys():
|
||||
value = eval( 'gpio_list[gpio].%s' % (reg) )
|
||||
if ( value ):
|
||||
# we have a high bit
|
||||
bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
|
||||
bit = value << (bit_shift)
|
||||
pxa_regs[bit_mapping['regs'][reg]] |= bit
|
||||
|
||||
for i in bit_mappings:
|
||||
stuff_bits(i, gpio_list)
|
||||
|
||||
# now print out all regs
|
||||
registers = pxa_regs.keys()
|
||||
registers.sort()
|
||||
for reg in registers:
|
||||
print '%s: 0x%x' % (reg, pxa_regs[reg])
|
||||
|
||||
# print define to past right into U-Boot source code
|
||||
|
||||
print
|
||||
print
|
||||
|
||||
for reg in registers:
|
||||
print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
|
||||
|
||||
# print all GPIOS
|
||||
print
|
||||
print
|
||||
|
||||
for i in range(len(gpio_list)):
|
||||
gpio_i = gpio_list[i]
|
||||
alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
|
||||
print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue