mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
|
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Manage the atheros ethernet PHY.
|
||||
*
|
||||
* All definitions in this file are operating system independent!
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include "athrs17_phy.h"
|
||||
#include "../../../drivers/net/ipq/ipq_gmac.h"
|
||||
/******************************************************************************
|
||||
* FUNCTION DESCRIPTION: Read switch internal register.
|
||||
* Switch internal register is accessed through the
|
||||
* MDIO interface. MDIO access is only 16 bits wide so
|
||||
* it needs the two time access to complete the internal
|
||||
* register access.
|
||||
* INPUT : register address
|
||||
* OUTPUT : Register value
|
||||
*
|
||||
*****************************************************************************/
|
||||
static uint32_t
|
||||
athrs17_reg_read(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr)
|
||||
{
|
||||
uint32_t reg_word_addr;
|
||||
uint32_t phy_addr, reg_val;
|
||||
uint16_t phy_val;
|
||||
uint16_t tmp_val;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/* change reg_addr to 16-bit word address, 32-bit aligned */
|
||||
reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
|
||||
|
||||
/* configure register high address */
|
||||
phy_addr = 0x18;
|
||||
phy_reg = 0x0;
|
||||
phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/*
|
||||
* For some registers such as MIBs, since it is read/clear, we should
|
||||
* read the lower 16-bit register then the higher one
|
||||
*/
|
||||
|
||||
/* read register in lower address */
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
|
||||
miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &phy_val);
|
||||
|
||||
/* read register in higher address */
|
||||
reg_word_addr++;
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
|
||||
miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &tmp_val);
|
||||
reg_val = (tmp_val << 16 | phy_val);
|
||||
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FUNCTION DESCRIPTION: Write switch internal register.
|
||||
* Switch internal register is accessed through the
|
||||
* MDIO interface. MDIO access is only 16 bits wide so
|
||||
* it needs the two time access to complete the internal
|
||||
* register access.
|
||||
* INPUT : register address, value to be written
|
||||
* OUTPUT : NONE
|
||||
*
|
||||
*****************************************************************************/
|
||||
static void
|
||||
athrs17_reg_write(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr,
|
||||
uint32_t reg_val)
|
||||
{
|
||||
uint32_t reg_word_addr;
|
||||
uint32_t phy_addr;
|
||||
uint16_t phy_val;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/* change reg_addr to 16-bit word address, 32-bit aligned */
|
||||
reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
|
||||
|
||||
/* configure register high address */
|
||||
phy_addr = 0x18;
|
||||
phy_reg = 0x0;
|
||||
phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/*
|
||||
* For some registers such as ARL and VLAN, since they include BUSY bit
|
||||
* in lower address, we should write the higher 16-bit register then the
|
||||
* lower one
|
||||
*/
|
||||
|
||||
/* read register in higher address */
|
||||
reg_word_addr++;
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
|
||||
phy_val = (uint16_t) ((reg_val >> 16) & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/* write register in lower address */
|
||||
reg_word_addr--;
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
|
||||
phy_val = (uint16_t) (reg_val & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* FUNCTION DESCRIPTION: V-lan configuration given by Switch team
|
||||
Vlan 1:PHY0,1,2,3 and Mac 6 of s17c
|
||||
Vlan 2:PHY4 and Mac 0 of s17c
|
||||
* INPUT : NONE
|
||||
* OUTPUT: NONE
|
||||
*********************************************************************/
|
||||
void athrs17_vlan_config(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
athrs17_reg_write(gmac_cfg, S17_P0LOOKUP_CTRL_REG, 0x00140020);
|
||||
athrs17_reg_write(gmac_cfg, S17_P0VLAN_CTRL0_REG, 0x20001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P1LOOKUP_CTRL_REG, 0x0014005c);
|
||||
athrs17_reg_write(gmac_cfg, S17_P1VLAN_CTRL0_REG, 0x10001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P2LOOKUP_CTRL_REG, 0x0014005a);
|
||||
athrs17_reg_write(gmac_cfg, S17_P2VLAN_CTRL0_REG, 0x10001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P3LOOKUP_CTRL_REG, 0x00140056);
|
||||
athrs17_reg_write(gmac_cfg, S17_P3VLAN_CTRL0_REG, 0x10001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P4LOOKUP_CTRL_REG, 0x0014004e);
|
||||
athrs17_reg_write(gmac_cfg, S17_P4VLAN_CTRL0_REG, 0x10001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P5LOOKUP_CTRL_REG, 0x00140001);
|
||||
athrs17_reg_write(gmac_cfg, S17_P5VLAN_CTRL0_REG, 0x20001);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P6LOOKUP_CTRL_REG, 0x0014001e);
|
||||
athrs17_reg_write(gmac_cfg, S17_P6VLAN_CTRL0_REG, 0x10001);
|
||||
printf("%s ...done\n", __func__);
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* FUNCTION DESCRIPTION: Reset S17 register
|
||||
* INPUT: NONE
|
||||
* OUTPUT: NONE
|
||||
*******************************************************************/
|
||||
int athrs17_init_switch(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
uint32_t data;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* Reset the switch before initialization */
|
||||
athrs17_reg_write(gmac_cfg, S17_MASK_CTRL_REG, S17_MASK_CTRL_SOFT_RET);
|
||||
do {
|
||||
udelay(10);
|
||||
data = athrs17_reg_read(gmac_cfg, S17_MASK_CTRL_REG);
|
||||
} while (data & S17_MASK_CTRL_SOFT_RET);
|
||||
|
||||
do {
|
||||
udelay(10);
|
||||
data = athrs17_reg_read(gmac_cfg, S17_GLOBAL_INT0_REG);
|
||||
i++;
|
||||
if (i == 10)
|
||||
return -1;
|
||||
} while ((data & S17_GLOBAL_INITIALIZED_STATUS) != S17_GLOBAL_INITIALIZED_STATUS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* FUNCTION DESCRIPTION: Configure S17 register
|
||||
* INPUT : NONE
|
||||
* OUTPUT: NONE
|
||||
*********************************************************************/
|
||||
void athrs17_reg_init(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
data = athrs17_reg_read(gmac_cfg, S17_MAC_PWR_REG) | gmac_cfg->mac_pwr0;
|
||||
athrs17_reg_write(gmac_cfg, S17_MAC_PWR_REG, data);
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P0STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN |
|
||||
S17_RXMAC_EN | S17_TX_FLOW_EN |
|
||||
S17_RX_FLOW_EN | S17_DUPLEX_FULL));
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_GLOFW_CTRL1_REG, (S17_IGMP_JOIN_LEAVE_DPALL |
|
||||
S17_BROAD_DPALL |
|
||||
S17_MULTI_FLOOD_DPALL |
|
||||
S17_UNI_FLOOD_DPALL));
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P5PAD_MODE_REG, S17_MAC0_RGMII_RXCLK_DELAY);
|
||||
athrs17_reg_write(gmac_cfg, S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN | \
|
||||
S17_MAC0_RGMII_TXCLK_DELAY | S17_MAC0_RGMII_RXCLK_DELAY | \
|
||||
(0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) | \
|
||||
(0x3 << S17_MAC0_RGMII_RXCLK_SHIFT)));
|
||||
|
||||
printf("%s: complete\n", __func__);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* FUNCTION DESCRIPTION: Configure S17 register
|
||||
* INPUT : NONE
|
||||
* OUTPUT: NONE
|
||||
*********************************************************************/
|
||||
void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_P6STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN |
|
||||
S17_RXMAC_EN |
|
||||
S17_DUPLEX_FULL));
|
||||
|
||||
reg_val = athrs17_reg_read(gmac_cfg, S17_MAC_PWR_REG) | gmac_cfg->mac_pwr1;
|
||||
athrs17_reg_write(gmac_cfg, S17_MAC_PWR_REG, reg_val);
|
||||
|
||||
reg_val = athrs17_reg_read(gmac_cfg, S17_P6PAD_MODE_REG);
|
||||
athrs17_reg_write(gmac_cfg, S17_P6PAD_MODE_REG, (reg_val | S17_MAC6_SGMII_EN));
|
||||
|
||||
reg_val = athrs17_reg_read(gmac_cfg, S17_PWS_REG);
|
||||
athrs17_reg_write(gmac_cfg, S17_PWS_REG, (reg_val |
|
||||
S17c_PWS_SERDES_ANEG_DISABLE));
|
||||
|
||||
athrs17_reg_write(gmac_cfg, S17_SGMII_CTRL_REG,(S17c_SGMII_EN_PLL |
|
||||
S17c_SGMII_EN_RX |
|
||||
S17c_SGMII_EN_TX |
|
||||
S17c_SGMII_EN_SD |
|
||||
S17c_SGMII_BW_HIGH |
|
||||
S17c_SGMII_SEL_CLK125M |
|
||||
S17c_SGMII_TXDR_CTRL_600mV |
|
||||
S17c_SGMII_CDR_BW_8 |
|
||||
S17c_SGMII_DIS_AUTO_LPI_25M |
|
||||
S17c_SGMII_MODE_CTRL_SGMII_PHY |
|
||||
S17c_SGMII_PAUSE_SG_TX_EN_25M |
|
||||
S17c_SGMII_ASYM_PAUSE_25M |
|
||||
S17c_SGMII_PAUSE_25M |
|
||||
S17c_SGMII_HALF_DUPLEX_25M |
|
||||
S17c_SGMII_FULL_DUPLEX_25M));
|
||||
}
|
||||
|
||||
struct athrs17_regmap {
|
||||
uint32_t start;
|
||||
uint32_t end;
|
||||
};
|
||||
|
||||
struct athrs17_regmap regmap[] = {
|
||||
{ 0x000, 0x0e0 },
|
||||
{ 0x100, 0x168 },
|
||||
{ 0x200, 0x270 },
|
||||
{ 0x400, 0x454 },
|
||||
{ 0x600, 0x718 },
|
||||
{ 0x800, 0xb70 },
|
||||
{ 0xC00, 0xC80 },
|
||||
};
|
||||
|
||||
int do_ar8xxx_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(regmap); i++) {
|
||||
uint32_t reg;
|
||||
struct athrs17_regmap *section = ®map[i];
|
||||
|
||||
for (reg = section->start; reg <= section->end; reg += sizeof(uint32_t)) {
|
||||
ipq_gmac_board_cfg_t *gmac_tmp_cfg = gboard_param->gmac_cfg;
|
||||
uint32_t val = athrs17_reg_read(gmac_tmp_cfg, reg);
|
||||
printf("%03zu: %08zu\n", reg, val);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
};
|
||||
U_BOOT_CMD(
|
||||
ar8xxx_dump, 1, 1, do_ar8xxx_dump,
|
||||
"Dump ar8xxx registers",
|
||||
"\n - print all ar8xxx registers\n"
|
||||
);
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FUNCTION DESCRIPTION: This function invokes RGMII,
|
||||
* SGMII switch init routines.
|
||||
* INPUT : ipq_gmac_board_cfg_t *
|
||||
* OUTPUT: NONE
|
||||
*
|
||||
**********************************************************************/
|
||||
int ipq_athrs17_init(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (gmac_cfg == NULL)
|
||||
return -1;
|
||||
|
||||
ret = athrs17_init_switch(gmac_cfg);
|
||||
if (ret != -1) {
|
||||
athrs17_reg_init(gmac_cfg);
|
||||
athrs17_reg_init_lan(gmac_cfg);
|
||||
athrs17_vlan_config(gmac_cfg);
|
||||
printf ("S17c init done\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,613 @@
|
|||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ATHRS17_PHY_H
|
||||
#define _ATHRS17_PHY_H
|
||||
|
||||
/*****************/
|
||||
/* PHY Registers */
|
||||
/*****************/
|
||||
#define ATHR_PHY_CONTROL 0
|
||||
#define ATHR_PHY_STATUS 1
|
||||
#define ATHR_PHY_ID1 2
|
||||
#define ATHR_PHY_ID2 3
|
||||
#define ATHR_AUTONEG_ADVERT 4
|
||||
#define ATHR_LINK_PARTNER_ABILITY 5
|
||||
#define ATHR_AUTONEG_EXPANSION 6
|
||||
#define ATHR_NEXT_PAGE_TRANSMIT 7
|
||||
#define ATHR_LINK_PARTNER_NEXT_PAGE 8
|
||||
#define ATHR_1000BASET_CONTROL 9
|
||||
#define ATHR_1000BASET_STATUS 10
|
||||
#define ATHR_PHY_SPEC_CONTROL 16
|
||||
#define ATHR_PHY_SPEC_STATUS 17
|
||||
#define ATHR_DEBUG_PORT_ADDRESS 29
|
||||
#define ATHR_DEBUG_PORT_DATA 30
|
||||
|
||||
/* ATHR_PHY_CONTROL fields */
|
||||
#define ATHR_CTRL_SOFTWARE_RESET 0x8000
|
||||
#define ATHR_CTRL_SPEED_LSB 0x2000
|
||||
#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
|
||||
#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
|
||||
#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
|
||||
#define ATHR_CTRL_SPEED_MSB 0x0040
|
||||
|
||||
#define ATHR_RESET_DONE(phy_control) \
|
||||
(((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
|
||||
|
||||
/* Phy status fields */
|
||||
#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
|
||||
|
||||
#define ATHR_AUTONEG_DONE(ip_phy_status) \
|
||||
(((ip_phy_status) & \
|
||||
(ATHR_STATUS_AUTO_NEG_DONE)) == \
|
||||
(ATHR_STATUS_AUTO_NEG_DONE))
|
||||
|
||||
/* Link Partner ability */
|
||||
#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
|
||||
#define ATHR_LINK_100BASETX 0x0080
|
||||
#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
|
||||
#define ATHR_LINK_10BASETX 0x0020
|
||||
|
||||
/* Advertisement register. */
|
||||
#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
|
||||
#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
|
||||
#define ATHR_ADVERTISE_PAUSE 0x0400
|
||||
#define ATHR_ADVERTISE_100FULL 0x0100
|
||||
#define ATHR_ADVERTISE_100HALF 0x0080
|
||||
#define ATHR_ADVERTISE_10FULL 0x0040
|
||||
#define ATHR_ADVERTISE_10HALF 0x0020
|
||||
|
||||
#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
|
||||
ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
|
||||
ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
|
||||
|
||||
/* 1000BASET_CONTROL */
|
||||
#define ATHR_ADVERTISE_1000FULL 0x0200
|
||||
|
||||
/* Phy Specific status fields */
|
||||
#define ATHER_STATUS_LINK_MASK 0xC000
|
||||
#define ATHER_STATUS_LINK_SHIFT 14
|
||||
#define ATHER_STATUS_FULL_DEPLEX 0x2000
|
||||
#define ATHR_STATUS_LINK_PASS 0x0400
|
||||
#define ATHR_STATUS_RESOVLED 0x0800
|
||||
|
||||
/*phy debug port register */
|
||||
#define ATHER_DEBUG_SERDES_REG 5
|
||||
|
||||
/* Serdes debug fields */
|
||||
#define ATHER_SERDES_BEACON 0x0100
|
||||
|
||||
/* S17 CSR Registers */
|
||||
|
||||
#define S17_ENABLE_CPU_BROADCAST (1 << 26)
|
||||
|
||||
#define S17_PHY_LINK_CHANGE_REG 0x4
|
||||
#define S17_PHY_LINK_UP 0x400
|
||||
#define S17_PHY_LINK_DOWN 0x800
|
||||
#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000
|
||||
#define S17_PHY_LINK_SPEED_CHANGE 0x4000
|
||||
#define S17_PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE)
|
||||
|
||||
#define S17_MASK_CTRL_REG 0x0000
|
||||
#define S17_P0PAD_MODE_REG 0x0004
|
||||
#define S17_P5PAD_MODE_REG 0x0008
|
||||
#define S17_P6PAD_MODE_REG 0x000c
|
||||
#define S17_PWS_REG 0x0010
|
||||
#define S17_GLOBAL_INT0_REG 0x0020
|
||||
#define S17_GLOBAL_INT1_REG 0x0024
|
||||
#define S17_GLOBAL_INTMASK0 0x0028
|
||||
#define S17_GLOBAL_INTMASK1 0x002c
|
||||
#define S17_MODULE_EN_REG 0x0030
|
||||
#define S17_MIB_REG 0x0034
|
||||
#define S17_INTF_HIADDR_REG 0x0038
|
||||
#define S17_MDIO_CTRL_REG 0x003c
|
||||
#define S17_BIST_CTRL_REG 0x0040
|
||||
#define S17_BIST_REC_REG 0x0044
|
||||
#define S17_SERVICE_REG 0x0048
|
||||
#define S17_LED_CTRL0_REG 0x0050
|
||||
#define S17_LED_CTRL1_REG 0x0054
|
||||
#define S17_LED_CTRL2_REG 0x0058
|
||||
#define S17_LED_CTRL3_REG 0x005c
|
||||
#define S17_MACADDR0_REG 0x0060
|
||||
#define S17_MACADDR1_REG 0x0064
|
||||
#define S17_MAX_FRAME_SIZE_REG 0x0078
|
||||
#define S17_P0STATUS_REG 0x007c
|
||||
#define S17_P1STATUS_REG 0x0080
|
||||
#define S17_P2STATUS_REG 0x0084
|
||||
#define S17_P3STATUS_REG 0x0088
|
||||
#define S17_P4STATUS_REG 0x008c
|
||||
#define S17_P5STATUS_REG 0x0090
|
||||
#define S17_P6STATUS_REG 0x0094
|
||||
#define S17_HDRCTRL_REG 0x0098
|
||||
#define S17_P0HDRCTRL_REG 0x009c
|
||||
#define S17_P1HDRCTRL_REG 0x00A0
|
||||
#define S17_P2HDRCTRL_REG 0x00a4
|
||||
#define S17_P3HDRCTRL_REG 0x00a8
|
||||
#define S17_P4HDRCTRL_REG 0x00ac
|
||||
#define S17_P5HDRCTRL_REG 0x00b0
|
||||
#define S17_P6HDRCTRL_REG 0x00b4
|
||||
#define S17_SGMII_CTRL_REG 0x00e0
|
||||
#define S17_MAC_PWR_REG 0x00e4
|
||||
#define S17_EEE_CTRL_REG 0x0100
|
||||
|
||||
/* ACL Registers */
|
||||
#define S17_ACL_FUNC0_REG 0x0400
|
||||
#define S17_ACL_FUNC1_REG 0x0404
|
||||
#define S17_ACL_FUNC2_REG 0x0408
|
||||
#define S17_ACL_FUNC3_REG 0x040c
|
||||
#define S17_ACL_FUNC4_REG 0x0410
|
||||
#define S17_ACL_FUNC5_REG 0x0414
|
||||
#define S17_PRIVATE_IP_REG 0x0418
|
||||
#define S17_P0VLAN_CTRL0_REG 0x0420
|
||||
#define S17_P0VLAN_CTRL1_REG 0x0424
|
||||
#define S17_P1VLAN_CTRL0_REG 0x0428
|
||||
#define S17_P1VLAN_CTRL1_REG 0x042c
|
||||
#define S17_P2VLAN_CTRL0_REG 0x0430
|
||||
#define S17_P2VLAN_CTRL1_REG 0x0434
|
||||
#define S17_P3VLAN_CTRL0_REG 0x0438
|
||||
#define S17_P3VLAN_CTRL1_REG 0x043c
|
||||
#define S17_P4VLAN_CTRL0_REG 0x0440
|
||||
#define S17_P4VLAN_CTRL1_REG 0x0444
|
||||
#define S17_P5VLAN_CTRL0_REG 0x0448
|
||||
#define S17_P5VLAN_CTRL1_REG 0x044c
|
||||
#define S17_P6VLAN_CTRL0_REG 0x0450
|
||||
#define S17_P6VLAN_CTRL1_REG 0x0454
|
||||
|
||||
/* Table Lookup Registers */
|
||||
#define S17_ATU_DATA0_REG 0x0600
|
||||
#define S17_ATU_DATA1_REG 0x0604
|
||||
#define S17_ATU_DATA2_REG 0x0608
|
||||
#define S17_ATU_FUNC_REG 0x060C
|
||||
#define S17_VTU_FUNC0_REG 0x0610
|
||||
#define S17_VTU_FUNC1_REG 0x0614
|
||||
#define S17_ARL_CTRL_REG 0x0618
|
||||
#define S17_GLOFW_CTRL0_REG 0x0620
|
||||
#define S17_GLOFW_CTRL1_REG 0x0624
|
||||
#define S17_GLOLEARN_LIMIT_REG 0x0628
|
||||
#define S17_TOS_PRIMAP_REG0 0x0630
|
||||
#define S17_TOS_PRIMAP_REG1 0x0634
|
||||
#define S17_TOS_PRIMAP_REG2 0x0638
|
||||
#define S17_TOS_PRIMAP_REG3 0x063c
|
||||
#define S17_TOS_PRIMAP_REG4 0x0640
|
||||
#define S17_TOS_PRIMAP_REG5 0x0644
|
||||
#define S17_TOS_PRIMAP_REG6 0x0648
|
||||
#define S17_TOS_PRIMAP_REG7 0x064c
|
||||
#define S17_VLAN_PRIMAP_REG0 0x0650
|
||||
#define S17_LOOP_CHECK_REG 0x0654
|
||||
#define S17_P0LOOKUP_CTRL_REG 0x0660
|
||||
#define S17_P0PRI_CTRL_REG 0x0664
|
||||
#define S17_P0LEARN_LMT_REG 0x0668
|
||||
#define S17_P1LOOKUP_CTRL_REG 0x066c
|
||||
#define S17_P1PRI_CTRL_REG 0x0670
|
||||
#define S17_P1LEARN_LMT_REG 0x0674
|
||||
#define S17_P2LOOKUP_CTRL_REG 0x0678
|
||||
#define S17_P2PRI_CTRL_REG 0x067c
|
||||
#define S17_P2LEARN_LMT_REG 0x0680
|
||||
#define S17_P3LOOKUP_CTRL_REG 0x0684
|
||||
#define S17_P3PRI_CTRL_REG 0x0688
|
||||
#define S17_P3LEARN_LMT_REG 0x068c
|
||||
#define S17_P4LOOKUP_CTRL_REG 0x0690
|
||||
#define S17_P4PRI_CTRL_REG 0x0694
|
||||
#define S17_P4LEARN_LMT_REG 0x0698
|
||||
#define S17_P5LOOKUP_CTRL_REG 0x069c
|
||||
#define S17_P5PRI_CTRL_REG 0x06a0
|
||||
#define S17_P5LEARN_LMT_REG 0x06a4
|
||||
#define S17_P6LOOKUP_CTRL_REG 0x06a8
|
||||
#define S17_P6PRI_CTRL_REG 0x06ac
|
||||
#define S17_P6LEARN_LMT_REG 0x06b0
|
||||
#define S17_GLO_TRUNK_CTRL0_REG 0x0700
|
||||
#define S17_GLO_TRUNK_CTRL1_REG 0x0704
|
||||
#define S17_GLO_TRUNK_CTRL2_REG 0x0708
|
||||
|
||||
/* Queue Management Registers */
|
||||
#define S17_PORT0_HOL_CTRL0 0x0970
|
||||
#define S17_PORT0_HOL_CTRL1 0x0974
|
||||
#define S17_PORT1_HOL_CTRL0 0x0978
|
||||
#define S17_PORT1_HOL_CTRL1 0x097c
|
||||
#define S17_PORT2_HOL_CTRL0 0x0980
|
||||
#define S17_PORT2_HOL_CTRL1 0x0984
|
||||
#define S17_PORT3_HOL_CTRL0 0x0988
|
||||
#define S17_PORT3_HOL_CTRL1 0x098c
|
||||
#define S17_PORT4_HOL_CTRL0 0x0990
|
||||
#define S17_PORT4_HOL_CTRL1 0x0994
|
||||
#define S17_PORT5_HOL_CTRL0 0x0998
|
||||
#define S17_PORT5_HOL_CTRL1 0x099c
|
||||
#define S17_PORT6_HOL_CTRL0 0x09a0
|
||||
#define S17_PORT6_HOL_CTRL1 0x09a4
|
||||
|
||||
/* Port flow control registers */
|
||||
#define S17_P0_FLCTL_REG 0x09b0
|
||||
#define S17_P1_FLCTL_REG 0x09b4
|
||||
#define S17_P2_FLCTL_REG 0x09b8
|
||||
#define S17_P3_FLCTL_REG 0x09bc
|
||||
#define S17_P4_FLCTL_REG 0x09c0
|
||||
#define S17_P5_FLCTL_REG 0x09c4
|
||||
|
||||
/* Packet Edit registers */
|
||||
#define S17_PKT_EDIT_CTRL 0x0c00
|
||||
#define S17_P0Q_REMAP_REG0 0x0c40
|
||||
#define S17_P0Q_REMAP_REG1 0x0c44
|
||||
#define S17_P1Q_REMAP_REG0 0x0c48
|
||||
#define S17_P2Q_REMAP_REG0 0x0c4c
|
||||
#define S17_P3Q_REMAP_REG0 0x0c50
|
||||
#define S17_P4Q_REMAP_REG0 0x0c54
|
||||
#define S17_P5Q_REMAP_REG0 0x0c58
|
||||
#define S17_P5Q_REMAP_REG1 0x0c5c
|
||||
#define S17_P6Q_REMAP_REG0 0x0c60
|
||||
#define S17_P6Q_REMAP_REG1 0x0c64
|
||||
#define S17_ROUTER_VID0 0x0c70
|
||||
#define S17_ROUTER_VID1 0x0c74
|
||||
#define S17_ROUTER_VID2 0x0c78
|
||||
#define S17_ROUTER_VID3 0x0c7c
|
||||
#define S17_ROUTER_EG_VLAN_MODE 0x0c80
|
||||
|
||||
/* L3 Registers */
|
||||
#define S17_HROUTER_CTRL_REG 0x0e00
|
||||
#define S17_HROUTER_PBCTRL0_REG 0x0e04
|
||||
#define S17_HROUTER_PBCTRL1_REG 0x0e08
|
||||
#define S17_HROUTER_PBCTRL2_REG 0x0e0c
|
||||
#define S17_WCMP_HASH_TABLE0_REG 0x0e10
|
||||
#define S17_WCMP_HASH_TABLE1_REG 0x0e14
|
||||
#define S17_WCMP_HASH_TABLE2_REG 0x0e18
|
||||
#define S17_WCMP_HASH_TABLE3_REG 0x0e1c
|
||||
#define S17_WCMP_NHOP_TABLE0_REG 0x0e20
|
||||
#define S17_WCMP_NHOP_TABLE1_REG 0x0e24
|
||||
#define S17_WCMP_NHOP_TABLE2_REG 0x0e28
|
||||
#define S17_WCMP_NHOP_TABLE3_REG 0x0e2c
|
||||
#define S17_ARP_ENTRY_CTRL_REG 0x0e30
|
||||
#define S17_ARP_USECNT_REG 0x0e34
|
||||
#define S17_HNAT_CTRL_REG 0x0e38
|
||||
#define S17_NAPT_ENTRY_CTRL0_REG 0x0e3c
|
||||
#define S17_NAPT_ENTRY_CTRL1_REG 0x0e40
|
||||
#define S17_NAPT_USECNT_REG 0x0e44
|
||||
#define S17_ENTRY_EDIT_DATA0_REG 0x0e48
|
||||
#define S17_ENTRY_EDIT_DATA1_REG 0x0e4c
|
||||
#define S17_ENTRY_EDIT_DATA2_REG 0x0e50
|
||||
#define S17_ENTRY_EDIT_DATA3_REG 0x0e54
|
||||
#define S17_ENTRY_EDIT_CTRL_REG 0x0e58
|
||||
#define S17_HNAT_PRIVATE_IP_REG 0x0e5c
|
||||
|
||||
/* MIB counters */
|
||||
#define S17_MIB_PORT0 0x1000
|
||||
#define S17_MIB_PORT1 0x1100
|
||||
#define S17_MIB_PORT2 0x1200
|
||||
#define S17_MIB_PORT3 0x1300
|
||||
#define S17_MIB_PORT4 0x1400
|
||||
#define S17_MIB_PORT5 0x1500
|
||||
#define S17_MIB_PORT6 0x1600
|
||||
|
||||
#define S17_MIB_RXBROAD 0x0
|
||||
#define S17_MIB_RXPAUSE 0x4
|
||||
#define S17_MIB_RXMULTI 0x8
|
||||
#define S17_MIB_RXFCSERR 0xC
|
||||
#define S17_MIB_RXALIGNERR 0x10
|
||||
#define S17_MIB_RXUNDERSIZE 0x14
|
||||
#define S17_MIB_RXFRAG 0x18
|
||||
#define S17_MIB_RX64B 0x1C
|
||||
#define S17_MIB_RX128B 0x20
|
||||
#define S17_MIB_RX256B 0x24
|
||||
#define S17_MIB_RX512B 0x28
|
||||
#define S17_MIB_RX1024B 0x2C
|
||||
#define S17_MIB_RX1518B 0x30
|
||||
#define S17_MIB_RXMAXB 0x34
|
||||
#define S17_MIB_RXTOOLONG 0x38
|
||||
#define S17_MIB_RXBYTE1 0x3C
|
||||
#define S17_MIB_RXBYTE2 0x40
|
||||
#define S17_MIB_RXOVERFLOW 0x4C
|
||||
#define S17_MIB_FILTERED 0x50
|
||||
#define S17_MIB_TXBROAD 0x54
|
||||
#define S17_MIB_TXPAUSE 0x58
|
||||
#define S17_MIB_TXMULTI 0x5C
|
||||
#define S17_MIB_TXUNDERRUN 0x60
|
||||
#define S17_MIB_TX64B 0x64
|
||||
#define S17_MIB_TX128B 0x68
|
||||
#define S17_MIB_TX256B 0x6c
|
||||
#define S17_MIB_TX512B 0x70
|
||||
#define S17_MIB_TX1024B 0x74
|
||||
#define S17_MIB_TX1518B 0x78
|
||||
#define S17_MIB_TXMAXB 0x7C
|
||||
#define S17_MIB_TXOVERSIZE 0x80
|
||||
#define S17_MIB_TXBYTE1 0x84
|
||||
#define S17_MIB_TXBYTE2 0x88
|
||||
#define S17_MIB_TXCOL 0x8C
|
||||
#define S17_MIB_TXABORTCOL 0x90
|
||||
#define S17_MIB_TXMULTICOL 0x94
|
||||
#define S17_MIB_TXSINGLECOL 0x98
|
||||
#define S17_MIB_TXEXCDEFER 0x9C
|
||||
#define S17_MIB_TXDEFER 0xA0
|
||||
#define S17_MIB_TXLATECOL 0xA4
|
||||
|
||||
/* Register fields */
|
||||
#define S17_CHIPID_V1_0 0x1201
|
||||
#define S17_CHIPID_V1_1 0x1202
|
||||
|
||||
#define S17_MASK_CTRL_SOFT_RET (1 << 31)
|
||||
|
||||
#define S17_GLOBAL_INT0_ACL_INI_INT (1<<29)
|
||||
#define S17_GLOBAL_INT0_LOOKUP_INI_INT (1<<28)
|
||||
#define S17_GLOBAL_INT0_QM_INI_INT (1<<27)
|
||||
#define S17_GLOBAL_INT0_MIB_INI_INT (1<<26)
|
||||
#define S17_GLOBAL_INT0_OFFLOAD_INI_INT (1<<25)
|
||||
#define S17_GLOBAL_INT0_HARDWARE_INI_DONE (1<<24)
|
||||
|
||||
#define S17_GLOBAL_INITIALIZED_STATUS \
|
||||
( \
|
||||
S17_GLOBAL_INT0_ACL_INI_INT | \
|
||||
S17_GLOBAL_INT0_LOOKUP_INI_INT | \
|
||||
S17_GLOBAL_INT0_QM_INI_INT | \
|
||||
S17_GLOBAL_INT0_MIB_INI_INT | \
|
||||
S17_GLOBAL_INT0_OFFLOAD_INI_INT | \
|
||||
S17_GLOBAL_INT0_HARDWARE_INI_DONE \
|
||||
)
|
||||
|
||||
#define S17_MAC0_MAC_MII_RXCLK_SEL (1 << 0)
|
||||
#define S17_MAC0_MAC_MII_TXCLK_SEL (1 << 1)
|
||||
#define S17_MAC0_MAC_MII_EN (1 << 2)
|
||||
#define S17_MAC0_MAC_GMII_RXCLK_SEL (1 << 4)
|
||||
#define S17_MAC0_MAC_GMII_TXCLK_SEL (1 << 5)
|
||||
#define S17_MAC0_MAC_GMII_EN (1 << 6)
|
||||
#define S17_MAC0_SGMII_EN (1 << 7)
|
||||
#define S17_MAC0_PHY_MII_RXCLK_SEL (1 << 8)
|
||||
#define S17_MAC0_PHY_MII_TXCLK_SEL (1 << 9)
|
||||
#define S17_MAC0_PHY_MII_EN (1 << 10)
|
||||
#define S17_MAC0_PHY_MII_PIPE_SEL (1 << 11)
|
||||
#define S17_MAC0_PHY_GMII_RXCLK_SEL (1 << 12)
|
||||
#define S17_MAC0_PHY_GMII_TXCLK_SEL (1 << 13)
|
||||
#define S17_MAC0_PHY_GMII_EN (1 << 14)
|
||||
#define S17_MAC0_RGMII_RXCLK_SHIFT 20
|
||||
#define S17_MAC0_RGMII_TXCLK_SHIFT 22
|
||||
#define S17_MAC0_RGMII_RXCLK_DELAY (1 << 24)
|
||||
#define S17_MAC0_RGMII_TXCLK_DELAY (1 << 25)
|
||||
#define S17_MAC0_RGMII_EN (1 << 26)
|
||||
|
||||
#define S17_MAC5_MAC_MII_RXCLK_SEL (1 << 0)
|
||||
#define S17_MAC5_MAC_MII_TXCLK_SEL (1 << 1)
|
||||
#define S17_MAC5_MAC_MII_EN (1 << 2)
|
||||
#define S17_MAC5_PHY_MII_RXCLK_SEL (1 << 8)
|
||||
#define S17_MAC5_PHY_MII_TXCLK_SEL (1 << 9)
|
||||
#define S17_MAC5_PHY_MII_EN (1 << 10)
|
||||
#define S17_MAC5_PHY_MII_PIPE_SEL (1 << 11)
|
||||
#define S17_MAC5_RGMII_RXCLK_SHIFT 20
|
||||
#define S17_MAC5_RGMII_TXCLK_SHIFT 22
|
||||
#define S17_MAC5_RGMII_RXCLK_DELAY (1 << 24)
|
||||
#define S17_MAC5_RGMII_TXCLK_DELAY (1 << 25)
|
||||
#define S17_MAC5_RGMII_EN (1 << 26)
|
||||
|
||||
#define S17_MAC6_MAC_MII_RXCLK_SEL (1 << 0)
|
||||
#define S17_MAC6_MAC_MII_TXCLK_SEL (1 << 1)
|
||||
#define S17_MAC6_MAC_MII_EN (1 << 2)
|
||||
#define S17_MAC6_MAC_GMII_RXCLK_SEL (1 << 4)
|
||||
#define S17_MAC6_MAC_GMII_TXCLK_SEL (1 << 5)
|
||||
#define S17_MAC6_MAC_GMII_EN (1 << 6)
|
||||
#define S17_MAC6_SGMII_EN (1 << 7)
|
||||
#define S17_MAC6_PHY_MII_RXCLK_SEL (1 << 8)
|
||||
#define S17_MAC6_PHY_MII_TXCLK_SEL (1 << 9)
|
||||
#define S17_MAC6_PHY_MII_EN (1 << 10)
|
||||
#define S17_MAC6_PHY_MII_PIPE_SEL (1 << 11)
|
||||
#define S17_MAC6_PHY_GMII_RXCLK_SEL (1 << 12)
|
||||
#define S17_MAC6_PHY_GMII_TXCLK_SEL (1 << 13)
|
||||
#define S17_MAC6_PHY_GMII_EN (1 << 14)
|
||||
#define S17_PHY4_GMII_EN (1 << 16)
|
||||
#define S17_PHY4_RGMII_EN (1 << 17)
|
||||
#define S17_PHY4_MII_EN (1 << 18)
|
||||
#define S17_MAC6_RGMII_RXCLK_SHIFT 20
|
||||
#define S17_MAC6_RGMII_TXCLK_SHIFT 22
|
||||
#define S17_MAC6_RGMII_RXCLK_DELAY (1 << 24)
|
||||
#define S17_MAC6_RGMII_TXCLK_DELAY (1 << 25)
|
||||
#define S17_MAC6_RGMII_EN (1 << 26)
|
||||
|
||||
#define S17_SPEED_10M (0 << 0)
|
||||
#define S17_SPEED_100M (1 << 0)
|
||||
#define S17_SPEED_1000M (2 << 0)
|
||||
#define S17_TXMAC_EN (1 << 2)
|
||||
#define S17_RXMAC_EN (1 << 3)
|
||||
#define S17_TX_FLOW_EN (1 << 4)
|
||||
#define S17_RX_FLOW_EN (1 << 5)
|
||||
#define S17_DUPLEX_FULL (1 << 6)
|
||||
#define S17_DUPLEX_HALF (0 << 6)
|
||||
#define S17_TX_HALF_FLOW_EN (1 << 7)
|
||||
#define S17_LINK_EN (1 << 9)
|
||||
#define S17_FLOW_LINK_EN (1 << 12)
|
||||
#define S17_PORT_STATUS_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \
|
||||
S17_RXMAC_EN | S17_TX_FLOW_EN | \
|
||||
S17_RX_FLOW_EN | S17_DUPLEX_FULL | \
|
||||
S17_TX_HALF_FLOW_EN)
|
||||
|
||||
#define S17_PORT_STATUS_AZ_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \
|
||||
S17_RXMAC_EN | S17_TX_FLOW_EN | \
|
||||
S17_RX_FLOW_EN | S17_DUPLEX_FULL)
|
||||
|
||||
|
||||
#define S17_HDRLENGTH_SEL (1 << 16)
|
||||
#define S17_HDR_VALUE 0xAAAA
|
||||
|
||||
#define S17_TXHDR_MODE_NO 0
|
||||
#define S17_TXHDR_MODE_MGM 1
|
||||
#define S17_TXHDR_MODE_ALL 2
|
||||
#define S17_RXHDR_MODE_NO (0 << 2)
|
||||
#define S17_RXHDR_MODE_MGM (1 << 2)
|
||||
#define S17_RXHDR_MODE_ALL (2 << 2)
|
||||
|
||||
#define S17_CPU_PORT_EN (1 << 10)
|
||||
#define S17_PPPOE_REDIR_EN (1 << 8)
|
||||
#define S17_MIRROR_PORT_SHIFT 4
|
||||
#define S17_IGMP_COPY_EN (1 << 3)
|
||||
#define S17_RIP_COPY_EN (1 << 2)
|
||||
#define S17_EAPOL_REDIR_EN (1 << 0)
|
||||
|
||||
#define S17_IGMP_JOIN_LEAVE_DP_SHIFT 24
|
||||
#define S17_BROAD_DP_SHIFT 16
|
||||
#define S17_MULTI_FLOOD_DP_SHIFT 8
|
||||
#define S17_UNI_FLOOD_DP_SHIFT 0
|
||||
#define S17_IGMP_JOIN_LEAVE_DPALL (0x7f << S17_IGMP_JOIN_LEAVE_DP_SHIFT)
|
||||
#define S17_BROAD_DPALL (0x7f << S17_BROAD_DP_SHIFT)
|
||||
#define S17_MULTI_FLOOD_DPALL (0x7f << S17_MULTI_FLOOD_DP_SHIFT)
|
||||
#define S17_UNI_FLOOD_DPALL (0x7f << S17_UNI_FLOOD_DP_SHIFT)
|
||||
|
||||
#define S17_PWS_CHIP_AR8327 (1 << 30)
|
||||
#define S17c_PWS_SERDES_ANEG_DISABLE (1 << 7)
|
||||
|
||||
/* S17_PHY_CONTROL fields */
|
||||
#define S17_CTRL_SOFTWARE_RESET 0x8000
|
||||
#define S17_CTRL_SPEED_LSB 0x2000
|
||||
#define S17_CTRL_AUTONEGOTIATION_ENABLE 0x1000
|
||||
#define S17_CTRL_RESTART_AUTONEGOTIATION 0x0200
|
||||
#define S17_CTRL_SPEED_FULL_DUPLEX 0x0100
|
||||
#define S17_CTRL_SPEED_MSB 0x0040
|
||||
|
||||
/* For EEE_CTRL_REG */
|
||||
#define S17_LPI_DISABLE_P1 (1 << 4)
|
||||
#define S17_LPI_DISABLE_P2 (1 << 6)
|
||||
#define S17_LPI_DISABLE_P3 (1 << 8)
|
||||
#define S17_LPI_DISABLE_P4 (1 << 10)
|
||||
#define S17_LPI_DISABLE_P5 (1 << 12)
|
||||
#define S17_LPI_DISABLE_ALL 0x1550
|
||||
|
||||
/* For MMD register control */
|
||||
#define S17_MMD_FUNC_ADDR (0 << 14)
|
||||
#define S17_MMD_FUNC_DATA (1 << 14)
|
||||
#define S17_MMD_FUNC_DATA_2 (2 << 14)
|
||||
#define S17_MMD_FUNC_DATA_3 (3 << 14)
|
||||
|
||||
/* For phyInfo_t azFeature */
|
||||
#define S17_8023AZ_PHY_ENABLED (1 << 0)
|
||||
#define S17_8023AZ_PHY_LINKED (1 << 1)
|
||||
|
||||
/* Queue Management registe fields */
|
||||
#define S17_HOL_CTRL0_LAN 0x2a008888 /* egress priority 8, eg_portq = 0x2a */
|
||||
#define S17_HOL_CTRL0_WAN 0x2a666666 /* egress priority 6, eg_portq = 0x2a */
|
||||
#define S17_HOL_CTRL1_DEFAULT 0xc6 /* enable HOL control */
|
||||
|
||||
/* Packet Edit register fields */
|
||||
#define S17_ROUTER_EG_UNMOD 0x0 /* unmodified */
|
||||
#define S17_ROUTER_EG_WOVLAN 0x1 /* without VLAN */
|
||||
#define S17_ROUTER_EG_WVLAN 0x2 /* with VLAN */
|
||||
#define S17_ROUTER_EG_UNTOUCH 0x3 /* untouched */
|
||||
#define S17_ROUTER_EG_MODE_DEFAULT 0x01111111 /* all ports without VLAN */
|
||||
|
||||
#define S17_RESET_DONE(phy_control) \
|
||||
(((phy_control) & (S17_CTRL_SOFTWARE_RESET)) == 0)
|
||||
|
||||
/* Phy status fields */
|
||||
#define S17_STATUS_AUTO_NEG_DONE 0x0020
|
||||
|
||||
#define S17_AUTONEG_DONE(ip_phy_status) \
|
||||
(((ip_phy_status) & \
|
||||
(S17_STATUS_AUTO_NEG_DONE)) == \
|
||||
(S17_STATUS_AUTO_NEG_DONE))
|
||||
|
||||
/* Link Partner ability */
|
||||
#define S17_LINK_100BASETX_FULL_DUPLEX 0x0100
|
||||
#define S17_LINK_100BASETX 0x0080
|
||||
#define S17_LINK_10BASETX_FULL_DUPLEX 0x0040
|
||||
#define S17_LINK_10BASETX 0x0020
|
||||
|
||||
/* Advertisement register. */
|
||||
#define S17_ADVERTISE_NEXT_PAGE 0x8000
|
||||
#define S17_ADVERTISE_ASYM_PAUSE 0x0800
|
||||
#define S17_ADVERTISE_PAUSE 0x0400
|
||||
#define S17_ADVERTISE_100FULL 0x0100
|
||||
#define S17_ADVERTISE_100HALF 0x0080
|
||||
#define S17_ADVERTISE_10FULL 0x0040
|
||||
#define S17_ADVERTISE_10HALF 0x0020
|
||||
|
||||
#define S17_ADVERTISE_ALL (S17_ADVERTISE_ASYM_PAUSE | S17_ADVERTISE_PAUSE | \
|
||||
S17_ADVERTISE_10HALF | S17_ADVERTISE_10FULL | \
|
||||
S17_ADVERTISE_100HALF | S17_ADVERTISE_100FULL)
|
||||
|
||||
/* 1000BASET_CONTROL */
|
||||
#define S17_ADVERTISE_1000FULL 0x0200
|
||||
|
||||
/* Phy Specific status fields */
|
||||
#define S17_STATUS_LINK_MASK 0xC000
|
||||
#define S17_STATUS_LINK_SHIFT 14
|
||||
#define S17_STATUS_FULL_DEPLEX 0x2000
|
||||
#define S17_STATUS_LINK_PASS 0x0400
|
||||
#define S17_STATUS_RESOLVED 0x0800
|
||||
#define S17_STATUS_LINK_10M 0
|
||||
#define S17_STATUS_LINK_100M 1
|
||||
#define S17_STATUS_LINK_1000M 2
|
||||
|
||||
#define S17_GLOBAL_INT_PHYMASK (1 << 15)
|
||||
|
||||
#define S17_PHY_LINK_UP 0x400
|
||||
#define S17_PHY_LINK_DOWN 0x800
|
||||
#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000
|
||||
#define S17_PHY_LINK_SPEED_CHANGE 0x4000
|
||||
|
||||
/* For Port flow control registers */
|
||||
#define S17_PORT_FLCTL_XON_DEFAULT (0x3a << 16)
|
||||
#define S17_PORT_FLCTL_XOFF_DEFAULT (0x4a)
|
||||
|
||||
/* Module enable Register */
|
||||
#define S17_MODULE_L3_EN (1 << 2)
|
||||
#define S17_MODULE_ACL_EN (1 << 1)
|
||||
#define S17_MODULE_MIB_EN (1 << 0)
|
||||
|
||||
/* MIB Function Register 1 */
|
||||
#define S17_MIB_FUNC_ALL (3 << 24)
|
||||
#define S17_MIB_CPU_KEEP (1 << 20)
|
||||
#define S17_MIB_BUSY (1 << 17)
|
||||
#define S17_MIB_AT_HALF_EN (1 << 16)
|
||||
#define S17_MIB_TIMER_DEFAULT 0x100
|
||||
|
||||
#define S17_MAC_MAX 7
|
||||
|
||||
/* MAC power selector bit definitions */
|
||||
#define S17_RGMII0_1_8V (1 << 19)
|
||||
#define S17_RGMII1_1_8V (1 << 18)
|
||||
|
||||
/* SGMII_CTRL bit definitions */
|
||||
#define S17c_SGMII_EN_LCKDT (1 << 0)
|
||||
#define S17c_SGMII_EN_PLL (1 << 1)
|
||||
#define S17c_SGMII_EN_RX (1 << 2)
|
||||
#define S17c_SGMII_EN_TX (1 << 3)
|
||||
#define S17c_SGMII_EN_SD (1 << 4)
|
||||
#define S17c_SGMII_BW_HIGH (1 << 6)
|
||||
#define S17c_SGMII_SEL_CLK125M (1 << 7)
|
||||
#define S17c_SGMII_TXDR_CTRL_600mV (1 << 10)
|
||||
#define S17c_SGMII_CDR_BW_8 (3 << 13)
|
||||
#define S17c_SGMII_DIS_AUTO_LPI_25M (1 << 16)
|
||||
#define S17c_SGMII_MODE_CTRL_SGMII_PHY (1 << 22)
|
||||
#define S17c_SGMII_PAUSE_SG_TX_EN_25M (1 << 24)
|
||||
#define S17c_SGMII_ASYM_PAUSE_25M (1 << 25)
|
||||
#define S17c_SGMII_PAUSE_25M (1 << 26)
|
||||
#define S17c_SGMII_HALF_DUPLEX_25M (1 << 30)
|
||||
#define S17c_SGMII_FULL_DUPLEX_25M (1 << 31)
|
||||
|
||||
#ifndef BOOL
|
||||
#define BOOL int
|
||||
#endif
|
||||
|
||||
/*add feature define here*/
|
||||
|
||||
#ifdef CONFIG_AR7242_S17_PHY
|
||||
#undef HEADER_REG_CONF
|
||||
#undef HEADER_EN
|
||||
#endif
|
||||
int athrs17_init_switch(ipq_gmac_board_cfg_t *gmac_cfg);
|
||||
void athrs17_reg_init(ipq_gmac_board_cfg_t *);
|
||||
void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg);
|
||||
void athrs17_vlan_config(ipq_gmac_board_cfg_t *gmac_cfg);
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2013 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _IPQ806X_PHY_H
|
||||
#define _IPQ806X_PHY_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
extern u16 ATH_GMAC_read_phy_reg(u32 *RegBase, u32 PhyBase, u32 RegOffset);
|
||||
extern s32 GMAC_write_phy_reg(u32 *RegBase, u32 PhyBase, u32 RegOffset, u16 *data);
|
||||
|
||||
#define phy_reg_read(base, addr, reg) \
|
||||
ATH_GMAC_read_phy_reg(0x37000000, addr, reg)
|
||||
|
||||
#define phy_reg_write(base, addr, reg, data) \
|
||||
GMAC_write_phy_reg(0x37000000, addr, reg, data)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,557 @@
|
|||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Manage the QCA8511 Music Switch.
|
||||
*
|
||||
* All definitions in this file are operating system independent!
|
||||
*/
|
||||
|
||||
#include <miiphy.h>
|
||||
#include "athrs17_phy.h"
|
||||
#include "qca8511.h"
|
||||
#include "../../../drivers/net/ipq/ipq_gmac.h"
|
||||
#undef DEBUG
|
||||
#ifdef DEBUG
|
||||
#define dbg(format, arg...) dbg("DEBUG: " format "\n", ## arg)
|
||||
#else
|
||||
#define dbg(format, arg...) do {} while(0)
|
||||
#endif /* DEBUG */
|
||||
ipq_gmac_board_cfg_t *gmac_cfg_qca8511;
|
||||
|
||||
static uint32_t
|
||||
qca8511_pp_reg_read(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr)
|
||||
{
|
||||
uint32_t reg_word_addr;
|
||||
uint32_t phy_addr, reg_val;
|
||||
uint16_t phy_val;
|
||||
uint16_t tmp_val;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/*
|
||||
* Change reg_addr to 16-bit word address, 32-bit aligned.
|
||||
*/
|
||||
reg_word_addr = (reg_addr & 0xfffffffc) ;
|
||||
dbg("WJL %s: 0-reg_addr=0x%08x, reg_word_addr=0x%08x.\n\n",
|
||||
__func__, reg_addr, reg_word_addr);
|
||||
|
||||
/*
|
||||
* configure register high address;
|
||||
*/
|
||||
phy_addr = 0x18 | (reg_word_addr >> 29);
|
||||
phy_reg = (reg_word_addr & 0x1f000000) >> 24;
|
||||
/*
|
||||
* Bit23-8 of reg address
|
||||
*/
|
||||
phy_val = (uint16_t) ((reg_word_addr >> 8) & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
dbg("WJL %s: 1-w.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/*
|
||||
* For some registers such as MIBs, since it is read/clear,
|
||||
* we should read the lower 16-bit register then the higher one
|
||||
*/
|
||||
|
||||
/*
|
||||
* Read register in lower address
|
||||
* Bit7-5 of reg address
|
||||
*/
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
|
||||
/*
|
||||
* Bit4-0 of reg address.
|
||||
*/
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f);
|
||||
miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &phy_val);
|
||||
dbg("WJL %s: 2-r.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x, reg_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val, reg_val);
|
||||
|
||||
/*
|
||||
* Read register in higher address
|
||||
* bit7-5 of reg address
|
||||
*/
|
||||
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
|
||||
/*
|
||||
* Bit4-0 of reg address.
|
||||
*/
|
||||
phy_reg = (uint8_t) ((reg_word_addr & 0x1f) | 0x2);
|
||||
miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &tmp_val);
|
||||
reg_val = (tmp_val << 16 | phy_val);
|
||||
|
||||
dbg("WJL %s: 3-r.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x, reg_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val, reg_val);
|
||||
|
||||
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
static void qca8511_pp_reg_write(ipq_gmac_board_cfg_t *gmac_cfg,
|
||||
uint32_t reg_addr, uint32_t reg_val)
|
||||
{
|
||||
uint32_t reg_word_addr;
|
||||
uint32_t phy_addr;
|
||||
uint16_t phy_val;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/*
|
||||
* change reg_addr to 16-bit word address,
|
||||
* 32-bit aligned
|
||||
*/
|
||||
reg_word_addr = (reg_addr & 0xfffffffc);
|
||||
dbg("WJL %s: 0-reg_addr=0x%08x, reg_word_addr=0x%08x.\n\n",
|
||||
__func__, reg_addr, reg_word_addr);
|
||||
|
||||
/*
|
||||
* configure register high address
|
||||
*/
|
||||
phy_addr = 0x18 | (reg_word_addr >> 29);
|
||||
phy_reg = (reg_word_addr & 0x1f000000) >> 24;
|
||||
/*
|
||||
* Bit23-8 of reg address.
|
||||
*/
|
||||
phy_val = (uint16_t) ((reg_word_addr >> 8) & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
dbg("WJL %s: 1-w.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val);
|
||||
/*
|
||||
* For some registers such as ARL and VLAN, since they include BUSY bit
|
||||
* in lower address, we should write the higher 16-bit register then the
|
||||
* lower one
|
||||
*/
|
||||
|
||||
/*
|
||||
* write register in higher address
|
||||
* bit7-5 of reg address
|
||||
*/
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
|
||||
/*
|
||||
* bit4-0 of reg address
|
||||
*/
|
||||
phy_reg = (uint8_t) (reg_word_addr & 0x1f);
|
||||
/*
|
||||
* lowest 16bit data
|
||||
*/
|
||||
phy_val = (uint16_t) (reg_val & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
|
||||
dbg("WJL %s: 2-w.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x, reg_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val, reg_val);
|
||||
|
||||
/*
|
||||
* write register in lower address
|
||||
* bit7-5 of reg address
|
||||
*/
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
|
||||
/*
|
||||
* Bit4-0 of reg address
|
||||
*/
|
||||
phy_reg = (uint8_t) ((reg_word_addr & 0x1f) | 0x2);
|
||||
/*
|
||||
* Highest 16bit data
|
||||
*/
|
||||
phy_val = (uint16_t) ((reg_val >> 16) & 0xffff);
|
||||
miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val);
|
||||
|
||||
dbg("WJL %s: 3-w.phy_addr=0x%04x, phy_reg=0x%04x,"
|
||||
"phy_val=0x%04x, reg_val=0x%04x.\n\n",
|
||||
__func__, phy_addr, phy_reg, phy_val, reg_val);
|
||||
|
||||
}
|
||||
|
||||
static uint32_t qca8511_pp_phy_reg_read(ipq_gmac_board_cfg_t *gmac_cfg,
|
||||
uint32_t phy_sel, uint32_t phy_addr,
|
||||
uint8_t reg_addr)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
/*
|
||||
* B31,MDIO_BUSY
|
||||
*/
|
||||
reg_val = (1 << 31);
|
||||
/*
|
||||
* B27, MDIO_CMD 0 = Write;1 = Read
|
||||
*/
|
||||
reg_val |= (1 << 27);
|
||||
/*
|
||||
* B29:28, PHY_SEL MDIO channel for MDIO master.
|
||||
* It is used to specify PHY group that to be operated.
|
||||
*/
|
||||
reg_val |= ((phy_sel & 0x3) << 28);
|
||||
/*
|
||||
* B25:21 R/W 0 PHY_ADDR PHY address.
|
||||
*/
|
||||
reg_val |= ((phy_addr & 0x1f) << 21);
|
||||
/*
|
||||
* b20:16 R/W 0 REG_ADDR PHY register address.
|
||||
*/
|
||||
reg_val |= ((reg_addr & 0x1f) << 16);
|
||||
|
||||
dbg("WJL %s: 1. phy_sel=0x%x, phy_addr=0x%x,"
|
||||
"reg_addr=0x%x, reg_val=0x%08x.\n",
|
||||
__func__, phy_sel, phy_addr,reg_addr, reg_val);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, 0x15004, reg_val);
|
||||
|
||||
udelay(10);
|
||||
|
||||
reg_val = qca8511_pp_reg_read(gmac_cfg, 0x15004);
|
||||
|
||||
dbg("WJL %s: 2. phy_sel=0x%x, phy_addr=0x%x,"
|
||||
"reg_addr=0x%x, reg_val=0x%08x.\n",
|
||||
__func__, phy_sel, phy_addr,reg_addr, reg_val);
|
||||
|
||||
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
static void qca8511_pp_phy_reg_write(ipq_gmac_board_cfg_t *gmac_cfg,
|
||||
uint32_t phy_sel, uint32_t phy_addr,
|
||||
uint32_t reg_addr, uint32_t reg_data)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
/* B31,MDIO_BUSY */
|
||||
reg_val = (1 << 31);
|
||||
|
||||
/*
|
||||
* b27, MDIO_CMD 0 = Write; 1 = Read;
|
||||
*/
|
||||
reg_val |= (0 << 27);
|
||||
/*
|
||||
* B29:28, PHY_SEL MDIO channel for MDIO master.
|
||||
* It is used to specify PHY group that to be operated.
|
||||
*/
|
||||
reg_val |= ((phy_sel & 0x3) << 28);
|
||||
/*
|
||||
* B25:21 R/W 0 PHY_ADDR PHY address
|
||||
*/
|
||||
reg_val |= ((phy_addr & 0x1f) << 21);
|
||||
/*
|
||||
* B20:16 R/W 0 REG_ADDR PHY register address
|
||||
*/
|
||||
reg_val |= ((reg_addr & 0x1f) << 16);
|
||||
|
||||
/*
|
||||
* b15:0 R/WW 0 MDIO_DATA When write, these bits are data written
|
||||
* to PHY register. When read, these bits are data read
|
||||
* out from PHY register.
|
||||
*/
|
||||
reg_val |= (reg_data & 0xffff);
|
||||
|
||||
dbg("WJL %s: 1. phy_sel=0x%x, phy_addr=0x%x,"
|
||||
"reg_addr=0x%x, reg_val=0x%08x.\n",
|
||||
__func__, phy_sel, phy_addr,reg_addr, reg_val);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, 0x15004, reg_val);
|
||||
|
||||
udelay(10);
|
||||
/*
|
||||
* if b31-MDIO_BUSY is reset to 0?
|
||||
*/
|
||||
reg_val = qca8511_pp_reg_read(gmac_cfg, 0x15004);
|
||||
|
||||
dbg("WJL %s: 2. phy_sel=0x%x, phy_addr=0x%x,"
|
||||
"reg_addr=0x%x, reg_val=0x%08x.\n",
|
||||
__func__, phy_sel, phy_addr,reg_addr, reg_val);
|
||||
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
static int do_qca8511_pp_reg_read(cmd_tbl_t *cmdtp, int flag,
|
||||
int argc, char * const argv[])
|
||||
{
|
||||
ulong addr, readval;
|
||||
int size;
|
||||
|
||||
if ((argc < 2) || (argc > 3))
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
/*
|
||||
* Check for size specification.
|
||||
*/
|
||||
if ((size = cmd_get_data_size(argv[0], 4)) < 1)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Address is specified since argc > 1
|
||||
*/
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
readval = qca8511_pp_reg_read(gmac_cfg_qca8511, addr);
|
||||
|
||||
printf("WJL %s: addr=0x%08lx, readval=0x%08lx.\n\n",
|
||||
__func__, addr, readval);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_qca8511_pp_reg_write( cmd_tbl_t *cmdtp, int flag,
|
||||
int argc, char * const argv[])
|
||||
{
|
||||
ulong addr, writeval;
|
||||
int size;
|
||||
|
||||
if ((argc < 3) || (argc > 4))
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
/*
|
||||
* Check for size specification.
|
||||
*/
|
||||
if ((size = cmd_get_data_size(argv[0], 4)) < 1)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Address is specified since argc > 1
|
||||
*/
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
/*
|
||||
* Get the value to write.
|
||||
*/
|
||||
writeval = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
if (argc == 4)
|
||||
simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
printf("WJL %s: addr=0x%08lx, writeval=0x%08lx.\n\n",
|
||||
__func__,addr, writeval);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg_qca8511, addr, writeval);
|
||||
dbg("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_qca8511_pp_phy_reg_read( cmd_tbl_t *cmdtp, int flag,
|
||||
int argc, char * const argv[])
|
||||
{
|
||||
ulong phy_sel, phy_addr, reg_addr, reg_val;
|
||||
int size;
|
||||
|
||||
if (argc != 4)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
/*
|
||||
* Check for size specification.
|
||||
*/
|
||||
if ((size = cmd_get_data_size(argv[0], 4)) < 1)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Address is specified since argc > 1
|
||||
*/
|
||||
phy_sel = simple_strtoul(argv[1], NULL, 16);
|
||||
phy_addr = simple_strtoul(argv[2], NULL, 16);
|
||||
reg_addr = simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
reg_val = qca8511_pp_phy_reg_read(gmac_cfg_qca8511, phy_sel,
|
||||
phy_addr, reg_addr);
|
||||
|
||||
printf("WJL %s: phy_sel=0x%lx, phy_addr=0x%lx, reg_addr=0x%lx,"
|
||||
"reg_val=0x%08lx, size=%d.\n\n",
|
||||
__func__, phy_sel, phy_addr, reg_addr, reg_val, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_qca8511_pp_phy_reg_write( cmd_tbl_t *cmdtp,
|
||||
int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong phy_sel, phy_addr, reg_addr, reg_data;
|
||||
int size;
|
||||
|
||||
if (argc != 5)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
/*
|
||||
* Check for size specification.
|
||||
*/
|
||||
if ((size = cmd_get_data_size(argv[0], 4)) < 1)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Address is specified since argc > 1
|
||||
*/
|
||||
phy_sel = simple_strtoul(argv[1], NULL, 16);
|
||||
phy_addr = simple_strtoul(argv[2], NULL, 16);
|
||||
reg_addr = simple_strtoul(argv[3], NULL, 16);
|
||||
reg_data = simple_strtoul(argv[4], NULL, 16);
|
||||
|
||||
printf("WJL %s: phy_sel=0x%lx, phy_addr=0x%lx, reg_addr=0x%lx,"
|
||||
"reg_data=0x%08lx, size=%d.\n",
|
||||
__func__, phy_sel, phy_addr, reg_addr, reg_data, size);
|
||||
|
||||
qca8511_pp_phy_reg_write(gmac_cfg_qca8511, phy_sel, phy_addr,
|
||||
reg_addr, reg_data);
|
||||
dbg("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FUNCTION DESCRIPTION: This function invokes RGMII,
|
||||
* SGMII switch init routines.
|
||||
* INPUT : ipq_gmac_board_cfg_t *
|
||||
* OUTPUT: NONE
|
||||
*
|
||||
**********************************************************************/
|
||||
int ipq_qca8511_init(ipq_gmac_board_cfg_t *gmac_cfg)
|
||||
{
|
||||
uint i;
|
||||
|
||||
gmac_cfg_qca8511 = gmac_cfg;
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_1_CTRL(QSGMII_1_CTRL0),
|
||||
QSGMII_1_CH0_DUPLEX_MODE |
|
||||
QSGMII_1_CH0_LINK |
|
||||
QSGMII_1_CH0_SPEED_MODE(FORCE_1000) |
|
||||
QSGMII_1_CH0_MR_AN_EN |
|
||||
QSGMII_1_RSVD16 |
|
||||
QSGMII_1_CH0_FORCED_MODE |
|
||||
QSGMII_1_CH_MODE_CTRL(QSGMII_MAC)|
|
||||
QSGMII_1_CH0_PAUSE_SG_TX_EN |
|
||||
QSGMII_1_CH0_ASYM_PAUSE |
|
||||
QSGMII_1_CH0_PAUSE |
|
||||
QSGMII_1_RSVD30 |
|
||||
QSGMII_1_RSVD31);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_2_CTRL(QSGMII_2_CTRL0),
|
||||
QSGMII_2_CH1_DUPLEX_MODE |
|
||||
QSGMII_2_CH1_LINK |
|
||||
QSGMII_2_CH1_SPEED_MODE(FORCE_1000) |
|
||||
QSGMII_2_CH1_MR_AN_EN |
|
||||
QSGMII_2_RSVD16 |
|
||||
QSGMII_2_CH1_FORCED_MODE |
|
||||
QSGMII_2_CH_RSVD(2) |
|
||||
QSGMII_2_CH1_PAUSE_SG_TX_EN |
|
||||
QSGMII_2_CH1_ASYM_PAUSE |
|
||||
QSGMII_2_CH1_PAUSE |
|
||||
QSGMII_2_RSVD30 |
|
||||
QSGMII_2_RSVD31);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_3_CTRL(QSGMII_3_CTRL0),
|
||||
QSGMII_3_CH2_DUPLEX_MODE |
|
||||
QSGMII_3_CH2_LINK |
|
||||
QSGMII_3_CH2_SPEED_MODE(FORCE_1000) |
|
||||
QSGMII_3_CH2_MR_AN_EN |
|
||||
QSGMII_3_RSVD16 |
|
||||
QSGMII_3_CH2_FORCED_MODE |
|
||||
QSGMII_2_CH_RSVD(2) |
|
||||
QSGMII_3_CH2_PAUSE_SG_TX_EN |
|
||||
QSGMII_3_CH2_ASYM_PAUSE |
|
||||
QSGMII_3_CH2_PAUSE |
|
||||
QSGMII_2_RSVD30 |
|
||||
QSGMII_2_RSVD31);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_4_CTRL(QSGMII_3_CTRL0),
|
||||
QSGMII_4_CH3_DUPLEX_MODE |
|
||||
QSGMII_4_CH3_LINK |
|
||||
QSGMII_4_CH3_SPEED_MODE(FORCE_1000) |
|
||||
QSGMII_4_CH3_MR_AN_EN |
|
||||
QSGMII_4_RSVD16 |
|
||||
QSGMII_4_CH3_FORCED_MODE |
|
||||
QSGMII_4_CH_RSVD(2) |
|
||||
QSGMII_4_CH3_PAUSE_SG_TX_EN |
|
||||
QSGMII_4_CH3_ASYM_PAUSE |
|
||||
QSGMII_4_CH3_PAUSE |
|
||||
QSGMII_4_RSVD30 |
|
||||
QSGMII_4_RSVD31);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_SGMII_CTRL0(SGMII_CTRL0_PORT8),
|
||||
SGMII_CTRL0_DUPLEX(1) |
|
||||
SGMII_CTRL0_SPEED_MODE(2) |
|
||||
SGMII_CTRL0_MR_AN_EN |
|
||||
SGMII_CTRL0_RSVD16 |
|
||||
SGMII_CTRL0_MODECTRL(2) |
|
||||
SGMII_CTRL0_PAUSE_SG_TX_EN |
|
||||
SGMII_CTRL0_ASYM_PAUSE_EN |
|
||||
SGMII_CTRL0_PAUSE_EN |
|
||||
SGMII_CTRL0_HALF_DUPLEX_EN |
|
||||
SGMII_CTRL0_FULL_DUPLEX_EN);
|
||||
|
||||
/*
|
||||
* Configure 8511 Ports
|
||||
*/
|
||||
|
||||
for (i = STATUS_PORT1; i < STATUS_PORT5; i++) {
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_PORT_STATUS_CFG(i),
|
||||
QCA8511_PORT_CFG_SPEED(FORCE_1000) |
|
||||
QCA8511_PORT_CFG_TX_MAC_EN |
|
||||
QCA8511_PORT_CFG_RX_MAC_EN |
|
||||
QCA8511_PORT_CFG_DUPLEX_MODE);
|
||||
}
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_GLOBAL_CTRL1,
|
||||
GLOBAL_CTL1_MAC25XG_4P3G_EN |
|
||||
GLOBAL_CTL1_MAC25XG_3P125G_EN |
|
||||
GLOBAL_CTL1_MAC26SG_1P25G_EN |
|
||||
GLOBAL_CTL1_MAC27SG_3P125G_EN |
|
||||
GLOBAL_CTL1_MAC28SG_3P125G_EN |
|
||||
GLOBAL_CTL1_MAC29SG_3P125G_EN |
|
||||
GLOBAL_CTL1_RSVD22 |
|
||||
GLOBAL_CTL1_SPI1_EN |
|
||||
GLOBAL_CTL1_TO_EXT_INT_EN |
|
||||
GLOBAL_CTL1_LED_CLK_EN_CFG |
|
||||
GLOBAL_CTL1_RSVD28 |
|
||||
GLOBAL_CTL1_RSVD29 |
|
||||
GLOBAL_CTL1_TWO_WIRE_LED_EN);
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_XAUI_SGMII_SERDES13_CTRL0,
|
||||
SGMII_CTRL0_RSVD(3) |
|
||||
SGMII_CTRL0_XAUI_EN_PLL(3) |
|
||||
SGMII_CTRL0_XAUI_DEEMP_CH0(1) |
|
||||
SGMII_CTRL0_XAUI_DEEMP_CH2(1) |
|
||||
SGMII_CTRL0_XAUI_DEEMP_CH3(1) |
|
||||
SGMII_CTRL0_XAUI_EN_SD(0xf));
|
||||
|
||||
qca8511_pp_reg_write(gmac_cfg, QCA8511_XAUI_SGMII_SERDES13_CTRL1,
|
||||
SGMII_CTRL1_RSVD4(3) |
|
||||
SGMII_CTRL1_XAUI_EN_RX(0xf) |
|
||||
SGMII_CTRL1_XAUI_EN_TX(0xf) |
|
||||
SGMII_CTRL1_XAUI_DEEMP_CH1(1) |
|
||||
SGMII_CTRL1_XAUI_REG(9) |
|
||||
SGMII_CTRL1_RSVD23(1) |
|
||||
SGMII_CTRL1_RSVD25(2));
|
||||
|
||||
printf("QCA8511 Init done....\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
mprd, 3, 1, do_qca8511_pp_reg_read,
|
||||
"qca8511 packet processor register display",
|
||||
"[.b, .w, .l] address [# of objects]"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
mprw, 4, 1, do_qca8511_pp_reg_write,
|
||||
"qca8511 packet processor register write (fill)",
|
||||
"[.b, .w, .l] address value [count]"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
mphyrd, 5, 1, do_qca8511_pp_phy_reg_read,
|
||||
"qca8511 packet processor PHY register display",
|
||||
"[.b, .w, .l] phy_sel phy_addr reg_addr [# of objects]"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
mphyrw, 6, 1, do_qca8511_pp_phy_reg_write,
|
||||
"qca8511 packet processor PHY register write (fill)",
|
||||
"[.b, .w, .l] phy_sel phy_addr reg_addr reg_data [count]"
|
||||
);
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _QCA8511_H
|
||||
#define _QCA8511_H
|
||||
|
||||
enum QSGMII_1_CTRL {
|
||||
QSGMII_1_CTRL0 = 0,
|
||||
QSGMII_1_CTRL1,
|
||||
QSGMII_1_CTRL2,
|
||||
};
|
||||
|
||||
enum QSGMII_SPEED_MODE {
|
||||
FORCE_10 = 0,
|
||||
FORCE_100,
|
||||
FORCE_1000,
|
||||
};
|
||||
|
||||
enum QSGMII_CH_MODE_CTRL {
|
||||
QSGMII_PHY = 1,
|
||||
QSGMII_MAC = 2,
|
||||
};
|
||||
|
||||
enum QSGMII_2_CTRL {
|
||||
QSGMII_2_CTRL0 = 0,
|
||||
QSGMII_2_CTRL1 = 1,
|
||||
QSGMII_2_CTRL2 = 2,
|
||||
};
|
||||
|
||||
enum QSGMII_3_CTRL {
|
||||
QSGMII_3_CTRL0 = 0,
|
||||
QSGMII_3_CTRL1 = 1,
|
||||
QSGMII_3_CTRL2 = 2,
|
||||
};
|
||||
|
||||
enum QCA8511_PORT {
|
||||
STATUS_PORT0 = 0,
|
||||
STATUS_PORT1,
|
||||
STATUS_PORT2,
|
||||
STATUS_PORT3,
|
||||
STATUS_PORT4,
|
||||
STATUS_PORT5,
|
||||
STATUS_PORT6,
|
||||
STATUS_PORT7,
|
||||
STATUS_PORT8,
|
||||
STATUS_PORT9,
|
||||
STATUS_PORT10,
|
||||
STATUS_PORT11,
|
||||
STATUS_PORT12,
|
||||
STATUS_PORT13,
|
||||
STATUS_PORT14,
|
||||
STATUS_PORT15,
|
||||
STATUS_PORT16,
|
||||
STATUS_PORT17,
|
||||
STATUS_PORT18,
|
||||
STATUS_PORT19,
|
||||
STATUS_PORT20,
|
||||
STATUS_PORT21,
|
||||
STATUS_PORT22,
|
||||
STATUS_PORT23,
|
||||
STATUS_PORT24,
|
||||
STATUS_PORT25,
|
||||
STATUS_PORT26,
|
||||
STATUS_PORT27,
|
||||
STATUS_PORT28,
|
||||
STATUS_PORT29,
|
||||
STATUS_PORT_MAX = 30,
|
||||
};
|
||||
|
||||
enum QCA8511_SGMII_CTRL_0 {
|
||||
SGMII_CTRL0_PORT0 = 0,
|
||||
SGMII_CTRL0_PORT1,
|
||||
SGMII_CTRL0_PORT2,
|
||||
SGMII_CTRL0_PORT3,
|
||||
SGMII_CTRL0_PORT4,
|
||||
SGMII_CTRL0_PORT5,
|
||||
SGMII_CTRL0_PORT6,
|
||||
SGMII_CTRL0_PORT7,
|
||||
SGMII_CTRL0_PORT8,
|
||||
SGMII_CTRL0_PORT9,
|
||||
SGMII_CTRL0_PORT10,
|
||||
SGMII_CTRL0_PORT11,
|
||||
SGMII_CTRL0_PORT_MAX = 12,
|
||||
};
|
||||
|
||||
#define QCA8511_QSGMII_CTRL1_BASE 0x13000
|
||||
#define QCA8511_SGMII_CTRL0_BASE 0x13100
|
||||
#define QCA8511_QSGMII_CTRL2_BASE 0x1300c
|
||||
#define QCA8511_QSGMII_CTRL3_BASE 0x13010
|
||||
#define QCA8511_QSGMII_CTRL4_BASE 0x13014
|
||||
#define QCA8511_PORT_BASE 0x100
|
||||
|
||||
#define QCA8511_QSGMII_1_CTRL(x) (QCA8511_QSGMII_CTRL1_BASE + (x * 0x50))
|
||||
#define QSGMII_1_CH0_DUPLEX_MODE (1 << 0)
|
||||
#define QSGMII_1_CH0_LINK (1 << 1)
|
||||
#define QSGMII_1_CH0_SPEED_MODE(x) (x << 2)
|
||||
#define QSGMII_1_CH0_MR_AN_EN (1 << 10)
|
||||
#define QSGMII_1_BERT_EN (1 << 14)
|
||||
#define QSGMII_1_RSVD16 (1 << 16)
|
||||
#define QSGMII_1_CH0_FORCED_MODE (1 << 21)
|
||||
#define QSGMII_1_CH_MODE_CTRL(x) (x << 22)
|
||||
#define QSGMII_1_CH0_PAUSE_SG_TX_EN (1 << 24)
|
||||
#define QSGMII_1_CH0_ASYM_PAUSE (1 << 25)
|
||||
#define QSGMII_1_CH0_PAUSE (1 << 26)
|
||||
#define QSGMII_1_RSVD30 (1 << 30)
|
||||
#define QSGMII_1_RSVD31 (1 << 31)
|
||||
|
||||
#define QCA8511_QSGMII_2_CTRL(x) (QCA8511_QSGMII_CTRL2_BASE + (x * 0x50))
|
||||
#define QSGMII_2_CH1_DUPLEX_MODE (1 << 0)
|
||||
#define QSGMII_2_CH1_LINK (1 << 1)
|
||||
#define QSGMII_2_CH1_SPEED_MODE(x) (x << 2)
|
||||
#define QSGMII_2_CH1_MR_AN_EN (1 << 10)
|
||||
#define QSGMII_2_RSVD16 (1 << 16)
|
||||
#define QSGMII_2_CH1_FORCED_MODE (1 << 21)
|
||||
#define QSGMII_2_CH_RSVD(x) (x << 22)
|
||||
#define QSGMII_2_CH1_PAUSE_SG_TX_EN (1 << 24)
|
||||
#define QSGMII_2_CH1_ASYM_PAUSE (1 << 25)
|
||||
#define QSGMII_2_CH1_PAUSE (1 << 26)
|
||||
#define QSGMII_2_RSVD30 (1 << 30)
|
||||
#define QSGMII_2_RSVD31 (1 << 31)
|
||||
|
||||
#define QCA8511_QSGMII_3_CTRL(x) (QCA8511_QSGMII_CTRL3_BASE + (x * 0x50))
|
||||
#define QSGMII_3_CH2_DUPLEX_MODE (1 << 0)
|
||||
#define QSGMII_3_CH2_LINK (1 << 1)
|
||||
#define QSGMII_3_CH2_SPEED_MODE(x) (x << 2)
|
||||
#define QSGMII_3_CH2_MR_AN_EN (1 << 10)
|
||||
#define QSGMII_3_RSVD16 (1 << 16)
|
||||
#define QSGMII_3_CH2_FORCED_MODE (1 << 21)
|
||||
#define QSGMII_3_CH_RSVD(x) (x << 22)
|
||||
#define QSGMII_3_CH2_PAUSE_SG_TX_EN (1 << 24)
|
||||
#define QSGMII_3_CH2_ASYM_PAUSE (1 << 25)
|
||||
#define QSGMII_3_CH2_PAUSE (1 << 26)
|
||||
#define QSGMII_3_RSVD30 (1 << 30)
|
||||
#define QSGMII_3_RSVD31 (1 << 31)
|
||||
|
||||
#define QCA8511_QSGMII_4_CTRL(x) (QCA8511_QSGMII_CTRL4_BASE + (x * 0x50))
|
||||
#define QSGMII_4_CH3_DUPLEX_MODE (1 << 0)
|
||||
#define QSGMII_4_CH3_LINK (1 << 1)
|
||||
#define QSGMII_4_CH3_SPEED_MODE(x) (x << 2)
|
||||
#define QSGMII_4_CH3_MR_AN_EN (1 << 10)
|
||||
#define QSGMII_4_RSVD16 (1 << 16)
|
||||
#define QSGMII_4_CH3_FORCED_MODE (1 << 21)
|
||||
#define QSGMII_4_CH_RSVD(x) (x << 22)
|
||||
#define QSGMII_4_CH3_PAUSE_SG_TX_EN (1 << 24)
|
||||
#define QSGMII_4_CH3_ASYM_PAUSE (1 << 25)
|
||||
#define QSGMII_4_CH3_PAUSE (1 << 26)
|
||||
#define QSGMII_4_RSVD30 (1 << 30)
|
||||
#define QSGMII_4_RSVD31 (1 << 31)
|
||||
|
||||
#define QCA8511_PORT_STATUS_CFG(x) (QCA8511_PORT_BASE + (x * 0x100))
|
||||
#define QCA8511_PORT_CFG_SPEED(x) (x << 0)
|
||||
#define QCA8511_PORT_CFG_TX_MAC_EN (1 << 2)
|
||||
#define QCA8511_PORT_CFG_RX_MAC_EN (1 << 3)
|
||||
#define QCA8511_PORT_CFG_DUPLEX_MODE (1 << 6)
|
||||
|
||||
#define QCA8511_GLOBAL_CTRL1 0x8
|
||||
#define GLOBAL_CTL1_MAC25XG_4P3G_EN (1 << 10)
|
||||
#define GLOBAL_CTL1_MAC25XG_3P125G_EN (1 << 11)
|
||||
#define GLOBAL_CTL1_MAC26SG_1P25G_EN (1 << 15)
|
||||
#define GLOBAL_CTL1_MAC27SG_3P125G_EN (1 << 16)
|
||||
#define GLOBAL_CTL1_MAC28SG_3P125G_EN (1 << 18)
|
||||
#define GLOBAL_CTL1_MAC29SG_3P125G_EN (1 << 20)
|
||||
#define GLOBAL_CTL1_RSVD22 (1 << 22)
|
||||
#define GLOBAL_CTL1_SPI1_EN (1 << 23)
|
||||
#define GLOBAL_CTL1_TO_EXT_INT_EN (1 << 25)
|
||||
#define GLOBAL_CTL1_LED_CLK_EN_CFG (1 << 27)
|
||||
#define GLOBAL_CTL1_RSVD28 (1 << 28)
|
||||
#define GLOBAL_CTL1_RSVD29 (1 << 29)
|
||||
#define GLOBAL_CTL1_TWO_WIRE_LED_EN (1 << 30)
|
||||
|
||||
#define QCA8511_XAUI_SGMII_SERDES13_CTRL0 0x1341c
|
||||
#define SGMII_CTRL0_RSVD(x) (x << 1)
|
||||
#define SGMII_CTRL0_XAUI_EN_PLL(x) (x << 3)
|
||||
#define SGMII_CTRL0_XAUI_DEEMP_CH0(x) (x << 5)
|
||||
#define SGMII_CTRL0_RSVD7(x) (x << 7)
|
||||
#define SGMII_CTRL0_XAUI_DEEMP_CH2(x) (x << 9)
|
||||
#define SGMII_CTRL0_RSVD11(x) (x << 11)
|
||||
#define SGMII_CTRL0_XAUI_TH_LOS_CH1(x) (x << 13)
|
||||
#define SGMII_CTRL0_XAUI_TH_LOS_CH3(x) (x << 15)
|
||||
#define SGMII_CTRL0_XAUI_DEEMP_CH3(x) (x << 17)
|
||||
#define SGMII_CTRL0_RSVD19(x) (x << 19)
|
||||
#define SGMII_CTRL0_XAUI_EN_SD(x) (x << 21)
|
||||
#define SGMII_CTRL0_XAUI_HALFTX(x) (x << 25)
|
||||
#define SGMII_CTRL0_RSVD29(x) (x << 29)
|
||||
|
||||
#define QCA8511_XAUI_SGMII_SERDES13_CTRL1 0x13420
|
||||
#define SGMII_CTRL1_RSVD4(x) (x << 4)
|
||||
#define SGMII_CTRL1_XAUI_EN_RX(x) (x << 6)
|
||||
#define SGMII_CTRL1_XAUI_EN_TX(x) (x << 10)
|
||||
#define SGMII_CTRL1_XAUI_TH_LOS_CH2(x) (x << 14)
|
||||
#define SGMII_CTRL1_XAUI_DEEMP_CH1(x) (x << 16)
|
||||
#define SGMII_CTRL1_XAUI_REG(x) (x << 19)
|
||||
#define SGMII_CTRL1_RSVD23(x) (x << 23)
|
||||
#define SGMII_CTRL1_RSVD25(x) (x << 25)
|
||||
|
||||
#define QCA8511_SGMII_CTRL0(x) (QCA8511_SGMII_CTRL0_BASE + (x * 0x20))
|
||||
#define SGMII_CTRL0_DUPLEX(x) (x << 0)
|
||||
#define SGMII_CTRL0_SPEED_MODE(x) (x << 2)
|
||||
#define SGMII_CTRL0_MR_AN_EN (1 << 10)
|
||||
#define SGMII_CTRL0_RSVD16 (1 << 16)
|
||||
#define SGMII_CTRL0_MODECTRL(x) (x << 22)
|
||||
#define SGMII_CTRL0_PAUSE_SG_TX_EN (1 << 24)
|
||||
#define SGMII_CTRL0_ASYM_PAUSE_EN (1 << 25)
|
||||
#define SGMII_CTRL0_PAUSE_EN (1 << 26)
|
||||
#define SGMII_CTRL0_HALF_DUPLEX_EN (1 << 30)
|
||||
#define SGMII_CTRL0_FULL_DUPLEX_EN (1 << 31)
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
# Copyright (c) 2012 The Linux Foundation. All rights reserved.
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := ipq806x_cdp.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _IPQ806X_CDP_H_
|
||||
#define _IPQ806X_CDP_H_
|
||||
#define MAX_CONF_NAME 5
|
||||
|
||||
#include <configs/ipq806x_cdp.h>
|
||||
#include <phy.h>
|
||||
#include <asm/arch-ipq806x/clock.h>
|
||||
#include <asm/u-boot.h>
|
||||
|
||||
unsigned int smem_get_board_machtype(void);
|
||||
|
||||
typedef struct {
|
||||
int gpio;
|
||||
unsigned int func;
|
||||
unsigned int out;
|
||||
unsigned int pull;
|
||||
unsigned int drvstr;
|
||||
unsigned int oe;
|
||||
} gpio_func_data_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned int m_value;
|
||||
unsigned int n_value;
|
||||
unsigned int d_value;
|
||||
} clk_mnd_t;
|
||||
|
||||
/* SPI Mode */
|
||||
|
||||
typedef enum {
|
||||
NOR_SPI_MODE_0,
|
||||
NOR_SPI_MODE_1,
|
||||
NOR_SPI_MODE_2,
|
||||
NOR_SPI_MODE_3,
|
||||
} spi_mode;
|
||||
|
||||
/* SPI GSBI Bus number */
|
||||
|
||||
typedef enum {
|
||||
GSBI_BUS_5 = 0,
|
||||
GSBI_BUS_6,
|
||||
GSBI_BUS_7,
|
||||
} spi_gsbi_bus_num;
|
||||
|
||||
/* SPI Chip selects */
|
||||
|
||||
typedef enum {
|
||||
SPI_CS_0 ,
|
||||
SPI_CS_1,
|
||||
SPI_CS_2,
|
||||
SPI_CS_3,
|
||||
} spi_cs;
|
||||
|
||||
/* Flash Types */
|
||||
|
||||
typedef enum {
|
||||
ONLY_NAND,
|
||||
ONLY_NOR,
|
||||
NAND_NOR,
|
||||
NOR_MMC,
|
||||
} flash_desc;
|
||||
|
||||
#define NO_OF_DBG_UART_GPIOS 2
|
||||
#define NO_OF_I2C_GPIOS 2
|
||||
|
||||
#define SPI_NOR_FLASH_VENDOR_MICRON 0x1
|
||||
#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2
|
||||
|
||||
/* SPI parameters */
|
||||
|
||||
typedef struct {
|
||||
spi_mode mode;
|
||||
spi_gsbi_bus_num bus_number;
|
||||
spi_cs chip_select;
|
||||
int vendor;
|
||||
} spinorflash_params_t;
|
||||
|
||||
typedef struct {
|
||||
uint count;
|
||||
u8 addr[7];
|
||||
} ipq_gmac_phy_addr_t;
|
||||
|
||||
typedef struct {
|
||||
uint base;
|
||||
int unit;
|
||||
uint is_macsec;
|
||||
uint mac_pwr0;
|
||||
uint mac_pwr1;
|
||||
uint mac_conn_to_phy;
|
||||
phy_interface_t phy;
|
||||
ipq_gmac_phy_addr_t phy_addr;
|
||||
const char phy_name[MDIO_NAME_LEN];
|
||||
} ipq_gmac_board_cfg_t;
|
||||
|
||||
typedef struct {
|
||||
uint base;
|
||||
uint gsbi_base;
|
||||
uint uart_dm_base;
|
||||
clk_mnd_t uart_mnd_value;
|
||||
gpio_func_data_t *dbg_uart_gpio;
|
||||
} uart_cfg_t;
|
||||
|
||||
#define IPQ_GMAC_NMACS 4
|
||||
#define IPQ_UART_MAX 2
|
||||
|
||||
#ifdef CONFIG_IPQ806X_PCI
|
||||
#define PCI_MAX_DEVICES 3
|
||||
|
||||
typedef struct {
|
||||
gpio_func_data_t *pci_rst_gpio;
|
||||
uint32_t parf;
|
||||
uint32_t elbi;
|
||||
uint32_t pcie20;
|
||||
uint32_t axi_bar_start;
|
||||
uint32_t axi_bar_size;
|
||||
uint32_t pcie_rst;
|
||||
clk_offset_t *pci_clks;
|
||||
uint32_t axi_conf;
|
||||
int linkup;
|
||||
} pcie_params_t;
|
||||
|
||||
void board_pci_init(void);
|
||||
#endif /* CONFIG_IPQ806X_PCI */
|
||||
|
||||
/* Board specific parameters */
|
||||
typedef struct {
|
||||
unsigned int machid;
|
||||
unsigned int ddr_size;
|
||||
unsigned int clk_dummy;
|
||||
clk_mnd_t usb_core_mnd_value;
|
||||
clk_mnd_t usb_utmi_mnd_value;
|
||||
unsigned int gmac_gpio_count;
|
||||
gpio_func_data_t *gmac_gpio;
|
||||
ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS];
|
||||
uart_cfg_t uart_cfg[IPQ_UART_MAX];
|
||||
uart_cfg_t *console_uart_cfg;
|
||||
gpio_func_data_t *switch_gpio;
|
||||
gpio_func_data_t *reset_switch_gpio;
|
||||
gpio_func_data_t *reset_ak01_gmac_gpio;
|
||||
gpio_func_data_t *ar8033_gpio;
|
||||
flash_desc flashdesc;
|
||||
spinorflash_params_t flash_param;
|
||||
#ifdef CONFIG_IPQ806X_I2C
|
||||
unsigned int i2c_gsbi;
|
||||
unsigned int i2c_gsbi_base;
|
||||
clk_mnd_t i2c_mnd_value;
|
||||
gpio_func_data_t i2c_gpio[NO_OF_I2C_GPIOS];
|
||||
#endif
|
||||
#ifdef CONFIG_IPQ806X_PCI
|
||||
pcie_params_t pcie_cfg[PCI_MAX_DEVICES];
|
||||
unsigned int wifi_pcie_power_gpio_cnt;
|
||||
gpio_func_data_t *wifi_pcie_power_gpio[PCI_MAX_DEVICES];
|
||||
#endif
|
||||
#ifdef CONFIG_IPQ_MMC
|
||||
gpio_func_data_t *emmc_gpio;
|
||||
unsigned int emmc_gpio_count;
|
||||
#endif
|
||||
const char *dtb_config_name[MAX_CONF_NAME];
|
||||
} __attribute__ ((__packed__)) board_ipq806x_params_t;
|
||||
|
||||
extern board_ipq806x_params_t *gboard_param;
|
||||
|
||||
static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
|
||||
{
|
||||
/*
|
||||
* 'cfg' is valid if and only if
|
||||
* unit number is non-negative and less than IPQ_GMAC_NMACS.
|
||||
* 'cfg' pointer lies within the array range of
|
||||
* board_ipq806x_params_t->gmac_cfg[]
|
||||
*/
|
||||
return ((cfg >= &gboard_param->gmac_cfg[0]) &&
|
||||
(cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
|
||||
(cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
|
||||
}
|
||||
|
||||
unsigned int get_board_index(unsigned int machid);
|
||||
void ipq_configure_gpio(gpio_func_data_t *gpio, uint count);
|
||||
|
||||
#ifdef CONFIG_IPQ_MMC
|
||||
|
||||
#define MSM_SDC1_BASE 0x12400000
|
||||
|
||||
typedef struct {
|
||||
uint base;
|
||||
uint clk_mode;
|
||||
struct mmc *mmc;
|
||||
int dev_num;
|
||||
} ipq_mmc;
|
||||
|
||||
int mmc_initialize(bd_t *bis);
|
||||
extern ipq_mmc mmc_host;
|
||||
int ipq_mmc_init(bd_t *, ipq_mmc *);
|
||||
void board_mmc_deinit(void);
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue