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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport

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Ycarus (Yannick Chabanois) 2023-04-22 08:07:24 +02:00
parent e910436a7a
commit 46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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48
common/package/utils/sysupgrade-helper/src/board/samsung/goni/Makefile Normal file
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#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := goni.o onenand.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
$(call cmd_link_o_target, $(SOBJS) $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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common/package/utils/sysupgrade-helper/src/board/samsung/goni/config.mk Normal file
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#
# Copyright (C) 2010 Samsung Electronics
# Kyungmin Park <kyungmin.park@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# On S5PC100 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x38000000 to 0x40000000 (128MiB)
#
# On S5PC110 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x50000000 (256MiB)
#
CONFIG_SYS_TEXT_BASE = 0x34800000

148
common/package/utils/sysupgrade-helper/src/board/samsung/goni/goni.c Normal file
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/*
* Copyright (C) 2008-2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <max8998_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
static struct s5pc110_gpio *s5pc110_gpio;
int board_init(void)
{
/* Set Initial global variables */
s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
#if defined(CONFIG_PMIC)
pmic_init();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
PHYS_SDRAM_3_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tGoni\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int i;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
/*
* MMC0 GPIO
* GPG0[0] SD_0_CLK
* GPG0[1] SD_0_CMD
* GPG0[2] SD_0_CDn -> Not used
* GPG0[3:6] SD_0_DATA[0:3]
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPG0[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
/* GPG0[0:6] pull disable */
s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
}
return s5p_mmc_init(0, 4);
}
#endif
#ifdef CONFIG_USB_GADGET
static int s5pc1xx_phy_control(int on)
{
int ret;
static int status;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on && !status) {
ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_ON);
ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_ON);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -1;
}
status = 1;
} else if (!on && status) {
ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_OFF);
ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_OFF);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -1;
}
status = 0;
}
udelay(10000);
return 0;
}
struct s3c_plat_otg_data s5pc110_otg_data = {
.phy_control = s5pc1xx_phy_control,
.regs_phy = S5PC110_PHY_BASE,
.regs_otg = S5PC110_OTG_BASE,
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
#endif

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common/package/utils/sysupgrade-helper/src/board/samsung/goni/lowlevel_init.S Normal file
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/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/power.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has S5PC100 GPIO base, 0xE0300000
* r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
* r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
*/
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r11, lr
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC100_GPIO_BASE
ldr r8, =S5PC100_GPIO_BASE
/* Read CPU ID */
ldr r2, =S5PC110_PRO_ID
ldr r0, [r2]
mov r1, #0x00010000
and r0, r0, r1
cmp r0, r5
beq 100f
ldr r8, =S5PC110_GPIO_BASE
100:
/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
cmp r7, r8
beq skip_check_didle @ Support C110 only
ldr r0, =S5PC110_RST_STAT
ldr r1, [r0]
and r1, r1, #0x000D0000
cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
beq didle_wakeup
cmp r7, r8
skip_check_didle:
addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
bic r1, r1, #(0xf << 4) @ 1 * 4-bit
orr r1, r1, #(0x1 << 4)
str r1, [r0, #0x0] @ GPIO_CON_OFFSET
ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
#ifdef CONFIG_ONENAND_IPL
orr r1, r1, #(1 << 1) @ 1 * 1-bit
#else
bic r1, r1, #(1 << 1)
#endif
str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
/* Don't setup at s5pc100 */
beq 100f
/*
* Initialize Async Register Setting for EVT1
* Because we are setting EVT1 as the default value of EVT0,
* setting EVT0 as well does not make things worse.
* Thus, for the simplicity, we set for EVT0, too
*
* The "Async Registers" are:
* 0xE0F0_0000
* 0xE1F0_0000
* 0xF180_0000
* 0xF190_0000
* 0xF1A0_0000
* 0xF1B0_0000
* 0xF1C0_0000
* 0xF1D0_0000
* 0xF1E0_0000
* 0xF1F0_0000
* 0xFAF0_0000
*/
ldr r0, =0xe0f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xe1f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1800000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1900000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1a00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1b00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1c00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1d00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1e00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xf1f00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
ldr r0, =0xfaf00000
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0]
/*
* Diable ABB block to reduce sleep current at low temperature
* Note that it's hidden register setup don't modify it
*/
ldr r0, =0xE010C300
ldr r1, =0x00800000
str r1, [r0]
100:
/* IO retension release */
ldreq r0, =S5PC100_OTHERS @ 0xE0108200
ldrne r0, =S5PC110_OTHERS @ 0xE010E000
ldr r1, [r0]
ldreq r2, =(1 << 31) @ IO_RET_REL
ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
orr r1, r1, r2
/* Do not release retention here for S5PC110 */
streq r1, [r0]
#ifndef CONFIG_ONENAND_IPL
/* Disable Watchdog */
ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
str r5, [r0]
/* setting SRAM */
ldreq r0, =S5PC100_SROMC_BASE
ldrne r0, =S5PC110_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
#endif
/* S5PC100 has 3 groups of interrupt sources */
ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
add r1, r0, #0x00100000
add r2, r0, #0x00200000
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
str r3, [r0, #0x14] @ INTENCLEAR
str r3, [r1, #0x14] @ INTENCLEAR
str r3, [r2, #0x14] @ INTENCLEAR
#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @ INTSELECT
str r5, [r1, #0xc] @ INTSELECT
str r5, [r2, #0xc] @ INTSELECT
/* Pending Interrupt Clear */
str r5, [r0, #0xf00] @ INTADDRESS
str r5, [r1, #0xf00] @ INTADDRESS
str r5, [r2, #0xf00] @ INTADDRESS
#endif
#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
bl internal_ram_init
#endif
#ifdef CONFIG_ONENAND_IPL
/* init system clock */
bl system_clock_init
/* OneNAND Sync Read Support at S5PC110 only
* RM[15] : Sync Read
* BRWL[14:12] : 7 CLK
* BL[11:9] : Continuous
* VHF[3] : Very High Frequency Enable (Over 83MHz)
* HF[2] : High Frequency Enable (Over 66MHz)
* WM[1] : Sync Write
*/
cmp r7, r8
ldrne r1, =0xE006
ldrne r0, =0xB001E442
strneh r1, [r0]
/*
* GCE[26] : Gated Clock Enable
* RPE[17] : Enables Read Prefetch
*/
ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
ldrne r0, =0xB0600000
strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
ldrne r1, =0x1212
strne r1, [r0, #0x108]
/* Board detection to set proper memory configuration */
cmp r7, r8
moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
movne r9, #2 /* r9 has 2Gib default at s5pc110 */
ldr r2, =0xE0200200
ldr r4, [r2, #0x48]
bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
str r1, [r2, #0x48]
/* For write completion */
nop
nop
ldr r3, [r2, #0x44]
and r1, r3, #(0x7 << 2)
mov r1, r1, lsr #2
cmp r1, #0x5
moveq r9, #3
cmp r1, #0x6
moveq r9, #1
cmp r1, #0x7
moveq r9, #2
and r0, r3, #(0x1 << 1)
mov r0, r0, lsr #1
orr r1, r1, r0, lsl #3
cmp r1, #0x8
moveq r9, #3
and r1, r3, #(0x7 << 2)
mov r1, r1, lsr #2
and r0, r3, #(0x1 << 7)
mov r0, r0, lsr #7
orr r1, r1, r0, lsl #3
cmp r1, #0x9
moveq r9, #3
str r4, [r2, #0x48] /* Restore PULLUP configuration */
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
ldreq r0, =S5PC100_RST_STAT
ldrne r0, =S5PC110_RST_STAT
ldr r1, [r0]
biceq r1, r1, #0xfffffff7
moveq r2, #(1 << 3)
bicne r1, r1, #0xfffeffff
movne r2, #(1 << 16)
cmp r1, r2
bne 1f
wakeup:
/* turn off L2 cache */
bl l2_cache_disable
cmp r7, r8
ldreq r0, =0xC100
ldrne r0, =0xC110
/* invalidate L2 cache also */
bl invalidate_dcache
/* turn on L2 cache */
bl l2_cache_enable
cmp r7, r8
/* Load return address and jump to kernel */
ldreq r0, =S5PC100_INFORM0
ldrne r0, =S5PC110_INFORM0
/* r1 = physical address of s5pc1xx_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel (sleep-s5pc1xx.S) */
mov pc, r1
nop
nop
#else
cmp r7, r8
/* Clear wakeup status register */
ldreq r0, =S5PC100_WAKEUP_STAT
ldrne r0, =S5PC110_WAKEUP_STAT
ldr r1, [r0]
str r1, [r0]
/* IO retension release */
ldreq r0, =S5PC100_OTHERS @ 0xE0108200
ldrne r0, =S5PC110_OTHERS @ 0xE010E000
ldr r1, [r0]
ldreq r2, =(1 << 31) @ IO_RET_REL
ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
orr r1, r1, r2
str r1, [r0]
#endif
b 1f
didle_wakeup:
/* Wait when APLL is locked */
ldr r0, =0xE0100100 @ S5PC110_APLL_CON
lockloop:
ldr r1, [r0]
and r1, r1, #(1 << 29)
cmp r1, #(1 << 29)
bne lockloop
ldr r0, =S5PC110_INFORM0
ldr r1, [r0]
mov pc, r1
nop
nop
nop
nop
nop
1:
mov lr, r11
mov pc, lr
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Check S5PC100 */
cmp r7, r8
bne 110f
100:
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
/* S5P_APLL_CON */
ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
str r1, [r0, #0x100]
/* S5P_MPLL_CON */
ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
str r1, [r0, #0x104]
/* S5P_EPLL_CON */
ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
str r1, [r0, #0x108]
/* S5P_HPLL_CON */
ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
str r1, [r0, #0x10C]
ldr r1, [r0, #0x300]
ldr r2, =0x00003fff
bic r1, r1, r2
ldr r2, =0x00011301
orr r1, r1, r2
str r1, [r0, #0x300]
ldr r1, [r0, #0x304]
ldr r2, =0x00011110
orr r1, r1, r2
str r1, [r0, #0x304]
ldr r1, =0x00000001
str r1, [r0, #0x308]
/* Set Source Clock */
ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
b 200f
110:
ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
/* Set OSC_FREQ value */
ldr r1, =0xf
str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
/* Set MTC_STABLE value */
ldr r1, =0xffffffff
str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
/* Set CLAMP_STABLE value */
ldr r1, =0x3ff03ff
str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
str r1, [r0, #0x300]
ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
str r1, [r0, #0x310]
/* Set Lock Time */
ldr r1, =0x2cf @ Locktime : 30us
str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
/* S5PC110_APLL_CON */
ldr r1, =0x80C80601 @ 800MHz
str r1, [r0, #0x100]
/* S5PC110_MPLL_CON */
ldr r1, =0x829B0C01 @ 667MHz
str r1, [r0, #0x108]
/* S5PC110_EPLL_CON */
ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
str r1, [r0, #0x110]
/* S5PC110_VPLL_CON */
ldr r1, =0x806C0603 @ 54MHz
str r1, [r0, #0x120]
/* Set Source Clock */
ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
/* OneDRAM(DMC0) clock setting */
ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
/* XCLKOUT = XUSBXTI 24MHz */
add r2, r0, #0xE000 @ S5PC110_OTHERS
ldr r1, [r2]
orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
str r1, [r2]
/* CLK_IP0 */
ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
str r1, [r0, #0x460] @ S5PC110_CLK_IP0
/* CLK_IP1 */
ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
@ NANDXL[24]
str r1, [r0, #0x464] @ S5PC110_CLK_IP1
/* CLK_IP2 */
ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
@ HOSTIF[10] HSMMC0[16]
@ HSMMC2[18] VIC[27:24]
str r1, [r0, #0x468] @ S5PC110_CLK_IP2
/* CLK_IP3 */
ldr r1, =0x8eff038c @ I2C[8:6]
@ SYSTIMER[16] UART0[17]
@ UART1[18] UART2[19]
@ UART3[20] WDT[22]
@ PWM[23] GPIO[26] SYSCON[27]
str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
/* CLK_IP4 */
ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
str r1, [r0, #0x470] @ S5PC110_CLK_IP3
200:
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
bne 1b
mov pc, lr
#ifndef CONFIG_ONENAND_IPL
internal_ram_init:
ldreq r0, =0xE3800000
ldrne r0, =0xF1500000
ldr r1, =0x0
str r1, [r0]
mov pc, lr
#endif
#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
uart_asm_init:
/* set GPIO to enable UART0-UART4 */
mov r0, r8
ldr r1, =0x22222222
str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
ldr r1, =0x00002222
str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
/* Check S5PC100 */
cmp r7, r8
bne 110f
/* UART_SEL GPK0[5] at S5PC100 */
add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
orr r1, r1, #(0x1 << 20) @ Output
str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
orr r1, r1, #(0x2 << 10) @ Pull-up enabled
str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
b 200f
110:
/*
* Note that the following address
* 0xE020'0360 is reserved address at S5PC100
*/
/* UART_SEL MP0_5[7] at S5PC110 */
add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28) @ Output
str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
orr r1, r1, #(0x2 << 14) @ Pull-up enabled
str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
200:
mov pc, lr
#endif

265
common/package/utils/sysupgrade-helper/src/board/samsung/goni/mem_setup.S Normal file
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/*
* Copyright (C) 2009 Samsung Electrnoics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
cmp r7, r8
ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
/* DLL parameter setting */
ldr r1, =0x50101000
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
ldr r1, =0x000000f4
str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
ldreq r1, =0x0
streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
/* DLL on */
ldr r1, =0x50101002
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* DLL start */
ldr r1, =0x50101003
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
mov r2, #0x4000
wait: subs r2, r2, #0x1
cmp r2, #0x0
bne wait
cmp r7, r8
/* Force value locking for DLL off */
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* DLL off */
ldr r1, =0x50101009
str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
/* auto refresh off */
ldr r1, =0xff001010 | (1 << 7)
ldr r2, =0xff001010 | (1 << 7)
str r1, [r0, #0x000] @ CONCONTROL_OFFSET
strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
/*
* Burst Length 4, 2 chips, 32-bit, LPDDR
* OFF: dynamic self refresh, force precharge, dynamic power down off
*/
ldr r1, =0x00212100
ldr r2, =0x00212100
str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
/*
* Note:
* If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
* So finally Bank1 OneDRAM should address start at at 0x3000'0000
*/
/*
* DMC0: CS0 : S5PC100/S5PC110
* 0x30 -> 0x30000000
* 0xf8 -> 0x37FFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
ldr r3, =0x30f80222
ldr r4, =0x40f00222
swap_memory:
str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
str r4, [r0, #0x00C] @ dummy write
/*
* DMC1: CS0 : S5PC110
* 0x40 -> 0x40000000
* 0xf8 -> 0x47FFFFFF (1Gib)
* 0x40 -> 0x40000000
* 0xf0 -> 0x4FFFFFFF (2Gib)
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits - Col (1Gib)
* [11:8 ] 3: 10 bits - Col (2Gib)
* [ 7:4 ] 2: 14 bits - Row
* [ 3:0 ] 2: 4 banks
*/
/* Default : 2GiB */
ldr r4, =0x40f01322 @ 2Gib: MCP B
ldr r5, =0x50f81312 @ dummy: MCP D
cmp r9, #1
ldreq r4, =0x40f81222 @ 1Gib: MCP A
cmp r9, #3
ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
cmp r9, #4
ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
cmp r7, r8
strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
/*
* DMC0: CS1: S5PC100
* 0x38 -> 0x38000000
* 0xf8 -> 0x3fFFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
eoreq r3, r3, #0x08000000
streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
ldr r1, =0x20000000
str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
/*
* S5PC100:
* DMC: CS0: 166MHz
* CS1: 166MHz
* S5PC110:
* DMC0: CS0: 166MHz
* DMC1: CS0: 200MHz
*
* 7.8us * 200MHz %LE %LONG1560(0x618)
* 7.8us * 166MHz %LE %LONG1294(0x50E)
* 7.8us * 133MHz %LE %LONG1038(0x40E),
* 7.8us * 100MHz %LE %LONG780(0x30C),
*/
ldr r1, =0x0000050E
str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
ldrne r1, =0x00000618
strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
ldr r1, =0x14233287
str r1, [r0, #0x034] @ TIMINGROW_OFFSET
ldrne r1, =0x182332c8
strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
ldr r1, =0x12130005
str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
ldrne r1, =0x13130005
strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
ldr r1, =0x0E140222
str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
ldrne r1, =0x0E180222
strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
/* chip0 Deselect */
ldr r1, =0x07000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 PALL */
ldr r1, =0x01000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 REFA */
ldr r1, =0x05000000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 REFA */
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 MRS */
ldr r1, =0x00000032
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip0 EMRS */
ldr r1, =0x00020020
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 Deselect */
ldr r1, =0x07100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 PALL */
ldr r1, =0x01100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 REFA */
ldr r1, =0x05100000
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 REFA */
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 MRS */
ldr r1, =0x00100032
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* chip1 EMRS */
ldr r1, =0x00120020
str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
/* auto refresh on */
ldr r1, =0xFF002030 | (1 << 7)
str r1, [r0, #0x000] @ CONCONTROL_OFFSET
strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
/* PwrdnConfig */
ldr r1, =0x00100002
str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
ldr r1, =0x00212113
str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
/* Skip when S5PC110 */
bne 1f
/* Check OneDRAM access area at s5pc100 */
ldreq r3, =0x38f80222
ldreq r1, =0x37ffff00
str r3, [r1]
ldr r2, [r1]
cmp r2, r3
beq swap_memory
1:
mov pc, lr
.ltorg

37
common/package/utils/sysupgrade-helper/src/board/samsung/goni/onenand.c Normal file
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/*
* Copyright (C) 2008-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/samsung_onenand.h>
#include <onenand_uboot.h>
void onenand_board_init(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
this->base = (void *)CONFIG_SYS_ONENAND_BASE;
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
this->chip_probe = s5pc110_chip_probe;
}

64
common/package/utils/sysupgrade-helper/src/board/samsung/origen/Makefile Normal file
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#
# Copyright (C) 2011 Samsung Electronics
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
SOBJS := mem_setup.o
SOBJS += lowlevel_init.o
ifndef CONFIG_SPL_BUILD
COBJS += origen.o
endif
ifdef CONFIG_SPL_BUILD
COBJS += mmc_boot.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL +=$(obj).depend $(LIB)
ifdef CONFIG_SPL_BUILD
ALL += $(OBJTREE)/tools/mk$(BOARD)spl
endif
all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
ifdef CONFIG_SPL_BUILD
$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
endif
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

362
common/package/utils/sysupgrade-helper/src/board/samsung/origen/lowlevel_init.S Normal file
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/*
* Lowlevel setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include "origen_setup.h"
/*
* Register usages:
*
* r5 has zero always
* r7 has GPIO part1 base 0x11400000
* r6 has GPIO part2 base 0x11000000
*/
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
push {lr}
/* r5 has always zero */
mov r5, #0
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
ldr r1, [r0]
/* AFTR wakeup reset */
ldr r2, =S5P_CHECK_DIDLE
cmp r1, r2
beq exit_wakeup
/* LPA wakeup reset */
ldr r2, =S5P_CHECK_LPA
cmp r1, r2
beq exit_wakeup
/* Sleep wakeup reset */
ldr r2, =S5P_CHECK_SLEEP
cmp r1, r2
beq wakeup_reset
/*
* If U-boot is already running in ram, no need to relocate U-Boot.
* Memory controller must be configured before relocating U-Boot
* in ram.
*/
ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
bic r1, pc, r0 /* pc <- current addr of code */
/* r1 <- unmasked bits of pc */
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
cmp r1, r2 /* compare r1, r2 */
beq 1f /* r0 == r1 then skip sdram init */
/* init system clock */
bl system_clock_init
/* Memory initialize */
bl mem_ctrl_asm_init
1:
/* for UART */
bl uart_asm_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
bl tzpc_init
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
/* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
mov pc, r1
nop
nop
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
push {lr}
ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =CLK_SRC_CPU_VAL
ldr r2, =CLK_SRC_CPU_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
2: subs r1, r1, #1
bne 2b
ldr r1, =CLK_SRC_TOP0_VAL
ldr r2, =CLK_SRC_TOP0_OFFSET
str r1, [r0, r2]
ldr r1, =CLK_SRC_TOP1_VAL
ldr r2, =CLK_SRC_TOP1_OFFSET
str r1, [r0, r2]
/* DMC */
ldr r1, =CLK_SRC_DMC_VAL
ldr r2, =CLK_SRC_DMC_OFFSET
str r1, [r0, r2]
/*CLK_SRC_LEFTBUS */
ldr r1, =CLK_SRC_LEFTBUS_VAL
ldr r2, =CLK_SRC_LEFTBUS_OFFSET
str r1, [r0, r2]
/*CLK_SRC_RIGHTBUS */
ldr r1, =CLK_SRC_RIGHTBUS_VAL
ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
str r1, [r0, r2]
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
ldr r1, =CLK_SRC_FSYS_VAL
ldr r2, =CLK_SRC_FSYS_OFFSET
str r1, [r0, r2]
/* UART[0:4] */
ldr r1, =CLK_SRC_PERIL0_VAL
ldr r2, =CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
/* FIMD0 */
ldr r1, =CLK_SRC_LCD0_VAL
ldr r2, =CLK_SRC_LCD0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1
bne 3b
/* CLK_DIV_CPU0 */
ldr r1, =CLK_DIV_CPU0_VAL
ldr r2, =CLK_DIV_CPU0_OFFSET
str r1, [r0, r2]
/* CLK_DIV_CPU1 */
ldr r1, =CLK_DIV_CPU1_VAL
ldr r2, =CLK_DIV_CPU1_OFFSET
str r1, [r0, r2]
/* CLK_DIV_DMC0 */
ldr r1, =CLK_DIV_DMC0_VAL
ldr r2, =CLK_DIV_DMC0_OFFSET
str r1, [r0, r2]
/*CLK_DIV_DMC1 */
ldr r1, =CLK_DIV_DMC1_VAL
ldr r2, =CLK_DIV_DMC1_OFFSET
str r1, [r0, r2]
/* CLK_DIV_LEFTBUS */
ldr r1, =CLK_DIV_LEFTBUS_VAL
ldr r2, =CLK_DIV_LEFTBUS_OFFSET
str r1, [r0, r2]
/* CLK_DIV_RIGHTBUS */
ldr r1, =CLK_DIV_RIGHTBUS_VAL
ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
str r1, [r0, r2]
/* CLK_DIV_TOP */
ldr r1, =CLK_DIV_TOP_VAL
ldr r2, =CLK_DIV_TOP_OFFSET
str r1, [r0, r2]
/* MMC[0:1] */
ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
ldr r2, =CLK_DIV_FSYS1_OFFSET
str r1, [r0, r2]
/* MMC[2:3] */
ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
ldr r2, =CLK_DIV_FSYS2_OFFSET
str r1, [r0, r2]
/* MMC4 */
ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
ldr r2, =CLK_DIV_FSYS3_OFFSET
str r1, [r0, r2]
/* CLK_DIV_PERIL0: UART Clock Divisors */
ldr r1, =CLK_DIV_PERIL0_VAL
ldr r2, =CLK_DIV_PERIL0_OFFSET
str r1, [r0, r2]
/* Set PLL locktime */
ldr r1, =PLL_LOCKTIME
ldr r2, =APLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =PLL_LOCKTIME
ldr r2, =MPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =PLL_LOCKTIME
ldr r2, =EPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =PLL_LOCKTIME
ldr r2, =VPLL_LOCK_OFFSET
str r1, [r0, r2]
/* APLL_CON1 */
ldr r1, =APLL_CON1_VAL
ldr r2, =APLL_CON1_OFFSET
str r1, [r0, r2]
/* APLL_CON0 */
ldr r1, =APLL_CON0_VAL
ldr r2, =APLL_CON0_OFFSET
str r1, [r0, r2]
/* MPLL_CON1 */
ldr r1, =MPLL_CON1_VAL
ldr r2, =MPLL_CON1_OFFSET
str r1, [r0, r2]
/* MPLL_CON0 */
ldr r1, =MPLL_CON0_VAL
ldr r2, =MPLL_CON0_OFFSET
str r1, [r0, r2]
/* EPLL */
ldr r1, =EPLL_CON1_VAL
ldr r2, =EPLL_CON1_OFFSET
str r1, [r0, r2]
/* EPLL_CON0 */
ldr r1, =EPLL_CON0_VAL
ldr r2, =EPLL_CON0_OFFSET
str r1, [r0, r2]
/* VPLL_CON1 */
ldr r1, =VPLL_CON1_VAL
ldr r2, =VPLL_CON1_OFFSET
str r1, [r0, r2]
/* VPLL_CON0 */
ldr r1, =VPLL_CON0_VAL
ldr r2, =VPLL_CON0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x30000
4: subs r1, r1, #1
bne 4b
pop {pc}
/*
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
* void uart_asm_init(void)
*/
.globl uart_asm_init
uart_asm_init:
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
ldr r0, =EXYNOS4_UART_BASE
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =ULCON_VAL
str r1, [r0, #ULCON_OFFSET]
ldr r1, =UCON_VAL
str r1, [r0, #UCON_OFFSET]
ldr r1, =UFCON_VAL
str r1, [r0, #UFCON_OFFSET]
ldr r1, =UBRDIV_VAL
str r1, [r0, #UBRDIV_OFFSET]
ldr r1, =UFRACVAL_VAL
str r1, [r0, #UFRACVAL_OFFSET]
mov pc, lr
nop
nop
nop
/* Setting TZPC[TrustZone Protection Controller] */
tzpc_init:
ldr r0, =TZPC0_BASE
mov r1, #R0SIZE
str r1, [r0]
mov r1, #DECPROTXSET
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC1_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC2_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC3_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC4_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC5_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
mov pc, lr

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common/package/utils/sysupgrade-helper/src/board/samsung/origen/mem_setup.S Normal file
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/*
* Memory setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "origen_setup.h"
#define SET_MIU
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
/*
* Async bridge configuration at CPU_core:
* 1: half_sync
* 0: full_sync
*/
ldr r0, =ASYNC_CONFIG
mov r1, #1
str r1, [r0]
#ifdef SET_MIU
ldr r0, =EXYNOS4_MIU_BASE
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
ldr r1, =0x20001507
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
/* Update MIU Configuration */
ldr r1, =0x00000001
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
#endif
/* DREX0 */
ldr r0, =EXYNOS4_DMC0_BASE
/*
* DLL Parameter Setting:
* Termination: Enable R/W
* Phase Delay for DQS Cleaning: 180' Shift
*/
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/*
* ZQ Calibration
* Termination: Disable
* Auto Calibration Start: Enable
*/
ldr r1, =0xE3855703
str r1, [r0, #DMC_PHYZQCONTROL]
/* Wait ?us*/
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
/*
* Update DLL Information:
* Force DLL Resyncronization
*/
ldr r1, =0xe000008e
str r1, [r0, #DMC_PHYCONTROL1]
/* Reset Force DLL Resyncronization */
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* Enable Differential DQS, DLL Off*/
ldr r1, =0x71101008
str r1, [r0, #DMC_PHYCONTROL0]
/* Activate PHY DLL: DLL On */
ldr r1, =0x7110100A
str r1, [r0, #DMC_PHYCONTROL0]
/* Set DLL Parameters */
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* DLL Start */
ldr r1, =0x7110100B
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00000000
str r1, [r0, #DMC_PHYCONTROL2]
/* Set Clock Ratio of Bus clock to Memory Clock */
ldr r1, =0x0FFF301a
str r1, [r0, #DMC_CONCONTROL]
/*
* Memor Burst length: 8
* Number of chips: 2
* Memory Bus width: 32 bit
* Memory Type: DDR3
* Additional Latancy for PLL: 1 Cycle
*/
ldr r1, =0x00312640
str r1, [r0, #DMC_MEMCONTROL]
/*
* Memory Configuration Chip 0
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
ldr r1, =0x20e01323
str r1, [r0, #DMC_MEMCONFIG0]
/*
* Memory Configuration Chip 1
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
ldr r1, =0x40e01323
str r1, [r0, #DMC_MEMCONFIG1]
/* Config Precharge Policy */
ldr r1, =0xff000000
str r1, [r0, #DMC_PRECHCONFIG]
/*
* TimingAref, TimingRow, TimingData, TimingPower Setting:
* Values as per Memory AC Parameters
*/
ldr r1, =0x000000BB
str r1, [r0, #DMC_TIMINGAREF]
ldr r1, =0x4046654f
str r1, [r0, #DMC_TIMINGROW]
ldr r1, =0x46400506
str r1, [r0, #DMC_TIMINGDATA]
ldr r1, =0x52000A3C
str r1, [r0, #DMC_TIMINGPOWER]
/* Chip0: NOP Command: Assert and Hold CKE to high level */
ldr r1, =0x07000000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
ldr r1, =0x00020000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00030000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010002
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000328
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
/* Chip0: ZQINIT */
ldr r1, =0x0a000000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
/* Chip1: NOP Command: Assert and Hold CKE to high level */
ldr r1, =0x07100000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
ldr r1, =0x00120000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00130000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110002
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100328
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
/* Chip1: ZQINIT */
ldr r1, =0x0a100000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #DMC_PHYCONTROL1]
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* Wait ?us*/
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* DREX1 */
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
/*
* DLL Parameter Setting:
* Termination: Enable R/W
* Phase Delay for DQS Cleaning: 180' Shift
*/
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/*
* ZQ Calibration:
* Termination: Disable
* Auto Calibration Start: Enable
*/
ldr r1, =0xE3855703
str r1, [r0, #DMC_PHYZQCONTROL]
/* Wait ?us*/
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
/*
* Update DLL Information:
* Force DLL Resyncronization
*/
ldr r1, =0xe000008e
str r1, [r0, #DMC_PHYCONTROL1]
/* Reset Force DLL Resyncronization */
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* Enable Differential DQS, DLL Off*/
ldr r1, =0x71101008
str r1, [r0, #DMC_PHYCONTROL0]
/* Activate PHY DLL: DLL On */
ldr r1, =0x7110100A
str r1, [r0, #DMC_PHYCONTROL0]
/* Set DLL Parameters */
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* DLL Start */
ldr r1, =0x7110100B
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00000000
str r1, [r0, #DMC_PHYCONTROL2]
/* Set Clock Ratio of Bus clock to Memory Clock */
ldr r1, =0x0FFF301a
str r1, [r0, #DMC_CONCONTROL]
/*
* Memor Burst length: 8
* Number of chips: 2
* Memory Bus width: 32 bit
* Memory Type: DDR3
* Additional Latancy for PLL: 1 Cycle
*/
ldr r1, =0x00312640
str r1, [r0, #DMC_MEMCONTROL]
/*
* Memory Configuration Chip 0
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
ldr r1, =0x20e01323
str r1, [r0, #DMC_MEMCONFIG0]
/*
* Memory Configuration Chip 1
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
ldr r1, =0x40e01323
str r1, [r0, #DMC_MEMCONFIG1]
/* Config Precharge Policy */
ldr r1, =0xff000000
str r1, [r0, #DMC_PRECHCONFIG]
/*
* TimingAref, TimingRow, TimingData, TimingPower Setting:
* Values as per Memory AC Parameters
*/
ldr r1, =0x000000BB
str r1, [r0, #DMC_TIMINGAREF]
ldr r1, =0x4046654f
str r1, [r0, #DMC_TIMINGROW]
ldr r1, =0x46400506
str r1, [r0, #DMC_TIMINGDATA]
ldr r1, =0x52000A3C
str r1, [r0, #DMC_TIMINGPOWER]
/* Chip0: NOP Command: Assert and Hold CKE to high level */
ldr r1, =0x07000000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
ldr r1, =0x00020000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00030000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010002
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000328
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
/* Chip 0: ZQINIT */
ldr r1, =0x0a000000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
/* Chip1: NOP Command: Assert and Hold CKE to high level */
ldr r1, =0x07100000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
ldr r1, =0x00120000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00130000
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110002
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100328
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
/* Chip1: ZQINIT */
ldr r1, =0x0a100000
str r1, [r0, #DMC_DIRECTCMD]
/* Wait ?us*/
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #DMC_PHYCONTROL1]
ldr r1, =0xe0000086
str r1, [r0, #DMC_PHYCONTROL1]
/* Wait ?us*/
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* turn on DREX0, DREX1 */
ldr r0, =EXYNOS4_DMC0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
ldr r0, =EXYNOS4_DMC1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
mov pc, lr

58
common/package/utils/sysupgrade-helper/src/board/samsung/origen/mmc_boot.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include<common.h>
#include<config.h>
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
* Pointer to API (Data transfer from mmc to ram)
*/
void copy_uboot_to_ram(void)
{
u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
}
void board_init_f(unsigned long bootflag)
{
__attribute__((noreturn)) void (*uboot)(void);
copy_uboot_to_ram();
/* Jump to U-Boot image */
uboot = (void *)CONFIG_SYS_TEXT_BASE;
(*uboot)();
/* Never returns Here */
}
/* Place Holders */
void board_init_r(gd_t *id, ulong dest_addr)
{
/* Function attribute is no-return */
/* This Function never executes */
while (1)
;
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}

109
common/package/utils/sysupgrade-helper/src/board/samsung/origen/origen.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
int board_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
PHYS_SDRAM_3_SIZE);
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
PHYS_SDRAM_4_SIZE);
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: ORIGEN\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int i, err;
/*
* MMC2 SD card GPIO:
*
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
}
#endif

558
common/package/utils/sysupgrade-helper/src/board/samsung/origen/origen_setup.h Normal file
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/*
* Machine Specific Values for ORIGEN board based on S5PV310
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ORIGEN_SETUP_H
#define _ORIGEN_SETUP_H
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/* Offsets of clock registers (sources and dividers) */
#define CLK_SRC_CPU_OFFSET 0x14200
#define CLK_DIV_CPU0_OFFSET 0x14500
#define CLK_DIV_CPU1_OFFSET 0x14504
#define CLK_SRC_DMC_OFFSET 0x10200
#define CLK_DIV_DMC0_OFFSET 0x10500
#define CLK_DIV_DMC1_OFFSET 0x10504
#define CLK_SRC_TOP0_OFFSET 0xC210
#define CLK_SRC_TOP1_OFFSET 0xC214
#define CLK_DIV_TOP_OFFSET 0xC510
#define CLK_SRC_LEFTBUS_OFFSET 0x4200
#define CLK_DIV_LEFTBUS_OFFSET 0x4500
#define CLK_SRC_RIGHTBUS_OFFSET 0x8200
#define CLK_DIV_RIGHTBUS_OFFSET 0x8500
#define CLK_SRC_FSYS_OFFSET 0xC240
#define CLK_DIV_FSYS1_OFFSET 0xC544
#define CLK_DIV_FSYS2_OFFSET 0xC548
#define CLK_DIV_FSYS3_OFFSET 0xC54C
#define CLK_SRC_PERIL0_OFFSET 0xC250
#define CLK_DIV_PERIL0_OFFSET 0xC550
#define CLK_SRC_LCD0_OFFSET 0xC234
#define APLL_LOCK_OFFSET 0x14000
#define MPLL_LOCK_OFFSET 0x14008
#define APLL_CON0_OFFSET 0x14100
#define APLL_CON1_OFFSET 0x14104
#define MPLL_CON0_OFFSET 0x14108
#define MPLL_CON1_OFFSET 0x1410C
#define EPLL_LOCK_OFFSET 0xC010
#define VPLL_LOCK_OFFSET 0xC020
#define EPLL_CON0_OFFSET 0xC110
#define EPLL_CON1_OFFSET 0xC114
#define VPLL_CON0_OFFSET 0xC120
#define VPLL_CON1_OFFSET 0xC124
/* DMC: DRAM Controllor Register offsets */
#define DMC_CONCONTROL 0x00
#define DMC_MEMCONTROL 0x04
#define DMC_MEMCONFIG0 0x08
#define DMC_MEMCONFIG1 0x0C
#define DMC_DIRECTCMD 0x10
#define DMC_PRECHCONFIG 0x14
#define DMC_PHYCONTROL0 0x18
#define DMC_PHYCONTROL1 0x1C
#define DMC_PHYCONTROL2 0x20
#define DMC_TIMINGAREF 0x30
#define DMC_TIMINGROW 0x34
#define DMC_TIMINGDATA 0x38
#define DMC_TIMINGPOWER 0x3C
#define DMC_PHYZQCONTROL 0x44
/* Bus Configuration Register Address */
#define ASYNC_CONFIG 0x10010350
/* MIU Config Register Offsets*/
#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
/* Offset for inform registers */
#define INFORM0_OFFSET 0x800
#define INFORM1_OFFSET 0x804
/* GPIO Offsets for UART: GPIO Contol Register */
#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
/* UART Register offsets */
#define ULCON_OFFSET 0x00
#define UCON_OFFSET 0x04
#define UFCON_OFFSET 0x08
#define UBRDIV_OFFSET 0x28
#define UFRACVAL_OFFSET 0x2C
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10110000
#define TZPC1_BASE 0x10120000
#define TZPC2_BASE 0x10130000
#define TZPC3_BASE 0x10140000
#define TZPC4_BASE 0x10150000
#define TZPC5_BASE 0x10160000
#define TZPC_DECPROT0SET_OFFSET 0x804
#define TZPC_DECPROT1SET_OFFSET 0x810
#define TZPC_DECPROT2SET_OFFSET 0x81C
#define TZPC_DECPROT3SET_OFFSET 0x828
/* CLK_SRC_CPU */
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
#define MUX_CORE_SEL_MOUTAPLL 0x0
#define MUX_CORE_SEL_SCLKMPLL 0x1
#define MUX_MPLL_SEL_FILPLL 0x0
#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
#define MUX_APLL_SEL_FILPLL 0x0
#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
| (MUX_CORE_SEL_MOUTAPLL << 16) \
| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
/* CLK_DIV_CPU0 */
#define APLL_RATIO 0x0
#define PCLK_DBG_RATIO 0x1
#define ATB_RATIO 0x3
#define PERIPH_RATIO 0x3
#define COREM1_RATIO 0x7
#define COREM0_RATIO 0x3
#define CORE_RATIO 0x0
#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (COREM1_RATIO << 8) \
| (COREM0_RATIO << 4) \
| (CORE_RATIO << 0))
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x0
#define COPY_RATIO 0x3
#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
/* CLK_SRC_DMC */
#define MUX_PWI_SEL_XXTI 0x0
#define MUX_PWI_SEL_XUSBXTI 0x1
#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
#define MUX_PWI_SEL_SCLKMPLL 0x6
#define MUX_PWI_SEL_SCLKEPLL 0x7
#define MUX_PWI_SEL_SCLKVPLL 0x8
#define MUX_DPHY_SEL_SCLKMPLL 0x0
#define MUX_DPHY_SEL_SCLKAPLL 0x1
#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
| (MUX_DPHY_SEL_SCLKMPLL << 8) \
| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
/* CLK_DIV_DMC0 */
#define CORE_TIMERS_RATIO 0x1
#define COPY2_RATIO 0x3
#define DMCP_RATIO 0x1
#define DMCD_RATIO 0x1
#define DMC_RATIO 0x1
#define DPHY_RATIO 0x1
#define ACP_PCLK_RATIO 0x1
#define ACP_RATIO 0x3
#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
| (COPY2_RATIO << 24) \
| (DMCP_RATIO << 20) \
| (DMCD_RATIO << 16) \
| (DMC_RATIO << 12) \
| (DPHY_RATIO << 8) \
| (ACP_PCLK_RATIO << 4) \
| (ACP_RATIO << 0))
/* CLK_DIV_DMC1 */
#define DPM_RATIO 0x1
#define DVSEM_RATIO 0x1
#define PWI_RATIO 0x1
#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
| (DVSEM_RATIO << 16) \
| (PWI_RATIO << 8))
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_SEL_ACLK_133 0x0
#define MUX_ONENAND_SEL_ACLK_160 0x1
#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
#define MUX_VPLL_SEL_FINPLL 0x0
#define MUX_VPLL_SEL_FOUTVPLL 0x1
#define MUX_EPLL_SEL_FINPLL 0x0
#define MUX_EPLL_SEL_FOUTEPLL 0x1
#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
| (MUX_VPLL_SEL_FINPLL << 8) \
| (MUX_EPLL_SEL_FINPLL << 4)\
| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
/* CLK_SRC_TOP1 */
#define VPLLSRC_SEL_FINPLL 0x0
#define VPLLSRC_SEL_SCLKHDMI24M 0x1
#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
/* CLK_DIV_TOP */
#define ONENAND_RATIO 0x0
#define ACLK_133_RATIO 0x5
#define ACLK_160_RATIO 0x4
#define ACLK_100_RATIO 0x7
#define ACLK_200_RATIO 0x3
#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
| (ACLK_133_RATIO << 12)\
| (ACLK_160_RATIO << 8) \
| (ACLK_100_RATIO << 4) \
| (ACLK_200_RATIO << 0))
/* CLK_SRC_LEFTBUS */
#define MUX_GDL_SEL_SCLKMPLL 0x0
#define MUX_GDL_SEL_SCLKAPLL 0x1
#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
/* CLK_DIV_LEFTBUS */
#define GPL_RATIO 0x1
#define GDL_RATIO 0x3
#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
/* CLK_SRC_RIGHTBUS */
#define MUX_GDR_SEL_SCLKMPLL 0x0
#define MUX_GDR_SEL_SCLKAPLL 0x1
#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO 0x1
#define GDR_RATIO 0x3
#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
/* CLK_SRS_FSYS: 6 = SCLKMPLL */
#define SATA_SEL_SCLKMPLL 0
#define SATA_SEL_SCLKAPLL 1
#define MMC_SEL_XXTI 0
#define MMC_SEL_XUSBXTI 1
#define MMC_SEL_SCLK_HDMI24M 2
#define MMC_SEL_SCLK_USBPHY0 3
#define MMC_SEL_SCLK_USBPHY1 4
#define MMC_SEL_SCLK_HDMIPHY 5
#define MMC_SEL_SCLKMPLL 6
#define MMC_SEL_SCLKEPLL 7
#define MMC_SEL_SCLKVPLL 8
#define MMCC0_SEL MMC_SEL_SCLKMPLL
#define MMCC1_SEL MMC_SEL_SCLKMPLL
#define MMCC2_SEL MMC_SEL_SCLKMPLL
#define MMCC3_SEL MMC_SEL_SCLKMPLL
#define MMCC4_SEL MMC_SEL_SCLKMPLL
#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
| (MMCC4_SEL << 16) \
| (MMCC3_SEL << 12) \
| (MMCC2_SEL << 8) \
| (MMCC1_SEL << 4) \
| (MMCC0_SEL << 0))
/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
/* CLK_DIV_FSYS1 */
#define MMC0_RATIO 0xF
#define MMC0_PRE_RATIO 0x0
#define MMC1_RATIO 0xF
#define MMC1_PRE_RATIO 0x0
#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
| (MMC1_RATIO << 16) \
| (MMC0_PRE_RATIO << 8) \
| (MMC0_RATIO << 0))
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO 0xF
#define MMC2_PRE_RATIO 0x0
#define MMC3_RATIO 0xF
#define MMC3_PRE_RATIO 0x0
#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
| (MMC3_RATIO << 16) \
| (MMC2_PRE_RATIO << 8) \
| (MMC2_RATIO << 0))
/* CLK_DIV_FSYS3 */
#define MMC4_RATIO 0xF
#define MMC4_PRE_RATIO 0x0
#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
| (MMC4_RATIO << 0))
/* CLK_SRC_PERIL0 */
#define UART_SEL_XXTI 0
#define UART_SEL_XUSBXTI 1
#define UART_SEL_SCLK_HDMI24M 2
#define UART_SEL_SCLK_USBPHY0 3
#define UART_SEL_SCLK_USBPHY1 4
#define UART_SEL_SCLK_HDMIPHY 5
#define UART_SEL_SCLKMPLL 6
#define UART_SEL_SCLKEPLL 7
#define UART_SEL_SCLKVPLL 8
#define UART0_SEL UART_SEL_SCLKMPLL
#define UART1_SEL UART_SEL_SCLKMPLL
#define UART2_SEL UART_SEL_SCLKMPLL
#define UART3_SEL UART_SEL_SCLKMPLL
#define UART4_SEL UART_SEL_SCLKMPLL
#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL << 0))
/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
/* CLK_DIV_PERIL0 */
#define UART0_RATIO 7
#define UART1_RATIO 7
#define UART2_RATIO 7
#define UART3_RATIO 7
#define UART4_RATIO 7
#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
| (UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_SRC_LCD0 */
#define FIMD_SEL_SCLKMPLL 6
#define MDNIE0_SEL_XUSBXTI 1
#define MDNIE_PWM0_SEL_XUSBXTI 1
#define MIPI0_SEL_XUSBXTI 1
#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
| (MDNIE0_SEL_XUSBXTI << 4) \
| (FIMD_SEL_SCLKMPLL << 0))
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20
/* PLL Values */
#define DISABLE 0
#define ENABLE 1
#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
| (mdiv << 16) \
| (pdiv << 8) \
| (sdiv << 0))
/* APLL_CON0 */
#define APLL_MDIV 0xFA
#define APLL_PDIV 0x6
#define APLL_SDIV 0x1
#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
/* APLL_CON1 */
#define APLL_AFC_ENB 0x1
#define APLL_AFC 0xC
#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
/* MPLL_CON0 */
#define MPLL_MDIV 0xC8
#define MPLL_PDIV 0x6
#define MPLL_SDIV 0x1
#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
/* MPLL_CON1 */
#define MPLL_AFC_ENB 0x0
#define MPLL_AFC 0x1C
#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
/* EPLL_CON0 */
#define EPLL_MDIV 0x30
#define EPLL_PDIV 0x3
#define EPLL_SDIV 0x2
#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
/* EPLL_CON1 */
#define EPLL_K 0x0
#define EPLL_CON1_VAL (EPLL_K >> 0)
/* VPLL_CON0 */
#define VPLL_MDIV 0x35
#define VPLL_PDIV 0x3
#define VPLL_SDIV 0x2
#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
/* VPLL_CON1 */
#define VPLL_SSCG_EN DISABLE
#define VPLL_SEL_PF_DN_SPREAD 0x0
#define VPLL_MRR 0x11
#define VPLL_MFR 0x0
#define VPLL_K 0x400
#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
| (VPLL_SEL_PF_DN_SPREAD << 29) \
| (VPLL_MRR << 24) \
| (VPLL_MFR << 16) \
| (VPLL_K << 0))
/*
* UART GPIO_A0/GPIO_A1 Control Register Value
* 0x2: UART Function
*/
#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
/* ULCON: UART Line Control Value 8N1 */
#define WORD_LEN_5_BIT 0x00
#define WORD_LEN_6_BIT 0x01
#define WORD_LEN_7_BIT 0x02
#define WORD_LEN_8_BIT 0x03
#define STOP_BIT_1 0x00
#define STOP_BIT_2 0x01
#define NO_PARITY 0x00
#define ODD_PARITY 0x4
#define EVEN_PARITY 0x5
#define FORCED_PARITY_CHECK_AS_1 0x6
#define FORCED_PARITY_CHECK_AS_0 0x7
#define INFRAMODE_NORMAL 0x00
#define INFRAMODE_INFRARED 0x01
#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
| (NO_PARITY << 3) \
| (STOP_BIT_1 << 2) \
| (WORD_LEN_8_BIT << 0))
/*
* UCON: UART Control Value
* Tx_interrupt Type: Level
* Rx_interrupt Type: Level
* Rx Timeout Enabled: Yes
* Rx-Error Atatus_Int Enable: Yes
* Loop_Back: No
* Break Signal: No
* Transmit mode : Interrupt request/polling
* Receive mode : Interrupt request/polling
*/
#define TX_PULSE_INTERRUPT 0
#define TX_LEVEL_INTERRUPT 1
#define RX_PULSE_INTERRUPT 0
#define RX_LEVEL_INTERRUPT 1
#define RX_TIME_OUT ENABLE
#define RX_ERROR_STATE_INT_ENB ENABLE
#define LOOP_BACK DISABLE
#define BREAK_SIGNAL DISABLE
#define TX_MODE_DISABLED 0X00
#define TX_MODE_IRQ_OR_POLL 0X01
#define TX_MODE_DMA 0X02
#define RX_MODE_DISABLED 0X00
#define RX_MODE_IRQ_OR_POLL 0X01
#define RX_MODE_DMA 0X02
#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
| (RX_LEVEL_INTERRUPT << 8) \
| (RX_TIME_OUT << 7) \
| (RX_ERROR_STATE_INT_ENB << 6) \
| (LOOP_BACK << 5) \
| (BREAK_SIGNAL << 4) \
| (TX_MODE_IRQ_OR_POLL << 2) \
| (RX_MODE_IRQ_OR_POLL << 0))
/*
* UFCON: UART FIFO Control Value
* Tx FIFO Trigger LEVEL: 2 Bytes (001)
* Rx FIFO Trigger LEVEL: 2 Bytes (001)
* Tx Fifo Reset: No
* Rx Fifo Reset: No
* FIFO Enable: Yes
*/
#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
#define TX_FIFO_RESET DISABLE
#define RX_FIFO_RESET DISABLE
#define FIFO_ENABLE ENABLE
#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
| (RX_FIFO_TRIGGER_LEVEL << 4) \
| (TX_FIFO_RESET << 2) \
| (RX_FIFO_RESET << 1) \
| (FIFO_ENABLE << 0))
/*
* Baud Rate Division Value
* 115200 BAUD:
* UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
* UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
*/
#define UBRDIV_VAL 0x35
/*
* Fractional Part of Baud Rate Divisor:
* 115200 BAUD:
* UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
* UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
*/
#define UFRACVAL_VAL 0x4
/*
* TZPC Register Value :
* R0SIZE: 0x0 : Size of secured ram
*/
#define R0SIZE 0x0
/*
* TZPC Decode Protection Register Value :
* DECPROTXSET: 0xFF : Set Decode region to non-secure
*/
#define DECPROTXSET 0xFF
#endif

126
common/package/utils/sysupgrade-helper/src/board/samsung/origen/tools/mkv310_image.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#include <string.h>
#include <sys/stat.h>
#define BUFSIZE (16*1024)
#define IMG_SIZE (16*1024)
#define SPL_HEADER_SIZE 16
#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
#define SPL_HEADER "S5PC210 HEADER "
/*
* Requirement:
* IROM code reads first 14K bytes from boot device.
* It then calculates the checksum of 14K-4 bytes and compare with data at
* 14K-4 offset.
*
* This function takes two filenames:
* IN "u-boot-spl.bin" and
* OUT "$(BOARD)-spl.bin as filenames.
* It reads the "u-boot-spl.bin" in 16K buffer.
* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
* It writes the buffer to "$(BOARD)-spl.bin" file.
*/
int main(int argc, char **argv)
{
int i, len;
unsigned char buffer[BUFSIZE] = {0};
int ifd, ofd;
unsigned int checksum = 0, count;
if (argc != 3) {
printf(" %d Wrong number of arguments\n", argc);
exit(EXIT_FAILURE);
}
ifd = open(argv[1], O_RDONLY);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[1], strerror(errno));
exit(EXIT_FAILURE);
}
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
exit(EXIT_FAILURE);
}
len = lseek(ifd, 0, SEEK_END);
lseek(ifd, 0, SEEK_SET);
memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE);
count = (len < (IMG_SIZE - SPL_HEADER_SIZE))
? len : (IMG_SIZE - SPL_HEADER_SIZE);
if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) {
fprintf(stderr, "%s: Can't read %s: %s\n",
argv[0], argv[1], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)
checksum += buffer[i+16];
*(ulong *)buffer ^= 0x1f;
*(ulong *)(buffer+4) ^= checksum;
for (i = 1; i < SPL_HEADER_SIZE; i++)
buffer[i] ^= buffer[i-1];
if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
fprintf(stderr, "%s: Can't write %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
if (ifd)
close(ifd);
if (ofd)
close(ofd);
return EXIT_SUCCESS;
}

45
common/package/utils/sysupgrade-helper/src/board/samsung/smdk2410/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := smdk2410.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

167
common/package/utils/sysupgrade-helper/src/board/samsung/smdk2410/lowlevel_init.S Normal file
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/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
/* some parameters for the board */
/*
*
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
*
* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
*
*/
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW32)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/* BANK0CON */
#define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0
#define B0_PMC 0x0 /* normal */
/* BANK1CON */
#define B1_Tacs 0x0 /* 0clk */
#define B1_Tcos 0x0 /* 0clk */
#define B1_Tacc 0x7 /* 14clk */
#define B1_Tcoh 0x0 /* 0clk */
#define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0x0 /* 0clk */
#define B3_Tcos 0x3 /* 4clk */
#define B3_Tacc 0x7 /* 14clk */
#define B3_Tcoh 0x1 /* 1clk */
#define B3_Tah 0x0 /* 0clk */
#define B3_Tacp 0x3 /* 6clk */
#define B3_PMC 0x0 /* normal */
#define B4_Tacs 0x0 /* 0clk */
#define B4_Tcos 0x0 /* 0clk */
#define B4_Tacc 0x7 /* 14clk */
#define B4_Tcoh 0x0 /* 0clk */
#define B4_Tah 0x0 /* 0clk */
#define B4_Tacp 0x0
#define B4_PMC 0x0 /* normal */
#define B5_Tacs 0x0 /* 0clk */
#define B5_Tcos 0x0 /* 0clk */
#define B5_Tacc 0x7 /* 14clk */
#define B5_Tcoh 0x0 /* 0clk */
#define B5_Tah 0x0 /* 0clk */
#define B5_Tacp 0x0
#define B5_PMC 0x0 /* normal */
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
/* REFRESH parameter */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */
ldr r0, =SMRDATA
ldr r1, _TEXT_BASE
sub r0, r0, r1
ldr r1, =BWSCON /* Bus Width Status Controller */
add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
/* everything is fine now */
mov pc, lr
.ltorg
/* the literal pools origin */
SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.word 0x32
.word 0x30
.word 0x30

155
common/package/utils/sysupgrade-helper/src/board/samsung/smdk2410/smdk2410.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002, 2010
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
#define FCLK_SPEED 1
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
#define M_MDIV 0xA1
#define M_PDIV 0x3
#define M_SDIV 0x1
#endif
#define USB_CLOCK 1
#if USB_CLOCK==0
#define U_M_MDIV 0xA1
#define U_M_PDIV 0x3
#define U_M_SDIV 0x1
#elif USB_CLOCK==1
#define U_M_MDIV 0x48
#define U_M_PDIV 0x3
#define U_M_SDIV 0x2
#endif
static inline void pll_delay(unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_early_init_f(void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */
writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);
/* some delay between MPLL and UPLL */
pll_delay(4000);
/* configure UPLL */
writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);
/* some delay between MPLL and UPLL */
pll_delay(8000);
/* set up the I/O ports */
writel(0x007FFFFF, &gpio->gpacon);
writel(0x00044555, &gpio->gpbcon);
writel(0x000007FF, &gpio->gpbup);
writel(0xAAAAAAAA, &gpio->gpccon);
writel(0x0000FFFF, &gpio->gpcup);
writel(0xAAAAAAAA, &gpio->gpdcon);
writel(0x0000FFFF, &gpio->gpdup);
writel(0xAAAAAAAA, &gpio->gpecon);
writel(0x0000FFFF, &gpio->gpeup);
writel(0x000055AA, &gpio->gpfcon);
writel(0x000000FF, &gpio->gpfup);
writel(0xFF95FFBA, &gpio->gpgcon);
writel(0x0000FFFF, &gpio->gpgup);
writel(0x002AFAAA, &gpio->gphcon);
writel(0x000007FF, &gpio->gphup);
return 0;
}
int board_init(void)
{
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
icache_enable();
dcache_enable();
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif
/*
* Hardcoded flash setup:
* Flash 0 is a non-CFI AMD AM29LV800BB flash.
*/
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
}

58
common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/Makefile Normal file
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#
# Copyright (C) 2012 Samsung Electronics
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
endif
ifdef CONFIG_SPL_BUILD
COBJS += mmc_boot.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL := $(obj).depend $(LIB)
all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

202
common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/clock_init.c Normal file
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/*
* Clock setup for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include "setup.h"
void system_clock_init()
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
/*
* MUX_APLL_SEL[0]: FINPLL = 0
* MUX_CPU_SEL[6]: MOUTAPLL = 0
* MUX_HPM_SEL[20]: MOUTAPLL = 0
*/
writel(0x0, &clk->src_cpu);
/* MUX_MPLL_SEL[8]: FINPLL = 0 */
writel(0x0, &clk->src_core1);
/*
* VPLLSRC_SEL[0]: FINPLL = 0
* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
*/
writel(0x0, &clk->src_top2);
/* MUX_BPLL_SEL[0]: FINPLL = 0 */
writel(0x0, &clk->src_cdrex);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
writel(CLK_SRC_LEX_VAL, &clk->src_lex);
/* UART [0-5]: SCLKMPLL = 6 */
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
/* Set Clock Ratios */
writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
/* Set COPY and HPM Ratio */
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
/* CORED_RATIO, COREP_RATIO */
writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
/* ACLK_*_RATIO */
writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
/* ACLK_*_RATIO */
writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
/* CDREX Ratio */
writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
/* MCLK_EFPHY_RATIO[3:0] */
writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
writel(CLK_DIV_LEX_VAL, &clk->div_lex);
/* PCLK_R0X_RATIO[3:0] */
writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
/* PCLK_R1X_RATIO[3:0] */
writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
/* UART[0-4] */
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
/* PWM_RATIO[3:0] */
writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
/* SATA_RATIO, USB_DRD_RATIO */
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
/* MMC[0-1] */
writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
/* MMC[2-3] */
writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
/* MMC[4] */
writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
/* ACLK|PLCK_ACP_RATIO */
writel(CLK_DIV_ACP_VAL, &clk->div_acp);
/* ISPDIV0_RATIO, ISPDIV1_RATIO */
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
/* MPWMDIV_RATIO */
writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
/* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock);
writel(MPLL_LOCK_VAL, &clk->mpll_lock);
writel(BPLL_LOCK_VAL, &clk->bpll_lock);
writel(CPLL_LOCK_VAL, &clk->cpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock);
writel(VPLL_LOCK_VAL, &clk->vpll_lock);
sdelay(0x10000);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
writel(APLL_CON0_VAL, &clk->apll_con0);
sdelay(0x30000);
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
writel(MPLL_CON0_VAL, &clk->mpll_con0);
sdelay(0x30000);
writel(BPLL_CON1_VAL, &clk->bpll_con1);
writel(BPLL_CON0_VAL, &clk->bpll_con0);
sdelay(0x30000);
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
writel(CPLL_CON0_VAL, &clk->cpll_con0);
sdelay(0x30000);
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
writel(EPLL_CON0_VAL, &clk->epll_con0);
sdelay(0x30000);
/* Set VPLL */
writel(VPLL_CON2_VAL, &clk->vpll_con2);
writel(VPLL_CON1_VAL, &clk->vpll_con1);
writel(VPLL_CON0_VAL, &clk->vpll_con0);
sdelay(0x30000);
/* Set MPLL */
/* After Initiallising th PLL select the sources accordingly */
/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
/*
* VPLLSRC_SEL[0]: FINPLL = 0
* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
* MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
*/
writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
}

462
common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/dmc_init.c Normal file
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/*
* Memory setup for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/io.h>
#include <asm/arch/dmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include "setup.h"
/* APLL : 1GHz */
/* MCLK_CDREX: MCLK_CDREX_533*/
/* LPDDR support: LPDDR2 */
static void reset_phy_ctrl(void);
static void config_zq(struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void update_reset_dll(struct exynos5_dmc *);
static void config_cdrex(void);
static void config_mrs(struct exynos5_dmc *);
static void sec_sdram_phy_init(struct exynos5_dmc *);
static void config_prech(struct exynos5_dmc *);
static void config_rdlvl(struct exynos5_dmc *,
struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void config_memory(struct exynos5_dmc *);
static void config_offsets(unsigned int,
struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
sdelay(0x10000);
}
static void config_zq(struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val = 0;
/*
* ZQ Calibration:
* Select Driver Strength,
* long calibration for manual calibration
*/
val = PHY_CON16_RESET_VAL;
SET_ZQ_MODE_DDS_VAL(val);
SET_ZQ_MODE_TERM_VAL(val);
val |= ZQ_CLK_DIV_EN;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
/* Disable termination */
val |= ZQ_MODE_NOTERM;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
/* ZQ_MANUAL_START: Enable */
val |= ZQ_MANUAL_STR;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
sdelay(0x10000);
/* ZQ_MANUAL_START: Disable */
val &= ~ZQ_MANUAL_STR;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
}
static void update_reset_dll(struct exynos5_dmc *dmc)
{
unsigned long val;
/*
* Update DLL Information:
* Force DLL Resyncronization
*/
val = readl(&dmc->phycontrol0);
val |= FP_RSYNC;
writel(val, &dmc->phycontrol0);
/* Reset Force DLL Resyncronization */
val = readl(&dmc->phycontrol0);
val &= ~FP_RSYNC;
writel(val, &dmc->phycontrol0);
}
static void config_mrs(struct exynos5_dmc *dmc)
{
unsigned long channel, chip, mask = 0, val;
for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
SET_CMD_CHANNEL(mask, channel);
for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
/*
* NOP CMD:
* Assert and hold CKE to logic high level
*/
SET_CMD_CHIP(mask, chip);
val = DIRECT_CMD_NOP | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
/* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
val = DIRECT_CMD_MRS1 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
val = DIRECT_CMD_MRS2 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
/* MCLK_CDREX_533 */
val = DIRECT_CMD_MRS3 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
val = DIRECT_CMD_MRS4 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
}
}
}
static void config_prech(struct exynos5_dmc *dmc)
{
unsigned long channel, chip, mask = 0, val;
for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
SET_CMD_CHANNEL(mask, channel);
for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
SET_CMD_CHIP(mask, chip);
/* PALL (all banks precharge) CMD */
val = DIRECT_CMD_PALL | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
}
}
}
static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
{
unsigned long val;
val = readl(&dmc->concontrol);
val |= DFI_INIT_START;
writel(val, &dmc->concontrol);
sdelay(0x10000);
val = readl(&dmc->concontrol);
val &= ~DFI_INIT_START;
writel(val, &dmc->concontrol);
}
static void config_offsets(unsigned int state,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
/* Set Offsets to read DQS */
val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con4);
writel(val, &phy1_ctrl->phy_con4);
/* Set Offsets to read DQ */
val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con6);
writel(val, &phy1_ctrl->phy_con6);
/* Debug Offset */
val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con10);
writel(val, &phy1_ctrl->phy_con10);
}
static void config_cdrex(void)
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
sdelay(0x30000);
}
static void config_ctrl_dll_on(unsigned int state,
unsigned int ctrl_force_val,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
val = readl(&phy0_ctrl->phy_con12);
CONFIG_CTRL_DLL_ON(val, state);
SET_CTRL_FORCE_VAL(val, ctrl_force_val);
writel(val, &phy0_ctrl->phy_con12);
val = readl(&phy1_ctrl->phy_con12);
CONFIG_CTRL_DLL_ON(val, state);
SET_CTRL_FORCE_VAL(val, ctrl_force_val);
writel(val, &phy1_ctrl->phy_con12);
}
static void config_ctrl_start(unsigned int state,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
val = readl(&phy0_ctrl->phy_con12);
CONFIG_CTRL_START(val, state);
writel(val, &phy0_ctrl->phy_con12);
val = readl(&phy1_ctrl->phy_con12);
CONFIG_CTRL_START(val, state);
writel(val, &phy1_ctrl->phy_con12);
}
#if defined(CONFIG_RD_LVL)
static void config_rdlvl(struct exynos5_dmc *dmc,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
/* Disable CTRL_DLL_ON and set ctrl_force */
config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl);
/*
* Set ctrl_gateadj, ctrl_readadj
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
val = SET_RDLVL_RDDATAPADJ;
writel(val, &phy0_ctrl->phy_con1);
writel(val, &phy1_ctrl->phy_con1);
/* LPDDR2 Address */
writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22);
writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22);
/* Enable Byte Read Leveling set ctrl_ddr_mode */
val = readl(&phy0_ctrl->phy_con0);
val |= BYTE_RDLVL_EN;
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val |= BYTE_RDLVL_EN;
writel(val, &phy1_ctrl->phy_con0);
/* rdlvl_en: Use levelling offset instead ctrl_shiftc */
val = PHY_CON2_RESET_VAL | RDLVL_EN;
writel(val, &phy0_ctrl->phy_con2);
writel(val, &phy1_ctrl->phy_con2);
sdelay(0x10000);
/* Enable Data Eye Training */
val = readl(&dmc->rdlvl_config);
val |= CTRL_RDLVL_DATA_EN;
writel(val, &dmc->rdlvl_config);
sdelay(0x10000);
/* Disable Data Eye Training */
val = readl(&dmc->rdlvl_config);
val &= ~CTRL_RDLVL_DATA_EN;
writel(val, &dmc->rdlvl_config);
/* RdDeSkew_clear: Clear */
val = readl(&phy0_ctrl->phy_con2);
val |= RDDSKEW_CLEAR;
writel(val, &phy0_ctrl->phy_con2);
val = readl(&phy1_ctrl->phy_con2);
val |= RDDSKEW_CLEAR;
writel(val, &phy1_ctrl->phy_con2);
/* Enable CTRL_DLL_ON */
config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
update_reset_dll(dmc);
sdelay(0x10000);
/* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */
val = readl(&phy0_ctrl->phy_con0);
val &= ~CTRL_ATGATE;
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val &= ~CTRL_ATGATE;
writel(val, &phy1_ctrl->phy_con0);
}
#endif
static void config_memory(struct exynos5_dmc *dmc)
{
/*
* Memory Configuration Chip 0
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
/*
* Memory Configuration Chip 1
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
/*
* Chip0: AXI
* AXI Base Address: 0x40000000
* AXI Base Address Mask: 0x780
*/
writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
/*
* Chip1: AXI
* AXI Base Address: 0x80000000
* AXI Base Address Mask: 0x780
*/
writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
}
void mem_ctrl_init()
{
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
struct exynos5_dmc *dmc;
unsigned long val;
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
/* Reset PHY Controllor: PHY_RESET[0] */
reset_phy_ctrl();
/*set Read Latancy and Burst Length for PHY0 and PHY1 */
writel(PHY_CON42_VAL, &phy0_ctrl->phy_con42);
writel(PHY_CON42_VAL, &phy1_ctrl->phy_con42);
/* ZQ Cofiguration */
config_zq(phy0_ctrl, phy1_ctrl);
/* Operation Mode : LPDDR2 */
val = PHY_CON0_RESET_VAL;
SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
writel(val, &phy0_ctrl->phy_con0);
writel(val, &phy1_ctrl->phy_con0);
/* DQS, DQ: Signal, for LPDDR2: Always Set */
val = CTRL_PULLD_DQ | CTRL_PULLD_DQS;
writel(val, &phy0_ctrl->phy_con14);
writel(val, &phy1_ctrl->phy_con14);
/* Init SEC SDRAM PHY */
sec_sdram_phy_init(dmc);
sdelay(0x10000);
update_reset_dll(dmc);
/*
* Dynamic Clock: Always Running
* Memory Burst length: 4
* Number of chips: 2
* Memory Bus width: 32 bit
* Memory Type: LPDDR2-S4
* Additional Latancy for PLL: 1 Cycle
*/
writel(DMC_MEMCONTROL_VAL, &dmc->memcontrol);
config_memory(dmc);
/* Precharge Configuration */
writel(DMC_PRECHCONFIG_VAL, &dmc->prechconfig);
/* Power Down mode Configuration */
writel(DMC_PWRDNCONFIG_VAL, &dmc->pwrdnconfig);
/* Periodic Refrese Interval */
writel(DMC_TIMINGREF_VAL, &dmc->timingref);
/*
* TimingRow, TimingData, TimingPower Setting:
* Values as per Memory AC Parameters
*/
writel(DMC_TIMINGROW_VAL, &dmc->timingrow);
writel(DMC_TIMINGDATA_VAL, &dmc->timingdata);
writel(DMC_TIMINGPOWER_VAL, &dmc->timingpower);
/* Memory Channel Inteleaving Size: 128 Bytes */
writel(CONFIG_IV_SIZE, &dmc->ivcontrol);
/* Set DQS, DQ and DEBUG offsets */
config_offsets(SET, phy0_ctrl, phy1_ctrl);
/* Disable CTRL_DLL_ON and set ctrl_force */
config_ctrl_dll_on(RESET, 0x7F, phy0_ctrl, phy1_ctrl);
sdelay(0x10000);
update_reset_dll(dmc);
/* Config MRS(Mode Register Settingg) */
config_mrs(dmc);
config_cdrex();
/* Reset DQS DQ and DEBUG offsets */
config_offsets(RESET, phy0_ctrl, phy1_ctrl);
/* Enable CTRL_DLL_ON */
config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
/* Stop DLL Locking */
config_ctrl_start(RESET, phy0_ctrl, phy1_ctrl);
sdelay(0x10000);
/* Start DLL Locking */
config_ctrl_start(SET, phy0_ctrl, phy1_ctrl);
sdelay(0x10000);
update_reset_dll(dmc);
#if defined(CONFIG_RD_LVL)
config_rdlvl(dmc, phy0_ctrl, phy1_ctrl);
#endif
config_prech(dmc);
/*
* Dynamic Clock: Stops During Idle Period
* Dynamic Power Down: Enable
* Dynamic Self refresh: Enable
*/
val = readl(&dmc->memcontrol);
val |= CLK_STOP_EN | DPWRDN_EN | DSREF_EN;
writel(val, &dmc->memcontrol);
/* Start Auto refresh */
val = readl(&dmc->concontrol);
val |= AREF_EN;
writel(val, &dmc->concontrol);
}

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common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/lowlevel_init.S Normal file
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/*
* Lowlevel setup for SMDK5250 board based on S5PC520
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* use iRAM stack in bl2 */
ldr sp, =CONFIG_IRAM_STACK
stmdb r13!, {ip,lr}
/* check reset status */
ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
ldr r1, [r0]
/* AFTR wakeup reset */
ldr r2, =S5P_CHECK_DIDLE
cmp r1, r2
beq exit_wakeup
/* LPA wakeup reset */
ldr r2, =S5P_CHECK_LPA
cmp r1, r2
beq exit_wakeup
/* Sleep wakeup reset */
ldr r2, =S5P_CHECK_SLEEP
cmp r1, r2
beq wakeup_reset
/*
* If U-boot is already running in RAM, no need to relocate U-Boot.
* Memory controller must be configured before relocating U-Boot
* in ram.
*/
ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
bic r1, pc, r0 /* pc <- current addr of code */
/* r1 <- unmasked bits of pc */
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
cmp r1, r2 /* compare r1, r2 */
beq 1f /* r0 == r1 then skip sdram init */
/* init system clock */
bl system_clock_init
/* Memory initialize */
bl mem_ctrl_init
1:
bl tzpc_init
ldmia r13!, {ip,pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_init
bl tzpc_init
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
/* r1 = physical address of exynos5_cpu_resume function*/
ldr r1, [r0]
/* Jump to kernel */
mov pc, r1
nop
nop

58
common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/mmc_boot.c Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include<common.h>
#include<config.h>
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
* Pointer to API (Data transfer from mmc to ram)
*/
void copy_uboot_to_ram(void)
{
u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
}
void board_init_f(unsigned long bootflag)
{
__attribute__((noreturn)) void (*uboot)(void);
copy_uboot_to_ram();
/* Jump to U-Boot image */
uboot = (void *)CONFIG_SYS_TEXT_BASE;
(*uboot)();
/* Never returns Here */
}
/* Place Holders */
void board_init_r(gd_t *id, ulong dest_addr)
{
/* Function attribute is no-return */
/* This Function never executes */
while (1)
;
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}

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common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/setup.h Normal file
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/*
* Machine Specific Values for SMDK5250 board based on S5PC520
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SMDK5250_SETUP_H
#define _SMDK5250_SETUP_H
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/* GPIO Offsets for UART: GPIO Contol Register */
#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10100000
#define TZPC1_BASE 0x10110000
#define TZPC2_BASE 0x10120000
#define TZPC3_BASE 0x10130000
#define TZPC4_BASE 0x10140000
#define TZPC5_BASE 0x10150000
#define TZPC6_BASE 0x10160000
#define TZPC7_BASE 0x10170000
#define TZPC8_BASE 0x10180000
#define TZPC9_BASE 0x10190000
/* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */
#define MUX_HPM_SEL 0
#define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
| (MUX_CPU_SEL << 16) \
| (MUX_APLL_SEL))
/* CLK_DIV_CPU0 */
#define ARM2_RATIO 0x0
#define APLL_RATIO 0x1
#define PCLK_DBG_RATIO 0x1
#define ATB_RATIO 0x4
#define PERIPH_RATIO 0x7
#define ACP_RATIO 0x7
#define CPUD_RATIO 0x2
#define ARM_RATIO 0x0
#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
| (APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (ACP_RATIO << 8) \
| (CPUD_RATIO << 4) \
| (ARM_RATIO))
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x4
#define COPY_RATIO 0x0
#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
| (COPY_RATIO))
#define APLL_MDIV 0x7D
#define APLL_PDIV 0x3
#define APLL_SDIV 0x0
#define MPLL_MDIV 0x64
#define MPLL_PDIV 0x3
#define MPLL_SDIV 0x0
#define CPLL_MDIV 0x96
#define CPLL_PDIV 0x4
#define CPLL_SDIV 0x0
/* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800)
/* MPLL_CON1 */
#define MPLL_CON1_VAL (0x00203800)
/* CPLL_CON1 */
#define CPLL_CON1_VAL (0x00203800)
#define EPLL_MDIV 0x60
#define EPLL_PDIV 0x3
#define EPLL_SDIV 0x3
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
#define VPLL_MDIV 0x96
#define VPLL_PDIV 0x3
#define VPLL_SDIV 0x2
#define VPLL_CON1_VAL 0x00000000
#define VPLL_CON2_VAL 0x00000080
#define BPLL_MDIV 0x215
#define BPLL_PDIV 0xC
#define BPLL_SDIV 0x1
#define BPLL_CON1_VAL 0x00203800
/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
/* CLK_SRC_CORE0 */
#define CLK_SRC_CORE0_VAL 0x00060000
/* CLK_SRC_CORE1 */
#define CLK_SRC_CORE1_VAL 0x100
/* CLK_DIV_CORE0 */
#define CLK_DIV_CORE0_VAL 0x120000
/* CLK_DIV_CORE1 */
#define CLK_DIV_CORE1_VAL 0x07070700
/* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_INIT_VAL 0x1
#define CLK_SRC_CDREX_VAL 0x111
/* CLK_DIV_CDREX */
#define CLK_DIV_CDREX_INIT_VAL 0x71771111
#define MCLK_CDREX2_RATIO 0x0
#define ACLK_EFCON_RATIO 0x1
#define MCLK_DPHY_RATIO 0x0
#define MCLK_CDREX_RATIO 0x0
#define ACLK_C2C_200_RATIO 0x1
#define C2C_CLK_400_RATIO 0x1
#define PCLK_CDREX_RATIO 0x3
#define ACLK_CDREX_RATIO 0x1
#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \
| (MCLK_CDREX_RATIO << 16) \
| (ACLK_C2C_200_RATIO << 12) \
| (C2C_CLK_400_RATIO << 8) \
| (PCLK_CDREX_RATIO << 4) \
| (ACLK_CDREX_RATIO))
#define MCLK_EFPHY_RATIO 0x4
#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO
/* CLK_DIV_ACP */
#define CLK_DIV_ACP_VAL 0x12
/* CLK_SRC_TOP0 */
#define MUX_ACLK_300_GSCL_SEL 0x1
#define MUX_ACLK_300_GSCL_MID_SEL 0x0
#define MUX_ACLK_400_SEL 0x0
#define MUX_ACLK_333_SEL 0x0
#define MUX_ACLK_300_DISP1_SEL 0x1
#define MUX_ACLK_300_DISP1_MID_SEL 0x0
#define MUX_ACLK_200_SEL 0x0
#define MUX_ACLK_166_SEL 0x0
#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
| (MUX_ACLK_400_SEL << 20) \
| (MUX_ACLK_333_SEL << 16) \
| (MUX_ACLK_300_DISP1_SEL << 15) \
| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
| (MUX_ACLK_200_SEL << 12) \
| (MUX_ACLK_166_SEL << 8))
/* CLK_SRC_TOP1 */
#define MUX_ACLK_400_ISP_SEL 0x0
#define MUX_ACLK_400_IOP_SEL 0x0
#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \
|(MUX_ACLK_400_IOP_SEL << 20) \
|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
/* CLK_SRC_TOP2 */
#define MUX_BPLL_USER_SEL 0x1
#define MUX_MPLL_USER_SEL 0x1
#define MUX_VPLL_SEL 0x0
#define MUX_EPLL_SEL 0x0
#define MUX_CPLL_SEL 0x0
#define VPLLSRC_SEL 0x0
#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \
| (MUX_MPLL_USER_SEL << 20) \
| (MUX_VPLL_SEL << 16) \
| (MUX_EPLL_SEL << 12) \
| (MUX_CPLL_SEL << 8) \
| (VPLLSRC_SEL))
/* CLK_SRC_TOP3 */
#define MUX_ACLK_333_SUB_SEL 0x1
#define MUX_ACLK_400_SUB_SEL 0x1
#define MUX_ACLK_266_ISP_SUB_SEL 0x1
#define MUX_ACLK_266_GPS_SUB_SEL 0x1
#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
| (MUX_ACLK_400_SUB_SEL << 20) \
| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
/* CLK_DIV_TOP0 */
#define ACLK_300_RATIO 0x0
#define ACLK_400_RATIO 0x3
#define ACLK_333_RATIO 0x2
#define ACLK_266_RATIO 0x2
#define ACLK_200_RATIO 0x3
#define ACLK_166_RATIO 0x5
#define ACLK_133_RATIO 0x1
#define ACLK_66_RATIO 0x5
#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \
| (ACLK_400_RATIO << 24) \
| (ACLK_333_RATIO << 20) \
| (ACLK_266_RATIO << 16) \
| (ACLK_200_RATIO << 12) \
| (ACLK_166_RATIO << 8) \
| (ACLK_133_RATIO << 4) \
| (ACLK_66_RATIO))
/* CLK_DIV_TOP1 */
#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
#define ACLK_66_PRE_RATIO 0x1
#define ACLK_400_ISP_RATIO 0x1
#define ACLK_400_IOP_RATIO 0x1
#define ACLK_300_GSCL_RATIO 0x0
#define ACLK_266_GPS_RATIO 0x7
#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
| (ACLK_66_PRE_RATIO << 24) \
| (ACLK_400_ISP_RATIO << 20) \
| (ACLK_400_IOP_RATIO << 16) \
| (ACLK_300_GSCL_RATIO << 12) \
| (ACLK_266_GPS_RATIO << 8))
/* APLL_LOCK */
#define APLL_LOCK_VAL (0x3E8)
/* MPLL_LOCK */
#define MPLL_LOCK_VAL (0x2F1)
/* CPLL_LOCK */
#define CPLL_LOCK_VAL (0x3E8)
/* EPLL_LOCK */
#define EPLL_LOCK_VAL (0x2321)
/* VPLL_LOCK */
#define VPLL_LOCK_VAL (0x2321)
/* BPLL_LOCK */
#define BPLL_LOCK_VAL (0x3E8)
/* CLK_SRC_PERIC0 */
/* SRC_CLOCK = SCLK_MPLL */
#define PWM_SEL 0
#define UART4_SEL 6
#define UART3_SEL 6
#define UART2_SEL 6
#define UART1_SEL 6
#define UART0_SEL 6
#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
| (UART4_SEL << 16) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL << 0))
#define CLK_SRC_FSYS_VAL 0x66666
#define CLK_DIV_FSYS0_VAL 0x0BB00000
#define CLK_DIV_FSYS1_VAL 0x000f000f
#define CLK_DIV_FSYS2_VAL 0x020f020f
#define CLK_DIV_FSYS3_VAL 0x000f
/* CLK_DIV_PERIC0 */
#define UART5_RATIO 8
#define UART4_RATIO 8
#define UART3_RATIO 8
#define UART2_RATIO 8
#define UART1_RATIO 8
#define UART0_RATIO 8
#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \
| (UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_DIV_PERIC3 */
#define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
/* CLK_SRC_LEX */
#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */
#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */
#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10
/* SCLK_SRC_ISP */
#define SCLK_SRC_ISP_VAL 0x600
/* CLK_DIV_ISP0 */
#define CLK_DIV_ISP0_VAL 0x31
/* CLK_DIV_ISP1 */
#define CLK_DIV_ISP1_VAL 0x0
/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1
#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
/*
* TZPC Register Value :
* R0SIZE: 0x0 : Size of secured ram
*/
#define R0SIZE 0x0
/*
* TZPC Decode Protection Register Value :
* DECPROTXSET: 0xFF : Set Decode region to non-secure
*/
#define DECPROTXSET 0xFF
/* DMC Init */
#define SET 1
#define RESET 0
/* (Memory Interleaving Size = 1 << IV_SIZE) */
#define CONFIG_IV_SIZE 0x07
#define PHY_RESET_VAL (0 << 0)
/*ZQ Configurations */
#define PHY_CON16_RESET_VAL 0x08000304
#define ZQ_MODE_DDS_VAL (0x5 << 24)
#define ZQ_MODE_TERM_VAL (0x5 << 21)
#define SET_ZQ_MODE_DDS_VAL(x) (x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
#define SET_ZQ_MODE_TERM_VAL(x) (x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
#define ZQ_MODE_NOTERM (1 << 19)
#define ZQ_CLK_DIV_EN (1 << 18)
#define ZQ_MANUAL_STR (1 << 1)
/* Channel and Chip Selection */
#define CONFIG_DMC_CHANNELS 2
#define CONFIG_CHIPS_PER_CHANNEL 2
#define SET_CMD_CHANNEL(x, y) (x = (x & ~(1 << 28)) | y << 28)
#define SET_CMD_CHIP(x, y) (x = (x & ~(1 << 20)) | y << 20)
/* Diret Command */
#define DIRECT_CMD_NOP 0x07000000
#define DIRECT_CMD_MRS1 0x00071C00
#define DIRECT_CMD_MRS2 0x00010BFC
#define DIRECT_CMD_MRS3 0x00000708
#define DIRECT_CMD_MRS4 0x00000818
#define DIRECT_CMD_PALL 0x01000000
/* DLL Resync */
#define FP_RSYNC (1 << 3)
#define CONFIG_CTRL_DLL_ON(x, y) (x = (x & ~(1 << 5)) | y << 5)
#define CONFIG_CTRL_START(x, y) (x = (x & ~(1 << 6)) | y << 6)
#define SET_CTRL_FORCE_VAL(x, y) (x = (x & ~(0x7F << 8)) | y << 8)
/* RDLVL */
#define PHY_CON0_RESET_VAL 0x17023240
#define DDR_MODE_LPDDR2 0x2
#define BYTE_RDLVL_EN (1 << 13)
#define CTRL_ATGATE (1 << 6)
#define SET_CTRL_DDR_MODE(x, y) (x = (x & ~(0x3 << 11)) | y << 11)
#define PHY_CON1_RESET_VAL 0x9210100
#define RDLVL_RDDATAPADJ 0x1
#define SET_RDLVL_RDDATAPADJ ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
| RDLVL_RDDATAPADJ << 0)
#define PHY_CON2_RESET_VAL 0x00010004
#define RDLVL_EN (1 << 25)
#define RDDSKEW_CLEAR (1 << 13)
#define CTRL_RDLVL_DATA_EN (1 << 1)
#define LPDDR2_ADDR 0x00000208
#define DMC_MEMCONFIG0_VAL 0x00001323
#define DMC_MEMCONFIG1_VAL 0x00001323
#define DMC_MEMBASECONFIG0_VAL 0x00400780
#define DMC_MEMBASECONFIG1_VAL 0x00800780
#define DMC_MEMCONTROL_VAL 0x00212500
#define DMC_PRECHCONFIG_VAL 0xFF000000
#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
#define DMC_TIMINGREF_VAL 0x0000005D
#define DMC_TIMINGROW_VAL 0x2336544C
#define DMC_TIMINGDATA_VAL 0x24202408
#define DMC_TIMINGPOWER_VAL 0x38260235
#define CTRL_BSTLEN 0x04
#define CTRL_RDLAT 0x08
#define PHY_CON42_VAL (CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
/* DQS, DQ, DEBUG offsets */
#define SET_DQS_OFFSET_VAL 0x7F7F7F7F
#define SET_DQ_OFFSET_VAL 0x7F7F7F7F
#define SET_DEBUG_OFFSET_VAL 0x7F
#define RESET_DQS_OFFSET_VAL 0x08080808
#define RESET_DQ_OFFSET_VAL 0x08080808
#define RESET_DEBUG_OFFSET_VAL 0x8
#define CTRL_PULLD_DQ (0x0F << 8)
#define CTRL_PULLD_DQS (0x0F << 0)
#define DFI_INIT_START (1 << 28)
#define CLK_STOP_EN (1 << 0)
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
#define AREF_EN (1 << 5)
void sdelay(unsigned long);
void mem_ctrl_init(void);
void system_clock_init(void);
void tzpc_init(void);
#endif

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common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/smdk5250.c Normal file
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/*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SMC911X
static int smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
int err;
/* Ethernet needs data bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
| SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
| SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
| SROMC_BC_PMC(0x01);
/* Select and configure the SROMC bank */
err = exynos_pinmux_config(PERIPH_ID_SROMC,
CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
if (err) {
debug("SROMC not configured\n");
return err;
}
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
return 0;
}
#endif
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
PHYS_SDRAM_3_SIZE);
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
PHYS_SDRAM_4_SIZE);
gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
PHYS_SDRAM_5_SIZE);
gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
PHYS_SDRAM_6_SIZE);
gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
PHYS_SDRAM_7_SIZE);
gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
PHYS_SDRAM_8_SIZE);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
if (smc9115_pre_init())
return -1;
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: SMDK5250\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err) {
debug("SDMMC2 not configured\n");
return err;
}
err = s5p_mmc_init(2, 4);
return err;
}
#endif
static int board_uart_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
if (err) {
debug("UART0 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
if (err) {
debug("UART1 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
if (err) {
debug("UART2 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
if (err) {
debug("UART3 not configured\n");
return err;
}
return 0;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
return board_uart_init();
}
#endif

48
common/package/utils/sysupgrade-helper/src/board/samsung/smdk5250/tzpc_init.c Normal file
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/*
* Lowlevel setup for SMDK5250 board based on S5PC520
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/arch/tzpc.h>
#include"setup.h"
/* Setting TZPC[TrustZone Protection Controller] */
void tzpc_init(void)
{
struct exynos_tzpc *tzpc;
unsigned int addr;
for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
tzpc = (struct exynos_tzpc *)addr;
if (addr == TZPC0_BASE)
writel(R0SIZE, &tzpc->r0size);
writel(DECPROTXSET, &tzpc->decprot0set);
writel(DECPROTXSET, &tzpc->decprot1set);
if (addr != TZPC9_BASE) {
writel(DECPROTXSET, &tzpc->decprot2set);
writel(DECPROTXSET, &tzpc->decprot3set);
}
}
}

5
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/.gitignore vendored Normal file
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#
# Generated files
#
/config.tmp

48
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/Makefile Normal file
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#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := smdk6400.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
$(call cmd_link_o_target, $(SOBJS) $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

30
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/config.mk Normal file
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#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
#
# see http://www.samsung.com/ for more information on SAMSUNG
# On SMDK6400 we use the 64 MB SDRAM bank at
#
# 0x50000000 to 0x58000000
#
# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
#
# we load ourselves to 0x57e00000 without MMU
# with MMU, load address is changed to 0xc7e00000
#
# download area is 0x5000c000
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef CONFIG_NAND_SPL
CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
else
CONFIG_SYS_TEXT_BASE = 0
endif

323
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/lowlevel_init.S Normal file
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/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/s3c6400.h>
#ifdef CONFIG_SERIAL1
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
#elif defined(CONFIG_SERIAL2)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
#else
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
#endif
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r12, lr
/* LED on only #8 */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x55540000
str r1, [r0, #GPNCON_OFFSET]
ldr r1, =0x55555555
str r1, [r0, #GPNPUD_OFFSET]
ldr r1, =0xf000
str r1, [r0, #GPNDAT_OFFSET]
/* Disable Watchdog */
ldr r0, =0x7e000000 @0x7e004000
orr r0, r0, #0x4000
mov r1, #0
str r1, [r0]
/* External interrupt pending clear */
ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
ldr r1, [r0]
str r1, [r0]
ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
/* Disable all interrupts (VIC0 and VIC1) */
mvn r3, #0x0
str r3, [r0, #oINTMSK]
str r3, [r1, #oINTMSK]
/* Set all interrupts as IRQ */
mov r3, #0x0
str r3, [r0, #oINTMOD]
str r3, [r1, #oINTMOD]
/* Pending Interrupt Clear */
mov r3, #0x0
str r3, [r0, #oVECTADDR]
str r3, [r1, #oVECTADDR]
/* init system clock */
bl system_clock_init
#ifndef CONFIG_NAND_SPL
/* for UART */
bl uart_asm_init
#endif
#ifdef CONFIG_BOOT_NAND
/* simple init for NAND */
bl nand_asm_init
#endif
/* Memory subsystem address 0x7e00f120 */
ldr r0, =ELFIN_MEM_SYS_CFG
/* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
mov r1, #S3C64XX_MEM_SYS_CFG_NAND
str r1, [r0]
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
beq wakeup_reset
1:
mov lr, r12
mov pc, lr
wakeup_reset:
/* Clear wakeup status register */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
ldr r1, [r0]
str r1, [r0]
/* LED test */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x3000
str r1, [r0, #GPNDAT_OFFSET]
/* Load return address and jump to kernel */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
/* r1 = physical address of s3c6400_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel (sleep-s3c6400.S) */
mov pc, r1
nop
nop
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
#ifdef CONFIG_SYNC_MODE
ldr r1, [r0, #OTHERS_OFFSET]
mov r2, #0x40
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
nop
nop
nop
nop
nop
ldr r2, =0x80
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
check_syncack:
ldr r1, [r0, #OTHERS_OFFSET]
ldr r2, =0xf00
and r1, r1, r2
cmp r1, #0xf00
bne check_syncack
#else /* ASYNC Mode */
nop
nop
nop
nop
nop
/*
* This was unconditional in original Samsung sources, but it doesn't
* seem to make much sense on S3C6400.
*/
#ifndef CONFIG_S3C6400
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0xC0
orr r1, r1, #0x40
str r1, [r0, #OTHERS_OFFSET]
wait_for_async:
ldr r1, [r0, #OTHERS_OFFSET]
and r1, r1, #0xf00
cmp r1, #0x0
bne wait_for_async
#endif
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0x40
str r1, [r0, #OTHERS_OFFSET]
#endif
mov r1, #0xff00
orr r1, r1, #0xff
str r1, [r0, #APLL_LOCK_OFFSET]
str r1, [r0, #MPLL_LOCK_OFFSET]
/* Set Clock Divider */
ldr r1, [r0, #CLK_DIV0_OFFSET]
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =CLK_DIV_VAL
orr r1, r1, r2
str r1, [r0, #CLK_DIV0_OFFSET]
ldr r1, =APLL_VAL
str r1, [r0, #APLL_CON_OFFSET]
ldr r1, =MPLL_VAL
str r1, [r0, #MPLL_CON_OFFSET]
/* FOUT of EPLL is 96MHz */
ldr r1, =0x200203
str r1, [r0, #EPLL_CON0_OFFSET]
ldr r1, =0x0
str r1, [r0, #EPLL_CON1_OFFSET]
/* APLL, MPLL, EPLL select to Fout */
ldr r1, [r0, #CLK_SRC_OFFSET]
orr r1, r1, #0x7
str r1, [r0, #CLK_SRC_OFFSET]
/* wait at least 200us to stablize all clock */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
/* Synchronization for VIC port */
#if defined(CONFIG_SYNC_MODE)
ldr r1, [r0, #OTHERS_OFFSET]
orr r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
#elif !defined(CONFIG_S3C6400)
/* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
#endif
mov pc, lr
#ifndef CONFIG_NAND_SPL
/*
* uart_asm_init: Initialize UART's pins
*/
uart_asm_init:
/* set GPIO to enable UART */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x220022
str r1, [r0, #GPACON_OFFSET]
mov pc, lr
#endif
#ifdef CONFIG_BOOT_NAND
/*
* NAND Interface init for SMDK6400
*/
nand_asm_init:
ldr r0, =ELFIN_NAND_BASE
ldr r1, [r0, #NFCONF_OFFSET]
orr r1, r1, #0x70
orr r1, r1, #0x7700
str r1, [r0, #NFCONF_OFFSET]
ldr r1, [r0, #NFCONT_OFFSET]
orr r1, r1, #0x07
str r1, [r0, #NFCONT_OFFSET]
mov pc, lr
#endif
#ifdef CONFIG_ENABLE_MMU
/*
* MMU Table for SMDK6400
*/
/* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b
.word (\base << 20) | (\ap << 10) | \
(\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
.endm
.section .mmudata, "a"
.align 14
/* the following alignment creates the mmu table at address 0x4000. */
.globl mmu_table
mmu_table:
.set __base, 0
/* 1:1 mapping for debugging */
.rept 0xA00
FL_SECTION_ENTRY __base, 3, 0, 0, 0
.set __base, __base + 1
.endr
/* access is not allowed. */
.rept 0xC00 - 0xA00
.word 0x00000000
.endr
/* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
.set __base, 0x500
.rept 0xC80 - 0xC00
FL_SECTION_ENTRY __base, 3, 0, 1, 1
.set __base, __base + 1
.endr
/* access is not allowed. */
.rept 0x1000 - 0xc80
.word 0x00000000
.endr
#endif

134
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/smdk6400.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/s3c6400.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
#define CS8900_Tacs 0x0 /* 0clk address set-up */
#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
#define CS8900_Tacc 0xE /* 14clk access cycle */
#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
#define CS8900_Tah 0x4 /* 4clk address holding time */
#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
static inline void delay(unsigned long loops)
{
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
"bne 1b"
: "=r" (loops) : "0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
static void cs8900_pre_init(void)
{
SROM_BW_REG &= ~(0xf << 4);
SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
(CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
(CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
}
int board_init(void)
{
cs8900_pre_init();
/* NOR-flash in SROM0 */
/* Enable WAIT */
SROM_BW_REG |= 4 | 8 | 1;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("Board: SMDK6400\n");
return 0;
}
#endif
#ifdef CONFIG_ENABLE_MMU
ulong virt_to_phy_smdk6400(ulong addr)
{
if ((0xc0000000 <= addr) && (addr < 0xc8000000))
return addr - 0xc0000000 + 0x50000000;
else
printf("do not support this address : %08lx\n", addr);
return addr;
}
#endif
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
} else
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif

37
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/smdk6400_nand_spl.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void board_init_f(unsigned long bootflag)
{
relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
CONFIG_SYS_TEXT_BASE);
}

84
common/package/utils/sysupgrade-helper/src/board/samsung/smdk6400/u-boot-nand.lds Normal file
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/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm1176/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.mmudata : { *(.mmudata) }
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
. = ALIGN(4);
__bss_end__ = .;
}
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

49
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/Makefile Normal file
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#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := smdkc100.o
COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
$(call cmd_link_o_target, $(SOBJS) $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

16
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/config.mk Normal file
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#
# Copyright (C) 2008 # Samsung Elecgtronics
# Kyungmin Park <kyungmin.park@samsung.com>
#
# On S5PC100 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x38000000 to 0x40000000 (128MiB)
#
# On S5PC110 we use the 128 MiB OneDRAM bank at
#
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x48000000 (128MiB)
#
CONFIG_SYS_TEXT_BASE = 0x34800000

215
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/lowlevel_init.S Normal file
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/*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include <asm/arch/power.h>
/*
* Register usages:
*
* r5 has zero always
*/
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r9, lr
/* r5 has always zero */
mov r5, #0
ldr r8, =S5PC100_GPIO_BASE
/* Disable Watchdog */
ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
orr r0, r0, #0x0
str r5, [r0]
#ifndef CONFIG_ONENAND_IPL
/* setting SRAM */
ldr r0, =S5PC100_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
#endif
/* S5PC100 has 3 groups of interrupt sources */
ldr r0, =S5PC100_VIC0_BASE @0xE4000000
ldr r1, =S5PC100_VIC1_BASE @0xE4000000
ldr r2, =S5PC100_VIC2_BASE @0xE4000000
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
str r3, [r0, #0x14] @INTENCLEAR
str r3, [r1, #0x14] @INTENCLEAR
str r3, [r2, #0x14] @INTENCLEAR
#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @INTSELECT
str r5, [r1, #0xc] @INTSELECT
str r5, [r2, #0xc] @INTSELECT
/* Pending Interrupt Clear */
str r5, [r0, #0xf00] @INTADDRESS
str r5, [r1, #0xf00] @INTADDRESS
str r5, [r2, #0xf00] @INTADDRESS
#endif
#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
/* for TZPC */
bl tzpc_asm_init
#endif
#ifdef CONFIG_ONENAND_IPL
/* init system clock */
bl system_clock_init
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =S5PC100_RST_STAT
ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
beq wakeup_reset
#endif
1:
mov lr, r9
mov pc, lr
#ifdef CONFIG_ONENAND_IPL
wakeup_reset:
/* Clear wakeup status register */
ldr r0, =S5PC100_WAKEUP_STAT
ldr r1, [r0]
str r1, [r0]
/* Load return address and jump to kernel */
ldr r0, =S5PC100_INFORM0
/* r1 = physical address of s5pc100_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel (sleep.S) */
mov pc, r1
nop
nop
#endif
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x00011110
str r1, [r8, #0x304]
ldr r1, =0x1
str r1, [r8, #0x308]
ldr r1, =0x00011301
str r1, [r8, #0x300]
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r8, #0x000] @ APLL_LOCK
str r1, [r8, #0x004] @ MPLL_LOCK
str r1, [r8, #0x008] @ EPLL_LOCK
str r1, [r8, #0x00C] @ HPLL_LOCK
/* APLL_CON */
ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
str r1, [r8, #0x100]
/* MPLL_CON */
ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
str r1, [r8, #0x104]
/* EPLL_CON */
ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
str r1, [r8, #0x108]
/* HPLL_CON */
ldr r1, =0x80600603
str r1, [r8, #0x10C]
/* Set Source Clock */
ldr r1, =0x1111 @ A, M, E, HPLL Muxing
str r1, [r8, #0x200] @ CLK_SRC0
ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
str r1, [r8, #0x204] @ CLK_SRC1
ldr r1, =0x9000 @ ARMCLK/4
str r1, [r8, #0x400] @ CLK_OUT
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
bne 1b
mov pc, lr
#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
uart_asm_init:
mov r0, r8
ldr r1, =0x22222222
str r1, [r0, #0x0] @ GPA0_CON
ldr r1, =0x00022222
str r1, [r0, #0x20] @ GPA1_CON
mov pc, lr
/*
* tzpc_asm_init: Initialize TZPC
*/
tzpc_asm_init:
ldr r0, =0xE3800000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x804]
str r1, [r0, #0x810]
ldr r0, =0xE2800000
str r1, [r0, #0x804]
str r1, [r0, #0x810]
str r1, [r0, #0x81C]
ldr r0, =0xE2900000
str r1, [r0, #0x804]
str r1, [r0, #0x810]
mov pc, lr
#endif

197
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/mem_setup.S Normal file
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/*
* Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
*
* Copyright (C) 2009 Samsung Electrnoics
* Inki Dae <inki.dae@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
/* DLL parameter setting */
ldr r1, =0x50101000
str r1, [r6, #0x018] @ PHYCONTROL0
ldr r1, =0xf4
str r1, [r6, #0x01C] @ PHYCONTROL1
ldr r1, =0x0
str r1, [r6, #0x020] @ PHYCONTROL2
/* DLL on */
ldr r1, =0x50101002
str r1, [r6, #0x018] @ PHYCONTROL0
/* DLL start */
ldr r1, =0x50101003
str r1, [r6, #0x018] @ PHYCONTROL0
/* Force value locking for DLL off */
str r1, [r6, #0x018] @ PHYCONTROL0
/* DLL off */
ldr r1, =0x50101001
str r1, [r6, #0x018] @ PHYCONTROL0
/* auto refresh off */
ldr r1, =0xff001010
str r1, [r6, #0x000] @ CONCONTROL
/*
* Burst Length 4, 2 chips, 32-bit, LPDDR
* OFF: dynamic self refresh, force precharge, dynamic power down off
*/
ldr r1, =0x00212100
str r1, [r6, #0x004] @ MEMCONTROL
/*
* Note:
* If Bank0 has OneDRAM we place it at 0x2800'0000
* So finally Bank1 should address start at at 0x2000'0000
*/
mov r4, #0x0
swap_memory:
/*
* Bank0
* 0x30 -> 0x30000000
* 0xf8 -> 0x37FFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
ldr r1, =0x30f80222
/* if r4 is 1, swap the bank */
cmp r4, #0x1
orreq r1, r1, #0x08000000
str r1, [r6, #0x008] @ MEMCONFIG0
/*
* Bank1
* 0x38 -> 0x38000000
* 0xf8 -> 0x3fFFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
ldr r1, =0x38f80222
/* if r4 is 1, swap the bank */
cmp r4, #0x1
biceq r1, r1, #0x08000000
str r1, [r6, #0x00c] @ MEMCONFIG1
ldr r1, =0x20000000
str r1, [r6, #0x014] @ PRECHCONFIG
/*
* FIXME: Please verify these values
* 7.8us * 166MHz %LE %LONG1294(0x50E)
* 7.8us * 133MHz %LE %LONG1038(0x40E),
* 7.8us * 100MHz %LE %LONG780(0x30C),
* 7.8us * 20MHz %LE %LONG156(0x9C),
* 7.8us * 10MHz %LE %LONG78(0x4E)
*/
ldr r1, =0x0000050e
str r1, [r6, #0x030] @ TIMINGAREF
/* 166 MHz */
ldr r1, =0x0c233287
str r1, [r6, #0x034] @ TIMINGROW
/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
ldr r1, =0x32330303
str r1, [r6, #0x038] @ TIMINGDATA
/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
ldr r1, =0x04141433
str r1, [r6, #0x03C] @ TIMINGPOWER
/* chip0 Deselect */
ldr r1, =0x07000000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip0 PALL */
ldr r1, =0x01000000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip0 REFA */
ldr r1, =0x05000000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip0 REFA */
str r1, [r6, #0x010] @ DIRECTCMD
/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
ldr r1, =0x00000032
str r1, [r6, #0x010] @ DIRECTCMD
/* chip1 Deselect */
ldr r1, =0x07100000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip1 PALL */
ldr r1, =0x01100000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip1 REFA */
ldr r1, =0x05100000
str r1, [r6, #0x010] @ DIRECTCMD
/* chip1 REFA */
str r1, [r6, #0x010] @ DIRECTCMD
/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
ldr r1, =0x00100032
str r1, [r6, #0x010] @ DIRECTCMD
/* auto refresh on */
ldr r1, =0xff002030
str r1, [r6, #0x000] @ CONCONTROL
/* PwrdnConfig */
ldr r1, =0x00100002
str r1, [r6, #0x028] @ PWRDNCONFIG
/* BL%LE %LONG */
ldr r1, =0xff212100
str r1, [r6, #0x004] @ MEMCONTROL
/* Try to test memory area */
cmp r4, #0x1
beq 1f
mov r4, #0x1
ldr r1, =0x37ffff00
str r4, [r1]
str r4, [r1, #0x4] @ dummy write
ldr r0, [r1]
cmp r0, r4
bne swap_memory
1:
mov pc, lr
.ltorg

84
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/onenand.c Normal file
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/*
* Copyright (C) 2008-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/samsung_onenand.h>
#include <onenand_uboot.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
void onenand_board_init(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
struct s5pc100_clock *clk =
(struct s5pc100_clock *)samsung_get_base_clock();
struct samsung_onenand *onenand;
int value;
this->base = (void *)S5PC100_ONENAND_BASE;
onenand = (struct samsung_onenand *)this->base;
/* D0 Domain memory clock gating */
value = readl(&clk->gate_d01);
value &= ~(1 << 2); /* CLK_ONENANDC */
value |= (1 << 2);
writel(value, &clk->gate_d01);
value = readl(&clk->src0);
value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
writel(value, &clk->src0);
value = readl(&clk->div1);
value &= ~(3 << 16); /* PCLKD1_RATIO */
value |= (1 << 16);
writel(value, &clk->div1);
writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
while (!(readl(&onenand->int_err_stat) & RST_CMP))
continue;
writel(RST_CMP, &onenand->int_err_ack);
/*
* Access_Clock [2:0]
* 166 MHz, 134 Mhz : 3
* 100 Mhz, 60 Mhz : 2
*/
writel(0x3, &onenand->acc_clock);
writel(INT_ERR_ALL, &onenand->int_err_mask);
writel(1 << 0, &onenand->int_pin_en); /* Enable */
value = readl(&onenand->int_err_mask);
value &= ~RDY_ACT;
writel(value, &onenand->int_err_mask);
s3c_onenand_init(mtd);
}

94
common/package/utils/sysupgrade-helper/src/board/samsung/smdkc100/smdkc100.c Normal file
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/*
* Copyright (C) 2008-2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sromc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
*/
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
struct s5pc100_gpio *const gpio =
(struct s5pc100_gpio *)samsung_get_base_gpio();
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)
{
smc9115_pre_init();
gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("Board:\tSMDKC100\n");
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

63
common/package/utils/sysupgrade-helper/src/board/samsung/smdkv310/Makefile Normal file
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#
# Copyright (C) 2011 Samsung Electronics
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
SOBJS := mem_setup.o
SOBJS += lowlevel_init.o
ifndef CONFIG_SPL_BUILD
COBJS += smdkv310.o
endif
ifdef CONFIG_SPL_BUILD
COBJS += mmc_boot.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL := $(obj).depend $(LIB)
ifdef CONFIG_SPL_BUILD
ALL += $(OBJTREE)/tools/mk$(BOARD)spl
endif
all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
ifdef CONFIG_SPL_BUILD
$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
endif
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

470
common/package/utils/sysupgrade-helper/src/board/samsung/smdkv310/lowlevel_init.S Normal file
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/*
* Lowlevel setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has GPIO part1 base 0x11400000
* r6 has GPIO part2 base 0x11000000
*/
#define MEM_DLLl_ON
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
push {lr}
/* r5 has always zero */
mov r5, #0
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
ldr r1, [r0]
/* AFTR wakeup reset */
ldr r2, =S5P_CHECK_DIDLE
cmp r1, r2
beq exit_wakeup
/* Sleep wakeup reset */
ldr r2, =S5P_CHECK_SLEEP
cmp r1, r2
beq wakeup_reset
/*
* If U-boot is already running in ram, no need to relocate U-Boot.
* Memory controller must be configured before relocating U-Boot
* in ram.
*/
ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
bic r1, pc, r0 /* pc <- current addr of code */
/* r1 <- unmasked bits of pc */
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
cmp r1, r2 /* compare r1, r2 */
beq 1f /* r0 == r1 then skip sdram init */
/* init system clock */
bl system_clock_init
/* Memory initialize */
bl mem_ctrl_asm_init
1:
/* for UART */
bl uart_asm_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
bl tzpc_init
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
/* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
mov pc, r1
nop
nop
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
push {lr}
ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
ldr r2, =0x14200 @CLK_SRC_CPU
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
2: subs r1, r1, #1
bne 2b
ldr r1, =0x00
ldr r2, =0x0C210 @CLK_SRC_TOP0
str r1, [r0, r2]
ldr r1, =0x00
ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
str r1, [r0, r2]
/* DMC */
ldr r1, =0x00
ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
str r1, [r0, r2]
/*CLK_SRC_LEFTBUS */
ldr r1, =0x00
ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
str r1, [r0, r2]
/*CLK_SRC_RIGHTBUS */
ldr r1, =0x00
ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
str r1, [r0, r2]
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
ldr r1, =0x066666
ldr r2, =0x0C240 @ CLK_SRC_FSYS
str r1, [r0, r2]
/* UART[0:4], PWM: SCLKMPLL(6) */
ldr r1, =0x06666666
ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1
bne 3b
/*
* CLK_DIV_CPU0:
*
* PCLK_DBG_RATIO[20] 0x1
* ATB_RATIO[16] 0x3
* PERIPH_RATIO[12] 0x3
* COREM1_RATIO[8] 0x7
* COREM0_RATIO[4] 0x3
*/
ldr r1, =0x0133730
ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
str r1, [r0, r2]
/* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
ldr r1, =0x03
ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_DMC0:
*
* CORE_TIMERS_RATIO[28] 0x1
* COPY2_RATIO[24] 0x3
* DMCP_RATIO[20] 0x1
* DMCD_RATIO[16] 0x1
* DMC_RATIO[12] 0x1
* DPHY_RATIO[8] 0x1
* ACP_PCLK_RATIO[4] 0x1
* ACP_RATIO[0] 0x3
*/
ldr r1, =0x13111113
ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_DMC1:
*
* DPM_RATIO[24] 0x1
* DVSEM_RATIO[16] 0x1
* PWI_RATIO[8] 0x1
*/
ldr r1, =0x01010100
ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_LEFRBUS:
*
* GPL_RATIO[4] 0x1
* GDL_RATIO[0] 0x3
*/
ldr r1, =0x013
ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_RIGHTBUS:
*
* GPR_RATIO[4] 0x1
* GDR_RATIO[0] 0x3
*/
ldr r1, =0x013
ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_TOP:
*
* ONENAND_RATIO[16] 0x0
* ACLK_133_RATIO[12] 0x5
* ACLK_160_RATIO[8] 0x4
* ACLK_100_RATIO[4] 0x7
* ACLK_200_RATIO[0] 0x3
*/
ldr r1, =0x05473
ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
str r1, [r0, r2]
/* MMC[0:1] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C544 @ CLK_DIV_FSYS1
str r1, [r0, r2]
/* MMC[2:3] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C548 @ CLK_DIV_FSYS2
str r1, [r0, r2]
/* MMC4 */
ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C54C @ CLK_DIV_FSYS3
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
4: subs r1, r1, #1
bne 4b
/*
* CLK_DIV_PERIL0:
*
* UART5_RATIO[20] 8
* UART4_RATIO[16] 8
* UART3_RATIO[12] 8
* UART2_RATIO[8] 8
* UART1_RATIO[4] 8
* UART0_RATIO[0] 8
*/
ldr r1, =0x774777
ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
str r1, [r0, r2]
/* SLIMBUS: ???, PWM */
ldr r1, =0x8
ldr r2, =0x0C55C @ CLK_DIV_PERIL3
str r1, [r0, r2]
/* Set PLL locktime */
ldr r1, =0x01C20
ldr r2, =0x014000 @APLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x014008 @MPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
str r1, [r0, r2]
/*
* APLL_CON1:
*
* APLL_AFC_ENB[31] 0x1
* APLL_AFC[0] 0xC
*/
ldr r1, =0x8000000C
ldr r2, =0x014104 @APLL_CON1_OFFSET
str r1, [r0, r2]
/*
* APLL_CON0:
*
* APLL_MDIV[16] 0xFA
* APLL_PDIV[8] 0x6
* APLL_SDIV[0] 0x1
*/
ldr r1, =0x80FA0601
ldr r2, =0x014100 @APLL_CON0_OFFSET
str r1, [r0, r2]
/*
* MPLL_CON1:
*
* MPLL_AFC_ENB[31] 0x1
* MPLL_AFC[0] 0x1C
*/
ldr r1, =0x0000001C
ldr r2, =0x01410C @MPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* MPLL_CON0:
*
* MPLL_MDIV[16] 0xC8
* MPLL_PDIV[8] 0x6
* MPLL_SDIV[0] 0x1
*/
ldr r1, =0x80C80601
ldr r2, =0x014108 @MPLL_CON0_OFFSET
str r1, [r0, r2]
/* EPLL */
ldr r1, =0x0
ldr r2, =0x0C114 @EPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* EPLL_CON0:
*
* EPLL_MDIV[16] 0x30
* EPLL_PDIV[8] 0x3
* EPLL_SDIV[0] 0x2
*/
ldr r1, =0x80300302
ldr r2, =0x0C110 @EPLL_CON0_OFFSET
str r1, [r0, r2]
/*
* VPLL_CON1:
*
* VPLL_MRR[24] 0x11
* VPLL_MFR[16] 0x0
* VPLL_K[0] 0x400
*/
ldr r1, =0x11000400
ldr r2, =0x0C124 @VPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* VPLL_CON0:
*
* VPLL_MDIV[16] 0x35
* VPLL_PDIV[8] 0x3
* VPLL_SDIV[0] 0x2
*/
ldr r1, =0x80350302
ldr r2, =0x0C120 @VPLL_CON0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x30000
3: subs r1, r1, #1
bne 3b
pop {pc}
/*
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
* void uart_asm_init(void)
*/
.globl uart_asm_init
uart_asm_init:
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =0x22222222
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00222222
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
ldr r0, =EXYNOS4_UART_BASE
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =0x3C5
str r1, [r0, #0x4]
ldr r1, =0x111
str r1, [r0, #0x8]
ldr r1, =0x3
str r1, [r0, #0x0]
ldr r1, =0x35
str r1, [r0, #0x28]
ldr r1, =0x4
str r1, [r0, #0x2c]
mov pc, lr
nop
nop
nop
/* Setting TZPC[TrustZone Protection Controller] */
tzpc_init:
ldr r0, =0x10110000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10120000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10130000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10140000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10150000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10160000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
mov pc, lr

365
common/package/utils/sysupgrade-helper/src/board/samsung/smdkv310/mem_setup.S Normal file
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/*
* Memory setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#define SET_MIU
#define MEM_DLL
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
/*
* Async bridge configuration at CPU_core:
* 1: half_sync
* 0: full_sync
*/
ldr r0, =0x10010350
mov r1, #1
str r1, [r0]
#ifdef SET_MIU
ldr r0, =EXYNOS4_MIU_BASE @0x10600000
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
ldr r1, =0x0000000c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
ldr r1, =0x40000000
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
ldr r1, =0x00000001
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#ifdef CONFIG_MIU_2BIT_INTERLEAVED
ldr r1, =0x2000150c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
ldr r1, =0x40000000
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
ldr r1, =0x00000001
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40000000
str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
ldr r1, =0x7fffffff
str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
ldr r1, =0x80000000
str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
ldr r1, =0x00000006
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#endif
/* DREX0 */
ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xE3855703
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x71101008
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x7110100A
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x7110100B
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x00000000
str r1, [r0, #0x20] @DMC_PHYCONTROL2
ldr r1, =0x0FFF301a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r1, =0x00312640
str r1, [r0, #0x04] @DMC_MEMCONTROL]
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x60e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
ldr r1, =0x20e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x40e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#endif
ldr r1, =0xff000000
str r1, [r0, #0x14] @DMC_PRECHCONFIG
ldr r1, =0x000000BC
str r1, [r0, #0x30] @DMC_TIMINGAREF
#ifdef DRAM_CLK_330
ldr r1, =0x3545548d
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x45430506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x4439033c
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
#ifdef DRAM_CLK_400
ldr r1, =0x4046654f
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x56500506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x5444033d
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
ldr r1, =0x07000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
ldr r1, =0x00020000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00030000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00010002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00000328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
ldr r1, =0x0a000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
ldr r1, =0x07100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
ldr r1, =0x00120000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00130000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00110002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00100328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
ldr r1, =0x0a100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* DREX1 */
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xE3855703
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x71101008
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x7110100A
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x7110100B
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x00000000
str r1, [r0, #0x20] @DMC_PHYCONTROL2
ldr r1, =0x0FFF301a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r1, =0x00312640
str r1, [r0, #0x04] @DMC_MEMCONTROL]
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x60e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
ldr r1, =0x20e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x40e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#endif
ldr r1, =0xff000000
str r1, [r0, #0x14] @DMC_PRECHCONFIG
ldr r1, =0x000000BC
str r1, [r0, #0x30] @DMC_TIMINGAREF
#ifdef DRAM_CLK_330
ldr r1, =0x3545548d
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x45430506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x4439033c
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
#ifdef DRAM_CLK_400
ldr r1, =0x4046654f
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x56500506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x5444033d
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
ldr r1, =0x07000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
ldr r1, =0x00020000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00030000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00010002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00000328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
ldr r1, =0x0a000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
ldr r1, =0x07100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
ldr r1, =0x00120000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00130000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00110002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00100328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
ldr r1, =0x0a100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* turn on DREX0, DREX1 */
ldr r0, =0x10400000 @APB_DMC_0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r0, =0x10410000 @APB_DMC_1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #0x00] @DMC_CONCONTROL
mov pc, lr

60
common/package/utils/sysupgrade-helper/src/board/samsung/smdkv310/mmc_boot.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include<common.h>
#include<config.h>
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
* API (Data transfer from mmc to ram)
*/
void copy_uboot_to_ram(void)
{
u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR;
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
}
void board_init_f(unsigned long bootflag)
{
__attribute__((noreturn)) void (*uboot)(void);
copy_uboot_to_ram();
/* Jump to U-Boot image */
uboot = (void *)CONFIG_SYS_TEXT_BASE;
(*uboot)();
/* Never returns Here */
}
/* Place Holders */
void board_init_r(gd_t *id, ulong dest_addr)
{
/*Function attribute is no-return*/
/*This Function never executes*/
while (1)
;
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
{
}

139
common/package/utils/sysupgrade-helper/src/board/samsung/smdkv310/smdkv310.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
| SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
| SROMC_BC_PMC(0x0F);
/* Select and configure the SROMC bank */
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
PHYS_SDRAM_3_SIZE);
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
PHYS_SDRAM_4_SIZE);
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: SMDKV310\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int i, err;
/*
* MMC2 SD card GPIO:
*
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
}
#endif

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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#include <string.h>
#include <sys/stat.h>
#define CHECKSUM_OFFSET (14*1024-4)
#define BUFSIZE (16*1024)
#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
/*
* Requirement:
* IROM code reads first 14K bytes from boot device.
* It then calculates the checksum of 14K-4 bytes and compare with data at
* 14K-4 offset.
*
* This function takes two filenames:
* IN "u-boot-spl.bin" and
* OUT "u-boot-mmc-spl.bin" as filenames.
* It reads the "u-boot-spl.bin" in 16K buffer.
* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
* It writes the buffer to "u-boot-mmc-spl.bin" file.
*/
int main(int argc, char **argv)
{
int i, len;
unsigned char buffer[BUFSIZE] = {0};
int ifd, ofd;
unsigned int checksum = 0, count;
if (argc != 3) {
printf(" %d Wrong number of arguments\n", argc);
exit(EXIT_FAILURE);
}
ifd = open(argv[1], O_RDONLY);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[1], strerror(errno));
exit(EXIT_FAILURE);
}
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
exit(EXIT_FAILURE);
}
len = lseek(ifd, 0, SEEK_END);
lseek(ifd, 0, SEEK_SET);
count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
if (read(ifd, buffer, count) != count) {
fprintf(stderr, "%s: Can't read %s: %s\n",
argv[0], argv[1], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
checksum += buffer[i];
memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
fprintf(stderr, "%s: Can't write %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
if (ifd)
close(ifd);
if (ofd)
close(ofd);
return EXIT_SUCCESS;
}

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#
# Copyright (C) 2011 Samsung Electronics
# Heungjun Kim <riverful.kim@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += trats.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* Machine Specific Values for TRATS board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TRATS_SETUP_H
#define _TRATS_SETUP_H
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
#define MUX_CORE_SEL_MOUTAPLL 0x0
#define MUX_CORE_SEL_SCLKMPLL 0x1
#define MUX_MPLL_SEL_FILPLL 0x0
#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
#define MUX_APLL_SEL_FILPLL 0x0
#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
| (MUX_CORE_SEL_MOUTAPLL << 16) \
| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
/* CLK_DIV_CPU0 */
#define APLL_RATIO 0x0
#define PCLK_DBG_RATIO 0x1
#define ATB_RATIO 0x3
#define PERIPH_RATIO 0x3
#define COREM1_RATIO 0x7
#define COREM0_RATIO 0x3
#define CORE_RATIO 0x0
#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (COREM1_RATIO << 8) \
| (COREM0_RATIO << 4) \
| (CORE_RATIO << 0))
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x0
#define COPY_RATIO 0x3
#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
/* CLK_DIV_DMC0 */
#define CORE_TIMERS_RATIO 0x1
#define COPY2_RATIO 0x3
#define DMCP_RATIO 0x1
#define DMCD_RATIO 0x1
#define DMC_RATIO 0x1
#define DPHY_RATIO 0x1
#define ACP_PCLK_RATIO 0x1
#define ACP_RATIO 0x3
#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
| (COPY2_RATIO << 24) \
| (DMCP_RATIO << 20) \
| (DMCD_RATIO << 16) \
| (DMC_RATIO << 12) \
| (DPHY_RATIO << 8) \
| (ACP_PCLK_RATIO << 4) \
| (ACP_RATIO << 0))
/* CLK_DIV_DMC1 */
#define DPM_RATIO 0x1
#define DVSEM_RATIO 0x1
#define PWI_RATIO 0x1
#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
| (DVSEM_RATIO << 16) \
| (PWI_RATIO << 8))
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_SEL_ACLK_133 0x0
#define MUX_ONENAND_SEL_ACLK_160 0x1
#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
#define MUX_VPLL_SEL_FINPLL 0x0
#define MUX_VPLL_SEL_FOUTVPLL 0x1
#define MUX_EPLL_SEL_FINPLL 0x0
#define MUX_EPLL_SEL_FOUTEPLL 0x1
#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
| (MUX_VPLL_SEL_FOUTVPLL << 8) \
| (MUX_EPLL_SEL_FOUTEPLL << 4) \
| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
/* CLK_DIV_TOP */
#define ONENAND_RATIO 0x0
#define ACLK_133_RATIO 0x5
#define ACLK_160_RATIO 0x4
#define ACLK_100_RATIO 0x7
#define ACLK_200_RATIO 0x3
#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
| (ACLK_133_RATIO << 12)\
| (ACLK_160_RATIO << 8) \
| (ACLK_100_RATIO << 4) \
| (ACLK_200_RATIO << 0))
/* CLK_DIV_LEFTBUS */
#define GPL_RATIO 0x1
#define GDL_RATIO 0x3
#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO 0x1
#define GDR_RATIO 0x3
#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
/* CLK_SRS_FSYS: 6 = SCLKMPLL */
#define SATA_SEL_SCLKMPLL 0
#define SATA_SEL_SCLKAPLL 1
#define MMC_SEL_XXTI 0
#define MMC_SEL_XUSBXTI 1
#define MMC_SEL_SCLK_HDMI24M 2
#define MMC_SEL_SCLK_USBPHY0 3
#define MMC_SEL_SCLK_USBPHY1 4
#define MMC_SEL_SCLK_HDMIPHY 5
#define MMC_SEL_SCLKMPLL 6
#define MMC_SEL_SCLKEPLL 7
#define MMC_SEL_SCLKVPLL 8
#define MMCC0_SEL MMC_SEL_SCLKMPLL
#define MMCC1_SEL MMC_SEL_SCLKMPLL
#define MMCC2_SEL MMC_SEL_SCLKMPLL
#define MMCC3_SEL MMC_SEL_SCLKMPLL
#define MMCC4_SEL MMC_SEL_SCLKMPLL
#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
| (MMCC4_SEL << 16) \
| (MMCC3_SEL << 12) \
| (MMCC2_SEL << 8) \
| (MMCC1_SEL << 4) \
| (MMCC0_SEL << 0))
/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
#define MMC0_RATIO 0xF
#define MMC0_PRE_RATIO 0x0
#define MMC1_RATIO 0xF
#define MMC1_PRE_RATIO 0x0
#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
| (MMC1_RATIO << 16) \
| (MMC0_PRE_RATIO << 8) \
| (MMC0_RATIO << 0))
/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
#define MMC2_RATIO 0xF
#define MMC2_PRE_RATIO 0x0
#define MMC3_RATIO 0xF
#define MMC3_PRE_RATIO 0x0
#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
| (MMC3_RATIO << 16) \
| (MMC2_PRE_RATIO << 8) \
| (MMC2_RATIO << 0))
/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
#define MMC4_RATIO 0xF
#define MMC4_PRE_RATIO 0x0
#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
| (MMC4_RATIO << 0))
/* CLK_SRC_PERIL0 */
#define UART_SEL_XXTI 0
#define UART_SEL_XUSBXTI 1
#define UART_SEL_SCLK_HDMI24M 2
#define UART_SEL_SCLK_USBPHY0 3
#define UART_SEL_SCLK_USBPHY1 4
#define UART_SEL_SCLK_HDMIPHY 5
#define UART_SEL_SCLKMPLL 6
#define UART_SEL_SCLKEPLL 7
#define UART_SEL_SCLKVPLL 8
#define UART0_SEL UART_SEL_SCLKMPLL
#define UART1_SEL UART_SEL_SCLKMPLL
#define UART2_SEL UART_SEL_SCLKMPLL
#define UART3_SEL UART_SEL_SCLKMPLL
#define UART4_SEL UART_SEL_SCLKMPLL
#define UART5_SEL UART_SEL_SCLKMPLL
#define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
| (UART4_SEL << 12) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL << 0))
/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
/* CLK_DIV_PERIL0 */
#define UART0_RATIO 7
#define UART1_RATIO 7
#define UART2_RATIO 7
#define UART3_RATIO 4
#define UART4_RATIO 7
#define UART5_RATIO 7
#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
| (UART4_RATIO << 12) \
| (UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_DIV_PERIL3 */
#define SLIMBUS_RATIO 0x0
#define PWM_RATIO 0x8
#define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
| (PWM_RATIO << 0))
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20
/* PLL Values */
#define DISABLE 0
#define ENABLE 1
#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
| (mdiv << 16) \
| (pdiv << 8) \
| (sdiv << 0))
/* APLL_CON0: 800MHz */
#define APLL_MDIV 0xC8
#define APLL_PDIV 0x6
#define APLL_SDIV 0x1
#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
/* APLL_CON1 */
#define APLL_AFC_ENB 0x1
#define APLL_AFC 0x1C
#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
/* MPLL_CON0: 800MHz */
#define MPLL_MDIV 0xC8
#define MPLL_PDIV 0x6
#define MPLL_SDIV 0x1
#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
/* MPLL_CON1 */
#define MPLL_AFC_ENB 0x1
#define MPLL_AFC 0x1C
#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
/* EPLL_CON0: 96MHz */
#define EPLL_MDIV 0x30
#define EPLL_PDIV 0x3
#define EPLL_SDIV 0x2
#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
/* EPLL_CON1 */
#define EPLL_K 0x0
#define EPLL_CON1_VAL (EPLL_K >> 0)
/* VPLL_CON0: 108MHz */
#define VPLL_MDIV 0x35
#define VPLL_PDIV 0x3
#define VPLL_SDIV 0x2
#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
/* VPLL_CON1 */
#define VPLL_SSCG_EN DISABLE
#define VPLL_SEL_PF_DN_SPREAD 0x0
#define VPLL_MRR 0x11
#define VPLL_MFR 0x0
#define VPLL_K 0x400
#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
| (VPLL_SEL_PF_DN_SPREAD << 29) \
| (VPLL_MRR << 24) \
| (VPLL_MFR << 16) \
| (VPLL_K << 0))
/* CLOCK GATE */
#define CLK_DIS 0x0
#define CLK_EN 0x1
#define BIT_CAM_CLK_PIXELASYNCM1 18
#define BIT_CAM_CLK_PIXELASYNCM0 17
#define BIT_CAM_CLK_PPMUCAMIF 16
#define BIT_CAM_CLK_QEFIMC3 15
#define BIT_CAM_CLK_QEFIMC2 14
#define BIT_CAM_CLK_QEFIMC1 13
#define BIT_CAM_CLK_QEFIMC0 12
#define BIT_CAM_CLK_SMMUJPEG 11
#define BIT_CAM_CLK_SMMUFIMC3 10
#define BIT_CAM_CLK_SMMUFIMC2 9
#define BIT_CAM_CLK_SMMUFIMC1 8
#define BIT_CAM_CLK_SMMUFIMC0 7
#define BIT_CAM_CLK_JPEG 6
#define BIT_CAM_CLK_CSIS1 5
#define BIT_CAM_CLK_CSIS0 4
#define BIT_CAM_CLK_FIMC3 3
#define BIT_CAM_CLK_FIMC2 2
#define BIT_CAM_CLK_FIMC1 1
#define BIT_CAM_CLK_FIMC0 0
#define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
| (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
| (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
| (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
| (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
| (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
| (CLK_EN << BIT_CAM_CLK_JPEG)\
| (CLK_EN << BIT_CAM_CLK_CSIS1)\
| (CLK_EN << BIT_CAM_CLK_CSIS0)\
| (CLK_EN << BIT_CAM_CLK_FIMC3)\
| (CLK_EN << BIT_CAM_CLK_FIMC2)\
| (CLK_EN << BIT_CAM_CLK_FIMC1)\
| (CLK_EN << BIT_CAM_CLK_FIMC0))
#define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
#define BIT_VP_CLK_PPMUTV 5
#define BIT_VP_CLK_SMMUTV 4
#define BIT_VP_CLK_HDMI 3
#define BIT_VP_CLK_TVENC 2
#define BIT_VP_CLK_MIXER 1
#define BIT_VP_CLK_VP 0
#define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
| (CLK_EN << BIT_VP_CLK_SMMUTV)\
| (CLK_EN << BIT_VP_CLK_HDMI)\
| (CLK_EN << BIT_VP_CLK_TVENC)\
| (CLK_EN << BIT_VP_CLK_MIXER)\
| (CLK_EN << BIT_VP_CLK_VP))
#define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
#define BIT_MFC_CLK_PPMUMFC_R 4
#define BIT_MFC_CLK_PPMUMFC_L 3
#define BIT_MFC_CLK_SMMUMFC_R 2
#define BIT_MFC_CLK_SMMUMFC_L 1
#define BIT_MFC_CLK_MFC 0
#define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
| (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
| (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
| (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
| (CLK_EN << BIT_MFC_CLK_MFC))
#define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
#define BIT_G3D_CLK_QEG3D 2
#define BIT_G3D_CLK_PPMUG3D 1
#define BIT_G3D_CLK_G3D 0
#define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
| (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
| (CLK_EN << BIT_G3D_CLK_G3D))
#define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
#define BIT_IMAGE_CLK_PPMUIMAGE 9
#define BIT_IMAGE_CLK_QEMDMA 8
#define BIT_IMAGE_CLK_QEROTATOR 7
#define BIT_IMAGE_CLK_QEG2D 6
#define BIT_IMAGE_CLK_SMMUMDMA 5
#define BIT_IMAGE_CLK_SMMUROTATOR 4
#define BIT_IMAGE_CLK_SMMUG2D 3
#define BIT_IMAGE_CLK_MDMA 2
#define BIT_IMAGE_CLK_ROTATOR 1
#define BIT_IMAGE_CLK_G2D 0
#define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
| (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
| (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
| (CLK_EN << BIT_IMAGE_CLK_MDMA)\
| (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
| (CLK_EN << BIT_IMAGE_CLK_G2D))
#define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
#define BIT_LCD0_CLK_PPMULCD0 5
#define BIT_LCD0_CLK_SMMUFIMD0 4
#define BIT_LCD0_CLK_DSIM0 3
#define BIT_LCD0_CLK_MDNIE0 2
#define BIT_LCD0_CLK_MIE0 1
#define BIT_LCD0_CLK_FIMD0 0
#define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
| (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
| (CLK_EN << BIT_LCD0_CLK_DSIM0)\
| (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
| (CLK_EN << BIT_LCD0_CLK_MIE0)\
| (CLK_EN << BIT_LCD0_CLK_FIMD0))
#define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
#define BIT_LCD1_CLK_PPMULCD1 5
#define BIT_LCD1_CLK_SMMUFIMD1 4
#define BIT_LCD1_CLK_DSIM1 3
#define BIT_LCD1_CLK_MDNIE1 2
#define BIT_LCD1_CLK_MIE1 1
#define BIT_LCD1_CLK_FIMD1 0
#define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
| (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
| (CLK_EN << BIT_LCD1_CLK_DSIM1)\
| (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
| (CLK_EN << BIT_LCD1_CLK_MIE1)\
| (CLK_EN << BIT_LCD1_CLK_FIMD1))
#define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
#define BIT_FSYS_CLK_SMMUPCIE 18
#define BIT_FSYS_CLK_PPMUFILE 17
#define BIT_FSYS_CLK_NFCON 16
#define BIT_FSYS_CLK_ONENAND 15
#define BIT_FSYS_CLK_PCIE 14
#define BIT_FSYS_CLK_USBDEVICE 13
#define BIT_FSYS_CLK_USBHOST 12
#define BIT_FSYS_CLK_SROMC 11
#define BIT_FSYS_CLK_SATA 10
#define BIT_FSYS_CLK_SDMMC4 9
#define BIT_FSYS_CLK_SDMMC3 8
#define BIT_FSYS_CLK_SDMMC2 7
#define BIT_FSYS_CLK_SDMMC1 6
#define BIT_FSYS_CLK_SDMMC0 5
#define BIT_FSYS_CLK_TSI 4
#define BIT_FSYS_CLK_SATAPHY 3
#define BIT_FSYS_CLK_PCIEPHY 2
#define BIT_FSYS_CLK_PDMA1 1
#define BIT_FSYS_CLK_PDMA0 0
#define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
| (CLK_EN << BIT_FSYS_CLK_NFCON)\
| (CLK_EN << BIT_FSYS_CLK_ONENAND)\
| (CLK_EN << BIT_FSYS_CLK_PCIE)\
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
| (CLK_EN << BIT_FSYS_CLK_SATA)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
| (CLK_EN << BIT_FSYS_CLK_TSI)\
| (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
| (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
#define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
#define BIT_GPS_CLK_SMMUGPS 1
#define BIT_GPS_CLK_GPS 0
#define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
| (CLK_EN << BIT_GPS_CLK_GPS))
#define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
#define BIT_PERIL_CLK_MODEMIF 28
#define BIT_PERIL_CLK_AC97 27
#define BIT_PERIL_CLK_SPDIF 26
#define BIT_PERIL_CLK_SLIMBUS 25
#define BIT_PERIL_CLK_PWM 24
#define BIT_PERIL_CLK_PCM2 23
#define BIT_PERIL_CLK_PCM1 22
#define BIT_PERIL_CLK_I2S2 21
#define BIT_PERIL_CLK_I2S1 20
#define BIT_PERIL_CLK_RESERVED0 19
#define BIT_PERIL_CLK_SPI2 18
#define BIT_PERIL_CLK_SPI1 17
#define BIT_PERIL_CLK_SPI0 16
#define BIT_PERIL_CLK_TSADC 15
#define BIT_PERIL_CLK_I2CHDMI 14
#define BIT_PERIL_CLK_I2C7 13
#define BIT_PERIL_CLK_I2C6 12
#define BIT_PERIL_CLK_I2C5 11
#define BIT_PERIL_CLK_I2C4 10
#define BIT_PERIL_CLK_I2C3 9
#define BIT_PERIL_CLK_I2C2 8
#define BIT_PERIL_CLK_I2C1 7
#define BIT_PERIL_CLK_I2C0 6
#define BIT_PERIL_CLK_RESERVED1 5
#define BIT_PERIL_CLK_UART4 4
#define BIT_PERIL_CLK_UART3 3
#define BIT_PERIL_CLK_UART2 2
#define BIT_PERIL_CLK_UART1 1
#define BIT_PERIL_CLK_UART0 0
#define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
| (CLK_EN << BIT_PERIL_CLK_AC97)\
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
| (CLK_EN << BIT_PERIL_CLK_PWM)\
| (CLK_EN << BIT_PERIL_CLK_PCM2)\
| (CLK_EN << BIT_PERIL_CLK_PCM1)\
| (CLK_EN << BIT_PERIL_CLK_I2S2)\
| (CLK_EN << BIT_PERIL_CLK_I2S1)\
| (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
| (CLK_EN << BIT_PERIL_CLK_SPI2)\
| (CLK_EN << BIT_PERIL_CLK_SPI1)\
| (CLK_EN << BIT_PERIL_CLK_SPI0)\
| (CLK_EN << BIT_PERIL_CLK_TSADC)\
| (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
| (CLK_EN << BIT_PERIL_CLK_I2C7)\
| (CLK_EN << BIT_PERIL_CLK_I2C6)\
| (CLK_EN << BIT_PERIL_CLK_I2C5)\
| (CLK_EN << BIT_PERIL_CLK_I2C4)\
| (CLK_EN << BIT_PERIL_CLK_I2C3)\
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
| (CLK_EN << BIT_PERIL_CLK_I2C1)\
| (CLK_EN << BIT_PERIL_CLK_I2C0)\
| (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
| (CLK_EN << BIT_PERIL_CLK_UART4)\
| (CLK_EN << BIT_PERIL_CLK_UART3)\
| (CLK_EN << BIT_PERIL_CLK_UART2)\
| (CLK_EN << BIT_PERIL_CLK_UART1)\
| (CLK_EN << BIT_PERIL_CLK_UART0))
#define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
#define BIT_PERIR_CLK_TMU_APBIF 17
#define BIT_PERIR_CLK_KEYIF 16
#define BIT_PERIR_CLK_RTC 15
#define BIT_PERIR_CLK_WDT 14
#define BIT_PERIR_CLK_MCT 13
#define BIT_PERIR_CLK_SECKEY 12
#define BIT_PERIR_CLK_HDMI_CEC 11
#define BIT_PERIR_CLK_TZPC5 10
#define BIT_PERIR_CLK_TZPC4 9
#define BIT_PERIR_CLK_TZPC3 8
#define BIT_PERIR_CLK_TZPC2 7
#define BIT_PERIR_CLK_TZPC1 6
#define BIT_PERIR_CLK_TZPC0 5
#define BIT_PERIR_CLK_CMU_DMCPART 4
#define BIT_PERIR_CLK_RESERVED 3
#define BIT_PERIR_CLK_CMU_APBIF 2
#define BIT_PERIR_CLK_SYSREG 1
#define BIT_PERIR_CLK_CHIP_ID 0
#define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
| (CLK_EN << BIT_PERIR_CLK_KEYIF)\
| (CLK_EN << BIT_PERIR_CLK_RTC)\
| (CLK_EN << BIT_PERIR_CLK_WDT)\
| (CLK_EN << BIT_PERIR_CLK_MCT)\
| (CLK_EN << BIT_PERIR_CLK_SECKEY)\
| (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
| (CLK_EN << BIT_PERIR_CLK_TZPC5)\
| (CLK_EN << BIT_PERIR_CLK_TZPC4)\
| (CLK_EN << BIT_PERIR_CLK_TZPC3)\
| (CLK_EN << BIT_PERIR_CLK_TZPC2)\
| (CLK_EN << BIT_PERIR_CLK_TZPC1)\
| (CLK_EN << BIT_PERIR_CLK_TZPC0)\
| (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
| (CLK_EN << BIT_PERIR_CLK_RESERVED)\
| (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
| (CLK_EN << BIT_PERIR_CLK_SYSREG)\
| (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
#define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
#define BIT_BLOCK_CLK_GPS 7
#define BIT_BLOCK_CLK_RESERVED 6
#define BIT_BLOCK_CLK_LCD1 5
#define BIT_BLOCK_CLK_LCD0 4
#define BIT_BLOCK_CLK_G3D 3
#define BIT_BLOCK_CLK_MFC 2
#define BIT_BLOCK_CLK_TV 1
#define BIT_BLOCK_CLK_CAM 0
#define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
| (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
| (CLK_EN << BIT_BLOCK_CLK_LCD1)\
| (CLK_EN << BIT_BLOCK_CLK_LCD0)\
| (CLK_EN << BIT_BLOCK_CLK_G3D)\
| (CLK_EN << BIT_BLOCK_CLK_MFC)\
| (CLK_EN << BIT_BLOCK_CLK_TV)\
| (CLK_EN << BIT_BLOCK_CLK_CAM))
#define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
/*
* GATE CAM : All block
* GATE VP : All block
* GATE MFC : All block
* GATE G3D : All block
* GATE IMAGE : All block
* GATE LCD0 : All block
* GATE LCD1 : All block
* GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
* GATE GPS : All block
* GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
* GATE PERI Right : All Enable, Block - KEYIF
* GATE Block : All block
*/
#define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
#define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
#define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
#define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
#define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
#define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
#define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
#define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
#define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
#define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
| ~((CLK_EN << BIT_PERIL_CLK_AC97)\
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
#define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
| ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
#define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
/* PS_HOLD: Data Hight, Output En */
#define BIT_DAT 8
#define BIT_EN 9
#define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)
#endif

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common/package/utils/sysupgrade-helper/src/board/samsung/trats/trats.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <lcd.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <max8997_pmic.h>
#include <libtizen.h>
#include "setup.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned int board_rev;
#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
return board_rev;
}
#endif
static void check_hw_revision(void);
static int hwrevision(int rev)
{
return (board_rev & 0xf) == rev;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
#if defined(CONFIG_PMIC)
pmic_init();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
int hwrev = 0;
int i;
/* hw_rev[3:0] == GPE1[3:0] */
for (i = 0; i < 4; i++) {
s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
}
udelay(1);
for (i = 0; i < 4; i++)
hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
debug("hwrev 0x%x\n", hwrev);
return hwrev;
}
static void check_hw_revision(void)
{
int hwrev;
hwrev = get_hw_revision();
board_rev |= hwrev;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tTRATS\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int i, err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
/*
* eMMC GPIO:
* SDR 8-bit@48MHz at MMC0
* GPK0[0] SD_0_CLK(2)
* GPK0[1] SD_0_CMD(2)
* GPK0[2] SD_0_CDn -> Not used
* GPK0[3:6] SD_0_DATA[0:3](2)
* GPK1[3:6] SD_0_DATA[0:3](3)
*
* DDR 4-bit@26MHz at MMC4
* GPK0[0] SD_4_CLK(3)
* GPK0[1] SD_4_CMD(3)
* GPK0[2] SD_4_CDn -> Not used
* GPK0[3:6] SD_4_DATA[0:3](3)
* GPK1[3:6] SD_4_DATA[4:7](4)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK0[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
/* GPK0[0:6] pull disable */
s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
/* GPK0[0:6] drv 4x */
s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
}
for (i = 3; i < 7; i++) {
/* GPK1[3:6] special function 3 */
s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
/* GPK1[3:6] pull disable */
s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
/* GPK1[3:6] drv 4x */
s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
}
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
/*
* SD card GPIO:
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn -> Not used
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
/* GPK2[0:6] pull disable */
s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
}
err = s5p_mmc_init(2, 4);
}
return err;
}
#endif
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
int ret = 0;
u32 val = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on) {
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_ON);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
} else {
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_OFF);
}
if (ret) {
puts("MAX8997 LDO setting error!\n");
return -1;
}
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
#endif
static void pmic_reset(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio->x0, 7, 1);
s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
}
static void board_clock_init(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
}
static void board_power_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
/* PS HOLD */
writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
/* Set power down */
writel(0, (unsigned int)&pwr->cam_configuration);
writel(0, (unsigned int)&pwr->tv_configuration);
writel(0, (unsigned int)&pwr->mfc_configuration);
writel(0, (unsigned int)&pwr->g3d_configuration);
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
}
static void board_uart_init(void)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int i;
/*
* UART2 GPIOs
* GPA1CON[0] = UART_2_RXD(2)
* GPA1CON[1] = UART_2_TXD(2)
* GPA1CON[2] = I2C_3_SDA (3)
* GPA1CON[3] = I2C_3_SCL (3)
*/
for (i = 0; i < 4; i++) {
s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
}
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
}
int board_early_init_f(void)
{
wdt_stop();
pmic_reset();
board_clock_init();
board_uart_init();
board_power_init();
return 0;
}
static void lcd_reset(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 0);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
}
static int lcd_power(void)
{
int ret = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return 0;
/* LDO15 voltage: 2.2v */
ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
/* LDO13 voltage: 3.0v */
ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
if (ret) {
puts("MAX8997 LDO setting error!\n");
return -1;
}
return 0;
}
static struct mipi_dsim_config dsim_config = {
.e_interface = DSIM_VIDEO,
.e_virtual_ch = DSIM_VIRTUAL_CH_0,
.e_pixel_format = DSIM_24BPP_888,
.e_burst_mode = DSIM_BURST_SYNC_EVENT,
.e_no_data_lane = DSIM_DATA_LANE_4,
.e_byte_clk = DSIM_PLL_OUT_DIV8,
.hfp = 1,
.p = 3,
.m = 120,
.s = 1,
/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
.pll_stable_time = 500,
/* escape clk : 10MHz */
.esc_clk = 20 * 1000000,
/* stop state holding counter after bta change count 0 ~ 0xfff */
.stop_holding_cnt = 0x7ff,
/* bta timeout 0 ~ 0xff */
.bta_timeout = 0xff,
/* lp rx timeout 0 ~ 0xffff */
.rx_timeout = 0xffff,
};
static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
.lcd_panel_info = NULL,
.dsim_config = &dsim_config,
};
static struct mipi_dsim_lcd_device mipi_lcd_device = {
.name = "s6e8ax0",
.id = -1,
.bus_id = 0,
.platform_data = (void *)&s6e8ax0_platform_data,
};
static int mipi_power(void)
{
int ret = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return 0;
/* LDO3 voltage: 1.1v */
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
/* LDO4 voltage: 1.8v */
ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
if (ret) {
puts("MAX8997 LDO setting error!\n");
return -1;
}
return 0;
}
vidinfo_t panel_info = {
.vl_freq = 60,
.vl_col = 720,
.vl_row = 1280,
.vl_width = 720,
.vl_height = 1280,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
.vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
/* s6e8ax0 Panel infomation */
.vl_hspw = 5,
.vl_hbpd = 10,
.vl_hfpd = 10,
.vl_vspw = 2,
.vl_vbpd = 1,
.vl_vfpd = 13,
.vl_cmd_allow_len = 0xf,
.win_id = 3,
.cfg_gpio = NULL,
.backlight_on = NULL,
.lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
.reset_lcd = lcd_reset,
.dual_lcd_enabled = 0,
.init_delay = 0,
.power_on_delay = 0,
.reset_delay = 0,
.interface_mode = FIMD_RGB_INTERFACE,
.mipi_enabled = 1,
};
void init_panel_info(vidinfo_t *vid)
{
vid->logo_on = 1,
vid->resolution = HD_RESOLUTION,
vid->rgb_mode = MODE_RGB_P,
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
if (hwrevision(2))
mipi_lcd_device.reverse_panel = 1;
strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
s6e8ax0_platform_data.lcd_power = lcd_power;
s6e8ax0_platform_data.mipi_power = mipi_power;
s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
s6e8ax0_init();
exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
setenv("lcdinfo", "lcd=s6e8ax0");
}

45
common/package/utils/sysupgrade-helper/src/board/samsung/universal_c210/Makefile Normal file
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#
# Copyright (C) 2010 Samsung Electronics
# Minkyu Kang <mk7.kang@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := universal.o onenand.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
$(call cmd_link_o_target, $(SOBJS) $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

395
common/package/utils/sysupgrade-helper/src/board/samsung/universal_c210/lowlevel_init.S Normal file
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/*
* Lowlevel setup for universal board based on EXYNOS4210
*
* Copyright (C) 2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has GPIO part1 base 0x11400000
* r6 has GPIO part2 base 0x11000000
*/
.globl lowlevel_init
lowlevel_init:
mov r11, lr
/* r5 has always zero */
mov r5, #0
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* System Timer */
ldr r0, =EXYNOS4_SYSTIMER_BASE
ldr r1, =0x5000
str r1, [r0, #0x0]
ldr r1, =0xffffffff
str r1, [r0, #0x8]
ldr r1, =0x49
str r1, [r0, #0x4]
/* PMIC manual reset */
/* nPOWER: XEINT_23: GPX2[7] */
add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
ldr r1, [r0, #0x0]
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28) @ Output
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
str r1, [r0, #0x4]
/* init system clock */
bl system_clock_init
/* Disable Watchdog */
ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
str r5, [r0]
/* UART */
bl uart_asm_init
/* PMU init */
bl system_power_init
bl tzpc_init
mov lr, r11
mov pc, lr
nop
nop
nop
/*
* uart_asm_init: Initialize UART's pins
*/
uart_asm_init:
/*
* setup UART0-UART4 GPIOs (part1)
* GPA1CON[3] = I2C_3_SCL (3)
* GPA1CON[2] = I2C_3_SDA (3)
*/
mov r0, r7
ldr r1, =0x22222222
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00223322
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
ldr r1, [r0, #0x0]
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28)
str r1, [r0, #0x0]
ldr r1, [r0, #0x8]
bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
orr r1, r1, #(0x3 << 14) @ Pull-up enabled
str r1, [r0, #0x8]
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
str r1, [r0, #0x4]
mov pc, lr
nop
nop
nop
system_clock_init:
ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
ldr r2, =0x14200 @ CLK_SRC_CPU
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
/*
* CLK_SRC_TOP0
* MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
* MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
* MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
*/
ldr r1, =0x10000110
ldr r2, =0x0C210 @ CLK_SRC_TOP
str r1, [r0, r2]
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
ldr r1, =0x0066666
ldr r2, =0x0C240 @ CLK_SRC_FSYS
str r1, [r0, r2]
/* UART[0:5], PWM: SCLKMPLL(6) */
ldr r1, =0x6666666
ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
/* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
ldr r1, =0x0133730
ldr r2, =0x14500 @ CLK_DIV_CPU0
str r1, [r0, r2]
/* CPU1: COPY, HPM */
ldr r1, =0x03
ldr r2, =0x14504 @ CLK_DIV_CPU1
str r1, [r0, r2]
/* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
ldr r1, =0x13111113
ldr r2, =0x10500 @ CLK_DIV_DMC0
str r1, [r0, r2]
/* DMC1: PWI, DVSEM, DPM */
ldr r1, =0x01010100
ldr r2, =0x10504 @ CLK_DIV_DMC1
str r1, [r0, r2]
/* LEFTBUS: GDL, GPL */
ldr r1, =0x13
ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
str r1, [r0, r2]
/* RIGHHTBUS: GDR, GPR */
ldr r1, =0x13
ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
str r1, [r0, r2]
/*
* CLK_DIV_TOP
* ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
* ACLK_200, ACLK_100, ACLK_160, ACLK_133,
*/
ldr r1, =0x00005473
ldr r2, =0x0C510 @ CLK_DIV_TOP
str r1, [r0, r2]
/* MMC[0:1] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C544 @ CLK_DIV_FSYS1
str r1, [r0, r2]
/* MMC[2:3] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C548 @ CLK_DIV_FSYS2
str r1, [r0, r2]
/* MMC4 */
ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C54C @ CLK_DIV_FSYS3
str r1, [r0, r2]
/* UART[0:5] */
ldr r1, =0x774777
ldr r2, =0x0C550 @ CLK_DIV_PERIL0
str r1, [r0, r2]
/* SLIMBUS: ???, PWM */
ldr r1, =0x8
ldr r2, =0x0C55C @ CLK_DIV_PERIL3
str r1, [r0, r2]
/* PLL Setting */
ldr r1, =0x1C20
ldr r2, =0x14000 @ APLL_LOCK
str r1, [r0, r2]
ldr r2, =0x14008 @ MPLL_LOCK
str r1, [r0, r2]
ldr r2, =0x0C010 @ EPLL_LOCK
str r1, [r0, r2]
ldr r2, =0x0C020 @ VPLL_LOCK
str r1, [r0, r2]
/* APLL */
ldr r1, =0x8000001c
ldr r2, =0x14104 @ APLL_CON1
str r1, [r0, r2]
ldr r1, =0x80c80601 @ 800MHz
ldr r2, =0x14100 @ APLL_CON0
str r1, [r0, r2]
/* MPLL */
ldr r1, =0x8000001C
ldr r2, =0x1410C @ MPLL_CON1
str r1, [r0, r2]
ldr r1, =0x80c80601 @ 800MHz
ldr r2, =0x14108 @ MPLL_CON0
str r1, [r0, r2]
/* EPLL */
ldr r1, =0x0
ldr r2, =0x0C114 @ EPLL_CON1
str r1, [r0, r2]
ldr r1, =0x80300302 @ 96MHz
ldr r2, =0x0C110 @ EPLL_CON0
str r1, [r0, r2]
/* VPLL */
ldr r1, =0x11000400
ldr r2, =0x0C124 @ VPLL_CON1
str r1, [r0, r2]
ldr r1, =0x80350302 @ 108MHz
ldr r2, =0x0C120 @ VPLL_CON0
str r1, [r0, r2]
/*
* SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
* Turn off all
*/
ldr r1, =0xFFF80000
ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFFC0
ldr r2, =0x0C924 @ CLK_GATE_IP_VP
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFFE0
ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFFFC
ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFC00
ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
str r1, [r0, r2]
/* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
ldr r1, =0xFFFFFFF1
ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFFC0
ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
str r1, [r0, r2]
/*
* SMMUPCIE[18], NFCON[16] : 1111 1010
* PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
* SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
*/
ldr r1, =0xFFFAB8A3
ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
str r1, [r0, r2]
/* Turn off all */
ldr r1, =0xFFFFFFFC
ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
str r1, [r0, r2]
/*
* AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
* I2C2[8] : 1111 1110
*/
ldr r1, =0xF1FFFEFF
ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
str r1, [r0, r2]
/*
* KEYIF[16] : 1111 1110
*/
ldr r1, =0xFFFEFFFF
ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
str r1, [r0, r2]
/* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
ldr r1, =0xFFFFFFD1
ldr r2, =0x0C970 @ CLK_GATE_BLOCK
str r1, [r0, r2]
mov pc, lr
nop
nop
nop
system_power_init:
ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
ldr r2, =0x330C @ PS_HOLD_CONTROL
ldr r1, [r0, r2]
orr r1, r1, #(0x3 << 8) @ Data High, Output En
str r1, [r0, r2]
/* Power Down */
add r2, r0, #0x3000
str r5, [r2, #0xC20] @ TV_CONFIGURATION
str r5, [r2, #0xC40] @ MFC_CONFIGURATION
str r5, [r2, #0xC60] @ G3D_CONFIGURATION
str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
mov pc, lr
nop
nop
nop
tzpc_init:
ldr r0, =0x10110000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10120000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10130000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10140000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10150000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
mov pc, lr

36
common/package/utils/sysupgrade-helper/src/board/samsung/universal_c210/onenand.c Normal file
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/*
* Copyright (C) 2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/samsung_onenand.h>
void onenand_board_init(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
this->base = (void *)CONFIG_SYS_ONENAND_BASE;
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
this->chip_probe = s5pc210_chip_probe;
}

322
common/package/utils/sysupgrade-helper/src/board/samsung/universal_c210/universal.c Normal file
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/*
* Copyright (C) 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <max8998_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
unsigned int board_rev;
u32 get_board_rev(void)
{
return board_rev;
}
static int get_hwrev(void)
{
return board_rev & 0xFF;
}
static void check_hw_revision(void);
int board_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
#if defined(CONFIG_PMIC)
pmic_init();
#endif
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
static unsigned short get_adc_value(int channel)
{
struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
unsigned short ret = 0;
unsigned int reg;
unsigned int loop = 0;
writel(channel & 0xF, &adc->adcmux);
writel((1 << 14) | (49 << 6), &adc->adccon);
writel(1000 & 0xffff, &adc->adcdly);
writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
udelay(10);
writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
udelay(10);
do {
udelay(1);
reg = readl(&adc->adccon);
} while (!(reg & (1 << 15)) && (loop++ < 1000));
ret = readl(&adc->adcdat0) & 0xFFF;
return ret;
}
static int adc_power_control(int on)
{
int ret;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
ret = pmic_set_output(p,
MAX8998_REG_ONOFF1,
MAX8998_LDO4, !!on);
return ret;
}
static unsigned int get_hw_revision(void)
{
int hwrev, mode0, mode1;
adc_power_control(1);
mode0 = get_adc_value(1); /* HWREV_MODE0 */
mode1 = get_adc_value(2); /* HWREV_MODE1 */
/*
* XXX Always set the default hwrev as the latest board
* ADC = (voltage) / 3.3 * 4096
*/
hwrev = 3;
#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
hwrev = 0x0; /* 0.01V 0.01V */
if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
hwrev = 0x1; /* 610mV 0.01V */
if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
hwrev = 0x2; /* 1.16V 0.01V */
if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
hwrev = 0x3; /* 1.79V 0.01V */
#undef IS_RANGE
debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
adc_power_control(0);
return hwrev;
}
static void check_hw_revision(void)
{
int hwrev;
hwrev = get_hw_revision();
board_rev |= hwrev;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tUniversal C210\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int i, err;
switch (get_hwrev()) {
case 0:
/*
* Set the low to enable LDO_EN
* But when you use the test board for eMMC booting
* you should set it HIGH since it removes the inverter
*/
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
s5p_gpio_direction_output(&gpio1->e3, 6, 0);
break;
default:
/*
* Default reset state is High and there's no inverter
* But set it as HIGH to ensure
*/
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
s5p_gpio_direction_output(&gpio1->e1, 3, 1);
break;
}
/*
* eMMC GPIO:
* SDR 8-bit@48MHz at MMC0
* GPK0[0] SD_0_CLK(2)
* GPK0[1] SD_0_CMD(2)
* GPK0[2] SD_0_CDn -> Not used
* GPK0[3:6] SD_0_DATA[0:3](2)
* GPK1[3:6] SD_0_DATA[0:3](3)
*
* DDR 4-bit@26MHz at MMC4
* GPK0[0] SD_4_CLK(3)
* GPK0[1] SD_4_CMD(3)
* GPK0[2] SD_4_CDn -> Not used
* GPK0[3:6] SD_4_DATA[0:3](3)
* GPK1[3:6] SD_4_DATA[4:7](4)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK0[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
/* GPK0[0:6] pull disable */
s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
/* GPK0[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
}
for (i = 3; i < 7; i++) {
/* GPK1[3:6] special function 3 */
s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
/* GPK1[3:6] pull disable */
s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
/* GPK1[3:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
}
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
err = s5p_mmc_init(0, 8);
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
/*
* SD card GPIO:
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn -> Not used
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
/* GPK2[0:6] pull disable */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
}
err = s5p_mmc_init(2, 4);
}
return err;
}
#endif
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
int ret = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on) {
ret |= pmic_set_output(p,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_SAFEOUT1, LDO_ON);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_ON);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_ON);
} else {
ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
MAX8998_LDO8, LDO_OFF);
ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
MAX8998_LDO3, LDO_OFF);
ret |= pmic_set_output(p,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_SAFEOUT1, LDO_OFF);
}
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -1;
}
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
#endif