mirror of
https://github.com/Ysurac/openmptcprouter.git
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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
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||||
#
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||||
# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := scb9328.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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325
common/package/utils/sysupgrade-helper/src/board/scb9328/flash.c
Normal file
325
common/package/utils/sysupgrade-helper/src/board/scb9328/flash.c
Normal file
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@ -0,0 +1,325 @@
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/*
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* Copyright (C) 2003 ETC s.r.o.
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*
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* This code was inspired by Marius Groeger and Kyle Harris code
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* available in other board ports for U-Boot
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Written by Peter Figuli <peposh@etc.sk>, 2003.
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*
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*/
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#include <common.h>
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#include "intel.h"
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/*
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* This code should handle CFI FLASH memory device. This code is very
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* minimalistic approach without many essential error handling code as well.
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* Because U-Boot actually is missing smart handling of FLASH device,
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* we just set flash_id to anything else to FLASH_UNKNOW, so common code
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* can call us without any restrictions.
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* TODO: Add CFI Query, to be able to determine FLASH device.
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* TODO: Add error handling code
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* NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
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* hopefully may work with other configurations.
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*/
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#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
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# define FLASH_BUS vu_char
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# define FLASH_BUS_RET u_char
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# if ( SCB9328_FLASH_INTERLEAVE == 1 )
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# define FLASH_CMD( x ) x
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# else
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# error "With 8bit bus only one chip is allowed"
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# endif
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#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
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# define FLASH_BUS vu_short
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# define FLASH_BUS_RET u_short
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# if ( SCB9328_FLASH_INTERLEAVE == 1 )
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# define FLASH_CMD( x ) x
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# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
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# define FLASH_CMD( x ) (( x << 8 )| x )
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# else
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# error "With 16bit bus only 1 or 2 chip(s) are allowed"
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# endif
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#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
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# define FLASH_BUS vu_long
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# define FLASH_BUS_RET u_long
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# if ( SCB9328_FLASH_INTERLEAVE == 1 )
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# define FLASH_CMD( x ) x
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# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
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# define FLASH_CMD( x ) (( x << 16 )| x )
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# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
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# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
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# else
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# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
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# endif
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#else
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# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
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#endif
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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static FLASH_BUS_RET flash_status_reg (void)
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{
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FLASH_BUS *addr = (FLASH_BUS *) 0;
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*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
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return *addr;
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}
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static int flash_ready (ulong timeout)
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{
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int ok = 1;
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ulong start;
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start = get_timer(0);
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while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
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FLASH_CMD (CFI_INTEL_SR_READY)) {
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if (get_timer(start) > timeout && timeout != 0) {
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ok = 0;
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break;
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}
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}
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return ok;
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}
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#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
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# error "SCB9328 platform has only one flash bank!"
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#endif
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ulong flash_init (void)
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{
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int i;
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unsigned long address = SCB9328_FLASH_BASE;
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flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
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flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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flash_info[0].flash_id = INTEL_MANUFACT;
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memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
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flash_info[0].start[i] = address;
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#ifdef SCB9328_FLASH_UNLOCK
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/* Some devices are hw locked after start. */
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*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
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*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
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flash_ready (0);
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*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
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#endif
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address += SCB9328_FLASH_SECT_SIZE;
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}
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
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return SCB9328_FLASH_BANK_SIZE;
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}
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void flash_print_info (flash_info_t * info)
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{
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int i;
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printf (" Intel vendor\n");
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; i++) {
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if (!(i % 5)) {
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printf ("\n");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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}
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag, non_protected = 0, sector;
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int rc = ERR_OK;
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FLASH_BUS *address;
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for (sector = s_first; sector <= s_last; sector++) {
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if (!info->protect[sector]) {
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non_protected++;
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}
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}
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if (!non_protected) {
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return ERR_PROTECTED;
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}
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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flag = disable_interrupts ();
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/* Start erase on unprotected sectors */
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for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
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if (info->protect[sector]) {
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printf ("Protected sector %2d skipping...\n", sector);
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continue;
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} else {
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printf ("Erasing sector %2d ... ", sector);
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}
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address = (FLASH_BUS *) (info->start[sector]);
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*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
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*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
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if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
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*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
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printf ("ok.\n");
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} else {
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*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
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rc = ERR_TIMOUT;
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printf ("timeout! Aborting...\n");
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break;
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}
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*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
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}
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if (ctrlc ())
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printf ("User Interrupt!\n");
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/* allow flash to settle - wait 10 ms */
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udelay_masked (10000);
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if (flag) {
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enable_interrupts ();
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}
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return rc;
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}
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static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
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{
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FLASH_BUS *address = (FLASH_BUS *) dest;
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int rc = ERR_OK;
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int flag;
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/* Check if Flash is (sufficiently) erased */
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if ((*address & data) != data) {
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return ERR_NOT_ERASED;
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}
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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flag = disable_interrupts ();
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*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
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*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
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*address = data;
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if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
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*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
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rc = ERR_TIMOUT;
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printf ("timeout! Aborting...\n");
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}
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*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
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if (flag) {
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enable_interrupts ();
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}
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return rc;
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}
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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ulong read_addr, write_addr;
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FLASH_BUS data;
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int i, result = ERR_OK;
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read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
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write_addr = read_addr;
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if (read_addr != addr) {
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data = 0;
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for (i = 0; i < sizeof (FLASH_BUS); i++) {
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if (read_addr < addr || cnt == 0) {
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data |= *((uchar *) read_addr) << i * 8;
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} else {
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data |= (*src++) << i * 8;
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cnt--;
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}
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read_addr++;
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}
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if ((result = write_data (info, write_addr, data)) != ERR_OK) {
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return result;
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}
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write_addr += sizeof (FLASH_BUS);
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}
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for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
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if ((result = write_data (info, write_addr,
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*((FLASH_BUS *) src))) != ERR_OK) {
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return result;
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}
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write_addr += sizeof (FLASH_BUS);
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src += sizeof (FLASH_BUS);
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}
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if (cnt > 0) {
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read_addr = write_addr;
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data = 0;
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for (i = 0; i < sizeof (FLASH_BUS); i++) {
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if (cnt > 0) {
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data |= (*src++) << i * 8;
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cnt--;
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} else {
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data |= *((uchar *) read_addr) << i * 8;
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}
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read_addr++;
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}
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if ((result = write_data (info, write_addr, data)) != 0) {
|
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return result;
|
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}
|
||||
}
|
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return ERR_OK;
|
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}
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@ -0,0 +1,99 @@
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/*
|
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* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
|
||||
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
|
||||
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
|
||||
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
|
||||
*
|
||||
* This file is taken from OpenWinCE project hosted by SourceForge.net
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_INTEL_H
|
||||
#define FLASH_INTEL_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
|
||||
|
||||
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
|
||||
|
||||
#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F320J3A 0x0016
|
||||
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
|
||||
#define CFI_CHIP_INTEL_28F640J3A 0x0017
|
||||
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
|
||||
#define CFI_CHIP_INTEL_28F128J3A 0x0018
|
||||
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F640K3 0x8801
|
||||
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
|
||||
#define CFI_CHIP_INTEL_28F128K3 0x8802
|
||||
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
|
||||
#define CFI_CHIP_INTEL_28F256K3 0x8803
|
||||
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
|
||||
#define CFI_CHIP_INTEL_28F640K18 0x8805
|
||||
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
|
||||
#define CFI_CHIP_INTEL_28F128K18 0x8806
|
||||
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
|
||||
#define CFI_CHIP_INTEL_28F256K18 0x8807
|
||||
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
|
||||
|
||||
#endif /* FLASH_INTEL_H */
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
* 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* Change PERCLK1DIV to 14 ie 14+1 */
|
||||
ldr r0, =PCDR
|
||||
ldr r1, =CONFIG_SYS_PCDR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set MCU PLL Control Register 0 */
|
||||
|
||||
ldr r0, =MPCTL0
|
||||
ldr r1, =CONFIG_SYS_MPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set mpll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<21)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
/* set System PLL Control Register 0 */
|
||||
|
||||
ldr r0, =SPCTL0
|
||||
ldr r1, =CONFIG_SYS_SPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set spll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<22)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
ldr r0, =CSCR
|
||||
ldr r1, =CONFIG_SYS_CSCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
|
||||
*this.....
|
||||
*
|
||||
* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
|
||||
* register 1, this stops it using the output of the PLL and thus runs at the
|
||||
* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
|
||||
* use the value set in the CM_OSC registers...regardless of what you set it
|
||||
* too! Thus, although i thought i was running at 140MHz, i'm actually running
|
||||
* at 40!..
|
||||
|
||||
* Slapping this into my bootloader does the trick...
|
||||
|
||||
* MRC p15,0,r0,c1,c0,0 ; read core configuration register
|
||||
* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
|
||||
* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
|
||||
* register
|
||||
*/
|
||||
MRC p15,0,r0,c1,c0,0
|
||||
ORR r0,r0,#0xC0000000
|
||||
MCR p15,0,r0,c1,c0,0
|
||||
|
||||
ldr r0, =GPR(0)
|
||||
ldr r1, =CONFIG_SYS_GPR_A_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GIUS(0)
|
||||
ldr r1, =CONFIG_SYS_GIUS_A_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
|
||||
|
||||
ldr r0, =FMCR
|
||||
ldr r1, =CONFIG_SYS_FMCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0U
|
||||
ldr r1, =CONFIG_SYS_CS0U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0L
|
||||
ldr r1, =CONFIG_SYS_CS0L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1U
|
||||
ldr r1, =CONFIG_SYS_CS1U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1L
|
||||
ldr r1, =CONFIG_SYS_CS1L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS2U
|
||||
ldr r1, =CONFIG_SYS_CS2U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS2L
|
||||
ldr r1, =CONFIG_SYS_CS2L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS3U
|
||||
ldr r1, =CONFIG_SYS_CS3U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS3L
|
||||
ldr r1, =CONFIG_SYS_CS3L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4U
|
||||
ldr r1, =CONFIG_SYS_CS4U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4L
|
||||
ldr r1, =CONFIG_SYS_CS4L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5U
|
||||
ldr r1, =CONFIG_SYS_CS5U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5L
|
||||
ldr r1, =CONFIG_SYS_CS5L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* SDRAM Setup */
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =PRECHARGE_CMD
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08200000
|
||||
ldr r1, =0x0 /* Issue Precharge all Command */
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =AUTOREFRESH_CMD
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08000000
|
||||
ldr r1, =0x0 /* Issue AutoRefresh Command */
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =0xb10a8300
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08223000 /* CAS Latency 2 */
|
||||
ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
|
||||
str r1, [r0]
|
||||
|
||||
mov pc,r10
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
|
||||
gd->bd->bi_boot_params = 0x08000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1,
|
||||
SCB9328_SDRAM_1_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
|
||||
}
|
||||
|
||||
/**
|
||||
* show_boot_progress: - indicate state of the boot process
|
||||
*
|
||||
* @param status: Status number - see README for details.
|
||||
*
|
||||
* The CSB226 does only have 3 LEDs, so we switch them on at the most
|
||||
* important states (1, 5, 15).
|
||||
*/
|
||||
|
||||
void show_boot_progress (int status)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return dm9000_initialize(bis);
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue