mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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@ -0,0 +1,299 @@
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/*
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* (C) Copyright 2001
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* Paul Geerinckx
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <net.h>
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#include "atm.h"
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#include <i2c.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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/* used PLD registers */
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# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
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# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
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# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
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# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
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# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
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_NOT_USED_,
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0xFFFAF834, 0xFFE5B435, /* last */
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_NOT_USED_,
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
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0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF1AAF804, 0xFFA5F447, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
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0xFFAFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* MRS sequence (Offset 38 in UPMA RAM)
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*/
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0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
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_NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0xFFAFFC04, 0xFFAFFC05, /* last */
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_NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile iop8xx_t *iop = &immap->im_ioport;
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volatile fec_t *fecp = &immap->im_cpm.cp_fec;
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long int size;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
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memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
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memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
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udelay (1);
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memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
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udelay (1);
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memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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*/
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size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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memctl->memc_mamr = CONFIG_SYS_MAMR;
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udelay (1000);
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/*
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* Final mapping
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*/
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
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memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
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udelay (10000);
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/* prepare pin multiplexing for fast ethernet */
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atmLoad ();
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fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
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iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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return (0);
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}
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void board_serial_init (void)
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{
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; /* nothing to do here */
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}
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void board_ether_init (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile iop8xx_t *iop = &immap->im_ioport;
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volatile fec_t *fecp = &immap->im_cpm.cp_fec;
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atmLoad ();
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fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
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iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
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}
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int board_early_init_f (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile iop8xx_t *iop = &immap->im_ioport;
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/* configure the LED timing output pins - port A pin 4 */
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iop->iop_papar = 0x0800;
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iop->iop_padir = 0x0800;
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/* start timer 2 for the 4hz LED blink rate */
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timers->cpmt_tmr2 = 0xff2c; /* 4HZ for 64MHz */
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timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
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timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
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/* chip select for PLD access */
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memctl->memc_br6 = 0x10000401;
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memctl->memc_or6 = 0xFC000908;
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/* PLD initial values ( set LEDs, remove reset on LXT) */
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*PLD_GCR1_REG = 0x06;
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*PLD_EXT_RES = 0xC0;
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*PLD_EXT_FETH = 0x40;
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*PLD_EXT_LED = 0xFF;
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*PLD_EXT_X21 = 0x04;
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return 0;
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}
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static void board_get_enetaddr(uchar *addr)
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{
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int i;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpm = &immap->im_cpm;
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unsigned int rccrtmp;
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char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
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for (i = 0; i < 6; i++)
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addr[i] = default_mac_addr[i];
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printf ("There is an error in the i2c driver .. /n");
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printf ("You need to fix it first....../n");
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rccrtmp = cpm->cp_rccr;
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cpm->cp_rccr |= 0x0020;
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i2c_reg_read (0xa0, 0);
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printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
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i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
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i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
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i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
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cpm->cp_rccr = rccrtmp;
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}
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int misc_init_r(void)
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{
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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board_get_enetaddr(enetaddr);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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return 0;
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}
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o atm.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,652 @@
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include "atm.h"
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#include <linux/stddef.h>
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#define SYNC __asm__("sync")
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#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
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#define FALSE 1
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#define TRUE 0
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#define OK 0
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#define ERROR -1
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|
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struct atm_connection_t g_conn[NUM_CONNECTIONS] =
|
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{
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{ NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
|
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};
|
||||
|
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struct atm_driver_t g_atm =
|
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{
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FALSE, /* loaded */
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FALSE, /* started */
|
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NULL, /* csram */
|
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0, /* csram_size */
|
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NULL, /* am_top */
|
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NULL, /* ap_top */
|
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NULL, /* int_reload_ptr */
|
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NULL, /* int_serv_ptr */
|
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NULL, /* rbd_base_ptr */
|
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NULL, /* tbd_base_ptr */
|
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0 /* linerate */
|
||||
};
|
||||
|
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char csram[1024]; /* more than enough for doing nothing*/
|
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|
||||
int atmLoad(void);
|
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void atmUnload(void);
|
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int atmMemInit(void);
|
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void atmIntInit(void);
|
||||
void atmApcInit(void);
|
||||
void atmAmtInit(void);
|
||||
void atmCpmInit(void);
|
||||
void atmUtpInit(void);
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmLoad
|
||||
*
|
||||
* DESCRIPTION: Basic ATM initialization.
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: OK or ERROR
|
||||
*
|
||||
****************************************************************************/
|
||||
int atmLoad()
|
||||
{
|
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
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volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
|
||||
volatile iop8xx_t *iop = &immap->im_ioport;
|
||||
|
||||
timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
|
||||
immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
|
||||
iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
|
||||
|
||||
if ( atmMemInit() != OK ) return ERROR;
|
||||
|
||||
atmIntInit();
|
||||
atmApcInit();
|
||||
atmAmtInit();
|
||||
atmCpmInit();
|
||||
atmUtpInit();
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||||
|
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g_atm.loaded = TRUE;
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||||
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return OK;
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||||
}
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||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmUnload
|
||||
*
|
||||
* DESCRIPTION: Disables ATM and UTOPIA.
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmUnload()
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
|
||||
volatile iop8xx_t *iop = &immap->im_ioport;
|
||||
|
||||
timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
|
||||
immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
|
||||
iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
|
||||
g_atm.loaded = FALSE;
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||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmMemInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* The ATM driver uses the following resources:
|
||||
*
|
||||
* A. Memory in DPRAM to hold
|
||||
*
|
||||
* 1/ CT = Connection Table ( RCT & TCT )
|
||||
* 2/ TCTE = Transmit Connection Table Extension
|
||||
* 3/ MPHYPT = Multi-PHY Pointing Table
|
||||
* 4/ APCP = APC Parameter Table
|
||||
* 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
|
||||
* 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
|
||||
* 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
|
||||
* 8/ TQ = Transmit Queue
|
||||
* 9/ AM = Address Matching Table
|
||||
* 10/ AP = Address Pointing Table
|
||||
*
|
||||
* B. Memory in cache safe RAM to hold
|
||||
*
|
||||
* 1/ INT = Interrupt Queue
|
||||
* 2/ RBD = Receive Buffer Descriptors
|
||||
* 3/ TBD = Transmit Buffer Descriptors
|
||||
*
|
||||
* This function
|
||||
* 1. clears the ATM DPRAM area,
|
||||
* 2. Allocates and clears cache safe memory,
|
||||
* 3. Initializes 'g_conn'.
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: OK or ERROR
|
||||
*
|
||||
****************************************************************************/
|
||||
int atmMemInit()
|
||||
{
|
||||
int i;
|
||||
unsigned immr = CONFIG_SYS_IMMR;
|
||||
int total_num_rbd = 0;
|
||||
int total_num_tbd = 0;
|
||||
|
||||
memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
|
||||
|
||||
g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
|
||||
|
||||
for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
|
||||
total_num_rbd += g_conn[i].num_rbd;
|
||||
total_num_tbd += g_conn[i].num_tbd;
|
||||
}
|
||||
|
||||
g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
|
||||
|
||||
g_atm.csram = &csram[0];
|
||||
memset(&(g_atm.csram), 0x00, g_atm.csram_size);
|
||||
|
||||
g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
|
||||
g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
|
||||
g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
|
||||
|
||||
g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
|
||||
g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
|
||||
g_conn[0].ct_ptr = CT_PTR(immr);
|
||||
g_conn[0].tcte_ptr = TCTE_PTR(immr);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmIntInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* Initialization of the MPC860 ESAR Interrupt Queue.
|
||||
* This function
|
||||
* - clears all entries in the INT,
|
||||
* - sets the WRAP bit of the last INT entry,
|
||||
* - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
|
||||
* to the first INT entry.
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
* REMARKS:
|
||||
*
|
||||
* - The INT resides in external cache safe memory.
|
||||
* - The base address of the INT is stored in g_atm.int_reload_ptr.
|
||||
* - The number of entries in the INT is given by NUM_INT_ENTRIES.
|
||||
* - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmIntInit()
|
||||
{
|
||||
int i;
|
||||
for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
|
||||
g_atm.int_reload_ptr[i] = INT_WRAP;
|
||||
g_atm.int_serv_ptr = g_atm.int_reload_ptr;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmApcInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function initializes the following ATM Pace Controller related
|
||||
* data structures:
|
||||
*
|
||||
* - 1 MPHY Pointing Table (contains only one entry)
|
||||
* - 3 APC Parameter Tables (one PHY with 3 priorities)
|
||||
* - 3 APC Tables (one table for each priority)
|
||||
* - 1 Transmit Queue (one transmit queue per PHY)
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmApcInit()
|
||||
{
|
||||
int i;
|
||||
/* unsigned immr = CONFIG_SYS_IMMR; */
|
||||
uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
|
||||
struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
|
||||
uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
|
||||
uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
|
||||
/***************************************************/
|
||||
/* Initialize MPHY Pointing Table (only one entry) */
|
||||
/***************************************************/
|
||||
*mphypt_ptr = APCP_BASE;
|
||||
|
||||
/********************************************/
|
||||
/* Initialize APC parameters for priority 1 */
|
||||
/********************************************/
|
||||
apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
|
||||
apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
|
||||
apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
|
||||
apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
|
||||
apcp_ptr->etqbase = TQ_BASE;
|
||||
apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
|
||||
apcp_ptr->etqaptr = TQ_BASE;
|
||||
apcp_ptr->etqtptr = TQ_BASE;
|
||||
apcp_ptr->apc_mi = 8;
|
||||
apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
|
||||
apcp_ptr->apcnt = 0;
|
||||
apcp_ptr->reserved1 = 0;
|
||||
apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
|
||||
apcp_ptr->ptp_counter = 0;
|
||||
apcp_ptr->ptp_txch = 0;
|
||||
apcp_ptr->reserved2 = 0;
|
||||
|
||||
|
||||
/***************************************************/
|
||||
/* Initialize APC Tables with empty slots (0xFFFF) */
|
||||
/***************************************************/
|
||||
for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
|
||||
|
||||
/************************/
|
||||
/* Clear Transmit Queue */
|
||||
/************************/
|
||||
for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmAmtInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function clears the first entry in the Address Matching Table and
|
||||
* lets the first entry in the Address Pointing table point to the first
|
||||
* entry in the TCT table (i.e. the raw cell channel).
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
* REMARKS:
|
||||
*
|
||||
* The values for the AMBASE, AMEND and APBASE registers in SAR parameter
|
||||
* RAM are initialized by atmCpmInit().
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmAmtInit()
|
||||
{
|
||||
unsigned immr = CONFIG_SYS_IMMR;
|
||||
|
||||
g_atm.am_top = AM_PTR(immr);
|
||||
g_atm.ap_top = AP_PTR(immr);
|
||||
|
||||
*(g_atm.ap_top--) = CT_BASE;
|
||||
*(g_atm.am_top--) = 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmCpmInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function initializes the Utopia Interface Parameter RAM Map
|
||||
* (SCC4, ATM Protocol) of the Communication Processor Modudule.
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmCpmInit()
|
||||
{
|
||||
unsigned immr = CONFIG_SYS_IMMR;
|
||||
|
||||
memset((char *)immr + 0x3F00, 0x00, 0xC0);
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RBDBASE - Receive buffer descriptors base address */
|
||||
/* The RBDs reside in cache safe external memory. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* SRFCR - SAR receive function code */
|
||||
/* 0-2 rsvd = 000 */
|
||||
/* 3-4 BO = 11 Byte ordering (big endian). */
|
||||
/* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
|
||||
/* when the SDMA channel accesses memory. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*SRFCR(immr) = 0x18;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* SRSTATE - SAR receive status */
|
||||
/* 0 EXT = 0 Extended mode off. */
|
||||
/* 1 ACP = 0 Valid only if EXT = 1. */
|
||||
/* 2 EC = 0 Standard 53-byte ATM cell. */
|
||||
/* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
|
||||
/* 4 ESAR = 1 Enhanced SAR functionality enabled. */
|
||||
/* 5 MCF = 1 Management Cell Filter active. */
|
||||
/* 6 SER = 0 UTOPIA mode. */
|
||||
/* 7 MPY = 1 Multiple PHY mode. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*SRSTATE(immr) = 0x0D;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* MRBLR - Maximum receive buffer length register. */
|
||||
/* Must be cleared for ATM operation (see also SMRBLR). */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*MRBLR(immr) = 0;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RSTATE - SCC internal receive state parameters */
|
||||
/* The first byte must be initialized with the value of SRFCR. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* STFCR - SAR transmit function code */
|
||||
/* 0-2 rsvd = 000 */
|
||||
/* 3-4 BO = 11 Byte ordering (big endian). */
|
||||
/* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
|
||||
/* when the SDMA channel accesses memory. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*STFCR(immr) = 0x18;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* SRSTATE - SAR transmit status */
|
||||
/* 0 EXT = 0 : Extended mode off */
|
||||
/* 1 rsvd = 0 : */
|
||||
/* 2 EC = 0 : Standard 53-byte ATM cell */
|
||||
/* 3 rsvd = 0 : */
|
||||
/* 4 ESAR = 1 : Enhanced SAR functionality enabled */
|
||||
/* 5 rsvd = 0 : */
|
||||
/* 6 SER = 0 : UTOPIA mode */
|
||||
/* 7 MPY = 1 : Multiple PHY mode */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*STSTATE(immr) = 0x09;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* TBDBASE - Transmit buffer descriptors base address */
|
||||
/* The TBDs reside in cache safe external memory. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* TSTATE - SCC internal transmit state parameters */
|
||||
/* The first byte must be initialized with the value of STFCR. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* CTBASE - Connection table base address */
|
||||
/* Offset from the beginning of DPRAM (64-byte aligned). */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*CTBASE(immr) = CT_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* INTBASE - Interrupt queue base pointer. */
|
||||
/* The interrupt queue resides in cache safe external memory. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* INTPTR - Pointer into interrupt queue. */
|
||||
/* Initialize to INTBASE. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*INTPTR(immr) = *INTBASE(immr);
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* C_MASK - Constant mask for CRC32 */
|
||||
/* Must be initialized to 0xDEBB20E3. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*C_MASK(immr) = 0xDEBB20E3;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* INT_ICNT - Interrupt threshold value */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*INT_ICNT(immr) = 1;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* INT_CNT - Interrupt counter */
|
||||
/* Initalize to INT_ICNT. Decremented for each interrupt entry */
|
||||
/* reported in the interrupt queue. On zero an interrupt is */
|
||||
/* signaled to the host by setting the GINT bit in the event */
|
||||
/* register. The counter is reinitialized with INT_ICNT. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*INT_CNT(immr) = *INT_ICNT(immr);
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* SMRBLR - SAR maximum receive buffer length register. */
|
||||
/* Must be a multiple of 48 bytes. Common for all ATM connections. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*SMRBLR(immr) = SAR_RXB_SIZE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* APCST - APC status register. */
|
||||
/* 0 rsvd 0 */
|
||||
/* 1-2 CSER 11 Initialize with the same value as NSER. */
|
||||
/* 3-4 NSER 11 Next serial or UTOPIA channel. */
|
||||
/* 5-7 rsvd 000 */
|
||||
/* 8-10 rsvd 000 */
|
||||
/* 11 rsvd 0 */
|
||||
/* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
|
||||
/* 13 DIS 0 APC disable. Must be initiazed to 0. */
|
||||
/* 14 PL2 0 Not used. */
|
||||
/* 15 MPY 1 Multiple PHY mode on. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*APCST(immr) = 0x7809;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* APCPTR - Pointer to the APC parameter table */
|
||||
/* In MPHY master mode this parameter points to the MPHY pointing */
|
||||
/* table. 2-byte aligned. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*APCPTR(immr) = MPHYPT_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* HMASK - Header mask */
|
||||
/* Each incoming cell is masked with HMASK before being compared */
|
||||
/* to the entries in the address matching table. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*HMASK(immr) = AM_HMASK;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* AMBASE - Address matching table base address */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*AMBASE(immr) = AM_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* AMEND - Address matching table end address */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*AMEND(immr) = AM_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* APBASE - Address pointing table base address */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*APBASE(immr) = AP_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* MPHYST - MPHY status register */
|
||||
/* 0-1 rsvd 00 */
|
||||
/* 2-6 NMPHY 00000 1 PHY */
|
||||
/* 7-9 rsvd 000 */
|
||||
/* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*MPHYST(immr) = 0x0000;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* TCTEBASE - Transmit connection table extension base address */
|
||||
/* Offset from the beginning of DPRAM (32-byte aligned). */
|
||||
/*-----------------------------------------------------------------*/
|
||||
*TCTEBASE(immr) = TCTE_BASE;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* Clear not used registers. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* FUNCTION NAME: atmUtpInit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function initializes the ATM interface for
|
||||
*
|
||||
* - UTOPIA mode
|
||||
* - muxed bus
|
||||
* - master operation
|
||||
* - multi PHY (because of a bug in the MPC860P rev. E.0)
|
||||
* - internal clock = SYSCLK / 2
|
||||
*
|
||||
* EXTERNAL EFFECTS:
|
||||
*
|
||||
* After calling this function, the MPC860ESAR UTOPIA bus is
|
||||
* active and uses the following ports/pins:
|
||||
*
|
||||
* Port Pin Signal Description
|
||||
* ------ --- ------- -------------------------------------------
|
||||
* PB[15] R17 TxClav Transmit cell available input/output signal
|
||||
* PC[15] D16 RxClav Receive cell available input/output signal
|
||||
* PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
|
||||
* PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
|
||||
* PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
|
||||
* PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
|
||||
* PD[11] T16 RXENB Receive enable input/output signal
|
||||
* PD[10] W18 TXENB Transmit enable input/output signal
|
||||
* PD[9] V17 UTPCLK UTOPIA clock input/output signal
|
||||
* PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
|
||||
* PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
|
||||
* PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
|
||||
* PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
|
||||
* PD[3] W16 SOC Start of cell input/output signal
|
||||
*
|
||||
* PARAMETERS: none
|
||||
*
|
||||
* RETURNS: void
|
||||
*
|
||||
* REMARK:
|
||||
*
|
||||
* The ATM parameters and data structures must be configured before
|
||||
* initializing the UTOPIA port. The UTOPIA port activates immediately
|
||||
* upon initialization, and if its associated data structures are not
|
||||
* initialized, the CPM will lock up.
|
||||
*
|
||||
****************************************************************************/
|
||||
void atmUtpInit()
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile iop8xx_t *iop = &immap->im_ioport;
|
||||
volatile car8xx_t *car = &immap->im_clkrst;
|
||||
volatile cpm8xx_t *cpm = &immap->im_cpm;
|
||||
int flag;
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* SCCR - System Clock Control Register */
|
||||
/* */
|
||||
/* The UTOPIA clock can be selected to be internal clock or */
|
||||
/* external clock (selected by the UTOPIA mode register). */
|
||||
/* In case of internal clock, the UTOPIA clock is derived from */
|
||||
/* the system frequency divided by two dividers. */
|
||||
/* Bits 27-31 of the SCCR register are defined to control the */
|
||||
/* UTOPIA clock. */
|
||||
/* */
|
||||
/* SCCR[27:29] DFUTP Division factor. Divide the system clock */
|
||||
/* by 2^DFUTP. */
|
||||
/* SCCR[30:31] DFAUTP Additional division factor. Divide the */
|
||||
/* system clock by the following value: */
|
||||
/* 00 = divide by 1 */
|
||||
/* 00 = divide by 3 */
|
||||
/* 10 = divide by 5 */
|
||||
/* 11 = divide by 7 */
|
||||
/* */
|
||||
/* Note that the UTOPIA clock must be programmed as to operate */
|
||||
/* within the range SYSCLK/10 .. 50MHz. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
car->car_sccr &= 0xFFFFFFE0;
|
||||
car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RCCR - RISC Controller Configuration Register */
|
||||
/* */
|
||||
/* RCCR[8] DR1M IDMA Request 0 Mode */
|
||||
/* 0 = edge sensitive */
|
||||
/* 1 = level sensitive */
|
||||
/* RCCR[9] DR0M IDMA Request 0 Mode */
|
||||
/* 0 = edge sensitive */
|
||||
/* 1 = level sensitive */
|
||||
/* RCCR[10:11] DRQP IDMA Request Priority */
|
||||
/* 00 = IDMA req. have more prio. than SCCs */
|
||||
/* 01 = IDMA req. have less prio. then SCCs */
|
||||
/* 10 = IDMA requests have the lowest prio. */
|
||||
/* 11 = reserved */
|
||||
/* */
|
||||
/* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
|
||||
/* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
|
||||
/* higher priority. */
|
||||
/*-----------------------------------------------------------------*/
|
||||
cpm->cp_rccr &= 0xFF0F;
|
||||
cpm->cp_rccr |= 0x00D0;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* Port B - TxClav Signal */
|
||||
/*-----------------------------------------------------------------*/
|
||||
cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
|
||||
cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* UTOPIA Mode Register */
|
||||
/* */
|
||||
/* - muxed bus (master operation only) */
|
||||
/* - multi PHY (because of a bug in the MPC860P rev.E.0) */
|
||||
/* - internal clock */
|
||||
/* - no loopback */
|
||||
/* - do no activate statistical counters */
|
||||
/*-----------------------------------------------------------------*/
|
||||
iop->utmode = 0x00000004; SYNC;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* Port D - UTOPIA Data and Control Signals */
|
||||
/* */
|
||||
/* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
|
||||
/* 11 RXENB UTOPIA receive enable input/output signal */
|
||||
/* 10 TXENB UTOPIA transmit enable input/output signal */
|
||||
/* 9 TUPCLK UTOPIA clock input/output signal */
|
||||
/* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
|
||||
/* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
|
||||
/* 3 SOC UTOPIA Start of cell input/output signal */
|
||||
/* 2 Reserved */
|
||||
/* 1 Enable UTOPIA mode */
|
||||
/* 0 Enable SAR */
|
||||
/*-----------------------------------------------------------------*/
|
||||
iop->iop_pdpar |= 0xDF7F; SYNC;
|
||||
iop->iop_pddir &= 0x2080; SYNC;
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* Port C - RxClav Signal */
|
||||
/*-----------------------------------------------------------------*/
|
||||
iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
|
||||
iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
|
||||
iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
}
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned int uint32;
|
||||
typedef volatile unsigned char vuint8;
|
||||
typedef volatile unsigned short vuint16;
|
||||
typedef volatile unsigned int vuint32;
|
||||
|
||||
|
||||
#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
|
||||
|
||||
#define ATM_DPRAM_BEGIN (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
|
||||
#define NUM_CONNECTIONS 1
|
||||
#define SAR_RXB_SIZE 1584
|
||||
#define AM_HMASK 0x0FFFFFF0
|
||||
|
||||
#define NUM_CT_ENTRIES (NUM_CONNECTIONS)
|
||||
#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS)
|
||||
#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1)
|
||||
#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1)
|
||||
#define NUM_MPHYPT_ENTRIES 1
|
||||
#define NUM_APCP_ENTRIES 1
|
||||
#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */
|
||||
#define NUM_TQ_ENTRIES 12
|
||||
|
||||
#define SIZE_OF_CT_ENTRY 64
|
||||
#define SIZE_OF_TCTE_ENTRY 32
|
||||
#define SIZE_OF_AM_ENTRY 4
|
||||
#define SIZE_OF_AP_ENTRY 2
|
||||
#define SIZE_OF_MPHYPT_ENTRY 2
|
||||
#define SIZE_OF_APCP_ENTRY 32
|
||||
#define SIZE_OF_APCT_ENTRY 2
|
||||
#define SIZE_OF_TQ_ENTRY 2
|
||||
|
||||
#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */
|
||||
#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */
|
||||
#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */
|
||||
#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */
|
||||
#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
|
||||
#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */
|
||||
#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
|
||||
#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */
|
||||
#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */
|
||||
#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */
|
||||
#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
|
||||
|
||||
#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
|
||||
#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
|
||||
#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
|
||||
#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
|
||||
#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
|
||||
#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
|
||||
#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
|
||||
#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
|
||||
#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
|
||||
#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
|
||||
|
||||
/* SAR registers */
|
||||
#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
|
||||
#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */
|
||||
#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */
|
||||
#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
|
||||
#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */
|
||||
#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */
|
||||
#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */
|
||||
#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */
|
||||
#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
|
||||
#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */
|
||||
#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */
|
||||
#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
|
||||
#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */
|
||||
#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
|
||||
#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
|
||||
#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
|
||||
#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
|
||||
#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
|
||||
#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */
|
||||
#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
|
||||
#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
|
||||
#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
|
||||
#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
|
||||
#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
|
||||
#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
|
||||
#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
|
||||
#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
|
||||
#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
|
||||
#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
|
||||
#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
|
||||
#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */
|
||||
#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
|
||||
#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */
|
||||
#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */
|
||||
#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
|
||||
#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
|
||||
#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */
|
||||
#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
|
||||
#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
|
||||
#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
|
||||
#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
|
||||
#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */
|
||||
#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */
|
||||
#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
|
||||
#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */
|
||||
|
||||
/* ESAR registers */
|
||||
#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
|
||||
#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
|
||||
#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
|
||||
#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
|
||||
#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
|
||||
#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
|
||||
#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
|
||||
#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
|
||||
#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
|
||||
|
||||
/* UTOPIA Mode Register */
|
||||
#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978))
|
||||
|
||||
/* SAR commands */
|
||||
#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1
|
||||
#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
|
||||
#define STOP_TRANSMIT_CMD 0x2FC1
|
||||
#define RESTART_TRANSMIT_CMD 0x3FC1
|
||||
#define STOP_RECEIVE_CMD 0x4FC1
|
||||
#define RESTART_RECEIVE_CMD 0x5FC1
|
||||
#define APC_BYPASS_CMD 0x6FC1
|
||||
#define MEM_WRITE_CMD 0x7FC1
|
||||
#define CPCR_FLG 0x0001
|
||||
|
||||
/* INT flags */
|
||||
#define INT_VALID 0x80000000
|
||||
#define INT_WRAP 0x40000000
|
||||
#define INT_APCO 0x00800000
|
||||
#define INT_TQF 0x00200000
|
||||
#define INT_RXF 0x00080000
|
||||
#define INT_BSY 0x00040000
|
||||
#define INT_TXB 0x00020000
|
||||
#define INT_RXB 0x00010000
|
||||
|
||||
#define NUM_INT_ENTRIES 80
|
||||
#define SIZE_OF_INT_ENTRY 4
|
||||
|
||||
struct apc_params_t {
|
||||
vuint16 apct_base1; /* APC Table - First Priority Base pointer */
|
||||
vuint16 apct_end1; /* First APC Table - Length */
|
||||
vuint16 apct_ptr1; /* First APC Table Pointer */
|
||||
vuint16 apct_sptr1; /* APC Table First Priority Service pointer */
|
||||
vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */
|
||||
vuint16 etqend; /* Enhanced Transmit Queue End pointer */
|
||||
vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */
|
||||
vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */
|
||||
vuint16 apc_mi; /* APC - Max Iteration */
|
||||
vuint16 ncits; /* Number of Cells In TimeSlot */
|
||||
vuint16 apcnt; /* APC - N Timer */
|
||||
vuint16 reserved1; /* reserved */
|
||||
vuint16 eapcst; /* APC status */
|
||||
vuint16 ptp_counter; /* PTP queue length */
|
||||
vuint16 ptp_txch; /* PTP channel */
|
||||
vuint16 reserved2; /* reserved */
|
||||
};
|
||||
|
||||
struct ct_entry_t {
|
||||
/* RCT */
|
||||
unsigned fhnt:1;
|
||||
unsigned pm_rct:1;
|
||||
unsigned reserved0:6;
|
||||
unsigned hec:1;
|
||||
unsigned clp:1;
|
||||
unsigned cng_ncrc:1;
|
||||
unsigned inf_rct:1;
|
||||
unsigned cngi_ptp:1;
|
||||
unsigned cdis_rct:1;
|
||||
unsigned aal_rct:2;
|
||||
uint16 rbalen;
|
||||
uint32 rcrc;
|
||||
uint32 rb_ptr;
|
||||
uint16 rtmlen;
|
||||
uint16 rbd_ptr;
|
||||
uint16 rbase;
|
||||
uint16 tstamp;
|
||||
uint16 imask;
|
||||
unsigned ft:2;
|
||||
unsigned nim:1;
|
||||
unsigned reserved1:2;
|
||||
unsigned rpmt:6;
|
||||
unsigned reserved2:5;
|
||||
uint8 reserved3[8];
|
||||
/* TCT */
|
||||
unsigned reserved4:1;
|
||||
unsigned pm_tct:1;
|
||||
unsigned reserved5:6;
|
||||
unsigned pc:1;
|
||||
unsigned reserved6:2;
|
||||
unsigned inf_tct:1;
|
||||
unsigned cr10:1;
|
||||
unsigned cdis_tct:1;
|
||||
unsigned aal_tct:2;
|
||||
uint16 tbalen;
|
||||
uint32 tcrc;
|
||||
uint32 tb_ptr;
|
||||
uint16 ttmlen;
|
||||
uint16 tbd_ptr;
|
||||
uint16 tbase;
|
||||
unsigned reserved7:5;
|
||||
unsigned tpmt:6;
|
||||
unsigned reserved8:3;
|
||||
unsigned avcf:1;
|
||||
unsigned act:1;
|
||||
uint32 chead;
|
||||
uint16 apcl;
|
||||
uint16 apcpr;
|
||||
unsigned out:1;
|
||||
unsigned bnr:1;
|
||||
unsigned tservice:2;
|
||||
unsigned apcp:12;
|
||||
uint16 apcpf;
|
||||
};
|
||||
|
||||
struct tcte_entry_t {
|
||||
unsigned res1:4;
|
||||
unsigned scr:12;
|
||||
uint16 scrf;
|
||||
uint16 bt;
|
||||
uint16 buptrh;
|
||||
uint32 buptrl;
|
||||
unsigned vbr2:1;
|
||||
unsigned res2:15;
|
||||
uint16 oobr;
|
||||
uint16 res3[8];
|
||||
};
|
||||
|
||||
#define SIZE_OF_RBD 12
|
||||
#define SIZE_OF_TBD 12
|
||||
|
||||
struct atm_bd_t {
|
||||
vuint16 flags;
|
||||
vuint16 length;
|
||||
unsigned char *buffer_ptr;
|
||||
vuint16 cpcs_uu_cpi;
|
||||
vuint16 reserved;
|
||||
};
|
||||
|
||||
/* BD flags */
|
||||
#define EMPTY 0x8000
|
||||
#define READY 0x8000
|
||||
#define WRAP 0x2000
|
||||
#define INTERRUPT 0x1000
|
||||
#define LAST 0x0800
|
||||
#define FIRST 0x0400
|
||||
#define OAM 0x0400
|
||||
#define CONTINUOUS 0x0200
|
||||
#define HEC_ERROR 0x0080
|
||||
#define CELL_LOSS 0x0040
|
||||
#define CONGESTION 0x0020
|
||||
#define ABORT 0x0010
|
||||
#define LEN_ERROR 0x0002
|
||||
#define CRC_ERROR 0x0001
|
||||
|
||||
struct atm_connection_t {
|
||||
struct atm_bd_t *rbd_ptr;
|
||||
int num_rbd;
|
||||
struct atm_bd_t *tbd_ptr;
|
||||
int num_tbd;
|
||||
struct ct_entry_t *ct_ptr;
|
||||
struct tcte_entry_t *tcte_ptr;
|
||||
void *drv;
|
||||
void (*notify) (void *drv, int event);
|
||||
};
|
||||
|
||||
struct atm_driver_t {
|
||||
int loaded;
|
||||
int started;
|
||||
char *csram;
|
||||
int csram_size;
|
||||
uint32 *am_top;
|
||||
uint16 *ap_top;
|
||||
uint32 *int_reload_ptr;
|
||||
uint32 *int_serv_ptr;
|
||||
struct atm_bd_t *rbd_base_ptr;
|
||||
struct atm_bd_t *tbd_base_ptr;
|
||||
unsigned linerate_in_bps;
|
||||
};
|
||||
|
||||
extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
|
||||
extern struct atm_driver_t g_atm;
|
||||
|
||||
extern int atmLoad (void);
|
||||
extern void atmUnload (void);
|
||||
|
|
@ -0,0 +1,502 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
unsigned long size;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size, size<<20);
|
||||
}
|
||||
|
||||
|
||||
/* Remap FLASH according to real size */
|
||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
|
||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
flash_info[0].size = size;
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x0000C000;
|
||||
info->start[3] = base + 0x00010000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00020000) - 0x00060000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
info->start[i--] = base + info->size - 0x0000C000;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00020000;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ulong value;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
addr[0x0555] = 0x00900090;
|
||||
|
||||
value = addr[0];
|
||||
|
||||
switch (value) {
|
||||
case AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case AMD_ID_LV400T:
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case AMD_ID_LV400B:
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
case AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
#endif
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x0000C000;
|
||||
info->start[3] = base + 0x00010000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00020000) - 0x00060000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
info->start[i--] = base + info->size - 0x0000C000;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00020000;
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
info->protect[i] = addr[2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
|
||||
*addr = 0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
addr[0x0555] = 0x00800080;
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long*)(info->start[sect]);
|
||||
addr[0] = 0x00300030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_long*)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x00800080) != 0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
addr[0] = 0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
addr[0x0555] = 0x00A000A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
|
||||
net/libnet.o (.text*)
|
||||
drivers/rtc/librtc.o (.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end__ = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
|
||||
../../tqc/tqm8xx/load_sernum_ethaddr.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,488 @@
|
|||
/*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Flash Routines for AMD devices on the TQM8260 board
|
||||
*
|
||||
*--------------------------------------------------------------------
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
|
||||
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
|
||||
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_reset (void)
|
||||
{
|
||||
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
|
||||
V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
|
||||
V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
ulong flash_get_size (ulong baseaddr, flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
unsigned long flashtest_h, flashtest_l;
|
||||
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
|
||||
|
||||
flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */
|
||||
flashtest_l = V_ULONG (baseaddr + 4);
|
||||
|
||||
switch ((int) flashtest_h) {
|
||||
case AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
flashtest_h = V_ULONG (baseaddr + 8); /* device ID */
|
||||
flashtest_l = V_ULONG (baseaddr + 12);
|
||||
if (flashtest_h != flashtest_l) {
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
} else {
|
||||
switch (flashtest_h) {
|
||||
case AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000;
|
||||
break; /* 4 * 1 MB = 4 MB */
|
||||
case AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000;
|
||||
break; /* 4 * 1 MB = 4 MB */
|
||||
case AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00800000;
|
||||
break; /* 4 * 2 MB = 8 MB */
|
||||
case AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00800000;
|
||||
break; /* 4 * 2 MB = 8 MB */
|
||||
case AMD_ID_DL322T:
|
||||
info->flash_id += FLASH_AMDL322T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL322B:
|
||||
info->flash_id += FLASH_AMDL322B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL323T:
|
||||
info->flash_id += FLASH_AMDL323T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL323B:
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_LV640U:
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x02000000;
|
||||
break; /* 4 * 8 MB = 32 MB */
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
}
|
||||
|
||||
if (flashtest_h == AMD_ID_LV640U) {
|
||||
|
||||
/* set up sector start adress table (uniform sector type) */
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = baseaddr + (i * 0x00040000);
|
||||
|
||||
} else if (info->flash_id & FLASH_BTYPE) {
|
||||
|
||||
/* set up sector start adress table (bottom sector type) */
|
||||
info->start[0] = baseaddr + 0x00000000;
|
||||
info->start[1] = baseaddr + 0x00010000;
|
||||
info->start[2] = baseaddr + 0x00018000;
|
||||
info->start[3] = baseaddr + 0x00020000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
/* set up sector start adress table (top sector type) */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = baseaddr + info->size - 0x00010000;
|
||||
info->start[i--] = baseaddr + info->size - 0x00018000;
|
||||
info->start[i--] = baseaddr + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = baseaddr + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
|
||||
(V_ULONG (info->start[i] + 20) & 0x00010001)) {
|
||||
info->protect[i] = 1; /* D0 = 1 if protected */
|
||||
} else {
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
flash_reset ();
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0 = 0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here (only one bank) */
|
||||
|
||||
size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0 >> 20);
|
||||
}
|
||||
|
||||
/*
|
||||
* protect monitor and environment sectors
|
||||
*/
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
|
||||
# ifndef CONFIG_ENV_SIZE
|
||||
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
# endif
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
|
||||
#endif
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
printf ("FUJITSU ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM800T:
|
||||
printf ("29LV800T (8 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B:
|
||||
printf ("29LV800T (8 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AM160T:
|
||||
printf ("29LV160T (16 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B:
|
||||
printf ("29LV160B (16 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322T:
|
||||
printf ("29DL322T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322B:
|
||||
printf ("29DL322B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323T:
|
||||
printf ("29DL323T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B:
|
||||
printf ("29DL323B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AM640U:
|
||||
printf ("29LV640D (64 M, uniform sector)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
udelay (1000);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
V_ULONG (info->start[sect]) = 0x00300030;
|
||||
V_ULONG (info->start[sect] + 4) = 0x00300030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
|
||||
(V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
|
||||
{
|
||||
if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
flash_reset ();
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_dword (flash_info_t *, ulong, unsigned char *);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong dp;
|
||||
static unsigned char bb[8];
|
||||
int i, l, rc, cc = cnt;
|
||||
|
||||
dp = (addr & ~7); /* get lower dword aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - dp) != 0) {
|
||||
for (i = 0; i < 8; i++)
|
||||
bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
|
||||
if ((rc = write_dword (info, dp, bb)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
cc -= 8 - l;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cc >= 8) {
|
||||
if ((rc = write_dword (info, dp, src)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
src += 8;
|
||||
cc -= 8;
|
||||
}
|
||||
|
||||
if (cc <= 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
|
||||
}
|
||||
return (write_dword (info, dp, bb));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a dword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
|
||||
{
|
||||
ulong start, cl, ch;
|
||||
int flag, i;
|
||||
|
||||
for (ch = 0, i = 0; i < 4; i++)
|
||||
ch = (ch << 8) + *pdata++; /* high word */
|
||||
for (cl = 0, i = 0; i < 4; i++)
|
||||
cl = (cl << 8) + *pdata++; /* low word */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *) dest) & ch) != ch
|
||||
|| (*((vu_long *) (dest + 4)) & cl) != cl) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
|
||||
V_ULONG (dest) = ch;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
|
||||
V_ULONG (dest + 4) = cl;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
|
||||
((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8260.h>
|
||||
#include <common.h>
|
||||
#include "../common/fpga.h"
|
||||
|
||||
fpga_t fpga_list[] = {
|
||||
{"FIOX", CONFIG_SYS_FIOX_BASE,
|
||||
CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
|
||||
,
|
||||
{"FDOHM", CONFIG_SYS_FDOHM_BASE,
|
||||
CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
|
||||
};
|
||||
int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
|
||||
|
||||
|
||||
ulong fpga_control (fpga_t * fpga, int cmd)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
|
||||
switch (cmd) {
|
||||
case FPGA_INIT_IS_HIGH:
|
||||
immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
|
||||
return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
|
||||
|
||||
case FPGA_INIT_SET_LOW:
|
||||
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
|
||||
immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
|
||||
break;
|
||||
|
||||
case FPGA_INIT_SET_HIGH:
|
||||
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
|
||||
immr->im_ioport.iop_pdatd |= fpga->init_mask;
|
||||
break;
|
||||
|
||||
case FPGA_PROG_SET_LOW:
|
||||
immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
|
||||
break;
|
||||
|
||||
case FPGA_PROG_SET_HIGH:
|
||||
immr->im_ioport.iop_pdatd |= fpga->prog_mask;
|
||||
break;
|
||||
|
||||
case FPGA_DONE_IS_HIGH:
|
||||
return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
|
||||
|
||||
case FPGA_READ_MODE:
|
||||
break;
|
||||
|
||||
case FPGA_LOAD_MODE:
|
||||
break;
|
||||
|
||||
case FPGA_GET_ID:
|
||||
if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
|
||||
ulong ver =
|
||||
*(volatile ulong *) (fpga->conf_base + 0x10);
|
||||
return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
|
||||
} else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
|
||||
return (*(volatile ushort *) fpga->conf_base) & 0xff;
|
||||
} else {
|
||||
return *(volatile ulong *) fpga->conf_base;
|
||||
}
|
||||
|
||||
case FPGA_INIT_PORTS:
|
||||
immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
|
||||
immr->im_ioport.iop_psord &= ~fpga->init_mask;
|
||||
immr->im_ioport.iop_pdird &= ~fpga->init_mask;
|
||||
|
||||
immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
|
||||
immr->im_ioport.iop_psord &= ~fpga->prog_mask;
|
||||
immr->im_ioport.iop_pdird |= fpga->prog_mask;
|
||||
|
||||
immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
|
||||
immr->im_ioport.iop_psord &= ~fpga->done_mask;
|
||||
immr->im_ioport.iop_pdird &= ~fpga->done_mask;
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,541 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc8260.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#include "scm.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void config_scoh_cs(void);
|
||||
extern int fpga_init(void);
|
||||
|
||||
#if 0
|
||||
#define DEBUGF(fmt,args...) printf (fmt ,##args)
|
||||
#else
|
||||
#define DEBUGF(fmt,args...)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
|
||||
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
|
||||
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
|
||||
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
|
||||
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
|
||||
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
|
||||
/* PA25 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA24 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA23 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA22 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
|
||||
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
|
||||
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
|
||||
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
|
||||
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
|
||||
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/
|
||||
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
|
||||
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
|
||||
/* PA13 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA12 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA11 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA10 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */
|
||||
/* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */
|
||||
/* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */
|
||||
/* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */
|
||||
/* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */
|
||||
/* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */
|
||||
/* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */
|
||||
/* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */
|
||||
/* PA1 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */
|
||||
/* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */
|
||||
/* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */
|
||||
/* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */
|
||||
/* PB27 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PB26 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */
|
||||
/* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */
|
||||
/* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */
|
||||
/* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */
|
||||
/* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */
|
||||
/* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
|
||||
/* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
|
||||
/* PB18 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
|
||||
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
|
||||
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
|
||||
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
|
||||
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
|
||||
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
|
||||
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
|
||||
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
|
||||
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
|
||||
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
|
||||
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
|
||||
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
|
||||
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
|
||||
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
|
||||
/* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
|
||||
/* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */
|
||||
/* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */
|
||||
/* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */
|
||||
/* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */
|
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 },
|
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
|
||||
/* PC19 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PC18 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
|
||||
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
|
||||
/* PC15 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 },
|
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
|
||||
/* PC12 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
|
||||
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
|
||||
/* PC7 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
|
||||
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
|
||||
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
|
||||
},
|
||||
|
||||
/* Port D configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
|
||||
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
|
||||
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
|
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 },
|
||||
/* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */
|
||||
/* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */
|
||||
/* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
|
||||
/* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */
|
||||
/* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */
|
||||
/* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */
|
||||
/* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
|
||||
#else
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#else /* normal I/O port pins */
|
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#endif
|
||||
#endif
|
||||
/* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */
|
||||
/* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */
|
||||
/* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */
|
||||
/* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */
|
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 },
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 },
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
|
||||
/* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (!i || strncmp (str, "TQM8260", 7)) {
|
||||
puts ("### No HW ID - assuming TQM8260\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
puts (str);
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
|
||||
*
|
||||
* This routine performs standard 8260 initialization sequence
|
||||
* and calculates the available memory size. It may be called
|
||||
* several times to try different SDRAM configurations on both
|
||||
* 60x and local buses.
|
||||
*/
|
||||
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||
ulong orx, volatile uchar * base)
|
||||
{
|
||||
volatile uchar c = 0xff;
|
||||
volatile uint *sdmr_ptr;
|
||||
volatile uint *orx_ptr;
|
||||
ulong maxsize, size;
|
||||
int i;
|
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be
|
||||
* mapped by the controller. That means, that the initial mapping has
|
||||
* to be (at least) twice as large as the maximum expected size.
|
||||
*/
|
||||
maxsize = (1 + (~orx | 0x7fff)) / 2;
|
||||
|
||||
/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
|
||||
* we are configuring CS1 if base != 0
|
||||
*/
|
||||
sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
|
||||
orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
|
||||
|
||||
*orx_ptr = orx;
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
|
||||
*(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*base = c;
|
||||
|
||||
size = get_ram_size((long *)base, maxsize);
|
||||
|
||||
*orx_ptr = orx | ~(size - 1);
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*
|
||||
* Test Power-On-Reset.
|
||||
*/
|
||||
int power_on_reset (void)
|
||||
{
|
||||
/* Test Reset Status Register */
|
||||
return gd->reset_status & RSR_CSRS ? 0 : 1;
|
||||
}
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
long size8, size9;
|
||||
#endif
|
||||
long psize, lsize;
|
||||
|
||||
psize = 16 * 1024 * 1024;
|
||||
lsize = 0;
|
||||
|
||||
memctl->memc_psrt = CONFIG_SYS_PSRT;
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
#if 0 /* Just for debugging */
|
||||
#define prt_br_or(brX,orX) do { \
|
||||
ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
|
||||
ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
|
||||
printf ("\n" \
|
||||
#brX " 0x%08x " #orX " 0x%08x " \
|
||||
"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
|
||||
memctl->memc_ ## brX, memctl->memc_ ## orX, \
|
||||
start, start+sizem, (sizem+1)>>20); \
|
||||
} while (0)
|
||||
prt_br_or (br0, or0);
|
||||
prt_br_or (br1, or1);
|
||||
prt_br_or (br2, or2);
|
||||
prt_br_or (br3, or3);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* 60x SDRAM setup:
|
||||
*/
|
||||
size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
|
||||
if (size8 < size9) {
|
||||
psize = size9;
|
||||
printf ("(60x:9COL - %ld MB, ", psize >> 20);
|
||||
} else {
|
||||
psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
printf ("(60x:8COL - %ld MB, ", psize >> 20);
|
||||
}
|
||||
|
||||
/* Local SDRAM setup:
|
||||
*/
|
||||
#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
|
||||
memctl->memc_lsrt = CONFIG_SYS_LSRT;
|
||||
size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
|
||||
if (size8 < size9) {
|
||||
lsize = size9;
|
||||
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
|
||||
} else {
|
||||
lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Set up BR2 so that the local SDRAM goes
|
||||
* right after the 60x SDRAM
|
||||
*/
|
||||
memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
|
||||
(CONFIG_SYS_SDRAM_BASE + psize);
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
icache_enable ();
|
||||
|
||||
config_scoh_cs ();
|
||||
|
||||
return (psize);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void config_scoh_cs (void)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immr->im_memctl;
|
||||
volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
|
||||
__maybe_unused volatile uint tmp, i;
|
||||
|
||||
/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
|
||||
memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
|
||||
memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
|
||||
/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
|
||||
memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
|
||||
memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
|
||||
|
||||
/* Initialize MAMR to write in the array at address 0x0 */
|
||||
memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
|
||||
|
||||
/* Initialize UPMA for CAN: single read */
|
||||
memctl->memc_mdr = 0xcffeec00;
|
||||
udelay (1); /* Necessary to have the data correct in the UPM array!!!! */
|
||||
/* The read on the CAN controller write the data of mdr in UPMA array. */
|
||||
/* The index to the array will be incremented automatically
|
||||
through this read */
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcfc00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x0ffcfc00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0xfffdec07;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
|
||||
/* Initialize MAMR to write in the array at address 0x18 */
|
||||
memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
|
||||
|
||||
/* Initialize UPMA for CAN: single write */
|
||||
memctl->memc_mdr = 0xfcffec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00ffec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00ffec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00ffec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00ffec00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00fffc00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x00fffc00;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
memctl->memc_mdr = 0x30ffec07;
|
||||
udelay (1);
|
||||
tmp = can->cpu_interface;
|
||||
|
||||
/* Initialize MAMR */
|
||||
memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
|
||||
|
||||
|
||||
/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
|
||||
memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
|
||||
memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
|
||||
/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
|
||||
memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
|
||||
memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
|
||||
|
||||
/* Initialize OR7 / BR7 for the Glue Logic */
|
||||
memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
|
||||
memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
|
||||
|
||||
/* Initialize OR8 / BR8 for the DOH Logic */
|
||||
memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
|
||||
memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
|
||||
|
||||
DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
|
||||
DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
|
||||
DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
|
||||
DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
|
||||
DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
|
||||
DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
|
||||
DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
|
||||
DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
|
||||
DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
|
||||
|
||||
DEBUGF ("UPMA addr 0x0\n");
|
||||
memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
|
||||
for (i = 0; i < 0x8; i++) {
|
||||
tmp = can->cpu_interface;
|
||||
udelay (1);
|
||||
DEBUGF (" %08x ", memctl->memc_mdr);
|
||||
}
|
||||
DEBUGF ("\nUPMA addr 0x18\n");
|
||||
memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
|
||||
for (i = 0; i < 0x8; i++) {
|
||||
tmp = can->cpu_interface;
|
||||
udelay (1);
|
||||
DEBUGF (" %08x ", memctl->memc_mdr);
|
||||
}
|
||||
DEBUGF ("\n");
|
||||
memctl->memc_mamr = MxMR_GPL_x4DIS;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
fpga_init ();
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SCM_H
|
||||
#define __SCM_H
|
||||
|
||||
/*----------------*/
|
||||
/* CAN Structures */
|
||||
/*----------------*/
|
||||
|
||||
/* Message */
|
||||
struct can_msg {
|
||||
uchar ctrl_0;
|
||||
uchar ctrl_1;
|
||||
uchar arbit_0;
|
||||
uchar arbit_1;
|
||||
uchar arbit_2;
|
||||
uchar arbit_3;
|
||||
uchar config;
|
||||
uchar data[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
typedef struct can_msg can_msg_t;
|
||||
|
||||
/* CAN Register */
|
||||
typedef struct can_reg {
|
||||
uchar ctrl;
|
||||
uchar status;
|
||||
uchar cpu_interface;
|
||||
uchar resv0;
|
||||
ushort high_speed_rd;
|
||||
ushort gbl_mask_std;
|
||||
uint gbl_mask_extd;
|
||||
uint msg15_mask;
|
||||
can_msg_t msg1;
|
||||
uchar clkout;
|
||||
can_msg_t msg2;
|
||||
uchar bus_config;
|
||||
can_msg_t msg3;
|
||||
uchar bit_timing_0;
|
||||
can_msg_t msg4;
|
||||
uchar bit_timing_1;
|
||||
can_msg_t msg5;
|
||||
uchar interrupt;
|
||||
can_msg_t msg6;
|
||||
uchar resv1;
|
||||
can_msg_t msg7;
|
||||
uchar resv2;
|
||||
can_msg_t msg8;
|
||||
uchar resv3;
|
||||
can_msg_t msg9;
|
||||
uchar p1conf;
|
||||
can_msg_t msg10;
|
||||
uchar p2conf;
|
||||
can_msg_t msg11;
|
||||
uchar p1in;
|
||||
can_msg_t msg12;
|
||||
uchar p2in;
|
||||
can_msg_t msg13;
|
||||
uchar p1out;
|
||||
can_msg_t msg14;
|
||||
uchar p2out;
|
||||
can_msg_t msg15;
|
||||
uchar ser_res_addr;
|
||||
uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */
|
||||
} can_reg_t;
|
||||
|
||||
|
||||
#endif /* __SCM_H */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
|
||||
-------------------------------------------
|
||||
|
||||
Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
|
||||
|
||||
=> help fpga
|
||||
fpga fpga status [name] - print FPGA status
|
||||
fpga reset [name] - reset FPGA
|
||||
fpga load [name] addr - load FPGA configuration data
|
||||
|
||||
Der Name kann beim CCM-Module auch weggelassen werden.
|
||||
Die Laengenangabe und damit "puma_len" ist nicht mehr
|
||||
noetig:
|
||||
|
||||
=> fpga load puma 40600000
|
||||
FPGA load PUMA: addr 40600000: (00000005)... done
|
||||
|
||||
Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
|
||||
geben werden:
|
||||
|
||||
=> printenv addmtd
|
||||
addmtd=setenv bootargs ${bootargs}
|
||||
mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
|
||||
|
||||
Die Portierung auf SMC ist natuerlich noch nicht getestet.
|
||||
|
||||
Wolfgang Grandegger (04.06.2002)
|
||||
|
|
@ -0,0 +1,369 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <common.h>
|
||||
|
||||
#include "fpga.h"
|
||||
|
||||
int power_on_reset(void);
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
|
||||
static int fpga_get_version(fpga_t* fpga, char* name)
|
||||
{
|
||||
char vname[12];
|
||||
/*
|
||||
* Net-list string format:
|
||||
* "vvvvvvvvddddddddn...".
|
||||
* Version Date Name
|
||||
* "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
|
||||
*/
|
||||
if (strlen(name) < (16 + strlen(fpga->name)))
|
||||
goto failure;
|
||||
/* Check FPGA name */
|
||||
if (strcmp(&name[16], fpga->name) != 0)
|
||||
goto failure;
|
||||
/* Get version number */
|
||||
memcpy(vname, name, 8);
|
||||
vname[8] = '\0';
|
||||
return simple_strtoul(vname, NULL, 16);
|
||||
|
||||
failure:
|
||||
printf("Image name %s is invalid\n", name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
static fpga_t* fpga_get(char* fpga_name)
|
||||
{
|
||||
char name[FPGA_NAME_LEN];
|
||||
int i;
|
||||
|
||||
if (strlen(fpga_name) >= FPGA_NAME_LEN)
|
||||
goto failure;
|
||||
for (i = 0; i < strlen(fpga_name); i++)
|
||||
name[i] = toupper(fpga_name[i]);
|
||||
name[i] = '\0';
|
||||
for (i = 0; i < fpga_count; i++) {
|
||||
if (strcmp(name, fpga_list[i].name) == 0)
|
||||
return &fpga_list[i];
|
||||
}
|
||||
failure:
|
||||
printf("FPGA: name %s is invalid\n", fpga_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
static void fpga_status (fpga_t* fpga)
|
||||
{
|
||||
/* Check state */
|
||||
if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
|
||||
printf ("%s is loaded (%08lx)\n",
|
||||
fpga->name, fpga_control(fpga, FPGA_GET_ID));
|
||||
else
|
||||
printf ("%s is NOT loaded\n", fpga->name);
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
|
||||
|
||||
static int fpga_reset (fpga_t* fpga)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Set PROG to low and wait til INIT goes low */
|
||||
fpga_control(fpga, FPGA_PROG_SET_LOW);
|
||||
for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
|
||||
udelay (100);
|
||||
if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
|
||||
break;
|
||||
}
|
||||
if (i == FPGA_RESET_TIMEOUT)
|
||||
goto failure;
|
||||
|
||||
/* Set PROG to high and wait til INIT goes high */
|
||||
fpga_control(fpga, FPGA_PROG_SET_HIGH);
|
||||
for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
|
||||
udelay (100);
|
||||
if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
|
||||
break;
|
||||
}
|
||||
if (i == FPGA_RESET_TIMEOUT)
|
||||
goto failure;
|
||||
|
||||
return 0;
|
||||
failure:
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
|
||||
|
||||
static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
|
||||
{
|
||||
volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
|
||||
image_header_t *hdr = (image_header_t *)addr;
|
||||
ulong len;
|
||||
uchar *data;
|
||||
char msg[32];
|
||||
int verify, i;
|
||||
|
||||
#if defined(CONFIG_FIT)
|
||||
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
|
||||
puts ("Non legacy image format not supported\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check the image header and data of the net-list
|
||||
*/
|
||||
if (!image_check_magic (hdr)) {
|
||||
strcpy (msg, "Bad Image Magic Number");
|
||||
goto failure;
|
||||
}
|
||||
|
||||
if (!image_check_hcrc (hdr)) {
|
||||
strcpy (msg, "Bad Image Header CRC");
|
||||
goto failure;
|
||||
}
|
||||
|
||||
data = (uchar*)image_get_data (hdr);
|
||||
len = image_get_data_size (hdr);
|
||||
|
||||
verify = getenv_yesno ("verify");
|
||||
if (verify) {
|
||||
if (!image_check_dcrc (hdr)) {
|
||||
strcpy (msg, "Bad Image Data CRC");
|
||||
goto failure;
|
||||
}
|
||||
}
|
||||
|
||||
if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
|
||||
return 1;
|
||||
|
||||
/* align length */
|
||||
if (len & 1)
|
||||
++len;
|
||||
|
||||
/*
|
||||
* Reset FPGA and wait for completion
|
||||
*/
|
||||
if (fpga_reset(fpga)) {
|
||||
strcpy (msg, "Reset Timeout");
|
||||
goto failure;
|
||||
}
|
||||
|
||||
printf ("(%s)... ", image_get_name (hdr));
|
||||
/*
|
||||
* Copy data to FPGA
|
||||
*/
|
||||
fpga_control (fpga, FPGA_LOAD_MODE);
|
||||
while (len--) {
|
||||
*fpga_addr = *data++;
|
||||
}
|
||||
fpga_control (fpga, FPGA_READ_MODE);
|
||||
|
||||
/*
|
||||
* Wait for completion and check error status if timeout
|
||||
*/
|
||||
for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
|
||||
udelay (100);
|
||||
if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
|
||||
break;
|
||||
}
|
||||
if (i == FPGA_LOAD_TIMEOUT) {
|
||||
if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
|
||||
strcpy(msg, "Invalid Size");
|
||||
else
|
||||
strcpy(msg, "CRC Error");
|
||||
goto failure;
|
||||
}
|
||||
|
||||
printf("done\n");
|
||||
return 0;
|
||||
|
||||
failure:
|
||||
|
||||
printf("ERROR: %s\n", msg);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr = 0;
|
||||
int i;
|
||||
fpga_t* fpga;
|
||||
|
||||
if (argc < 2)
|
||||
goto failure;
|
||||
|
||||
if (strncmp(argv[1], "stat", 4) == 0) { /* status */
|
||||
if (argc == 2) {
|
||||
for (i = 0; i < fpga_count; i++) {
|
||||
fpga_status (&fpga_list[i]);
|
||||
}
|
||||
}
|
||||
else if (argc == 3) {
|
||||
if ((fpga = fpga_get(argv[2])) == 0)
|
||||
goto failure;
|
||||
fpga_status (fpga);
|
||||
}
|
||||
else
|
||||
goto failure;
|
||||
}
|
||||
else if (strcmp(argv[1],"load") == 0) { /* load */
|
||||
if (argc == 3 && fpga_count == 1) {
|
||||
fpga = &fpga_list[0];
|
||||
}
|
||||
else if (argc == 4) {
|
||||
if ((fpga = fpga_get(argv[2])) == 0)
|
||||
goto failure;
|
||||
}
|
||||
else
|
||||
goto failure;
|
||||
|
||||
addr = simple_strtoul(argv[argc-1], NULL, 16);
|
||||
|
||||
printf ("FPGA load %s: addr %08lx: ",
|
||||
fpga->name, addr);
|
||||
fpga_load (fpga, addr, 1);
|
||||
|
||||
}
|
||||
else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
|
||||
if (argc == 2 && fpga_count == 1) {
|
||||
fpga = &fpga_list[0];
|
||||
}
|
||||
else if (argc == 3) {
|
||||
if ((fpga = fpga_get(argv[2])) == 0)
|
||||
goto failure;
|
||||
}
|
||||
else
|
||||
goto failure;
|
||||
|
||||
printf ("FPGA reset %s: ", fpga->name);
|
||||
if (fpga_reset(fpga))
|
||||
printf ("ERROR: Timeout\n");
|
||||
else
|
||||
printf ("done\n");
|
||||
}
|
||||
else
|
||||
goto failure;
|
||||
|
||||
return 0;
|
||||
|
||||
failure:
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
fpga, 4, 1, do_fpga,
|
||||
"access FPGA(s)",
|
||||
"fpga status [name] - print FPGA status\n"
|
||||
"fpga reset [name] - reset FPGA\n"
|
||||
"fpga load [name] addr - load FPGA configuration data"
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
int fpga_init (void)
|
||||
{
|
||||
ulong addr;
|
||||
ulong new_id, old_id = 0;
|
||||
image_header_t *hdr;
|
||||
fpga_t* fpga;
|
||||
int do_load, i, j;
|
||||
char name[16], *s;
|
||||
|
||||
/*
|
||||
* Port setup for FPGA control
|
||||
*/
|
||||
for (i = 0; i < fpga_count; i++) {
|
||||
fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
|
||||
}
|
||||
|
||||
/*
|
||||
* Load FPGA(s): a new net-list is loaded if the FPGA is
|
||||
* empty, Power-on-Reset or the old one is not up-to-date
|
||||
*/
|
||||
for (i = 0; i < fpga_count; i++) {
|
||||
fpga = &fpga_list[i];
|
||||
printf ("%s: ", fpga->name);
|
||||
|
||||
for (j = 0; j < strlen(fpga->name); j++)
|
||||
name[j] = tolower(fpga->name[j]);
|
||||
name[j] = '\0';
|
||||
sprintf(name, "%s_addr", name);
|
||||
addr = 0;
|
||||
if ((s = getenv(name)) != NULL)
|
||||
addr = simple_strtoul(s, NULL, 16);
|
||||
|
||||
if (!addr) {
|
||||
printf ("env. variable %s undefined\n", name);
|
||||
return 1;
|
||||
}
|
||||
|
||||
hdr = (image_header_t *)addr;
|
||||
#if defined(CONFIG_FIT)
|
||||
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
|
||||
puts ("Non legacy image format not supported\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
|
||||
return 1;
|
||||
|
||||
do_load = 1;
|
||||
|
||||
if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
|
||||
old_id = fpga_control(fpga, FPGA_GET_ID);
|
||||
if (new_id == old_id)
|
||||
do_load = 0;
|
||||
}
|
||||
|
||||
if (do_load) {
|
||||
printf ("loading ");
|
||||
fpga_load (fpga, addr, 0);
|
||||
} else {
|
||||
printf ("loaded (%08lx)\n", old_id);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FPGA_H_
|
||||
#define _FPGA_H_
|
||||
|
||||
#define FPGA_INIT_IS_HIGH 0
|
||||
#define FPGA_INIT_SET_HIGH 1
|
||||
#define FPGA_INIT_SET_LOW 2
|
||||
#define FPGA_PROG_SET_HIGH 3
|
||||
#define FPGA_PROG_SET_LOW 4
|
||||
#define FPGA_DONE_IS_HIGH 5
|
||||
#define FPGA_READ_MODE 6
|
||||
#define FPGA_LOAD_MODE 7
|
||||
#define FPGA_GET_ID 8
|
||||
#define FPGA_INIT_PORTS 9
|
||||
|
||||
#define FPGA_NAME_LEN 8
|
||||
typedef struct {
|
||||
char name[FPGA_NAME_LEN];
|
||||
ulong conf_base;
|
||||
uint init_mask;
|
||||
uint prog_mask;
|
||||
uint done_mask;
|
||||
} fpga_t;
|
||||
|
||||
extern fpga_t fpga_list[];
|
||||
extern int fpga_count;
|
||||
|
||||
ulong fpga_control (fpga_t* fpga, int cmd);
|
||||
|
||||
#endif /* _FPGA_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue