mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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||||
#
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||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-y += flash.o
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COBJS-$(CONFIG_FSL_DDR1) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,46 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/* 2T timing enable */
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popts->twoT_en = 1;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@ -0,0 +1,515 @@
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/*
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* (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. <dan@embeddededge.com>
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* Copied from ADS85xx.
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* Updated to support the Silicon Tx GP3 8560. We should only find
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* two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash),
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* but I left other code here in case people order custom boards.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao,(X.Xiao@motorola.com)
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*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* Add support the Sharp chips on the mpc8260ads.
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* I started with board/ip860/flash.c and made changes I found in
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* the MTD project by David Schleef.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if !defined(CONFIG_SYS_NO_FLASH)
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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#if defined(CONFIG_ENV_IS_IN_FLASH)
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# ifndef CONFIG_ENV_ADDR
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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# endif
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# ifndef CONFIG_ENV_SIZE
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# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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# endif
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# ifndef CONFIG_ENV_SECT_SIZE
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# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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# endif
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#endif
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#undef DEBUG
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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static int clear_block_lock_bit(vu_long * addr);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size;
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int i;
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/* Init: enable write,
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* or we cannot even write flash commands
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*/
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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/* set the default sector offset */
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size, size<<20);
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}
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/* Re-do sizing to get full correct info */
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size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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flash_info[0].size = size;
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
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&flash_info[0]);
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#endif
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#endif
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return (size);
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL: printf ("Intel "); break;
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case FLASH_MAN_SHARP: printf ("Sharp "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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{
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short i;
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ulong value;
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ulong base = (ulong)addr;
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ulong sector_offset;
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#ifdef DEBUG
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printf("Check flash at 0x%08x\n",(uint)addr);
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#endif
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/* Write "Intelligent Identifier" command: read Manufacturer ID */
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*addr = 0x90909090;
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udelay(20);
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asm("sync");
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value = addr[0] & 0x00FF00FF;
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#ifdef DEBUG
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printf("manufacturer=0x%x\n",(uint)value);
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#endif
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switch (value) {
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case MT_MANUFACT: /* SHARP, MT or => Intel */
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case INTEL_ALT_MANU:
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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printf("unknown manufacturer: %x\n", (unsigned int)value);
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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value = addr[1]; /* device ID */
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#ifdef DEBUG
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printf("deviceID=0x%x\n",(uint)value);
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#endif
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switch (value) {
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case (INTEL_ID_28F640C3T):
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info->flash_id += FLASH_28F640C3T;
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info->sector_count = 135;
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info->size = 0x01000000;
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sector_offset = 0x20000;
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break; /* => 2x8 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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/* set up sector start address table
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* The first 127 blocks are large, the last 8 are small.
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*/
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for (i = 0; i < 127; i++) {
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info->start[i] = base;
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base += sector_offset;
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/* Sectors are locked upon reset */
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info->protect[i] = 0;
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}
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for (i = 127; i < 135; i++) {
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info->start[i] = base;
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base += 0x4000;
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/* Sectors are locked upon reset */
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info->protect[i] = 0;
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}
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||||
|
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|
||||
/*
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||||
* Prevent writes to uninitialized FLASH.
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||||
*/
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if (info->flash_id != FLASH_UNKNOWN) {
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addr = (vu_long *)info->start[0];
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*addr = 0xFFFFFF; /* reset bank to read array mode */
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asm("sync");
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}
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|
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return (info->size);
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}
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||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
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int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
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printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
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return 1;
|
||||
}
|
||||
|
||||
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
|
||||
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("\nFlash Erase:\n");
|
||||
#endif
|
||||
/* Make Sure Block Lock Bit is not set. */
|
||||
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
#if defined(DEBUG)
|
||||
printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
|
||||
#endif
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
vu_long *addr = (vu_long *)(info->start[sect]);
|
||||
asm("sync");
|
||||
|
||||
last = start = get_timer (0);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Reset Array */
|
||||
*addr = 0xffffffff;
|
||||
asm("sync");
|
||||
/* Clear Status Register */
|
||||
*addr = 0x50505050;
|
||||
asm("sync");
|
||||
/* Single Block Erase Command */
|
||||
*addr = 0x20202020;
|
||||
asm("sync");
|
||||
/* Confirm */
|
||||
*addr = 0xD0D0D0D0;
|
||||
asm("sync");
|
||||
|
||||
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
|
||||
/* Resume Command, as per errata update */
|
||||
*addr = 0xD0D0D0D0;
|
||||
asm("sync");
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
while ((*addr & 0x00800080) != 0x00800080) {
|
||||
if(*addr & 0x00200020){
|
||||
printf("Error in Block Erase - Lock Bit may be set!\n");
|
||||
printf("Status Register = 0x%X\n", (uint)*addr);
|
||||
*addr = 0xFFFFFFFF; /* reset bank */
|
||||
asm("sync");
|
||||
return 1;
|
||||
}
|
||||
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
*addr = 0xFFFFFFFF; /* reset bank */
|
||||
asm("sync");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
/* reset to read mode */
|
||||
*addr = 0xFFFFFFFF;
|
||||
asm("sync");
|
||||
}
|
||||
}
|
||||
|
||||
printf ("flash erase done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long *)dest;
|
||||
ulong start, csr;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Write Command */
|
||||
*addr = 0x10101010;
|
||||
asm("sync");
|
||||
|
||||
/* Write Data */
|
||||
*addr = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
flag = 0;
|
||||
|
||||
while (((csr = *addr) & 0x00800080) != 0x00800080) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
flag = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (csr & 0x40404040) {
|
||||
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
|
||||
flag = 1;
|
||||
}
|
||||
|
||||
/* Clear Status Registers Command */
|
||||
*addr = 0x50505050;
|
||||
asm("sync");
|
||||
/* Reset to read array mode */
|
||||
*addr = 0xFFFFFFFF;
|
||||
asm("sync");
|
||||
|
||||
return (flag);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clear Block Lock Bit, returns:
|
||||
* 0 - OK
|
||||
* 1 - Timeout
|
||||
*/
|
||||
|
||||
static int clear_block_lock_bit(vu_long * addr)
|
||||
{
|
||||
ulong start, now;
|
||||
|
||||
/* Reset Array */
|
||||
*addr = 0xffffffff;
|
||||
asm("sync");
|
||||
/* Clear Status Register */
|
||||
*addr = 0x50505050;
|
||||
asm("sync");
|
||||
|
||||
*addr = 0x60606060;
|
||||
asm("sync");
|
||||
*addr = 0xd0d0d0d0;
|
||||
asm("sync");
|
||||
|
||||
start = get_timer (0);
|
||||
while((*addr & 0x00800080) != 0x00800080){
|
||||
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout on clearing Block Lock Bit\n");
|
||||
*addr = 0xFFFFFFFF; /* reset bank */
|
||||
asm("sync");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_SYS_NO_FLASH */
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
|
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
|
||||
* 0xfc00_0000 0xfc00_ffff Config Latch 64K
|
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
|
||||
*
|
||||
* Notes:
|
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*/
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
|
||||
#endif
|
||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
|
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */
|
||||
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
|
||||
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* (C) Copyright 2003, Embedded Edge, LLC
|
||||
* Dan Malek, <dan@embeddededge.com>
|
||||
* Copied from ADS85xx.
|
||||
* Updates for Silicon Tx GP3 8560
|
||||
*
|
||||
* (C) Copyright 2003,Motorola Inc.
|
||||
* Xianghua Xiao, (X.Xiao@motorola.com)
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <ioports.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
|
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
|
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
|
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
|
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
|
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
|
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
|
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
|
||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
|
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
static uint64_t next_led_update;
|
||||
static uint led_bit;
|
||||
|
||||
int
|
||||
board_early_init_f(void)
|
||||
{
|
||||
#if defined(CONFIG_PCI)
|
||||
volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
|
||||
|
||||
pci->peer &= 0xfffffffdf; /* disable master abort */
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
reset_phy(void)
|
||||
{
|
||||
volatile uint *blatch;
|
||||
|
||||
blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
|
||||
|
||||
/* reset Giga bit Ethernet port if needed here */
|
||||
|
||||
*blatch &= ~0x000000c0;
|
||||
udelay(100);
|
||||
*blatch = 0x000000c1; /* Light one led, too */
|
||||
udelay(1000);
|
||||
|
||||
#if 0 /* This is the port we really want to use for debugging. */
|
||||
/* reset the CPM FEC port */
|
||||
#if (CONFIG_ETHER_INDEX == 2)
|
||||
bcsr->bcsr2 &= ~FETH2_RST;
|
||||
udelay(2);
|
||||
bcsr->bcsr2 |= FETH2_RST;
|
||||
udelay(1000);
|
||||
#elif (CONFIG_ETHER_INDEX == 3)
|
||||
bcsr->bcsr3 &= ~FETH3_RST;
|
||||
udelay(2);
|
||||
bcsr->bcsr3 |= FETH3_RST;
|
||||
udelay(1000);
|
||||
#endif
|
||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
|
||||
/* reset PHY */
|
||||
miiphy_reset("FCC1", 0x0);
|
||||
|
||||
/* change PHY address to 0x02 */
|
||||
bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
|
||||
|
||||
bb_miiphy_write(NULL, 0x02, MII_BMCR,
|
||||
BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
#endif /* CONFIG_MII */
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
checkboard(void)
|
||||
{
|
||||
printf ("Board: Silicon Tx GPPP 8560 Board\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Blinkin' LEDS for Robert.
|
||||
*/
|
||||
void
|
||||
show_activity(int flag)
|
||||
{
|
||||
volatile uint *blatch;
|
||||
|
||||
if (next_led_update > get_ticks())
|
||||
return;
|
||||
|
||||
blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
|
||||
|
||||
led_bit >>= 1;
|
||||
if (led_bit == 0)
|
||||
led_bit = 0x08;
|
||||
*blatch = (0xc0 | led_bit);
|
||||
eieio();
|
||||
next_led_update += (get_tbclk() / 4);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_SYS_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
|
||||
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_stxgp3_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
||||
} },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table: pci_stxgp3_config_table,
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_mpc85xx_init(&hose);
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI1 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
* 0xc0000000 256M Rapid IO MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded
|
||||
* 0xd0000000 256M Rapid IO MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 16M PCI1 IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded
|
||||
* 0xfc000000 16K Configuration Latch register
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_16K, 1),
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* TLB 8, 9: 128M DDR
|
||||
* 0x00000000 64M DDR System memory
|
||||
* 0x04000000 64M DDR System memory
|
||||
* Without SPD EEPROM configured DDR, this must be setup manually.
|
||||
* Make sure the TLB count at the top of this table is correct.
|
||||
* Likely it needs to be increased by two for these entries.
|
||||
*/
|
||||
#error("Update the number of table entries in tlb1_entry")
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 8, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 9, BOOKE_PAGESZ_64M, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
Loading…
Add table
Add a link
Reference in a new issue