mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2004-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := sx1.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,19 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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#
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# SX1 board with OMAP1510 (ARM925T) cpu
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# see http://www.ti.com/ for more information on Texas Insturments
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#
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# SX1 has 1 bank of 256 MB SDRAM
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# Physical Address:
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# 1000'0000 to 2000'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
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#
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# we load ourself to 1108'0000
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#
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#
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CONFIG_SYS_TEXT_BASE = 0x11080000
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@ -0,0 +1,397 @@
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/*
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* Board specific setup info
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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*
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* -- Some bits of code used from rrload's head_OMAP1510.s --
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* Copyright (C) 2002 RidgeRun, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_OMAP1510)
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#include <./configs/omap1510.h>
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#endif
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#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Configure 1510 pins functions to match our board.
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*/
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ldr r0, REG_PULL_DWN_CTRL_0
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ldr r1, VAL_PULL_DWN_CTRL_0
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_1
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ldr r1, VAL_PULL_DWN_CTRL_1
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_2
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ldr r1, VAL_PULL_DWN_CTRL_2
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str r1, [r0]
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ldr r0, REG_PULL_DWN_CTRL_3
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ldr r1, VAL_PULL_DWN_CTRL_3
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_4
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ldr r1, VAL_FUNC_MUX_CTRL_4
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_5
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ldr r1, VAL_FUNC_MUX_CTRL_5
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_6
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ldr r1, VAL_FUNC_MUX_CTRL_6
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_7
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ldr r1, VAL_FUNC_MUX_CTRL_7
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_8
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ldr r1, VAL_FUNC_MUX_CTRL_8
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_9
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ldr r1, VAL_FUNC_MUX_CTRL_9
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_A
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ldr r1, VAL_FUNC_MUX_CTRL_A
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_B
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ldr r1, VAL_FUNC_MUX_CTRL_B
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_C
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ldr r1, VAL_FUNC_MUX_CTRL_C
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str r1, [r0]
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ldr r0, REG_FUNC_MUX_CTRL_D
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ldr r1, VAL_FUNC_MUX_CTRL_D
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str r1, [r0]
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ldr r0, REG_VOLTAGE_CTRL_0
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ldr r1, VAL_VOLTAGE_CTRL_0
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str r1, [r0]
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ldr r0, REG_TEST_DBG_CTRL_0
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ldr r1, VAL_TEST_DBG_CTRL_0
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str r1, [r0]
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ldr r0, REG_MOD_CONF_CTRL_0
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ldr r1, VAL_MOD_CONF_CTRL_0
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str r1, [r0]
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/* Move to 1510 mode */
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ldr r0, REG_COMP_MODE_CTRL_0
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ldr r1, VAL_COMP_MODE_CTRL_0
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str r1, [r0]
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/* Set up Traffic Ctlr*/
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ldr r0, REG_TC_IMIF_PRIO
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mov r1, #0x0
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str r1, [r0]
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ldr r0, REG_TC_EMIFS_PRIO
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str r1, [r0]
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ldr r0, REG_TC_EMIFF_PRIO
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str r1, [r0]
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ldr r0, REG_TC_EMIFS_CONFIG
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ldr r1, [r0]
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bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
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bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
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str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
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ldr r0, _GPIO_PIN_CONTROL_REG
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mov r1,#0
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orr r1, r1, #0x0001 /* M_PCM_SYNC */
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orr r1, r1, #0x4000 /* IPC_ACTIVE */
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strh r1,[r0]
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ldr r0, _GPIO_DIR_CONTROL_REG
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mov r1,#0
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bic r1, r1, #0x0001 /* M_PCM_SYNC */
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bic r1, r1, #0x4000 /* IPC_ACTIVE */
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strh r1,[r0]
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ldr r0, _GPIO_DATA_OUTPUT_REG
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mov r1,#0
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bic r1, r1, #0x0001 /* M_PCM_SYNC */
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orr r1, r1, #0x4000 /* IPC_ACTIVE */
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strh r1,[r0]
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/* Setup some clock domains */
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ldr r1, =OMAP1510_CLKS
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ldr r0, REG_ARM_IDLECT2
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strh r1, [r0] /* CLKM, Clock domain control. */
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mov r1, #0x01 /* PER_EN bit */
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ldr r0, REG_ARM_RSTCT2
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* Set CLKM to Sync-Scalable */
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/* I supposidly need to enable the dsp clock before switching */
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mov r1, #0x1000
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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1:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 1b
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ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* setup DPLL 1 */
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ldr r1, VAL_DPLL1_CTL
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ldr r0, REG_DPLL1_CTL
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strh r1, [r0]
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ands r1, r1, #0x10 /* Check if PLL is enabled. */
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beq lock_end /* Do not look for lock if BYPASS selected */
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2:
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ldrh r1, [r0]
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ands r1, r1, #0x01 /* Check the LOCK bit. */
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beq 2b /* ...loop until bit goes hi. */
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lock_end:
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/* Set memory timings corresponding to the new clock speed */
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/* Check execution location to determine current execution location
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* and branch to appropriate initialization code.
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*/
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mov r0, #0x10000000 /* Load physical SDRAM base. */
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mov r1, pc /* Get current execution location. */
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cmp r1, r0 /* Compare. */
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bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800 /* value should be checked */
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3:
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subs r3, r3, #0x1 /* Decrement count */
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bne 3b
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/*
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* Set SDRAM control values. Disable refresh before MRS command.
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*/
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ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
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bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
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orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
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orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
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ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
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str r3, [r2] /* Store the passed value with AR disabled. */
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ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
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ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
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str r1, [r2] /* Store the passed value.*/
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ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
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str r0, [r2] /* Store the passed value. */
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800
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4:
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subs r3, r3, #1 /* Decrement count. */
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bne 4b
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skip_sdram:
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/* slow interface */
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG
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ldr r0, REG_TC_EMIFS_CS0_CONFIG
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str r1, [r0] /* Chip Select 0 */
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG
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ldr r0, REG_TC_EMIFS_CS1_CONFIG
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str r1, [r0] /* Chip Select 1 */
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ldr r1, VAL_TC_EMIFS_CS2_CONFIG
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ldr r0, REG_TC_EMIFS_CS2_CONFIG
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str r1, [r0] /* Chip Select 2 */
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG
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ldr r0, REG_TC_EMIFS_CS3_CONFIG
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str r1, [r0] /* Chip Select 3 */
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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/* OMAP configuration registers */
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REG_FUNC_MUX_CTRL_0: /* 32 bits */
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.word 0xfffe1000
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REG_FUNC_MUX_CTRL_1: /* 32 bits */
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.word 0xfffe1004
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REG_FUNC_MUX_CTRL_2: /* 32 bits */
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.word 0xfffe1008
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REG_COMP_MODE_CTRL_0: /* 32 bits */
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.word 0xfffe100c
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REG_FUNC_MUX_CTRL_3: /* 32 bits */
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.word 0xfffe1010
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REG_FUNC_MUX_CTRL_4: /* 32 bits */
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.word 0xfffe1014
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REG_FUNC_MUX_CTRL_5: /* 32 bits */
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.word 0xfffe1018
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REG_FUNC_MUX_CTRL_6: /* 32 bits */
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.word 0xfffe101c
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REG_FUNC_MUX_CTRL_7: /* 32 bits */
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.word 0xfffe1020
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REG_FUNC_MUX_CTRL_8: /* 32 bits */
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.word 0xfffe1024
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REG_FUNC_MUX_CTRL_9: /* 32 bits */
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.word 0xfffe1028
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REG_FUNC_MUX_CTRL_A: /* 32 bits */
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.word 0xfffe102C
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REG_FUNC_MUX_CTRL_B: /* 32 bits */
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.word 0xfffe1030
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REG_FUNC_MUX_CTRL_C: /* 32 bits */
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.word 0xfffe1034
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REG_FUNC_MUX_CTRL_D: /* 32 bits */
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.word 0xfffe1038
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REG_PULL_DWN_CTRL_0: /* 32 bits */
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.word 0xfffe1040
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REG_PULL_DWN_CTRL_1: /* 32 bits */
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.word 0xfffe1044
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REG_PULL_DWN_CTRL_2: /* 32 bits */
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.word 0xfffe1048
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REG_PULL_DWN_CTRL_3: /* 32 bits */
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.word 0xfffe104c
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REG_VOLTAGE_CTRL_0: /* 32 bits */
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.word 0xfffe1060
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REG_TEST_DBG_CTRL_0: /* 32 bits */
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.word 0xfffe1070
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REG_MOD_CONF_CTRL_0: /* 32 bits */
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.word 0xfffe1080
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REG_TC_IMIF_PRIO: /* 32 bits */
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.word 0xfffecc00
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REG_TC_EMIFS_PRIO: /* 32 bits */
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.word 0xfffecc04
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REG_TC_EMIFF_PRIO: /* 32 bits */
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.word 0xfffecc08
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REG_TC_EMIFS_CONFIG: /* 32 bits */
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
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.word 0xfffecc1c
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REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
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.word 0xfffecc20
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REG_TC_EMIFF_MRS: /* 32 bits */
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.word 0xfffecc24
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/* MPU clock/reset/power mode control registers */
|
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REG_ARM_CKCTL: /* 16 bits */
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.word 0xfffece00
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REG_ARM_IDLECT2: /* 16 bits */
|
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.word 0xfffece08
|
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REG_ARM_RSTCT2: /* 16 bits */
|
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.word 0xfffece14
|
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REG_ARM_SYSST: /* 16 bits */
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.word 0xfffece18
|
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/* DPLL control registers */
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REG_DPLL1_CTL: /* 16 bits */
|
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.word 0xfffecf00
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/* identification code register */
|
||||
REG_IDCODE: /* 32 bits */
|
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.word 0xfffed404
|
||||
|
||||
/* SX1 specific */
|
||||
_GPIO_PIN_CONTROL_REG:
|
||||
.word GPIO_PIN_CONTROL_REG
|
||||
_GPIO_DIR_CONTROL_REG:
|
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.word GPIO_DIR_CONTROL_REG
|
||||
_GPIO_DATA_OUTPUT_REG:
|
||||
.word GPIO_DATA_OUTPUT_REG
|
||||
|
||||
VAL_COMP_MODE_CTRL_0:
|
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.word 0x0000eaef
|
||||
VAL_FUNC_MUX_CTRL_4:
|
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.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_5:
|
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.word 0x00000000
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VAL_FUNC_MUX_CTRL_6:
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.word 0x00000001
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VAL_FUNC_MUX_CTRL_7:
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.word 0x00001000
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VAL_FUNC_MUX_CTRL_8:
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.word 0x00001240 /*[Knoller] Value of Symbian Image Wing B2*/
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VAL_FUNC_MUX_CTRL_9:
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.word 0x00201008
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VAL_FUNC_MUX_CTRL_A:
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.word 0x00001000
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VAL_FUNC_MUX_CTRL_B:
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||||
.word 0x00000000
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||||
VAL_FUNC_MUX_CTRL_C:
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.word 0x09008001 /*[Knoller] Value of Symbian Image Wing B2*/
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VAL_FUNC_MUX_CTRL_D:
|
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.word 0x00000000
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VAL_PULL_DWN_CTRL_0:
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.word 0xfffeffff
|
||||
VAL_PULL_DWN_CTRL_1:
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.word 0xd1ffffec
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VAL_PULL_DWN_CTRL_2:
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.word 0xffa80c5b
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||||
VAL_PULL_DWN_CTRL_3:
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.word 0xffffc0fe
|
||||
VAL_VOLTAGE_CTRL_0:
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.word 0x00000007
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||||
VAL_TEST_DBG_CTRL_0:
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||||
/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
|
||||
* says to write a 7. Don't know what the right thing is to do, so
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* I'm leaving it at 7 since that's what was already here.
|
||||
*/
|
||||
.word 0x00000007
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||||
VAL_MOD_CONF_CTRL_0:
|
||||
.word 0x0da20000 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
VAL_ARM_CKCTL:
|
||||
.word 0x010D
|
||||
|
||||
VAL_DPLL1_CTL:
|
||||
.word 0x3A33 /*[Hertle] Value of Symbian Image*/
|
||||
|
||||
VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
|
||||
.word 0x00001149
|
||||
|
||||
VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
|
||||
.word 0x00004158
|
||||
|
||||
VAL_TC_EMIFS_CS0_CONFIG:
|
||||
.word 0x00213090 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
VAL_TC_EMIFS_CS1_CONFIG:
|
||||
.word 0x00215070 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
VAL_TC_EMIFS_CS2_CONFIG:
|
||||
.word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
VAL_TC_EMIFS_CS3_CONFIG:
|
||||
.word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
VAL_TC_EMIFF_SDRAM_CONFIG:
|
||||
.word 0x0105f0b4 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
|
||||
|
||||
VAL_TC_EMIFF_MRS:
|
||||
.word 0x00000027 /*[Knoller] Value of Symbian Image Wing B2*/
|
||||
123
common/package/utils/sysupgrade-helper/src/board/sx1/sx1.c
Normal file
123
common/package/utils/sysupgrade-helper/src/board/sx1/sx1.c
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
*
|
||||
* (C) Copyright 2003
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void flash__init (void);
|
||||
static void ether__init (void);
|
||||
|
||||
static inline void delay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
/* arch number of SX1 Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SX1;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0x10000100;
|
||||
|
||||
/* kk - this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed.
|
||||
* ... rkw ...
|
||||
*/
|
||||
icache_enable ();
|
||||
|
||||
flash__init ();
|
||||
ether__init ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
|
||||
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
|
||||
|
||||
/* setup gpio direction to match board (no floats!) */
|
||||
/**gdir = 0xCFF9; */
|
||||
/**mdir = 0x103F; */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
static void flash__init (void)
|
||||
{
|
||||
#define CS0_CHIP_SELECT_REG 0xfffecc10
|
||||
#define CS3_CHIP_SELECT_REG 0xfffecc1c
|
||||
#define EMIFS_GlB_Config_REG 0xfffecc0c
|
||||
|
||||
unsigned int regval;
|
||||
|
||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
|
||||
regval = regval | 0x0001; /* Turn off write protection for flash devices. */
|
||||
if (regval & 0x0002) {
|
||||
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
|
||||
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
|
||||
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
|
||||
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
|
||||
}
|
||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
|
||||
}
|
||||
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
static void ether__init (void)
|
||||
{
|
||||
#define ETH_CONTROL_REG 0x0800000b
|
||||
/* take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete.
|
||||
*/
|
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
|
||||
udelay (3);
|
||||
}
|
||||
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue