mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o ethaddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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213
common/package/utils/sysupgrade-helper/src/board/v38b/ethaddr.c
Normal file
213
common/package/utils/sysupgrade-helper/src/board/v38b/ethaddr.c
Normal file
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@ -0,0 +1,213 @@
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/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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/* For the V38B board the pin is GPIO_PSC_6 */
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#define GPIO_PIN GPIO_PSC6_0
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#define NO_ERROR 0
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#define ERR_NO_NUMBER 1
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#define ERR_BAD_NUMBER 2
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static int is_high(void);
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static int check_device(void);
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static void io_out(int value);
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static void io_input(void);
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static void io_output(void);
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static void init_gpio(void);
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static void read_byte(unsigned char *data);
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static void write_byte(unsigned char command);
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void read_2501_memory(unsigned char *psernum, unsigned char *perr);
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void board_get_enetaddr(uchar *enetaddr);
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static int is_high()
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{
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return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
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}
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static void io_out(int value)
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{
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if (value)
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*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
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else
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*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
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}
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static void io_input()
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{
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*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
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udelay(3); /* allow input to settle */
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}
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static void io_output()
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{
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*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
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}
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static void init_gpio()
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{
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*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
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}
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void read_2501_memory(unsigned char *psernum, unsigned char *perr)
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{
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#define NBYTES 28
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unsigned char crcval, i;
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unsigned char buf[NBYTES];
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*perr = 0;
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crcval = 0;
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for (i = 0; i < NBYTES; i++)
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buf[i] = 0;
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if (!check_device())
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*perr = ERR_NO_NUMBER;
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else {
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*perr = NO_ERROR;
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write_byte(0xCC); /* skip ROM (0xCC) */
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write_byte(0xF0); /* Read memory command 0xF0 */
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write_byte(0x00); /* Address TA1=0, TA2=0 */
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write_byte(0x00);
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read_byte(&crcval); /* Read CRC of address and command */
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for (i = 0; i < NBYTES; i++)
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read_byte(&buf[i]);
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}
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if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
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*perr = ERR_BAD_NUMBER;
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psernum[0] = 0x00;
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psernum[1] = 0xE0;
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psernum[2] = 0xEE;
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psernum[3] = 0xFF;
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psernum[4] = 0xFF;
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psernum[5] = 0xFF;
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} else {
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psernum[0] = 0x00;
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psernum[1] = 0xE0;
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psernum[2] = 0xEE;
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psernum[3] = buf[7];
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psernum[4] = buf[6];
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psernum[5] = buf[5];
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}
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}
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static int check_device()
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{
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int found;
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io_output();
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io_out(0);
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udelay(500); /* must be at least 480 us low pulse */
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io_input();
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udelay(60);
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found = (is_high() == 0) ? 1 : 0;
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udelay(500); /* must be at least 480 us low pulse */
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return found;
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}
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static void write_byte(unsigned char command)
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{
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char i;
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for (i = 0; i < 8; i++) {
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/* 1 us to 15 us low pulse starts bit slot */
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/* Start with high pulse for 3 us */
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io_input();
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udelay(3);
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io_out(0);
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io_output();
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udelay(3);
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if (command & 0x01) {
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/* 60 us high for 1-bit */
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io_input();
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udelay(60);
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} else
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/* 60 us low for 0-bit */
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udelay(60);
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/* Leave pin as input */
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io_input();
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command = command >> 1;
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}
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}
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static void read_byte(unsigned char *data)
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{
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unsigned char i, rdat = 0;
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for (i = 0; i < 8; i++) {
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/* read one bit from one-wire device */
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/* 1 - 15 us low starts bit slot */
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io_out(0);
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io_output();
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udelay(0);
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/* allow line to be pulled high */
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io_input();
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/* delay 10 us */
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udelay(10);
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/* now sample input status */
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if (is_high())
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rdat = (rdat >> 1) | 0x80;
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else
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rdat = rdat >> 1;
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udelay(60); /* at least 60 us */
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}
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/* copy the return value */
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*data = rdat;
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}
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void board_get_enetaddr(uchar *enetaddr)
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{
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unsigned char sn[6], err = NO_ERROR;
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init_gpio();
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read_2501_memory(sn, &err);
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if (err == NO_ERROR) {
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sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
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sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
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printf("MAC address: %s\n", enetaddr);
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setenv("ethaddr", (char *)enetaddr);
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} else {
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sprintf((char *)enetaddr, "00:01:02:03:04:05");
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printf("Error reading MAC address.\n");
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printf("Setting default to %s\n", enetaddr);
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setenv("ethaddr", (char *)enetaddr);
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}
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}
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276
common/package/utils/sysupgrade-helper/src/board/v38b/v38b.c
Normal file
276
common/package/utils/sysupgrade-helper/src/board/v38b/v38b.c
Normal file
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@ -0,0 +1,276 @@
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/*
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* (C) Copyright 2003-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <net.h>
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#include <asm/processor.h>
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif /* SDRAM_DDR */
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif /* !CONFIG_SYS_RAMBOOT */
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif /* SDRAM_DDR */
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else
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dramsize = test2;
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|
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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|
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/* set SDRAM CS0 size according to the amount of RAM found */
|
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if (dramsize > 0)
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
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else
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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|
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/* let SDRAM CS1 start right after CS0 */
|
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
|
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|
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/* find RAM size using SDRAM CS1 only */
|
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if (!dramsize)
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sdram_start(0);
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test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
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if (!dramsize) {
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sdram_start(1);
|
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test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
||||
}
|
||||
if (test1 > test2) {
|
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sdram_start(0);
|
||||
dramsize2 = test1;
|
||||
} else
|
||||
dramsize2 = test2;
|
||||
|
||||
/* memory smaller than 1MB is impossible */
|
||||
if (dramsize2 < (1 << 20))
|
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dramsize2 = 0;
|
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */
|
||||
if (dramsize2 > 0)
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
|
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
|
||||
else
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
||||
|
||||
#else /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
/* retrieve size of memory connected to SDRAM CS0 */
|
||||
dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
|
||||
if (dramsize >= 0x13)
|
||||
dramsize = (1 << (dramsize - 0x13)) << 20;
|
||||
else
|
||||
dramsize = 0;
|
||||
|
||||
/* retrieve size of memory connected to SDRAM CS1 */
|
||||
dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
|
||||
if (dramsize2 >= 0x13)
|
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
||||
else
|
||||
dramsize2 = 0;
|
||||
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
/*
|
||||
* On MPC5200B we need to set the special configuration delay in the
|
||||
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
|
||||
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
|
||||
*
|
||||
* "The SDelay should be written to a value of 0x00000004. It is
|
||||
* required to account for changes caused by normal wafer processing
|
||||
* parameters."
|
||||
*/
|
||||
svr = get_svr();
|
||||
pvr = get_pvr();
|
||||
if ((SVR_MJREV(svr) >= 2) &&
|
||||
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
|
||||
|
||||
*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
return dramsize + dramsize2;
|
||||
}
|
||||
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts("Board: MarelV38B\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
/*
|
||||
* Enable and configure the direction (output) of PSC3_9 - watchdog
|
||||
* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
|
||||
* Manual.
|
||||
*/
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
|
||||
#endif /* CONFIG_HW_WATCHDOG */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/*
|
||||
* Now, when we are in RAM, enable flash write access for the
|
||||
* detection process. Note that CS_BOOT cannot be cleared when
|
||||
* executing in flash.
|
||||
*/
|
||||
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
|
||||
/*
|
||||
* Enable GPIO_WKUP_7 to "read the status of the actual power
|
||||
* situation". Default direction is input, so no need to set it
|
||||
* explicitly.
|
||||
*/
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern void board_get_enetaddr(uchar *enetaddr);
|
||||
int misc_init_r(void)
|
||||
{
|
||||
uchar enetaddr[6];
|
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
||||
board_get_enetaddr(enetaddr);
|
||||
eth_setenv_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
|
||||
void init_ide_reset(void)
|
||||
{
|
||||
debug("init_ide_reset\n");
|
||||
|
||||
/* Configure PSC1_4 as GPIO output for ATA reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
|
||||
/* Deassert reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
|
||||
}
|
||||
|
||||
|
||||
void ide_set_reset(int idereset)
|
||||
{
|
||||
debug("ide_reset(%d)\n", idereset);
|
||||
|
||||
if (idereset) {
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
|
||||
/* Make a delay. MPC5200 spec says 25 usec min */
|
||||
udelay(500000);
|
||||
} else
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
/*
|
||||
* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
|
||||
* we need a positive or negative transition on WDI i.e., our PSC3_9.
|
||||
*/
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
|
||||
}
|
||||
#endif /* CONFIG_HW_WATCHDOG */
|
||||
Loading…
Add table
Add a link
Reference in a new issue