mirror of
https://github.com/Ysurac/openmptcprouter.git
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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude ($obj).depend
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#########################################################################
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@ -0,0 +1,140 @@
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/*
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* Copyright 2009 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr2_spd_eeprom_t));
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}
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/*
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* There are four board-specific SDRAM timing parameters which must be
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* calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths.
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* Unless clock and DQ lanes are very different
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* lengths (>2"), this should be set to the nominal value
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* of 1/2 clock delay.
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* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 4.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* PCB routing on the XPedite5170 is nearly identical to the XPedite5370
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* so we use the XPedite5370 settings as a basis for the XPedite5170.
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*/
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typedef struct board_memctl_options {
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uint16_t datarate_mhz_low;
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uint16_t datarate_mhz_high;
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uint8_t clk_adjust;
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uint8_t cpo_override;
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uint8_t write_data_delay;
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} board_memctl_options_t;
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static struct board_memctl_options bopts_ctrl[][2] = {
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{
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/* Controller 0 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 9,
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.write_data_delay = 2,
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},
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},
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{
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/* Controller 1 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 7,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
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sys_info_t sysinfo;
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int i;
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unsigned int datarate;
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get_sys_info(&sysinfo);
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datarate = get_ddr_freq(0) / 1000000;
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for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
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if ((bopts[i].datarate_mhz_low <= datarate) &&
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(bopts[i].datarate_mhz_high >= datarate)) {
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debug("controller %d:\n", ctrl_num);
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debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
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debug(" cpo = %d\n", bopts[i].cpo_override);
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debug(" write_data_delay = %d\n",
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bopts[i].write_data_delay);
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popts->clk_adjust = bopts[i].clk_adjust;
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popts->cpo_override = bopts[i].cpo_override;
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popts->write_data_delay = bopts[i].write_data_delay;
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}
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* Notes:
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* CCSRBAR don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_NAND_BASE
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/* NAND LAW covers 2 NAND flashes */
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SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -0,0 +1,95 @@
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/*
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* Copyright 2009 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <pca953x.h>
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#include "../common/fsl_8xxx_misc.h"
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
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extern void ft_board_pci_setup(void *blob, bd_t *bd);
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#endif
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/*
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* Print out which flash was booted from and if booting from the 2nd flash,
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* swap flash chip selects to maintain consistent flash numbering/addresses.
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*/
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static void flash_cs_fixup(void)
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{
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int flash_sel;
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/*
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* Print boot dev and swap flash flash chip selects if booted from 2nd
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* flash. Swapping chip selects presents user with a common memory
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* map regardless of which flash was booted from.
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*/
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flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
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CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
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printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
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if (flash_sel) {
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set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
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set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
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set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
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set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
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}
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}
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int board_early_init_r(void)
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{
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/* Initialize PCA9557 devices */
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
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flash_cs_fixup();
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = fsl_ddr_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize and enable DDR ECC */
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ddr_enable_ecc(dram_size);
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#endif
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return dram_size;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCI
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ft_board_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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}
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#endif
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