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Add a directory by kernel instead of a common root, add qnap-301w and rpi4 kernel 6.1 suppport
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e910436a7a
commit
46837ec4c0
9459 changed files with 362648 additions and 116345 deletions
146
common/package/utils/sysupgrade-helper/src/include/lxt971a.h
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146
common/package/utils/sysupgrade-helper/src/include/lxt971a.h
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/***********************************************************************
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*
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* Copyright (C) 2004 by FS Forth-Systeme GmbH.
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* All rights reserved.
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*
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* $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
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* @Author: Markus Pietrek
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* @References: [1] NS9750 Hardware Reference, December 2003
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* [2] Intel LXT971 Datasheet #249414 Rev. 02
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* [3] NS7520 Linux Ethernet Driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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***********************************************************************/
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#ifndef __LXT971A_H__
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#define __LXT971A_H__
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/* PHY definitions (LXT971A) [2] */
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#define PHY_LXT971_PORT_CFG (0x10)
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#define PHY_LXT971_STAT2 (0x11)
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#define PHY_LXT971_INT_ENABLE (0x12)
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#define PHY_LXT971_INT_STATUS (0x13)
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#define PHY_LXT971_LED_CFG (0x14)
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#define PHY_LXT971_DIG_CFG (0x1A)
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#define PHY_LXT971_TX_CTRL (0x1E)
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/* PORT_CFG Port Configuration Register Bit Fields */
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#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
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#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
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#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
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#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
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#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
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#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
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#define PHY_LXT971_PORT_CFG_SQE (0x0200)
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#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
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#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
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#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
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#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
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#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
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#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
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#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
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#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
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#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
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#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
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#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
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/* STAT2 Status Register #2 Bit Fields */
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#define PHY_LXT971_STAT2_RES1 (0x8000)
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#define PHY_LXT971_STAT2_100BTX (0x4000)
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#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
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#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
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#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
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#define PHY_LXT971_STAT2_LINK (0x0400)
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#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
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#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
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#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
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#define PHY_LXT971_STAT2_RES2 (0x0040)
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#define PHY_LXT971_STAT2_POLARITY (0x0020)
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#define PHY_LXT971_STAT2_PAUSE (0x0010)
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#define PHY_LXT971_STAT2_ERROR (0x0008)
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#define PHY_LXT971_STAT2_RES3 (0x0007)
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/* INT_ENABLE Interrupt Enable Register Bit Fields */
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#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
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#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
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#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
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#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
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#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
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#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
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#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
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#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
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/* INT_STATUS Interrupt Status Register Bit Fields */
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#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
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#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
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#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
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#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
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#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
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#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
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#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
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#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
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/* LED_CFG Interrupt LED Configuration Register Bit Fields */
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#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
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#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
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#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
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#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
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#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
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#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
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#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
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#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
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#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
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#define PHY_LXT971_LED_CFG_RES1 (0x0001)
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/* only one of these values must be shifted for each SHIFT_LED? */
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#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
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#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
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#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
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#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
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#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
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#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
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#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
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#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
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#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
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#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
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#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
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#define PHY_LXT971_LED_CFG_LINK (0x0004)
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#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
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#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
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#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
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#define PHY_LXT971_LED_CFG_SPEED (0x0000)
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/* DIG_CFG Digitial Configuration Register Bit Fields */
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#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
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#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
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#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
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#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
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#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
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#define PHY_LXT971_MDIO_MAX_CLK (8000000)
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#define PHY_MDIO_MAX_CLK (2500000)
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/* TX_CTRL Transmit Control Register Bit Fields
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documentation is buggy for this register, therefore setting not included */
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typedef enum
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{
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PHY_NONE = 0x0000, /* no PHY detected yet */
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PHY_LXT971A = 0x0013
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} PhyType;
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#endif /* __LXT971A_H__ */
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