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Fix bpi-r64 on 6.1 kernel

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Ycarus (Yannick Chabanois) 2023-06-27 17:50:14 +02:00
parent 34aa6d03cd
commit 48a664ff20
126 changed files with 17222 additions and 2387 deletions
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1
6.1/target/linux/generic/config-6.1
View file

@ -1016,6 +1016,7 @@ CONFIG_CMDLINE=""
# CONFIG_CMDLINE_EXTEND is not set
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_CMDLINE_FROM_BOOTLOADER is not set
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_CMDLINE_PARTITION is not set
# CONFIG_CNIC is not set
# CONFIG_CODA_FS is not set

775
6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi Normal file
View file

@ -0,0 +1,775 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
* Author: Jianhui Zhao <zhaojh329@gmail.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/mux.h>
/ {
compatible = "mediatek,mt7981";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
};
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM_HCK>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
cooling-levels = <0 128 192 255>;
#cooling-cells = <2>;
status = "disabled";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <60000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
cpu-active-high {
/* active: set fan to cooling level 3 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
cpu-active-med {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
cpu-active-low {
/* passive: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
};
thermal: thermal@1100c800 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7981-auxadc",
"mediatek,mt7986-auxadc",
"mediatek,mt7622-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
<&infracfg CLK_INFRA_ADC_FRC_CK>;
clock-names = "main", "32k";
#io-channel-cells = <1>;
};
wdma: wdma@15104800 {
compatible = "mediatek,wed-wdma";
reg = <0 0x15104800 0 0x400>,
<0 0x15104c00 0 0x400>;
};
ap2woccif: ap2woccif@151a5000 {
compatible = "mediatek,ap2woccif";
reg = <0 0x151a5000 0 0x1000>,
<0 0x151ad000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 64 KiB reserved for ramoops/pstore */
ramoops@42ff0000 {
compatible = "ramoops";
reg = <0 0x42ff0000 0 0x10000>;
record-size = <0x1000>;
};
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
wmcpu_emi: wmcpu-reserved@47c80000 {
reg = <0 0x47c80000 0 0x100000>;
no-map;
};
wo_emi0: wo-emi@47d80000 {
reg = <0 0x47d80000 0 0x40000>;
no-map;
};
wo_data: wo-data@47dc0000 {
reg = <0 0x47dc0000 0 0x240000>;
no-map;
};
wo_ilm0: wo-ilm@151e0000 {
reg = <0 0x151e0000 0 0x8000>;
no-map;
};
wo_dlm0: wo-dlm@151e8000 {
reg = <0 0x151e8000 0 0x2000>;
no-map;
};
wo_boot: wo-boot@15194000 {
reg = <0 0x15194000 0 0x1000>;
no-map;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
trng {
compatible = "mediatek,mt7981-rng";
};
clk40m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "clkxtal";
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@1001B000 {
compatible = "mediatek,mt7981-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys: apmixedsys@1001E000 {
compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
clock-frequency = <13000000>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
status = "disabled";
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
<&infracfg CLK_INFRA_UART0_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
<&topckgen CLK_TOP_UART_SEL>;
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
<&infracfg CLK_INFRA_UART1_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_UART1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
<&infracfg CLK_INFRA_UART2_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_UART2_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11007000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>,
<&infracfg CLK_INFRA_I2C_MCK_CK>,
<&infracfg CLK_INFRA_I2C_PCK_CK>;
clock-names = "main", "dma", "arb", "pmic";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pcie: pcie@11280000 {
compatible = "mediatek,mt7981-pcie",
"mediatek,mt7986-pcie";
device_type = "pci";
reg = <0 0x11280000 0 0x4000>;
reg-names = "pcie-mac";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000
0x0 0x20000000 0 0x10000000>;
status = "disabled";
clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
phys = <&u3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
pcie_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
crypto: crypto@10320000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&topckgen CLK_TOP_EIP97B>;
clock-names = "top_eip97_ck";
assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
};
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
<0 0x11c00000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rt", "iocfg_rm",
"iocfg_rb", "iocfg_lb", "iocfg_bl",
"iocfg_tm", "iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 56>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
mdio_pins: mdc-mdio-pins {
mux {
function = "eth";
groups = "smi_mdc_mdio";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
};
};
wifi_dbdc_pins: wifi-dbdc-pins {
mux {
function = "eth";
groups = "wf0_mode1";
};
conf {
pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
"WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
"WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
"WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
"WF_CBA_RESETB", "WF_DIG_RESETB";
drive-strength = <4>;
};
};
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7981-ethsys",
"mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed: wed@15010000 {
compatible = "mediatek,mt7981-wed",
"mediatek,mt7986-wed",
"syscon";
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
<&wo_data>, <&wo_boot>;
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
"wo-data", "wo-boot";
mediatek,wo-ccif = <&wo_ccif0>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7981-eth";
reg = <0 0x15100000 0 0x80000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_WOCPU0_EN>,
<&sgmiisys0 CLK_SGM0_TX_EN>,
<&sgmiisys0 CLK_SGM0_RX_EN>,
<&sgmiisys0 CLK_SGM0_CK0_EN>,
<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
<&sgmiisys1 CLK_SGM1_TX_EN>,
<&sgmiisys1 CLK_SGM1_RX_EN>,
<&sgmiisys1 CLK_SGM1_CK1_EN>,
<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
<&topckgen CLK_TOP_SGM_REG>,
<&topckgen CLK_TOP_NETSYS_SEL>,
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
clock-names = "fe", "gp2", "gp1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "netsys0", "netsys1";
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
<&topckgen CLK_TOP_CB_SGM_325M>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,infracfg = <&topmisc>;
mediatek,wed = <&wed>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio_bus: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
int_gbe_phy: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
phy-mode = "gmii";
phy-is-integrated;
nvmem-cells = <&phy_calibration>;
nvmem-cell-names = "phy-cal-data";
};
};
};
wo_ccif0: syscon@151a5000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151a5000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
reg = <0 0x10060000 0 0x1000>;
mediatek,pnswap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
topmisc: topmisc@11d10000 {
compatible = "mediatek,mt7981-topmisc", "syscon";
reg = <0 0x11d10000 0 0x10000>;
#clock-cells = <1>;
};
snand: snfi@11005000 {
compatible = "mediatek,mt7986-snand";
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
<&infracfg CLK_INFRA_NFI1_CK>,
<&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
<&topckgen CLK_TOP_NFI1X_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
<&topckgen CLK_TOP_CB_M_D8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc",
"mediatek,mt7981-mmc";
reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_MSDC_CK>,
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
<&infracfg CLK_INFRA_MSDC_66M_CK>,
<&infracfg CLK_INFRA_MSDC_133M_CK>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
<&topckgen CLK_TOP_EMMC_400M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_CB_NET2_D2>;
clock-names = "source", "hclk", "axi_cg", "ahb_cg";
status = "disabled";
};
wed_pcie: wed_pcie@10003000 {
compatible = "mediatek,wed_pcie";
reg = <0 0x10003000 0 0x10>;
};
spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPIM_MST_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11009000 0 0x100>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2_CK>,
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
consys: consys@10000000 {
compatible = "mediatek,mt7981-consys";
reg = <0 0x10000000 0 0x8600000>;
memory-region = <&wmcpu_emi>;
};
xhci: usb@11200000 {
compatible = "mediatek,mt7986-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
<&infracfg CLK_INFRA_IUSB_CK>,
<&infracfg CLK_INFRA_IUSB_133_CK>,
<&infracfg CLK_INFRA_IUSB_66M_CK>,
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
clock-names = "sys_ck",
"ref_ck",
"mcu_ck",
"dma_ck",
"xhci_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>;
vusb33-supply = <&reg_3p3v>;
status = "disabled";
};
usb_phy: usb-phy@11e10000 {
compatible = "mediatek,mt7981",
"mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e10000 0x1700>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
clock-names = "ref";
#phy-cells = <1>;
};
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x218 0>;
status = "okay";
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
efuse: efuse@11f20000 {
compatible = "mediatek,mt7981-efuse",
"mediatek,efuse";
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};
phy_calibration: phy-calib@8dc {
reg = <0x8dc 0x10>;
};
comb_rx_imp_p0: usb3-rx-imp@8c8 {
reg = <0x8c8 1>;
bits = <0 5>;
};
comb_tx_imp_p0: usb3-tx-imp@8c8 {
reg = <0x8c8 2>;
bits = <5 5>;
};
comb_intr_p0: usb3-intr@8c9 {
reg = <0x8c9 1>;
bits = <2 6>;
};
};
afe: audio-controller@11210000 {
compatible = "mediatek,mt79xx-audio";
reg = <0 0x11210000 0 0x9000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
<&infracfg CLK_INFRA_AUD_26M_CK>,
<&infracfg CLK_INFRA_AUD_L_CK>,
<&infracfg CLK_INFRA_AUD_AUD_CK>,
<&infracfg CLK_INFRA_AUD_EG2_CK>,
<&topckgen CLK_TOP_AUD_SEL>;
clock-names = "aud_bus_ck",
"aud_26m_ck",
"aud_l_ck",
"aud_aud_ck",
"aud_eg2_ck",
"aud_sel";
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
<&topckgen CLK_TOP_A1SYS_SEL>,
<&topckgen CLK_TOP_AUD_L_SEL>,
<&topckgen CLK_TOP_A_TUNER_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
<&topckgen CLK_TOP_APLL2_D4>,
<&topckgen CLK_TOP_CB_APLL2_196M>,
<&topckgen CLK_TOP_APLL2_D4>;
status = "disabled";
};
ice: ice_debug {
compatible = "mediatek,mt7981-ice_debug",
"mediatek,mt2701-ice_debug";
clocks = <&infracfg CLK_INFRA_DBG_CK>;
clock-names = "ice_dbg";
};
wifi: wifi@18000000 {
compatible = "mediatek,mt7981-wmac";
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
pinctrl-0 = <&wifi_dbdc_pins>;
pinctrl-names = "dbdc";
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wmcpu_emi>;
status = "disabled";
};
};

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snand";
};
&spi0 {
status = "okay";
spi_nand: spi_nand@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snor";
};
&spi0 {
status = "okay";
spi_nor: spi_nor@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@00000 {
label = "BL2";
reg = <0x00000 0x0040000>;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x0010000>;
};
factory: partition@50000 {
label = "Factory";
reg = <0x50000 0x00B0000>;
};
partition@100000 {
label = "FIP";
reg = <0x100000 0x0080000>;
};
partition@180000 {
label = "firmware";
reg = <0x180000 0xE00000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986a.dtsi"
/ {
model = "MediaTek MT7986a RFB";
compatible = "mediatek,mt7986a-rfb";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0 0x40000000 0 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&mdio {
phy5: phy@5 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <5>;
reset-gpios = <&pio 6 1>;
reset-deassert-us = <20000>;
};
phy6: phy@6 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <6>;
};
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 0>;
};
};
&crypto {
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
spic_pins_g2: spic-pins-29-to-32 {
mux {
function = "spi";
groups = "spi1_2";
};
};
spi_flash_pins: spi-flash-pins-33-to-38 {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <8>;
mediatek,pull-up-adv = <0>; /* bias-disable */
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <8>;
mediatek,pull-down-adv = <0>; /* bias-disable */
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf_dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins_g2>;
status = "okay";
proslic_spi: proslic_spi@0 {
compatible = "silabs,proslic_spi";
reg = <0>;
spi-max-frequency = <10000000>;
spi-cpha = <1>;
spi-cpol = <1>;
channel_count = <1>;
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
reset_gpio = <&pio 7 0>;
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
};
};
&gmac1 {
phy-mode = "2500base-x";
phy-connection-type = "2500base-x";
phy-handle = <&phy6>;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "lan6";
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7988a-rfb-spim-nand.dtsi"
#include <dt-bindings/pinctrl/mt65xx.h>
/ {
model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
"mediatek,mt7988a-rfb-snand",
"mediatek,mt7988";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11000000 \
pci=pcie_bus_perf";
};
memory {
reg = <0 0x40000000 0 0x40000000>;
};
};
&eth {
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "internal";
phy-connection-type = "internal";
phy = <&phy15>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
phy-mode = "10gbase-kr";
phy-connection-type = "10gbase-kr";
phy = <&phy8>;
};
mdio0: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* external Aquantia AQR113C */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 72 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
/* external Aquantia AQR113C */
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 71 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
/* external Maxlinear GPY211C */
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
/* external Maxlinear GPY211C */
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
/* internal 2.5G PHY */
phy15: ethernet-phy@15 {
reg = <15>;
pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
};
};
&switch {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe0_led0_pins>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
};
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.9481";
reg = <1>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe1_led0_pins>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id03a2.9481";
reg = <2>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe2_led0_pins>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id03a2.9481";
reg = <3>;
phy-mode = "internal";
pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe3_led0_pins>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7988a-rfb.dtsi"
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
};
};
&spi_nand {
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0400000>;
};
partition@580000 {
label = "FIP";
reg = <0x580000 0x0200000>;
};
partition@780000 {
label = "ubi";
reg = <0x780000 0x7080000>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7988a.dtsi"
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
&cpu0 {
proc-supply = <&rt5190_buck3>;
};
&cpu1 {
proc-supply = <&rt5190_buck3>;
};
&cpu2 {
proc-supply = <&rt5190_buck3>;
};
&cpu3 {
proc-supply = <&rt5190_buck3>;
};
&cci {
proc-supply = <&rt5190_buck3>;
};
&eth {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
rt5190a_64: rt5190a@64 {
compatible = "richtek,rt5190a";
reg = <0x64>;
/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
vin2-supply = <&rt5190_buck1>;
vin3-supply = <&rt5190_buck1>;
vin4-supply = <&rt5190_buck1>;
regulators {
rt5190_buck1: buck1 {
regulator-name = "rt5190a-buck1";
regulator-min-microvolt = <5090000>;
regulator-max-microvolt = <5090000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
buck2 {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
rt5190_buck3: buck3 {
regulator-name = "vproc";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
};
buck4 {
regulator-name = "rt5190a-buck4";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
ldo {
regulator-name = "rt5190a-ldo";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&pcie2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_pins>;
status = "disabled";
};
&pcie3 {
pinctrl-names = "default";
pinctrl-0 = <&pcie3_pins>;
status = "okay";
};
&ssusb0 {
status = "okay";
};
&ssusb1 {
status = "okay";
};
&tphy {
status = "okay";
};
&pio {
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
"pcie_wake_n0_0";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
"pcie_wake_n1_0";
};
};
pcie2_pins: pcie2-pins {
mux {
function = "pcie";
groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
"pcie_wake_n2_0";
};
};
pcie3_pins: pcie3-pins {
mux {
function = "pcie";
groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
"pcie_wake_n3_0";
};
};
};
&spi0 {
status = "disabled";
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&xphy {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt7988";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
clk40m: oscillator@0 {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
clock-output-names = "clkxtal";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x0>;
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x1>;
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x2>;
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
enable-method = "psci";
reg = <0x3>;
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <900000>;
};
};
};
cci: cci {
compatible = "mediatek,mt7988-cci",
"mediatek,mt8183-cci";
clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cci", "intermediate";
operating-points-v2 = <&cci_opp>;
};
cci_opp: opp_table_cci {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <850000>;
};
opp01 {
opp-hz = /bits/ 64 <660000000>;
opp-microvolt = <850000>;
};
opp02 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <900000>;
};
};
pmu {
compatible = "arm,cortex-a73-pmu";
interrupt-parent = <&gic>;
interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
phyfw: phy-firmware@f000000 {
compatible = "mediatek,2p5gphy-fw";
reg = <0 0x0f000000 0 0x8000>,
<0 0x0f100000 0 0x20000>,
<0 0x0f0f0000 0 0x200>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7988-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7988-wdt",
"mediatek,mt6589-wdt",
"syscon";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7988-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7988-pinctrl";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d00000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio_base", "iocfg_tr_base",
"iocfg_br_base", "iocfg_rb_base",
"iocfg_lb_base", "iocfg_tl_base", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 83>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
mdio0_pins: mdio0-pins {
mux {
function = "eth";
groups = "mdc_mdio0";
};
conf {
groups = "mdc_mdio0";
drive-strength = <MTK_DRIVE_8mA>;
};
};
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
groups = "i2c0_1";
};
};
i2c1_pins: i2c1-pins-g0 {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins-g0 {
mux {
function = "i2c";
groups = "i2c2_1";
};
};
gbe0_led0_pins: gbe0-pins {
mux {
function = "led";
groups = "gbe0_led0";
};
};
gbe1_led0_pins: gbe1-pins {
mux {
function = "led";
groups = "gbe1_led0";
};
};
gbe2_led0_pins: gbe2-pins {
mux {
function = "led";
groups = "gbe2_led0";
};
};
gbe3_led0_pins: gbe3-pins {
mux {
function = "led";
groups = "gbe3_led0";
};
};
i2p5gbe_led0_pins: 2p5gbe-pins {
mux {
function = "led";
groups = "2p5gbe_led0";
};
};
};
boottrap: boottrap@1001f6f0 {
compatible = "mediatek,boottrap";
reg = <0 0x1001f6f0 0 0x4>;
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7988-sgmiisys",
"mediatek,mt7988-sgmiisys_0",
"syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7988-sgmiisys",
"mediatek,mt7988-sgmiisys_1",
"syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
usxgmiisys0: usxgmiisys@10080000 {
compatible = "mediatek,mt7988-usxgmiisys",
"mediatek,mt7988-usxgmiisys_0",
"syscon";
reg = <0 0x10080000 0 0x1000>;
#clock-cells = <1>;
};
usxgmiisys1: usxgmiisys@10081000 {
compatible = "mediatek,mt7988-usxgmiisys",
"mediatek,mt7988-usxgmiisys_1",
"syscon";
reg = <0 0x10081000 0 0x1000>;
#clock-cells = <1>;
};
xfi_pextp0: xfi_pextp@11f20000 {
compatible = "mediatek,mt7988-xfi_pextp",
"mediatek,mt7988-xfi_pextp_0",
"syscon";
reg = <0 0x11f20000 0 0x10000>;
#clock-cells = <1>;
};
xfi_pextp1: xfi_pextp@11f30000 {
compatible = "mediatek,mt7988-xfi_pextp",
"mediatek,mt7988-xfi_pextp_1",
"syscon";
reg = <0 0x11f30000 0 0x10000>;
#clock-cells = <1>;
};
xfi_pll: xfi_pll@11f40000 {
compatible = "mediatek,mt7988-xfi_pll", "syscon";
reg = <0 0x11f40000 0 0x1000>;
#clock-cells = <1>;
};
mcusys: mcusys@100e0000 {
compatible = "mediatek,mt7988-mcusys", "syscon";
reg = <0 0x100e0000 0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@11000000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
/*
* 8250-mtk driver don't control "baud" clock since commit
* e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
* still need to be passed to the driver to prevent probe fail
*/
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART0_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_MUX_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
i2c0: i2c@11003000 {
compatible = "mediatek,mt7988-i2c",
"mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11004000 {
compatible = "mediatek,mt7988-i2c",
"mediatek,mt7981-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11005000 {
compatible = "mediatek,mt7988-i2c",
"mediatek,mt7981-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@11007000 {
compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
reg = <0 0x11007000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_104M_SPI0>,
<&infracfg CLK_INFRA_66M_SPI0_HCK>;
clock-names = "parent-clk", "sel-clk", "spi-clk",
"spi-hclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pcie2: pcie@11280000 {
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11280000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <3>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x20000000 0x00
0x20000000 0x00 0x00200000>,
<0x82000000 0x00 0x20200000 0x00
0x20200000 0x00 0x07e00000>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
status = "disabled";
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
<0 0 0 2 &pcie_intc2 1>,
<0 0 0 3 &pcie_intc2 2>,
<0 0 0 4 &pcie_intc2 3>;
pcie_intc2: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie3: pcie@11290000 {
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11290000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <2>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x28000000 0x00
0x28000000 0x00 0x00200000>,
<0x82000000 0x00 0x28200000 0x00
0x28200000 0x00 0x07e00000>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
<0 0 0 2 &pcie_intc3 1>,
<0 0 0 3 &pcie_intc3 2>,
<0 0 0 4 &pcie_intc3 3>;
pcie_intc3: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie0: pcie@11300000 {
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11300000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x30000000 0x00
0x30000000 0x00 0x00200000>,
<0x82000000 0x00 0x30200000 0x00
0x30200000 0x00 0x07e00000>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie1: pcie@11310000 {
compatible = "mediatek,mt7988-pcie",
"mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0 0x11310000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <1>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x81000000 0x00 0x38000000 0x00
0x38000000 0x00 0x00200000>,
<0x82000000 0x00 0x38200000 0x00
0x38200000 0x00 0x07e00000>;
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
clock-names = "pl_250m", "tl_26m", "peri_26m",
"top_133m";
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
ssusb0: usb@11190000 {
compatible = "mediatek,mt7988-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
<0 0x11193e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
phys = <&xphyu2port0 PHY_TYPE_USB2>,
<&xphyu3port0 PHY_TYPE_USB3>;
clocks = <&infracfg CLK_INFRA_USB_SYS>,
<&infracfg CLK_INFRA_USB_XHCI>,
<&infracfg CLK_INFRA_USB_REF>,
<&infracfg CLK_INFRA_66M_USB_HCK>,
<&infracfg CLK_INFRA_133M_USB_HCK>;
clock-names = "sys_ck",
"xhci_ck",
"ref_ck",
"mcu_ck",
"dma_ck";
#address-cells = <2>;
#size-cells = <2>;
mediatek,p0_speed_fixup;
status = "disabled";
};
ssusb1: usb@11200000 {
compatible = "mediatek,mt7988-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
phys = <&tphyu2port0 PHY_TYPE_USB2>,
<&tphyu3port0 PHY_TYPE_USB3>;
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
<&infracfg CLK_INFRA_USB_CK_P1>,
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
clock-names = "sys_ck",
"xhci_ck",
"ref_ck",
"mcu_ck",
"dma_ck";
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
};
tphy: tphy@11c50000 {
compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
tphyu2port0: usb-phy@11c50000 {
reg = <0 0x11c50000 0 0x700>;
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
};
tphyu3port0: usb-phy@11c50700 {
reg = <0 0x11c50700 0 0x900>;
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,usb3-pll-ssc-delta;
mediatek,usb3-pll-ssc-delta1;
};
};
topmisc: topmisc@11d10000 {
compatible = "mediatek,mt7988-topmisc", "syscon",
"mediatek,mt7988-power-controller";
reg = <0 0x11d10000 0 0x10000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
xphy: xphy@11e10000 {
compatible = "mediatek,mt7988",
"mediatek,xsphy";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
xphyu2port0: usb-phy@11e10000 {
reg = <0 0x11e10000 0 0x400>;
clocks = <&infracfg CLK_INFRA_USB_UTMI>;
clock-names = "ref";
#phy-cells = <1>;
};
xphyu3port0: usb-phy@11e13000 {
reg = <0 0x11e13400 0 0x500>;
clocks = <&infracfg CLK_INFRA_USB_PIPE>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x218 0>;
};
};
efuse: efuse@11f50000 {
compatible = "mediatek,efuse";
reg = <0 0x11f50000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
phy_calibration_p0: calib@940 {
reg = <0x940 0x10>;
};
phy_calibration_p1: calib@954 {
reg = <0x954 0x10>;
};
phy_calibration_p2: calib@968 {
reg = <0x968 0x10>;
};
phy_calibration_p3: calib@97c {
reg = <0x97c 0x10>;
};
cpufreq_calibration: calib@278 {
reg = <0x278 0x1>;
};
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
switch: switch@15020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7988-switch";
reg = <0 0x15020000 0 0x8000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethrst 0>;
};
ethwarp: syscon@15031000 {
compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
ethrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
>;
};
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7988-eth";
reg = <0 0x15100000 0 0x80000>,
<0 0x15400000 0 0x380000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
<&ethsys CLK_ETHDMA_XGP2_EN>,
<&ethsys CLK_ETHDMA_XGP3_EN>,
<&ethsys CLK_ETHDMA_FE_EN>,
<&ethsys CLK_ETHDMA_GP2_EN>,
<&ethsys CLK_ETHDMA_GP1_EN>,
<&ethsys CLK_ETHDMA_GP3_EN>,
<&ethsys CLK_ETHDMA_ESW_EN>,
<&ethsys CLK_ETHDMA_CRYPT0_EN>,
<&sgmiisys0 CLK_SGM0_TX_EN>,
<&sgmiisys0 CLK_SGM0_RX_EN>,
<&sgmiisys1 CLK_SGM1_TX_EN>,
<&sgmiisys1 CLK_SGM1_RX_EN>,
<&ethwarp CLK_ETHWARP_WOCPU2_EN>,
<&ethwarp CLK_ETHWARP_WOCPU1_EN>,
<&ethwarp CLK_ETHWARP_WOCPU0_EN>,
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
<&topckgen CLK_TOP_SGM_0_SEL>,
<&topckgen CLK_TOP_SGM_1_SEL>,
<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
<&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
<&topckgen CLK_TOP_ETH_GMII_SEL>,
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_SEL>,
<&topckgen CLK_TOP_ETH_XGMII_SEL>,
<&topckgen CLK_TOP_ETH_MII_SEL>,
<&topckgen CLK_TOP_NETSYS_SEL>,
<&topckgen CLK_TOP_NETSYS_500M_SEL>,
<&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
<&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_WARP_SEL>;
clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
"gp3", "esw", "crypto", "sgmii_tx250m",
"sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
"ethwarp_wocpu2", "ethwarp_wocpu1",
"ethwarp_wocpu0", "top_usxgmii0_sel",
"top_usxgmii1_sel", "top_sgm0_sel",
"top_sgm1_sel", "top_xfi_phy0_xtal_sel",
"top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
"top_eth_sys_sel", "top_eth_xgmii_sel",
"top_eth_mii_sel", "top_netsys_sel",
"top_netsys_500m_sel", "top_netsys_pao_2x_sel",
"top_netsys_sync_250m_sel",
"top_netsys_ppefb_250m_sel",
"top_netsys_warp_sel";
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
<&topckgen CLK_TOP_NETSYS_GSW_SEL>,
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
<&topckgen CLK_TOP_SGM_0_SEL>,
<&topckgen CLK_TOP_SGM_1_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&topckgen CLK_TOP_NET1PLL_D4>,
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
<&apmixedsys CLK_APMIXED_SGMPLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
mediatek,xfi_pll = <&xfi_pll>;
mediatek,infracfg = <&topmisc>;
mediatek,toprgu = <&watchdog>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#define MT7988_PLL_FMAX (2500UL * MHZ)
#define MT7988_PCW_CHG_SHIFT 2
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \
_div_table) \
{ \
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
.en_mask = _en_mask, .flags = _flags, \
.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
.pcwbits = _pcwbits, .pd_reg = _pd_reg, \
.pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
.div_table = _div_table, .parent_name = "clkxtal", \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
0x0154),
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
0x0204),
PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
};
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
{ .compatible = "mediatek,mt7988-apmixedsys", },
{ /* sentinel */ }
};
static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
goto free_apmixed_data;
}
return r;
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt7988_apmixed_drv = {
.probe = clk_mt7988_apmixed_probe,
.driver = {
.name = "clk-mt7988-apmixed",
.of_match_table = of_match_clk_mt7988_apmixed,
},
};
builtin_platform_driver(clk_mt7988_apmixed_drv);
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static const struct mtk_gate_regs ethdma_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_ETHDMA(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &ethdma_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethdma_clks[] = {
GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
29),
};
static const struct mtk_clk_desc ethdma_desc = {
.clks = ethdma_clks,
.num_clks = ARRAY_SIZE(ethdma_clks),
};
static const struct mtk_gate_regs sgmii0_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII0(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &sgmii0_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii0_clks[] = {
GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii0_desc = {
.clks = sgmii0_clks,
.num_clks = ARRAY_SIZE(sgmii0_clks),
};
static const struct mtk_gate_regs sgmii1_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII1(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &sgmii1_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii1_clks[] = {
GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii1_desc = {
.clks = sgmii1_clks,
.num_clks = ARRAY_SIZE(sgmii1_clks),
};
static const struct mtk_gate_regs ethwarp_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
#define GATE_ETHWARP(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &ethwarp_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethwarp_clks[] = {
GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
"netsys_mcu_sel", 13),
GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
"netsys_mcu_sel", 14),
GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
"netsys_mcu_sel", 15),
};
static const struct mtk_clk_desc ethwarp_desc = {
.clks = ethwarp_clks,
.num_clks = ARRAY_SIZE(ethwarp_clks),
};
static const struct of_device_id of_match_clk_mt7986_eth[] = {
{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
static struct platform_driver clk_mt7988_eth_drv = {
.driver = {
.name = "clk-mt7988-eth",
.of_match_table = of_match_clk_mt7986_eth,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const char *const infra_mux_uart0_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_uart1_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_uart2_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
"spi_sel" };
static const char *const infra_mux_spi1_parents[] __initconst = {
"i2c_sel", "spim_mst_sel"
};
static const char *const infra_pwm_bck_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p1_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p2_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p3_sel"
};
static const struct mtk_mux infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
0, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
1, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
2, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
2, -1, -1, -1),
/* MODULE_CLK_SEL_1 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
"infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
0x0020, 0x0024, 0, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
"infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
0x0020, 0x0024, 2, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
"infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
0x0020, 0x0024, 4, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
"infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
0x0020, 0x0024, 6, 2, -1, -1, -1),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x54,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs infra3_cg_regs = {
.set_ofs = 0x60,
.clr_ofs = 0x64,
.sta_ofs = 0x68,
};
#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra0_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra1_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra2_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra3_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA0(_id, _name, _parent, _shift) \
GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA1(_id, _name, _parent, _shift) \
GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA2(_id, _name, _parent, _shift) \
GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA3(_id, _name, _parent, _shift) \
GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
"infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
"infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
"infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
"infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
"sysaxi_sel", 0),
GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
"sysaxi_sel", 1),
GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
"infra_pwm_sel", 2),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
"infra_pwm_ck1_sel", 3),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
"infra_pwm_ck2_sel", 4),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
"infra_pwm_ck3_sel", 5),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
"infra_pwm_ck4_sel", 6),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
"infra_pwm_ck5_sel", 7),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
"infra_pwm_ck6_sel", 8),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
"infra_pwm_ck7_sel", 9),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
"infra_pwm_ck8_sel", 10),
GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
"sysaxi_sel", 12),
GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
"sysaxi_sel", 13),
GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
"csw_infra_f26m_sel", 14),
GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
"csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
// JTAG
GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
"sysaxi_sel", 20, CLK_IS_CRITICAL),
GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
"sysaxi_sel", 21),
GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
"sysaxi_sel", 29),
GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
"csw_infra_f26m_sel", 30),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
"csw_infra_f26m_sel", 0),
GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
"infra_mux_uart0_sel", 3),
GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
"infra_mux_uart1_sel", 4),
GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
"infra_mux_uart2_sel", 5),
GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
"sysaxi_sel", 11, CLK_IS_CRITICAL),
GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
"infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
"infra_mux_spi1_sel", 13),
GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
"infra_mux_spi2_sel", 14),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
"sysaxi_sel", 15, CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
"sysaxi_sel", 16),
GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
"sysaxi_sel", 17),
GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
"sysaxi_sel", 18),
GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19),
GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
"csw_infra_f26m_sel", 20),
GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
21),
GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
22),
GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
23),
GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
"sysaxi_sel", 24),
GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
"sysaxi_sel", 25),
GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
"sysaxi_sel", 26),
GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
"infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
"infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
/* INFRA3 */
GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
0),
GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
"sysaxi_sel", 1),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
2),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
"sysaxi_sel", 3),
GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
"usb_sys_p1_sel", 5),
GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
"usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
"usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
"usb_phy_sel", 11),
GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
"top_xtal", 13),
GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
"usb_xhci_p1_sel", 15),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
"infra_pcie_gfmux_tl_o_p0_sel", 20),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
"infra_pcie_gfmux_tl_o_p1_sel", 21),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
"infra_pcie_gfmux_tl_o_p2_sel", 22),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
"infra_pcie_gfmux_tl_o_p3_sel", 23),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
"top_xtal", 24),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
"top_xtal", 25),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
"top_xtal", 26),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
"top_xtal", 27),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
"sysaxi_sel", 28),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
"sysaxi_sel", 29),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
"sysaxi_sel", 30),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
"sysaxi_sel", 31),
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.mux_clks = infra_muxes,
.num_mux_clks = ARRAY_SIZE(infra_muxes),
.clk_lock = &mt7988_clk_lock,
};
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
static struct platform_driver clk_mt7988_infracfg_drv = {
.driver = {
.name = "clk-mt7988-infracfg",
.of_match_table = of_match_clk_mt7988_infracfg,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_infracfg_drv);

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
};
static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
"mmpll_d2" };
static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
"net1pll_d5_d2" };
static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
"mmpll" };
static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
"net1pll_d5" };
static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll",
"mmpll", "net1pll_d4",
"net1pll_d5", "mpll" };
static const char *const eip197_parents[] = { "top_xtal", "netsyspll",
"net2pll", "mmpll",
"net1pll_d4", "net1pll_d5" };
static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
"mpll_d8_d2" };
static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
"mmpll_d4" };
static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
"mmpll_d2", "mpll_d2",
"mmpll_d4", "net1pll_d8_d2" };
static const char *const spi_parents[] = { "top_xtal", "mpll_d2",
"mmpll_d4", "net1pll_d8_d2",
"net2pll_d6", "net1pll_d5_d4",
"mpll_d4", "net1pll_d8_d4" };
static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4",
"net1pll_d8_d2", "net2pll_d6",
"mpll_d4", "mmpll_d8",
"net1pll_d8_d4", "mpll_d8" };
static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal",
"net1pll_d5_d4", "mpll_d4",
"mmpll_d8", "net1pll_d8_d4",
"mmpll_d6_d2", "mpll_d8" };
static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2",
"net1pll_d5_d4", "mpll_d4",
"mpll_d8_d2", "top_rtc_32k" };
static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
"mpll_d4", "net1pll_d8_d4" };
static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
"net1pll_d5_d2" };
static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
"mmpll_d8", "mpll_d8_d2",
"top_rtc_32k" };
static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
static const char *const aud_parents[] = { "top_xtal", "apll2" };
static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
static const char *const aud_l_parents[] = { "top_xtal", "apll2",
"mpll_d8_d2" };
static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
"net1pll_d8_d4" };
static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
static const char *const eth_refck_50m_parents[] = { "top_xtal",
"net2pll_d4_d4" };
static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
"net1pll_d8_d8",
"net1pll_d8_d16" };
static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
"net2pll_d2" };
static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
"wedmcupll" };
static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
"net2pll_d8" };
static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
"net1pll_d4" };
static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
"net1pll_d8" };
static const char *const netsys_tops_400m_parents[] = { "top_xtal",
"net2pll_d2" };
static const char *const eth_mii_parents[] = { "top_xtal_d2",
"net2pll_d4_d8" };
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
axi_infra_parents, 0x020, 0x024, 0x028, 0,
1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
0x024, 0x028, 8, 2, 15, 0x1c0, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
0x1C0, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
0x1C0, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
0x034, 0x038, 0, 3, 7, 0x1c0, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
0x044, 0x048, 0, 3, 7, 0x1c0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
0x044, 0x048, 8, 2, 15, 0x1c0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
"pcie_mbist_250m_sel", pcie_mbist_250m_parents,
0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
31, 0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
15, 0x1C0, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
23, 0x1C0, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
31, 0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
0x1C0, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
0x074, 0x078, 8, 1, 15, 0x1c0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
0x1c4, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
1, 31, 0x1C4, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
7, 0x1C4, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
0x1C4, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
0x1C4, 11),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
7, 0x1c4, 13, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
15, 0x1C4, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
23, 0x1C4, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
1, 31, 0x1C4, 16),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
0x1C4, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
0x1C4, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
0x1C4, 19),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
31, 0x1C4, 20, CLK_IS_CRITICAL),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(
CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
0x1C4, 23),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
0x1C4, 24),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
0x1C4, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
0x1C4, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
23, 0x1C4, 27),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
31, 0x1C4, 28),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
7, 0x1C4, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
15, 0x1C4, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
/* CLK_CFG_16 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
0x1C8, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
"mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
16, 1, 23, 0x1C8, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
"netsys_sync_250m_sel", pcie_mbist_250m_parents,
0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
/* CLK_CFG_17 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
"netsys_tops_400m_sel", netsys_tops_400m_parents,
0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
"netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
0x1C8, 9),
/* CLK_CFG_18 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
0x1c8, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
static const struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
8, 8),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
.clk_lock = &mt7988_clk_lock,
};
static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
"net1pll_d4" };
static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
"net1pll_d4" };
static struct mtk_composite mcu_muxes[] = {
/* bus_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
/* mp2_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
};
static const struct mtk_clk_desc mcusys_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
};
static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
static struct platform_driver clk_mt7988_topckgen_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7988-topckgen",
.of_match_table = of_match_clk_mt7988_topckgen,
},
};
module_platform_driver(clk_mt7988_topckgen_drv);
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0+
#include <linux/bitfield.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/phy.h>
#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
#define MD32_EN_CFG 0x18
#define MD32_EN BIT(0)
#define BASE100T_STATUS_EXTEND 0x10
#define BASE1000T_STATUS_EXTEND 0x11
#define EXTEND_CTRL_AND_STATUS 0x16
#define PHY_AUX_CTRL_STATUS 0x1d
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
/* Registers on MDIO_MMD_VEND1 */
#define MTK_PHY_LINK_STATUS_MISC 0xa2
#define MTK_PHY_FDX_ENABLE BIT(5)
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
#define MTK_PHY_LED0_ON_LINK100 BIT(1)
#define MTK_PHY_LED0_ON_LINK10 BIT(2)
#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
#define MTK_PHY_LED0_POLARITY BIT(14)
#define MTK_PHY_LED1_ON_CTRL 0x26
#define MTK_PHY_LED1_ON_FDX BIT(4)
#define MTK_PHY_LED1_ON_HDX BIT(5)
#define MTK_PHY_LED1_POLARITY BIT(14)
enum {
PHY_AUX_SPD_10 = 0,
PHY_AUX_SPD_100,
PHY_AUX_SPD_1000,
PHY_AUX_SPD_2500,
};
static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
{
int ret;
int i;
const struct firmware *fw;
struct device *dev = &phydev->mdio.dev;
struct device_node *np;
void __iomem *dmb_addr;
void __iomem *pmb_addr;
void __iomem *mcucsr_base;
u16 reg;
struct pinctrl *pinctrl;
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
if (!np)
return -ENOENT;
dmb_addr = of_iomap(np, 0);
if (!dmb_addr)
return -ENOMEM;
pmb_addr = of_iomap(np, 1);
if (!pmb_addr)
return -ENOMEM;
mcucsr_base = of_iomap(np, 2);
if (!mcucsr_base)
return -ENOMEM;
ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
MEDAITEK_2P5GE_PHY_DMB_FW, ret);
return ret;
}
for (i = 0; i < fw->size - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
release_firmware(fw);
ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
MEDIATEK_2P5GE_PHY_PMB_FW, ret);
return ret;
}
for (i = 0; i < fw->size - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
release_firmware(fw);
reg = readw(mcucsr_base + MD32_EN_CFG);
writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
dev_dbg(dev, "Firmware loading/trigger ok.\n");
/* Setup LED */
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_POLARITY);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_ON_LINK10 |
MTK_PHY_LED0_ON_LINK100 |
MTK_PHY_LED0_ON_LINK1000 |
MTK_PHY_LED0_ON_LINK2500);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
if (IS_ERR(pinctrl)) {
dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
return PTR_ERR(pinctrl);
}
return 0;
}
static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
{
bool changed = false;
u32 adv;
int ret;
if (phydev->autoneg == AUTONEG_DISABLE) {
/* Configure half duplex with genphy_setup_forced,
* because genphy_c45_pma_setup_forced does not support.
*/
return phydev->duplex != DUPLEX_FULL
? genphy_setup_forced(phydev)
: genphy_c45_pma_setup_forced(phydev);
}
ret = genphy_c45_an_config_aneg(phydev);
if (ret < 0)
return ret;
if (ret > 0)
changed = true;
adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
ret = phy_modify_changed(phydev, MII_CTRL1000,
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
adv);
if (ret < 0)
return ret;
if (ret > 0)
changed = true;
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
{
int ret;
ret = genphy_read_abilities(phydev);
if (ret)
return ret;
/* We don't support HDX at MAC layer on mt798x.
* So mask phy's HDX capabilities, too.
*/
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
return 0;
}
static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
{
int ret;
ret = genphy_update_link(phydev);
if (ret)
return ret;
phydev->speed = SPEED_UNKNOWN;
phydev->duplex = DUPLEX_UNKNOWN;
phydev->pause = 0;
phydev->asym_pause = 0;
if (!phydev->link)
return 0;
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
ret = genphy_c45_read_lpa(phydev);
if (ret < 0)
return ret;
/* Read the link partner's 1G advertisement */
ret = phy_read(phydev, MII_STAT1000);
if (ret < 0)
return ret;
mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
} else if (phydev->autoneg == AUTONEG_DISABLE) {
linkmode_zero(phydev->lp_advertising);
}
ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
if (ret < 0)
return ret;
switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
case PHY_AUX_SPD_10:
phydev->speed = SPEED_10;
break;
case PHY_AUX_SPD_100:
phydev->speed = SPEED_100;
break;
case PHY_AUX_SPD_1000:
phydev->speed = SPEED_1000;
break;
case PHY_AUX_SPD_2500:
phydev->speed = SPEED_2500;
phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
break;
}
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
if (ret < 0)
return ret;
phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
return 0;
}
static struct phy_driver mtk_gephy_driver[] = {
{
PHY_ID_MATCH_EXACT(0x00339c11),
.name = "MediaTek MT798x 2.5GbE PHY",
.config_init = mt798x_2p5ge_phy_config_init,
.config_aneg = mt798x_2p5ge_phy_config_aneg,
.get_features = mt798x_2p5ge_phy_get_features,
.read_status = mt798x_2p5ge_phy_read_status,
},
};
module_phy_driver(mtk_gephy_driver);
static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
{ PHY_ID_MATCH_VENDOR(0x00339c00) },
{ }
};
MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
/* APMIXEDSYS */
#define CLK_APMIXED_NETSYSPLL 0
#define CLK_APMIXED_MPLL 1
#define CLK_APMIXED_MMPLL 2
#define CLK_APMIXED_APLL2 3
#define CLK_APMIXED_NET1PLL 4
#define CLK_APMIXED_NET2PLL 5
#define CLK_APMIXED_WEDMCUPLL 6
#define CLK_APMIXED_SGMPLL 7
#define CLK_APMIXED_ARM_B 8
#define CLK_APMIXED_CCIPLL2_B 9
#define CLK_APMIXED_USXGMIIPLL 10
#define CLK_APMIXED_MSDCPLL 11
/* TOPCKGEN */
#define CLK_TOP_XTAL 0
#define CLK_TOP_XTAL_D2 1
#define CLK_TOP_RTC_32K 2
#define CLK_TOP_RTC_32P7K 3
#define CLK_TOP_MPLL_D2 4
#define CLK_TOP_MPLL_D3_D2 5
#define CLK_TOP_MPLL_D4 6
#define CLK_TOP_MPLL_D8 7
#define CLK_TOP_MPLL_D8_D2 8
#define CLK_TOP_MMPLL_D2 9
#define CLK_TOP_MMPLL_D3_D5 10
#define CLK_TOP_MMPLL_D4 11
#define CLK_TOP_MMPLL_D6_D2 12
#define CLK_TOP_MMPLL_D8 13
#define CLK_TOP_APLL2_D4 14
#define CLK_TOP_NET1PLL_D4 15
#define CLK_TOP_NET1PLL_D5 16
#define CLK_TOP_NET1PLL_D5_D2 17
#define CLK_TOP_NET1PLL_D5_D4 18
#define CLK_TOP_NET1PLL_D8 19
#define CLK_TOP_NET1PLL_D8_D2 20
#define CLK_TOP_NET1PLL_D8_D4 21
#define CLK_TOP_NET1PLL_D8_D8 22
#define CLK_TOP_NET1PLL_D8_D16 23
#define CLK_TOP_NET2PLL_D2 24
#define CLK_TOP_NET2PLL_D4 25
#define CLK_TOP_NET2PLL_D4_D4 26
#define CLK_TOP_NET2PLL_D4_D8 27
#define CLK_TOP_NET2PLL_D6 28
#define CLK_TOP_NET2PLL_D8 29
#define CLK_TOP_NETSYS_SEL 30
#define CLK_TOP_NETSYS_500M_SEL 31
#define CLK_TOP_NETSYS_2X_SEL 32
#define CLK_TOP_NETSYS_GSW_SEL 33
#define CLK_TOP_ETH_GMII_SEL 34
#define CLK_TOP_NETSYS_MCU_SEL 35
#define CLK_TOP_NETSYS_PAO_2X_SEL 36
#define CLK_TOP_EIP197_SEL 37
#define CLK_TOP_AXI_INFRA_SEL 38
#define CLK_TOP_UART_SEL 39
#define CLK_TOP_EMMC_250M_SEL 40
#define CLK_TOP_EMMC_400M_SEL 41
#define CLK_TOP_SPI_SEL 42
#define CLK_TOP_SPIM_MST_SEL 43
#define CLK_TOP_NFI1X_SEL 44
#define CLK_TOP_SPINFI_SEL 45
#define CLK_TOP_PWM_SEL 46
#define CLK_TOP_I2C_SEL 47
#define CLK_TOP_PCIE_MBIST_250M_SEL 48
#define CLK_TOP_PEXTP_TL_SEL 49
#define CLK_TOP_PEXTP_TL_P1_SEL 50
#define CLK_TOP_PEXTP_TL_P2_SEL 51
#define CLK_TOP_PEXTP_TL_P3_SEL 52
#define CLK_TOP_USB_SYS_SEL 53
#define CLK_TOP_USB_SYS_P1_SEL 54
#define CLK_TOP_USB_XHCI_SEL 55
#define CLK_TOP_USB_XHCI_P1_SEL 56
#define CLK_TOP_USB_FRMCNT_SEL 57
#define CLK_TOP_USB_FRMCNT_P1_SEL 58
#define CLK_TOP_AUD_SEL 59
#define CLK_TOP_A1SYS_SEL 60
#define CLK_TOP_AUD_L_SEL 61
#define CLK_TOP_A_TUNER_SEL 62
#define CLK_TOP_SSPXTP_SEL 63
#define CLK_TOP_USB_PHY_SEL 64
#define CLK_TOP_USXGMII_SBUS_0_SEL 65
#define CLK_TOP_USXGMII_SBUS_1_SEL 66
#define CLK_TOP_SGM_0_SEL 67
#define CLK_TOP_SGM_SBUS_0_SEL 68
#define CLK_TOP_SGM_1_SEL 69
#define CLK_TOP_SGM_SBUS_1_SEL 70
#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
#define CLK_TOP_SYSAXI_SEL 73
#define CLK_TOP_SYSAPB_SEL 74
#define CLK_TOP_ETH_REFCK_50M_SEL 75
#define CLK_TOP_ETH_SYS_200M_SEL 76
#define CLK_TOP_ETH_SYS_SEL 77
#define CLK_TOP_ETH_XGMII_SEL 78
#define CLK_TOP_BUS_TOPS_SEL 79
#define CLK_TOP_NPU_TOPS_SEL 80
#define CLK_TOP_DRAMC_SEL 81
#define CLK_TOP_DRAMC_MD32_SEL 82
#define CLK_TOP_INFRA_F26M_SEL 83
#define CLK_TOP_PEXTP_P0_SEL 84
#define CLK_TOP_PEXTP_P1_SEL 85
#define CLK_TOP_PEXTP_P2_SEL 86
#define CLK_TOP_PEXTP_P3_SEL 87
#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
#define CLK_TOP_CKM_SEL 92
#define CLK_TOP_DA_SEL 93
#define CLK_TOP_PEXTP_SEL 94
#define CLK_TOP_TOPS_P2_26M_SEL 95
#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
#define CLK_TOP_MACSEC_SEL 98
#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
#define CLK_TOP_NETSYS_WARP_SEL 101
#define CLK_TOP_ETH_MII_SEL 102
#define CLK_TOP_NPU_SEL 103
#define CLK_TOP_AUD_I2S_M 104
/* MCUSYS */
#define CLK_MCU_BUS_DIV_SEL 0
#define CLK_MCU_ARM_DIV_SEL 1
/* INFRACFG_AO */
#define CLK_INFRA_MUX_UART0_SEL 0
#define CLK_INFRA_MUX_UART1_SEL 1
#define CLK_INFRA_MUX_UART2_SEL 2
#define CLK_INFRA_MUX_SPI0_SEL 3
#define CLK_INFRA_MUX_SPI1_SEL 4
#define CLK_INFRA_MUX_SPI2_SEL 5
#define CLK_INFRA_PWM_SEL 6
#define CLK_INFRA_PWM_CK1_SEL 7
#define CLK_INFRA_PWM_CK2_SEL 8
#define CLK_INFRA_PWM_CK3_SEL 9
#define CLK_INFRA_PWM_CK4_SEL 10
#define CLK_INFRA_PWM_CK5_SEL 11
#define CLK_INFRA_PWM_CK6_SEL 12
#define CLK_INFRA_PWM_CK7_SEL 13
#define CLK_INFRA_PWM_CK8_SEL 14
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
/* INFRACFG */
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
#define CLK_INFRA_66M_GPT_BCK 23
#define CLK_INFRA_66M_PWM_HCK 24
#define CLK_INFRA_66M_PWM_BCK 25
#define CLK_INFRA_66M_PWM_CK1 26
#define CLK_INFRA_66M_PWM_CK2 27
#define CLK_INFRA_66M_PWM_CK3 28
#define CLK_INFRA_66M_PWM_CK4 29
#define CLK_INFRA_66M_PWM_CK5 30
#define CLK_INFRA_66M_PWM_CK6 31
#define CLK_INFRA_66M_PWM_CK7 32
#define CLK_INFRA_66M_PWM_CK8 33
#define CLK_INFRA_133M_CQDMA_BCK 34
#define CLK_INFRA_66M_AUD_SLV_BCK 35
#define CLK_INFRA_AUD_26M 36
#define CLK_INFRA_AUD_L 37
#define CLK_INFRA_AUD_AUD 38
#define CLK_INFRA_AUD_EG2 39
#define CLK_INFRA_DRAMC_F26M 40
#define CLK_INFRA_133M_DBG_ACKM 41
#define CLK_INFRA_66M_AP_DMA_BCK 42
#define CLK_INFRA_66M_SEJ_BCK 43
#define CLK_INFRA_PRE_CK_SEJ_F13M 44
#define CLK_INFRA_26M_THERM_SYSTEM 45
#define CLK_INFRA_I2C_BCK 46
#define CLK_INFRA_52M_UART0_CK 47
#define CLK_INFRA_52M_UART1_CK 48
#define CLK_INFRA_52M_UART2_CK 49
#define CLK_INFRA_NFI 50
#define CLK_INFRA_SPINFI 51
#define CLK_INFRA_66M_NFI_HCK 52
#define CLK_INFRA_104M_SPI0 53
#define CLK_INFRA_104M_SPI1 54
#define CLK_INFRA_104M_SPI2_BCK 55
#define CLK_INFRA_66M_SPI0_HCK 56
#define CLK_INFRA_66M_SPI1_HCK 57
#define CLK_INFRA_66M_SPI2_HCK 58
#define CLK_INFRA_66M_FLASHIF_AXI 59
#define CLK_INFRA_RTC 60
#define CLK_INFRA_26M_ADC_BCK 61
#define CLK_INFRA_RC_ADC 62
#define CLK_INFRA_MSDC400 63
#define CLK_INFRA_MSDC2_HCK 64
#define CLK_INFRA_133M_MSDC_0_HCK 65
#define CLK_INFRA_66M_MSDC_0_HCK 66
#define CLK_INFRA_133M_CPUM_BCK 67
#define CLK_INFRA_BIST2FPC 68
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
#define CLK_INFRA_133M_USB_HCK 71
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
#define CLK_INFRA_66M_USB_HCK 73
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
#define CLK_INFRA_USB_SYS 75
#define CLK_INFRA_USB_SYS_CK_P1 76
#define CLK_INFRA_USB_REF 77
#define CLK_INFRA_USB_CK_P1 78
#define CLK_INFRA_USB_FRMCNT 79
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
#define CLK_INFRA_USB_PIPE 81
#define CLK_INFRA_USB_PIPE_CK_P1 82
#define CLK_INFRA_USB_UTMI 83
#define CLK_INFRA_USB_UTMI_CK_P1 84
#define CLK_INFRA_USB_XHCI 85
#define CLK_INFRA_USB_XHCI_CK_P1 86
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
#define CLK_INFRA_PCIE_PIPE_P0 91
#define CLK_INFRA_PCIE_PIPE_P1 92
#define CLK_INFRA_PCIE_PIPE_P2 93
#define CLK_INFRA_PCIE_PIPE_P3 94
#define CLK_INFRA_133M_PCIE_CK_P0 95
#define CLK_INFRA_133M_PCIE_CK_P1 96
#define CLK_INFRA_133M_PCIE_CK_P2 97
#define CLK_INFRA_133M_PCIE_CK_P3 98
/* ETHDMA */
#define CLK_ETHDMA_XGP1_EN 0
#define CLK_ETHDMA_XGP2_EN 1
#define CLK_ETHDMA_XGP3_EN 2
#define CLK_ETHDMA_FE_EN 3
#define CLK_ETHDMA_GP2_EN 4
#define CLK_ETHDMA_GP1_EN 5
#define CLK_ETHDMA_GP3_EN 6
#define CLK_ETHDMA_ESW_EN 7
#define CLK_ETHDMA_CRYPT0_EN 8
#define CLK_ETHDMA_NR_CLK 9
/* SGMIISYS_0 */
#define CLK_SGM0_TX_EN 0
#define CLK_SGM0_RX_EN 1
#define CLK_SGMII0_NR_CLK 2
/* SGMIISYS_1 */
#define CLK_SGM1_TX_EN 0
#define CLK_SGM1_RX_EN 1
#define CLK_SGMII1_NR_CLK 2
/* ETHWARP */
#define CLK_ETHWARP_WOCPU2_EN 0
#define CLK_ETHWARP_WOCPU1_EN 1
#define CLK_ETHWARP_WOCPU0_EN 2
#define CLK_ETHWARP_NR_CLK 3
#endif /* _DT_BINDINGS_CLK_MT7988_H */

597
6.1/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
View file

@ -1,597 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/reset.h>
#include <linux/hrtimer.h>
#include <linux/mii.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/of_net.h>
#include <linux/of_irq.h>
#include <linux/phy.h>
#include "mt753x.h"
#include "mt753x_swconfig.h"
#include "mt753x_regs.h"
#include "mt753x_nl.h"
#include "mt7530.h"
#include "mt7531.h"
static u32 mt753x_id;
struct list_head mt753x_devs;
static DEFINE_MUTEX(mt753x_devs_lock);
static struct mt753x_sw_id *mt753x_sw_ids[] = {
&mt7530_id,
&mt7531_id,
};
u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg)
{
u32 high, low;
mutex_lock(&gsw->host_bus->mdio_lock);
gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
(reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr,
(reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S);
high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10);
mutex_unlock(&gsw->host_bus->mdio_lock);
return (high << 16) | (low & 0xffff);
}
void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
{
mutex_lock(&gsw->host_bus->mdio_lock);
gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
(reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
gsw->host_bus->write(gsw->host_bus, gsw->smi_addr,
(reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff);
gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16);
mutex_unlock(&gsw->host_bus->mdio_lock);
}
/* Indirect MDIO clause 22/45 access */
static int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data,
u32 cmd, u32 st)
{
ktime_t timeout;
u32 val, timeout_us;
int ret = 0;
timeout_us = 100000;
timeout = ktime_add_us(ktime_get(), timeout_us);
while (1) {
val = mt753x_reg_read(gsw, PHY_IAC);
if ((val & PHY_ACS_ST) == 0)
break;
if (ktime_compare(ktime_get(), timeout) > 0)
return -ETIMEDOUT;
}
val = (st << MDIO_ST_S) |
((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
val |= data & MDIO_RW_DATA_M;
mt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST);
timeout_us = 100000;
timeout = ktime_add_us(ktime_get(), timeout_us);
while (1) {
val = mt753x_reg_read(gsw, PHY_IAC);
if ((val & PHY_ACS_ST) == 0)
break;
if (ktime_compare(ktime_get(), timeout) > 0)
return -ETIMEDOUT;
}
if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
val = mt753x_reg_read(gsw, PHY_IAC);
ret = val & MDIO_RW_DATA_M;
}
return ret;
}
int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg)
{
int val;
if (phy < MT753X_NUM_PHYS)
phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
val = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
return val;
}
void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)
{
if (phy < MT753X_NUM_PHYS)
phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
mt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
}
int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
{
int val;
if (addr < MT753X_NUM_PHYS)
addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
val = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45,
MDIO_ST_C45);
mutex_unlock(&gsw->mii_lock);
return val;
}
void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
u16 val)
{
if (addr < MT753X_NUM_PHYS)
addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
mt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45);
mutex_unlock(&gsw->mii_lock);
}
int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
{
u16 val;
if (addr < MT753X_NUM_PHYS)
addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_ADDR << MMD_CMD_S) |
((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
MDIO_CMD_WRITE, MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_DATA << MMD_CMD_S) |
((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0,
MDIO_CMD_READ, MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
return val;
}
void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
u16 val)
{
if (addr < MT753X_NUM_PHYS)
addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
mutex_lock(&gsw->mii_lock);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_ADDR << MMD_CMD_S) |
((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
MDIO_CMD_WRITE, MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_DATA << MMD_CMD_S) |
((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val,
MDIO_CMD_WRITE, MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
}
static inline int mt753x_get_duplex(const struct device_node *np)
{
return of_property_read_bool(np, "full-duplex");
}
static void mt753x_load_port_cfg(struct gsw_mt753x *gsw)
{
struct device_node *port_np;
struct device_node *fixed_link_node;
struct mt753x_port_cfg *port_cfg;
u32 port;
for_each_child_of_node(gsw->dev->of_node, port_np) {
if (!of_device_is_compatible(port_np, "mediatek,mt753x-port"))
continue;
if (!of_device_is_available(port_np))
continue;
if (of_property_read_u32(port_np, "reg", &port))
continue;
switch (port) {
case 5:
port_cfg = &gsw->port5_cfg;
break;
case 6:
port_cfg = &gsw->port6_cfg;
break;
default:
continue;
}
if (port_cfg->enabled) {
dev_info(gsw->dev, "duplicated node for port%d\n",
port_cfg->phy_mode);
continue;
}
port_cfg->np = port_np;
if (of_get_phy_mode(port_np, &port_cfg->phy_mode) < 0) {
dev_info(gsw->dev, "incorrect phy-mode %d\n", port);
continue;
}
fixed_link_node = of_get_child_by_name(port_np, "fixed-link");
if (fixed_link_node) {
u32 speed;
port_cfg->force_link = 1;
port_cfg->duplex = mt753x_get_duplex(fixed_link_node);
if (of_property_read_u32(fixed_link_node, "speed",
&speed)) {
speed = 0;
continue;
}
of_node_put(fixed_link_node);
switch (speed) {
case 10:
port_cfg->speed = MAC_SPD_10;
break;
case 100:
port_cfg->speed = MAC_SPD_100;
break;
case 1000:
port_cfg->speed = MAC_SPD_1000;
break;
case 2500:
port_cfg->speed = MAC_SPD_2500;
break;
default:
dev_info(gsw->dev, "incorrect speed %d\n",
speed);
continue;
}
}
port_cfg->enabled = 1;
}
}
static void mt753x_add_gsw(struct gsw_mt753x *gsw)
{
mutex_lock(&mt753x_devs_lock);
gsw->id = mt753x_id++;
INIT_LIST_HEAD(&gsw->list);
list_add_tail(&gsw->list, &mt753x_devs);
mutex_unlock(&mt753x_devs_lock);
}
static void mt753x_remove_gsw(struct gsw_mt753x *gsw)
{
mutex_lock(&mt753x_devs_lock);
list_del(&gsw->list);
mutex_unlock(&mt753x_devs_lock);
}
struct gsw_mt753x *mt753x_get_gsw(u32 id)
{
struct gsw_mt753x *dev;
mutex_lock(&mt753x_devs_lock);
list_for_each_entry(dev, &mt753x_devs, list) {
if (dev->id == id)
return dev;
}
mutex_unlock(&mt753x_devs_lock);
return NULL;
}
struct gsw_mt753x *mt753x_get_first_gsw(void)
{
struct gsw_mt753x *dev;
mutex_lock(&mt753x_devs_lock);
list_for_each_entry(dev, &mt753x_devs, list)
return dev;
mutex_unlock(&mt753x_devs_lock);
return NULL;
}
void mt753x_put_gsw(void)
{
mutex_unlock(&mt753x_devs_lock);
}
void mt753x_lock_gsw(void)
{
mutex_lock(&mt753x_devs_lock);
}
static int mt753x_hw_reset(struct gsw_mt753x *gsw)
{
struct device_node *np = gsw->dev->of_node;
struct reset_control *rstc;
int mcm;
int ret = -EINVAL;
mcm = of_property_read_bool(np, "mediatek,mcm");
if (mcm) {
rstc = devm_reset_control_get(gsw->dev, "mcm");
ret = IS_ERR(rstc);
if (IS_ERR(rstc)) {
dev_err(gsw->dev, "Missing reset ctrl of switch\n");
return ret;
}
reset_control_assert(rstc);
msleep(30);
reset_control_deassert(rstc);
gsw->reset_pin = -1;
return 0;
}
gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0);
if (gsw->reset_pin < 0) {
dev_err(gsw->dev, "Missing reset pin of switch\n");
return ret;
}
ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset");
if (ret) {
dev_info(gsw->dev, "Failed to request gpio %d\n",
gsw->reset_pin);
return ret;
}
gpio_direction_output(gsw->reset_pin, 0);
msleep(30);
gpio_set_value(gsw->reset_pin, 1);
msleep(500);
return 0;
}
static irqreturn_t mt753x_irq_handler(int irq, void *dev)
{
struct gsw_mt753x *gsw = dev;
disable_irq_nosync(gsw->irq);
schedule_work(&gsw->irq_worker);
return IRQ_HANDLED;
}
static int mt753x_probe(struct platform_device *pdev)
{
struct gsw_mt753x *gsw;
struct mt753x_sw_id *sw;
struct device_node *np = pdev->dev.of_node;
struct device_node *mdio;
struct mii_bus *mdio_bus;
int ret = -EINVAL;
struct chip_rev rev;
struct mt753x_mapping *map;
int i;
mdio = of_parse_phandle(np, "mediatek,mdio", 0);
if (!mdio)
return -EINVAL;
mdio_bus = of_mdio_find_bus(mdio);
if (!mdio_bus)
return -EPROBE_DEFER;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL);
if (!gsw)
return -ENOMEM;
gsw->host_bus = mdio_bus;
gsw->dev = &pdev->dev;
mutex_init(&gsw->mii_lock);
/* Switch hard reset */
if (mt753x_hw_reset(gsw))
goto fail;
/* Fetch the SMI address dirst */
if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr))
gsw->smi_addr = MT753X_DFL_SMI_ADDR;
/* Get LAN/WAN port mapping */
map = mt753x_find_mapping(np);
if (map) {
mt753x_apply_mapping(gsw, map);
gsw->global_vlan_enable = 1;
dev_info(gsw->dev, "LAN/WAN VLAN setting=%s\n", map->name);
}
/* Load MAC port configurations */
mt753x_load_port_cfg(gsw);
/* Check for valid switch and then initialize */
for (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) {
if (!mt753x_sw_ids[i]->detect(gsw, &rev)) {
sw = mt753x_sw_ids[i];
gsw->name = rev.name;
gsw->model = sw->model;
dev_info(gsw->dev, "Switch is MediaTek %s rev %d",
gsw->name, rev.rev);
/* Initialize the switch */
ret = sw->init(gsw);
if (ret)
goto fail;
break;
}
}
if (i >= ARRAY_SIZE(mt753x_sw_ids)) {
dev_err(gsw->dev, "No mt753x switch found\n");
goto fail;
}
gsw->irq = platform_get_irq(pdev, 0);
if (gsw->irq >= 0) {
ret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler,
0, dev_name(gsw->dev), gsw);
if (ret) {
dev_err(gsw->dev, "Failed to request irq %d\n",
gsw->irq);
goto fail;
}
INIT_WORK(&gsw->irq_worker, mt753x_irq_worker);
}
platform_set_drvdata(pdev, gsw);
gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node,
"mediatek,phy-poll");
mt753x_add_gsw(gsw);
mt753x_swconfig_init(gsw);
if (sw->post_init)
sw->post_init(gsw);
if (gsw->irq >= 0)
mt753x_irq_enable(gsw);
return 0;
fail:
devm_kfree(&pdev->dev, gsw);
return ret;
}
static int mt753x_remove(struct platform_device *pdev)
{
struct gsw_mt753x *gsw = platform_get_drvdata(pdev);
if (gsw->irq >= 0)
cancel_work_sync(&gsw->irq_worker);
if (gsw->reset_pin >= 0)
gpio_free(gsw->reset_pin);
#ifdef CONFIG_SWCONFIG
mt753x_swconfig_destroy(gsw);
#endif
mt753x_remove_gsw(gsw);
platform_set_drvdata(pdev, NULL);
return 0;
}
static const struct of_device_id mt753x_ids[] = {
{ .compatible = "mediatek,mt753x" },
{ },
};
MODULE_DEVICE_TABLE(of, mt753x_ids);
static struct platform_driver mt753x_driver = {
.probe = mt753x_probe,
.remove = mt753x_remove,
.driver = {
.name = "mt753x",
.of_match_table = mt753x_ids,
},
};
static int __init mt753x_init(void)
{
int ret;
INIT_LIST_HEAD(&mt753x_devs);
ret = platform_driver_register(&mt753x_driver);
mt753x_nl_init();
return ret;
}
module_init(mt753x_init);
static void __exit mt753x_exit(void)
{
mt753x_nl_exit();
platform_driver_unregister(&mt753x_driver);
}
module_exit(mt753x_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Weijie Gao <weijie.gao@mediatek.com>");
MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");

1003
6.1/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c
View file

File diff suppressed because it is too large Load diff

312
6.1/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c
View file

@ -1,312 +0,0 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include "./rtl8367c/include/rtk_switch.h"
#include "./rtl8367c/include/port.h"
#include "./rtl8367c/include/vlan.h"
#include "./rtl8367c/include/rtl8367c_asicdrv_port.h"
struct rtk_gsw {
struct device *dev;
struct mii_bus *bus;
int reset_pin;
};
static struct rtk_gsw *_gsw;
extern int gsw_debug_proc_init(void);
extern void gsw_debug_proc_exit(void);
#ifdef CONFIG_SWCONFIG
extern int rtl8367s_swconfig_init( void (*reset_func)(void) );
#endif
/*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/
unsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data)
{
struct mii_bus *bus = _gsw->bus;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
*read_data = bus->read(bus, phy_addr, phy_register);
mutex_unlock(&bus->mdio_lock);
return 0;
}
unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsigned int write_data)
{
struct mii_bus *bus = _gsw->bus;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
bus->write(bus, phy_addr, phy_register, write_data);
mutex_unlock(&bus->mdio_lock);
return 0;
}
static int rtl8367s_hw_reset(void)
{
struct rtk_gsw *gsw = _gsw;
int ret;
if (gsw->reset_pin < 0)
return 0;
ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin");
if (ret)
printk("fail to devm_gpio_request\n");
gpio_direction_output(gsw->reset_pin, 0);
usleep_range(1000, 1100);
gpio_set_value(gsw->reset_pin, 1);
mdelay(500);
gpio_free(gsw->reset_pin);
return 0;
}
static int rtl8367s_vlan_config(int want_at_p0)
{
rtk_vlan_cfg_t vlan1, vlan2;
/* Set LAN/WAN VLAN partition */
memset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t));
RTK_PORTMASK_PORT_SET(vlan1.mbr, EXT_PORT0);
RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT1);
RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT2);
RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT3);
RTK_PORTMASK_PORT_SET(vlan1.untag, EXT_PORT0);
RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1);
RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2);
RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3);
if (want_at_p0) {
RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4);
RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4);
} else {
RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT0);
RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT0);
}
vlan1.ivl_en = 1;
rtk_vlan_set(1, &vlan1);
memset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t));
RTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1);
RTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1);
if (want_at_p0) {
RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT0);
RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT0);
} else {
RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT4);
RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT4);
}
vlan2.ivl_en = 1;
rtk_vlan_set(2, &vlan2);
rtk_vlan_portPvid_set(EXT_PORT0, 1, 0);
rtk_vlan_portPvid_set(UTP_PORT1, 1, 0);
rtk_vlan_portPvid_set(UTP_PORT2, 1, 0);
rtk_vlan_portPvid_set(UTP_PORT3, 1, 0);
rtk_vlan_portPvid_set(EXT_PORT1, 2, 0);
if (want_at_p0) {
rtk_vlan_portPvid_set(UTP_PORT0, 2, 0);
rtk_vlan_portPvid_set(UTP_PORT4, 1, 0);
} else {
rtk_vlan_portPvid_set(UTP_PORT0, 1, 0);
rtk_vlan_portPvid_set(UTP_PORT4, 2, 0);
}
return 0;
}
static int rtl8367s_hw_init(void)
{
rtl8367s_hw_reset();
if(rtk_switch_init())
return -1;
mdelay(500);
if (rtk_vlan_reset())
return -1;
if (rtk_vlan_init())
return -1;
return 0;
}
static void set_rtl8367s_sgmii(void)
{
rtk_port_mac_ability_t mac_cfg;
rtk_mode_ext_t mode;
mode = MODE_EXT_HSGMII;
mac_cfg.forcemode = MAC_FORCE;
mac_cfg.speed = PORT_SPEED_2500M;
mac_cfg.duplex = PORT_FULL_DUPLEX;
mac_cfg.link = PORT_LINKUP;
mac_cfg.nway = DISABLED;
mac_cfg.txpause = ENABLED;
mac_cfg.rxpause = ENABLED;
rtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg);
rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED);
rtk_port_phyEnableAll_set(ENABLED);
}
static void set_rtl8367s_rgmii(void)
{
rtk_port_mac_ability_t mac_cfg;
rtk_mode_ext_t mode;
mode = MODE_EXT_RGMII;
mac_cfg.forcemode = MAC_FORCE;
mac_cfg.speed = PORT_SPEED_1000M;
mac_cfg.duplex = PORT_FULL_DUPLEX;
mac_cfg.link = PORT_LINKUP;
mac_cfg.nway = DISABLED;
mac_cfg.txpause = ENABLED;
mac_cfg.rxpause = ENABLED;
rtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg);
rtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3);
rtk_port_phyEnableAll_set(ENABLED);
}
void init_gsw(void)
{
rtl8367s_hw_init();
set_rtl8367s_sgmii();
set_rtl8367s_rgmii();
}
// bleow are platform driver
static const struct of_device_id rtk_gsw_match[] = {
{ .compatible = "mediatek,rtk-gsw" },
{},
};
MODULE_DEVICE_TABLE(of, rtk_gsw_match);
static int rtk_gsw_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *mdio;
struct mii_bus *mdio_bus;
struct rtk_gsw *gsw;
const char *pm;
mdio = of_parse_phandle(np, "mediatek,mdio", 0);
if (!mdio)
return -EINVAL;
mdio_bus = of_mdio_find_bus(mdio);
if (!mdio_bus)
return -EPROBE_DEFER;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL);
if (!gsw)
return -ENOMEM;
gsw->dev = &pdev->dev;
gsw->bus = mdio_bus;
gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
_gsw = gsw;
init_gsw();
//init default vlan or init swocnfig
if(!of_property_read_string(pdev->dev.of_node,
"mediatek,port_map", &pm)) {
if (!strcasecmp(pm, "wllll"))
rtl8367s_vlan_config(1);
else
rtl8367s_vlan_config(0);
} else {
#ifdef CONFIG_SWCONFIG
rtl8367s_swconfig_init(&init_gsw);
#else
rtl8367s_vlan_config(0);
#endif
}
gsw_debug_proc_init();
platform_set_drvdata(pdev, gsw);
return 0;
}
static int rtk_gsw_remove(struct platform_device *pdev)
{
platform_set_drvdata(pdev, NULL);
gsw_debug_proc_exit();
return 0;
}
static struct platform_driver gsw_driver = {
.probe = rtk_gsw_probe,
.remove = rtk_gsw_remove,
.driver = {
.name = "rtk-gsw",
.owner = THIS_MODULE,
.of_match_table = rtk_gsw_match,
},
};
module_platform_driver(gsw_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mark Lee <marklee0201@gmail.com>");
MODULE_DESCRIPTION("rtl8367c switch driver for MT7622");

11
6.1/target/linux/mediatek/mt7622/config-6.1
View file

@ -85,7 +85,10 @@ CONFIG_COMMON_CLK_MT7622=y
CONFIG_COMMON_CLK_MT7622_AUDSYS=y
CONFIG_COMMON_CLK_MT7622_ETHSYS=y
CONFIG_COMMON_CLK_MT7622_HIFSYS=y
CONFIG_COMMON_CLK_MT7981=y
CONFIG_COMMON_CLK_MT7981_ETHSYS=y
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
@ -252,7 +255,9 @@ CONFIG_MAGIC_SYSRQ=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_2P5G_PHY=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_GE_SOC_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MEMFD_CREATE=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
@ -289,6 +294,7 @@ CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_SVS=y
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
@ -298,9 +304,12 @@ CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
CONFIG_NET_DSA_MT7530_MMIO=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_USXGMII=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
@ -365,6 +374,8 @@ CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
CONFIG_PINCTRL_MT7622=y
CONFIG_PINCTRL_MT7981=y
CONFIG_PINCTRL_MT7988=y
# CONFIG_PINCTRL_MT7986 is not set
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set

609
6.1/target/linux/mediatek/mt7623/config-6.1 Normal file
View file

@ -0,0 +1,609 @@
# CONFIG_AIO is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
CONFIG_ARM_DMA_USE_IOMMU=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LED=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2701=y
CONFIG_COMMON_CLK_MT2701_AUDSYS=y
CONFIG_COMMON_CLK_MT2701_BDPSYS=y
CONFIG_COMMON_CLK_MT2701_ETHSYS=y
CONFIG_COMMON_CLK_MT2701_G3DSYS=y
CONFIG_COMMON_CLK_MT2701_HIFSYS=y
CONFIG_COMMON_CLK_MT2701_IMGSYS=y
CONFIG_COMMON_CLK_MT2701_MMSYS=y
CONFIG_COMMON_CLK_MT2701_VDECSYS=y
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
# CONFIG_COMMON_CLK_MT7629 is not set
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_COREDUMP=y
# CONFIG_CPUFREQ_DT is not set
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEBUG_MT6589_UART0=y
# CONFIG_DEBUG_MT8127_UART0 is not set
# CONFIG_DEBUG_MT8135_UART3 is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0x11004000
CONFIG_DEBUG_UART_VIRT=0xf1004000
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DIMLIB=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEDIATEK=y
# CONFIG_DRM_MEDIATEK_DP is not set
CONFIG_DRM_MEDIATEK_HDMI=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_NOMODESET=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
CONFIG_DRM_SCHED=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_ELF_CORE=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FIT_PARTITION=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_8x8=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAME_WARN=1024
CONFIG_FREEZER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HDMI=y
CONFIG_HID=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HW_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
CONFIG_IIO=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KCMP=y
# CONFIG_KEYBOARD_MT6779 is not set
CONFIG_KEYBOARD_MTK_PMIC=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_LEDS_MT6323=y
# CONFIG_LEDS_QCOM_LPG is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
CONFIG_MACH_MT7623=y
# CONFIG_MACH_MT7629 is not set
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_MT6397=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_ADSP_MBOX is not set
CONFIG_MTK_CMDQ=y
CONFIG_MTK_CMDQ_MBOX=y
CONFIG_MTK_CQDMA=y
# CONFIG_MTK_HSDMA is not set
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_IOMMU=y
CONFIG_MTK_IOMMU_V1=y
CONFIG_MTK_MMSYS=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_SMI=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_VENDOR_MEDIATEK=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_MTK_EFUSE=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IOMMU=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
CONFIG_PHY_MTK_HDMI=y
CONFIG_PHY_MTK_MIPI_DSI=y
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT2701=y
# CONFIG_PINCTRL_MT6397 is not set
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_OPP=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_MT6323 is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PREEMPT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_BUILD=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_PWM_SYSFS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MT6323=y
# CONFIG_REGULATOR_MT6331 is not set
# CONFIG_REGULATOR_MT6332 is not set
# CONFIG_REGULATOR_MT6358 is not set
# CONFIG_REGULATOR_MT6380 is not set
# CONFIG_REGULATOR_MT6397 is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MT6397 is not set
# CONFIG_RTC_DRV_MT7622 is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
# CONFIG_SPI_MTK_NOR is not set
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_SPMI_MTK_PMIF is not set
CONFIG_SRCU=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYNC_FILE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
# CONFIG_UACCE is not set
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_CDC=y
# CONFIG_USB_G_MULTI_RNDIS is not set
CONFIG_USB_HID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_MEDIATEK=y
CONFIG_USB_OTG=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_SERIAL=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

349
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@ -0,0 +1,349 @@
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CHR_DEV_SCH=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2701 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7629=y
CONFIG_COMMON_CLK_MT7629_ETHSYS=y
CONFIG_COMMON_CLK_MT7629_HIFSYS=y
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEFAULT_HOSTNAME="(mt7629)"
CONFIG_DIMLIB=y
CONFIG_DMA_OPS=y
CONFIG_DTC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_WARN=1024
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
# CONFIG_MACH_MT7623 is not set
CONFIG_MACH_MT7629=y
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_INFRACFG=y
# CONFIG_MTK_PMIC_WRAP is not set
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_TIMER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NETFILTER=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
# CONFIG_NVMEM_MTK_EFUSE is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT7629=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_PWM_SYSFS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=y
CONFIG_SPI_MTK_SNFI=y
CONFIG_SRCU=y
CONFIG_STACKTRACE=y
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MTK=y
# CONFIG_USB_XHCI_PLATFORM is not set
CONFIG_USE_OF=y
# CONFIG_VFP is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

44
6.1/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch Normal file
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@ -0,0 +1,44 @@
From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
From: Andrew Davis <afd@ti.com>
Date: Mon, 24 Oct 2022 12:34:28 -0500
Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
files
Currently DTB Overlays (.dtbo) are build from source files with the same
extension (.dts) as the base DTs (.dtb). This may become confusing and
even lead to wrong results. For example, a composite DTB (created from a
base DTB and a set of overlays) might have the same name as one of the
overlays that create it.
Different files should be generated from differently named sources.
.dtb <-> .dts
.dtbo <-> .dtso
We do not remove the ability to compile DTBO files from .dts files here,
only add a new rule allowing the .dtso file name. The current .dts named
overlays can be renamed with time. After all have been renamed we can
remove the other rule.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Frank Rowand <frowand.list@gmail.com>
Tested-by: Frank Rowand <frowand.list@gmail.com>
Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com
Signed-off-by: Rob Herring <robh@kernel.org>
---
scripts/Makefile.lib | 3 +++
1 file changed, 3 insertions(+)
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
$(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
$(call if_changed_dep,dtc)
+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
+ $(call if_changed_dep,dtc)
+
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
# Bzip2

106
6.1/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch Normal file
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@ -0,0 +1,106 @@
From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Sat, 5 Nov 2022 23:36:16 +0100
Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
Wireless Ethernet Dispatch
Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
Dispatch to offload traffic received by the wlan interface to lan/wan
one.
Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
1 file changed, 65 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -76,6 +76,47 @@
no-map;
reg = <0 0x4fc00000 0 0x00100000>;
};
+
+ wo_emi0: wo-emi@4fd00000 {
+ reg = <0 0x4fd00000 0 0x40000>;
+ no-map;
+ };
+
+ wo_emi1: wo-emi@4fd40000 {
+ reg = <0 0x4fd40000 0 0x40000>;
+ no-map;
+ };
+
+ wo_ilm0: wo-ilm@151e0000 {
+ reg = <0 0x151e0000 0 0x8000>;
+ no-map;
+ };
+
+ wo_ilm1: wo-ilm@151f0000 {
+ reg = <0 0x151f0000 0 0x8000>;
+ no-map;
+ };
+
+ wo_data: wo-data@4fd80000 {
+ reg = <0 0x4fd80000 0 0x240000>;
+ no-map;
+ };
+
+ wo_dlm0: wo-dlm@151e8000 {
+ reg = <0 0x151e8000 0 0x2000>;
+ no-map;
+ };
+
+ wo_dlm1: wo-dlm@151f8000 {
+ reg = <0 0x151f8000 0 0x2000>;
+ no-map;
+ };
+
+ wo_boot: wo-boot@15194000 {
+ reg = <0 0x15194000 0 0x1000>;
+ no-map;
+ };
+
};
timer {
@@ -239,6 +280,11 @@
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
+ <&wo_data>, <&wo_boot>;
+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+ "wo-data", "wo-boot";
+ mediatek,wo-ccif = <&wo_ccif0>;
};
wed1: wed@15011000 {
@@ -247,6 +293,25 @@
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
+ <&wo_data>, <&wo_boot>;
+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+ "wo-data", "wo-boot";
+ mediatek,wo-ccif = <&wo_ccif1>;
+ };
+
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif1: syscon@151ad000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151ad000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
eth: ethernet@15100000 {

166
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@ -0,0 +1,166 @@
From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Sun, 6 Nov 2022 09:50:24 +0100
Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
This arrange device tree nodes in alphabetical order.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
2 files changed, 58 insertions(+), 58 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -54,6 +54,53 @@
};
};
+&pio {
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_dbdc_pins: wf-dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+};
+
&switch {
ports {
#address-cells = <1>;
@@ -121,50 +168,3 @@
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
-
-&pio {
- uart1_pins: uart1-pins {
- mux {
- function = "uart";
- groups = "uart1";
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2";
- };
- };
-
- wf_2g_5g_pins: wf-2g-5g-pins {
- mux {
- function = "wifi";
- groups = "wf_2g", "wf_5g";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_dbdc_pins: wf-dbdc-pins {
- mux {
- function = "wifi";
- groups = "wf_dbdc";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA";
- drive-strength = <4>;
- };
- };
-};
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -25,10 +25,6 @@
};
};
-&uart0 {
- status = "okay";
-};
-
&eth {
status = "okay";
@@ -99,13 +95,6 @@
};
};
-&wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>;
- pinctrl-1 = <&wf_dbdc_pins>;
-};
-
&pio {
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
@@ -138,3 +127,14 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>;
+};

68
6.1/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch Normal file
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@ -0,0 +1,68 @@
From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Sun, 6 Nov 2022 09:50:27 +0100
Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
This patch adds crypto engine support for MT7986.
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++
3 files changed, 23 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -25,6 +25,10 @@
};
};
+&crypto {
+ status = "okay";
+};
+
&eth {
status = "okay";
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -223,6 +223,21 @@
status = "disabled";
};
+ crypto: crypto@10320000 {
+ compatible = "inside-secure,safexcel-eip97";
+ reg = <0 0x10320000 0 0x40000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ clocks = <&infracfg CLK_INFRA_EIP97_CK>;
+ clock-names = "infra_eip97_ck";
+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -25,6 +25,10 @@
};
};
+&crypto {
+ status = "okay";
+};
+
&eth {
status = "okay";

37
6.1/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch Normal file
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@ -0,0 +1,37 @@
From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 6 Nov 2022 09:50:29 +0100
Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
Add i2c Node to mt7986 devicetree.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -279,6 +279,20 @@
status = "disabled";
};
+ i2c0: i2c@11008000 {
+ compatible = "mediatek,mt7986-i2c";
+ reg = <0 0x11008000 0 0x90>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <5>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;

61
6.1/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch Normal file
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@ -0,0 +1,61 @@
From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Mon, 14 Nov 2022 13:16:53 +0100
Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
Missing SoC compatible in the board file causes dt bindings check.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++
4 files changed, 6 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986a RFB";
- compatible = "mediatek,mt7986a-rfb";
+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/reset/mt7986-resets.h>
/ {
+ compatible = "mediatek,mt7986a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986b RFB";
- compatible = "mediatek,mt7986b-rfb";
+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
aliases {
serial0 = &uart0;
--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -5,6 +5,9 @@
*/
#include "mt7986a.dtsi"
+/ {
+ compatible = "mediatek,mt7986b";
+};
&pio {
compatible = "mediatek,mt7986b-pinctrl";

157
6.1/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch Normal file
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@ -0,0 +1,157 @@
From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Fri, 18 Nov 2022 20:01:21 +0100
Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
This patch adds spi support for MT7986.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
3 files changed, 98 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -59,6 +59,20 @@
};
&pio {
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spic_pins: spic-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
uart1_pins: uart1-pins {
mux {
function = "uart";
@@ -105,6 +119,27 @@
};
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+};
+
&switch {
ports {
#address-cells = <1>;
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -294,6 +294,34 @@
status = "disabled";
};
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_CK>,
+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ status = "disabled";
+ };
+
+ spi1: spi@1100b000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100b000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_CK>,
+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ status = "disabled";
+ };
+
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -100,6 +100,20 @@
};
&pio {
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spic_pins: spic-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
@@ -132,6 +146,27 @@
};
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};

127
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@ -0,0 +1,127 @@
From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Fri, 6 Jan 2023 16:28:42 +0100
Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
This patch adds USB support for MT7986.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++
3 files changed, 71 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -140,6 +140,10 @@
status = "okay";
};
+&ssusb {
+ status = "okay";
+};
+
&switch {
ports {
#address-cells = <1>;
@@ -201,6 +205,10 @@
status = "okay";
};
+&usb_phy {
+ status = "okay";
+};
+
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -322,6 +322,61 @@
status = "disabled";
};
+ ssusb: usb@11200000 {
+ compatible = "mediatek,mt7986-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck",
+ "xhci_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ usb_phy: t-phy@11e10000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e10000 0x1700>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x900>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@1000 {
+ reg = <0x1000 0x700>;
+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -167,10 +167,18 @@
status = "okay";
};
+&ssusb {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
+&usb_phy {
+ status = "okay";
+};
+
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";

160
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@ -0,0 +1,160 @@
From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Fri, 6 Jan 2023 16:28:43 +0100
Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
This patch adds mmc support for MT7986.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++
2 files changed, 111 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -5,6 +5,8 @@
*/
/dts-v1/;
+#include <dt-bindings/pinctrl/mt65xx.h>
+
#include "mt7986a.dtsi"
/ {
@@ -23,6 +25,24 @@
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&crypto {
@@ -58,7 +78,83 @@
};
};
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x14014>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
&pio {
+ mmc0_pins_default: mmc0-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -345,6 +345,21 @@
status = "disabled";
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7986-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11c20000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&infracfg CLK_INFRA_MSDC_HCK_CK>,
+ <&infracfg CLK_INFRA_MSDC_CK>,
+ <&infracfg CLK_INFRA_MSDC_133M_CK>,
+ <&infracfg CLK_INFRA_MSDC_66M_CK>;
+ clock-names = "source", "hclk", "source_cg", "bus_clk",
+ "sys_cg";
+ status = "disabled";
+ };
+
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";

118
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@ -0,0 +1,118 @@
From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Fri, 6 Jan 2023 16:28:44 +0100
Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
This patch adds PCIe support for MT7986.
Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++
2 files changed, 68 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -93,6 +93,15 @@
non-removable;
no-sd;
no-sdio;
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&pcie_phy {
status = "okay";
};
@@ -155,6 +164,13 @@
};
};
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+ };
+ };
+
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
+#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7986a";
@@ -360,6 +361,57 @@
status = "disabled";
};
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x00 0x11280000 0x00 0x4000>;
+ reg-names = "pcie-mac";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0x00 0x20000000 0x00
+ 0x20000000 0x00 0x10000000>;
+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
+ <&infracfg CLK_INFRA_IPCIE_CK>,
+ <&infracfg CLK_INFRA_IPCIER_CK>,
+ <&infracfg CLK_INFRA_IPCIEB_CK>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ status = "disabled";
+
+ phys = <&pcie_port PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie_phy: t-phy@11c00000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ pcie_port: pcie-phy@11c00000 {
+ reg = <0 0x11c00000 0 0x20000>;
+ clocks = <&clk40m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";

689
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@ -0,0 +1,689 @@
From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 6 Jan 2023 16:28:45 +0100
Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
Add support for Bananapi R3 SBC.
- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
- SPI-NAND/NOR support (switched CS by sw5/C)
- all rj45 ports and both SFP working (eth1/lan4)
- all USB-Ports + SIM-Slot tested
- i2c and all uarts tested
- wifi tested (with eeprom calibration data)
The device can boot from all 4 storage options. Both, SPI and MMC, can
be switched using hardware switches on the board, see
https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 5 +
.../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++
.../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++
.../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++
.../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 +
.../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++
6 files changed, 630 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ fragment@0 {
+ target-path = "/soc/mmc@11230000";
+ __overlay__ {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x14014>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+ };
+ };
+};
+
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Authors: Daniel Golle <daniel@makrotopia.org>
+ * Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ fragment@0 {
+ target-path = "/soc/spi@1100a000";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "reserved";
+ reg = <0x80000 0x300000>;
+ };
+
+ partition@380000 {
+ label = "fip";
+ reg = <0x380000 0x200000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x7a80000>;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Authors: Daniel Golle <daniel@makrotopia.org>
+ * Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ fragment@0 {
+ target-path = "/soc/spi@1100a000";
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x20000>;
+ read-only;
+ };
+
+ partition@20000 {
+ label = "reserved";
+ reg = <0x20000 0x20000>;
+ };
+
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x40000>;
+ };
+
+ partition@80000 {
+ label = "reserved2";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition@100000 {
+ label = "fip";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "recovery";
+ reg = <0x180000 0xa80000>;
+ };
+
+ partition@c00000 {
+ label = "fit";
+ reg = <0xc00000 0x1400000>;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ fragment@0 {
+ target-path = "/soc/mmc@11230000";
+ __overlay__ {
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ status = "okay";
+ };
+ };
+};
+
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Authors: Sam.Shih <sam.shih@mediatek.com>
+ * Frank Wunderlich <frank-w@public-files.de>
+ * Daniel Golle <daniel@makrotopia.org>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+ model = "Bananapi BPI-R3";
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcin: regulator-12vd {
+ compatible = "regulator-fixed";
+ regulator-name = "12vd";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset-key {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ wps-key {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /* i2c of the left SFP cage (wan) */
+ i2c_sfp1: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* i2c of the right SFP cage (lan) */
+ i2c_sfp2: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ blue_led: led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1.8vd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&dcin>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3vd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&dcin>;
+ };
+
+ /* left SFP cage (wan) */
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* right SFP cage (lan) */
+ sfp2: sfp-2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&eth {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "2500base-x";
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&mdio {
+ switch: switch@31 {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pio {
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c";
+ };
+ };
+
+ mmc0_pins_default: mmc0-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_pereset";
+ };
+ };
+
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spic_pins: spic-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_0";
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_rx_tx";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_0_rx_tx";
+ };
+ };
+
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_dbdc_pins: wf-dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_led_pins: wf-led-pins {
+ mux {
+ function = "led";
+ groups = "wifi_led";
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins>;
+ status = "okay";
+};
+
+&ssusb {
+ status = "okay";
+};
+
+&switch {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port5: port@5 {
+ reg = <5>;
+ label = "lan4";
+ phy-mode = "2500base-x";
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+};
+
+&trng {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
+};
+

323
6.1/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch Normal file
View file

@ -0,0 +1,323 @@
From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Wed, 17 May 2023 12:11:08 +0200
Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
The chassis-type string identifies the form-factor of the system:
add this property to all device trees of devices for which the form
factor is known.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 +
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 +
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 +
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 +
.../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 +
28 files changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -11,6 +11,7 @@
/ {
model = "MediaTek MT2712 evaluation board";
+ chassis-type = "embedded";
compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek MT6755 EVB";
+ chassis-type = "embedded";
compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -10,6 +10,7 @@
/ {
model = "MediaTek MT6779 EVB";
+ chassis-type = "embedded";
compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek MT6795 Evaluation Board";
+ chassis-type = "embedded";
compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek MT6797 Evaluation Board";
+ chassis-type = "embedded";
compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
@@ -12,6 +12,7 @@
/ {
model = "Mediatek X20 Development Board";
+ chassis-type = "embedded";
compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -15,6 +15,7 @@
/ {
model = "Bananapi BPI-R64";
+ chassis-type = "embedded";
compatible = "bananapi,bpi-r64", "mediatek,mt7622";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -15,6 +15,7 @@
/ {
model = "MediaTek MT7622 RFB1 board";
+ chassis-type = "embedded";
compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -16,6 +16,7 @@
/ {
model = "Bananapi BPI-R3";
+ chassis-type = "embedded";
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -11,6 +11,7 @@
/ {
model = "MediaTek MT7986a RFB";
+ chassis-type = "embedded";
compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek MT7986b RFB";
+ chassis-type = "embedded";
compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
@@ -11,6 +11,7 @@
/ {
model = "Pumpkin MT8167";
+ chassis-type = "embedded";
compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
memory@40000000 {
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
@@ -8,6 +8,7 @@
/ {
model = "Google Hanawl";
+ chassis-type = "laptop";
compatible = "google,hana-rev7", "mediatek,mt8173";
};
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
@@ -8,6 +8,7 @@
/ {
model = "Google Hana";
+ chassis-type = "laptop";
compatible = "google,hana-rev6", "google,hana-rev5",
"google,hana-rev4", "google,hana-rev3",
"google,hana", "mediatek,mt8173";
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
@@ -8,6 +8,7 @@
/ {
model = "Google Elm";
+ chassis-type = "laptop";
compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
"google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
"google,elm", "mediatek,mt8173";
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -10,6 +10,7 @@
/ {
model = "MediaTek MT8173 evaluation board";
+ chassis-type = "embedded";
compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -11,6 +11,7 @@
/ {
model = "MediaTek MT8183 evaluation board";
+ chassis-type = "embedded";
compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
aliases {
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
@@ -9,6 +9,7 @@
/ {
model = "Google burnet board";
+ chassis-type = "convertible";
compatible = "google,burnet", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
@@ -9,6 +9,7 @@
/ {
model = "Google damu board";
+ chassis-type = "convertible";
compatible = "google,damu", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
@@ -9,6 +9,7 @@
/ {
model = "Google juniper sku16 board";
+ chassis-type = "convertible";
compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek kakadu board sku22";
+ chassis-type = "tablet";
compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
"google,kakadu", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
@@ -9,6 +9,7 @@
/ {
model = "MediaTek kakadu board";
+ chassis-type = "tablet";
compatible = "google,kakadu-rev3", "google,kakadu-rev2",
"google,kakadu", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
@@ -12,6 +12,7 @@
/ {
model = "MediaTek kodama sku16 board";
+ chassis-type = "tablet";
compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
@@ -12,6 +12,7 @@
/ {
model = "MediaTek kodama sku272 board";
+ chassis-type = "tablet";
compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
@@ -12,6 +12,7 @@
/ {
model = "MediaTek kodama sku288 board";
+ chassis-type = "tablet";
compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
@@ -14,6 +14,7 @@
/ {
model = "MediaTek krane sku0 board";
+ chassis-type = "tablet";
compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
@@ -14,6 +14,7 @@
/ {
model = "MediaTek krane sku176 board";
+ chassis-type = "tablet";
compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
};
--- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -7,6 +7,7 @@
/ {
model = "MediaTek MT8186 evaluation board";
+ chassis-type = "embedded";
compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
aliases {

38
6.1/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch Normal file
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@ -0,0 +1,38 @@
From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 21 Apr 2023 15:20:44 +0200
Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
This adds pwm node to mt7986.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -240,6 +240,20 @@
status = "disabled";
};
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #clock-cells = <1>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_STA>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2";
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";

43
6.1/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch Normal file
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@ -0,0 +1,43 @@
From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 21 Apr 2023 15:20:45 +0200
Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
Add pwm node and pinctrl to BananaPi R3 devicetree.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -275,6 +275,13 @@
};
};
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1_0";
+ };
+ };
+
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
@@ -345,6 +352,12 @@
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;

27
6.1/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch Normal file
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@ -0,0 +1,27 @@
From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 5 Feb 2023 18:48:33 +0100
Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
Leds for Wifi are low-active, so add property to devicetree.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -460,5 +460,9 @@
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
+
+ led {
+ led-active-low;
+ };
};

46
6.1/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch Normal file
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@ -0,0 +1,46 @@
From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 28 May 2023 13:33:42 +0200
Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
bl2
To store uncompressed bl2 more space is required than partition is
actually defined.
There is currently no known usage of this reserved partition.
Openwrt uses same partition layout.
We added same change to u-boot with commit d7bb1099 [1].
[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
Cc: stable@vger.kernel.org
Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
@@ -27,15 +27,10 @@
partition@0 {
label = "bl2";
- reg = <0x0 0x20000>;
+ reg = <0x0 0x40000>;
read-only;
};
- partition@20000 {
- label = "reserved";
- reg = <0x20000 0x20000>;
- };
-
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x40000>;

80
6.1/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch Normal file
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@ -0,0 +1,80 @@
From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 30 May 2023 22:12:33 +0200
Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
Add thermal related nodes to mt7986 devicetree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -337,6 +337,15 @@
status = "disabled";
};
+ auxadc: adc@1100d000 {
+ compatible = "mediatek,mt7986-auxadc";
+ reg = <0 0x1100d000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
ssusb: usb@11200000 {
compatible = "mediatek,mt7986-xhci",
"mediatek,mtk-xhci";
@@ -375,6 +384,21 @@
status = "disabled";
};
+ thermal: thermal@1100c800 {
+ #thermal-sensor-cells = <1>;
+ compatible = "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>,
+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
+ clock-names = "therm", "auxadc", "adc_32k";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
@@ -426,6 +450,17 @@
};
};
+ efuse: efuse@11d00000 {
+ compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
+ reg = <0 0x11d00000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@274 {
+ reg = <0x274 0xc>;
+ };
+ };
+
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
@@ -567,5 +602,4 @@
memory-region = <&wmcpu_emi>;
};
};
-
};

51
6.1/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch Normal file
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@ -0,0 +1,51 @@
From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 30 May 2023 22:12:34 +0200
Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
Add thermal-zones to mt7986 devicetree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -602,4 +602,32 @@
memory-region = <&wmcpu_emi>;
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu_trip_active_high: active-high {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_passive: passive {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+ };
+ };
};

64
6.1/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch Normal file
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@ -0,0 +1,64 @@
From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 30 May 2023 22:12:35 +0200
Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
BPI-R3 dts
Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -38,6 +38,15 @@
regulator-always-on;
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ /* cooling level (0, 1, 2) - pwm inverted */
+ cooling-levels = <255 96 0>;
+ pwms = <&pwm 0 10000 0>;
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -133,6 +142,28 @@
};
};
+&cpu_thermal {
+ cooling-maps {
+ cpu-active-high {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ cpu-active-low {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_low>;
+ };
+
+ cpu-passive {
+ /* passive: set fan to cooling level 0 */
+ cooling-device = <&fan 0 0>;
+ trip = <&cpu_trip_passive>;
+ };
+ };
+};
+
&crypto {
status = "okay";
};

41
6.1/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch Normal file
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@ -0,0 +1,41 @@
From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 6 Jun 2023 16:43:20 +0100
Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
Bananapi R3
The bootrom burned into the MT7986 SoC will try multiple locations on
the SPI-NAND flash to load bl2 in case the bl2 image located at the the
previously attempted offset is corrupt.
Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
allowing for up to four redundant copies of bl2 (typically sized a
bit less than 0x40000).
Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
@@ -29,13 +29,13 @@
partition@0 {
label = "bl2";
- reg = <0x0 0x80000>;
+ reg = <0x0 0x100000>;
read-only;
};
- partition@80000 {
+ partition@100000 {
label = "reserved";
- reg = <0x80000 0x300000>;
+ reg = <0x100000 0x280000>;
};
partition@380000 {

10
6.1/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch
View file

@ -10,7 +10,7 @@
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
@@ -23,7 +22,7 @@
@@ -24,7 +23,7 @@
chosen {
stdout-path = "serial0:115200n8";
@ -19,7 +19,7 @@
};
cpus {
@@ -44,18 +43,18 @@
@@ -45,18 +44,18 @@
key-factory {
label = "factory";
linux,code = <BTN_0>;
@ -41,7 +41,7 @@
};
reg_1p8v: regulator-1p8v {
@@ -131,22 +130,22 @@
@@ -132,22 +131,22 @@
port@0 {
reg = <0>;
@ -68,7 +68,7 @@
};
port@4 {
@@ -239,7 +238,22 @@
@@ -240,7 +239,22 @@
status = "okay";
};
@ -91,7 +91,7 @@
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
@@ -516,11 +530,11 @@
@@ -517,11 +531,11 @@
};
&sata {

2
6.1/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch
View file

@ -40,7 +40,7 @@
};
};
};
@@ -272,3 +281,17 @@
@@ -273,3 +282,17 @@
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};

2
6.1/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -558,6 +558,7 @@
@@ -578,6 +578,7 @@
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;

9
6.1/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch
View file

@ -1,14 +1,5 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -118,7 +118,7 @@
};
psci {
- compatible = "arm,psci-0.2";
+ compatible = "arm,psci-1.0";
method = "smc";
};
@@ -134,6 +134,13 @@
#size-cells = <2>;
ranges;

2
6.1/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -22,7 +22,7 @@
@@ -24,7 +24,7 @@
chosen {
stdout-path = "serial0:115200n8";

4
6.1/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -18,6 +18,7 @@
@@ -20,6 +20,7 @@
aliases {
serial0 = &uart0;
@ -8,7 +8,7 @@
};
chosen {
@@ -160,22 +161,22 @@
@@ -164,22 +165,22 @@
port@1 {
reg = <1>;

33
6.1/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -20,6 +20,10 @@
@@ -21,6 +21,10 @@
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
@ -11,7 +11,7 @@
};
chosen {
@@ -43,8 +47,8 @@
@@ -44,8 +48,8 @@
compatible = "gpio-keys";
factory-key {
@ -22,17 +22,15 @@
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
@@ -58,19 +62,25 @@
@@ -59,17 +63,17 @@
leds {
compatible = "gpio-leds";
- led-0 {
- label = "bpi-r64:pio:green";
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+ led_system_blue: blue {
+ label = "bpi-r64:pio:blue";
+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
+ led_system_green: led-0 {
label = "bpi-r64:pio:green";
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@ -40,19 +38,10 @@
- label = "bpi-r64:pio:red";
- color = <LED_COLOR_ID_RED>;
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+ led_system_green: green {
+ label = "bpi-r64:pio:green";
+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+ led_system_blue: led-1 {
+ label = "bpi-r64:pio:blue";
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
+
+/*
+ * red {
+ * label = "bpi-r64:pio:red";
+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+ * default-state = "off";
+ * };
+ */
};
memory {

2
6.1/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -564,12 +564,16 @@
@@ -558,12 +558,16 @@
status = "okay";
};

2
6.1/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -259,14 +259,42 @@
@@ -255,14 +255,42 @@
status = "disabled";
};

4
6.1/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch
View file

@ -1,6 +1,6 @@
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -714,7 +714,7 @@ static int spinand_mtd_write(struct mtd_
@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
{
struct spinand_device *spinand = nand_to_spinand(nand);
@ -9,7 +9,7 @@
struct nand_page_io_req req = {
.pos = *pos,
.ooblen = sizeof(marker),
@@ -725,7 +725,7 @@ static bool spinand_isbad(struct nand_de
@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
spinand_select_target(spinand, pos->target);
spinand_read_page(spinand, &req);

2
6.1/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch
View file

@ -41,7 +41,7 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
"mediatek,mt7622-spi";
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -254,6 +254,50 @@
@@ -255,6 +255,50 @@
};
};

2
6.1/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -539,6 +539,65 @@
@@ -538,6 +538,65 @@
status = "disabled";
};

4
6.1/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -580,7 +580,7 @@
@@ -579,7 +579,7 @@
reg = <0x140000 0x0080000>;
};
@ -9,7 +9,7 @@
label = "Factory";
reg = <0x1c0000 0x0100000>;
};
@@ -641,5 +641,6 @@
@@ -640,5 +640,6 @@
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&wmac_pins>;

2
6.1/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -951,17 +951,15 @@
@@ -984,17 +984,15 @@
};
crypto: crypto@1b240000 {

69
6.1/target/linux/mediatek/patches-6.1/173-arm-dts-mt7623-add-musb-device-nodes.patch
View file

@ -1,69 +0,0 @@
From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
From: Sungbo Eo <mans0n@gorani.run>
Date: Sun, 8 Aug 2021 21:38:40 +0900
Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
MT7623 has an musb controller that is compatible with the one from MT2701.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
---
arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623a.dtsi | 4 ++++
2 files changed, 38 insertions(+)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -585,6 +585,40 @@
status = "disabled";
};
+ usb0: usb@11200000 {
+ compatible = "mediatek,mt7623-musb",
+ "mediatek,mtk-musb";
+ reg = <0 0x11200000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ status = "disabled";
+ };
+
+ u2phy1: t-phy@11210000 {
+ compatible = "mediatek,mt7623-tphy",
+ "mediatek,generic-tphy-v1";
+ reg = <0 0x11210000 0 0x0800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port2: usb-phy@11210800 {
+ reg = <0 0x11210800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7623-audsys",
"mediatek,mt2701-audsys",
--- a/arch/arm/boot/dts/mt7623a.dtsi
+++ b/arch/arm/boot/dts/mt7623a.dtsi
@@ -35,6 +35,10 @@
clock-names = "ethif";
};
+&usb0 {
+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
+};
+
&usb1 {
power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
};

2
6.1/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -160,6 +160,10 @@
@@ -156,6 +156,10 @@
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;

2
6.1/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
View file

@ -95,7 +95,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -339,7 +339,7 @@
@@ -346,7 +346,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10310000 0 0x1000>,

17
6.1/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch Normal file
View file

@ -0,0 +1,17 @@
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -68,6 +68,14 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+
+ /* 64 KiB reserved for ramoops/pstore */
+ ramoops@42ff0000 {
+ compatible = "ramoops";
+ reg = <0 0x42ff0000 0 0x10000>;
+ record-size = <0x1000>;
+ };
+
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;

196
6.1/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch Normal file
View file

@ -0,0 +1,196 @@
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -23,6 +23,10 @@
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
+ led-boot = &green_led;
+ led-failsafe = &green_led;
+ led-running = &green_led;
+ led-upgrade = &blue_led;
};
chosen {
@@ -417,27 +421,27 @@
port@1 {
reg = <1>;
- label = "lan0";
+ label = "lan1";
};
port@2 {
reg = <2>;
- label = "lan1";
+ label = "lan2";
};
port@3 {
reg = <3>;
- label = "lan2";
+ label = "lan3";
};
port@4 {
reg = <4>;
- label = "lan3";
+ label = "lan4";
};
port5: port@5 {
reg = <5>;
- label = "lan4";
+ label = "sfp2";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
@@ -488,9 +492,137 @@
&wifi {
status = "okay";
- pinctrl-names = "default", "dbdc";
+ pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
+
+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
led {
led-active-low;
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
@@ -55,6 +55,7 @@
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
+ compatible = "denx,fit";
};
};
};

88
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@ -0,0 +1,88 @@
From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Sat, 8 Oct 2022 18:48:06 +0200
Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
separately
Some mt7986 boards use uart rts/cts pins as gpio,
This patch allows to change rts/cts to gpio mode, but keep
rx/tx as UART function.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
1 file changed, 25 insertions(+), 7 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
+
+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
+
+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
+
+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
+
static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
+ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
+ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
+ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
+ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
+ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
static const char *mt7986_spi_groups[] = {
"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
static const char *mt7986_uart_groups[] = {
- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
+ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
+ "uart1_2_rx_tx", "uart1_2_cts_rts",
+ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
};
static const char *mt7986_wdt_groups[] = { "watchdog", };

100
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@ -0,0 +1,100 @@
From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Sun, 6 Nov 2022 09:01:13 +0100
Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
MT7986 SoC
Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
add SoC specify 'pull_type' attribute for bias configuration.
This patch add pull_type attribute to pinctrl-mt7986.c, and make
bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
1 file changed, 56 insertions(+)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
};
+static const unsigned int mt7986_pull_type[] = {
+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
+ MTK_PULL_PU_PD_TYPE,/*100*/
+};
+
static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
.ies_present = false,
.base_names = mt7986_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
+ .pull_type = mt7986_pull_type,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
.ies_present = false,
.base_names = mt7986_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
+ .pull_type = mt7986_pull_type,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,

1094
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30
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@ -0,0 +1,30 @@
From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
Date: Sat, 18 Feb 2023 09:51:06 +0300
Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
There are options missing from PINCTRL_MT7981 whilst being on every other
pin controller. Add them.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/mediatek/Kconfig | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -130,6 +130,8 @@ config PINCTRL_MT7622
config PINCTRL_MT7981
bool "Mediatek MT7981 pin control"
depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
config PINCTRL_MT7986

536
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@ -0,0 +1,536 @@
From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:33 +0100
Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
mtk_clk_register_gates()
Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpose of propagating a
struct device pointer to the clk API when registering the mtk-gate
clocks to take advantage of Runtime PM when/where needed and where
a power domain is defined in devicetree.
Function mtk_clk_register_gates() then becomes a wrapper around the
new mtk_clk_register_gates_with_dev() function that will simply pass
NULL as struct device: this is essential when registering drivers
with CLK_OF_DECLARE instead of as a platform device, as there will
be no struct device to pass... but we can as well simply have only
one function that always takes such pointer as a param and pass NULL
when unavoidable.
This commit removes the mtk_clk_register_gates() wrapper and renames
mtk_clk_register_gates_with_dev() to the former and all of the calls
to either of the two functions were fixed in all drivers in order to
reflect this change; also, to improve consistency with other kernel
functions, the pointer to struct device was moved as the first param.
Since a lot of MediaTek clock drivers are actually registering as a
platform device, but were still registering the mtk-gate clocks
without passing any struct device to the clock framework, they've
been changed to pass a valid one now, as to make all those platforms
able to use runtime power management where available.
While at it, some much needed indentation changes were also done.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[daniel@makrotopia.org: dropped parts not relevant for OpenWrt]
---
drivers/clk/mediatek/clk-gate.c | 23 +++++++---------------
drivers/clk/mediatek/clk-gate.h | 7 +------
drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++--
drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++--
drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++--
drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++--
drivers/clk/mediatek/clk-mt2701.c | 12 +++++------
drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++--
drivers/clk/mediatek/clk-mt2712.c | 12 +++++------
drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++--
drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++----
drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++----
drivers/clk/mediatek/clk-mt7622.c | 14 ++++++-------
drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++---
drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++----
drivers/clk/mediatek/clk-mt7629.c | 10 +++++-----
drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++-----
drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++--
19 files changed, 68 insertions(+), 81 deletions(-)
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
-static struct clk_hw *mtk_clk_register_gate(const char *name,
+static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
const char *parent_name,
struct regmap *regmap, int set_ofs,
int clr_ofs, int sta_ofs, u8 bit,
const struct clk_ops *ops,
- unsigned long flags, struct device *dev)
+ unsigned long flags)
{
struct mtk_clk_gate *cg;
int ret;
@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
kfree(cg);
}
-int mtk_clk_register_gates_with_dev(struct device_node *node,
- const struct mtk_gate *clks, int num,
- struct clk_hw_onecell_data *clk_data,
- struct device *dev)
+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
+ const struct mtk_gate *clks, int num,
+ struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk_hw *hw;
@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
continue;
}
- hw = mtk_clk_register_gate(gate->name, gate->parent_name,
+ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
regmap,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
gate->shift, gate->ops,
- gate->flags, dev);
+ gate->flags);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", gate->name,
@@ -261,14 +260,6 @@ err:
return PTR_ERR(hw);
}
-EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
-
-int mtk_clk_register_gates(struct device_node *node,
- const struct mtk_gate *clks, int num,
- struct clk_hw_onecell_data *clk_data)
-{
- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
-}
EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -50,15 +50,10 @@ struct mtk_gate {
#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
-int mtk_clk_register_gates(struct device_node *node,
+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_hw_onecell_data *clk_data);
-int mtk_clk_register_gates_with_dev(struct device_node *node,
- const struct mtk_gate *clks, int num,
- struct clk_hw_onecell_data *clk_data,
- struct device *dev);
-
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
struct clk_hw_onecell_data *clk_data);
--- a/drivers/clk/mediatek/clk-mt2701-aud.c
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+ ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+ ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, hif_clks,
+ ARRAY_SIZE(hif_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
--- a/drivers/clk/mediatek/clk-mt2701-mm.c
+++ b/drivers/clk/mediatek/clk-mt2701-mm.c
@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
clk_data = mtk_alloc_clk_data(CLK_MM_NR);
- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
+ ARRAY_SIZE(mm_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -683,8 +683,8 @@ static int mtk_topckgen_init(struct plat
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt2701_clk_lock, clk_data);
- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
+ ARRAY_SIZE(top_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
@@ -783,8 +783,8 @@ static int mtk_infrasys_init(struct plat
}
}
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- infra_clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), infra_clk_data);
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
@@ -894,8 +894,8 @@ static int mtk_pericfg_init(struct platf
clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
&mt2701_clk_lock, clk_data);
--- a/drivers/clk/mediatek/clk-mt2712-mm.c
+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
+ ARRAY_SIZE(mm_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
&mt2712_clk_lock, top_clk_data);
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
&mt2712_clk_lock, top_clk_data);
- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
- top_clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
+ ARRAY_SIZE(top_clks), top_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+ ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+ ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
+ ARRAY_SIZE(sgmii_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+ ARRAY_SIZE(ssusb_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+ ARRAY_SIZE(pcie_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt7622_clk_lock, clk_data);
- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
+ ARRAY_SIZE(top_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
clk_data);
@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
clk_data);
- mtk_clk_register_gates(node, apmixed_clks,
+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
&mt7622_clk_lock, clk_data);
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -80,7 +80,8 @@ static int clk_mt7629_ethsys_init(struct
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+ CLK_ETH_NR_CLK, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -102,8 +103,8 @@ static int clk_mt7629_sgmiisys_init(stru
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
+ CLK_SGMII_NR_CLK, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+ ARRAY_SIZE(ssusb_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+ ARRAY_SIZE(pcie_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -581,8 +581,8 @@ static int mtk_infrasys_init(struct plat
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
clk_data);
@@ -604,8 +604,8 @@ static int mtk_pericfg_init(struct platf
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
&mt7629_clk_lock, clk_data);
@@ -631,7 +631,7 @@ static int mtk_apmixedsys_init(struct pl
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
clk_data);
- mtk_clk_register_gates(node, apmixed_clks,
+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
--- a/drivers/clk/mediatek/clk-mt7986-eth.c
+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
- clk_data);
+ mtk_clk_register_gates(NULL, node, sgmii0_clks,
+ ARRAY_SIZE(sgmii0_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
- clk_data);
+ mtk_clk_register_gates(NULL, node, sgmii1_clks,
+ ARRAY_SIZE(sgmii1_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
&mt7986_clk_lock, clk_data);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
- clk_data, &pdev->dev);
+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
+ clk_data);
if (r)
goto free_data;

140
6.1/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch Normal file
View file

@ -0,0 +1,140 @@
From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:34 +0100
Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
possible
Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
Even though runtime pm is unlikely to be used with CPU muxes, this
helps with code consistency and possibly opens to commonization of
some mtk_clk_register_(x) functions.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-cpumux.c | 8 ++++----
drivers/clk/mediatek/clk-cpumux.h | 2 +-
drivers/clk/mediatek/clk-mt2701.c | 2 +-
drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
drivers/clk/mediatek/clk-mt7622.c | 4 ++--
drivers/clk/mediatek/clk-mt7629.c | 4 ++--
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
7 files changed, 14 insertions(+), 13 deletions(-)
--- a/drivers/clk/mediatek/clk-cpumux.c
+++ b/drivers/clk/mediatek/clk-cpumux.c
@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
};
static struct clk_hw *
-mtk_clk_register_cpumux(const struct mtk_composite *mux,
+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
struct regmap *regmap)
{
struct mtk_clk_cpumux *cpumux;
@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
cpumux->regmap = regmap;
cpumux->hw.init = &init;
- ret = clk_hw_register(NULL, &cpumux->hw);
+ ret = clk_hw_register(dev, &cpumux->hw);
if (ret) {
kfree(cpumux);
return ERR_PTR(ret);
@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
kfree(cpumux);
}
-int mtk_clk_register_cpumuxes(struct device_node *node,
+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
const struct mtk_composite *clks, int num,
struct clk_hw_onecell_data *clk_data)
{
@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
continue;
}
- hw = mtk_clk_register_cpumux(mux, regmap);
+ hw = mtk_clk_register_cpumux(dev, mux, regmap);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,
hw);
--- a/drivers/clk/mediatek/clk-cpumux.h
+++ b/drivers/clk/mediatek/clk-cpumux.h
@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
struct device_node;
struct mtk_composite;
-int mtk_clk_register_cpumuxes(struct device_node *node,
+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
const struct mtk_composite *clks, int num,
struct clk_hw_onecell_data *clk_data);
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -757,7 +757,7 @@ static void __init mtk_infrasys_init_ear
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
if (ret)
goto free_clk_data;
- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
+ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
+ ARRAY_SIZE(cpu_muxes), clk_data);
if (ret)
goto unregister_gates;
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- clk_data);
+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
+ ARRAY_SIZE(infra_muxes), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
clk_data);
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -584,8 +584,8 @@ static int mtk_infrasys_init(struct plat
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- clk_data);
+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
+ ARRAY_SIZE(infra_muxes), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
clk_data);
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
clk_data);
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
- clk_data);
+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
+ ARRAY_SIZE(cpu_muxes), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)

181
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@ -0,0 +1,181 @@
From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:35 +0100
Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
composites
Like done for cpumux clocks, propagate struct device for composite
clocks registered through clk-mtk helpers to be able to get runtime
pm support for MTK clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[daniel@makrotopia.org: remove parts not relevant for OpenWrt]
---
drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
drivers/clk/mediatek/clk-mt7622.c | 8 +++++---
drivers/clk/mediatek/clk-mt7629.c | 8 +++++---
drivers/clk/mediatek/clk-mtk.c | 11 ++++++-----
drivers/clk/mediatek/clk-mtk.h | 3 ++-
6 files changed, 32 insertions(+), 20 deletions(-)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data);
- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
- base, &mt2701_clk_lock, clk_data);
+ mtk_clk_register_composites(&pdev->dev, top_muxes,
+ ARRAY_SIZE(top_muxes), base,
+ &mt2701_clk_lock, clk_data);
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt2701_clk_lock, clk_data);
@@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
- &mt2701_clk_lock, clk_data);
+ mtk_clk_register_composites(&pdev->dev, peri_muxs,
+ ARRAY_SIZE(peri_muxs), base,
+ &mt2701_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
top_clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
- &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_composites(&pdev->dev, top_muxes,
+ ARRAY_SIZE(top_muxes), base,
+ &mt2712_clk_lock, top_clk_data);
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
&mt2712_clk_lock, top_clk_data);
mtk_clk_register_gates(&pdev->dev, node, top_clks,
@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
- &mt2712_clk_lock, clk_data);
+ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
+ ARRAY_SIZE(mcu_muxes), base,
+ &mt2712_clk_lock, clk_data);
+ if (r)
+ dev_err(&pdev->dev, "Could not register composites: %d\n", r);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
clk_data);
- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
- base, &mt7622_clk_lock, clk_data);
+ mtk_clk_register_composites(&pdev->dev, top_muxes,
+ ARRAY_SIZE(top_muxes), base,
+ &mt7622_clk_lock, clk_data);
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt7622_clk_lock, clk_data);
@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ mtk_clk_register_composites(&pdev->dev, peri_muxes,
+ ARRAY_SIZE(peri_muxes), base,
&mt7622_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
clk_data);
- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
- base, &mt7629_clk_lock, clk_data);
+ mtk_clk_register_composites(&pdev->dev, top_muxes,
+ ARRAY_SIZE(top_muxes), base,
+ &mt7629_clk_lock, clk_data);
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
@@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ mtk_clk_register_composites(&pdev->dev, peri_muxes,
+ ARRAY_SIZE(peri_muxes), base,
&mt7629_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
-static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
- void __iomem *base, spinlock_t *lock)
+static struct clk_hw *mtk_clk_register_composite(struct device *dev,
+ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
{
struct clk_hw *hw;
struct clk_mux *mux = NULL;
@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
div_ops = &clk_divider_ops;
}
- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
+ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
mux_hw, mux_ops,
div_hw, div_ops,
gate_hw, gate_ops,
@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
kfree(mux);
}
-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
+int mtk_clk_register_composites(struct device *dev,
+ const struct mtk_composite *mcs, int num,
void __iomem *base, spinlock_t *lock,
struct clk_hw_onecell_data *clk_data)
{
@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
continue;
}
- hw = mtk_clk_register_composite(mc, base, lock);
+ hw = mtk_clk_register_composite(dev, mc, base, lock);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mc->name,
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -149,7 +149,8 @@ struct mtk_composite {
.flags = 0, \
}
-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
+int mtk_clk_register_composites(struct device *dev,
+ const struct mtk_composite *mcs, int num,
void __iomem *base, spinlock_t *lock,
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,

103
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@ -0,0 +1,103 @@
From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:36 +0100
Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
mtk-mux
Like done for other clocks, propagate struct device for mtk mux clocks
registered through clk-mux helpers to enable runtime pm support.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
---
drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++-
drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++-
drivers/clk/mediatek/clk-mux.c | 14 ++++++++------
drivers/clk/mediatek/clk-mux.h | 3 ++-
4 files changed, 14 insertions(+), 9 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
return -ENOMEM;
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+ mtk_clk_register_muxes(&pdev->dev, infra_muxes,
+ ARRAY_SIZE(infra_muxes), node,
&mt7986_clk_lock, clk_data);
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
+ mtk_clk_register_muxes(&pdev->dev, top_muxes,
+ ARRAY_SIZE(top_muxes), node,
&mt7986_clk_lock, clk_data);
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
- struct regmap *regmap,
- spinlock_t *lock)
+static struct clk_hw *mtk_clk_register_mux(struct device *dev,
+ const struct mtk_mux *mux,
+ struct regmap *regmap,
+ spinlock_t *lock)
{
struct mtk_clk_mux *clk_mux;
struct clk_init_data init = {};
@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
clk_mux->lock = lock;
clk_mux->hw.init = &init;
- ret = clk_hw_register(NULL, &clk_mux->hw);
+ ret = clk_hw_register(dev, &clk_mux->hw);
if (ret) {
kfree(clk_mux);
return ERR_PTR(ret);
@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
kfree(mux);
}
-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+int mtk_clk_register_muxes(struct device *dev,
+ const struct mtk_mux *muxes,
int num, struct device_node *node,
spinlock_t *lock,
struct clk_hw_onecell_data *clk_data)
@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
continue;
}
- hw = mtk_clk_register_mux(mux, regmap, lock);
+ hw = mtk_clk_register_mux(dev, mux, regmap, lock);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,
--- a/drivers/clk/mediatek/clk-mux.h
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+int mtk_clk_register_muxes(struct device *dev,
+ const struct mtk_mux *muxes,
int num, struct device_node *node,
spinlock_t *lock,
struct clk_hw_onecell_data *clk_data);

74
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@ -0,0 +1,74 @@
From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:37 +0100
Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
In order to migrate some (few) old clock drivers to the common
mtk_clk_simple_probe() function, add dummy clock ops to be able
to insert a dummy clock with ID 0 at the beginning of the list.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
2 files changed, 35 insertions(+)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -18,6 +18,22 @@
#include "clk-mtk.h"
#include "clk-gate.h"
+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
+EXPORT_SYMBOL_GPL(cg_regs_dummy);
+
+static int mtk_clk_dummy_enable(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
+
+const struct clk_ops mtk_clk_dummy_ops = {
+ .enable = mtk_clk_dummy_enable,
+ .disable = mtk_clk_dummy_disable,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
+
static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
unsigned int clk_num)
{
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -22,6 +22,25 @@
struct platform_device;
+/*
+ * We need the clock IDs to start from zero but to maintain devicetree
+ * backwards compatibility we can't change bindings to start from zero.
+ * Only a few platforms are affected, so we solve issues given by the
+ * commonized MTK clocks probe function(s) by adding a dummy clock at
+ * the beginning where needed.
+ */
+#define CLK_DUMMY 0
+
+extern const struct clk_ops mtk_clk_dummy_ops;
+extern const struct mtk_gate_regs cg_regs_dummy;
+
+#define GATE_DUMMY(_id, _name) { \
+ .id = _id, \
+ .name = _name, \
+ .regs = &cg_regs_dummy, \
+ .ops = &mtk_clk_dummy_ops, \
+ }
+
struct mtk_fixed_clk {
int id;
const char *name;

790
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@ -0,0 +1,790 @@
From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:41 +0100
Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
possible
mtk_clk_simple_probe() is a function that registers mtk gate clocks
and, if reset data is present, a reset controller and across all of
the MTK clock drivers, such a function is duplicated many times:
switch to the common mtk_clk_simple_probe() function for all of the
clock drivers that are registering as platform drivers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
---
drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++----------------
drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
9 files changed, 144 insertions(+), 406 deletions(-)
--- a/drivers/clk/mediatek/clk-mt2701-aud.c
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
};
static const struct mtk_gate audio_clks[] = {
+ GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
/* AUDIO0 */
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
+static const struct mtk_clk_desc audio_desc = {
+ .clks = audio_clks,
+ .num_clks = ARRAY_SIZE(audio_clks),
+};
+
static const struct of_device_id of_match_clk_mt2701_aud[] = {
- { .compatible = "mediatek,mt2701-audsys", },
- {}
+ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
+ { /* sentinel */ }
};
static int clk_mt2701_aud_probe(struct platform_device *pdev)
{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
-
- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
- ARRAY_SIZE(audio_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
- goto err_clk_provider;
+ return r;
}
r = devm_of_platform_populate(&pdev->dev);
@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
return 0;
err_plat_populate:
- of_clk_del_provider(node);
-err_clk_provider:
+ mtk_clk_simple_remove(pdev);
return r;
}
+static int clk_mt2701_aud_remove(struct platform_device *pdev)
+{
+ of_platform_depopulate(&pdev->dev);
+ return mtk_clk_simple_remove(pdev);
+}
+
static struct platform_driver clk_mt2701_aud_drv = {
.probe = clk_mt2701_aud_probe,
+ .remove = clk_mt2701_aud_remove,
.driver = {
.name = "clk-mt2701-aud",
.of_match_table = of_match_clk_mt2701_aud,
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate eth_clks[] = {
+ GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static const struct of_device_id of_match_clk_mt2701_eth[] = {
- { .compatible = "mediatek,mt2701-ethsys", },
- {}
+static const struct mtk_clk_desc eth_desc = {
+ .clks = eth_clks,
+ .num_clks = ARRAY_SIZE(eth_clks),
+ .rst_desc = &clk_rst_desc,
};
-static int clk_mt2701_eth_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
-
- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
- ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return r;
-}
+static const struct of_device_id of_match_clk_mt2701_eth[] = {
+ { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
+ { /* sentinel */ }
+};
static struct platform_driver clk_mt2701_eth_drv = {
- .probe = clk_mt2701_eth_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-eth",
.of_match_table = of_match_clk_mt2701_eth,
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
};
static const struct mtk_gate g3d_clks[] = {
+ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
};
@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
-
- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
- clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return r;
-}
+static const struct mtk_clk_desc g3d_desc = {
+ .clks = g3d_clks,
+ .num_clks = ARRAY_SIZE(g3d_clks),
+ .rst_desc = &clk_rst_desc,
+};
static const struct of_device_id of_match_clk_mt2701_g3d[] = {
- {
- .compatible = "mediatek,mt2701-g3dsys",
- .data = clk_mt2701_g3dsys_init,
- }, {
- /* sentinel */
- }
+ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
+ { /* sentinel */ }
};
-static int clk_mt2701_g3d_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt2701_g3d_drv = {
- .probe = clk_mt2701_g3d_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-g3d",
.of_match_table = of_match_clk_mt2701_g3d,
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate hif_clks[] = {
+ GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static const struct of_device_id of_match_clk_mt2701_hif[] = {
- { .compatible = "mediatek,mt2701-hifsys", },
- {}
+static const struct mtk_clk_desc hif_desc = {
+ .clks = hif_clks,
+ .num_clks = ARRAY_SIZE(hif_clks),
+ .rst_desc = &clk_rst_desc,
};
-static int clk_mt2701_hif_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
-
- mtk_clk_register_gates(&pdev->dev, node, hif_clks,
- ARRAY_SIZE(hif_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
- return r;
- }
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return 0;
-}
+static const struct of_device_id of_match_clk_mt2701_hif[] = {
+ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
+ { /* sentinel */ }
+};
static struct platform_driver clk_mt2701_hif_drv = {
- .probe = clk_mt2701_hif_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-hif",
.of_match_table = of_match_clk_mt2701_hif,
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
return r;
}
-static int clk_mt2712_infra_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
- if (r != 0)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
-
- return r;
-}
-
-static int clk_mt2712_peri_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- ARRAY_SIZE(peri_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
- if (r != 0)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
-
- return r;
-}
-
static int clk_mt2712_mcu_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
.compatible = "mediatek,mt2712-topckgen",
.data = clk_mt2712_top_probe,
}, {
- .compatible = "mediatek,mt2712-infracfg",
- .data = clk_mt2712_infra_probe,
- }, {
- .compatible = "mediatek,mt2712-pericfg",
- .data = clk_mt2712_peri_probe,
- }, {
.compatible = "mediatek,mt2712-mcucfg",
.data = clk_mt2712_mcu_probe,
}, {
@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
return r;
}
+static const struct mtk_clk_desc infra_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .rst_desc = &clk_rst_desc[0],
+};
+
+static const struct mtk_clk_desc peri_desc = {
+ .clks = peri_clks,
+ .num_clks = ARRAY_SIZE(peri_clks),
+ .rst_desc = &clk_rst_desc[1],
+};
+
+static const struct of_device_id of_match_clk_mt2712_simple[] = {
+ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
+ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt2712_simple_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt2712-simple",
+ .of_match_table = of_match_clk_mt2712_simple,
+ },
+};
+
static struct platform_driver clk_mt2712_drv = {
.probe = clk_mt2712_probe,
.driver = {
@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
static int __init clk_mt2712_init(void)
{
- return platform_driver_register(&clk_mt2712_drv);
+ int ret = platform_driver_register(&clk_mt2712_drv);
+
+ if (ret)
+ return ret;
+ return platform_driver_register(&clk_mt2712_simple_drv);
}
arch_initcall(clk_mt2712_init);
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
-static int clk_mt7622_audiosys_init(struct platform_device *pdev)
+static const struct mtk_clk_desc audio_desc = {
+ .clks = audio_clks,
+ .num_clks = ARRAY_SIZE(audio_clks),
+};
+
+static int clk_mt7622_aud_probe(struct platform_device *pdev)
{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
- ARRAY_SIZE(audio_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
- goto err_clk_provider;
+ return r;
}
r = devm_of_platform_populate(&pdev->dev);
@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
return 0;
err_plat_populate:
- of_clk_del_provider(node);
-err_clk_provider:
+ mtk_clk_simple_remove(pdev);
return r;
}
-static const struct of_device_id of_match_clk_mt7622_aud[] = {
- {
- .compatible = "mediatek,mt7622-audsys",
- .data = clk_mt7622_audiosys_init,
- }, {
- /* sentinel */
- }
-};
-
-static int clk_mt7622_aud_probe(struct platform_device *pdev)
+static int clk_mt7622_aud_remove(struct platform_device *pdev)
{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
+ of_platform_depopulate(&pdev->dev);
+ return mtk_clk_simple_remove(pdev);
}
+static const struct of_device_id of_match_clk_mt7622_aud[] = {
+ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
+ { /* sentinel */ }
+};
+
static struct platform_driver clk_mt7622_aud_drv = {
.probe = clk_mt7622_aud_probe,
+ .remove = clk_mt7622_aud_remove,
.driver = {
.name = "clk-mt7622-aud",
.of_match_table = of_match_clk_mt7622_aud,
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static int clk_mt7622_ethsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
- ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return r;
-}
-
-static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
- ARRAY_SIZE(sgmii_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
+static const struct mtk_clk_desc eth_desc = {
+ .clks = eth_clks,
+ .num_clks = ARRAY_SIZE(eth_clks),
+ .rst_desc = &clk_rst_desc,
+};
- return r;
-}
+static const struct mtk_clk_desc sgmii_desc = {
+ .clks = sgmii_clks,
+ .num_clks = ARRAY_SIZE(sgmii_clks),
+};
static const struct of_device_id of_match_clk_mt7622_eth[] = {
- {
- .compatible = "mediatek,mt7622-ethsys",
- .data = clk_mt7622_ethsys_init,
- }, {
- .compatible = "mediatek,mt7622-sgmiisys",
- .data = clk_mt7622_sgmiisys_init,
- }, {
- /* sentinel */
- }
+ { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
+ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
+ { /* sentinel */ }
};
-static int clk_mt7622_eth_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt7622_eth_drv = {
- .probe = clk_mt7622_eth_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-eth",
.of_match_table = of_match_clk_mt7622_eth,
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
- ARRAY_SIZE(ssusb_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return r;
-}
-
-static int clk_mt7622_pciesys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
- ARRAY_SIZE(pcie_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+static const struct mtk_clk_desc ssusb_desc = {
+ .clks = ssusb_clks,
+ .num_clks = ARRAY_SIZE(ssusb_clks),
+ .rst_desc = &clk_rst_desc,
+};
- return r;
-}
+static const struct mtk_clk_desc pcie_desc = {
+ .clks = pcie_clks,
+ .num_clks = ARRAY_SIZE(pcie_clks),
+ .rst_desc = &clk_rst_desc,
+};
static const struct of_device_id of_match_clk_mt7622_hif[] = {
- {
- .compatible = "mediatek,mt7622-pciesys",
- .data = clk_mt7622_pciesys_init,
- }, {
- .compatible = "mediatek,mt7622-ssusbsys",
- .data = clk_mt7622_ssusbsys_init,
- }, {
- /* sentinel */
- }
+ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
+ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
+ { /* sentinel */ }
};
-static int clk_mt7622_hif_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt7622_hif_drv = {
- .probe = clk_mt7622_hif_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-hif",
.of_match_table = of_match_clk_mt7622_hif,
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
-static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
- ARRAY_SIZE(ssusb_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-
- return r;
-}
-
-static int clk_mt7629_pciesys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
-
- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
- ARRAY_SIZE(pcie_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+static const struct mtk_clk_desc ssusb_desc = {
+ .clks = ssusb_clks,
+ .num_clks = ARRAY_SIZE(ssusb_clks),
+ .rst_desc = &clk_rst_desc,
+};
- return r;
-}
+static const struct mtk_clk_desc pcie_desc = {
+ .clks = pcie_clks,
+ .num_clks = ARRAY_SIZE(pcie_clks),
+ .rst_desc = &clk_rst_desc,
+};
static const struct of_device_id of_match_clk_mt7629_hif[] = {
- {
- .compatible = "mediatek,mt7629-pciesys",
- .data = clk_mt7629_pciesys_init,
- }, {
- .compatible = "mediatek,mt7629-ssusbsys",
- .data = clk_mt7629_ssusbsys_init,
- }, {
- /* sentinel */
- }
+ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
+ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
+ { /* sentinel */ }
};
-static int clk_mt7629_hif_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt7629_hif_drv = {
- .probe = clk_mt7629_hif_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7629-hif",
.of_match_table = of_match_clk_mt7629_hif,

189
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@ -0,0 +1,189 @@
From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:42 +0100
Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
As a preparation to increase probe functions commonization across
various MediaTek SoC clock controller drivers, extend function
mtk_clk_simple_probe() to be able to register not only gates, but
also fixed clocks, factors, muxes and composites.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
drivers/clk/mediatek/clk-mtk.h | 10 ++++
2 files changed, 103 insertions(+), 8 deletions(-)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -11,12 +11,14 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-mtk.h"
#include "clk-gate.h"
+#include "clk-mux.h"
const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
EXPORT_SYMBOL_GPL(cg_regs_dummy);
@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
const struct mtk_clk_desc *mcd;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
- int r;
+ void __iomem *base;
+ int num_clks, r;
mcd = of_device_get_match_data(&pdev->dev);
if (!mcd)
return -EINVAL;
- clk_data = mtk_alloc_clk_data(mcd->num_clks);
+ /* Composite clocks needs us to pass iomem pointer */
+ if (mcd->composite_clks) {
+ if (!mcd->shared_io)
+ base = devm_platform_ioremap_resource(pdev, 0);
+ else
+ base = of_iomap(node, 0);
+
+ if (IS_ERR_OR_NULL(base))
+ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
+ }
+
+ /* Calculate how many clk_hw_onecell_data entries to allocate */
+ num_clks = mcd->num_clks + mcd->num_composite_clks;
+ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
+ num_clks += mcd->num_mux_clks;
+
+ clk_data = mtk_alloc_clk_data(num_clks);
if (!clk_data)
return -ENOMEM;
- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
- clk_data);
- if (r)
- goto free_data;
+ if (mcd->fixed_clks) {
+ r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
+ mcd->num_fixed_clks, clk_data);
+ if (r)
+ goto free_data;
+ }
+
+ if (mcd->factor_clks) {
+ r = mtk_clk_register_factors(mcd->factor_clks,
+ mcd->num_factor_clks, clk_data);
+ if (r)
+ goto unregister_fixed_clks;
+ }
+
+ if (mcd->mux_clks) {
+ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
+ mcd->num_mux_clks, node,
+ mcd->clk_lock, clk_data);
+ if (r)
+ goto unregister_factors;
+ };
+
+ if (mcd->composite_clks) {
+ /* We don't check composite_lock because it's optional */
+ r = mtk_clk_register_composites(&pdev->dev,
+ mcd->composite_clks,
+ mcd->num_composite_clks,
+ base, mcd->clk_lock, clk_data);
+ if (r)
+ goto unregister_muxes;
+ }
+
+ if (mcd->clks) {
+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
+ mcd->num_clks, clk_data);
+ if (r)
+ goto unregister_composites;
+ }
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
return r;
unregister_clks:
- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
+ if (mcd->clks)
+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
+unregister_composites:
+ if (mcd->composite_clks)
+ mtk_clk_unregister_composites(mcd->composite_clks,
+ mcd->num_composite_clks, clk_data);
+unregister_muxes:
+ if (mcd->mux_clks)
+ mtk_clk_unregister_muxes(mcd->mux_clks,
+ mcd->num_mux_clks, clk_data);
+unregister_factors:
+ if (mcd->factor_clks)
+ mtk_clk_unregister_factors(mcd->factor_clks,
+ mcd->num_factor_clks, clk_data);
+unregister_fixed_clks:
+ if (mcd->fixed_clks)
+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
+ mcd->num_fixed_clks, clk_data);
free_data:
mtk_free_clk_data(clk_data);
+ if (mcd->shared_io && base)
+ iounmap(base);
return r;
}
EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
+ if (mcd->clks)
+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
+ if (mcd->composite_clks)
+ mtk_clk_unregister_composites(mcd->composite_clks,
+ mcd->num_composite_clks, clk_data);
+ if (mcd->mux_clks)
+ mtk_clk_unregister_muxes(mcd->mux_clks,
+ mcd->num_mux_clks, clk_data);
+ if (mcd->factor_clks)
+ mtk_clk_unregister_factors(mcd->factor_clks,
+ mcd->num_factor_clks, clk_data);
+ if (mcd->fixed_clks)
+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
+ mcd->num_fixed_clks, clk_data);
mtk_free_clk_data(clk_data);
return 0;
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
struct mtk_clk_desc {
const struct mtk_gate *clks;
size_t num_clks;
+ const struct mtk_composite *composite_clks;
+ size_t num_composite_clks;
+ const struct mtk_fixed_clk *fixed_clks;
+ size_t num_fixed_clks;
+ const struct mtk_fixed_factor *factor_clks;
+ size_t num_factor_clks;
+ const struct mtk_mux *mux_clks;
+ size_t num_mux_clks;
const struct mtk_clk_rst_desc *rst_desc;
+ spinlock_t *clk_lock;
+ bool shared_io;
};
int mtk_clk_simple_probe(struct platform_device *pdev);

97
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@ -0,0 +1,97 @@
From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:52 +0100
Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
clocks enabled
Instead of calling clk_prepare_enable() on a bunch of clocks at probe
time, set the CLK_IS_CRITICAL flag to the same as these are required
to be always on, and this is the right way of achieving that.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
1 file changed, 24 insertions(+), 22 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
0x1C0, 10),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
+ f_26m_adc_parents, 0x020, 0x024, 0x028,
+ 24, 1, 31, 0x1C0, 11,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_3 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
- 0x1C0, 12),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+ dramc_md32_parents, 0x030, 0x034, 0x038,
+ 0, 1, 7, 0x1C0, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
+ sysaxi_parents, 0x030, 0x034, 0x038,
+ 8, 2, 15, 0x1C0, 13,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
+ sysapb_parents, 0x030, 0x034, 0x038,
+ 16, 2, 23, 0x1C0, 14,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
31, 0x1C0, 15),
@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
0x1C0, 21),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
- 0x1C0, 22),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
+ sgm_reg_parents, 0x050, 0x054, 0x058,
+ 16, 1, 23, 0x1C0, 22,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
0x1C0, 27),
/* CLK_CFG_7 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
- 0x1C0, 28),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
+ f_26m_adc_parents, 0x070, 0x074, 0x078,
+ 0, 1, 7, 0x1C0, 28,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
ARRAY_SIZE(top_muxes), node,
&mt7986_clk_lock, clk_data);
- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
-
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {

88
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@ -0,0 +1,88 @@
From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 20 Jan 2023 10:20:53 +0100
Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
mtk_clk_simple_probe()
There are no more non-common calls in clk_mt7986_topckgen_probe():
migrate this driver to mtk_clk_simple_probe().
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
1 file changed, 13 insertions(+), 42 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
0x1C4, 5),
};
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
- ARRAY_SIZE(top_muxes);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
- mtk_clk_register_muxes(&pdev->dev, top_muxes,
- ARRAY_SIZE(top_muxes), node,
- &mt7986_clk_lock, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_topckgen_data;
- }
- return r;
-
-free_topckgen_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc topck_desc = {
+ .fixed_clks = top_fixed_clks,
+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+ .factor_clks = top_divs,
+ .num_factor_clks = ARRAY_SIZE(top_divs),
+ .mux_clks = top_muxes,
+ .num_mux_clks = ARRAY_SIZE(top_muxes),
+ .clk_lock = &mt7986_clk_lock,
+};
static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
- { .compatible = "mediatek,mt7986-topckgen", },
- {}
+ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
+ { /* sentinel */ }
};
static struct platform_driver clk_mt7986_topckgen_drv = {
- .probe = clk_mt7986_topckgen_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7986-topckgen",
.of_match_table = of_match_clk_mt7986_topckgen,

38
6.1/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch Normal file
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@ -0,0 +1,38 @@
From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Mon, 6 Mar 2023 15:05:21 +0100
Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
critical clock
Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
@@ -42,7 +42,7 @@
"clkxtal")
static const struct mtk_pll_data plls[] = {
- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
0x0200, 4, 0, 0x0204, 0),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
0x0210, 4, 0, 0x0214, 0),
@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
-
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",

237
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@ -0,0 +1,237 @@
From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 26 Jan 2023 03:34:05 +0000
Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
infracfg, and ethernet subsystem clocks.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
.../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++
1 file changed, 215 insertions(+)
create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7981_H
+#define _DT_BINDINGS_CLK_MT7981_H
+
+/* TOPCKGEN */
+#define CLK_TOP_CB_CKSQ_40M 0
+#define CLK_TOP_CB_M_416M 1
+#define CLK_TOP_CB_M_D2 2
+#define CLK_TOP_CB_M_D3 3
+#define CLK_TOP_M_D3_D2 4
+#define CLK_TOP_CB_M_D4 5
+#define CLK_TOP_CB_M_D8 6
+#define CLK_TOP_M_D8_D2 7
+#define CLK_TOP_CB_MM_720M 8
+#define CLK_TOP_CB_MM_D2 9
+#define CLK_TOP_CB_MM_D3 10
+#define CLK_TOP_CB_MM_D3_D5 11
+#define CLK_TOP_CB_MM_D4 12
+#define CLK_TOP_CB_MM_D6 13
+#define CLK_TOP_MM_D6_D2 14
+#define CLK_TOP_CB_MM_D8 15
+#define CLK_TOP_CB_APLL2_196M 16
+#define CLK_TOP_APLL2_D2 17
+#define CLK_TOP_APLL2_D4 18
+#define CLK_TOP_NET1_2500M 19
+#define CLK_TOP_CB_NET1_D4 20
+#define CLK_TOP_CB_NET1_D5 21
+#define CLK_TOP_NET1_D5_D2 22
+#define CLK_TOP_NET1_D5_D4 23
+#define CLK_TOP_CB_NET1_D8 24
+#define CLK_TOP_NET1_D8_D2 25
+#define CLK_TOP_NET1_D8_D4 26
+#define CLK_TOP_CB_NET2_800M 27
+#define CLK_TOP_CB_NET2_D2 28
+#define CLK_TOP_CB_NET2_D4 29
+#define CLK_TOP_NET2_D4_D2 30
+#define CLK_TOP_NET2_D4_D4 31
+#define CLK_TOP_CB_NET2_D6 32
+#define CLK_TOP_CB_WEDMCU_208M 33
+#define CLK_TOP_CB_SGM_325M 34
+#define CLK_TOP_CKSQ_40M_D2 35
+#define CLK_TOP_CB_RTC_32K 36
+#define CLK_TOP_CB_RTC_32P7K 37
+#define CLK_TOP_USB_TX250M 38
+#define CLK_TOP_FAUD 39
+#define CLK_TOP_NFI1X 40
+#define CLK_TOP_USB_EQ_RX250M 41
+#define CLK_TOP_USB_CDR_CK 42
+#define CLK_TOP_USB_LN0_CK 43
+#define CLK_TOP_SPINFI_BCK 44
+#define CLK_TOP_SPI 45
+#define CLK_TOP_SPIM_MST 46
+#define CLK_TOP_UART_BCK 47
+#define CLK_TOP_PWM_BCK 48
+#define CLK_TOP_I2C_BCK 49
+#define CLK_TOP_PEXTP_TL 50
+#define CLK_TOP_EMMC_208M 51
+#define CLK_TOP_EMMC_400M 52
+#define CLK_TOP_DRAMC_REF 53
+#define CLK_TOP_DRAMC_MD32 54
+#define CLK_TOP_SYSAXI 55
+#define CLK_TOP_SYSAPB 56
+#define CLK_TOP_ARM_DB_MAIN 57
+#define CLK_TOP_AP2CNN_HOST 58
+#define CLK_TOP_NETSYS 59
+#define CLK_TOP_NETSYS_500M 60
+#define CLK_TOP_NETSYS_WED_MCU 61
+#define CLK_TOP_NETSYS_2X 62
+#define CLK_TOP_SGM_325M 63
+#define CLK_TOP_SGM_REG 64
+#define CLK_TOP_F26M 65
+#define CLK_TOP_EIP97B 66
+#define CLK_TOP_USB3_PHY 67
+#define CLK_TOP_AUD 68
+#define CLK_TOP_A1SYS 69
+#define CLK_TOP_AUD_L 70
+#define CLK_TOP_A_TUNER 71
+#define CLK_TOP_U2U3_REF 72
+#define CLK_TOP_U2U3_SYS 73
+#define CLK_TOP_U2U3_XHCI 74
+#define CLK_TOP_USB_FRMCNT 75
+#define CLK_TOP_NFI1X_SEL 76
+#define CLK_TOP_SPINFI_SEL 77
+#define CLK_TOP_SPI_SEL 78
+#define CLK_TOP_SPIM_MST_SEL 79
+#define CLK_TOP_UART_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_I2C_SEL 82
+#define CLK_TOP_PEXTP_TL_SEL 83
+#define CLK_TOP_EMMC_208M_SEL 84
+#define CLK_TOP_EMMC_400M_SEL 85
+#define CLK_TOP_F26M_SEL 86
+#define CLK_TOP_DRAMC_SEL 87
+#define CLK_TOP_DRAMC_MD32_SEL 88
+#define CLK_TOP_SYSAXI_SEL 89
+#define CLK_TOP_SYSAPB_SEL 90
+#define CLK_TOP_ARM_DB_MAIN_SEL 91
+#define CLK_TOP_AP2CNN_HOST_SEL 92
+#define CLK_TOP_NETSYS_SEL 93
+#define CLK_TOP_NETSYS_500M_SEL 94
+#define CLK_TOP_NETSYS_MCU_SEL 95
+#define CLK_TOP_NETSYS_2X_SEL 96
+#define CLK_TOP_SGM_325M_SEL 97
+#define CLK_TOP_SGM_REG_SEL 98
+#define CLK_TOP_EIP97B_SEL 99
+#define CLK_TOP_USB3_PHY_SEL 100
+#define CLK_TOP_AUD_SEL 101
+#define CLK_TOP_A1SYS_SEL 102
+#define CLK_TOP_AUD_L_SEL 103
+#define CLK_TOP_A_TUNER_SEL 104
+#define CLK_TOP_U2U3_SEL 105
+#define CLK_TOP_U2U3_SYS_SEL 106
+#define CLK_TOP_U2U3_XHCI_SEL 107
+#define CLK_TOP_USB_FRMCNT_SEL 108
+#define CLK_TOP_AUD_I2S_M 109
+
+/* INFRACFG */
+#define CLK_INFRA_66M_MCK 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_SPI2_SEL 6
+#define CLK_INFRA_PWM1_SEL 7
+#define CLK_INFRA_PWM2_SEL 8
+#define CLK_INFRA_PWM3_SEL 9
+#define CLK_INFRA_PWM_BSEL 10
+#define CLK_INFRA_PCIE_SEL 11
+#define CLK_INFRA_GPT_STA 12
+#define CLK_INFRA_PWM_HCK 13
+#define CLK_INFRA_PWM_STA 14
+#define CLK_INFRA_PWM1_CK 15
+#define CLK_INFRA_PWM2_CK 16
+#define CLK_INFRA_PWM3_CK 17
+#define CLK_INFRA_CQ_DMA_CK 18
+#define CLK_INFRA_AUD_BUS_CK 19
+#define CLK_INFRA_AUD_26M_CK 20
+#define CLK_INFRA_AUD_L_CK 21
+#define CLK_INFRA_AUD_AUD_CK 22
+#define CLK_INFRA_AUD_EG2_CK 23
+#define CLK_INFRA_DRAMC_26M_CK 24
+#define CLK_INFRA_DBG_CK 25
+#define CLK_INFRA_AP_DMA_CK 26
+#define CLK_INFRA_SEJ_CK 27
+#define CLK_INFRA_SEJ_13M_CK 28
+#define CLK_INFRA_THERM_CK 29
+#define CLK_INFRA_I2C0_CK 30
+#define CLK_INFRA_UART0_CK 31
+#define CLK_INFRA_UART1_CK 32
+#define CLK_INFRA_UART2_CK 33
+#define CLK_INFRA_SPI2_CK 34
+#define CLK_INFRA_SPI2_HCK_CK 35
+#define CLK_INFRA_NFI1_CK 36
+#define CLK_INFRA_SPINFI1_CK 37
+#define CLK_INFRA_NFI_HCK_CK 38
+#define CLK_INFRA_SPI0_CK 39
+#define CLK_INFRA_SPI1_CK 40
+#define CLK_INFRA_SPI0_HCK_CK 41
+#define CLK_INFRA_SPI1_HCK_CK 42
+#define CLK_INFRA_FRTC_CK 43
+#define CLK_INFRA_MSDC_CK 44
+#define CLK_INFRA_MSDC_HCK_CK 45
+#define CLK_INFRA_MSDC_133M_CK 46
+#define CLK_INFRA_MSDC_66M_CK 47
+#define CLK_INFRA_ADC_26M_CK 48
+#define CLK_INFRA_ADC_FRC_CK 49
+#define CLK_INFRA_FBIST2FPC_CK 50
+#define CLK_INFRA_I2C_MCK_CK 51
+#define CLK_INFRA_I2C_PCK_CK 52
+#define CLK_INFRA_IUSB_133_CK 53
+#define CLK_INFRA_IUSB_66M_CK 54
+#define CLK_INFRA_IUSB_SYS_CK 55
+#define CLK_INFRA_IUSB_CK 56
+#define CLK_INFRA_IPCIE_CK 57
+#define CLK_INFRA_IPCIE_PIPE_CK 58
+#define CLK_INFRA_IPCIER_CK 59
+#define CLK_INFRA_IPCIEB_CK 60
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
+
+/* SGMIISYS_0 */
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
+
+/* SGMIISYS_1 */
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
+
+/* ETHSYS */
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU0_EN 3
+
+#endif /* _DT_BINDINGS_CLK_MT7981_H */

932
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@ -0,0 +1,932 @@
From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 26 Jan 2023 03:34:24 +0000
Subject: [PATCH] clk: mediatek: add MT7981 clock support
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
ethernet subsystem clocks.
The drivers are based on clk-mt7981.c which can be found in MediaTek's
SDK sources. To be fit for upstream inclusion the driver has been split
into clock domains and the infracfg part has been significantly
de-bloated by removing all the 1:1 factors (aliases).
Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[sboyd@kernel.org: Add module license]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/mediatek/Kconfig | 17 +
drivers/clk/mediatek/Makefile | 4 +
drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++
drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++
drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
6 files changed, 870 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
This driver supports MediaTek MT7629 HIFSYS clocks providing
to PCI-E and USB.
+config COMMON_CLK_MT7981
+ bool "Clock driver for MediaTek MT7981"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT7981 basic clocks and clocks
+ required for various peripherals found on this SoC.
+
+config COMMON_CLK_MT7981_ETHSYS
+ tristate "Clock driver for MediaTek MT7981 ETHSYS"
+ depends on COMMON_CLK_MT7981
+ default COMMON_CLK_MT7981
+ help
+ This driver adds support for clocks for Ethernet and SGMII
+ required on MediaTek MT7981 SoC.
+
config COMMON_CLK_MT7986
bool "Clock driver for MediaTek MT7986"
depends on ARCH_MEDIATEK || COMPILE_TEST
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+#include <linux/clk.h>
+
+#define MT7981_PLL_FMAX (2500UL * MHZ)
+#define CON0_MT7981_RST_BAR BIT(27)
+
+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ _div_table, _parent_name) \
+ { \
+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, .flags = _flags, \
+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, .div_table = _div_table, \
+ .parent_name = _parent_name, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
+ "clkxtal")
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
+ 32, 0x0200, 4, 0, 0x0204, 0),
+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
+ 0x0210, 4, 0, 0x0214, 0),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
+ 0x0220, 4, 0, 0x0224, 0),
+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
+ 0x0230, 4, 0, 0x0234, 0),
+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
+ 0x0240, 4, 0, 0x0244, 0),
+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
+ 0x0250, 4, 0, 0x0254, 0),
+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
+ 0x0260, 4, 0, 0x0264, 0),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
+ 0x0278, 4, 0, 0x027C, 0),
+};
+
+static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
+ { .compatible = "mediatek,mt7981-apmixedsys", },
+ { /* sentinel */ }
+};
+
+static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
+ if (!clk_data)
+ return -ENOMEM;
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+ goto free_apmixed_data;
+ }
+ return r;
+
+free_apmixed_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static struct platform_driver clk_mt7981_apmixed_drv = {
+ .probe = clk_mt7981_apmixed_probe,
+ .driver = {
+ .name = "clk-mt7981-apmixed",
+ .of_match_table = of_match_clk_mt7981_apmixed,
+ },
+};
+builtin_platform_driver(clk_mt7981_apmixed_drv);
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7981-eth.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+
+static const struct mtk_gate_regs sgmii0_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &sgmii0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii0_clks[] __initconst = {
+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
+};
+
+static const struct mtk_gate_regs sgmii1_cg_regs = {
+ .set_ofs = 0xE4,
+ .clr_ofs = 0xE4,
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &sgmii1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii1_clks[] __initconst = {
+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
+};
+
+static const struct mtk_gate_regs eth_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &eth_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate eth_clks[] __initconst = {
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
+};
+
+static const struct mtk_clk_desc eth_desc = {
+ .clks = eth_clks,
+ .num_clks = ARRAY_SIZE(eth_clks),
+};
+
+static const struct mtk_clk_desc sgmii0_desc = {
+ .clks = sgmii0_clks,
+ .num_clks = ARRAY_SIZE(sgmii0_clks),
+};
+
+static const struct mtk_clk_desc sgmii1_desc = {
+ .clks = sgmii1_clks,
+ .num_clks = ARRAY_SIZE(sgmii1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt7981_eth[] = {
+ { .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
+ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
+ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt7981_eth_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7981-eth",
+ .of_match_table = of_match_clk_mt7981_eth,
+ },
+};
+module_platform_driver(clk_mt7981_eth_drv);
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-mux.h"
+
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+#include <linux/clk.h>
+
+static DEFINE_SPINLOCK(mt7981_clk_lock);
+
+static const struct mtk_fixed_factor infra_divs[] = {
+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
+};
+
+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
+ "uart_sel" };
+
+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
+ "spi_sel" };
+
+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
+ "spim_mst_sel" };
+
+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
+
+static const char *const infra_pwm_bsel_parents[] __initconst = {
+ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
+};
+
+static const char *const infra_pcie_parents[] __initconst = {
+ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
+};
+
+static const struct mtk_mux infra_muxes[] = {
+ /* MODULE_CLK_SEL_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
+ 2, -1, -1, -1),
+ /* MODULE_CLK_SEL_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
+ -1, -1, -1),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x54,
+ .sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x60,
+ .clr_ofs = 0x64,
+ .sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra0_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_INFRA1(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra1_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_INFRA2(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra2_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ /* INFRA0 */
+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
+
+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
+ 14),
+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
+ /* INFRA1 */
+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
+ 13),
+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
+ 14),
+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
+ /* INFRA2 */
+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
+ 13),
+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
+};
+
+static const struct mtk_clk_desc infracfg_desc = {
+ .factor_clks = infra_divs,
+ .num_factor_clks = ARRAY_SIZE(infra_divs),
+ .mux_clks = infra_muxes,
+ .num_mux_clks = ARRAY_SIZE(infra_muxes),
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .clk_lock = &mt7981_clk_lock,
+};
+
+static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
+ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt7981_infracfg_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7981-infracfg",
+ .of_match_table = of_match_clk_mt7981_infracfg,
+ },
+};
+builtin_platform_driver(clk_mt7981_infracfg_drv);
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
+ */
+
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-mux.h"
+
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+#include <linux/clk.h>
+
+static DEFINE_SPINLOCK(mt7981_clk_lock);
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
+};
+
+static const char * const nfi1x_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_mm_d4",
+ "net1_d8_d2",
+ "cb_net2_d6",
+ "cb_m_d4",
+ "cb_mm_d8",
+ "net1_d8_d4",
+ "cb_m_d8"
+};
+
+static const char * const spinfi_parents[] __initconst = {
+ "cksq_40m_d2",
+ "cb_cksq_40m",
+ "net1_d5_d4",
+ "cb_m_d4",
+ "cb_mm_d8",
+ "net1_d8_d4",
+ "mm_d6_d2",
+ "cb_m_d8"
+};
+
+static const char * const spi_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_m_d2",
+ "cb_mm_d4",
+ "net1_d8_d2",
+ "cb_net2_d6",
+ "net1_d5_d4",
+ "cb_m_d4",
+ "net1_d8_d4"
+};
+
+static const char * const uart_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_m_d8",
+ "m_d8_d2"
+};
+
+static const char * const pwm_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d8_d2",
+ "net1_d5_d4",
+ "cb_m_d4",
+ "m_d8_d2",
+ "cb_rtc_32k"
+};
+
+static const char * const i2c_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d5_d4",
+ "cb_m_d4",
+ "net1_d8_d4"
+};
+
+static const char * const pextp_tl_ck_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d5_d4",
+ "cb_m_d4",
+ "cb_rtc_32k"
+};
+
+static const char * const emmc_208m_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_m_d2",
+ "cb_net2_d4",
+ "cb_apll2_196m",
+ "cb_mm_d4",
+ "net1_d8_d2",
+ "cb_mm_d6"
+};
+
+static const char * const emmc_400m_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net2_d2",
+ "cb_mm_d2",
+ "cb_net2_d2"
+};
+
+static const char * const csw_f26m_parents[] __initconst = {
+ "cksq_40m_d2",
+ "m_d8_d2"
+};
+
+static const char * const dramc_md32_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_m_d2",
+ "cb_wedmcu_208m"
+};
+
+static const char * const sysaxi_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d8_d2"
+};
+
+static const char * const sysapb_parents[] __initconst = {
+ "cb_cksq_40m",
+ "m_d3_d2"
+};
+
+static const char * const arm_db_main_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net2_d6"
+};
+
+static const char * const ap2cnn_host_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d8_d4"
+};
+
+static const char * const netsys_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_mm_d2"
+};
+
+static const char * const netsys_500m_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net1_d5"
+};
+
+static const char * const netsys_mcu_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_mm_720m",
+ "cb_net1_d4",
+ "cb_net1_d5",
+ "cb_m_416m"
+};
+
+static const char * const netsys_2x_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net2_800m",
+ "cb_mm_720m"
+};
+
+static const char * const sgm_325m_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_sgm_325m"
+};
+
+static const char * const sgm_reg_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net2_d4"
+};
+
+static const char * const eip97b_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_net1_d5",
+ "cb_m_416m",
+ "cb_mm_d2",
+ "net1_d5_d2"
+};
+
+static const char * const aud_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_apll2_196m"
+};
+
+static const char * const a1sys_parents[] __initconst = {
+ "cb_cksq_40m",
+ "apll2_d4"
+};
+
+static const char * const aud_l_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_apll2_196m",
+ "m_d8_d2"
+};
+
+static const char * const a_tuner_parents[] __initconst = {
+ "cb_cksq_40m",
+ "apll2_d4",
+ "m_d8_d2"
+};
+
+static const char * const u2u3_parents[] __initconst = {
+ "cb_cksq_40m",
+ "m_d8_d2"
+};
+
+static const char * const u2u3_sys_parents[] __initconst = {
+ "cb_cksq_40m",
+ "net1_d5_d4"
+};
+
+static const char * const usb_frmcnt_parents[] __initconst = {
+ "cb_cksq_40m",
+ "cb_mm_d3_d5"
+};
+
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
+ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
+ 0x1C0, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
+ 0x1C0, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
+ 0x1C0, 9),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
+ 0x1C0, 10,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
+ 31, 0x1C0, 11,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
+ 7, 0x1C0, 12,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
+ 0x1C0, 13,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
+ 23, 0x1C0, 14,
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
+ 0x1C0, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
+ 0x1C0, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
+ 0x1C0, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
+ 0x1C0, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
+ 0x1C0, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 0x1C0, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
+ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
+ 7, 0x1C0, 24),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
+ 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
+ 0x1C0, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
+ 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
+ 0x1C0, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
+ 0x1C4, 0),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
+ 0x1C4, 1),
+};
+
+static struct mtk_composite top_aud_divs[] = {
+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
+ 0x0420, 0, 0x0420, 8, 8),
+};
+
+static const struct mtk_clk_desc topck_desc = {
+ .factor_clks = top_divs,
+ .num_factor_clks = ARRAY_SIZE(top_divs),
+ .mux_clks = top_muxes,
+ .num_mux_clks = ARRAY_SIZE(top_muxes),
+ .composite_clks = top_aud_divs,
+ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
+ .clk_lock = &mt7981_clk_lock,
+};
+
+static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
+ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt7981_topckgen_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7981-topckgen",
+ .of_match_table = of_match_clk_mt7981_topckgen,
+ },
+};
+builtin_platform_driver(clk_mt7981_topckgen_drv);

26
6.1/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch Normal file
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@ -0,0 +1,26 @@
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -141,6 +141,13 @@ config PINCTRL_MT7986
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
+config PINCTRL_MT7988
+ bool "Mediatek MT7988 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARCH_MEDIATEK
+ select PINCTRL_MTK_MOORE
+
config PINCTRL_MT8167
bool "Mediatek MT8167 pin control"
depends on OF
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o

24
6.1/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch Normal file
View file

@ -0,0 +1,24 @@
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
+ if (pll->data->pcw_chg_shift)
+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
+ else
+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
writel(val + 1, pll->tuner_addr);
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -42,6 +42,7 @@ struct mtk_pll_data {
u32 pcw_reg;
int pcw_shift;
u32 pcw_chg_reg;
+ int pcw_chg_shift;
const struct mtk_pll_div_table *div_table;
const char *parent_name;
u32 en_reg;

31
6.1/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch Normal file
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@ -0,0 +1,31 @@
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
This driver adds support for clocks for Ethernet and SGMII
required on MediaTek MT7986 SoC.
+config COMMON_CLK_MT7988
+ bool "Clock driver for MediaTek MT7988"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT7988 basic clocks and clocks
+ required for various periperals found on MediaTek.
+
config COMMON_CLK_MT8135
bool "Clock driver for MediaTek MT8135"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o

19
6.1/target/linux/mediatek/patches-6.1/320-mmc-mediatek-add-support-for-MT7986-SoC.patch → 6.1/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch
View file

@ -1,21 +1,24 @@
From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001
From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Sat, 25 Jun 2022 02:10:13 +0800
Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC
Date: Tue, 25 Oct 2022 15:29:53 +0200
Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC
Adding mt7986 own characteristics and of_device_id to have support
of MT7986 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -591,6 +591,19 @@ static const struct mtk_mmc_compatible m
.support_64g = true,
@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m
.support_64g = false,
};
+static const struct mtk_mmc_compatible mt7986_compat = {
@ -31,8 +34,8 @@ Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a
+ .support_64g = true,
+};
+
static const struct mtk_mmc_compatible mt8516_compat = {
.clk_div_bits = 12,
static const struct mtk_mmc_compatible mt8135_compat = {
.clk_div_bits = 8,
.recheck_sdio_irq = true,
@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of
{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},

57
6.1/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch Normal file
View file

@ -0,0 +1,57 @@
From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <mengqi.zhang@mediatek.com>
Date: Sun, 6 Nov 2022 11:39:24 +0800
Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control
Add crypto clock control and ungate it before CQHCI init.
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -452,6 +452,7 @@ struct msdc_host {
struct clk *bus_clk; /* bus clock which used to access register */
struct clk *src_clk_cg; /* msdc source clock control gate */
struct clk *sys_clk_cg; /* msdc subsys clock control gate */
+ struct clk *crypto_clk; /* msdc crypto clock control gate */
struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct
static void msdc_gate_clock(struct msdc_host *host)
{
clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
+ clk_disable_unprepare(host->crypto_clk);
clk_disable_unprepare(host->src_clk_cg);
clk_disable_unprepare(host->src_clk);
clk_disable_unprepare(host->bus_clk);
@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc
clk_prepare_enable(host->bus_clk);
clk_prepare_enable(host->src_clk);
clk_prepare_enable(host->src_clk_cg);
+ clk_prepare_enable(host->crypto_clk);
ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
if (ret) {
dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor
goto host_free;
}
+ /* only eMMC has crypto property */
+ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
+ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
+ if (IS_ERR(host->crypto_clk))
+ host->crypto_clk = NULL;
+ else
+ mmc->caps2 |= MMC_CAP2_CRYPTO;
+ }
+
host->irq = platform_get_irq(pdev, 0);
if (host->irq < 0) {
ret = -EINVAL;

36
6.1/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch Normal file
View file

@ -0,0 +1,36 @@
From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001
From: Yu Zhe <yuzhe@nfschina.com>
Date: Thu, 10 Nov 2022 15:28:19 +0800
Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment
spelling mistake fix : "alreay" -> "already"
"checksume" -> "checksum"
Signed-off-by: Yu Zhe <yuzhe@nfschina.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mtk-sd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct
else
bd[j].bd_info &= ~BDMA_DESC_EOL;
- /* checksume need to clear first */
+ /* checksum need to clear first */
bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
}
@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho
!host->hs400_tuning))
/*
* should not clear fifo/interrupt as the tune data
- * may have alreay come when cmd19/cmd21 gets response
+ * may have already come when cmd19/cmd21 gets response
* CRC error.
*/
msdc_reset_hw(host);

39
6.1/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch Normal file
View file

@ -0,0 +1,39 @@
From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001
From: ChanWoo Lee <cw9316.lee@samsung.com>
Date: Thu, 24 Nov 2022 17:00:31 +0900
Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning()
Replace code with the already defined function. No functional changes.
Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mtk-sd.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho
if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
if (events & MSDC_INT_CMDTMO ||
- (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
- !host->hs400_tuning))
+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
/*
* should not clear fifo/interrupt as the tune data
* may have already come when cmd19/cmd21 gets response
@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho
{
if ((cmd->error &&
!(cmd->error == -EILSEQ &&
- (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
- host->hs400_tuning))) ||
+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
(mrq->sbc && mrq->sbc->error))
msdc_request_done(host, mrq);
else if (cmd == mrq->sbc)

6
6.1/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch
View file

@ -8,7 +8,7 @@
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
{
@@ -1333,6 +1334,7 @@ static int spinand_probe(struct spi_mem
@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
if (ret)
return ret;
@ -16,7 +16,7 @@
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto err_spinand_cleanup;
@@ -1340,6 +1342,7 @@ static int spinand_probe(struct spi_mem
@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
return 0;
err_spinand_cleanup:
@ -24,7 +24,7 @@
spinand_cleanup(spinand);
return ret;
@@ -1358,6 +1361,7 @@ static int spinand_remove(struct spi_mem
@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
if (ret)
return ret;

2
6.1/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -553,6 +553,7 @@
@@ -552,6 +552,7 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
nand-ecc-engine = <&snfi>;

41
6.1/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch Normal file
View file

@ -0,0 +1,41 @@
From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Tue, 28 Feb 2023 19:59:22 +0800
Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
This add cpufreq support for mediatek MT7988 SoC.
The platform data of MT7988 is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform
.ccifreq_supported = false,
};
+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 900000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+ .ccifreq_supported = true,
+};
+
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
.min_volt_shift = 100000,
.max_volt_shift = 200000,
@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },

53
6.1/target/linux/mediatek/patches-6.1/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch Normal file
View file

@ -0,0 +1,53 @@
From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 26 May 2023 10:31:40 +0100
Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623
The MT6380 regulator typically used together with MT7622 does not
support the current maximum processor and SRAM voltage in the cpufreq
driver (1360000uV).
For MT7622 limit processor and SRAM supply voltages to 1350000uV to
avoid having the tracking algorithm request unsupported voltages from
the regulator.
On MT7623 there is no separate SRAM supply and the maximum voltage used
is 1300000uV. Create dedicated platform data for MT7623 to cover that
case as well.
Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623")
Suggested-by: Jia-wei Chang <Jia-wei.Chang@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform
static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
.min_volt_shift = 100000,
.max_volt_shift = 200000,
- .proc_max_volt = 1360000,
+ .proc_max_volt = 1350000,
.sram_min_volt = 0,
- .sram_max_volt = 1360000,
+ .sram_max_volt = 1350000,
+ .ccifreq_supported = false,
+};
+
+static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1300000,
.ccifreq_supported = false,
};
@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },

8
6.1/target/linux/mediatek/patches-6.1/405-mt7986-trng-add-rng-support.patch → 6.1/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch
View file

@ -1,12 +1,14 @@
From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001
From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001
From: "Mingming.Su" <Mingming.Su@mediatek.com>
Date: Wed, 30 Jun 2021 16:59:32 +0800
Subject: [PATCH] mt7986: trng: add rng support
Date: Sat, 8 Oct 2022 18:45:53 +0200
Subject: [PATCH] hwrng: mtk - add mt7986 support
1. Add trng compatible name for MT7986
2. Fix mtk_rng_wait_ready() function
Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
drivers/char/hw_random/mtk-rng.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

10
6.1/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch
View file

@ -1,16 +1,16 @@
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -85,6 +85,7 @@ struct serial8250_config {
#define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:
@@ -86,6 +86,7 @@ struct serial8250_config {
* STOP PARITY EPAR SPAR WLEN5 WLEN6
*/
+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */
#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -286,7 +286,7 @@ static const struct serial8250_config ua
@@ -287,7 +287,7 @@ static const struct serial8250_config ua
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
@ -19,7 +19,7 @@
},
[PORT_NPCM] = {
.name = "Nuvoton 16550",
@@ -2754,6 +2754,11 @@ serial8250_do_set_termios(struct uart_po
@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po
unsigned long flags;
unsigned int baud, quot, frac = 0;

27
6.1/target/linux/mediatek/patches-6.1/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
View file

@ -1,27 +0,0 @@
From: David Bauer <mail@david-bauer.net>
To: linux-mtd@lists.infradead.org
Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV
Date: Sat, 13 Feb 2021 16:10:47 +0100
The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K
sectors as well as block protection and Dual-/Quad-read.
Tested on: Ubiquiti UniFi 6 LR
Signed-off-by: David Bauer <mail@david-bauer.net>
---
drivers/mtd/spi-nor/winbond.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -130,6 +130,9 @@ static const struct flash_info winbond_n
{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ |
SPI_NOR_DUAL_READ) },

130
6.1/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch Normal file
View file

@ -0,0 +1,130 @@
From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:29:51 +0800
Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
data
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
include/linux/platform_data/spi-mt65xx.h | 17 --------------
2 files changed, 11 insertions(+), 35 deletions(-)
delete mode 100644 include/linux/platform_data/spi-mt65xx.h
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -14,7 +14,6 @@
#include <linux/of.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
-#include <linux/platform_data/spi-mt65xx.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
@@ -171,6 +170,8 @@ struct mtk_spi {
struct device *dev;
dma_addr_t tx_dma;
dma_addr_t rx_dma;
+ u32 sample_sel;
+ u32 get_tick_dly;
};
static const struct mtk_spi_compatible mtk_common_compat;
@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
.no_need_unprepare = true,
};
-/*
- * A piece of default chip info unless the platform
- * supplies it.
- */
-static const struct mtk_chip_config mtk_default_chip_info = {
- .sample_sel = 0,
- .tick_delay = 0,
-};
-
static const struct of_device_id mtk_spi_of_match[] = {
{ .compatible = "mediatek,spi-ipm",
.data = (void *)&mtk_ipm_compat,
@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
{
u16 cpha, cpol;
u32 reg_val;
- struct mtk_chip_config *chip_config = spi->controller_data;
struct mtk_spi *mdata = spi_master_get_devdata(master);
cpha = spi->mode & SPI_CPHA ? 1 : 0;
@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
else
reg_val &= ~SPI_CMD_CS_POL;
- if (chip_config->sample_sel)
+ if (mdata->sample_sel)
reg_val |= SPI_CMD_SAMPLE_SEL;
else
reg_val &= ~SPI_CMD_SAMPLE_SEL;
@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
if (mdata->dev_comp->ipm_design) {
reg_val = readl(mdata->base + SPI_CMD_REG);
reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
- reg_val |= ((chip_config->tick_delay & 0x7)
+ reg_val |= ((mdata->get_tick_dly & 0x7)
<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
writel(reg_val, mdata->base + SPI_CMD_REG);
} else {
reg_val = readl(mdata->base + SPI_CFG1_REG);
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
- reg_val |= ((chip_config->tick_delay & 0x7)
+ reg_val |= ((mdata->get_tick_dly & 0x7)
<< SPI_CFG1_GET_TICK_DLY_OFFSET);
writel(reg_val, mdata->base + SPI_CFG1_REG);
}
} else {
reg_val = readl(mdata->base + SPI_CFG1_REG);
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
- reg_val |= ((chip_config->tick_delay & 0x3)
+ reg_val |= ((mdata->get_tick_dly & 0x3)
<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
writel(reg_val, mdata->base + SPI_CFG1_REG);
}
@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
{
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
- if (!spi->controller_data)
- spi->controller_data = (void *)&mtk_default_chip_info;
-
if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
/* CS de-asserted, gpiolib will handle inversion */
gpiod_direction_output(spi->cs_gpiod, 0);
@@ -1138,6 +1126,10 @@ static int mtk_spi_probe(struct platform
mdata = spi_master_get_devdata(master);
mdata->dev_comp = device_get_match_data(dev);
+ /* Set device configs to default first. Calibrate it later. */
+ mdata->sample_sel = 0;
+ mdata->get_tick_dly = 2;
+
if (mdata->dev_comp->enhance_timing)
master->mode_bits |= SPI_CS_HIGH;
--- a/include/linux/platform_data/spi-mt65xx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MTK SPI bus driver definitions
- *
- * Copyright (c) 2015 MediaTek Inc.
- * Author: Leilk Liu <leilk.liu@mediatek.com>
- */
-
-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
-
-/* Board specific platform_data */
-struct mtk_chip_config {
- u32 sample_sel;
- u32 tick_delay;
-};
-#endif

236
6.1/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch Normal file
View file

@ -0,0 +1,236 @@
From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:35:52 +0800
Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++
include/linux/spi/spi.h | 42 ++++++++++++
2 files changed, 179 insertions(+)
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1374,6 +1374,70 @@ static int spi_transfer_wait(struct spi_
return 0;
}
+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
+{
+ int datalen = ctlr->cal_rule->datalen;
+ int addrlen = ctlr->cal_rule->addrlen;
+ u8 *buf;
+ int ret;
+ int i;
+ struct list_head *cal_head, *listptr;
+ struct spi_cal_target *target;
+
+ /* Calculate calibration result */
+ int hit_val, total_hit, origin;
+ bool hit;
+
+ /* Make sure we can start calibration */
+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
+ return 0;
+
+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
+ if(!buf)
+ return -ENOMEM;
+
+ ret = ctlr->append_caldata(ctlr);
+ if (ret)
+ goto cal_end;
+
+ cal_head = ctlr->cal_target;
+ list_for_each(listptr, cal_head) {
+ target = list_entry(listptr, struct spi_cal_target, list);
+
+ hit = false;
+ hit_val = 0;
+ total_hit = 0;
+ origin = *target->cal_item;
+
+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
+ *target->cal_item = i;
+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
+ if(ret)
+ break;
+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
+ hit = true;
+ hit_val += i;
+ total_hit++;
+ dev_dbg(&spi->dev, "golden data matches data read!\n");
+ }
+ }
+ if(hit) {
+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
+ } else {
+ *target->cal_item = origin;
+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
+ }
+ }
+
+cal_end:
+ kfree(buf);
+ return ret? ret: 0;
+}
+EXPORT_SYMBOL_GPL(spi_do_calibration);
+
static void _spi_transfer_delay_ns(u32 ns)
{
if (!ns)
@@ -2208,6 +2272,75 @@ void spi_flush_queue(struct spi_controll
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_OF)
+static inline void alloc_cal_data(struct list_head **cal_target,
+ struct spi_cal_rule **cal_rule, bool enable)
+{
+ if(enable) {
+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
+ INIT_LIST_HEAD(*cal_target);
+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
+ } else {
+ kfree(*cal_target);
+ kfree(*cal_rule);
+ }
+}
+
+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
+ struct device_node *nc)
+{
+ u32 value;
+ int rc;
+ const char *cal_mode;
+
+ rc = of_property_read_bool(nc, "spi-cal-enable");
+ if (rc)
+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
+ else
+ return 0;
+
+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
+ if(!rc) {
+ if(strcmp("read-data", cal_mode) == 0){
+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
+ } else if(strcmp("read-pp", cal_mode) == 0) {
+ ctlr->cal_rule->mode = SPI_CAL_READ_PP;
+ return 0;
+ } else if(strcmp("read-sfdp", cal_mode) == 0){
+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
+ return 0;
+ }
+ } else
+ goto err;
+
+ ctlr->cal_rule->datalen = 0;
+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
+ if(!rc && value > 0) {
+ ctlr->cal_rule->datalen = value;
+
+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
+ rc = of_property_read_u8_array(nc, "spi-cal-data",
+ ctlr->cal_rule->match_data, value);
+ if(rc)
+ kfree(ctlr->cal_rule->match_data);
+ }
+
+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
+ if(!rc && value > 0) {
+ ctlr->cal_rule->addrlen = value;
+
+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
+ rc = of_property_read_u32_array(nc, "spi-cal-addr",
+ ctlr->cal_rule->addr, value);
+ if(rc)
+ kfree(ctlr->cal_rule->addr);
+ }
+ return 0;
+
+err:
+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
+ return 0;
+}
+
static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
struct device_node *nc)
{
@@ -2326,6 +2459,10 @@ of_register_spi_device(struct spi_contro
if (rc)
goto err_out;
+ rc = of_spi_parse_cal_dt(ctlr, spi, nc);
+ if (rc)
+ goto err_out;
+
/* Store a pointer to the node in the device structure */
of_node_get(nc);
spi->dev.of_node = nc;
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -298,6 +298,40 @@ struct spi_driver {
struct device_driver driver;
};
+enum {
+ SPI_CAL_READ_DATA = 0,
+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
+};
+
+struct nand_addr {
+ unsigned int lun;
+ unsigned int plane;
+ unsigned int eraseblock;
+ unsigned int page;
+ unsigned int dataoffs;
+};
+
+/**
+ * Read calibration rule from device dts node.
+ * Once calibration result matches the rule, we regard is as success.
+ */
+struct spi_cal_rule {
+ int datalen;
+ u8 *match_data;
+ int addrlen;
+ u32 *addr;
+ int mode;
+};
+
+struct spi_cal_target {
+ u32 *cal_item;
+ int cal_min; /* min of cal_item */
+ int cal_max; /* max of cal_item */
+ int step; /* Increase/decrease cal_item */
+ struct list_head list;
+};
+
static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
{
return drv ? container_of(drv, struct spi_driver, driver) : NULL;
@@ -682,6 +716,11 @@ struct spi_controller {
void *dummy_rx;
void *dummy_tx;
+ /* For calibration */
+ int (*append_caldata)(struct spi_controller *ctlr);
+ struct list_head *cal_target;
+ struct spi_cal_rule *cal_rule;
+
int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
/*
@@ -1489,6 +1528,9 @@ spi_register_board_info(struct spi_board
{ return 0; }
#endif
+extern int spi_do_calibration(struct spi_controller *ctlr,
+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
+
/* If you're hotplugging an adapter with devices (parport, usb, etc)
* use spi_new_device() to describe each device. You can also call
* spi_unregister_device() to start making that device vanish, but

41
6.1/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch Normal file
View file

@ -0,0 +1,41 @@
From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:37:55 +0800
Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/spi/spi-mem.c | 8 ++++++++
include/linux/spi/spi-mem.h | 4 ++++
2 files changed, 12 insertions(+)
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
}
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
+int spi_mem_do_calibration(struct spi_mem *mem,
+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
+ void *priv)
+{
+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
+}
+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
+
/**
* spi_mem_get_name() - Return the SPI mem device name to be used by the
* upper layer if necessary
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
int spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op);
+int spi_mem_do_calibration(struct spi_mem *mem,
+ int (*cal_read)(void *, u32 *, int, u8 *, int),
+ void *priv);
+
const char *spi_mem_get_name(struct spi_mem *mem);
struct spi_mem_dirmap_desc *

43
6.1/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch Normal file
View file

@ -0,0 +1,43 @@
From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:39:03 +0800
Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
paramter
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -832,6 +832,21 @@ static irqreturn_t mtk_spi_interrupt(int
return IRQ_HANDLED;
}
+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
+{
+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
+
+ cal_target->cal_item = &mdata->get_tick_dly;
+ cal_target->cal_min = 0;
+ cal_target->cal_max = 7;
+ cal_target->step = 1;
+
+ list_add(&cal_target->list, ctlr->cal_target);
+
+ return 0;
+}
+
static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
struct spi_mem_op *op)
{
@@ -1122,6 +1137,7 @@ static int mtk_spi_probe(struct platform
master->setup = mtk_spi_setup;
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
master->use_gpio_descriptors = true;
+ master->append_caldata = mtk_spi_append_caldata;
mdata = spi_master_get_devdata(master);
mdata->dev_comp = device_get_match_data(dev);

81
6.1/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch Normal file
View file

@ -0,0 +1,81 @@
From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:39:56 +0800
Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
spinand
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st
return -ENOTSUPP;
}
+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
+ struct spinand_device *spinand = (struct spinand_device *)priv;
+ struct device *dev = &spinand->spimem->spi->dev;
+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
+ struct nand_pos pos;
+ struct nand_page_io_req req;
+ u8 status;
+ int ret;
+
+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
+ return -EINVAL;
+ }
+
+ ret = spinand_reset_op(spinand);
+ if (ret)
+ return ret;
+
+ /* We should store our golden data in first target because
+ * we can't switch target at this moment.
+ */
+ pos = (struct nand_pos){
+ .target = 0,
+ .lun = *addr,
+ .plane = *(addr+1),
+ .eraseblock = *(addr+2),
+ .page = *(addr+3),
+ };
+
+ req = (struct nand_page_io_req){
+ .pos = pos,
+ .dataoffs = *(addr+4),
+ .datalen = readlen,
+ .databuf.in = buf,
+ .mode = MTD_OPS_AUTO_OOB,
+ };
+
+ ret = spinand_load_page_op(spinand, &req);
+ if (ret)
+ return ret;
+
+ ret = spinand_wait(spinand, &status);
+ if (ret < 0)
+ return ret;
+
+ ret = spi_mem_exec_op(spinand->spimem, &op);
+
+ return 0;
+}
+
static int spinand_id_detect(struct spinand_device *spinand)
{
u8 *id = spinand->id.data;
@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d
if (!spinand->scratchbuf)
return -ENOMEM;
+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
+ if (ret)
+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
+
ret = spinand_detect(spinand);
if (ret)
goto err_free_bufs;

57
6.1/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch Normal file
View file

@ -0,0 +1,57 @@
From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 23 Jun 2022 18:40:59 +0800
Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
spi-nor
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/mtd/nand/spi/core.c | 5 ++++-
drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad
if (ret)
return ret;
- ret = spinand_wait(spinand, &status);
+ ret = spinand_wait(spinand,
+ SPINAND_READ_INITIAL_DELAY_US,
+ SPINAND_READ_POLL_DELAY_US,
+ &status);
if (ret < 0)
return ret;
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2899,6 +2899,18 @@ static const struct flash_info *spi_nor_
return NULL;
}
+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
+{
+ struct spi_nor *nor = (struct spi_nor *)priv;
+
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+ nor->read_proto = SNOR_PROTO_1_1_1;
+ nor->read_opcode = SPINOR_OP_READ;
+ nor->read_dummy = 0;
+
+ return nor->controller_ops->read(nor, *addr, readlen, buf);
+}
+
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
const char *name)
{
@@ -3002,6 +3014,9 @@ int spi_nor_scan(struct spi_nor *nor, co
if (!nor->bouncebuf)
return -ENOMEM;
+ if(nor->spimem)
+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
+
info = spi_nor_get_flash_info(nor, name);
if (IS_ERR(info))
return PTR_ERR(info);

4
6.1/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
View file

@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -366,6 +366,12 @@ config ROCKCHIP_PHY
@@ -382,6 +382,12 @@ config ROCKCHIP_PHY
help
Currently supports the integrated Ethernet PHY.
@ -15,7 +15,7 @@
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o

2
6.1/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
View file

@ -20,7 +20,7 @@ Acked-by: Pali Rohár <pali@kernel.org>
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
*/
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
msleep(100);
+ /*
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and

4
6.1/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -848,6 +848,12 @@
@@ -849,6 +849,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};
@ -13,7 +13,7 @@
};
pcie1: pcie@1a145000 {
@@ -886,6 +892,12 @@
@@ -887,6 +893,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};

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