From 4ade942da43042278a6533930aa5099aea4f6804 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Mon, 28 Dec 2020 13:59:56 +0800 Subject: [PATCH] Update 999-ipq40xx-unlock-cpu-frequency.patch --- .../999-ipq40xx-unlock-cpu-frequency.patch | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/root/target/linux/ipq40xx/patches-5.4/999-ipq40xx-unlock-cpu-frequency.patch b/root/target/linux/ipq40xx/patches-5.4/999-ipq40xx-unlock-cpu-frequency.patch index dd654f88..c08658bb 100644 --- a/root/target/linux/ipq40xx/patches-5.4/999-ipq40xx-unlock-cpu-frequency.patch +++ b/root/target/linux/ipq40xx/patches-5.4/999-ipq40xx-unlock-cpu-frequency.patch @@ -1,6 +1,6 @@ From: William Subject: [PATCH] ipq40xx: improve CPU clock -Date: Tue, 15 Dec 2020 15:28:10 +0800 +Date: Tue, 15 Dec 2020 15:26:35 +0800 This patch will match the clock-latency-ns values in the device tree for those found inside the OEM device tree and kernel source code and @@ -10,42 +10,38 @@ Signed-off-by: William --- --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -121,23 +121,28 @@ +@@ -114,20 +114,24 @@ + opp-48000000 { opp-hz = /bits/ 64 <48000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <256000>; + clock-latency-ns = <100000>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <256000>; + clock-latency-ns = <100000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <256000>; + clock-latency-ns = <100000>; }; opp-716000000 { opp-hz = /bits/ 64 <716000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <256000>; + clock-latency-ns = <100000>; }; + opp-896000000 { + opp-hz = /bits/ 64 <896000000>; -+ opp-microvolt = <1100000>; + clock-latency-ns = <100000>; + }; }; - pmu { + memory { --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -587,6 +587,9 @@ static const struct freq_tbl ftbl_gcc_ap +@@ -579,6 +579,9 @@ static const struct freq_tbl ftbl_gcc_ap F(632000000, P_DDRPLLAPSS, 1, 0, 0), F(672000000, P_DDRPLLAPSS, 1, 0, 0), F(716000000, P_DDRPLLAPSS, 1, 0, 0),