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Update kernel and OpenWrt

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This commit is contained in:
Ycarus (Yannick Chabanois) 2022-03-18 13:37:57 +01:00
parent 32af00ff63
commit 4db21fc111
35 changed files with 4925 additions and 491 deletions
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16
build.sh
View file

@ -98,9 +98,9 @@ if [ "$OMR_OPENWRT" = "default" ]; then
_get_repo feeds/packages https://github.com/openwrt/packages "793e7ee484ae4ec37b1cd920b4032dde3cae69cc"
_get_repo feeds/luci https://github.com/openwrt/luci "701ea947fc920e63d14d8efb8287097fd63442ca"
else
_get_repo "$OMR_TARGET/source" https://github.com/openwrt/openwrt "02de391b086dd2b7a72c2394cfb66cec666a51c1"
_get_repo feeds/packages https://github.com/openwrt/packages "7b2dd3e9efbc20ef4e7f47f60c3db9aaef37c0a5"
_get_repo feeds/luci https://github.com/openwrt/luci "73e21c3b5791ac97aa7b437c8e683cdbea407395"
_get_repo "$OMR_TARGET/source" https://github.com/openwrt/openwrt "83ca16fc4350c65110caeb7143afc9e9cd300d23"
_get_repo feeds/packages https://github.com/openwrt/packages "9aba2936e29ace28411e82e1ce1fb4432bcfda2c"
_get_repo feeds/luci https://github.com/openwrt/luci "f27fe280aa7a1d39de7144298541bfac8bb59f7f"
fi
elif [ "$OMR_OPENWRT" = "master" ]; then
_get_repo "$OMR_TARGET/source" https://github.com/openwrt/openwrt "master"
@ -558,9 +558,12 @@ if [ "$OMR_KERNEL" = "5.14" ]; then
echo "Set to kernel 5.14 for ramips"
find target/linux/ramips -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.4%KERNEL_PATCHVER:=5.14%g' {} \;
echo "Done"
echo "Set to kernel 5.14 for ramips"
echo "Set to kernel 5.14 for ipq806x"
find target/linux/ipq806x -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.10%KERNEL_PATCHVER:=5.14%g' {} \;
echo "Done"
echo "Set to kernel 5.14 for ipq40xx"
find target/linux/ipq40xx -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.10%KERNEL_PATCHVER:=5.14%g' {} \;
echo "Done"
#rm -rf target/linux/generic/files/drivers/net/phy/b53
rm -f target/linux/bcm27xx/modules/sound.mk
echo "CONFIG_DEVEL=y" >> ".config"
@ -597,9 +600,12 @@ if [ "$OMR_KERNEL" = "5.15" ]; then
echo "Set to kernel 5.15 for ramips"
find target/linux/ramips -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.4%KERNEL_PATCHVER:=5.15%g' {} \;
echo "Done"
echo "Set to kernel 5.15 for ramips"
echo "Set to kernel 5.15 for ipq806x"
find target/linux/ipq806x -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.10%KERNEL_PATCHVER:=5.15%g' {} \;
echo "Done"
echo "Set to kernel 5.15 for ipq40xx"
find target/linux/ipq40xx -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.10%KERNEL_PATCHVER:=5.15%g' {} \;
echo "Done"
#rm -rf target/linux/generic/files/drivers/net/phy/b53
rm -f target/linux/bcm27xx/modules/sound.mk
echo "CONFIG_DEVEL=y" >> ".config"

3
root/include/kernel-version.mk
View file

@ -9,7 +9,7 @@ endif
LINUX_VERSION-5.4 = .182
LINUX_VERSION-5.10 = .64
LINUX_VERSION-5.14 = .6
LINUX_VERSION-5.15 = .17
LINUX_VERSION-5.15 = .29
LINUX_KERNEL_HASH-5.4.132 = 8466adbfb3579e751ede683496df7bb20f258b5f882250f3dd82be63736d00ef
LINUX_KERNEL_HASH-5.4.182 = b2f1201f64f010e9e3c85d6f303a559a7944a80a0244a86b8f5035bd23f1f40d
@ -18,6 +18,7 @@ LINUX_KERNEL_HASH-5.14.6 = 54848c1268771ee3515e4c33e29abc3f1fa90d8144894cce6d0eb
LINUX_KERNEL_HASH-5.15.4 = 549d0fb75e65f6158e6f4becc648f249d386843da0e1211460bde8b1ea99cbca
LINUX_KERNEL_HASH-5.15.15 = 1d3c57cf8071af174933df3e5d77da801e240a59da3c5e8406f7769de2c83a5a
LINUX_KERNEL_HASH-5.15.17 = 2787f5c0cc59984902fd97916dc604f39718c73817497c25f963141bfb70abde
LINUX_KERNEL_HASH-5.15.29 = 5905e684602c47ae95746d4003cb834335e5451aca4ac7c3013f15dd49ed876e
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

120
root/target/linux/generic/hack-5.15/220-gc_sections.patch
View file

@ -1,120 +0,0 @@
From e3d8676f5722b7622685581e06e8f53e6138e3ab Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Sat, 15 Jul 2017 23:42:36 +0200
Subject: use -ffunction-sections, -fdata-sections and --gc-sections
In combination with kernel symbol export stripping this significantly reduces
the kernel image size. Used on both ARM and MIPS architectures.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -117,6 +117,7 @@ config ARM
select HAVE_UID16
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select IRQ_FORCED_THREADING
+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
select MODULES_USE_ELF_REL
select NEED_DMA_MAP_STATE
select OF_EARLY_FLATTREE if OF
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -92,6 +92,7 @@ endif
ifeq ($(CONFIG_USE_OF),y)
OBJS += $(libfdt_objs) fdt_check_mem_start.o
endif
+KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL))
# -fstack-protector-strong triggers protection checks in this code,
# but it is being used too early to link to meaningful stack_chk logic.
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -100,24 +100,24 @@ SECTIONS
}
.init.arch.info : {
__arch_info_begin = .;
- *(.arch.info.init)
+ KEEP(*(.arch.info.init))
__arch_info_end = .;
}
.init.tagtable : {
__tagtable_begin = .;
- *(.taglist.init)
+ KEEP(*(.taglist.init))
__tagtable_end = .;
}
#ifdef CONFIG_SMP_ON_UP
.init.smpalt : {
__smpalt_begin = .;
- *(.alt.smp.init)
+ KEEP(*(.alt.smp.init))
__smpalt_end = .;
}
#endif
.init.pv_table : {
__pv_table_begin = .;
- *(.pv_table)
+ KEEP(*(.pv_table))
__pv_table_end = .;
}
--- a/arch/arm/include/asm/vmlinux.lds.h
+++ b/arch/arm/include/asm/vmlinux.lds.h
@@ -23,19 +23,19 @@
#define ARM_MMU_DISCARD(x)
#else
#define ARM_MMU_KEEP(x)
-#define ARM_MMU_DISCARD(x) x
+#define ARM_MMU_DISCARD(x) KEEP(x)
#endif
#define PROC_INFO \
. = ALIGN(4); \
__proc_info_begin = .; \
- *(.proc.info.init) \
+ KEEP(*(.proc.info.init)) \
__proc_info_end = .;
#define IDMAP_TEXT \
ALIGN_FUNCTION(); \
__idmap_text_start = .; \
- *(.idmap.text) \
+ KEEP(*(.idmap.text)) \
__idmap_text_end = .; \
#define ARM_DISCARD \
@@ -96,12 +96,12 @@
. = ALIGN(8); \
.ARM.unwind_idx : { \
__start_unwind_idx = .; \
- *(.ARM.exidx*) \
+ KEEP(*(.ARM.exidx*)) \
__stop_unwind_idx = .; \
} \
.ARM.unwind_tab : { \
__start_unwind_tab = .; \
- *(.ARM.extab*) \
+ KEEP(*(.ARM.extab*)) \
__stop_unwind_tab = .; \
}
@@ -112,14 +112,14 @@
#define ARM_VECTORS \
__vectors_start = .; \
.vectors 0xffff0000 : AT(__vectors_start) { \
- *(.vectors) \
+ KEEP(*(.vectors)) \
} \
. = __vectors_start + SIZEOF(.vectors); \
__vectors_end = .; \
\
__stubs_start = .; \
.stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) { \
- *(.stubs) \
+ KEEP(*(.stubs)) \
} \
. = __stubs_start + SIZEOF(.stubs); \
__stubs_end = .; \

52
root/target/linux/generic/hack-5.15/780-net-ipheth-fix-RX-EOVERFLOW.patch
View file

@ -1,52 +0,0 @@
From dd109ded2b526636fff438d33433ab64ffd21583 Mon Sep 17 00:00:00 2001
From: Georgi Valkov <gvalkov@abv.bg>
Date: Fri, 16 Apr 2021 20:44:36 +0300
Subject: [PATCH] ipheth: fix EOVERFLOW in ipheth_rcvbulk_callback
When rx_buf is allocated we need to account for IPHETH_IP_ALIGN,
which reduces the usable size by 2 bytes. Otherwise we have 1512
bytes usable instead of 1514, and if we receive more than 1512
bytes, ipheth_rcvbulk_callback is called with status -EOVERFLOW,
after which the driver malfunctiones and all communication stops.
Fixes: ipheth 2-1:4.2: ipheth_rcvbulk_callback: urb status: -75
Signed-off-by: Georgi Valkov <gvalkov@abv.bg>
---
drivers/net/usb/ipheth.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c
index 207e59e74935..06d9f19ca142 100644
--- a/drivers/net/usb/ipheth.c
+++ b/drivers/net/usb/ipheth.c
@@ -121,7 +121,7 @@ static int ipheth_alloc_urbs(struct ipheth_device *iphone)
if (tx_buf == NULL)
goto free_rx_urb;
- rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE,
+ rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
GFP_KERNEL, &rx_urb->transfer_dma);
if (rx_buf == NULL)
goto free_tx_buf;
@@ -146,7 +146,7 @@ static int ipheth_alloc_urbs(struct ipheth_device *iphone)
static void ipheth_free_urbs(struct ipheth_device *iphone)
{
- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->rx_buf,
+ usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN, iphone->rx_buf,
iphone->rx_urb->transfer_dma);
usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf,
iphone->tx_urb->transfer_dma);
@@ -317,7 +317,7 @@ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags)
usb_fill_bulk_urb(dev->rx_urb, udev,
usb_rcvbulkpipe(udev, dev->bulk_in),
- dev->rx_buf, IPHETH_BUF_SIZE,
+ dev->rx_buf, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
ipheth_rcvbulk_callback,
dev);
dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
--
2.31.1

4
root/target/linux/generic/pending-5.15/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch
View file

@ -262,7 +262,7 @@ Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
#ifdef CONFIG_SMP
/*
@@ -181,9 +183,15 @@ kexec_indirection_page:
PTR 0
PTR_WD 0
.size kexec_indirection_page, PTRSIZE
-relocate_new_kernel_end:
@ -278,7 +278,7 @@ Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
-relocate_new_kernel_size:
- EXPORT(relocate_new_kernel_size)
- PTR relocate_new_kernel_end - relocate_new_kernel
- PTR_WD relocate_new_kernel_end - relocate_new_kernel
- .size relocate_new_kernel_size, PTRSIZE
+kexec_relocate_new_kernel_end:
+ EXPORT(kexec_relocate_new_kernel_end)

102
root/target/linux/generic/pending-5.15/681-NET-add-mtd-mac-address-support-to-of_get_mac_addres.patch
View file

@ -1,102 +0,0 @@
From 6f8e5369ae054ec6c9265581d5a7e39738a5cd84 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 30 Mar 2021 13:16:38 +0200
Subject: [PATCH 1/2] NET: add mtd-mac-address support to of_get_mac_address()
Many embedded devices have information such as mac addresses stored inside mtd
devices. This patch allows us to add a property inside a node describing a
network interface. The new property points at a mtd partition with an offset
where the mac address can be found.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/of/of_net.c | 75 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 74 insertions(+), 1 deletion(-)
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -12,6 +12,7 @@
#include <linux/export.h>
#include <linux/device.h>
#include <linux/nvmem-consumer.h>
+#include <linux/mtd/mtd.h>
/**
* of_get_phy_mode - Get phy mode for given device_node
@@ -95,6 +96,52 @@ static int of_get_mac_addr_nvmem(struct
return 0;
}
+static int of_get_mac_address_mtd(struct device_node *np, u8 *addr)
+{
+#ifdef CONFIG_MTD
+ struct platform_device *pdev = of_find_device_by_node(np);
+ struct device_node *mtd_np = NULL;
+ size_t retlen;
+ int size, ret;
+ struct mtd_info *mtd;
+ const char *part;
+ const __be32 *list;
+ phandle phandle;
+ u8 mac[ETH_ALEN];
+
+ list = of_get_property(np, "mtd-mac-address", &size);
+ if (!list || (size != (2 * sizeof(*list))))
+ return -ENODEV;
+
+ phandle = be32_to_cpup(list++);
+ if (phandle)
+ mtd_np = of_find_node_by_phandle(phandle);
+
+ if (!mtd_np)
+ return -ENODEV;
+
+ part = of_get_property(mtd_np, "label", NULL);
+ if (!part)
+ part = mtd_np->name;
+
+ mtd = get_mtd_device_nm(part);
+ if (IS_ERR(mtd))
+ return -ENODEV;
+
+ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, mac);
+ put_mtd_device(mtd);
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ memcpy(addr, mac, ETH_ALEN);
+
+ return 0;
+#endif
+ return -EINVAL;
+}
+
+
/**
* of_get_mac_address()
* @np: Caller's Device Node
@@ -119,6 +166,10 @@ static int of_get_mac_addr_nvmem(struct
* this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
* but is all zeros.
*
+ *
+ * If a mtd-mac-address property exists, try to fetch the MAC address from the
+ * specified mtd device.
+ *
* Return: 0 on success and errno in case of error.
*/
int of_get_mac_address(struct device_node *np, u8 *addr)
@@ -140,6 +191,10 @@ int of_get_mac_address(struct device_nod
if (!ret)
return 0;
+ ret = of_get_mac_address_mtd(np, addr);
+ if (!ret)
+ return 0;
+
return of_get_mac_addr_nvmem(np, addr);
}
EXPORT_SYMBOL(of_get_mac_address);

84
root/target/linux/generic/pending-5.15/682-of_net-add-mac-address-increment-support.patch
View file

@ -1,84 +0,0 @@
From 639dba857aa554f2a78572adc4cf3c32de9ec2e2 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 30 Mar 2021 18:21:14 +0200
Subject: [PATCH 2/2] of_net: add mac-address-increment support
Lots of embedded devices use the mac-address of other interface
extracted from nvmem cells and increments it by one or two. Add two
bindings to integrate this and directly use the right mac-address for
the interface. Some example are some routers that use the gmac
mac-address stored in the art partition and increments it by one for the
wifi. mac-address-increment-byte bindings is used to tell what byte of
the mac-address has to be increased (if not defined the last byte is
increased) and mac-address-increment tells how much the byte decided
early has to be increased.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/of/of_net.c | 59 ++++++++++++++++++++++++++++++++++-----------
1 file changed, 45 insertions(+), 14 deletions(-)
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -170,31 +170,56 @@ static int of_get_mac_address_mtd(struct
* If a mtd-mac-address property exists, try to fetch the MAC address from the
* specified mtd device.
*
+ * DT can tell the system to increment the mac-address after is extracted by
+ * using:
+ * - mac-address-increment-byte to decide what byte to increase
+ * (if not defined is increased the last byte)
+ * - mac-address-increment to decide how much to increase. The value will
+ * not overflow to other bytes if the increment is over 255.
+ * (example 00:01:02:03:04:ff + 1 == 00:01:02:03:04:00)
+ *
* Return: 0 on success and errno in case of error.
*/
int of_get_mac_address(struct device_node *np, u8 *addr)
{
+ u32 inc_idx, mac_inc;
int ret;
+ /* Check first if the increment byte is present and valid.
+ * If not set assume to increment the last byte if found.
+ */
+ if (of_property_read_u32(np, "mac-address-increment-byte", &inc_idx))
+ inc_idx = 5;
+ if (inc_idx < 3 || inc_idx > 5)
+ return -EINVAL;
+
if (!np)
return -ENODEV;
ret = of_get_mac_addr(np, "mac-address", addr);
if (!ret)
- return 0;
+ goto found;
ret = of_get_mac_addr(np, "local-mac-address", addr);
if (!ret)
- return 0;
+ goto found;
ret = of_get_mac_addr(np, "address", addr);
if (!ret)
- return 0;
+ goto found;
ret = of_get_mac_address_mtd(np, addr);
if (!ret)
- return 0;
+ goto found;
+
+ ret = of_get_mac_addr_nvmem(np, addr);
+ if (ret)
+ return ret;
+
+found:
+ if (!of_property_read_u32(np, "mac-address-increment", &mac_inc))
+ addr[inc_idx] += mac_inc;
- return of_get_mac_addr_nvmem(np, addr);
+ return ret;
}
EXPORT_SYMBOL(of_get_mac_address);

37
root/target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch
View file

@ -1,37 +0,0 @@
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -141,6 +141,26 @@ static int of_get_mac_address_mtd(struct
return -EINVAL;
}
+static int of_add_mac_address(struct device_node *np, u8* addr)
+{
+ struct property *prop;
+
+ prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+ if (!prop)
+ return -ENOMEM;
+
+ prop->name = "mac-address";
+ prop->length = ETH_ALEN;
+ prop->value = kmemdup(addr, ETH_ALEN, GFP_KERNEL);
+ if (!prop->value || of_update_property(np, prop))
+ goto free;
+
+ return 0;
+free:
+ kfree(prop->value);
+ kfree(prop);
+ return -ENOMEM;
+}
/**
* of_get_mac_address()
@@ -220,6 +240,7 @@ found:
if (!of_property_read_u32(np, "mac-address-increment", &mac_inc))
addr[inc_idx] += mac_inc;
+ of_add_mac_address(np, addr);
return ret;
}
EXPORT_SYMBOL(of_get_mac_address);

495
root/target/linux/ipq40xx/config-5.15 Normal file
View file

@ -0,0 +1,495 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_ESSEDMA=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

1890
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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

14
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac-128m.dts
View file

@ -5,14 +5,14 @@
/ {
model = "P&W R619AC 128M";
compatible = "p2w,r619ac-128m";
chosen {
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
};
};
&rootfs_part1 {
&nand_rootfs {
/*
* Watch out: stock MIBIB is set up for a 64MiB chip.
* If a 128MiB flash chip is used, make sure to have
* the right values in MIBIB or the device might not
* boot.
*/
reg = <0x0 0x8000000>;
};
/delete-node/ &rootfs_part2;

12
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac-64m.dts Normal file
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-r619ac.dtsi"
/ {
model = "P&W R619AC 64M";
compatible = "p2w,r619ac-64m";
};
&nand_rootfs {
reg = <0x0 0x4000000>;
};

12
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dts
View file

@ -1,12 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-r619ac.dtsi"
/ {
model = "P&W R619AC";
compatible = "p2w,r619ac";
chosen {
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
};
};

156
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
View file

@ -4,8 +4,13 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
#include <dt-bindings/leds/common.h>
/ {
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
@ -80,24 +85,30 @@
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_sys: sys {
label = "r619ac:blue:sys";
led_sys: led-0 {
label = "blue:sys";
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
};
wlan2g {
label = "r619ac:blue:wlan2g";
led-1 {
label = "blue:wlan2g";
gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <0>;
};
wlan5g {
label = "r619ac:blue:wlan5g";
led-2 {
label = "blue:wlan5g";
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <1>;
};
};
@ -171,21 +182,38 @@
read-only;
};
partition@1 {
label = "Bootloader";
reg = <0x0 0x170000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
partition@180000 {
label = "unused";
reg = <0x180000 0xe80000>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
nand_rootfs: partition@0 {
label = "ubi";
/* reg defined in 64M/128M variant dts. */
};
};
};
@ -201,25 +229,19 @@
status = "okay";
};
&nand {
&pcie0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
rootfs_part1: partition@0 {
label = "rootfs";
reg = <0x0 0x4000000>;
};
rootfs_part2: partition@4000000 {
label = "unused1";
reg = <0x4000000 0x4000000>;
};
};
/* Free slot for use */
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
@ -235,6 +257,15 @@
};
&tlmm {
pcie_pins: pcie_pinmux {
mux {
pins = "gpio2";
function = "gpio";
output-low;
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
@ -270,29 +301,36 @@
bias-disable;
};
};
};
led_pins: led_pinmux {
mux {
pins = "gpio32", "gpio39", "gpio50";
function = "gpio";
bias-pull-up;
output-low;
};
&ethphy0 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
mux_1 {
pins = "gpio52";
function = "gpio";
bias-pull-up;
output-high;
};
&ethphy1 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
mux_2 {
pins = "gpio61";
function = "gpio";
bias-pull-down;
output-high;
};
};
&ethphy2 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy3 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy4 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&usb3_ss_phy {
@ -313,10 +351,14 @@
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "R619AC";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_1000>;
qcom,ath10k-calibration-variant = "P&W R619AC";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "R619AC";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_5000>;
qcom,ath10k-calibration-variant = "P&W R619AC";
};

400
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts Normal file
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@ -0,0 +1,400 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Compex WPJ419";
compatible = "compex,wpj419", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
reserved-memory {
ranges;
rsvd1@87000000 {
/* Reserved for other subsystem */
reg = <0x87000000 0x500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
/* Reserved for other subsystem */
reg = <0x87B00000 0x500000>;
no-map;
};
};
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
soc {
pinctrl@1000000 {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
led_0_pins: led0_pinmux {
mux_1 {
pins = "gpio36";
function = "led0";
bias-pull-down;
};
mux_2 {
pins = "gpio40";
function = "led4";
bias-pull-down;
};
};
};
blsp_dma: dma@7884000 {
status = "okay";
};
spi_0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
num-cs = <2>;
flash0@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x040000 0x020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x060000 0x060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x0c0000 0x010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x0d0000 0x010000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0x0e0000 0x010000>;
};
partition@f0000 {
label = "u-boot";
reg = <0x0f0000 0x080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
};
nand@1 {
reg = <1>;
status = "okay";
compatible = "spi-nand";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* The device has 128MB, but we can only address
* 64MB because of the bootloader's default settings.
* This is due to the old mt29f driver,
* which detected the deivce with only 64MB
*/
partition@0 {
label = "ubi";
reg = <0x0000000 0x4000000>;
};
};
};
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
usb3_ss_phy: ssphy@9a000 {
status = "okay";
};
usb3_hs_phy: hsphy@a6000 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
usb2_hs_phy: hsphy@a8000 {
status = "okay";
};
usb2: usb2@60f8800 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x1e>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
qpic_bam: dma@7984000 {
status = "okay";
};
pcie0: pci@40000000 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
nand: nand-controller@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_1000>;
};
&wifi1 {
status = "okay";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_5000>;
};

350
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/*
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/string.h>
#include <linux/version.h>
#include "edma.h"
struct edma_ethtool_stats {
uint8_t stat_string[ETH_GSTRING_LEN];
uint32_t stat_offset;
};
#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
#define DRVINFO_LEN 32
/* Array of strings describing statistics
*/
static const struct edma_ethtool_stats edma_gstrings_stats[] = {
{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
{"tx_desc_error", EDMA_STAT(tx_desc_error)},
{"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
};
#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
/* edma_get_strset_count()
* Get strset count
*/
static int edma_get_strset_count(struct net_device *netdev,
int sset)
{
switch (sset) {
case ETH_SS_STATS:
return EDMA_STATS_LEN;
default:
netdev_dbg(netdev, "%s: Invalid string set", __func__);
return -EOPNOTSUPP;
}
}
/* edma_get_strings()
* get stats string
*/
static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
uint8_t *data)
{
uint8_t *p = data;
uint32_t i;
switch (stringset) {
case ETH_SS_STATS:
for (i = 0; i < EDMA_STATS_LEN; i++) {
memcpy(p, edma_gstrings_stats[i].stat_string,
min((size_t)ETH_GSTRING_LEN,
strlen(edma_gstrings_stats[i].stat_string)
+ 1));
p += ETH_GSTRING_LEN;
}
break;
}
}
/* edma_get_ethtool_stats()
* Get ethtool statistics
*/
static void edma_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *stats, uint64_t *data)
{
struct edma_adapter *adapter = netdev_priv(netdev);
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
int i;
uint8_t *p = NULL;
edma_read_append_stats(edma_cinfo);
for(i = 0; i < EDMA_STATS_LEN; i++) {
p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
edma_gstrings_stats[i].stat_offset;
data[i] = *(uint32_t *)p;
}
}
/* edma_get_drvinfo()
* get edma driver info
*/
static void edma_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
}
/* edma_nway_reset()
* Reset the phy, if available.
*/
static int edma_nway_reset(struct net_device *netdev)
{
return -EINVAL;
}
/* edma_get_wol()
* get wake on lan info
*/
static void edma_get_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
wol->supported = 0;
wol->wolopts = 0;
}
/* edma_get_msglevel()
* get message level.
*/
static uint32_t edma_get_msglevel(struct net_device *netdev)
{
return 0;
}
/* edma_get_settings()
* Get edma settings
*/
static int edma_get_settings(struct net_device *netdev,
struct ethtool_link_ksettings *cmd)
{
struct edma_adapter *adapter = netdev_priv(netdev);
if (adapter->poll_required) {
if ((adapter->forced_speed != SPEED_UNKNOWN)
&& !(adapter->poll_required))
return -EPERM;
phy_ethtool_ksettings_get(adapter->phydev, cmd);
if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, adapter->phydev->advertising))
cmd->base.port = PORT_FIBRE;
else
cmd->base.port = PORT_TP;
} else {
/* If the speed/duplex for this GMAC is forced and we
* are not polling for link state changes, return the
* values as specified by platform. This will be true
* for GMACs connected to switch, and interfaces that
* do not use a PHY.
*/
if (!(adapter->poll_required)) {
if (adapter->forced_speed != SPEED_UNKNOWN) {
/* set speed and duplex */
cmd->base.speed = SPEED_1000;
cmd->base.duplex = DUPLEX_FULL;
/* Populate capabilities advertised by self */
linkmode_zero(cmd->link_modes.advertising);
cmd->base.autoneg = 0;
cmd->base.port = PORT_TP;
cmd->base.transceiver = XCVR_EXTERNAL;
} else {
/* non link polled and non
* forced speed/duplex interface
*/
return -EIO;
}
}
}
return 0;
}
/* edma_set_settings()
* Set EDMA settings
*/
static int edma_set_settings(struct net_device *netdev,
const struct ethtool_link_ksettings *cmd)
{
struct edma_adapter *adapter = netdev_priv(netdev);
if ((adapter->forced_speed != SPEED_UNKNOWN) &&
!adapter->poll_required)
return -EPERM;
return phy_ethtool_ksettings_set(adapter->phydev, cmd);
}
/* edma_get_coalesce
* get interrupt mitigation
*/
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
static int edma_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec,
struct kernel_ethtool_coalesce *kernel_coal,
struct netlink_ext_ack *extack)
#else
static int edma_get_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ec)
#endif
{
u32 reg_val;
edma_get_tx_rx_coalesce(&reg_val);
/* We read the Interrupt Moderation Timer(IMT) register value,
* use lower 16 bit for rx and higher 16 bit for Tx. We do a
* left shift by 1, because IMT resolution timer is 2usecs.
* Hence the value given by the register is multiplied by 2 to
* get the actual time in usecs.
*/
ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
return 0;
}
/* edma_set_coalesce
* set interrupt mitigation
*/
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
static int edma_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec,
struct kernel_ethtool_coalesce *kernel_coal,
struct netlink_ext_ack *extack)
#else
static int edma_set_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ec)
#endif
{
if (ec->tx_coalesce_usecs)
edma_change_tx_coalesce(ec->tx_coalesce_usecs);
if (ec->rx_coalesce_usecs)
edma_change_rx_coalesce(ec->rx_coalesce_usecs);
return 0;
}
/* edma_set_priv_flags()
* Set EDMA private flags
*/
static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
{
return 0;
}
/* edma_get_priv_flags()
* get edma driver flags
*/
static u32 edma_get_priv_flags(struct net_device *netdev)
{
return 0;
}
/* edma_get_ringparam()
* get ring size
*/
static void edma_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct edma_adapter *adapter = netdev_priv(netdev);
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
ring->tx_max_pending = edma_cinfo->tx_ring_count;
ring->rx_max_pending = edma_cinfo->rx_ring_count;
}
/* Ethtool operations
*/
static const struct ethtool_ops edma_ethtool_ops = {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,7,0)
.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
#endif
.get_drvinfo = &edma_get_drvinfo,
.get_link = &ethtool_op_get_link,
.get_msglevel = &edma_get_msglevel,
.nway_reset = &edma_nway_reset,
.get_wol = &edma_get_wol,
.get_link_ksettings = &edma_get_settings,
.set_link_ksettings = &edma_set_settings,
.get_strings = &edma_get_strings,
.get_sset_count = &edma_get_strset_count,
.get_ethtool_stats = &edma_get_ethtool_stats,
.get_coalesce = &edma_get_coalesce,
.set_coalesce = &edma_set_coalesce,
.get_priv_flags = edma_get_priv_flags,
.set_priv_flags = edma_set_priv_flags,
.get_ringparam = edma_get_ringparam,
};
/* edma_set_ethtool_ops
* Set ethtool operations
*/
void edma_set_ethtool_ops(struct net_device *netdev)
{
netdev->ethtool_ops = &edma_ethtool_ops;
}

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From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Sun, 11 Mar 2018 14:41:31 +0100
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
There's an interaction issue between the clk changes:"
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
" and the cpufreq-dt.
cpufreq-dt is now spamming the kernel-log with the following:
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
for freq 761142857 (-34)
This only happens on certain devices like the Compex WPJ428
and AVM FritzBox!4040. However, other devices like the Asus
RT-AC58U and Meraki MR33 work just fine.
The issue stem from the fact that all higher CPU-Clocks
are achieved by switching the clock-parent to the P_DDRPLLAPSS
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
as part of the DDR calibration.
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
This patch attempts to fix the issue by modifying
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
to use a new qcom_find_freq_close() function, which returns the closest
matching frequency, instead of the next higher. This way, the SoC in
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
try to overclock to 761 MHz.
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *last = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate == f->freq)
+ return f;
+
+ if (f->freq > rate) {
+ if (!last ||
+ (f->freq - rate) < (rate - last->freq))
+ return f;
+ else
+ return last;
+ }
+ last = f;
+ }
+
+ return last;
+}
+
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
u32 mask;
int ret;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1305,6 +1328,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ const struct freq_tbl *f;
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
- return rate;
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return rate;
+
+ return f->freq;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {

26
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From a63c7162a1dae9f1185897641dc3e47e295563d6 Mon Sep 17 00:00:00 2001
From: Pavel Kubelun <be.dissent@gmail.com>
Date: Mon, 6 May 2019 20:55:16 +0300
Subject: [PATCH] ARM: dts: qcom: ipq4019: fix sleep clock
It seems like sleep_clk was copied from ipq806x.
Fix ipq40xx sleep_clk to the value QSDK defines.
Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d
Link: https://patchwork.kernel.org/comment/22721613/
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> [clock-output-names]
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [just fixed the value]
---
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -142,7 +142,8 @@
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
- clock-frequency = <32768>;
+ clock-frequency = <32000>;
+ clock-output-names = "gcc_sleep_clk_src";
#clock-cells = <0>;
};

52
root/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch Normal file
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From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Tue, 28 Mar 2017 22:35:33 +0530
Subject: [PATCH] clk: qcom: ipq4019: add ess reset
Added the ESS reset in IPQ4019 GCC.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
2 files changed, 22 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -165,5 +165,16 @@
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
+#define ESS_MAC1_ARES 72
+#define ESS_MAC2_ARES 73
+#define ESS_MAC3_ARES 74
+#define ESS_MAC4_ARES 75
+#define ESS_MAC5_ARES 76
+#define ESS_PSGMII_ARES 77
+#define ESS_MAC1_CLK_DIS 78
+#define ESS_MAC2_CLK_DIS 79
+#define ESS_MAC3_CLK_DIS 80
+#define ESS_MAC4_CLK_DIS 81
+#define ESS_MAC5_CLK_DIS 82
#endif

48
root/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch Normal file
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From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 30 Oct 2020 13:36:31 +0100
Subject: [PATCH] arm: compressed: add appended DTB section
This adds a appended_dtb section to the ARM decompressor
linker script.
This allows using the existing ARM zImage appended DTB support for
appending a DTB to the raw ELF kernel.
Its size is set to 1MB max to match the zImage appended DTB size limit.
To use it to pass the DTB to the kernel, objcopy is used:
objcopy --set-section-flags=.appended_dtb=alloc,contents \
--update-section=.appended_dtb=<target>.dtb vmlinux
This is based off the following patch:
https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -101,6 +101,13 @@ SECTIONS
_edata = .;
+ .appended_dtb : {
+ /* leave space for appended DTB */
+ . += 0x100000;
+ }
+
+ _edata_dtb = .;
+
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
@@ -138,4 +145,4 @@ SECTIONS
ARM_ASSERTS
}
-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");

66
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From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Fri, 23 Oct 2020 19:42:36 +1000
Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
For IPQ40XX systems where the SoC watchdog is activated before linux,
the watchdog timer may be too small for linux to finish uncompress,
boot, and watchdog management start.
If the watchdog is enabled, set the timeout for it to 30 seconds.
The functionality and offsets were copied from:
drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
The watchdog memory address was taken from:
arch/arm/boot/dts/qcom-ipq4019.dtsi
This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
RouterBoot bootloader.
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
---
arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -602,6 +602,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+ /* offsets:
+ * 0x04 reset (=1 resets countdown)
+ * 0x08 enable (=0 disables)
+ * 0x0c status (=1 when SoC was reset by watchdog)
+ * 0x10 bark (=timeout warning in ticks)
+ * 0x14 bite (=timeout reset in ticks)
+ * clock rate is 1<<15 hertz
+ */
+ .equ watchdog, 0x0b017000 @Store watchdog base address
+ movw r0, #:lower16:watchdog
+ movt r0, #:upper16:watchdog
+ ldr r1, [r0, #0x08] @Get enabled?
+ cmp r1, #1 @If not enabled, do not change
+ bne watchdog_finished
+ mov r1, #0
+ str r1, [r0, #0x08] @Disable the watchdog
+ mov r1, #1
+ str r1, [r0, #0x04] @Pet the watchdog
+ mov r1, #30 @30 seconds timeout
+ lsl r1, r1, #15 @converted to ticks
+ str r1, [r0, #0x10] @Set the bark timeout
+ str r1, [r0, #0x14] @Set the bite timeout
+ mov r1, #1
+ str r1, [r0, #0x08] @Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
/*
* The C runtime environment should now be setup sufficiently.
* Set up some pointers, and start decompressing.

24
root/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch Normal file
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@ -0,0 +1,24 @@
From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Dec 2020 13:35:35 +0100
Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
When using sdhci_msm_set_clock clock setting will fail, so lets
use the generic sdhci_set_clock.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/host/sdhci-msm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
- .set_clock = sdhci_msm_set_clock,
+ .set_clock = sdhci_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,

46
root/target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch Normal file
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@ -0,0 +1,46 @@
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 02:20:54 +0100
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
nodes which are needed for the ar40xx.c driver to initialize the
switch.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -617,6 +617,29 @@
};
};
+ ess-switch@c000000 {
+ compatible = "qcom,ess-switch";
+ reg = <0xc000000 0x80000>;
+ switch_access_mode = "local bus";
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
+ switch_initvlas = <0x7c 0x54>;
+ status = "disabled";
+ };
+
+ ess-psgmii@98000 {
+ compatible = "qcom,ess-psgmii";
+ reg = <0x98000 0x800>;
+ psgmii_access_mode = "local bus";
+ status = "disabled";
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;

53
root/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch Normal file
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@ -0,0 +1,53 @@
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
From: Rakesh Nair <ranair@codeaurora.org>
Date: Wed, 20 Jul 2016 15:02:01 +0530
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
netdev_ops
Add callback support to get default vlan tag and register
receive flow steering filter.
Used by IPQ4019 ess-edma driver.
BUG=chrome-os-partner:33096
TEST=none
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/362203
Commit-Ready: Grant Grundler <grundler@chromium.org>
Tested-by: Grant Grundler <grundler@chromium.org>
Reviewed-by: Grant Grundler <grundler@chromium.org>
---
include/linux/netdevice.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -765,6 +765,16 @@ struct xps_map {
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
- sizeof(struct xps_map)) / sizeof(u16))
+#ifdef CONFIG_RFS_ACCEL
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
+ __be32 src,
+ __be32 dst,
+ __be16 sport,
+ __be16 dport,
+ u8 proto,
+ u16 rxq_index,
+ u32 action);
+#endif
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.
*/
@@ -1445,6 +1455,9 @@ struct net_device_ops {
const struct sk_buff *skb,
u16 rxq_index,
u32 flow_id);
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
+ set_rfs_filter_callback_t set_filter);
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
#endif
int (*ndo_add_slave)(struct net_device *dev,
struct net_device *slave_dev,

27
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@ -0,0 +1,27 @@
--- a/drivers/net/mdio/Kconfig
+++ b/drivers/net/mdio/Kconfig
@@ -27,6 +27,13 @@ config OF_MDIO
help
OpenFirmware MDIO bus (Ethernet PHY) accessors
+config AR40XX_PHY
+ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
+ depends on HAS_IOMEM && OF && OF_MDIO
+ select SWCONFIG
+ help
+ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
+
if MDIO_BUS
config MDIO_DEVRES
--- a/drivers/net/mdio/Makefile
+++ b/drivers/net/mdio/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.
obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
+obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
+
obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o

61
root/target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch Normal file
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@ -0,0 +1,61 @@
From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
--- /dev/null
+++ b/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device Tree constants for the Qualcomm QCA807X PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
+#define _DT_BINDINGS_QCOM_QCA807X_H
+
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+/* Default value */
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/* Full amplitude, full bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+/* Both amplitude and bias current follow DSP */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+/* Full amplitude, half bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
+ * otherwise half bias current
+ */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+/* Full amplitude; same bias current setting with “010” and “011”,
+ * but half more bias is reduced when cable <10m
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+/* Amplitude follow DSP; same bias current setting with “110”, default value */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif

50
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@ -0,0 +1,50 @@
From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 7 Oct 2020 17:38:48 +0200
Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by userspace,
so lets enable registering each PHY as GPIO controller and add driver for it.
These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
2 files changed, 7 insertions(+)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -320,6 +320,12 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
+config QCA807X_PHY
+ tristate "Qualcomm QCA807X PHYs"
+ depends on OF_MDIO
+ help
+ Currently supports the QCA8072 and QCA8075 models.
+
config QSEMI_PHY
tristate "Quality Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o

62
root/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch Normal file
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@ -0,0 +1,62 @@
From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 2 Oct 2020 10:43:26 +0200
Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/qcom-qca807x.h>
/ {
#address-cells = <1>;
@@ -598,22 +599,39 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+
+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
+ qcom,psgmii-az;
};
};

37
root/target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch Normal file
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@ -0,0 +1,37 @@
From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Thu, 19 Jan 2017 02:01:31 +0100
Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++
drivers/net/ethernet/qualcomm/Makefile | 1 +
2 files changed, 10 insertions(+)
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -62,4 +62,14 @@ config QCOM_EMAC
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
+config ESSEDMA
+ tristate "Qualcomm Atheros ESS Edma support"
+ depends on OF_MDIO
+ help
+ This driver supports ethernet edma adapter.
+ Say Y to build this driver.
+
+ To compile this driver as a module, choose M here. The module
+ will be called essedma.ko.
+
endif # NET_VENDOR_QUALCOMM
--- a/drivers/net/ethernet/qualcomm/Makefile
+++ b/drivers/net/ethernet/qualcomm/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
qcauart-objs := qca_uart.o
obj-y += emac/
+obj-$(CONFIG_ESSEDMA) += essedma/
obj-$(CONFIG_RMNET) += rmnet/

92
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@ -0,0 +1,92 @@
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 01:01:10 +0100
Subject: [PATCH] dts: ipq4019: add ethernet essedma node
This patch adds the device-tree node for the ethernet
interfaces.
Note: The driver isn't anywhere close to be upstream,
so the info might change.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -39,6 +39,8 @@
spi1 = &blsp1_spi2;
i2c0 = &blsp1_i2c3;
i2c1 = &blsp1_i2c4;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
cpus {
@@ -658,6 +660,64 @@
status = "disabled";
};
+ edma@c080000 {
+ compatible = "qcom,ess-edma";
+ reg = <0xc080000 0x8000>;
+ qcom,page-mode = <0>;
+ qcom,rx_head_buf_size = <1540>;
+ qcom,mdio_supported;
+ qcom,poll_required = <1>;
+ qcom,num_gmac = <2>;
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
+ 0 66 IRQ_TYPE_EDGE_RISING
+ 0 67 IRQ_TYPE_EDGE_RISING
+ 0 68 IRQ_TYPE_EDGE_RISING
+ 0 69 IRQ_TYPE_EDGE_RISING
+ 0 70 IRQ_TYPE_EDGE_RISING
+ 0 71 IRQ_TYPE_EDGE_RISING
+ 0 72 IRQ_TYPE_EDGE_RISING
+ 0 73 IRQ_TYPE_EDGE_RISING
+ 0 74 IRQ_TYPE_EDGE_RISING
+ 0 75 IRQ_TYPE_EDGE_RISING
+ 0 76 IRQ_TYPE_EDGE_RISING
+ 0 77 IRQ_TYPE_EDGE_RISING
+ 0 78 IRQ_TYPE_EDGE_RISING
+ 0 79 IRQ_TYPE_EDGE_RISING
+ 0 80 IRQ_TYPE_EDGE_RISING
+ 0 240 IRQ_TYPE_EDGE_RISING
+ 0 241 IRQ_TYPE_EDGE_RISING
+ 0 242 IRQ_TYPE_EDGE_RISING
+ 0 243 IRQ_TYPE_EDGE_RISING
+ 0 244 IRQ_TYPE_EDGE_RISING
+ 0 245 IRQ_TYPE_EDGE_RISING
+ 0 246 IRQ_TYPE_EDGE_RISING
+ 0 247 IRQ_TYPE_EDGE_RISING
+ 0 248 IRQ_TYPE_EDGE_RISING
+ 0 249 IRQ_TYPE_EDGE_RISING
+ 0 250 IRQ_TYPE_EDGE_RISING
+ 0 251 IRQ_TYPE_EDGE_RISING
+ 0 252 IRQ_TYPE_EDGE_RISING
+ 0 253 IRQ_TYPE_EDGE_RISING
+ 0 254 IRQ_TYPE_EDGE_RISING
+ 0 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ gmac0: gmac0 {
+ local-mac-address = [00 00 00 00 00 00];
+ vlan_tag = <1 0x1f>;
+ };
+
+ gmac1: gmac1 {
+ local-mac-address = [00 00 00 00 00 00];
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+ };
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;

180
root/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch Normal file
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@ -0,0 +1,180 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
obj-$(CONFIG_QCOM_APR) += apr.o
obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -189,6 +189,13 @@ config QCOM_SOCINFO
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on ARCH_QCOM || COMPILE_TEST
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL 0xb0
+#define TCSR_USB_HSPHY_CONFIG 0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+ writel(val, base + TCSR_USB_PORT_SEL);
+ }
+
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
+ }
+
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+ u32 tmp = 0;
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+ dev_info(&pdev->dev,
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+ .driver = {
+ .name = "tcsr",
+ .owner = THIS_MODULE,
+ .of_match_table = tcsr_dt_match,
+ },
+ .probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0 0x1
+#define TCSR_USB_SELECT_USB3_P1 0x2
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII 0
+#define TCSR_ESS_PSGMII_RGMII5 1
+#define TCSR_ESS_PSGMII_RMII0 2
+#define TCSR_ESS_PSGMII_RMII1 4
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
+#define TCSR_ESS_PSGMII_RGMII4 9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG 0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
+
+#endif

176
root/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch Normal file
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@ -0,0 +1,176 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -15,6 +15,7 @@
*/
#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
@@ -29,6 +30,32 @@
};
soc {
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
rng@22000 {
status = "ok";
};
@@ -74,14 +101,6 @@
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
};
serial@78af000 {
@@ -109,5 +128,41 @@
wifi@a800000 {
status = "ok";
};
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,5 +18,73 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&blsp1_spi1 {
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ kernel@180000 {
+ label = "kernel";
+ reg = <0x180000 0x400000>;
+ };
+ rootfs@580000 {
+ label = "rootfs";
+ reg = <0x580000 0x1600000>;
+ };
+ firmware@180000 {
+ label = "firmware";
+ reg = <0x180000 0x1a00000>;
+ };
+ };
};

45
root/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch
View file

@ -1,47 +1,68 @@
From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 11:03:18 +0100
Subject: [PATCH] arm: boot: add dts files
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -950,11 +950,54 @@
@@ -902,11 +902,65 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4018-ap120c-ac.dtb \
qcom-ipq4018-ap120c-ac-bit.dtb \
qcom-ipq4018-jalapeno.dtb \
+ qcom-ipq4018-a42.dtb \
+ qcom-ipq4018-dap-2610.dtb \
+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \
+ qcom-ipq4018-magic-2-wifi-next.dtb \
+ qcom-ipq4018-ea6350v3.dtb \
+ qcom-ipq4018-eap1300.dtb \
+ qcom-ipq4018-ecw5211.dtb \
+ qcom-ipq4018-emd1.dtb \
+ qcom-ipq4018-emr3500.dtb \
+ qcom-ipq4018-ens620ext.dtb \
+ qcom-ipq4018-ex6100v2.dtb \
+ qcom-ipq4018-ex6150v2.dtb \
+ qcom-ipq4018-fritzbox-4040.dtb \
+ qcom-ipq4018-jalapeno.dtb \
+ qcom-ipq4018-gl-ap1300.dtb \
+ qcom-ipq4018-meshpoint-one.dtb \
+ qcom-ipq4018-hap-ac2.dtb \
+ qcom-ipq4018-sxtsq-5-ac.dtb \
+ qcom-ipq4018-nbg6617.dtb \
+ qcom-ipq4019-oap100.dtb \
+ qcom-ipq4018-pa1200.dtb \
+ qcom-ipq4018-rt-ac58u.dtb \
+ qcom-ipq4018-rutx-08_10.dtb \
+ qcom-ipq4018-rutx-09_11.dtb \
+ qcom-ipq4018-rutx-12.dtb \
+ qcom-ipq4018-wac510.dtb \
+ qcom-ipq4018-wre6606.dtb \
+ qcom-ipq4018-wrtq-329acn.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ com-ipq4019-a62.dtb \
+ qcom-ipq4019-a62.dtb \
+ qcom-ipq4019-cm520-79f.dtb \
+ qcom-ipq4019-e2600ac-c1.dtb \
+ qcom-ipq4019-e2600ac-c2.dtb \
+ qcom-ipq4019-ea8300.dtb \
+ qcom-ipq4019-eap2200.dtb \
+ qcom-ipq4019-fritzbox-7530.dtb \
+ qcom-ipq4019-fritzrepeater-1200.dtb \
+ qcom-ipq4019-fritzrepeater-3000.dtb \
+ qcom-ipq4019-r619ac.dtb \
+ qcom-ipq4019-r619ac-128m.dtb \
+ qcom-ipq4019-map-ac2200.dtb \
+ qcom-ipq4019-e2600ac-c1.dtb \
+ qcom-ipq4019-e2600ac-c2.dtb \
+ qcom-ipq4019-habanero-dvk.dtb \
+ qcom-ipq4019-map-ac2200.dtb \
+ qcom-ipq4019-mr8300.dtb \
+ qcom-ipq4019-pa2200.dtb \
+ qcom-ipq4019-r619ac-64m.dtb \
+ qcom-ipq4019-r619ac-128m.dtb \
+ qcom-ipq4019-rbr50.dtb \
+ qcom-ipq4019-rbs50.dtb \
+ qcom-ipq4019-rtl30vw.dtb \
+ qcom-ipq4019-srr60.dtb \
+ qcom-ipq4019-srs60.dtb \
+ qcom-ipq4019-u4019-32m.dtb \
+ qcom-ipq4019-wpj419.dtb \
+ qcom-ipq4019-wtr-m2133hp.dtb \
@ -54,4 +75,4 @@
+ qcom-ipq4029-mr33.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \

167
root/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch Normal file
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@ -0,0 +1,167 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -17,53 +17,79 @@
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
soc {
+ rng@22000 {
+ status = "okay";
+ };
+
pinctrl@1000000 {
serial_0_pins: serial0-pinmux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
};
serial_1_pins: serial1-pinmux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
};
spi_0_pins: spi-0-pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
+ };
+ pinconf {
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio12";
+ drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c-0-pinmux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio10", "gpio11";
+ };
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
nand_pins: nand-pins {
- pins = "gpio53", "gpio55", "gpio56",
- "gpio57", "gpio58", "gpio59",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68", "gpio69";
- function = "qpic";
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
};
};
@@ -89,11 +115,11 @@
status = "ok";
cs-gpios = <&tlmm 12 0>;
- m25p80@0 {
+ mx25l25635e@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "mx25l25635e";
spi-max-frequency = <24000000>;
};
};
@@ -103,9 +129,48 @@
perst-gpio = <&tlmm 38 0x1>;
};
+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ };
+
qpic-nand@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ cryptobam: dma@8e04000 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
};
};