mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,48 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
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||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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||||
# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,103 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include "adciop.h"
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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/* ------------------------------------------------------------------------- */
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int board_early_init_f (void)
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{
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/*
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* Set port pin in escc2 to keep living, and configure user led output
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*/
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*(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */
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*(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */
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/*
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* Init pci regs
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*/
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*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
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*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
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*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
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*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
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*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
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*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
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*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_f("serial#", str, sizeof (str));
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puts ("Board: ");
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if (!i || strncmp (str, "ADCIOP", 6)) {
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puts ("### No HW ID - assuming ADCIOP\n");
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return (1);
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}
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puts (str);
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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return (16 * 1024 * 1024);
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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@ -0,0 +1,44 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor:
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*
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* Start Address Length
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* +-----------------------+ 0x4000_0000 Start of Flash -----------------
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* | MON8xx code | 0x4000_0100 Reset Vector
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* +-----------------------+ 0x400?_????
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* | (unused) |
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* +-----------------------+ 0x4001_FF00
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* | Ethernet Addresses | 0x78
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* +-----------------------+ 0x4001_FF78
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* | (Reserved for MON8xx) | 0x44
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* +-----------------------+ 0x4001_FFBC
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* | Lock Address | 0x04
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* +-----------------------+ 0x4001_FFC0 ^
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* | Hardware Information | 0x40 | MON8xx
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* +=======================+ 0x4002_0000 (sector border) -----------------
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* | Autostart Header | | Applications
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* | ... | v
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*
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*****************************************************************************/
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@ -0,0 +1,113 @@
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/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0, size_b1;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
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if (size_b1 > size_b0) {
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printf ("## ERROR: "
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"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
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size_b1, size_b1<<20,
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size_b0, size_b0<<20
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);
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flash_info[0].flash_id = FLASH_UNKNOWN;
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[0].sector_count = -1;
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flash_info[1].sector_count = -1;
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flash_info[0].size = 0;
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flash_info[1].size = 0;
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return (0);
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}
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/* Re-do sizing to get full correct info */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
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FLASH_BASE0_PRELIM+size_b0-1,
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&flash_info[0]);
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if (size_b1) {
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/* Re-do sizing to get full correct info */
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size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0),
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&flash_info[1]);
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flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]);
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
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FLASH_BASE0_PRELIM+size_b0+size_b1-1,
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&flash_info[1]);
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/* monitor protection OFF by default (one is enough) */
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flash_protect(FLAG_PROTECT_CLEAR,
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FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
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FLASH_BASE0_PRELIM+size_b0-1,
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&flash_info[0]);
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} else {
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[1].sector_count = -1;
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}
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flash_info[0].size = size_b0;
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flash_info[1].size = size_b1;
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return (size_b0 + size_b1);
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}
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@ -0,0 +1,49 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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|
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o \
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../common/misc.o \
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../common/auto_update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $^)
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|
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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|
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sinclude $(obj).depend
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|
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#########################################################################
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@ -0,0 +1,477 @@
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/*
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* (C) Copyright 2005-2008
|
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
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*
|
||||
* (C) Copyright 2001-2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <flash.h>
|
||||
#include <mtd/cfi_flash.h>
|
||||
#include <asm/4xx_pci.h>
|
||||
#include <pci.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef FPGA_DEBUG
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
/* fpga configuration data - gzip compressed and generated by bin2c */
|
||||
const unsigned char fpgadata[] =
|
||||
{
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
#ifdef CONFIG_LCD_USED
|
||||
/* logo bitmap data - gzip compressed and generated by bin2c */
|
||||
unsigned char logo_bmp[] =
|
||||
{
|
||||
#include "logo_640_480_24bpp.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common lcd code (for esd boards)
|
||||
*/
|
||||
#include "../common/lcd.c"
|
||||
#include "../common/s1d13505_640_480_16bpp.h"
|
||||
#include "../common/s1d13806_640_480_16bpp.h"
|
||||
#endif /* CONFIG_LCD_USED */
|
||||
|
||||
/*
|
||||
* include common auto-update code (for esd boards)
|
||||
*/
|
||||
#include "../common/auto_update.h"
|
||||
|
||||
au_image_t au_image[] = {
|
||||
{"preinst.img", 0, -1, AU_SCRIPT},
|
||||
{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
|
||||
{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
|
||||
{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
|
||||
{"work.img", 0xfe500000, 0x01400000, AU_NOR},
|
||||
{"data.img", 0xff900000, 0x00580000, AU_NOR},
|
||||
{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
|
||||
{"postinst.img", 0, 0, AU_SCRIPT},
|
||||
};
|
||||
|
||||
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
|
||||
|
||||
int board_revision(void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
unsigned long value;
|
||||
|
||||
/*
|
||||
* Get version of APC405 board from GPIO's
|
||||
*/
|
||||
|
||||
/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
|
||||
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
|
||||
|
||||
/* wait some time before reading input */
|
||||
udelay(1000);
|
||||
|
||||
/* get config bits */
|
||||
value = in_be32((void*)GPIO0_IR) & 0x001c0000;
|
||||
/*
|
||||
* Restore GPIO settings
|
||||
*/
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg);
|
||||
|
||||
switch (value) {
|
||||
case 0x001c0000:
|
||||
/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
|
||||
return 2;
|
||||
case 0x000c0000:
|
||||
/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
|
||||
return 3;
|
||||
case 0x00180000:
|
||||
/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
|
||||
return 6;
|
||||
case 0x00140000:
|
||||
/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
|
||||
return 8;
|
||||
default:
|
||||
/* should not be reached! */
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* First pull fpga-prg pin low, to disable fpga logic
|
||||
*/
|
||||
out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
|
||||
out_be32((void*)GPIO0_OR, 0); /* pull prg low */
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks
|
||||
*/
|
||||
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
|
||||
|
||||
/*
|
||||
* New boards have a single 32MB flash connected to CS0
|
||||
* instead of two 16MB flashes on CS0+1.
|
||||
*/
|
||||
if (board_revision() >= 8) {
|
||||
/* disable CS1 */
|
||||
mtebc(PB1AP, 0);
|
||||
mtebc(PB1CR, 0);
|
||||
|
||||
/* resize CS0 to 32MB */
|
||||
mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
|
||||
mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
if (gd->board_type >= 8)
|
||||
cfi_flash_num_flash_banks = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define FUJI_BASE 0xf0100200
|
||||
#define LCDBL_PWM 0xa0
|
||||
#define LCDBL_PWMMIN 0xa4
|
||||
#define LCDBL_PWMMAX 0xa8
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
|
||||
u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
|
||||
u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
|
||||
u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
int status;
|
||||
int index;
|
||||
int i;
|
||||
unsigned long CPC0_CR0Reg;
|
||||
char *str;
|
||||
uchar *logo_addr;
|
||||
ulong logo_size;
|
||||
ushort minb, maxb;
|
||||
int result;
|
||||
|
||||
/*
|
||||
* Setup GPIO pins (CS6+CS7 as GPIO)
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
|
||||
|
||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
|
||||
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
|
||||
printf("GUNZIP ERROR - must RESET board to recover\n");
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
status = fpga_boot(dst, len);
|
||||
if (status != 0) {
|
||||
printf("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf("(Timeout: "
|
||||
"INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf("(Timeout: "
|
||||
"INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf("(Timeout: "
|
||||
"DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = dst[index];
|
||||
printf("FPGA: %s\n", &(dst[index+1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf("Rebooting in %2d seconds \r",i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay(1000);
|
||||
}
|
||||
putc('\n');
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/* restore gpio/cs settings */
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg);
|
||||
|
||||
puts("FPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = dst[index];
|
||||
printf("%s ", &(dst[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
free(dst);
|
||||
|
||||
/*
|
||||
* Reset FPGA via FPGA_DATA pin
|
||||
*/
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK);
|
||||
udelay(1000); /* wait 1ms */
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Write board revision in FPGA
|
||||
*/
|
||||
out_be16(fpga_ctrl2,
|
||||
(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
|
||||
|
||||
/*
|
||||
* Enable power on PS/2 interface (with reset)
|
||||
*/
|
||||
out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
|
||||
for (i=0;i<100;i++)
|
||||
udelay(1000);
|
||||
udelay(1000);
|
||||
out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
out_8(duart0_mcr, 0x08);
|
||||
out_8(duart1_mcr, 0x08);
|
||||
|
||||
/*
|
||||
* Init lcd interface and display logo
|
||||
*/
|
||||
str = getenv("splashimage");
|
||||
if (str) {
|
||||
logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
|
||||
logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
|
||||
} else {
|
||||
logo_addr = logo_bmp;
|
||||
logo_size = sizeof(logo_bmp);
|
||||
}
|
||||
|
||||
if (gd->board_type >= 6) {
|
||||
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
|
||||
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
|
||||
regs_13505_640_480_16bpp,
|
||||
sizeof(regs_13505_640_480_16bpp) /
|
||||
sizeof(regs_13505_640_480_16bpp[0]),
|
||||
logo_addr, logo_size);
|
||||
if (result && str) {
|
||||
/* retry with internal image */
|
||||
logo_addr = logo_bmp;
|
||||
logo_size = sizeof(logo_bmp);
|
||||
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
|
||||
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
|
||||
regs_13505_640_480_16bpp,
|
||||
sizeof(regs_13505_640_480_16bpp) /
|
||||
sizeof(regs_13505_640_480_16bpp[0]),
|
||||
logo_addr, logo_size);
|
||||
}
|
||||
} else {
|
||||
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
|
||||
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
|
||||
regs_13806_640_480_16bpp,
|
||||
sizeof(regs_13806_640_480_16bpp) /
|
||||
sizeof(regs_13806_640_480_16bpp[0]),
|
||||
logo_addr, logo_size);
|
||||
if (result && str) {
|
||||
/* retry with internal image */
|
||||
logo_addr = logo_bmp;
|
||||
logo_size = sizeof(logo_bmp);
|
||||
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
|
||||
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
|
||||
regs_13806_640_480_16bpp,
|
||||
sizeof(regs_13806_640_480_16bpp) /
|
||||
sizeof(regs_13806_640_480_16bpp[0]),
|
||||
logo_addr, logo_size);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset microcontroller and setup backlight PWM controller
|
||||
*/
|
||||
out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
|
||||
for (i=0;i<10;i++)
|
||||
udelay(1000);
|
||||
out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
|
||||
|
||||
minb = 0;
|
||||
maxb = 0xff;
|
||||
str = getenv("lcdbl");
|
||||
if (str) {
|
||||
minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
|
||||
if (str && (*str=',')) {
|
||||
str++;
|
||||
maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
|
||||
} else
|
||||
minb = 0;
|
||||
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
|
||||
|
||||
printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
|
||||
}
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
|
||||
|
||||
/*
|
||||
* fix environment for field updated units
|
||||
*/
|
||||
if (getenv("altbootcmd") == NULL) {
|
||||
setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
|
||||
setenv("usbargs", CONFIG_SYS_USB_ARGS);
|
||||
setenv("bootcmd", CONFIG_BOOTCOMMAND);
|
||||
setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
|
||||
setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
|
||||
setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
|
||||
saveenv();
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof(str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming APC405");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
gd->board_type = board_revision();
|
||||
printf(", Rev. 1.%ld\n", gd->board_type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
|
||||
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) {
|
||||
out_be16(fpga_mode,
|
||||
in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
|
||||
} else {
|
||||
out_be16(fpga_mode,
|
||||
in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
|
||||
int usb_board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_stop(void)
|
||||
{
|
||||
unsigned short tmp;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* reset PCI bus
|
||||
* This is required to make some very old Linux OHCI driver
|
||||
* work after U-Boot has used the OHCI controller.
|
||||
*/
|
||||
pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
|
||||
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
|
||||
|
||||
for (i = 0; i < 100; i++)
|
||||
udelay(1000);
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_init_fail(void)
|
||||
{
|
||||
usb_board_stop();
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
|
||||
4008
root/package/utils/sysupgrade-helper/src/board/esd/apc405/fpgadata.c
Normal file
4008
root/package/utils/sysupgrade-helper/src/board/esd/apc405/fpgadata.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
410
root/package/utils/sysupgrade-helper/src/board/esd/ar405/ar405.c
Normal file
410
root/package/utils/sysupgrade-helper/src/board/esd/ar405/ar405.c
Normal file
|
|
@ -0,0 +1,410 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "ar405.h"
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
/* fpga configuration data - generated by bin2cc */
|
||||
const unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
const unsigned char fpgadata_xl30[] = {
|
||||
#include "fpgadata_xl30.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
int index, len, i;
|
||||
int status;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
/* first try 40er image */
|
||||
gd->board_type = 40;
|
||||
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
|
||||
if (status != 0) {
|
||||
/* try xl30er image */
|
||||
gd->board_type = 30;
|
||||
status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
|
||||
if (status != 0) {
|
||||
/* booting FPGA failed */
|
||||
#ifndef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
printf ("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf ("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf ("Rebooting in %2d seconds \r", i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay (1000);
|
||||
}
|
||||
putc ('\n');
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
|
||||
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
const unsigned char *fpga;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming AR405");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
if (gd->board_type == 30) {
|
||||
fpga = fpgadata_xl30;
|
||||
} else {
|
||||
fpga = fpgadata;
|
||||
}
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpga[index];
|
||||
printf ("%s ", &(fpga[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#if 1 /* test-only: some internal test routines... */
|
||||
#define DIGEN ((void *)0xf03000b4) /* u8 */
|
||||
#define DIGOUT ((void *)0xf03000b0) /* u16 */
|
||||
#define DIGIN ((void *)0xf03000a0) /* u16 */
|
||||
|
||||
/*
|
||||
* Some test routines
|
||||
*/
|
||||
int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int start;
|
||||
int end;
|
||||
|
||||
if (argc != 3) {
|
||||
puts("Usage: digtest n_start n_end (digtest 0 7)\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
start = simple_strtol (argv[1], NULL, 10);
|
||||
end = simple_strtol (argv[2], NULL, 10);
|
||||
|
||||
/*
|
||||
* Enable digital outputs
|
||||
*/
|
||||
out_8(DIGEN, 0x08);
|
||||
|
||||
printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
|
||||
start, end);
|
||||
|
||||
/*
|
||||
* Set outputs one by one
|
||||
*/
|
||||
for (;;) {
|
||||
for (i=start; i<=end; i++) {
|
||||
out_be16(DIGOUT, 0x0001 << i);
|
||||
for (k=0; k<200; k++)
|
||||
udelay(1000);
|
||||
|
||||
if (in_be16(DIGIN) != (0x0001 << i)) {
|
||||
printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
|
||||
0x0001 << i, in_be16(DIGIN));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
digtest, 3, 1, do_digtest,
|
||||
"Test digital in-/output",
|
||||
""
|
||||
);
|
||||
|
||||
#define ERROR_DELTA 256
|
||||
|
||||
struct io {
|
||||
short val;
|
||||
short dummy;
|
||||
};
|
||||
|
||||
int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
short val;
|
||||
int i;
|
||||
int volt;
|
||||
struct io *out;
|
||||
struct io *in;
|
||||
|
||||
out = (struct io *)0xf0300090;
|
||||
in = (struct io *)0xf0300000;
|
||||
|
||||
i = simple_strtol (argv[1], NULL, 10);
|
||||
|
||||
volt = 0;
|
||||
printf("Setting Channel %d to %dV...\n", i, volt);
|
||||
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
|
||||
udelay(10000);
|
||||
val = in_be16((void *)&(in[i*2].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
val = in_be16((void *)&(in[i*2+1].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
|
||||
volt = 5;
|
||||
printf("Setting Channel %d to %dV...\n", i, volt);
|
||||
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
|
||||
udelay(10000);
|
||||
val = in_be16((void *)&(in[i*2].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
val = in_be16((void *)&(in[i*2+1].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
|
||||
volt = 10;
|
||||
printf("Setting Channel %d to %dV...\n", i, volt);
|
||||
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
|
||||
udelay(10000);
|
||||
val = in_be16((void *)&(in[i*2].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
val = in_be16((void *)&(in[i*2+1].val));
|
||||
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
|
||||
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
|
||||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
|
||||
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
|
||||
((volt * 0x7fff) / 40) + ERROR_DELTA);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("Channel %d OK!\n", i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
anatest, 2, 1, do_anatest,
|
||||
"Test analog in-/output",
|
||||
""
|
||||
);
|
||||
|
||||
|
||||
int counter = 0;
|
||||
|
||||
void cyclicInt(void *ptr)
|
||||
{
|
||||
out_be16((void *)0xf03000e8, 0x0800); /* ack int */
|
||||
counter++;
|
||||
}
|
||||
|
||||
|
||||
int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong *incin;
|
||||
int i;
|
||||
|
||||
incin = (ulong *)0xf0300040;
|
||||
|
||||
/*
|
||||
* Clear inc counter
|
||||
*/
|
||||
out_be32((void *)&incin[0], 0);
|
||||
out_be32((void *)&incin[1], 0);
|
||||
out_be32((void *)&incin[2], 0);
|
||||
out_be32((void *)&incin[3], 0);
|
||||
|
||||
incin = (ulong *)0xf0300050;
|
||||
|
||||
/*
|
||||
* Inc a little
|
||||
*/
|
||||
for (i=0; i<10000; i++) {
|
||||
switch (i & 0x03) {
|
||||
case 0:
|
||||
out_8(DIGEN, 0x02);
|
||||
break;
|
||||
case 1:
|
||||
out_8(DIGEN, 0x03);
|
||||
break;
|
||||
case 2:
|
||||
out_8(DIGEN, 0x01);
|
||||
break;
|
||||
case 3:
|
||||
out_8(DIGEN, 0x00);
|
||||
break;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
|
||||
printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
|
||||
printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
|
||||
printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
|
||||
|
||||
out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
|
||||
out_be16((void *)0xf03000ec,
|
||||
in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
|
||||
irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
|
||||
printf("counter=%d\n", counter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
inctest, 3, 1, do_inctest,
|
||||
"Test incremental encoder inputs",
|
||||
""
|
||||
);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
101
root/package/utils/sysupgrade-helper/src/board/esd/ar405/flash.c
Normal file
101
root/package/utils/sysupgrade-helper/src/board/esd/ar405/flash.c
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
int size_val = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
switch (size_b0) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CONFIG_SYS_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
5500
root/package/utils/sysupgrade-helper/src/board/esd/ar405/fpgadata.c
Normal file
5500
root/package/utils/sysupgrade-helper/src/board/esd/ar405/fpgadata.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
/* fpga configuration data - gzip compressed and generated by bin2c */
|
||||
const unsigned char fpgadata[] =
|
||||
{
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
|
||||
*/
|
||||
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
int status;
|
||||
int index;
|
||||
int i;
|
||||
|
||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
|
||||
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
|
||||
printf ("GUNZIP ERROR - must RESET board to recover\n");
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
status = fpga_boot(dst, len);
|
||||
if (status != 0) {
|
||||
printf("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i=0; i<4; i++) {
|
||||
len = dst[index];
|
||||
printf("FPGA: %s\n", &(dst[index+1]));
|
||||
index += len+3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i=20; i>0; i--) {
|
||||
printf("Rebooting in %2d seconds \r",i);
|
||||
for (index=0;index<1000;index++)
|
||||
udelay(1000);
|
||||
}
|
||||
putc ('\n');
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
puts("FPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i=0; i<4; i++) {
|
||||
len = dst[index];
|
||||
printf("%s ", &(dst[index+1]));
|
||||
index += len+3;
|
||||
}
|
||||
putc ('\n');
|
||||
|
||||
free(dst);
|
||||
|
||||
/*
|
||||
* Reset FPGA via FPGA_DATA pin
|
||||
*/
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK);
|
||||
udelay(1000); /* wait 1ms */
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Reset external DUARTs
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
|
||||
udelay(10); /* wait 10us */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
out_8((void *)(DUART0_BA + 4), 0x08);
|
||||
out_8((void *)(DUART1_BA + 4), 0x08);
|
||||
out_8((void *)(DUART2_BA + 4), 0x08);
|
||||
out_8((void *)(DUART3_BA + 4), 0x08);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof(str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming ASH405");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
int size_val = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
switch (size_b0) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CONFIG_SYS_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
4983
root/package/utils/sysupgrade-helper/src/board/esd/ash405/fpgadata.c
Normal file
4983
root/package/utils/sysupgrade-helper/src/board/esd/ash405/fpgadata.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
180
root/package/utils/sysupgrade-helper/src/board/esd/canbt/canbt.c
Normal file
180
root/package/utils/sysupgrade-helper/src/board/esd/canbt/canbt.c
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "canbt.h"
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
/* fpga configuration data */
|
||||
const unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
int index, len, i;
|
||||
int status;
|
||||
|
||||
/*
|
||||
* Setup GPIO pins
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
|
||||
CPC0_CR0Reg |= 0x0070f000;
|
||||
mtdcr (CPC0_CR0, CPC0_CR0Reg);
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
|
||||
if (status != 0) {
|
||||
/* booting FPGA failed */
|
||||
#ifndef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
printf ("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf ("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf ("Rebooting in %2d seconds \r", i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay (1000);
|
||||
}
|
||||
putc ('\n');
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup port pins for normal operation
|
||||
*/
|
||||
out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */
|
||||
out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
|
||||
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (!i || strncmp (str, "CANBT", 5)) {
|
||||
puts ("### No HW ID - assuming CANBT\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
puts (str);
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
/* printf("PB1CR = %x\n", pbcr); */
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-monitor_flash_len,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
|
@ -0,0 +1,807 @@
|
|||
0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
|
||||
0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0c,
|
||||
0x69, 0x6f, 0x5f, 0x63, 0x68, 0x69, 0x70, 0x2e,
|
||||
0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, 0x73,
|
||||
0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31, 0x30,
|
||||
0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, 0x30,
|
||||
0x31, 0x2f, 0x31, 0x31, 0x2f, 0x32, 0x33, 0x00,
|
||||
0x64, 0x00, 0x09, 0x31, 0x33, 0x3a, 0x33, 0x34,
|
||||
0x3a, 0x34, 0x33, 0x00, 0x65, 0xe2, 0x01, 0x00,
|
||||
0x00, 0x18, 0xe6, 0xff, 0x30, 0xe8, 0x01, 0x01,
|
||||
0x01, 0x01, 0xe7, 0xe6, 0x04, 0x01, 0x0d, 0x04,
|
||||
0x07, 0x03, 0x05, 0x03, 0x05, 0x03, 0xe5, 0xe5,
|
||||
0x05, 0x09, 0x04, 0x06, 0x01, 0x07, 0x09, 0x01,
|
||||
0x07, 0x0b, 0x0f, 0x07, 0x03, 0x05, 0x03, 0x05,
|
||||
0x03, 0x11, 0x03, 0x0f, 0x09, 0x03, 0x05, 0x10,
|
||||
0xe5, 0xe6, 0x1a, 0x0a, 0x13, 0x29, 0x19, 0x05,
|
||||
0x09, 0x04, 0x04, 0x09, 0x09, 0x09, 0x0b, 0x04,
|
||||
0x04, 0x09, 0x09, 0x09, 0x0e, 0xe5, 0x01, 0x14,
|
||||
0x09, 0x09, 0x09, 0x03, 0x05, 0x0b, 0x03, 0x05,
|
||||
0x09, 0x09, 0x09, 0x09, 0x01, 0xe6, 0x7b, 0x01,
|
||||
0x01, 0x02, 0x75, 0xe8, 0x3e, 0x3b, 0x02, 0x34,
|
||||
0x0a, 0x09, 0x07, 0x09, 0x01, 0x11, 0x0a, 0xe5,
|
||||
0xe6, 0x5c, 0x1e, 0xe6, 0xe5, 0x0a, 0xe5, 0x50,
|
||||
0x1d, 0x0d, 0x31, 0x09, 0x14, 0x13, 0x07, 0x01,
|
||||
0x01, 0x2a, 0x08, 0x0b, 0x1e, 0x1c, 0x01, 0xe5,
|
||||
0x0f, 0x09, 0x09, 0xe5, 0x07, 0x09, 0xe6, 0x08,
|
||||
0x05, 0x03, 0x01, 0x07, 0x09, 0x09, 0x0d, 0xe8,
|
||||
0x0f, 0x09, 0xe5, 0x07, 0x09, 0x04, 0x05, 0x0a,
|
||||
0x01, 0x07, 0x01, 0x07, 0x09, 0x09, 0x0d, 0xe5,
|
||||
0xe6, 0x0c, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x03, 0x03, 0xe5, 0x06, 0xe5, 0xe6, 0x03,
|
||||
0x03, 0xe5, 0x04, 0x02, 0xe5, 0x01, 0x05, 0xe5,
|
||||
0x07, 0xe5, 0x01, 0x07, 0x05, 0xe7, 0x0f, 0x09,
|
||||
0x09, 0x09, 0x10, 0x04, 0x05, 0x03, 0x03, 0x05,
|
||||
0x09, 0x09, 0x08, 0x08, 0x04, 0x01, 0x06, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x02, 0xe5, 0x04, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x07, 0xe5, 0x02, 0x04, 0xe5, 0x07, 0x02, 0x03,
|
||||
0x02, 0xe5, 0x0e, 0x09, 0x09, 0x09, 0x15, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0e, 0xe6, 0xe5, 0x0c, 0x09,
|
||||
0x09, 0x09, 0x09, 0x04, 0x04, 0x01, 0x09, 0x06,
|
||||
0x02, 0x09, 0x09, 0x11, 0xe7, 0x0c, 0x02, 0x06,
|
||||
0x02, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x02,
|
||||
0x06, 0x02, 0x03, 0x02, 0x01, 0x02, 0x06, 0x02,
|
||||
0x01, 0x04, 0x02, 0x06, 0x02, 0x03, 0x02, 0x02,
|
||||
0x11, 0x03, 0x17, 0x03, 0x05, 0x12, 0x15, 0x02,
|
||||
0x23, 0x08, 0x16, 0x06, 0x0c, 0x05, 0x15, 0x07,
|
||||
0x01, 0x0a, 0x02, 0x0f, 0x01, 0x07, 0x02, 0xe5,
|
||||
0xe5, 0x08, 0x07, 0x02, 0x07, 0x02, 0x10, 0x03,
|
||||
0x11, 0x03, 0x2b, 0x05, 0xe6, 0x2b, 0x0a, 0x06,
|
||||
0x01, 0x01, 0x11, 0x0b, 0x0e, 0xe5, 0x08, 0xe6,
|
||||
0xe5, 0x0f, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09,
|
||||
0x09, 0x01, 0x07, 0x09, 0x0e, 0x01, 0xe5, 0x0f,
|
||||
0x0d, 0x22, 0xe5, 0xe5, 0x27, 0x0e, 0xe6, 0x47,
|
||||
0x11, 0x17, 0x02, 0x04, 0x01, 0x01, 0x0d, 0x0d,
|
||||
0x1f, 0x04, 0x01, 0x24, 0x10, 0x03, 0x01, 0x2a,
|
||||
0x12, 0x0c, 0x06, 0xe5, 0x0a, 0x09, 0x11, 0xe5,
|
||||
0x01, 0x1c, 0x09, 0x17, 0x0b, 0x09, 0x09, 0x04,
|
||||
0x19, 0xe5, 0x0c, 0x01, 0x0d, 0x22, 0x0a, 0x01,
|
||||
0x0d, 0xe5, 0x04, 0x18, 0x01, 0xe5, 0x01, 0x05,
|
||||
0x04, 0x01, 0x02, 0xe5, 0x14, 0x10, 0x0b, 0x02,
|
||||
0x01, 0x02, 0x02, 0xe5, 0x19, 0x0d, 0xe5, 0xe5,
|
||||
0x0e, 0x09, 0x09, 0x02, 0x06, 0x09, 0x02, 0x03,
|
||||
0x04, 0x03, 0x05, 0x09, 0x15, 0x0c, 0x02, 0xe5,
|
||||
0x01, 0x0b, 0x04, 0x04, 0x09, 0x09, 0x02, 0x06,
|
||||
0x09, 0xe5, 0x01, 0x06, 0x05, 0x03, 0x06, 0x1e,
|
||||
0x02, 0x1c, 0x1d, 0x08, 0xe5, 0x05, 0x02, 0x06,
|
||||
0x02, 0x03, 0xe5, 0x1b, 0x03, 0x17, 0xe5, 0x08,
|
||||
0x02, 0x09, 0xe5, 0x09, 0x0f, 0xe5, 0x08, 0x07,
|
||||
0x09, 0x06, 0x0b, 0x02, 0x17, 0xe5, 0x09, 0x01,
|
||||
0x1f, 0x05, 0xe5, 0x02, 0x05, 0x03, 0x1f, 0xe5,
|
||||
0xe6, 0x0e, 0x09, 0x03, 0x05, 0x03, 0x05, 0x09,
|
||||
0x11, 0x01, 0x01, 0x04, 0x0c, 0x01, 0x0a, 0x0e,
|
||||
0x01, 0xe5, 0x0c, 0xe6, 0x06, 0xe6, 0x06, 0xe6,
|
||||
0x06, 0xe6, 0x02, 0x03, 0xe6, 0x03, 0x03, 0x02,
|
||||
0x09, 0x06, 0xe5, 0xe5, 0x25, 0x14, 0x1a, 0x12,
|
||||
0x05, 0x04, 0x02, 0x13, 0x16, 0xe7, 0xe5, 0x11,
|
||||
0xe5, 0x11, 0xe5, 0x06, 0xe5, 0x14, 0xe5, 0x11,
|
||||
0xe5, 0x03, 0xe5, 0x08, 0xe5, 0x06, 0x01, 0x02,
|
||||
0x02, 0x02, 0x01, 0x2c, 0xe5, 0x08, 0x01, 0x1d,
|
||||
0xe5, 0xe6, 0x01, 0x02, 0x01, 0x04, 0x09, 0x01,
|
||||
0x02, 0xe6, 0x03, 0x04, 0xe5, 0x02, 0x01, 0x02,
|
||||
0xe5, 0x02, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
|
||||
0x01, 0x02, 0xe5, 0x04, 0x01, 0x07, 0x05, 0xe5,
|
||||
0x01, 0x01, 0x02, 0xe5, 0x07, 0xe5, 0x01, 0x01,
|
||||
0xe5, 0x09, 0xe5, 0xe5, 0xe7, 0x01, 0x0e, 0x08,
|
||||
0x03, 0xe5, 0x04, 0x02, 0x06, 0x02, 0xe5, 0x04,
|
||||
0x0d, 0xe5, 0x07, 0xe5, 0x08, 0xe5, 0x07, 0x05,
|
||||
0x07, 0x02, 0x01, 0x01, 0xe8, 0xe5, 0x10, 0x01,
|
||||
0x05, 0x0c, 0x10, 0xe5, 0x01, 0x06, 0xe5, 0x08,
|
||||
0x08, 0xe6, 0x01, 0x02, 0x05, 0xe5, 0x04, 0xe5,
|
||||
0x01, 0x06, 0xe5, 0x01, 0xe5, 0x01, 0x10, 0x02,
|
||||
0x05, 0xe5, 0x01, 0x06, 0x02, 0x06, 0x02, 0x05,
|
||||
0x03, 0x07, 0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05,
|
||||
0x04, 0x03, 0x03, 0xe5, 0x04, 0x08, 0xe6, 0xe5,
|
||||
0xe6, 0x01, 0x0b, 0x05, 0x03, 0x09, 0x09, 0x09,
|
||||
0x06, 0x04, 0x05, 0x01, 0x01, 0x09, 0x05, 0x0a,
|
||||
0x01, 0x01, 0x02, 0x08, 0x02, 0xe5, 0xe6, 0x01,
|
||||
0x11, 0xe5, 0x31, 0x14, 0x10, 0x0a, 0x02, 0xe8,
|
||||
0x0c, 0x03, 0xe6, 0x02, 0x03, 0x05, 0x03, 0x05,
|
||||
0x03, 0x02, 0x02, 0x03, 0x02, 0x04, 0x03, 0x01,
|
||||
0x03, 0x03, 0x05, 0x0d, 0xe5, 0x06, 0x0b, 0x01,
|
||||
0x01, 0x11, 0x0c, 0x01, 0x04, 0x02, 0x01, 0x04,
|
||||
0x02, 0x09, 0x0b, 0x01, 0x07, 0x01, 0x07, 0x09,
|
||||
0x13, 0xe6, 0xe6, 0x0a, 0x02, 0x06, 0x02, 0x03,
|
||||
0x02, 0x02, 0x04, 0xe6, 0x01, 0x05, 0xe5, 0x01,
|
||||
0x03, 0x07, 0x03, 0x02, 0x02, 0x05, 0xe5, 0x01,
|
||||
0x03, 0x02, 0x02, 0x03, 0xe5, 0xe5, 0x01, 0x06,
|
||||
0x04, 0x01, 0x01, 0xe5, 0xe5, 0x01, 0x08, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x08, 0x08, 0xe5, 0x08,
|
||||
0x0a, 0xe5, 0x05, 0x09, 0x02, 0x09, 0x05, 0xe5,
|
||||
0x01, 0x07, 0xe5, 0xe6, 0x08, 0x05, 0x03, 0x05,
|
||||
0x03, 0x05, 0x05, 0x03, 0x03, 0x05, 0x03, 0x07,
|
||||
0x03, 0x05, 0x09, 0x03, 0x0a, 0x08, 0x0d, 0xe5,
|
||||
0x5e, 0x06, 0x07, 0x0b, 0xe8, 0x10, 0x01, 0x07,
|
||||
0x09, 0x01, 0x07, 0x01, 0x07, 0x0b, 0x09, 0x09,
|
||||
0x08, 0x03, 0x06, 0x0c, 0xe8, 0x09, 0x54, 0x01,
|
||||
0x0d, 0x02, 0x07, 0x01, 0x01, 0x15, 0xe5, 0x05,
|
||||
0xe7, 0x05, 0xe7, 0x07, 0xe5, 0x06, 0xe6, 0x08,
|
||||
0xe6, 0x05, 0xe7, 0x06, 0xe7, 0xe5, 0x02, 0xe7,
|
||||
0x05, 0xe7, 0x0a, 0x10, 0xe5, 0x07, 0x09, 0x33,
|
||||
0x06, 0x0b, 0x0f, 0xe7, 0x19, 0x05, 0x03, 0x02,
|
||||
0x02, 0x13, 0x0b, 0x09, 0x03, 0x05, 0x06, 0x02,
|
||||
0xe5, 0x07, 0x08, 0x02, 0xe5, 0x1b, 0xe6, 0x07,
|
||||
0xe5, 0x11, 0xe5, 0x01, 0x07, 0xe5, 0x06, 0xe6,
|
||||
0x07, 0xe5, 0xe5, 0xe5, 0x03, 0xe5, 0x02, 0x03,
|
||||
0xe6, 0x0a, 0xe5, 0x02, 0x0e, 0x09, 0xe5, 0xe6,
|
||||
0x04, 0xe8, 0x04, 0x09, 0xe5, 0xe6, 0x06, 0xe5,
|
||||
0xe6, 0x04, 0xe5, 0xe6, 0x04, 0xe5, 0xe7, 0xe6,
|
||||
0x01, 0x01, 0xe6, 0x03, 0xe8, 0x06, 0x01, 0x01,
|
||||
0x0e, 0x01, 0x03, 0x03, 0x01, 0x07, 0x01, 0x07,
|
||||
0x01, 0xe5, 0x05, 0x01, 0x09, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x01, 0x08, 0x08, 0x01, 0x0a, 0xe9,
|
||||
0x10, 0x01, 0x01, 0x05, 0x01, 0xe5, 0x05, 0x01,
|
||||
0xe6, 0x04, 0x01, 0xe6, 0x04, 0x01, 0x01, 0x02,
|
||||
0x03, 0xe5, 0xe5, 0xe5, 0x03, 0xe5, 0xe5, 0x06,
|
||||
0x01, 0x02, 0x04, 0x01, 0x07, 0x01, 0xe5, 0x08,
|
||||
0x01, 0xe6, 0x0e, 0xe5, 0x02, 0x0e, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0xe5, 0x0d, 0x09, 0xe5, 0x06,
|
||||
0x04, 0xe5, 0x05, 0x01, 0xe5, 0x0c, 0xe6, 0xe6,
|
||||
0x1e, 0x07, 0x15, 0x07, 0x09, 0xe5, 0x0d, 0xe5,
|
||||
0xe5, 0xe5, 0x01, 0x01, 0x09, 0x04, 0xe6, 0xe6,
|
||||
0x04, 0x02, 0x04, 0x01, 0x02, 0x09, 0x04, 0x01,
|
||||
0x02, 0x04, 0x01, 0x07, 0x01, 0x04, 0x02, 0x08,
|
||||
0x0b, 0x06, 0x0e, 0x10, 0xe5, 0xe6, 0x0b, 0x01,
|
||||
0x07, 0x01, 0x03, 0xe5, 0x01, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x02, 0x05, 0x09, 0x17, 0x04, 0x03,
|
||||
0x03, 0x09, 0xe7, 0xe5, 0x0d, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x04, 0x02, 0x01, 0x07, 0x01, 0x04,
|
||||
0x01, 0x0a, 0x07, 0x06, 0x01, 0x02, 0x0a, 0x13,
|
||||
0xe6, 0x0d, 0x03, 0x05, 0x09, 0x03, 0x05, 0x09,
|
||||
0x03, 0x03, 0x03, 0x02, 0x05, 0xe5, 0x02, 0x04,
|
||||
0xe5, 0x07, 0xe5, 0x01, 0x03, 0x02, 0x0d, 0x01,
|
||||
0x02, 0x0d, 0x02, 0x02, 0x03, 0x09, 0x02, 0x06,
|
||||
0x04, 0x04, 0x02, 0xe5, 0x04, 0x01, 0x05, 0x03,
|
||||
0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x08, 0x0c,
|
||||
0x06, 0x06, 0x02, 0x05, 0xe6, 0x06, 0xe6, 0x06,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0xe5, 0x03, 0xe5,
|
||||
0x01, 0xe5, 0xe5, 0xe5, 0x06, 0x09, 0x01, 0xe5,
|
||||
0x17, 0x03, 0x01, 0xe6, 0x09, 0x02, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0x01, 0xe6, 0x07, 0x11, 0xe5, 0xe5, 0x09, 0x02,
|
||||
0x0e, 0x0b, 0x04, 0x01, 0x03, 0x03, 0x09, 0x01,
|
||||
0x07, 0x04, 0x04, 0x02, 0xe5, 0xe6, 0x03, 0x07,
|
||||
0x18, 0xe5, 0x13, 0xe5, 0xe6, 0x0c, 0xe5, 0x03,
|
||||
0x03, 0xe5, 0x07, 0xe5, 0x02, 0x04, 0xe5, 0x07,
|
||||
0xe5, 0x0a, 0x03, 0xe5, 0x01, 0x01, 0x07, 0x01,
|
||||
0xe5, 0x03, 0xe5, 0x09, 0x01, 0x0a, 0x02, 0x03,
|
||||
0xe5, 0x0c, 0xe6, 0x06, 0xe6, 0x01, 0x04, 0xe6,
|
||||
0x06, 0xe7, 0xe5, 0x03, 0xe6, 0x01, 0x05, 0x02,
|
||||
0x09, 0x05, 0x03, 0x07, 0x01, 0x02, 0x06, 0x0a,
|
||||
0x03, 0xe5, 0xe6, 0xe5, 0x06, 0x1c, 0x1a, 0xe5,
|
||||
0x02, 0x05, 0x0a, 0x12, 0x02, 0x0c, 0xe5, 0x01,
|
||||
0x01, 0x1b, 0xe5, 0x04, 0x03, 0x01, 0x06, 0xe5,
|
||||
0x10, 0xe5, 0x01, 0xe5, 0x03, 0xe5, 0x12, 0xe5,
|
||||
0x06, 0xe5, 0x07, 0x01, 0x03, 0xe9, 0xe5, 0x17,
|
||||
0xe5, 0x08, 0xe5, 0x06, 0xe5, 0x08, 0xe5, 0x09,
|
||||
0xe5, 0x17, 0x03, 0x01, 0x0e, 0x01, 0x01, 0x02,
|
||||
0x02, 0x01, 0x04, 0xe5, 0x02, 0x04, 0xe5, 0x02,
|
||||
0x09, 0x09, 0x09, 0x04, 0xe5, 0x04, 0x01, 0xe5,
|
||||
0x05, 0x01, 0xe5, 0x05, 0x01, 0x08, 0xe5, 0x01,
|
||||
0xe5, 0x05, 0xe5, 0x07, 0xe5, 0x01, 0x01, 0xe5,
|
||||
0x01, 0x1b, 0x09, 0xe5, 0x07, 0x14, 0xe5, 0x05,
|
||||
0x01, 0xe5, 0x04, 0x02, 0xe5, 0x01, 0x06, 0x0d,
|
||||
0x02, 0x01, 0xe5, 0x02, 0xe5, 0xe5, 0x06, 0x01,
|
||||
0x05, 0xe5, 0x01, 0x05, 0x02, 0x10, 0xe5, 0xe6,
|
||||
0x04, 0x01, 0x01, 0x06, 0x01, 0x02, 0x0f, 0xe5,
|
||||
0x01, 0xe5, 0x02, 0xe5, 0x01, 0x08, 0x01, 0x06,
|
||||
0xe5, 0xe7, 0x01, 0x06, 0x02, 0x05, 0x01, 0x01,
|
||||
0x05, 0x03, 0x07, 0x01, 0x05, 0x01, 0x01, 0x05,
|
||||
0x0d, 0x01, 0x0f, 0x04, 0x04, 0x08, 0x01, 0x02,
|
||||
0x04, 0xe6, 0x01, 0xe6, 0x01, 0x0b, 0x09, 0x06,
|
||||
0x02, 0x09, 0x09, 0x0b, 0x05, 0x03, 0x09, 0x0a,
|
||||
0x02, 0x06, 0x08, 0x02, 0x02, 0xe6, 0xe5, 0x12,
|
||||
0xe5, 0x11, 0xe5, 0x1d, 0xe6, 0x14, 0x04, 0xe6,
|
||||
0x01, 0x0f, 0x03, 0xe6, 0x07, 0x05, 0x03, 0x02,
|
||||
0x02, 0x03, 0x05, 0x03, 0xe5, 0x03, 0x03, 0x02,
|
||||
0x02, 0x03, 0x02, 0x04, 0x03, 0xe5, 0x03, 0x03,
|
||||
0x05, 0x03, 0x08, 0xe5, 0x01, 0x12, 0xe5, 0xe5,
|
||||
0xe5, 0x07, 0x01, 0x07, 0xe5, 0x07, 0x01, 0x04,
|
||||
0x16, 0x08, 0x02, 0xe5, 0x04, 0x02, 0x01, 0x07,
|
||||
0x01, 0x07, 0xe5, 0x07, 0x09, 0xe5, 0x01, 0xe5,
|
||||
0x09, 0xe5, 0x01, 0x06, 0x02, 0x03, 0x02, 0x02,
|
||||
0x06, 0x02, 0x06, 0x02, 0x03, 0x07, 0x06, 0x02,
|
||||
0x03, 0x05, 0x03, 0xe5, 0xe5, 0x01, 0x04, 0x01,
|
||||
0x02, 0x05, 0xe5, 0x05, 0x01, 0xe5, 0xe5, 0x0a,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0x09, 0xe5,
|
||||
0x08, 0x0a, 0xe5, 0x08, 0x09, 0x05, 0x03, 0x06,
|
||||
0x02, 0x07, 0xe8, 0x08, 0x05, 0x03, 0x05, 0x03,
|
||||
0x05, 0x09, 0x03, 0x05, 0x05, 0x05, 0x03, 0x05,
|
||||
0x03, 0x05, 0x04, 0x09, 0x0a, 0x08, 0xe5, 0xe6,
|
||||
0x5b, 0x07, 0x17, 0xe6, 0x01, 0x0e, 0x09, 0x09,
|
||||
0x01, 0x07, 0x09, 0x0b, 0x01, 0x07, 0x01, 0x07,
|
||||
0x05, 0x03, 0x04, 0xe5, 0x01, 0x0e, 0xe5, 0xe6,
|
||||
0x1c, 0x1c, 0xe5, 0x1e, 0x04, 0x09, 0x0e, 0x01,
|
||||
0xe6, 0x08, 0x0b, 0xe5, 0x05, 0x01, 0xe5, 0x05,
|
||||
0x01, 0xe5, 0x07, 0xe5, 0x05, 0x01, 0xe5, 0x07,
|
||||
0xe7, 0x05, 0xe7, 0x05, 0x01, 0xe6, 0x04, 0x01,
|
||||
0xe6, 0x04, 0xe7, 0x06, 0x02, 0xe5, 0xe5, 0x0d,
|
||||
0xe5, 0x07, 0x29, 0x09, 0x09, 0x08, 0x09, 0x0e,
|
||||
0x03, 0x20, 0x09, 0x13, 0x05, 0x05, 0x03, 0x05,
|
||||
0x09, 0x09, 0xe5, 0x07, 0x09, 0xe6, 0x19, 0x02,
|
||||
0x01, 0x07, 0x01, 0x11, 0x01, 0x02, 0x06, 0xe6,
|
||||
0x06, 0xe6, 0x03, 0x02, 0x01, 0x07, 0x01, 0x03,
|
||||
0x03, 0xe6, 0x07, 0xe5, 0xe6, 0x11, 0x09, 0xe8,
|
||||
0x04, 0x01, 0xe6, 0x04, 0x09, 0xe8, 0x06, 0xe5,
|
||||
0xe6, 0x04, 0xe5, 0xe6, 0x04, 0xe8, 0x04, 0xe9,
|
||||
0x04, 0x01, 0xe5, 0x06, 0x03, 0xe5, 0x0b, 0xe5,
|
||||
0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
|
||||
0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x07, 0xe5, 0xe5,
|
||||
0x05, 0xe5, 0xe6, 0x04, 0x02, 0x06, 0x02, 0x01,
|
||||
0x14, 0xe9, 0x05, 0x0a, 0x01, 0xe5, 0x05, 0x01,
|
||||
0xe5, 0x05, 0x01, 0xe6, 0x04, 0x01, 0x01, 0x05,
|
||||
0x01, 0xe6, 0x01, 0x04, 0x01, 0x01, 0x05, 0x01,
|
||||
0xe6, 0x01, 0x02, 0x01, 0x01, 0x05, 0x01, 0x01,
|
||||
0x05, 0x01, 0x02, 0x07, 0xe8, 0x02, 0x05, 0x04,
|
||||
0x07, 0x01, 0xe5, 0x07, 0x03, 0x02, 0x02, 0x09,
|
||||
0x04, 0x01, 0x04, 0x04, 0xe5, 0x02, 0xe6, 0x02,
|
||||
0x02, 0x02, 0x03, 0x02, 0xe5, 0x01, 0x1a, 0xe5,
|
||||
0x1a, 0x02, 0x06, 0x0a, 0x02, 0x16, 0x08, 0xe5,
|
||||
0x06, 0x04, 0x02, 0x02, 0x0d, 0xe5, 0xe5, 0x01,
|
||||
0xe6, 0x12, 0x04, 0x1b, 0x04, 0x05, 0x0a, 0x02,
|
||||
0x02, 0x07, 0x0b, 0x15, 0xe5, 0x01, 0xe5, 0x0b,
|
||||
0xe6, 0x03, 0x02, 0xe6, 0x03, 0x02, 0xe6, 0x03,
|
||||
0x02, 0xe7, 0x05, 0xe6, 0x02, 0x08, 0x09, 0x06,
|
||||
0xe6, 0x01, 0x02, 0x03, 0x09, 0xe5, 0x01, 0x09,
|
||||
0x04, 0x09, 0x03, 0x09, 0x09, 0x09, 0x09, 0x03,
|
||||
0x03, 0x01, 0xe5, 0x07, 0x0b, 0x19, 0x0c, 0xe7,
|
||||
0x08, 0x08, 0x06, 0xe6, 0x0c, 0x01, 0xe6, 0x04,
|
||||
0x0a, 0xe5, 0x05, 0xe5, 0x03, 0x02, 0x0a, 0x03,
|
||||
0x05, 0x03, 0x05, 0x09, 0x04, 0x10, 0x13, 0x06,
|
||||
0x02, 0x09, 0x02, 0x03, 0x04, 0x04, 0x04, 0x09,
|
||||
0x0f, 0x12, 0x02, 0x01, 0x04, 0x15, 0x02, 0x08,
|
||||
0x02, 0x04, 0x0e, 0x08, 0x05, 0x28, 0x04, 0x01,
|
||||
0x03, 0x19, 0x20, 0xe6, 0x08, 0x06, 0x10, 0x19,
|
||||
0x01, 0x06, 0x01, 0x1d, 0x15, 0x02, 0x0a, 0x08,
|
||||
0x06, 0x01, 0xe6, 0x06, 0x07, 0x0b, 0x02, 0xe7,
|
||||
0xe5, 0x05, 0x09, 0x01, 0x11, 0x04, 0xe5, 0x02,
|
||||
0x04, 0xe5, 0x04, 0x01, 0x08, 0x07, 0x08, 0xe5,
|
||||
0x05, 0x16, 0x01, 0x02, 0x19, 0x10, 0x01, 0x0a,
|
||||
0x08, 0x0d, 0x0a, 0x0b, 0x0a, 0x09, 0x01, 0x01,
|
||||
0x19, 0x0e, 0x07, 0x04, 0xe5, 0x1a, 0x28, 0x02,
|
||||
0x01, 0x26, 0xe5, 0x04, 0x11, 0x02, 0xe5, 0x01,
|
||||
0xe5, 0xe5, 0x08, 0x02, 0xe5, 0x07, 0xe5, 0x13,
|
||||
0x01, 0xe5, 0xe9, 0xe5, 0x1b, 0xe5, 0x12, 0xe5,
|
||||
0x03, 0x01, 0x02, 0x03, 0x01, 0xe5, 0x01, 0xe6,
|
||||
0x03, 0x01, 0xe5, 0x0c, 0x11, 0x01, 0x01, 0xe5,
|
||||
0xe5, 0xe5, 0x01, 0x01, 0x12, 0x01, 0x09, 0x02,
|
||||
0x01, 0xe5, 0xe5, 0xe7, 0x01, 0xe5, 0x03, 0x08,
|
||||
0x06, 0x01, 0xe5, 0x01, 0x01, 0x04, 0x03, 0x16,
|
||||
0x01, 0x02, 0x01, 0xe5, 0xe6, 0x01, 0x02, 0x11,
|
||||
0xe5, 0xe5, 0xe5, 0x06, 0x06, 0xe5, 0xe5, 0xe5,
|
||||
0x02, 0xe5, 0x05, 0x07, 0x0b, 0x07, 0x19, 0xe5,
|
||||
0x05, 0x02, 0xe6, 0xe6, 0xe5, 0x01, 0x03, 0x02,
|
||||
0x16, 0x09, 0x01, 0x01, 0x02, 0x02, 0x09, 0x09,
|
||||
0x01, 0x01, 0xe5, 0x03, 0x23, 0xe5, 0x01, 0xe5,
|
||||
0x01, 0x06, 0x02, 0x0e, 0x05, 0x03, 0x0c, 0x01,
|
||||
0x02, 0x01, 0x07, 0x03, 0x05, 0x01, 0x01, 0x05,
|
||||
0x03, 0x1d, 0xe5, 0x02, 0x01, 0x02, 0x14, 0x01,
|
||||
0x09, 0x07, 0x04, 0x01, 0x0e, 0x04, 0x04, 0x03,
|
||||
0xe5, 0xe5, 0xe6, 0x03, 0x19, 0x02, 0x02, 0x03,
|
||||
0x17, 0x01, 0x07, 0x09, 0x04, 0x01, 0xe5, 0x0c,
|
||||
0x09, 0x01, 0x04, 0x01, 0xe5, 0x25, 0x01, 0xe5,
|
||||
0x03, 0x03, 0x26, 0xe5, 0xe5, 0x05, 0x0c, 0x08,
|
||||
0x0a, 0xe5, 0x1b, 0x02, 0xe6, 0x09, 0x01, 0x22,
|
||||
0x02, 0x01, 0x13, 0x01, 0x04, 0x02, 0xe5, 0x11,
|
||||
0xe5, 0x12, 0xe5, 0xe6, 0x07, 0x05, 0x09, 0x09,
|
||||
0x09, 0x03, 0x05, 0x0b, 0x03, 0x05, 0x09, 0x09,
|
||||
0x09, 0x06, 0x06, 0x03, 0xe5, 0x29, 0x05, 0x03,
|
||||
0x05, 0x0f, 0x05, 0x20, 0x0b, 0xe5, 0x27, 0x09,
|
||||
0x14, 0x07, 0x2b, 0xe7, 0x15, 0x02, 0x16, 0x10,
|
||||
0x01, 0x04, 0x02, 0x09, 0x01, 0x07, 0x01, 0x18,
|
||||
0x03, 0x19, 0xe5, 0x0c, 0x02, 0x01, 0x01, 0x01,
|
||||
0x06, 0xe5, 0x03, 0x02, 0x01, 0xe5, 0x07, 0xe6,
|
||||
0x04, 0x01, 0xe5, 0x04, 0xe5, 0xe6, 0x16, 0x03,
|
||||
0xe5, 0x17, 0x22, 0x0b, 0x02, 0x2e, 0xe5, 0x01,
|
||||
0x15, 0xe5, 0x01, 0x03, 0xe5, 0xe5, 0x05, 0x02,
|
||||
0xe5, 0xe5, 0x04, 0xe5, 0x07, 0x0a, 0xe7, 0xe5,
|
||||
0x04, 0xe5, 0x06, 0xe6, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x06, 0x03, 0x04, 0x14, 0x03, 0x23, 0x01, 0x04,
|
||||
0x0c, 0x01, 0xe6, 0x04, 0x01, 0x1b, 0xe5, 0x18,
|
||||
0x06, 0x09, 0xe5, 0xe5, 0x0f, 0x02, 0x01, 0x06,
|
||||
0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x18, 0x02,
|
||||
0x19, 0x04, 0xe6, 0x05, 0x01, 0xe5, 0x09, 0x0a,
|
||||
0x09, 0x09, 0x07, 0x01, 0x1b, 0x01, 0x01, 0x19,
|
||||
0x04, 0x08, 0xe5, 0x01, 0x04, 0x09, 0x01, 0x07,
|
||||
0x0b, 0x01, 0x05, 0x21, 0x01, 0x01, 0xe5, 0x0f,
|
||||
0x19, 0xe5, 0xe5, 0x11, 0x01, 0xe6, 0x04, 0x01,
|
||||
0xe5, 0xe5, 0x03, 0xe5, 0xe5, 0xe5, 0x1d, 0x01,
|
||||
0xe7, 0x05, 0x0a, 0x01, 0x02, 0x04, 0x01, 0x07,
|
||||
0x01, 0xe5, 0x02, 0x01, 0xe5, 0xe6, 0xe5, 0x03,
|
||||
0x01, 0x01, 0x02, 0x01, 0x02, 0x01, 0xe5, 0x01,
|
||||
0x03, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01, 0x07,
|
||||
0x01, 0x0b, 0x01, 0xe5, 0x08, 0x20, 0x09, 0x02,
|
||||
0xe6, 0xe6, 0x05, 0x03, 0x0e, 0x0a, 0xe5, 0x01,
|
||||
0x16, 0xe7, 0x1d, 0x08, 0x07, 0x04, 0x01, 0x03,
|
||||
0x02, 0x05, 0x02, 0x06, 0x05, 0x0b, 0x07, 0x07,
|
||||
0x08, 0xe5, 0x01, 0xe5, 0x11, 0x16, 0x0f, 0xe5,
|
||||
0x03, 0xe5, 0xe5, 0x01, 0x04, 0x03, 0x04, 0x05,
|
||||
0x06, 0x19, 0xe6, 0xe7, 0x05, 0xe5, 0x05, 0x09,
|
||||
0x03, 0x09, 0x04, 0x02, 0x01, 0x02, 0x01, 0x10,
|
||||
0x02, 0x01, 0x04, 0x01, 0x03, 0x20, 0x02, 0xe6,
|
||||
0x10, 0x18, 0xe5, 0x03, 0x04, 0x01, 0x05, 0x01,
|
||||
0x09, 0x04, 0x14, 0x16, 0xe5, 0x01, 0xe5, 0x12,
|
||||
0x0b, 0x04, 0x07, 0x0e, 0x02, 0xe5, 0x02, 0x06,
|
||||
0x05, 0x26, 0xe6, 0xe7, 0x12, 0xe5, 0x04, 0x0f,
|
||||
0x03, 0x0b, 0x04, 0x0e, 0x0f, 0x03, 0x18, 0x01,
|
||||
0xe5, 0x1a, 0xe5, 0x10, 0x05, 0x0a, 0x11, 0x14,
|
||||
0x14, 0xe5, 0xe5, 0x16, 0xe6, 0x02, 0x02, 0xe7,
|
||||
0x02, 0x03, 0xe6, 0x06, 0xe6, 0xe6, 0x03, 0xe5,
|
||||
0x08, 0xe7, 0xe5, 0x29, 0x03, 0x02, 0x10, 0x06,
|
||||
0x03, 0x05, 0x03, 0x01, 0x02, 0x0a, 0x03, 0x02,
|
||||
0x07, 0xe5, 0x04, 0x0a, 0x20, 0x01, 0x01, 0xe5,
|
||||
0x14, 0x17, 0x02, 0xe5, 0x19, 0x01, 0xe5, 0xe5,
|
||||
0xe5, 0x02, 0x03, 0x06, 0x0d, 0x07, 0xe6, 0x01,
|
||||
0x2e, 0x03, 0x02, 0x01, 0x03, 0x02, 0x01, 0x0b,
|
||||
0xe5, 0x09, 0x01, 0x1f, 0x01, 0xe6, 0x12, 0x0c,
|
||||
0x0e, 0x17, 0x05, 0x0d, 0x09, 0x14, 0x02, 0xe5,
|
||||
0xe5, 0x01, 0x0b, 0xe5, 0xe6, 0x05, 0x02, 0xe5,
|
||||
0x10, 0xe5, 0x01, 0x0e, 0xe8, 0x05, 0xe5, 0xe6,
|
||||
0xe5, 0x01, 0xe5, 0x1d, 0x02, 0x01, 0xe5, 0x01,
|
||||
0x0e, 0x01, 0xe5, 0x04, 0x03, 0x01, 0x0c, 0x03,
|
||||
0xe5, 0x01, 0x0b, 0xe5, 0x01, 0x01, 0xe5, 0x05,
|
||||
0xe5, 0x03, 0x03, 0x1b, 0x01, 0x01, 0xe5, 0xe5,
|
||||
0xe5, 0x03, 0x15, 0x12, 0x07, 0x0b, 0x01, 0x04,
|
||||
0xe5, 0x03, 0x06, 0x1a, 0x01, 0x02, 0x01, 0xe5,
|
||||
0xe6, 0xe7, 0xe5, 0x16, 0x10, 0x01, 0x07, 0x05,
|
||||
0xe5, 0x03, 0x01, 0x04, 0xe5, 0xe5, 0x01, 0x06,
|
||||
0x1a, 0xe5, 0x04, 0x02, 0x01, 0x01, 0xe5, 0xe5,
|
||||
0x18, 0x09, 0x04, 0x04, 0x04, 0x04, 0x08, 0x0c,
|
||||
0x04, 0x23, 0xe6, 0xe7, 0xe5, 0x01, 0x25, 0x04,
|
||||
0x04, 0x03, 0x07, 0x03, 0x01, 0x02, 0x04, 0x04,
|
||||
0xe5, 0x02, 0x1d, 0xe5, 0xe6, 0x01, 0x02, 0x18,
|
||||
0x02, 0x06, 0x02, 0x02, 0x01, 0x04, 0x02, 0x06,
|
||||
0x01, 0x02, 0x01, 0x03, 0xe5, 0x08, 0xe7, 0x20,
|
||||
0x06, 0xe5, 0x1a, 0x01, 0xe5, 0x05, 0xe7, 0xe5,
|
||||
0x03, 0x01, 0xe7, 0x02, 0xe7, 0x03, 0x01, 0x04,
|
||||
0x02, 0x03, 0xe5, 0xe5, 0x01, 0x25, 0x01, 0xe5,
|
||||
0x04, 0x14, 0x01, 0xe5, 0xe6, 0x02, 0x01, 0x09,
|
||||
0x07, 0x01, 0x0c, 0x01, 0xe5, 0x02, 0x01, 0x02,
|
||||
0x25, 0x01, 0x02, 0x01, 0x18, 0xe5, 0x07, 0xe5,
|
||||
0x11, 0xe5, 0x13, 0xe5, 0x01, 0x27, 0x02, 0xe6,
|
||||
0x0d, 0x09, 0xe6, 0x06, 0xe6, 0x06, 0x09, 0xe5,
|
||||
0x04, 0x04, 0x09, 0xe5, 0x01, 0x05, 0x02, 0x01,
|
||||
0x01, 0x02, 0x09, 0x0d, 0xe9, 0x01, 0x19, 0x09,
|
||||
0x09, 0x09, 0xe5, 0x01, 0x11, 0x2a, 0x02, 0x39,
|
||||
0x01, 0x13, 0x2b, 0x02, 0x17, 0x01, 0xe7, 0x06,
|
||||
0x01, 0x09, 0x06, 0xe7, 0x02, 0x02, 0x01, 0x04,
|
||||
0x05, 0xe6, 0xe5, 0xe6, 0xe5, 0x08, 0x18, 0xe8,
|
||||
0x16, 0x01, 0xe6, 0x08, 0x09, 0x04, 0x02, 0xe6,
|
||||
0x01, 0x04, 0x01, 0xe5, 0x04, 0x02, 0xe6, 0x04,
|
||||
0x01, 0xe5, 0x05, 0x02, 0x17, 0xe8, 0x15, 0x04,
|
||||
0x0c, 0x0e, 0x09, 0x01, 0x04, 0x04, 0x01, 0x05,
|
||||
0x01, 0x06, 0x02, 0x18, 0xe6, 0xe5, 0x14, 0xe5,
|
||||
0x05, 0xe6, 0x06, 0xe6, 0x08, 0xe5, 0x01, 0xe5,
|
||||
0x02, 0xe5, 0x02, 0x01, 0x04, 0xe5, 0x02, 0x04,
|
||||
0xe5, 0xe5, 0xe5, 0x03, 0xe5, 0xe5, 0x06, 0xe5,
|
||||
0x07, 0xe5, 0x0a, 0x17, 0x01, 0xe5, 0x03, 0x09,
|
||||
0x01, 0x01, 0x09, 0xe5, 0x07, 0x01, 0xe6, 0x06,
|
||||
0xe5, 0x11, 0x18, 0xe5, 0x01, 0x17, 0x01, 0x03,
|
||||
0x02, 0x06, 0x02, 0xe5, 0xe5, 0x08, 0x06, 0x02,
|
||||
0x01, 0x06, 0x02, 0xe5, 0x04, 0x09, 0xe5, 0x19,
|
||||
0xe8, 0x19, 0x03, 0xe5, 0x07, 0xe5, 0xe5, 0xe5,
|
||||
0x08, 0xe5, 0x02, 0x03, 0x02, 0x04, 0x04, 0x04,
|
||||
0x09, 0x04, 0x17, 0xe9, 0x1b, 0xe5, 0x07, 0xe5,
|
||||
0x02, 0x01, 0x02, 0x06, 0x02, 0x06, 0x02, 0x03,
|
||||
0x04, 0x02, 0x07, 0x03, 0x02, 0x1a, 0xe9, 0x09,
|
||||
0x09, 0x09, 0x08, 0x05, 0xe5, 0x07, 0x0c, 0x05,
|
||||
0x02, 0x06, 0x24, 0x03, 0x0b, 0x05, 0x01, 0x06,
|
||||
0xe5, 0xe5, 0x06, 0xe6, 0xe5, 0x04, 0x01, 0xe5,
|
||||
0x05, 0x01, 0x04, 0x04, 0xe7, 0x01, 0x03, 0x01,
|
||||
0xe6, 0x04, 0x01, 0x07, 0x01, 0xe5, 0xe5, 0x03,
|
||||
0x01, 0x0a, 0xe8, 0x0e, 0xe5, 0x09, 0x07, 0xe5,
|
||||
0x05, 0x08, 0xe5, 0xe5, 0x02, 0x08, 0xe6, 0xe5,
|
||||
0xe6, 0xe6, 0x01, 0x04, 0xe5, 0x0c, 0x0a, 0x06,
|
||||
0x02, 0x01, 0xe7, 0x13, 0x07, 0xe5, 0x01, 0x01,
|
||||
0x06, 0x0c, 0xe5, 0x03, 0x03, 0x03, 0x05, 0x12,
|
||||
0x1a, 0x01, 0x02, 0x0d, 0x01, 0x03, 0x09, 0x02,
|
||||
0x04, 0x01, 0xe5, 0xe5, 0x08, 0x09, 0xe5, 0x05,
|
||||
0x03, 0x01, 0x07, 0x01, 0x0d, 0x0f, 0xe5, 0x03,
|
||||
0x03, 0x03, 0xe5, 0x18, 0x0e, 0x12, 0xe7, 0x06,
|
||||
0x01, 0x09, 0x03, 0x19, 0x05, 0x02, 0xe5, 0x06,
|
||||
0x09, 0x09, 0xe5, 0x07, 0x02, 0x01, 0x05, 0x01,
|
||||
0x0b, 0x01, 0x07, 0x03, 0x01, 0x03, 0x01, 0x0f,
|
||||
0x10, 0x02, 0xe5, 0xe8, 0x08, 0x01, 0x06, 0x12,
|
||||
0x06, 0x09, 0x03, 0xe5, 0x01, 0x03, 0x03, 0x03,
|
||||
0xe6, 0x08, 0x06, 0x10, 0x01, 0x07, 0xe5, 0xe8,
|
||||
0xe5, 0x0c, 0x0f, 0x0b, 0x02, 0xe5, 0x04, 0x04,
|
||||
0x03, 0xe5, 0x02, 0x03, 0x02, 0x02, 0x01, 0x04,
|
||||
0x06, 0x0b, 0x10, 0x01, 0xe5, 0xe5, 0x11, 0x01,
|
||||
0x06, 0x14, 0x08, 0x02, 0x01, 0xe5, 0x03, 0xe5,
|
||||
0xe5, 0x01, 0x02, 0x04, 0x02, 0x02, 0x01, 0x1f,
|
||||
0x03, 0xe5, 0x0a, 0x09, 0x09, 0xe7, 0x02, 0x0d,
|
||||
0xe6, 0x06, 0xe6, 0x03, 0x05, 0x04, 0x27, 0xe7,
|
||||
0xe5, 0xe5, 0x06, 0x1a, 0x03, 0x0e, 0x07, 0x01,
|
||||
0x0a, 0x23, 0x0b, 0xe7, 0xe6, 0x11, 0x02, 0x0a,
|
||||
0xe5, 0xe5, 0x01, 0x02, 0x01, 0x07, 0x03, 0xe5,
|
||||
0x05, 0x0d, 0x02, 0x02, 0x05, 0x1b, 0x02, 0x01,
|
||||
0x03, 0x0f, 0x09, 0xe5, 0x06, 0x05, 0xe5, 0xe7,
|
||||
0x01, 0x01, 0xe6, 0xe5, 0x04, 0xe7, 0x05, 0x02,
|
||||
0xe5, 0x06, 0xe5, 0x04, 0x1d, 0x02, 0x17, 0x0d,
|
||||
0x06, 0x02, 0x06, 0x16, 0x09, 0x24, 0x01, 0x01,
|
||||
0x11, 0xe5, 0x08, 0x01, 0x0d, 0xe5, 0x04, 0x02,
|
||||
0xe5, 0x0b, 0x08, 0x05, 0x02, 0xe6, 0x06, 0xe5,
|
||||
0x13, 0x01, 0xe6, 0xe5, 0x01, 0x01, 0x0e, 0xe5,
|
||||
0x08, 0xe5, 0xe6, 0x03, 0xe5, 0x0f, 0x15, 0x06,
|
||||
0xe6, 0x09, 0x11, 0x01, 0x01, 0x02, 0xe6, 0x03,
|
||||
0x15, 0x08, 0xe5, 0x09, 0x05, 0x06, 0x01, 0x04,
|
||||
0x11, 0x01, 0x02, 0x15, 0x01, 0x02, 0x01, 0xe5,
|
||||
0xe6, 0x01, 0x02, 0x17, 0x06, 0x03, 0x01, 0xe5,
|
||||
0x12, 0x1a, 0x18, 0xe5, 0x04, 0x03, 0xe5, 0xe6,
|
||||
0xe5, 0x18, 0x06, 0x02, 0x03, 0xe5, 0x08, 0x01,
|
||||
0x05, 0x03, 0x04, 0x01, 0x01, 0x06, 0x02, 0xe5,
|
||||
0xe6, 0x02, 0x01, 0x1a, 0xe5, 0xe5, 0xe5, 0x01,
|
||||
0x1e, 0x03, 0x02, 0xe6, 0x01, 0x01, 0x01, 0x02,
|
||||
0xe5, 0xe5, 0xe5, 0x06, 0x04, 0x04, 0x08, 0xe5,
|
||||
0xe6, 0x01, 0x02, 0x15, 0x02, 0xe5, 0x03, 0xe5,
|
||||
0x01, 0x18, 0x07, 0x04, 0x01, 0x0a, 0x01, 0x09,
|
||||
0x01, 0x02, 0x01, 0x01, 0x08, 0x01, 0x01, 0x0c,
|
||||
0x12, 0x02, 0xe8, 0x1b, 0xe6, 0x01, 0x03, 0xe5,
|
||||
0xe5, 0x0b, 0x01, 0x09, 0x04, 0x01, 0x01, 0xe5,
|
||||
0x08, 0x01, 0xe5, 0x22, 0x01, 0xe5, 0x07, 0x10,
|
||||
0x01, 0xe5, 0x01, 0x03, 0x01, 0x02, 0x07, 0x02,
|
||||
0x06, 0xe5, 0x08, 0xe5, 0x01, 0x06, 0xe5, 0x07,
|
||||
0x09, 0x02, 0x10, 0x04, 0x0a, 0x01, 0x0d, 0xe5,
|
||||
0x01, 0x05, 0xe5, 0x15, 0x0b, 0xe5, 0x04, 0x02,
|
||||
0xe5, 0x07, 0xe6, 0x1a, 0x01, 0xe8, 0x06, 0x05,
|
||||
0x09, 0xe6, 0xe5, 0x04, 0xe5, 0x02, 0x01, 0x02,
|
||||
0x02, 0x06, 0x02, 0xe5, 0x01, 0x04, 0x09, 0x09,
|
||||
0xe5, 0x02, 0x01, 0x02, 0x09, 0x0d, 0x01, 0x02,
|
||||
0x02, 0x19, 0x03, 0x04, 0xe5, 0x02, 0x09, 0x08,
|
||||
0xe5, 0x06, 0x09, 0x03, 0x09, 0x1f, 0x1f, 0x05,
|
||||
0x03, 0x09, 0x09, 0x13, 0x09, 0x1e, 0x01, 0x01,
|
||||
0x17, 0x01, 0xe5, 0xe5, 0x05, 0xe7, 0x02, 0x02,
|
||||
0x07, 0x01, 0x04, 0x09, 0x01, 0x01, 0xe5, 0x03,
|
||||
0x04, 0x02, 0x08, 0x07, 0x01, 0x0e, 0xe5, 0xe6,
|
||||
0x15, 0xe5, 0xe7, 0x01, 0x02, 0x02, 0xe5, 0x01,
|
||||
0x02, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x09, 0x01,
|
||||
0x05, 0x02, 0xe5, 0xe5, 0x01, 0xe5, 0xe6, 0x05,
|
||||
0x02, 0x06, 0x01, 0xe5, 0x0c, 0x01, 0x01, 0x08,
|
||||
0x0b, 0x02, 0x0b, 0xe5, 0x05, 0x01, 0x09, 0x04,
|
||||
0x06, 0x07, 0x09, 0x09, 0x09, 0x01, 0x10, 0x01,
|
||||
0x15, 0xe6, 0x04, 0xe8, 0x04, 0xe8, 0xe5, 0x04,
|
||||
0xe6, 0xe5, 0x03, 0xe5, 0x0a, 0x01, 0x07, 0x01,
|
||||
0x01, 0x05, 0x03, 0x05, 0xe6, 0xe5, 0x04, 0xe5,
|
||||
0x06, 0xe5, 0x01, 0x1a, 0x08, 0x09, 0xe5, 0x05,
|
||||
0x01, 0xe5, 0x09, 0x07, 0x01, 0x07, 0x0b, 0x1b,
|
||||
0xe5, 0x19, 0x02, 0x02, 0xe5, 0x05, 0x01, 0xe5,
|
||||
0xe5, 0x06, 0x01, 0xe5, 0x02, 0x01, 0x0b, 0xe5,
|
||||
0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0x19, 0x01,
|
||||
0x01, 0xe5, 0x15, 0x06, 0xe5, 0x02, 0x03, 0x01,
|
||||
0x01, 0x01, 0xe5, 0x07, 0x08, 0x02, 0x07, 0x09,
|
||||
0x09, 0x1b, 0xe7, 0x16, 0x04, 0xe5, 0xe7, 0x03,
|
||||
0x01, 0xe7, 0xe6, 0x05, 0x01, 0xe5, 0x02, 0x09,
|
||||
0x01, 0x02, 0x04, 0x04, 0x0b, 0x1a, 0x01, 0xe5,
|
||||
0x34, 0x01, 0x03, 0x04, 0x01, 0xe6, 0x01, 0xe5,
|
||||
0x03, 0xe5, 0x02, 0x01, 0x23, 0x01, 0x01, 0xe5,
|
||||
0x10, 0x01, 0x07, 0x01, 0xe5, 0x05, 0x01, 0x06,
|
||||
0xe5, 0xe6, 0x05, 0x01, 0x04, 0xe5, 0x02, 0x01,
|
||||
0x07, 0x01, 0x02, 0xe5, 0x02, 0x01, 0xe5, 0xe5,
|
||||
0x03, 0x01, 0xe6, 0x04, 0x01, 0x0a, 0x03, 0x16,
|
||||
0x02, 0xe5, 0x07, 0x06, 0x02, 0xe5, 0x04, 0x02,
|
||||
0xe5, 0x02, 0x08, 0x01, 0x03, 0x01, 0xe5, 0x08,
|
||||
0x02, 0x05, 0xe5, 0x01, 0x0a, 0x09, 0x01, 0x01,
|
||||
0xe5, 0x15, 0x01, 0x05, 0x0c, 0x09, 0xe5, 0xe5,
|
||||
0x01, 0x03, 0x06, 0x02, 0xe5, 0xe5, 0x02, 0xe5,
|
||||
0x01, 0x03, 0x01, 0x03, 0x08, 0x09, 0x06, 0xe5,
|
||||
0xe7, 0x04, 0x1d, 0x01, 0x07, 0x0a, 0xe5, 0x03,
|
||||
0xe5, 0x05, 0x03, 0x05, 0xe5, 0x01, 0x0c, 0x18,
|
||||
0xe9, 0x17, 0x05, 0x0a, 0x05, 0x09, 0x06, 0x06,
|
||||
0x04, 0x07, 0xe6, 0xe5, 0x0e, 0x0b, 0x05, 0xe5,
|
||||
0xe5, 0x15, 0xe5, 0x07, 0x0e, 0x01, 0x01, 0x0b,
|
||||
0x04, 0xe5, 0x02, 0x01, 0x05, 0xe6, 0xe5, 0x15,
|
||||
0x09, 0x02, 0x03, 0xe7, 0x17, 0x12, 0x0d, 0x03,
|
||||
0x0a, 0x09, 0x01, 0xe5, 0x02, 0x01, 0x1b, 0x01,
|
||||
0xe5, 0xe5, 0x11, 0x0d, 0x0a, 0xe6, 0x05, 0xe5,
|
||||
0x02, 0x05, 0xe5, 0x09, 0x01, 0x03, 0x06, 0x04,
|
||||
0x1b, 0x01, 0xe5, 0xe5, 0x1a, 0x0a, 0x0b, 0x01,
|
||||
0xe5, 0x05, 0x02, 0xe5, 0x04, 0xe6, 0x08, 0x09,
|
||||
0x14, 0x08, 0xe5, 0x01, 0x06, 0x11, 0x0c, 0x01,
|
||||
0x11, 0x04, 0xe5, 0x09, 0x05, 0x08, 0x1f, 0xe5,
|
||||
0xe7, 0x0a, 0x06, 0x03, 0x02, 0x06, 0x1e, 0x09,
|
||||
0x07, 0x0c, 0x04, 0x09, 0x0d, 0x02, 0xe5, 0x01,
|
||||
0x06, 0x09, 0x05, 0x03, 0x04, 0x06, 0x02, 0x10,
|
||||
0x06, 0x08, 0x03, 0x02, 0x01, 0x01, 0x07, 0x12,
|
||||
0x04, 0x04, 0x03, 0x18, 0x0d, 0x02, 0x0d, 0x04,
|
||||
0x05, 0x02, 0x03, 0x03, 0x05, 0x03, 0x05, 0x11,
|
||||
0x09, 0xe5, 0xe5, 0x1e, 0x05, 0x03, 0x01, 0x17,
|
||||
0x06, 0x09, 0x05, 0x02, 0xe5, 0x12, 0x07, 0x01,
|
||||
0x03, 0x06, 0x23, 0x06, 0x04, 0x0b, 0x10, 0x01,
|
||||
0x08, 0x11, 0x02, 0x02, 0xe5, 0xe6, 0x07, 0x07,
|
||||
0x14, 0x08, 0x06, 0x18, 0x09, 0x09, 0x09, 0x0e,
|
||||
0x02, 0xe6, 0x0a, 0x09, 0x09, 0x02, 0xe5, 0x1d,
|
||||
0xe5, 0x01, 0x01, 0x04, 0xe5, 0x24, 0xe6, 0xe9,
|
||||
0x01, 0x01, 0x08, 0x09, 0xe6, 0x06, 0xe6, 0xe5,
|
||||
0x1e, 0x02, 0x01, 0xe5, 0x2a, 0x01, 0x01, 0xe5,
|
||||
0xe5, 0x03, 0x08, 0x06, 0x01, 0x0a, 0x2c, 0xe5,
|
||||
0x26, 0x02, 0xe5, 0xe6, 0x01, 0x0a, 0x06, 0xe5,
|
||||
0x02, 0x04, 0x02, 0x01, 0x27, 0x06, 0xe5, 0x02,
|
||||
0x1c, 0x02, 0x01, 0xe6, 0xe6, 0x0c, 0x09, 0x01,
|
||||
0x02, 0x02, 0x01, 0x01, 0x03, 0x02, 0xe5, 0xe5,
|
||||
0x06, 0x01, 0x15, 0x01, 0xe5, 0xe5, 0xe5, 0x05,
|
||||
0x02, 0x19, 0xe6, 0xe7, 0x01, 0x0a, 0x03, 0x05,
|
||||
0x01, 0x02, 0x01, 0x01, 0xe5, 0xe5, 0xe5, 0x03,
|
||||
0xe5, 0xe5, 0xe5, 0x04, 0x01, 0x01, 0x16, 0x08,
|
||||
0x02, 0x01, 0x15, 0x02, 0x01, 0xe5, 0x02, 0xe5,
|
||||
0x03, 0xe5, 0x05, 0x0e, 0x04, 0x01, 0x03, 0xe6,
|
||||
0xe5, 0xe5, 0x06, 0x01, 0x15, 0x02, 0x0b, 0x1a,
|
||||
0x02, 0xe5, 0xe6, 0x05, 0x06, 0x0b, 0x07, 0x05,
|
||||
0xe5, 0x01, 0x01, 0x07, 0x01, 0x18, 0xe6, 0x07,
|
||||
0xe6, 0x18, 0x01, 0xe6, 0xe6, 0x12, 0x08, 0x0a,
|
||||
0x02, 0x25, 0x14, 0xe5, 0x0c, 0x02, 0x03, 0x02,
|
||||
0x0a, 0x09, 0x01, 0x11, 0xe5, 0x31, 0x09, 0xe5,
|
||||
0x12, 0x02, 0xe5, 0x09, 0x03, 0x05, 0xe5, 0x01,
|
||||
0x06, 0x02, 0x02, 0x06, 0x09, 0x0b, 0x09, 0x04,
|
||||
0x01, 0x02, 0x03, 0x05, 0x09, 0x0d, 0xe9, 0x01,
|
||||
0x12, 0x09, 0xe5, 0x2e, 0x03, 0x26, 0xe5, 0xe5,
|
||||
0x1e, 0x31, 0x2b, 0xe5, 0xe5, 0x0a, 0x01, 0x09,
|
||||
0x04, 0x02, 0x06, 0x1f, 0x07, 0x01, 0x0e, 0x1a,
|
||||
0x01, 0x0d, 0x01, 0xe5, 0x04, 0xe5, 0x01, 0xe5,
|
||||
0x07, 0x05, 0x03, 0x19, 0x06, 0x07, 0xe5, 0x04,
|
||||
0x02, 0xe5, 0x17, 0x02, 0x0c, 0x0c, 0x06, 0x3e,
|
||||
0x1a, 0x01, 0x01, 0x13, 0xe5, 0xe6, 0x04, 0xe6,
|
||||
0x06, 0xe6, 0x06, 0xe6, 0x08, 0xe5, 0x09, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe6, 0x06, 0xe5, 0x07, 0xe5,
|
||||
0x06, 0x01, 0xe6, 0x13, 0x05, 0x04, 0x04, 0xe5,
|
||||
0x02, 0x01, 0x02, 0x03, 0xe5, 0x18, 0x0a, 0xe5,
|
||||
0x04, 0x1a, 0xe5, 0xe6, 0x15, 0x07, 0x01, 0x09,
|
||||
0xe5, 0x07, 0x18, 0x11, 0x1b, 0xe5, 0xe5, 0x12,
|
||||
0x01, 0xe5, 0x02, 0x02, 0x01, 0x07, 0xe6, 0xe5,
|
||||
0x01, 0x02, 0x01, 0x0c, 0x0c, 0x13, 0x18, 0x01,
|
||||
0xe6, 0x12, 0x06, 0x01, 0xe6, 0x04, 0x03, 0x02,
|
||||
0x02, 0x02, 0x1b, 0x02, 0x07, 0x08, 0x18, 0xe5,
|
||||
0x01, 0x0d, 0xe5, 0xe5, 0x05, 0x01, 0xe5, 0x02,
|
||||
0x02, 0x03, 0x0a, 0x02, 0x17, 0x02, 0x03, 0x05,
|
||||
0x0e, 0x11, 0x02, 0x01, 0x0a, 0x06, 0x01, 0xe5,
|
||||
0x01, 0x03, 0x01, 0x04, 0x02, 0x01, 0x07, 0x01,
|
||||
0x01, 0x05, 0x01, 0x02, 0x01, 0x04, 0x01, 0x01,
|
||||
0x05, 0x01, 0x07, 0x01, 0x02, 0x04, 0xe6, 0x06,
|
||||
0x01, 0x0b, 0x02, 0x09, 0x04, 0x0a, 0x09, 0xe5,
|
||||
0x01, 0x05, 0xe5, 0x13, 0xe5, 0x01, 0x03, 0xe5,
|
||||
0x01, 0x05, 0x05, 0x1e, 0x01, 0x01, 0xe5, 0xe5,
|
||||
0x01, 0x0b, 0x04, 0x05, 0x04, 0x01, 0x05, 0x03,
|
||||
0x12, 0xe5, 0xe5, 0x0b, 0x01, 0x06, 0x01, 0x1d,
|
||||
0x02, 0x01, 0x0b, 0x0d, 0x11, 0x0e, 0x04, 0x09,
|
||||
0x30, 0x03, 0xe5, 0x03, 0x02, 0x04, 0x01, 0x02,
|
||||
0x01, 0xe5, 0xe7, 0x04, 0x01, 0x01, 0x07, 0x01,
|
||||
0x0a, 0x0b, 0x08, 0x09, 0xe5, 0x05, 0x01, 0xe5,
|
||||
0x11, 0x05, 0x02, 0x02, 0x02, 0x09, 0x03, 0x04,
|
||||
0x0a, 0x0a, 0x02, 0x01, 0x07, 0x03, 0x11, 0x01,
|
||||
0x01, 0x05, 0x05, 0x0d, 0x06, 0x02, 0xe5, 0xe5,
|
||||
0xe6, 0x0b, 0x08, 0x06, 0xe8, 0xe5, 0x03, 0xe5,
|
||||
0xe5, 0xe5, 0x10, 0x04, 0x04, 0x01, 0x0a, 0xe5,
|
||||
0x01, 0x04, 0xe6, 0x16, 0x02, 0x01, 0x05, 0x0a,
|
||||
0x06, 0x02, 0x02, 0x04, 0x01, 0x15, 0x04, 0x05,
|
||||
0x04, 0x0a, 0x01, 0x21, 0x03, 0xe5, 0x05, 0x12,
|
||||
0x04, 0x07, 0x07, 0x10, 0x12, 0x27, 0xe8, 0x02,
|
||||
0x08, 0x0f, 0x16, 0x08, 0x02, 0x0a, 0x05, 0x03,
|
||||
0x07, 0x1c, 0xe6, 0xe6, 0xe5, 0x11, 0x1a, 0x01,
|
||||
0x02, 0x08, 0x01, 0x06, 0x1c, 0x16, 0xe5, 0xe6,
|
||||
0x08, 0xe5, 0x07, 0x0c, 0x02, 0xe5, 0x07, 0x09,
|
||||
0x10, 0x08, 0x05, 0xe5, 0x03, 0x01, 0x01, 0x17,
|
||||
0x01, 0xe7, 0x18, 0x08, 0xe5, 0x02, 0x05, 0x08,
|
||||
0xe5, 0x07, 0x16, 0x05, 0xe5, 0x01, 0x01, 0x18,
|
||||
0xe6, 0x18, 0x08, 0x08, 0xe5, 0x09, 0x17, 0x01,
|
||||
0x03, 0xe5, 0x08, 0x16, 0x03, 0x02, 0x03, 0x09,
|
||||
0x09, 0x13, 0x04, 0x20, 0xe5, 0x01, 0x02, 0x06,
|
||||
0x17, 0xe5, 0x01, 0x01, 0xe6, 0x0b, 0x0b, 0x02,
|
||||
0x0b, 0x01, 0xe7, 0x22, 0xe5, 0x02, 0x09, 0x14,
|
||||
0x01, 0x01, 0x03, 0xe5, 0x0c, 0x05, 0xe5, 0x0e,
|
||||
0x02, 0xe5, 0x04, 0x22, 0xe5, 0x03, 0x07, 0x0f,
|
||||
0xe5, 0x03, 0x01, 0x04, 0x01, 0xe5, 0xe5, 0x01,
|
||||
0x07, 0x19, 0xe5, 0x01, 0x01, 0xe5, 0x22, 0x04,
|
||||
0x04, 0xe5, 0xe5, 0x0e, 0xe5, 0x05, 0x02, 0x01,
|
||||
0x01, 0xe5, 0x0b, 0x12, 0xe5, 0x02, 0x05, 0x01,
|
||||
0x02, 0xe5, 0x01, 0x1e, 0x01, 0x02, 0x1f, 0xeb,
|
||||
0xe5, 0x09, 0x03, 0x09, 0x01, 0x01, 0xe6, 0x08,
|
||||
0x01, 0x04, 0x01, 0x20, 0x02, 0x06, 0x01, 0x01,
|
||||
0x01, 0x02, 0x0e, 0x05, 0xe6, 0x0b, 0x13, 0x09,
|
||||
0x01, 0x27, 0x01, 0x04, 0x04, 0x15, 0x04, 0xe7,
|
||||
0x0b, 0x13, 0x06, 0x01, 0xe5, 0xe5, 0xe5, 0x2b,
|
||||
0xe5, 0x02, 0x1a, 0xe6, 0x1c, 0x02, 0x05, 0xe5,
|
||||
0x07, 0xe5, 0x01, 0x06, 0x1c, 0x02, 0x01, 0xe5,
|
||||
0x05, 0x02, 0x0b, 0x04, 0xe5, 0x02, 0x0a, 0x13,
|
||||
0x06, 0x02, 0x01, 0x05, 0x01, 0x0b, 0x1d, 0x1d,
|
||||
0x01, 0xe7, 0x09, 0x03, 0x02, 0x06, 0x02, 0x02,
|
||||
0x03, 0x03, 0x05, 0xe5, 0xe5, 0xe7, 0x01, 0x0b,
|
||||
0x09, 0x04, 0x01, 0x02, 0x02, 0x01, 0xe6, 0x01,
|
||||
0x02, 0x06, 0x0d, 0x01, 0xe7, 0x15, 0x09, 0x05,
|
||||
0x03, 0x09, 0x1f, 0x09, 0x1b, 0xe8, 0x14, 0x09,
|
||||
0x08, 0x08, 0x20, 0x08, 0x1e, 0xe5, 0x01, 0x16,
|
||||
0xe5, 0xe5, 0x06, 0x01, 0x06, 0xe5, 0x07, 0x20,
|
||||
0x01, 0xe6, 0x04, 0x01, 0x19, 0x01, 0xe5, 0x01,
|
||||
0x14, 0x01, 0xe5, 0x05, 0x01, 0x01, 0x01, 0x06,
|
||||
0xe5, 0x07, 0x1c, 0x08, 0xe5, 0x01, 0x17, 0xe6,
|
||||
0xe6, 0x15, 0x01, 0x04, 0x40, 0x01, 0x18, 0xe8,
|
||||
0x14, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07, 0xe6, 0x01,
|
||||
0x04, 0xe6, 0xe5, 0x04, 0xe5, 0x07, 0xe5, 0x06,
|
||||
0x02, 0xe5, 0x16, 0x01, 0x07, 0x01, 0x57, 0xe7,
|
||||
0x03, 0x12, 0x01, 0x07, 0x01, 0x13, 0x1f, 0x07,
|
||||
0x1c, 0xe6, 0x16, 0x01, 0x26, 0x14, 0x01, 0x07,
|
||||
0x1c, 0x01, 0x04, 0x12, 0x01, 0x07, 0x04, 0x09,
|
||||
0x26, 0x07, 0x15, 0x01, 0x04, 0xe6, 0x0c, 0x01,
|
||||
0xe5, 0x09, 0x05, 0xe5, 0xe5, 0x13, 0x1b, 0x06,
|
||||
0x02, 0x10, 0x04, 0x03, 0xe6, 0xe6, 0x02, 0xe5,
|
||||
0x06, 0x01, 0x02, 0x01, 0xe5, 0x05, 0x01, 0x04,
|
||||
0x02, 0xe6, 0x06, 0x01, 0x01, 0x05, 0x01, 0x04,
|
||||
0x04, 0x01, 0x02, 0x04, 0x01, 0x04, 0x02, 0x01,
|
||||
0x01, 0x02, 0x02, 0x01, 0x07, 0x01, 0x01, 0x04,
|
||||
0x05, 0xe6, 0x02, 0x12, 0x0e, 0x07, 0x03, 0x0c,
|
||||
0x08, 0x0c, 0x06, 0x1e, 0x01, 0xe7, 0x1d, 0x08,
|
||||
0x01, 0x0e, 0x24, 0x13, 0x06, 0xe5, 0xe5, 0xe5,
|
||||
0x14, 0x09, 0xe5, 0x07, 0xe5, 0x01, 0x01, 0x0a,
|
||||
0x02, 0x01, 0x05, 0x34, 0xe9, 0xe5, 0x01, 0x02,
|
||||
0x0e, 0x01, 0x07, 0x01, 0xe5, 0x05, 0xe7, 0x01,
|
||||
0xe5, 0x01, 0x0f, 0x0f, 0x09, 0x15, 0x07, 0xe5,
|
||||
0x16, 0x01, 0x0a, 0x03, 0x03, 0x06, 0x03, 0x02,
|
||||
0x04, 0x13, 0x03, 0x09, 0x03, 0x10, 0x02, 0x01,
|
||||
0xe5, 0xe6, 0x18, 0x06, 0x0b, 0xe6, 0x07, 0x06,
|
||||
0x06, 0x07, 0x0e, 0x1b, 0xe9, 0x0f, 0x05, 0x04,
|
||||
0x08, 0x06, 0xe5, 0x04, 0x05, 0x02, 0x03, 0x14,
|
||||
0x04, 0x03, 0x1b, 0x01, 0x02, 0x11, 0x0a, 0xe5,
|
||||
0x07, 0x06, 0x11, 0xe5, 0x39, 0x02, 0x0d, 0xe5,
|
||||
0x0b, 0x03, 0x0c, 0x10, 0x01, 0x39, 0x01, 0xe5,
|
||||
0xe5, 0x0c, 0x02, 0x05, 0x04, 0x10, 0x05, 0xe5,
|
||||
0x0a, 0x3a, 0xe5, 0xe6, 0x01, 0x16, 0x0d, 0x02,
|
||||
0x06, 0x05, 0xe5, 0x06, 0xe5, 0xe5, 0x0e, 0x25,
|
||||
0xe5, 0x01, 0xe5, 0x1b, 0x09, 0xe5, 0x04, 0x08,
|
||||
0xe5, 0x07, 0x02, 0x19, 0x11, 0x0b, 0x02, 0x17,
|
||||
0x15, 0x06, 0x02, 0x0a, 0x3a, 0xe7, 0x11, 0xe5,
|
||||
0x04, 0x0f, 0x4b, 0xe5, 0x02, 0xe6, 0x01, 0x01,
|
||||
0x0e, 0xe5, 0x05, 0x0f, 0xe6, 0x11, 0x34, 0x01,
|
||||
0x01, 0x03, 0xe5, 0x03, 0x05, 0x01, 0xe5, 0xe5,
|
||||
0x03, 0xe5, 0xe5, 0xe6, 0x0f, 0x01, 0x04, 0x01,
|
||||
0xe5, 0x01, 0x03, 0xe5, 0x02, 0x04, 0x28, 0xe5,
|
||||
0x03, 0x01, 0x03, 0x02, 0x02, 0x07, 0x02, 0x01,
|
||||
0x04, 0xe5, 0xe5, 0xe6, 0x0c, 0xe5, 0xe5, 0xe5,
|
||||
0x03, 0xe5, 0x02, 0x04, 0x32, 0xe5, 0x05, 0x02,
|
||||
0x01, 0x01, 0x0b, 0x01, 0x01, 0x02, 0x04, 0x21,
|
||||
0xe5, 0x01, 0xe5, 0xe5, 0x05, 0x02, 0x2d, 0xe7,
|
||||
0xe6, 0x01, 0x0a, 0x01, 0x02, 0x04, 0x13, 0x01,
|
||||
0x01, 0x01, 0x02, 0x05, 0x02, 0xe5, 0x05, 0x2e,
|
||||
0x02, 0x03, 0x01, 0xe6, 0x17, 0x11, 0x01, 0x07,
|
||||
0x07, 0x03, 0x35, 0x02, 0xe8, 0x11, 0x06, 0x11,
|
||||
0x01, 0x09, 0x03, 0xe5, 0x3d, 0x01, 0xe5, 0x11,
|
||||
0x09, 0x14, 0x02, 0x05, 0x3e, 0xe7, 0xe5, 0x1a,
|
||||
0xe5, 0x1e, 0x3d, 0xe5, 0x01, 0xe5, 0x0a, 0x02,
|
||||
0x09, 0x09, 0x09, 0x06, 0x02, 0x03, 0x02, 0x04,
|
||||
0x09, 0x09, 0x09, 0x09, 0x0d, 0xe9, 0x01, 0x08,
|
||||
0xe5, 0x04, 0x09, 0x14, 0x02, 0x05, 0x02, 0xe5,
|
||||
0x3a, 0xe5, 0xe6, 0x0a, 0x26, 0x08, 0x40, 0xe6,
|
||||
0x0c, 0x04, 0x04, 0x01, 0x02, 0x15, 0x0b, 0x04,
|
||||
0x36, 0xe8, 0x0e, 0x01, 0x02, 0x02, 0x01, 0xe6,
|
||||
0xe5, 0x0f, 0x0a, 0x09, 0xe5, 0x35, 0xe8, 0x08,
|
||||
0x02, 0x09, 0x01, 0x10, 0x07, 0x08, 0x07, 0x2e,
|
||||
0x08, 0xe7, 0x0e, 0x05, 0xe6, 0xe5, 0x04, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x09, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x09, 0xe5, 0x0c, 0x09, 0x01, 0x14, 0x14, 0x36,
|
||||
0x02, 0xe5, 0x0e, 0x07, 0x16, 0x4d, 0x01, 0xe5,
|
||||
0x0b, 0x09, 0x01, 0x11, 0x0b, 0x01, 0x06, 0x02,
|
||||
0x36, 0xe5, 0xe6, 0x02, 0x0b, 0x02, 0x04, 0x04,
|
||||
0x0e, 0x02, 0x11, 0x39, 0xe5, 0x01, 0x2b, 0x15,
|
||||
0x01, 0xe5, 0x20, 0x12, 0xe5, 0xe7, 0x10, 0x01,
|
||||
0x02, 0x03, 0xe5, 0xe5, 0x06, 0x01, 0x02, 0x04,
|
||||
0x01, 0x07, 0x01, 0x05, 0x03, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x0b, 0xe5,
|
||||
0xe5, 0x18, 0x12, 0x02, 0x09, 0x21, 0x01, 0x1c,
|
||||
0xe6, 0xe6, 0x13, 0x1c, 0x0b, 0x01, 0x13, 0x24,
|
||||
0xe5, 0x01, 0xe5, 0x18, 0x14, 0x10, 0x3b, 0x02,
|
||||
0x17, 0x01, 0x0e, 0x02, 0x01, 0x07, 0xe5, 0x09,
|
||||
0x01, 0x16, 0x1a, 0x05, 0x02, 0x17, 0x01, 0x13,
|
||||
0x0d, 0x03, 0x04, 0x03, 0x10, 0x1c, 0x02, 0x02,
|
||||
0xe6, 0x19, 0x09, 0x06, 0x05, 0x0f, 0x37, 0x01,
|
||||
0xe7, 0x25, 0x04, 0x01, 0x11, 0x08, 0x10, 0x1f,
|
||||
0x02, 0x01, 0x26, 0x08, 0x0f, 0x06, 0x33, 0x01,
|
||||
0x01, 0x0a, 0x10, 0x0f, 0x13, 0x07, 0x31, 0x02,
|
||||
0xe6, 0x11, 0x16, 0x01, 0x03, 0x0f, 0x3b, 0x02,
|
||||
0x14, 0x01, 0x16, 0xe5, 0x0c, 0x28, 0x13, 0x04,
|
||||
0xe5, 0x2b, 0x0a, 0x36, 0x0a, 0x01, 0x01, 0x2b,
|
||||
0xe5, 0x0d, 0x3e, 0xe8, 0xe5, 0x75, 0xe5, 0x03,
|
||||
0x02, 0x01, 0x28, 0x47, 0x01, 0x02, 0xe6, 0xe5,
|
||||
0x03, 0x23, 0x01, 0x4a, 0x04, 0xe5, 0x01, 0x02,
|
||||
0x74, 0x02, 0xe6, 0xe6, 0x04, 0x05, 0x21, 0x01,
|
||||
0x01, 0x01, 0x45, 0x01, 0xe6, 0x01, 0x08, 0x25,
|
||||
0x02, 0x3f, 0x02, 0x05, 0xe6, 0x72, 0x04, 0xe5,
|
||||
0xe5, 0xe5, 0x01, 0x2c, 0x4a, 0x03, 0xe6, 0x2d,
|
||||
0x43, 0x06, 0x01, 0xe5, 0x7a, 0xe8, 0x0d, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09,
|
||||
0x0d, 0x03, 0xe5, 0x01, 0x27, 0x4c, 0x06, 0x29,
|
||||
0x52, 0x01, 0x2d, 0xe5, 0x48, 0x03, 0x01, 0x16,
|
||||
0x03, 0x14, 0x4a, 0xe6, 0xe5, 0x2c, 0x03, 0x4a,
|
||||
0xe6, 0x03, 0x10, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x06, 0x02,
|
||||
0xe5, 0x16, 0x01, 0x13, 0x4c, 0x03, 0x17, 0x01,
|
||||
0x63, 0xe6, 0x15, 0x01, 0x13, 0x12, 0x39, 0x03,
|
||||
0x03, 0x13, 0x01, 0x16, 0x49, 0xe5, 0xe6, 0x2a,
|
||||
0x01, 0xe5, 0x49, 0x02, 0xe6, 0x10, 0x01, 0x01,
|
||||
0x05, 0x01, 0x02, 0x03, 0xe5, 0xe5, 0x02, 0x03,
|
||||
0x01, 0x01, 0x05, 0x01, 0x01, 0x02, 0x03, 0xe5,
|
||||
0xe5, 0x06, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
|
||||
0x01, 0x0a, 0xe5, 0x01, 0x5b, 0x22, 0xe5, 0x09,
|
||||
0x34, 0x07, 0x09, 0x0b, 0x1a, 0x02, 0x01, 0x3f,
|
||||
0x3a, 0xe6, 0xe5, 0x16, 0x10, 0x17, 0x07, 0x2b,
|
||||
0x08, 0xe5, 0x19, 0x16, 0x09, 0x03, 0x3b, 0xe7,
|
||||
0x23, 0x1a, 0x04, 0xe5, 0x33, 0x01, 0xe6, 0x1b,
|
||||
0x22, 0x0a, 0x0d, 0x23, 0x01, 0x3f, 0x3c, 0xe6,
|
||||
0x20, 0xe6, 0x15, 0x04, 0x2a, 0x09, 0x06, 0xe5,
|
||||
0xe5, 0x23, 0x1a, 0xe5, 0x28, 0x0f, 0x02, 0xe5,
|
||||
0x38, 0x41, 0xe5, 0xe6, 0xe5, 0x24, 0x04, 0x1a,
|
||||
0x30, 0x01, 0xe5, 0xe5, 0x2c, 0x4c, 0xe5, 0x01,
|
||||
0xe6, 0x75, 0xe8, 0xe5, 0x01, 0x01, 0x70, 0x01,
|
||||
0x03, 0xe5, 0xe5, 0x03, 0x70, 0x04, 0xe5, 0x01,
|
||||
0x02, 0x74, 0x02, 0x01, 0xe6, 0x01, 0x78, 0x02,
|
||||
0x74, 0x02, 0x02, 0xe8, 0x13, 0x5f, 0x04, 0x03,
|
||||
0xe5, 0x13, 0xe5, 0x63, 0x01, 0xe6, 0x08, 0x02,
|
||||
0x08, 0x64, 0xe5, 0x01, 0x0a, 0xe5, 0x6e, 0xe5,
|
||||
0xe6, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0d, 0xe9, 0x01, 0x74, 0x06,
|
||||
0x7a, 0x03, 0x01, 0x2b, 0x4d, 0xe5, 0xe5, 0x23,
|
||||
0x08, 0xe5, 0x47, 0x02, 0xe8, 0x2c, 0x4b, 0xe5,
|
||||
0x01, 0xe5, 0x12, 0x01, 0x07, 0xe6, 0x07, 0xe5,
|
||||
0x02, 0x03, 0x01, 0x09, 0xe5, 0x09, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x06,
|
||||
0x01, 0xe6, 0x0f, 0xe5, 0x02, 0x09, 0x01, 0x01,
|
||||
0xe5, 0x03, 0x03, 0x03, 0x01, 0x38, 0x0b, 0x01,
|
||||
0x01, 0x01, 0x13, 0x02, 0x09, 0xe5, 0xe6, 0x02,
|
||||
0x01, 0x02, 0x06, 0x37, 0x0d, 0x01, 0x01, 0x15,
|
||||
0x07, 0xe6, 0xe5, 0xe5, 0x04, 0x03, 0x05, 0x47,
|
||||
0xe5, 0xe5, 0x0f, 0x02, 0xe5, 0x07, 0xe5, 0x01,
|
||||
0x01, 0xe5, 0x01, 0xe5, 0x03, 0x03, 0xe5, 0x38,
|
||||
0x0e, 0x01, 0xe5, 0x2e, 0x33, 0x15, 0xe5, 0xe5,
|
||||
0xe5, 0x10, 0x01, 0x07, 0x01, 0x07, 0x01, 0xe5,
|
||||
0xe5, 0x03, 0x01, 0xe5, 0xe5, 0x02, 0xe5, 0xe6,
|
||||
0x07, 0x01, 0xe5, 0x05, 0x01, 0xe6, 0x04, 0xe7,
|
||||
0x05, 0x01, 0x07, 0x01, 0x0b, 0xe7, 0x3d, 0x15,
|
||||
0x21, 0x03, 0x03, 0xe5, 0x3e, 0x38, 0xe5, 0xe5,
|
||||
0xe5, 0x12, 0x02, 0x09, 0x1e, 0x07, 0x32, 0x03,
|
||||
0xe5, 0x19, 0x05, 0x01, 0x0a, 0x09, 0x06, 0x3a,
|
||||
0xe5, 0x01, 0x23, 0x03, 0x17, 0x3a, 0x03, 0xe5,
|
||||
0x1f, 0x1d, 0x16, 0xe5, 0x24, 0xe5, 0x1e, 0x09,
|
||||
0x12, 0x02, 0x15, 0x01, 0x23, 0xe7, 0x3e, 0x23,
|
||||
0x17, 0x01, 0xe5, 0x3e, 0x3c, 0xe6, 0x24, 0x19,
|
||||
0x3d, 0xe6, 0x1b, 0xe5, 0x04, 0x02, 0xe5, 0x08,
|
||||
0x38, 0x12, 0x33, 0x36, 0xe6, 0x0b, 0x01, 0xe5,
|
||||
0xe5, 0x6a, 0x10, 0xe6, 0x02, 0x0b, 0xe5, 0xe5,
|
||||
0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe6, 0x06, 0xe5,
|
||||
0x07, 0xe7, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x07, 0xe5, 0x0b, 0x03, 0xe5, 0x0f, 0x09, 0x09,
|
||||
0x09, 0x09, 0x04, 0x04, 0x01, 0x09, 0x09, 0x09,
|
||||
0x01, 0x07, 0x0d, 0xe5, 0xe6, 0x0e, 0x09, 0x03,
|
||||
0x05, 0x09, 0x09, 0x04, 0x06, 0x04, 0x04, 0x04,
|
||||
0x04, 0x04, 0x04, 0x09, 0x0e, 0x03, 0x26, 0x57,
|
||||
0x0f, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x01, 0x07,
|
||||
0x09, 0x09, 0x02, 0x06, 0x0e, 0xe5, 0xe6, 0x0c,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x0e, 0x03, 0x03, 0x09, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09,
|
||||
0x12, 0xe6, 0x0d, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
|
||||
0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
|
||||
0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
|
||||
0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
|
||||
0x0b, 0x03, 0x0e, 0x09, 0x09, 0x09, 0x09, 0x03,
|
||||
0x07, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x02, 0xe5,
|
||||
0x79, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09, 0x09,
|
||||
0x08, 0x02, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe6,
|
||||
0x3e, 0x3b, 0x02, 0x10, 0x09, 0x09, 0x09, 0x09,
|
||||
0x0b, 0x09, 0x09, 0x09, 0x09, 0x10, 0xe5, 0x7d,
|
||||
0x3f, 0x3a, 0xe5, 0x01, 0x3f, 0x36, 0x04, 0x02,
|
||||
0x7a, 0x01, 0x01, 0x13, 0x3d, 0x28, 0x01, 0x01,
|
||||
0x3f, 0x33, 0x0a, 0x3f, 0x34, 0x08, 0xe5, 0x79,
|
||||
0x01, 0x01, 0x14, 0x09, 0x09, 0x09, 0x09, 0x0b,
|
||||
0x09, 0x09, 0x09, 0x09, 0x09, 0xe5, 0x01, 0x0f,
|
||||
0x09, 0x09, 0x09, 0x09, 0x07, 0x03, 0x09, 0x09,
|
||||
0x09, 0x08, 0xe5, 0x0d, 0x03, 0x3a, 0x04, 0x3a,
|
||||
0x02, 0xe5, 0x0c, 0x09, 0x03, 0x05, 0x09, 0x09,
|
||||
0x03, 0x07, 0x09, 0x09, 0x07, 0x01, 0x1b, 0x01,
|
||||
0xe5, 0x0a, 0x02, 0x07, 0x05, 0x03, 0x01, 0x03,
|
||||
0x03, 0x01, 0x03, 0x03, 0x09, 0x06, 0xe5, 0x02,
|
||||
0x04, 0x04, 0x04, 0x02, 0x06, 0xe5, 0x02, 0x02,
|
||||
0x06, 0x02, 0xe5, 0x02, 0x03, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff,
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common/xilinx_jtag)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
# Objects for Xilinx JTAG programming (CPLD)
|
||||
CPLD = ../common/xilinx_jtag/lenval.o \
|
||||
../common/xilinx_jtag/micro.o \
|
||||
../common/xilinx_jtag/ports.o
|
||||
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
$(CPLD) \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2007
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
|
||||
*/
|
||||
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
|
||||
|
||||
/*
|
||||
* Reset CPLD via GPIO12 (CS3) pin
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
|
||||
udelay(1000); /* wait 1ms */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
/*
|
||||
* Setup and enable EEPROM write protection
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int flashcnt;
|
||||
int delay;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (getenv_f("serial#", str, sizeof(str)) == -1) {
|
||||
puts ("### No HW ID - assuming CMS700");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
printf(" (PLD-Version=%02d)\n",
|
||||
in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
|
||||
|
||||
/*
|
||||
* Flash LEDs
|
||||
*/
|
||||
for (flashcnt = 0; flashcnt < 3; flashcnt++) {
|
||||
out_8((void *)LED_REG, 0x00); /* LEDs off */
|
||||
for (delay = 0; delay < 100; delay++)
|
||||
udelay(1000);
|
||||
out_8((void *)LED_REG, 0x0f); /* LEDs on */
|
||||
for (delay = 0; delay < 50; delay++)
|
||||
udelay(1000);
|
||||
}
|
||||
out_8((void *)LED_REG, 0x70);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||
{
|
||||
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO_SINT2. */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO_SINT2. */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts ("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"Enable / disable / query EEPROM write access",
|
||||
""
|
||||
);
|
||||
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
int size_val = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
switch (size_b0) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CONFIG_SYS_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <command.h>
|
||||
#include <image.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <fat.h>
|
||||
#include <part.h>
|
||||
|
||||
#include "auto_update.h"
|
||||
|
||||
#ifdef CONFIG_AUTO_UPDATE
|
||||
|
||||
#if !defined(CONFIG_CMD_FAT)
|
||||
#error "must define CONFIG_CMD_FAT"
|
||||
#endif
|
||||
|
||||
extern au_image_t au_image[];
|
||||
extern int N_AU_IMAGES;
|
||||
|
||||
/* where to load files into memory */
|
||||
#define LOAD_ADDR ((unsigned char *)0x100000)
|
||||
#define MAX_LOADSZ 0x1c00000
|
||||
|
||||
/* externals */
|
||||
extern int fat_register_device(block_dev_desc_t *, int);
|
||||
extern int file_fat_detectfs(void);
|
||||
extern long file_fat_read(const char *, void *, unsigned long);
|
||||
long do_fat_read (const char *filename, void *buffer,
|
||||
unsigned long maxsize, int dols);
|
||||
extern int flash_sect_erase(ulong, ulong);
|
||||
extern int flash_sect_protect (int, ulong, ulong);
|
||||
extern int flash_write (char *, ulong, ulong);
|
||||
|
||||
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
|
||||
|
||||
int au_check_cksum_valid(int i, long nbytes)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
#if defined(CONFIG_FIT)
|
||||
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
|
||||
puts ("Non legacy image format not supported\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
if ((au_image[i].type == AU_FIRMWARE) &&
|
||||
(au_image[i].size != image_get_data_size (hdr))) {
|
||||
printf ("Image %s has wrong size\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (nbytes != (image_get_image_size (hdr))) {
|
||||
printf ("Image %s bad total SIZE\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* check the data CRC */
|
||||
if (!image_check_dcrc (hdr)) {
|
||||
printf ("Image %s bad data checksum\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au_check_header_valid(int i, long nbytes)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
#if defined(CONFIG_FIT)
|
||||
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
|
||||
puts ("Non legacy image format not supported\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* check the easy ones first */
|
||||
if (nbytes < image_get_header_size ()) {
|
||||
printf ("Image %s bad header SIZE\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
|
||||
printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
if (!image_check_hcrc (hdr)) {
|
||||
printf ("Image %s bad header checksum\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* check the type - could do this all in one gigantic if() */
|
||||
if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) &&
|
||||
!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
|
||||
printf ("Image %s wrong type\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) &&
|
||||
!image_check_type (hdr, IH_TYPE_SCRIPT)) {
|
||||
printf ("Image %s wrong type\n", au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au_do_update(int i, long sz)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
char *addr;
|
||||
long start, end;
|
||||
int off, rc;
|
||||
uint nbytes;
|
||||
int k;
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
#if defined(CONFIG_FIT)
|
||||
if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
|
||||
puts ("Non legacy image format not supported\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
switch (au_image[i].type & AU_TYPEMASK) {
|
||||
case AU_SCRIPT:
|
||||
printf("Executing script %s\n", au_image[i].name);
|
||||
|
||||
/* execute a script */
|
||||
if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
|
||||
addr = (char *)((char *)hdr + image_get_header_size ());
|
||||
/* stick a NULL at the end of the script, otherwise */
|
||||
/* parse_string_outer() runs off the end. */
|
||||
addr[image_get_data_size (hdr)] = 0;
|
||||
addr += 8;
|
||||
|
||||
/*
|
||||
* Replace cr/lf with ;
|
||||
*/
|
||||
k = 0;
|
||||
while (addr[k] != 0) {
|
||||
if ((addr[k] == 10) || (addr[k] == 13)) {
|
||||
addr[k] = ';';
|
||||
}
|
||||
k++;
|
||||
}
|
||||
|
||||
run_command(addr, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case AU_FIRMWARE:
|
||||
case AU_NOR:
|
||||
case AU_NAND:
|
||||
start = au_image[i].start;
|
||||
end = au_image[i].start + au_image[i].size - 1;
|
||||
|
||||
/*
|
||||
* do not update firmware when image is already in flash.
|
||||
*/
|
||||
if (au_image[i].type == AU_FIRMWARE) {
|
||||
char *orig = (char*)start;
|
||||
char *new = (char *)((char *)hdr +
|
||||
image_get_header_size ());
|
||||
nbytes = image_get_data_size (hdr);
|
||||
|
||||
while (--nbytes) {
|
||||
if (*orig++ != *new++) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!nbytes) {
|
||||
printf ("Skipping firmware update - "
|
||||
"images are identical\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* unprotect the address range */
|
||||
if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
|
||||
(au_image[i].type == AU_FIRMWARE)) {
|
||||
flash_sect_protect (0, start, end);
|
||||
}
|
||||
|
||||
/*
|
||||
* erase the address range.
|
||||
*/
|
||||
if (au_image[i].type != AU_NAND) {
|
||||
printf ("Updating NOR FLASH with image %s\n",
|
||||
au_image[i].name);
|
||||
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
|
||||
flash_sect_erase (start, end);
|
||||
}
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* strip the header - except for the kernel and ramdisk */
|
||||
if (au_image[i].type != AU_FIRMWARE) {
|
||||
addr = (char *)hdr;
|
||||
off = image_get_header_size ();
|
||||
nbytes = image_get_image_size (hdr);
|
||||
} else {
|
||||
addr = (char *)((char *)hdr + image_get_header_size ());
|
||||
off = 0;
|
||||
nbytes = image_get_data_size (hdr);
|
||||
}
|
||||
|
||||
/*
|
||||
* copy the data from RAM to FLASH
|
||||
*/
|
||||
if (au_image[i].type != AU_NAND) {
|
||||
debug ("flash_write(%p, %lx, %x)\n",
|
||||
addr, start, nbytes);
|
||||
rc = flash_write ((char *)addr, start,
|
||||
(nbytes + 1) & ~1);
|
||||
} else {
|
||||
rc = -1;
|
||||
}
|
||||
if (rc != 0) {
|
||||
printf ("Flashing failed due to error %d\n", rc);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* check the dcrc of the copy
|
||||
*/
|
||||
if (au_image[i].type != AU_NAND) {
|
||||
rc = crc32 (0, (uchar *)(start + off),
|
||||
image_get_data_size (hdr));
|
||||
}
|
||||
if (rc != image_get_dcrc (hdr)) {
|
||||
printf ("Image %s Bad Data Checksum After COPY\n",
|
||||
au_image[i].name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* protect the address range */
|
||||
/* this assumes that ONLY the firmware is protected! */
|
||||
if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
|
||||
(au_image[i].type == AU_FIRMWARE)) {
|
||||
flash_sect_protect (1, start, end);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Wrong image type selected!\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void process_macros (const char *input, char *output)
|
||||
{
|
||||
char c, prev;
|
||||
const char *varname_start = NULL;
|
||||
int inputcnt = strlen (input);
|
||||
int outputcnt = CONFIG_SYS_CBSIZE;
|
||||
int state = 0; /* 0 = waiting for '$' */
|
||||
/* 1 = waiting for '(' or '{' */
|
||||
/* 2 = waiting for ')' or '}' */
|
||||
/* 3 = waiting for ''' */
|
||||
#ifdef DEBUG_PARSER
|
||||
char *output_start = output;
|
||||
|
||||
printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n",
|
||||
strlen(input), input);
|
||||
#endif
|
||||
|
||||
prev = '\0'; /* previous character */
|
||||
|
||||
while (inputcnt && outputcnt) {
|
||||
c = *input++;
|
||||
inputcnt--;
|
||||
|
||||
if (state != 3) {
|
||||
/* remove one level of escape characters */
|
||||
if ((c == '\\') && (prev != '\\')) {
|
||||
if (inputcnt-- == 0)
|
||||
break;
|
||||
prev = c;
|
||||
c = *input++;
|
||||
}
|
||||
}
|
||||
|
||||
switch (state) {
|
||||
case 0: /* Waiting for (unescaped) $ */
|
||||
if ((c == '\'') && (prev != '\\')) {
|
||||
state = 3;
|
||||
break;
|
||||
}
|
||||
if ((c == '$') && (prev != '\\')) {
|
||||
state++;
|
||||
} else {
|
||||
*(output++) = c;
|
||||
outputcnt--;
|
||||
}
|
||||
break;
|
||||
case 1: /* Waiting for ( */
|
||||
if (c == '(' || c == '{') {
|
||||
state++;
|
||||
varname_start = input;
|
||||
} else {
|
||||
state = 0;
|
||||
*(output++) = '$';
|
||||
outputcnt--;
|
||||
|
||||
if (outputcnt) {
|
||||
*(output++) = c;
|
||||
outputcnt--;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 2: /* Waiting for ) */
|
||||
if (c == ')' || c == '}') {
|
||||
int i;
|
||||
char envname[CONFIG_SYS_CBSIZE], *envval;
|
||||
/* Varname # of chars */
|
||||
int envcnt = input - varname_start - 1;
|
||||
|
||||
/* Get the varname */
|
||||
for (i = 0; i < envcnt; i++) {
|
||||
envname[i] = varname_start[i];
|
||||
}
|
||||
envname[i] = 0;
|
||||
|
||||
/* Get its value */
|
||||
envval = getenv (envname);
|
||||
|
||||
/* Copy into the line if it exists */
|
||||
if (envval != NULL)
|
||||
while ((*envval) && outputcnt) {
|
||||
*(output++) = *(envval++);
|
||||
outputcnt--;
|
||||
}
|
||||
/* Look for another '$' */
|
||||
state = 0;
|
||||
}
|
||||
break;
|
||||
case 3: /* Waiting for ' */
|
||||
if ((c == '\'') && (prev != '\\')) {
|
||||
state = 0;
|
||||
} else {
|
||||
*(output++) = c;
|
||||
outputcnt--;
|
||||
}
|
||||
break;
|
||||
}
|
||||
prev = c;
|
||||
}
|
||||
|
||||
if (outputcnt)
|
||||
*output = 0;
|
||||
|
||||
#ifdef DEBUG_PARSER
|
||||
printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
|
||||
strlen (output_start), output_start);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* this is called from board_init() after the hardware has been set up
|
||||
* and is usable. That seems like a good time to do this.
|
||||
* Right now the return value is ignored.
|
||||
*/
|
||||
int do_auto_update(void)
|
||||
{
|
||||
block_dev_desc_t *stor_dev = NULL;
|
||||
long sz;
|
||||
int i, res, cnt, old_ctrlc;
|
||||
char buffer[32];
|
||||
char str[80];
|
||||
int n;
|
||||
|
||||
if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) {
|
||||
stor_dev = get_dev ("ide", 0);
|
||||
if (stor_dev == NULL) {
|
||||
debug ("ide: unknown device\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (fat_register_device (stor_dev, 1) != 0) {
|
||||
debug ("Unable to register ide disk 0:1\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if magic file is present
|
||||
*/
|
||||
if ((n = do_fat_read (AU_MAGIC_FILE, buffer,
|
||||
sizeof(buffer), LS_NO)) <= 0) {
|
||||
debug ("No auto_update magic file (n=%d)\n", n);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_AUTO_UPDATE_SHOW
|
||||
board_auto_update_show (1);
|
||||
#endif
|
||||
puts("\nAutoUpdate Disk detected! Trying to update system...\n");
|
||||
|
||||
/* make sure that we see CTRL-C and save the old state */
|
||||
old_ctrlc = disable_ctrlc (0);
|
||||
|
||||
/* just loop thru all the possible files */
|
||||
for (i = 0; i < N_AU_IMAGES; i++) {
|
||||
/*
|
||||
* Try to expand the environment var in the fname
|
||||
*/
|
||||
process_macros (au_image[i].name, str);
|
||||
strcpy (au_image[i].name, str);
|
||||
|
||||
printf("Reading %s ...", au_image[i].name);
|
||||
/* just read the header */
|
||||
sz = do_fat_read (au_image[i].name, LOAD_ADDR,
|
||||
image_get_header_size (), LS_NO);
|
||||
debug ("read %s sz %ld hdr %d\n",
|
||||
au_image[i].name, sz, image_get_header_size ());
|
||||
if (sz <= 0 || sz < image_get_header_size ()) {
|
||||
puts(" not found\n");
|
||||
continue;
|
||||
}
|
||||
if (au_check_header_valid (i, sz) < 0) {
|
||||
puts(" header not valid\n");
|
||||
continue;
|
||||
}
|
||||
sz = do_fat_read (au_image[i].name, LOAD_ADDR,
|
||||
MAX_LOADSZ, LS_NO);
|
||||
debug ("read %s sz %ld hdr %d\n",
|
||||
au_image[i].name, sz, image_get_header_size ());
|
||||
if (sz <= 0 || sz <= image_get_header_size ()) {
|
||||
puts(" not found\n");
|
||||
continue;
|
||||
}
|
||||
if (au_check_cksum_valid (i, sz) < 0) {
|
||||
puts(" checksum not valid\n");
|
||||
continue;
|
||||
}
|
||||
puts(" done\n");
|
||||
|
||||
do {
|
||||
res = au_do_update (i, sz);
|
||||
/* let the user break out of the loop */
|
||||
if (ctrlc() || had_ctrlc ()) {
|
||||
clear_ctrlc ();
|
||||
break;
|
||||
}
|
||||
cnt++;
|
||||
} while (res < 0);
|
||||
}
|
||||
|
||||
/* restore the old state */
|
||||
disable_ctrlc (old_ctrlc);
|
||||
|
||||
puts("AutoUpdate finished\n\n");
|
||||
#ifdef CONFIG_AUTO_UPDATE_SHOW
|
||||
board_auto_update_show (0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
do_auto_update();
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
autoupd, 1, 1, auto_update,
|
||||
"Automatically update images",
|
||||
""
|
||||
);
|
||||
#endif /* CONFIG_AUTO_UPDATE */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _AUTO_UPDATE_H_
|
||||
#define _AUTO_UPDATE_H_
|
||||
|
||||
#define MBR_MAGIC 0x07081967
|
||||
#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */
|
||||
|
||||
#define AU_MAGIC_FILE "__auto_update"
|
||||
|
||||
#define AU_TYPEMASK 0x000000ff
|
||||
#define AU_FLAGMASK 0xffff0000
|
||||
|
||||
#define AU_PROTECT 0x80000000
|
||||
|
||||
#define AU_SCRIPT 0x01
|
||||
#define AU_FIRMWARE (0x02 | AU_PROTECT)
|
||||
#define AU_NOR 0x03
|
||||
#define AU_NAND 0x04
|
||||
|
||||
struct au_image_s {
|
||||
char name[80];
|
||||
ulong start;
|
||||
ulong size;
|
||||
ulong type;
|
||||
};
|
||||
|
||||
typedef struct au_image_s au_image_t;
|
||||
|
||||
int do_auto_update(void);
|
||||
#ifdef CONFIG_AUTO_UPDATE_SHOW
|
||||
void board_auto_update_show(int au_active);
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef _AUTO_UPDATE_H_ */
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2008
|
||||
* Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#if !defined(CONFIG_440)
|
||||
#include <asm/4xx_pci.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
||||
extern int do_source (cmd_tbl_t *, int, int, char *[]);
|
||||
|
||||
#define ADDRMASK 0xfffff000
|
||||
|
||||
/*
|
||||
* Command loadpci: wait for signal from host and boot image.
|
||||
*/
|
||||
int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
u32 *ptr = 0;
|
||||
int count = 0;
|
||||
int count2 = 0;
|
||||
char addr[16];
|
||||
char str[] = "\\|/-";
|
||||
char *local_args[2];
|
||||
u32 la, ptm1la;
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
ptm1la = in32r(PCIL0_PTM1LA);
|
||||
#else
|
||||
ptm1la = in32r(PTM1LA);
|
||||
#endif
|
||||
while(1) {
|
||||
/*
|
||||
* Mark sync address
|
||||
*/
|
||||
ptr = (u32 *)ptm1la;
|
||||
memset(ptr, 0, 0x20);
|
||||
|
||||
*ptr = 0xffffffff;
|
||||
puts("\nWaiting for action from pci host -");
|
||||
|
||||
/*
|
||||
* Wait for host to write the start address
|
||||
*/
|
||||
while (*ptr == 0xffffffff) {
|
||||
count++;
|
||||
if (!(count % 100)) {
|
||||
count2++;
|
||||
putc(0x08); /* backspace */
|
||||
putc(str[count2 % 4]);
|
||||
}
|
||||
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
printf("\nGot bootcode %08x: ", *ptr);
|
||||
la = ptm1la + (*ptr & ADDRMASK);
|
||||
sprintf(addr, "%08x", la);
|
||||
|
||||
switch (*ptr & ~ADDRMASK) {
|
||||
case 0:
|
||||
/*
|
||||
* Boot image via bootm
|
||||
*/
|
||||
printf("booting image at addr 0x%s ...\n", addr);
|
||||
setenv("loadaddr", addr);
|
||||
do_bootm(cmdtp, 0, 0, NULL);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
/*
|
||||
* Boot image via "source" command
|
||||
*/
|
||||
printf("executing script at addr 0x%s ...\n", addr);
|
||||
local_args[0] = addr;
|
||||
local_args[1] = NULL;
|
||||
do_source(cmdtp, 0, 1, local_args);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/*
|
||||
* Call run_cmd
|
||||
*/
|
||||
printf("running command at addr 0x%s ...\n", addr);
|
||||
run_command((char *)la, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("unhandled boot method\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
loadpci, 1, 1, do_loadpci,
|
||||
"Wait for pci bootcmd and boot it",
|
||||
""
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
|
||||
/*
|
||||
* hardware specific access to control-lines
|
||||
*/
|
||||
static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
|
||||
else
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
|
||||
if ( ctrl & NAND_ALE )
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
|
||||
else
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
|
||||
if ( ctrl & NAND_NCE )
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
|
||||
else
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* read device ready pin
|
||||
*/
|
||||
static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
|
||||
{
|
||||
if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to defaults
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
|
||||
|
||||
/*
|
||||
* Initialize nand_chip structure
|
||||
*/
|
||||
nand->cmd_ctrl = esd405ep_nand_hwcontrol;
|
||||
nand->dev_ready = esd405ep_nand_device_ready;
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->chip_delay = NAND_BIG_DELAY_US;
|
||||
nand->options = NAND_SAMSUNG_LP_OPTIONS;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,675 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#ifdef __PPC__
|
||||
#include <asm/ppc4xx.h>
|
||||
#endif
|
||||
#include <asm/processor.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
short n;
|
||||
|
||||
/* set up sector start address table */
|
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
while (i < info->sector_count) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
|
||||
/* set sector offsets for top boot block type */
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int size;
|
||||
int erased;
|
||||
volatile unsigned long *flash;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
case FLASH_MAN_SST: printf ("SST "); break;
|
||||
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
|
||||
break;
|
||||
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
if (i != (info->sector_count-1))
|
||||
size = info->start[i+1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
erased = 1;
|
||||
flash = (volatile unsigned long *)info->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k=0; k<size; k++)
|
||||
{
|
||||
if (*flash++ != 0xffffffff)
|
||||
{
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
/* print empty and read-only info */
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " ");
|
||||
#else
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
#endif
|
||||
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
short n;
|
||||
CONFIG_SYS_FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong)addr;
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
|
||||
|
||||
value = addr2[CONFIG_SYS_FLASH_READ0];
|
||||
|
||||
switch (value) {
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_EXCEL;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
|
||||
info->flash_id += FLASH_AMDL322T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
|
||||
info->flash_id += FLASH_AMDL322B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
|
||||
info->flash_id += FLASH_AMDL323T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000; break; /* => 8 MB */
|
||||
|
||||
#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
|
||||
info->flash_id += FLASH_SST800A;
|
||||
info->sector_count = 16;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
|
||||
info->flash_id += FLASH_SST160A;
|
||||
info->sector_count = 32;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
|
||||
info->flash_id += FLASH_SST320;
|
||||
info->sector_count = 64;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
|
||||
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
|
||||
info->flash_id += FLASH_SST640;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
#endif
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
while (i < info->sector_count) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
|
||||
/* set sector offsets for top boot block type */
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
|
||||
*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
for (i=0; i<50; i++)
|
||||
udelay(1000); /* wait 1 ms */
|
||||
} else {
|
||||
if (sect == s_first) {
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
}
|
||||
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
|
||||
while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
ulong *data_ptr = &data;
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
|
||||
{
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
277
root/package/utils/sysupgrade-helper/src/board/esd/common/fpga.c
Normal file
277
root/package/utils/sysupgrade-helper/src/board/esd/common/fpga.c
Normal file
|
|
@ -0,0 +1,277 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
#define DBG(x...) printf(x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
#define MAX_ONES 226
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_PRG
|
||||
# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
|
||||
# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
|
||||
# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
|
||||
# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
|
||||
# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
|
||||
#else
|
||||
# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
|
||||
# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
|
||||
# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
|
||||
# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
|
||||
# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
|
||||
#endif
|
||||
|
||||
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
|
||||
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
|
||||
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
|
||||
|
||||
#ifndef SET_FPGA
|
||||
# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
|
||||
#endif
|
||||
|
||||
#ifdef FPGA_PROG_ACTIVE_HIGH
|
||||
# define FPGA_PRG_LOW FPGA_PRG
|
||||
# define FPGA_PRG_HIGH 0
|
||||
#else
|
||||
# define FPGA_PRG_LOW 0
|
||||
# define FPGA_PRG_HIGH FPGA_PRG
|
||||
#endif
|
||||
|
||||
#define FPGA_CLK_LOW 0
|
||||
#define FPGA_CLK_HIGH FPGA_CLK
|
||||
|
||||
#define FPGA_DATA_LOW 0
|
||||
#define FPGA_DATA_HIGH FPGA_DATA
|
||||
|
||||
#define FPGA_WRITE_1 { \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
|
||||
|
||||
#define FPGA_WRITE_0 { \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
|
||||
|
||||
#ifndef FPGA_DONE_STATE
|
||||
# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
|
||||
#endif
|
||||
#ifndef FPGA_INIT_STATE
|
||||
# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
|
||||
#endif
|
||||
|
||||
|
||||
static int fpga_boot (const unsigned char *fpgadata, int size)
|
||||
{
|
||||
int i, index, len;
|
||||
int count;
|
||||
unsigned char b;
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
int j;
|
||||
#else
|
||||
int bit;
|
||||
#endif
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
/* search for preamble 0xFFFFFFFF */
|
||||
while (1) {
|
||||
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
|
||||
&& (fpgadata[index + 2] == 0xff)
|
||||
&& (fpgadata[index + 3] == 0xff))
|
||||
break; /* preamble found */
|
||||
else
|
||||
index++;
|
||||
}
|
||||
#else
|
||||
/* search for preamble 0xFF2X */
|
||||
for (index = 0; index < size - 1; index++) {
|
||||
if ((fpgadata[index] == 0xff)
|
||||
&& ((fpgadata[index + 1] & 0xf0) == 0x30))
|
||||
break;
|
||||
}
|
||||
index += 2;
|
||||
#endif
|
||||
|
||||
DBG ("FPGA: configdata starts at position 0x%x\n", index);
|
||||
DBG ("FPGA: length of fpga-data %d\n", size - index);
|
||||
|
||||
/*
|
||||
* Setup port pins for fpga programming
|
||||
*/
|
||||
#ifndef CONFIG_M5249
|
||||
out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
/* setup for output */
|
||||
out_be32 ((void *)GPIO0_TCR,
|
||||
in_be32 ((void *)GPIO0_TCR) |
|
||||
FPGA_PRG | FPGA_CLK | FPGA_DATA);
|
||||
#endif
|
||||
SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
|
||||
|
||||
DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/*
|
||||
* Init fpga by asserting and deasserting PROGRAM*
|
||||
*/
|
||||
SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
|
||||
|
||||
/* Wait for FPGA init line low */
|
||||
count = 0;
|
||||
while (FPGA_INIT_STATE) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout - 100us max, so use 3ms */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/* deassert PROGRAM* */
|
||||
SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
|
||||
|
||||
/* Wait for FPGA end of init period . */
|
||||
count = 0;
|
||||
while (!(FPGA_INIT_STATE)) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_HIGH;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
DBG ("write configuration data into fpga\n");
|
||||
/* write configuration-data into fpga... */
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
/*
|
||||
* Load uncompressed image into fpga
|
||||
*/
|
||||
for (i = index; i < size; i++) {
|
||||
b = fpgadata[i];
|
||||
for (j = 0; j < 8; j++) {
|
||||
if ((b & 0x80) == 0x80) {
|
||||
FPGA_WRITE_1;
|
||||
} else {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
b <<= 1;
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* send 0xff 0x20 */
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
|
||||
/*
|
||||
** Bit_DeCompression
|
||||
** Code 1 .. maxOnes : n '1's followed by '0'
|
||||
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
|
||||
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
|
||||
** 255 : '1'
|
||||
*/
|
||||
|
||||
for (i = index; i < size; i++) {
|
||||
b = fpgadata[i];
|
||||
if ((b >= 1) && (b <= MAX_ONES)) {
|
||||
for (bit = 0; bit < b; bit++) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
FPGA_WRITE_0;
|
||||
} else if (b == (MAX_ONES + 1)) {
|
||||
for (bit = 1; bit < b; bit++) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
|
||||
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
FPGA_WRITE_1;
|
||||
} else if (b == 255) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/*
|
||||
* Check if fpga's DONE signal - correctly booted ?
|
||||
*/
|
||||
|
||||
/* Wait for FPGA end of programming period . */
|
||||
count = 0;
|
||||
while (!(FPGA_DONE_STATE)) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("FPGA: Booting successful!\n");
|
||||
return 0;
|
||||
}
|
||||
375
root/package/utils/sysupgrade-helper/src/board/esd/common/lcd.c
Normal file
375
root/package/utils/sysupgrade-helper/src/board/esd/common/lcd.c
Normal file
|
|
@ -0,0 +1,375 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "asm/io.h"
|
||||
#include "lcd.h"
|
||||
|
||||
|
||||
extern int video_display_bitmap (ulong, int, int);
|
||||
|
||||
|
||||
int palette_index;
|
||||
int palette_value;
|
||||
int lcd_depth;
|
||||
unsigned char *glob_lcd_reg;
|
||||
unsigned char *glob_lcd_mem;
|
||||
|
||||
#if defined(CONFIG_SYS_LCD_ENDIAN)
|
||||
void lcd_setup(int lcd, int config)
|
||||
{
|
||||
if (lcd == 0) {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 0 (small)
|
||||
*/
|
||||
|
||||
/* set reset to low */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1) {
|
||||
/* big-endian */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
|
||||
} else {
|
||||
/* little-endian */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
|
||||
}
|
||||
udelay(10); /* wait 10us */
|
||||
/* set reset to high */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
|
||||
} else {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 1 (big)
|
||||
*/
|
||||
|
||||
/* set reset to low */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1) {
|
||||
/* big-endian */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
|
||||
} else {
|
||||
/* little-endian */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
|
||||
}
|
||||
udelay(10); /* wait 10us */
|
||||
/* set reset to high */
|
||||
out_be32((void*)GPIO0_OR,
|
||||
in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
|
||||
}
|
||||
|
||||
/*
|
||||
* CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
|
||||
}
|
||||
#endif /* CONFIG_SYS_LCD_ENDIAN */
|
||||
|
||||
|
||||
int lcd_bmp(uchar *logo_bmp)
|
||||
{
|
||||
int i;
|
||||
uchar *ptr;
|
||||
ushort *ptr2;
|
||||
ushort val;
|
||||
unsigned char *dst = NULL;
|
||||
int x, y;
|
||||
int width, height, bpp, colors, line_size;
|
||||
int header_size;
|
||||
unsigned char *bmp;
|
||||
unsigned char r, g, b;
|
||||
BITMAPINFOHEADER *bm_info;
|
||||
ulong len;
|
||||
|
||||
/*
|
||||
* Check for bmp mark 'BM'
|
||||
*/
|
||||
if (*(ushort *)logo_bmp != 0x424d) {
|
||||
/*
|
||||
* Decompress bmp image
|
||||
*/
|
||||
len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
|
||||
dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
|
||||
if (dst == NULL) {
|
||||
printf("Error: malloc for gunzip failed!\n");
|
||||
return 1;
|
||||
}
|
||||
if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
|
||||
(uchar *)logo_bmp, &len) != 0) {
|
||||
free(dst);
|
||||
return 1;
|
||||
}
|
||||
if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
|
||||
printf("Image could be truncated"
|
||||
" (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for bmp mark 'BM'
|
||||
*/
|
||||
if (*(ushort *)dst != 0x424d) {
|
||||
printf("LCD: Unknown image format!\n");
|
||||
free(dst);
|
||||
return 1;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Uncompressed BMP image, just use this pointer
|
||||
*/
|
||||
dst = (uchar *)logo_bmp;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get image info from bmp-header
|
||||
*/
|
||||
bm_info = (BITMAPINFOHEADER *)(dst + 14);
|
||||
bpp = LOAD_SHORT(bm_info->biBitCount);
|
||||
width = LOAD_LONG(bm_info->biWidth);
|
||||
height = LOAD_LONG(bm_info->biHeight);
|
||||
switch (bpp) {
|
||||
case 1:
|
||||
colors = 1;
|
||||
line_size = width >> 3;
|
||||
break;
|
||||
case 4:
|
||||
colors = 16;
|
||||
line_size = width >> 1;
|
||||
break;
|
||||
case 8:
|
||||
colors = 256;
|
||||
line_size = width;
|
||||
break;
|
||||
case 24:
|
||||
colors = 0;
|
||||
line_size = width * 3;
|
||||
break;
|
||||
default:
|
||||
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||
free(dst);
|
||||
return 1;
|
||||
}
|
||||
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
|
||||
|
||||
/*
|
||||
* Write color palette
|
||||
*/
|
||||
if ((colors <= 256) && (lcd_depth <= 8)) {
|
||||
ptr = (unsigned char *)(dst + 14 + 40);
|
||||
for (i = 0; i < colors; i++) {
|
||||
b = *ptr++;
|
||||
g = *ptr++;
|
||||
r = *ptr++;
|
||||
ptr++;
|
||||
S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Write bitmap data into framebuffer
|
||||
*/
|
||||
ptr = glob_lcd_mem;
|
||||
ptr2 = (ushort *)glob_lcd_mem;
|
||||
header_size = 14 + 40 + 4*colors; /* skip bmp header */
|
||||
for (y = 0; y < height; y++) {
|
||||
bmp = &dst[(height-1-y)*line_size + header_size];
|
||||
if (lcd_depth == 16) {
|
||||
if (bpp == 24) {
|
||||
for (x = 0; x < width; x++) {
|
||||
/*
|
||||
* Generate epson 16bpp fb-format
|
||||
* from 24bpp image
|
||||
*/
|
||||
b = *bmp++ >> 3;
|
||||
g = *bmp++ >> 2;
|
||||
r = *bmp++ >> 3;
|
||||
val = ((r & 0x1f) << 11) |
|
||||
((g & 0x3f) << 5) |
|
||||
(b & 0x1f);
|
||||
*ptr2++ = val;
|
||||
}
|
||||
} else if (bpp == 8) {
|
||||
for (x = 0; x < line_size; x++) {
|
||||
/* query rgb value from palette */
|
||||
ptr = (unsigned char *)(dst + 14 + 40);
|
||||
ptr += (*bmp++) << 2;
|
||||
b = *ptr++ >> 3;
|
||||
g = *ptr++ >> 2;
|
||||
r = *ptr++ >> 3;
|
||||
val = ((r & 0x1f) << 11) |
|
||||
((g & 0x3f) << 5) |
|
||||
(b & 0x1f);
|
||||
*ptr2++ = val;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (x = 0; x < line_size; x++)
|
||||
*ptr++ = *bmp++;
|
||||
}
|
||||
}
|
||||
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||
free(dst);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||
uchar *logo_bmp, ulong len)
|
||||
{
|
||||
int i;
|
||||
ushort s1dReg;
|
||||
uchar s1dValue;
|
||||
int reg_byte_swap;
|
||||
|
||||
/*
|
||||
* Detect epson
|
||||
*/
|
||||
out_8(&lcd_reg[0], 0x00);
|
||||
out_8(&lcd_reg[1], 0x00);
|
||||
|
||||
if (in_8(&lcd_reg[0]) == 0x1c) {
|
||||
/*
|
||||
* Big epson detected
|
||||
*/
|
||||
reg_byte_swap = FALSE;
|
||||
palette_index = 0x1e2;
|
||||
palette_value = 0x1e4;
|
||||
lcd_depth = 16;
|
||||
puts("LCD: S1D13806");
|
||||
} else if (in_8(&lcd_reg[1]) == 0x1c) {
|
||||
/*
|
||||
* Big epson detected (with register swap bug)
|
||||
*/
|
||||
reg_byte_swap = TRUE;
|
||||
palette_index = 0x1e3;
|
||||
palette_value = 0x1e5;
|
||||
lcd_depth = 16;
|
||||
puts("LCD: S1D13806S");
|
||||
} else if (in_8(&lcd_reg[0]) == 0x18) {
|
||||
/*
|
||||
* Small epson detected (704)
|
||||
*/
|
||||
reg_byte_swap = FALSE;
|
||||
palette_index = 0x15;
|
||||
palette_value = 0x17;
|
||||
lcd_depth = 8;
|
||||
puts("LCD: S1D13704");
|
||||
} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
|
||||
/*
|
||||
* Small epson detected (705)
|
||||
*/
|
||||
reg_byte_swap = FALSE;
|
||||
palette_index = 0x15;
|
||||
palette_value = 0x17;
|
||||
lcd_depth = 8;
|
||||
lcd_reg += 0x10000; /* add offset for 705 regs */
|
||||
puts("LCD: S1D13705");
|
||||
} else {
|
||||
out_8(&lcd_reg[0x1a], 0x00);
|
||||
udelay(1000);
|
||||
if (in_8(&lcd_reg[1]) == 0x0c) {
|
||||
/*
|
||||
* S1D13505 detected
|
||||
*/
|
||||
reg_byte_swap = TRUE;
|
||||
palette_index = 0x25;
|
||||
palette_value = 0x27;
|
||||
lcd_depth = 16;
|
||||
|
||||
puts("LCD: S1D13505");
|
||||
} else {
|
||||
puts("LCD: No controller detected!\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup lcd controller regs
|
||||
*/
|
||||
for (i = 0; i < reg_count; i++) {
|
||||
s1dReg = regs[i].Index;
|
||||
if (reg_byte_swap) {
|
||||
if ((s1dReg & 0x0001) == 0)
|
||||
s1dReg |= 0x0001;
|
||||
else
|
||||
s1dReg &= ~0x0001;
|
||||
}
|
||||
s1dValue = regs[i].Value;
|
||||
out_8(&lcd_reg[s1dReg], s1dValue);
|
||||
}
|
||||
|
||||
/*
|
||||
* Save reg & mem pointer for later usage (e.g. bmp command)
|
||||
*/
|
||||
glob_lcd_reg = lcd_reg;
|
||||
glob_lcd_mem = lcd_mem;
|
||||
|
||||
/*
|
||||
* Display bmp image
|
||||
*/
|
||||
return lcd_bmp(logo_bmp);
|
||||
}
|
||||
|
||||
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr;
|
||||
#ifdef CONFIG_VIDEO_SM501
|
||||
char *str;
|
||||
#endif
|
||||
if (argc != 2)
|
||||
return cmd_usage(cmdtp);
|
||||
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
#ifdef CONFIG_VIDEO_SM501
|
||||
str = getenv("bd_type");
|
||||
if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
|
||||
/*
|
||||
* SM501 available, use standard bmp command
|
||||
*/
|
||||
return video_display_bitmap(addr, 0, 0);
|
||||
} else {
|
||||
/*
|
||||
* No SM501 available, use esd epson bmp command
|
||||
*/
|
||||
return lcd_bmp((uchar *)addr);
|
||||
}
|
||||
#else
|
||||
return lcd_bmp((uchar *)addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
esdbmp, 2, 1, do_esdbmp,
|
||||
"display BMP image",
|
||||
"<imageAddr> - display image"
|
||||
);
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Neutralize little endians.
|
||||
*/
|
||||
#define SWAP_LONG(data) ((unsigned long) \
|
||||
(((unsigned long)(data) >> 24) | \
|
||||
((unsigned long)(data) << 24) | \
|
||||
(((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
|
||||
(((unsigned long)(data) << 8) & 0x00ff0000 )))
|
||||
#define SWAP_SHORT(data) ((unsigned short) \
|
||||
(((unsigned short)(data) >> 8 ) | \
|
||||
((unsigned short)(data) << 8 )))
|
||||
#define LOAD_LONG(data) SWAP_LONG(data)
|
||||
#define LOAD_SHORT(data) SWAP_SHORT(data)
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#define TRUE (!FALSE)
|
||||
#endif
|
||||
|
||||
#define S1D_WRITE_PALETTE(p,i,r,g,b) \
|
||||
{ \
|
||||
out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \
|
||||
out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \
|
||||
out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \
|
||||
out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \
|
||||
}
|
||||
|
||||
typedef struct
|
||||
{
|
||||
ushort Index;
|
||||
uchar Value;
|
||||
} S1D_REGS;
|
||||
|
||||
typedef struct /**** BMP file info structure ****/
|
||||
{
|
||||
unsigned int biSize; /* Size of info header */
|
||||
int biWidth; /* Width of image */
|
||||
int biHeight; /* Height of image */
|
||||
unsigned short biPlanes; /* Number of color planes */
|
||||
unsigned short biBitCount; /* Number of bits per pixel */
|
||||
unsigned int biCompression; /* Type of compression to use */
|
||||
unsigned int biSizeImage; /* Size of image data */
|
||||
int biXPelsPerMeter; /* X pixels per meter */
|
||||
int biYPelsPerMeter; /* Y pixels per meter */
|
||||
unsigned int biClrUsed; /* Number of colors used */
|
||||
unsigned int biClrImportant; /* Number of important colors */
|
||||
} BITMAPINFOHEADER;
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
#include <miiphy.h>
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
void lxt971_no_sleep(void)
|
||||
{
|
||||
unsigned short reg;
|
||||
|
||||
miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®);
|
||||
reg &= ~0x0040; /* disable sleep mode */
|
||||
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
|
||||
}
|
||||
#endif /* CONFIG_LXT971_NO_SLEEP */
|
||||
202
root/package/utils/sysupgrade-helper/src/board/esd/common/pci.c
Normal file
202
root/package/utils/sysupgrade-helper/src/board/esd/common/pci.c
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
|
||||
|
||||
u_long pci9054_iobase;
|
||||
|
||||
|
||||
#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
|
||||
#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_read_config_dword
|
||||
| Description: Read a PCI configuration register
|
||||
| Inputs:
|
||||
| hose PCI Controller
|
||||
| dev PCI Bus+Device+Function number
|
||||
| offset Configuration register number
|
||||
| value Address of the configuration register value
|
||||
| Return value:
|
||||
| 0 Successful
|
||||
+-----------------------------------------------------------------------------*/
|
||||
int pci9054_read_config_dword(struct pci_controller *hose,
|
||||
pci_dev_t dev, int offset, u32* value)
|
||||
{
|
||||
unsigned long conAdrVal;
|
||||
unsigned long val;
|
||||
|
||||
/* generate coded value for CON_ADR register */
|
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
|
||||
|
||||
/* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
|
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
|
||||
|
||||
/* Note: *pResult comes back as -1 if machine check happened */
|
||||
val = in32r(PCI_PRIMARY_CDR);
|
||||
|
||||
*value = (unsigned long) val;
|
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0);
|
||||
|
||||
if ((*(unsigned long *)0x50000304) & 0x60000000)
|
||||
{
|
||||
/* clear pci master/target abort bits */
|
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_write_config_dword
|
||||
| Description: Write a PCI configuration register.
|
||||
| Inputs:
|
||||
| hose PCI Controller
|
||||
| dev PCI Bus+Device+Function number
|
||||
| offset Configuration register number
|
||||
| Value Configuration register value
|
||||
| Return value:
|
||||
| 0 Successful
|
||||
| Updated for pass2 errata #6. Need to disable interrupts and clear the
|
||||
| PCICFGADR reg after writing the PCICFGDATA reg.
|
||||
+-----------------------------------------------------------------------------*/
|
||||
int pci9054_write_config_dword(struct pci_controller *hose,
|
||||
pci_dev_t dev, int offset, u32 value)
|
||||
{
|
||||
unsigned long conAdrVal;
|
||||
|
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
|
||||
|
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
|
||||
|
||||
out32r(PCI_PRIMARY_CDR, value);
|
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0);
|
||||
|
||||
/* clear pci master/target abort bits */
|
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DASA_SIM
|
||||
static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
|
||||
struct pci_config_table *_)
|
||||
{
|
||||
unsigned int iobase;
|
||||
unsigned short status = 0;
|
||||
unsigned char timer;
|
||||
|
||||
/*
|
||||
* Configure PLX PCI9054
|
||||
*/
|
||||
pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
|
||||
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
|
||||
|
||||
/* Check the latency timer for values >= 0x60.
|
||||
*/
|
||||
pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
|
||||
if (timer < 0x60)
|
||||
{
|
||||
pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
|
||||
}
|
||||
|
||||
/* Set I/O base register.
|
||||
*/
|
||||
pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
|
||||
pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
|
||||
|
||||
pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
|
||||
|
||||
if (pci9054_iobase == 0xffffffff)
|
||||
{
|
||||
printf("Error: Can not set I/O base register.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct pci_config_table pci9054_config_table[] = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
|
||||
pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
|
||||
CONFIG_SYS_ETH_IOBASE,
|
||||
PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
|
||||
#ifdef CONFIG_DASA_SIM
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
|
||||
pci_dasa_sim_config_pci9054 },
|
||||
#endif
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct pci_controller pci9054_hose = {
|
||||
config_table: pci9054_config_table,
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
struct pci_controller *hose = &pci9054_hose;
|
||||
|
||||
/*
|
||||
* Register the hose
|
||||
*/
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region(hose->regions + 0,
|
||||
0x00000000, 0x00000000, 0x01000000,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI Memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
0x00000000, 0xc0000000, 0x10000000,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
pci_set_ops(hose,
|
||||
pci_hose_read_config_byte_via_dword,
|
||||
pci_hose_read_config_word_via_dword,
|
||||
pci9054_read_config_dword,
|
||||
pci_hose_write_config_byte_via_dword,
|
||||
pci_hose_write_config_word_via_dword,
|
||||
pci9054_write_config_dword);
|
||||
|
||||
hose->region_count = 2;
|
||||
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
|
||||
* Memory: DRAM (MCLK=40.000 MHz)
|
||||
*/
|
||||
static S1D_REGS regs_13505_640_480_16bpp[] =
|
||||
{
|
||||
{0x1B,0x00}, /* Miscellaneous Register */
|
||||
{0x23,0x20}, /* Performance Enhancement Register 1 */
|
||||
{0x01,0x30}, /* Memory Configuration Register */
|
||||
{0x22,0x24}, /* Performance Enhancement Register 0 */
|
||||
{0x02,0x25}, /* Panel Type Register */
|
||||
{0x03,0x00}, /* MOD Rate Register */
|
||||
{0x04,0x4F}, /* Horizontal Display Width Register */
|
||||
{0x05,0x0c}, /* Horizontal Non-Display Period Register */
|
||||
{0x06,0x00}, /* HRTC/FPLINE Start Position Register */
|
||||
{0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
|
||||
{0x08,0xDF}, /* Vertical Display Height Register 0 */
|
||||
{0x09,0x01}, /* Vertical Display Height Register 1 */
|
||||
{0x0A,0x3E}, /* Vertical Non-Display Period Register */
|
||||
{0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
|
||||
{0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
|
||||
{0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
|
||||
{0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
|
||||
{0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
|
||||
{0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
|
||||
{0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
|
||||
{0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
|
||||
{0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
|
||||
{0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
|
||||
{0x16,0x80}, /* Memory Address Offset Register 0 */
|
||||
{0x17,0x02}, /* Memory Address Offset Register 1 */
|
||||
{0x18,0x00}, /* Pixel Panning Register */
|
||||
{0x19,0x01}, /* Clock Configuration Register */
|
||||
{0x1A,0x00}, /* Power Save Configuration Register */
|
||||
{0x1C,0x00}, /* MD Configuration Readback Register 0 */
|
||||
{0x1E,0x06}, /* General IO Pins Configuration Register 0 */
|
||||
{0x1F,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x20,0x00}, /* General IO Pins Control Register 0 */
|
||||
{0x21,0x00}, /* General IO Pins Control Register 1 */
|
||||
{0x23,0x20}, /* Performance Enhancement Register 1 */
|
||||
{0x0D,0x15}, /* Display Mode Register */
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Generic Header information generated by 13704CFG.EXE (Build 10)
|
||||
* Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13704_320_240_4bpp[] =
|
||||
{
|
||||
{ 0x00, 0x00 }, /* Revision Code Register */
|
||||
{ 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */
|
||||
{ 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */
|
||||
{ 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */
|
||||
{ 0x04, 0x27 }, /* Horizontal Panel Size Register */
|
||||
{ 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
|
||||
{ 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
|
||||
{ 0x07, 0x00 }, /* FPLINE Start Position Register */
|
||||
{ 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
|
||||
{ 0x09, 0x00 }, /* FPFRAME Start Position Register */
|
||||
{ 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
|
||||
{ 0x0B, 0x00 }, /* MOD Rate Register */
|
||||
{ 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
|
||||
{ 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
|
||||
{ 0x0E, 0x00 }, /* Not Used */
|
||||
{ 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
|
||||
{ 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
|
||||
{ 0x11, 0x00 }, /* Not Used */
|
||||
{ 0x12, 0x00 }, /* Memory Address Offset Register */
|
||||
{ 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
|
||||
{ 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
|
||||
{ 0x15, 0x00 }, /* Look-Up Table Address Register */
|
||||
{ 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
|
||||
{ 0x17, 0x00 }, /* Look-Up Table Data Register */
|
||||
{ 0x18, 0x01 }, /* GPIO Configuration Control Register */
|
||||
{ 0x19, 0x01 }, /* GPIO Status/Control Register */
|
||||
{ 0x1A, 0x00 }, /* Scratch Pad Register */
|
||||
{ 0x1B, 0x00 }, /* SwivelView Mode Register */
|
||||
{ 0x1C, 0xA0 }, /* Line Byte Count Register */
|
||||
{ 0x1D, 0x00 }, /* Not Used */
|
||||
{ 0x1E, 0x00 }, /* Not Used */
|
||||
{ 0x1F, 0x00 }, /* Not Used */
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Generic Header information generated by 13704CFG.EXE (Build 10)
|
||||
* Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13705_320_240_8bpp[] =
|
||||
{
|
||||
{ 0x00, 0x00 }, /* Revision Code Register */
|
||||
{ 0x01, 0x23 }, /* Mode Register 0 Register */
|
||||
{ 0x02, 0xE0 }, /* Mode Register 1 Register */
|
||||
{ 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */
|
||||
{ 0x04, 0x27 }, /* Horizontal Panel Size Register */
|
||||
{ 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
|
||||
{ 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
|
||||
{ 0x07, 0x00 }, /* FPLINE Start Position Register */
|
||||
{ 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
|
||||
{ 0x09, 0x01 }, /* FPFRAME Start Position Register */
|
||||
{ 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
|
||||
{ 0x0B, 0x00 }, /* MOD Rate Register */
|
||||
{ 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
|
||||
{ 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
|
||||
{ 0x0E, 0x00 }, /* Not Used */
|
||||
{ 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
|
||||
{ 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
|
||||
{ 0x11, 0x00 }, /* Not Used */
|
||||
{ 0x12, 0x00 }, /* Memory Address Offset Register */
|
||||
{ 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
|
||||
{ 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
|
||||
{ 0x15, 0x00 }, /* Look-Up Table Address Register */
|
||||
{ 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
|
||||
{ 0x17, 0x00 }, /* Look-Up Table Data Register */
|
||||
{ 0x18, 0x01 }, /* GPIO Configuration Control Register */
|
||||
{ 0x19, 0x01 }, /* GPIO Status/Control Register */
|
||||
{ 0x1A, 0x00 }, /* Scratch Pad Register */
|
||||
{ 0x1B, 0x00 }, /* SwivelView Mode Register */
|
||||
{ 0x1C, 0xFF }, /* Line Byte Count Register */
|
||||
{ 0x1D, 0x00 }, /* Not Used */
|
||||
{ 0x1E, 0x00 }, /* Not Used */
|
||||
{ 0x1F, 0x00 }, /* Not Used */
|
||||
};
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* File generated by S1D13806CFG.EXE
|
||||
* Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
|
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13806_1024_768_8bpp[] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x00}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0x00}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x01}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x55}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x7F}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x02}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x03}, /* LCD Display Mode Register */
|
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x00}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x10}, /* TV Output Control Register */
|
||||
{0x0060,0x03}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
};
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* File generated by S1D13806CFG.EXE
|
||||
* Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
|
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13806_320_240_4bpp[] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x08}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x08}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0x08}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x32}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x00}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x27}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x00}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x02}, /* LCD Display Mode Register */
|
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x50}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x00}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x10}, /* TV Output Control Register */
|
||||
{0x0060,0x03}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
};
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* File generated by S1D13806CFG.EXE
|
||||
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
|
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13806_640_480_16bpp[] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x18}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0x18}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x25}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x00}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x05}, /* LCD Display Mode Register */
|
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x10}, /* TV Output Control Register */
|
||||
{0x0060,0x05}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
};
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* File generated by S1D13806CFG.EXE
|
||||
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
|
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
|
||||
*/
|
||||
|
||||
static S1D_REGS regs_13806_640_320_16bpp[] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x18}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0x18}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x25}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x00}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x03}, /* LCD Display Mode Register (8bpp) */
|
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x10}, /* TV Output Control Register */
|
||||
{0x0060,0x05}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
};
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*******************************************************/
|
||||
/* file: lenval.c */
|
||||
/* abstract: This file contains routines for using */
|
||||
/* the lenVal data structure. */
|
||||
/*******************************************************/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include "lenval.h"
|
||||
#include "ports.h"
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: value
|
||||
* Description: Extract the long value from the lenval array.
|
||||
* Parameters: plvValue - ptr to lenval.
|
||||
* Returns: long - the extracted value.
|
||||
*****************************************************************************/
|
||||
long value( lenVal* plvValue )
|
||||
{
|
||||
long lValue; /* result to hold the accumulated result */
|
||||
short sIndex;
|
||||
|
||||
lValue = 0;
|
||||
for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
|
||||
{
|
||||
lValue <<= 8; /* shift the accumulated result */
|
||||
lValue |= plvValue->val[ sIndex]; /* get the last byte first */
|
||||
}
|
||||
|
||||
return( lValue );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: initLenVal
|
||||
* Description: Initialize the lenval array with the given value.
|
||||
* Assumes lValue is less than 256.
|
||||
* Parameters: plv - ptr to lenval.
|
||||
* lValue - the value to set.
|
||||
* Returns: void.
|
||||
*****************************************************************************/
|
||||
void initLenVal( lenVal* plv,
|
||||
long lValue )
|
||||
{
|
||||
plv->len = 1;
|
||||
plv->val[0] = (unsigned char)lValue;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: EqualLenVal
|
||||
* Description: Compare two lenval arrays with an optional mask.
|
||||
* Parameters: plvTdoExpected - ptr to lenval #1.
|
||||
* plvTdoCaptured - ptr to lenval #2.
|
||||
* plvTdoMask - optional ptr to mask (=0 if no mask).
|
||||
* Returns: short - 0 = mismatch; 1 = equal.
|
||||
*****************************************************************************/
|
||||
short EqualLenVal( lenVal* plvTdoExpected,
|
||||
lenVal* plvTdoCaptured,
|
||||
lenVal* plvTdoMask )
|
||||
{
|
||||
short sEqual;
|
||||
short sIndex;
|
||||
unsigned char ucByteVal1;
|
||||
unsigned char ucByteVal2;
|
||||
unsigned char ucByteMask;
|
||||
|
||||
sEqual = 1;
|
||||
sIndex = plvTdoExpected->len;
|
||||
|
||||
while ( sEqual && sIndex-- )
|
||||
{
|
||||
ucByteVal1 = plvTdoExpected->val[ sIndex ];
|
||||
ucByteVal2 = plvTdoCaptured->val[ sIndex ];
|
||||
if ( plvTdoMask )
|
||||
{
|
||||
ucByteMask = plvTdoMask->val[ sIndex ];
|
||||
ucByteVal1 &= ucByteMask;
|
||||
ucByteVal2 &= ucByteMask;
|
||||
}
|
||||
if ( ucByteVal1 != ucByteVal2 )
|
||||
{
|
||||
sEqual = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return( sEqual );
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: RetBit
|
||||
* Description: return the (byte, bit) of lv (reading from left to right).
|
||||
* Parameters: plv - ptr to lenval.
|
||||
* iByte - the byte to get the bit from.
|
||||
* iBit - the bit number (0=msb)
|
||||
* Returns: short - the bit value.
|
||||
*****************************************************************************/
|
||||
short RetBit( lenVal* plv,
|
||||
int iByte,
|
||||
int iBit )
|
||||
{
|
||||
/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
|
||||
/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
|
||||
return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: SetBit
|
||||
* Description: set the (byte, bit) of lv equal to val
|
||||
* Example: SetBit("00000000",byte, 1) equals "01000000".
|
||||
* Parameters: plv - ptr to lenval.
|
||||
* iByte - the byte to get the bit from.
|
||||
* iBit - the bit number (0=msb).
|
||||
* sVal - the bit value to set.
|
||||
* Returns: void.
|
||||
*****************************************************************************/
|
||||
void SetBit( lenVal* plv,
|
||||
int iByte,
|
||||
int iBit,
|
||||
short sVal )
|
||||
{
|
||||
unsigned char ucByteVal;
|
||||
unsigned char ucBitMask;
|
||||
|
||||
ucBitMask = (unsigned char)(1 << ( 7 - iBit ));
|
||||
ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
|
||||
|
||||
if ( sVal )
|
||||
{
|
||||
ucByteVal |= ucBitMask;
|
||||
}
|
||||
plv->val[ iByte ] = ucByteVal;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: AddVal
|
||||
* Description: add val1 to val2 and store in resVal;
|
||||
* assumes val1 and val2 are of equal length.
|
||||
* Parameters: plvResVal - ptr to result.
|
||||
* plvVal1 - ptr of addendum.
|
||||
* plvVal2 - ptr of addendum.
|
||||
* Returns: void.
|
||||
*****************************************************************************/
|
||||
void addVal( lenVal* plvResVal,
|
||||
lenVal* plvVal1,
|
||||
lenVal* plvVal2 )
|
||||
{
|
||||
unsigned char ucCarry;
|
||||
unsigned short usSum;
|
||||
unsigned short usVal1;
|
||||
unsigned short usVal2;
|
||||
short sIndex;
|
||||
|
||||
plvResVal->len = plvVal1->len; /* set up length of result */
|
||||
|
||||
/* start at least significant bit and add bytes */
|
||||
ucCarry = 0;
|
||||
sIndex = plvVal1->len;
|
||||
while ( sIndex-- )
|
||||
{
|
||||
usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */
|
||||
usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */
|
||||
|
||||
/* add the two bytes plus carry from previous addition */
|
||||
usSum = (unsigned short)( usVal1 + usVal2 + ucCarry );
|
||||
|
||||
/* set up carry for next byte */
|
||||
ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
|
||||
|
||||
/* set the i'th byte of the result */
|
||||
plvResVal->val[ sIndex ] = (unsigned char)usSum;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: readVal
|
||||
* Description: read from XSVF numBytes bytes of data into x.
|
||||
* Parameters: plv - ptr to lenval in which to put the bytes read.
|
||||
* sNumBytes - the number of bytes to read.
|
||||
* Returns: void.
|
||||
*****************************************************************************/
|
||||
void readVal( lenVal* plv,
|
||||
short sNumBytes )
|
||||
{
|
||||
unsigned char* pucVal;
|
||||
|
||||
plv->len = sNumBytes; /* set the length of the lenVal */
|
||||
for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
|
||||
{
|
||||
/* read a byte of data into the lenVal */
|
||||
readByte( pucVal );
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*******************************************************/
|
||||
/* file: lenval.h */
|
||||
/* abstract: This file contains a description of the */
|
||||
/* data structure "lenval". */
|
||||
/*******************************************************/
|
||||
|
||||
#ifndef lenval_dot_h
|
||||
#define lenval_dot_h
|
||||
|
||||
/* the lenVal structure is a byte oriented type used to store an */
|
||||
/* arbitrary length binary value. As an example, the hex value */
|
||||
/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */
|
||||
/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */
|
||||
|
||||
/* maximum length (in bytes) of value to read in */
|
||||
/* this needs to be at least 4, and longer than the */
|
||||
/* length of the longest SDR instruction. If there is, */
|
||||
/* only 1 device in the chain, MAX_LEN must be at least */
|
||||
/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */
|
||||
/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */
|
||||
/* devices MAX_LEN must be 7, etc.. */
|
||||
/* You can safely set MAX_LEN to a smaller number if you*/
|
||||
/* know how many devices will be in your chain. */
|
||||
#define MAX_LEN 7000
|
||||
|
||||
|
||||
typedef struct var_len_byte
|
||||
{
|
||||
short len; /* number of chars in this value */
|
||||
unsigned char val[MAX_LEN+1]; /* bytes of data */
|
||||
} lenVal;
|
||||
|
||||
|
||||
/* return the long representation of a lenVal */
|
||||
extern long value(lenVal *x);
|
||||
|
||||
/* set lenVal equal to value */
|
||||
extern void initLenVal(lenVal *x, long value);
|
||||
|
||||
/* check if expected equals actual (taking the mask into account) */
|
||||
extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
|
||||
|
||||
/* add val1+val2 and put the result in resVal */
|
||||
extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
|
||||
|
||||
/* return the (byte, bit) of lv (reading from left to right) */
|
||||
extern short RetBit(lenVal *lv, int byte, int bit);
|
||||
|
||||
/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
|
||||
equals "01000000" */
|
||||
extern void SetBit(lenVal *lv, int byte, int bit, short val);
|
||||
|
||||
/* read from XSVF numBytes bytes of data into x */
|
||||
extern void readVal(lenVal *x, short numBytes);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*****************************************************************************
|
||||
* File: micro.h
|
||||
* Description: This header file contains the function prototype to the
|
||||
* primary interface function for the XSVF player.
|
||||
* Usage: FIRST - PORTS.C
|
||||
* Customize the ports.c function implementations to establish
|
||||
* the correct protocol for communicating with your JTAG ports
|
||||
* (setPort() and readTDOBit()) and tune the waitTime() delay
|
||||
* function. Also, establish access to the XSVF data source
|
||||
* in the readByte() function.
|
||||
* FINALLY - Call xsvfExecute().
|
||||
*****************************************************************************/
|
||||
#ifndef XSVF_MICRO_H
|
||||
#define XSVF_MICRO_H
|
||||
|
||||
/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
|
||||
#define XSVF_LEGACY_SUCCESS 1
|
||||
#define XSVF_LEGACY_ERROR 0
|
||||
|
||||
/* 4.04 [NEW] Error codes for xsvfExecute. */
|
||||
/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
|
||||
#define XSVF_ERROR_NONE 0
|
||||
#define XSVF_ERROR_UNKNOWN 1
|
||||
#define XSVF_ERROR_TDOMISMATCH 2
|
||||
#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
|
||||
#define XSVF_ERROR_ILLEGALCMD 4
|
||||
#define XSVF_ERROR_ILLEGALSTATE 5
|
||||
#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
|
||||
/* Insert new errors here */
|
||||
#define XSVF_ERROR_LAST 7
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: xsvfExecute
|
||||
* Description: Process, interpret, and apply the XSVF commands.
|
||||
* See port.c:readByte for source of XSVF data.
|
||||
* Parameters: none.
|
||||
* Returns: int - For error codes see above.
|
||||
*****************************************************************************/
|
||||
int xsvfExecute(void);
|
||||
|
||||
#endif /* XSVF_MICRO_H */
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*******************************************************/
|
||||
/* file: ports.c */
|
||||
/* abstract: This file contains the routines to */
|
||||
/* output values on the JTAG ports, to read */
|
||||
/* the TDO bit, and to read a byte of data */
|
||||
/* from the prom */
|
||||
/* */
|
||||
/*******************************************************/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "ports.h"
|
||||
|
||||
static unsigned long output = 0;
|
||||
static int filepos = 0;
|
||||
static int oldstate = 0;
|
||||
static int newstate = 0;
|
||||
static int readptr = 0;
|
||||
|
||||
extern const unsigned char *xsvfdata;
|
||||
|
||||
/* if in debugging mode, then just set the variables */
|
||||
void setPort(short p,short val)
|
||||
{
|
||||
if (p==TMS) {
|
||||
if (val) {
|
||||
output |= JTAG_TMS;
|
||||
} else {
|
||||
output &= ~JTAG_TMS;
|
||||
}
|
||||
}
|
||||
if (p==TDI) {
|
||||
if (val) {
|
||||
output |= JTAG_TDI;
|
||||
} else {
|
||||
output &= ~JTAG_TDI;
|
||||
}
|
||||
}
|
||||
if (p==TCK) {
|
||||
if (val) {
|
||||
output |= JTAG_TCK;
|
||||
} else {
|
||||
output &= ~JTAG_TCK;
|
||||
}
|
||||
out_be32((void *)GPIO0_OR, output);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* toggle tck LH */
|
||||
void pulseClock(void)
|
||||
{
|
||||
setPort(TCK,0); /* set the TCK port to low */
|
||||
setPort(TCK,1); /* set the TCK port to high */
|
||||
}
|
||||
|
||||
|
||||
/* read in a byte of data from the prom */
|
||||
void readByte(unsigned char *data)
|
||||
{
|
||||
/* pretend reading using a file */
|
||||
*data = xsvfdata[readptr++];
|
||||
newstate = filepos++ >> 10;
|
||||
if (newstate != oldstate) {
|
||||
printf("%4d kB\r\r\r\r", newstate);
|
||||
oldstate = newstate;
|
||||
}
|
||||
}
|
||||
|
||||
/* read the TDO bit from port */
|
||||
unsigned char readTDOBit(void)
|
||||
{
|
||||
unsigned long inputs;
|
||||
|
||||
inputs = in_be32((void *)GPIO0_IR);
|
||||
if (inputs & JTAG_TDO)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Wait at least the specified number of microsec. */
|
||||
/* Use a timer if possible; otherwise estimate the number of instructions */
|
||||
/* necessary to be run based on the microcontroller speed. For this example */
|
||||
/* we pulse the TCK port a number of times based on the processor speed. */
|
||||
void waitTime(long microsec)
|
||||
{
|
||||
udelay(microsec); /* esd */
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*******************************************************/
|
||||
/* file: ports.h */
|
||||
/* abstract: This file contains extern declarations */
|
||||
/* for providing stimulus to the JTAG ports.*/
|
||||
/*******************************************************/
|
||||
|
||||
#ifndef ports_dot_h
|
||||
#define ports_dot_h
|
||||
|
||||
/* these constants are used to send the appropriate ports to setPort */
|
||||
/* they should be enumerated types, but some of the microcontroller */
|
||||
/* compilers don't like enumerated types */
|
||||
#define TCK (short) 0
|
||||
#define TMS (short) 1
|
||||
#define TDI (short) 2
|
||||
|
||||
/*
|
||||
* Use CONFIG_SYS_FPGA_xxx defines from board include file.
|
||||
*/
|
||||
#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */
|
||||
#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */
|
||||
#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */
|
||||
#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */
|
||||
|
||||
/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
|
||||
void setPort(short p, short val);
|
||||
|
||||
/* read the TDO bit and store it in val */
|
||||
unsigned char readTDOBit(void);
|
||||
|
||||
/* make clock go down->up->down*/
|
||||
void pulseClock(void);
|
||||
|
||||
/* read the next byte of data from the xsvf file */
|
||||
void readByte(unsigned char *data);
|
||||
|
||||
void waitTime(long microsec);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
|
||||
/*
|
||||
* Setup GPIO pins
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg |
|
||||
((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
|
||||
CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
|
||||
|
||||
/* set output pins to high */
|
||||
out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
|
||||
/* setup for output (LED=off) */
|
||||
out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) unused
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
/*
|
||||
* Select cts (and not dsr) on uart1
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof(str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming CPCI2DP");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
printf(" (Ver 1.0)");
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable (unsigned dev_addr, int state) {
|
||||
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO_SINT2. */
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO_SINT2. */
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32((void *)GPIO0_OR) &
|
||||
CONFIG_SYS_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts ("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
eepwren, 2, 0, do_eep_wren,
|
||||
"Enable / disable / query EEPROM write access",
|
||||
""
|
||||
);
|
||||
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
/* printf("PB1CR = %x\n", pbcr); */
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-monitor_flash_len,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
|
||||
COBJS += ../common/cmd_loadpci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,783 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <pci.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void __ft_board_setup(void *blob, bd_t *bd);
|
||||
|
||||
#undef FPGA_DEBUG
|
||||
|
||||
/* fpga configuration data - generated by bin2cc */
|
||||
const unsigned char fpgadata[] =
|
||||
{
|
||||
#if defined(CONFIG_CPCI405_VER2)
|
||||
# if defined(CONFIG_CPCI405AB)
|
||||
# include "fpgadata_cpci405ab.c"
|
||||
# else
|
||||
# include "fpgadata_cpci4052.c"
|
||||
# endif
|
||||
#else
|
||||
# include "fpgadata_cpci405.c"
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
#include "../common/auto_update.h"
|
||||
|
||||
#if defined(CONFIG_CPCI405AB)
|
||||
au_image_t au_image[] = {
|
||||
{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
|
||||
{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
|
||||
{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
|
||||
{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
|
||||
{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
|
||||
};
|
||||
#else
|
||||
#if defined(CONFIG_CPCI405_VER2)
|
||||
au_image_t au_image[] = {
|
||||
{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
|
||||
{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
|
||||
{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
|
||||
{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
|
||||
{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
|
||||
};
|
||||
#else
|
||||
au_image_t au_image[] = {
|
||||
{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
|
||||
{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
|
||||
{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
|
||||
{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
|
||||
{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
|
||||
|
||||
/* Prototypes */
|
||||
int cpci405_version(void);
|
||||
void lxt971_no_sleep(void);
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifndef CONFIG_CPCI405_VER2
|
||||
int index, len, i;
|
||||
int status;
|
||||
#endif
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void)get_clocks();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init();
|
||||
console_init_f();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* First pull fpga-prg pin low,
|
||||
* to disable fpga logic (on version 2 board)
|
||||
*/
|
||||
out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
|
||||
out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
|
||||
out_be32((void *)GPIO0_OR, 0); /* pull prg low */
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
#ifndef CONFIG_CPCI405_VER2
|
||||
if (cpci405_version() == 1) {
|
||||
status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
|
||||
if (status != 0) {
|
||||
/* booting FPGA failed */
|
||||
#ifndef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void)get_clocks();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init();
|
||||
console_init_f();
|
||||
#endif
|
||||
printf("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf("(Timeout: INIT not low after "
|
||||
"asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf("(Timeout: INIT not high after "
|
||||
"deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf("(Timeout: DONE not high after "
|
||||
"programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf("Rebooting in %2d seconds \r",i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay(1000);
|
||||
}
|
||||
putc('\n');
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
}
|
||||
#endif /* !CONFIG_CPCI405_VER2 */
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
|
||||
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
#if defined(CONFIG_CPCI405_6U)
|
||||
if (cpci405_version() == 3) {
|
||||
mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
|
||||
} else {
|
||||
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
}
|
||||
#else
|
||||
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
|
||||
#endif
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
|
||||
* INT0 highest priority */
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ctermm2(void)
|
||||
{
|
||||
#if defined(CONFIG_CPCI405_VER2)
|
||||
return 0; /* no, board is cpci405 */
|
||||
#else
|
||||
if ((in_8((void*)0xf0000400) == 0x00) &&
|
||||
(in_8((void*)0xf0000401) == 0x01))
|
||||
return 0; /* no, board is cpci405 */
|
||||
else
|
||||
return -1; /* yes, board is cterm-m2 */
|
||||
#endif
|
||||
}
|
||||
|
||||
int cpci405_host(void)
|
||||
{
|
||||
if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
|
||||
return -1; /* yes, board is cpci405 host */
|
||||
else
|
||||
return 0; /* no, board is cpci405 adapter */
|
||||
}
|
||||
|
||||
int cpci405_version(void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
unsigned long value;
|
||||
|
||||
/*
|
||||
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
|
||||
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
|
||||
udelay(1000); /* wait some time before reading input */
|
||||
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
|
||||
|
||||
/*
|
||||
* Restore GPIO settings
|
||||
*/
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg);
|
||||
|
||||
switch (value) {
|
||||
case 0x00180000:
|
||||
/* CS2==1 && CS3==1 -> version 1 */
|
||||
return 1;
|
||||
case 0x00080000:
|
||||
/* CS2==0 && CS3==1 -> version 2 */
|
||||
return 2;
|
||||
case 0x00100000:
|
||||
/* CS2==1 && CS3==0 -> version 3 or 6U board */
|
||||
return 3;
|
||||
case 0x00000000:
|
||||
/* CS2==0 && CS3==0 -> version 4 */
|
||||
return 4;
|
||||
default:
|
||||
/* should not be reached! */
|
||||
return 2;
|
||||
}
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
#if defined(CONFIG_CPCI405_VER2)
|
||||
{
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
int status;
|
||||
int index;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* On CPCI-405 version 2 the environment is saved in eeprom!
|
||||
* FPGA can be gzip compressed (malloc) and booted this late.
|
||||
*/
|
||||
if (cpci405_version() >= 2) {
|
||||
/*
|
||||
* Setup GPIO pins (CS6+CS7 as GPIO)
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
|
||||
|
||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
|
||||
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
|
||||
(uchar *)fpgadata, &len) != 0) {
|
||||
printf("GUNZIP ERROR - must RESET board to recover\n");
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
status = fpga_boot(dst, len);
|
||||
if (status != 0) {
|
||||
printf("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf("(Timeout: INIT not low after "
|
||||
"asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf("(Timeout: INIT not high after "
|
||||
"deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf("(Timeout: DONE not high after "
|
||||
"programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = dst[index];
|
||||
printf("FPGA: %s\n", &(dst[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf("Rebooting in %2d seconds \r", i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay(1000);
|
||||
}
|
||||
putc('\n');
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/* restore gpio/cs settings */
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg);
|
||||
|
||||
puts("FPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = dst[index];
|
||||
printf("%s ", &(dst[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
free(dst);
|
||||
|
||||
/*
|
||||
* Reset FPGA via FPGA_DATA pin
|
||||
*/
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK);
|
||||
udelay(1000); /* wait 1ms */
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
#if defined(CONFIG_CPCI405_6U)
|
||||
#error HIER GETH ES WEITER MIT IO ACCESSORS
|
||||
if (cpci405_version() == 3) {
|
||||
/*
|
||||
* Enable outputs in fpga on version 3 board
|
||||
*/
|
||||
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
|
||||
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
|
||||
CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
|
||||
|
||||
/*
|
||||
* Set outputs to 0
|
||||
*/
|
||||
out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
|
||||
|
||||
/*
|
||||
* Reset external DUART
|
||||
*/
|
||||
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
|
||||
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
|
||||
CONFIG_SYS_FPGA_MODE_DUART_RESET);
|
||||
udelay(100);
|
||||
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
|
||||
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
|
||||
~CONFIG_SYS_FPGA_MODE_DUART_RESET);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
puts("\n*** U-Boot Version does not match Board Version!\n");
|
||||
puts("*** CPCI-405 Version 1.x detected!\n");
|
||||
puts("*** Please use correct U-Boot version "
|
||||
"(CPCI405 instead of CPCI4052)!\n\n");
|
||||
}
|
||||
}
|
||||
#else /* CONFIG_CPCI405_VER2 */
|
||||
if (cpci405_version() >= 2) {
|
||||
puts("\n*** U-Boot Version does not match Board Version!\n");
|
||||
puts("*** CPCI-405 Board Version 2.x detected!\n");
|
||||
puts("*** Please use correct U-Boot version "
|
||||
"(CPCI4052 instead of CPCI405)!\n\n");
|
||||
}
|
||||
#endif /* CONFIG_CPCI405_VER2 */
|
||||
|
||||
/*
|
||||
* Select cts (and not dsr) on uart1
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifndef CONFIG_CPCI405_VER2
|
||||
int index;
|
||||
int len;
|
||||
#endif
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof(str));
|
||||
unsigned short ver;
|
||||
|
||||
puts("Board: ");
|
||||
|
||||
if (i == -1)
|
||||
puts("### No HW ID - assuming CPCI405");
|
||||
else
|
||||
puts(str);
|
||||
|
||||
ver = cpci405_version();
|
||||
printf(" (Ver %d.x, ", ver);
|
||||
|
||||
if (ctermm2()) {
|
||||
char str[4];
|
||||
|
||||
/*
|
||||
* Read board-id and save in env-variable
|
||||
*/
|
||||
sprintf(str, "%d", *(unsigned char *)0xf0000400);
|
||||
setenv("boardid", str);
|
||||
printf("CTERM-M2 - Id=%s)", str);
|
||||
} else {
|
||||
if (cpci405_host())
|
||||
puts("PCI Host Version)");
|
||||
else
|
||||
puts("PCI Adapter Version)");
|
||||
}
|
||||
|
||||
#ifndef CONFIG_CPCI405_VER2
|
||||
puts("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
#endif
|
||||
|
||||
putc('\n');
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_LXT971_NO_SLEEP)
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) { /* assert RESET */
|
||||
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
|
||||
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
|
||||
~CONFIG_SYS_FPGA_MODE_CF_RESET);
|
||||
} else { /* release RESET */
|
||||
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
|
||||
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
|
||||
CONFIG_SYS_FPGA_MODE_CF_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
unsigned char int_line = 0xff;
|
||||
|
||||
/*
|
||||
* Write pci interrupt line register (cpci405 specific)
|
||||
*/
|
||||
switch (PCI_DEV(dev) & 0x03) {
|
||||
case 0:
|
||||
int_line = 27 + 2;
|
||||
break;
|
||||
case 1:
|
||||
int_line = 27 + 3;
|
||||
break;
|
||||
case 2:
|
||||
int_line = 27 + 0;
|
||||
break;
|
||||
case 3:
|
||||
int_line = 27 + 1;
|
||||
break;
|
||||
}
|
||||
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
||||
}
|
||||
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
hose->fixup_irq = cpci405_pci_fixup_irq;
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int rc;
|
||||
|
||||
__ft_board_setup(blob, bd);
|
||||
|
||||
/*
|
||||
* Disable PCI in adapter mode.
|
||||
*/
|
||||
if (!cpci405_host()) {
|
||||
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
|
||||
"disabled", sizeof("disabled"), 1);
|
||||
if (rc) {
|
||||
printf("Unable to update property status in PCI node, "
|
||||
"err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
||||
#if defined(CONFIG_CPCI405AB)
|
||||
#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
||||
CONFIG_SYS_FPGA_MODE), \
|
||||
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
||||
CONFIG_SYS_FPGA_MODE)) | \
|
||||
CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
|
||||
|
||||
#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
||||
CONFIG_SYS_FPGA_MODE), \
|
||||
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
||||
CONFIG_SYS_FPGA_MODE)) & \
|
||||
~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
|
||||
|
||||
#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
||||
CONFIG_SYS_FPGA_STATUS)) & \
|
||||
CONFIG_SYS_FPGA_MODE_1WIRE)
|
||||
|
||||
/*
|
||||
* Generate a 1-wire reset, return 1 if no presence detect was found,
|
||||
* return 0 otherwise.
|
||||
* (NOTE: Does not handle alarm presence from DS2404/DS1994)
|
||||
*/
|
||||
int OWTouchReset(void)
|
||||
{
|
||||
int result;
|
||||
|
||||
ONE_WIRE_CLEAR;
|
||||
udelay(480);
|
||||
ONE_WIRE_SET;
|
||||
udelay(70);
|
||||
|
||||
result = ONE_WIRE_GET;
|
||||
|
||||
udelay(410);
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* Send 1 a 1-wire write bit.
|
||||
* Provide 10us recovery time.
|
||||
*/
|
||||
void OWWriteBit(int bit)
|
||||
{
|
||||
if (bit) {
|
||||
/*
|
||||
* write '1' bit
|
||||
*/
|
||||
ONE_WIRE_CLEAR;
|
||||
udelay(6);
|
||||
ONE_WIRE_SET;
|
||||
udelay(64);
|
||||
} else {
|
||||
/*
|
||||
* write '0' bit
|
||||
*/
|
||||
ONE_WIRE_CLEAR;
|
||||
udelay(60);
|
||||
ONE_WIRE_SET;
|
||||
udelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a bit from the 1-wire bus and return it.
|
||||
* Provide 10us recovery time.
|
||||
*/
|
||||
int OWReadBit(void)
|
||||
{
|
||||
int result;
|
||||
|
||||
ONE_WIRE_CLEAR;
|
||||
udelay(6);
|
||||
ONE_WIRE_SET;
|
||||
udelay(9);
|
||||
|
||||
result = ONE_WIRE_GET;
|
||||
|
||||
udelay(55);
|
||||
return result;
|
||||
}
|
||||
|
||||
void OWWriteByte(int data)
|
||||
{
|
||||
int loop;
|
||||
|
||||
for (loop = 0; loop < 8; loop++) {
|
||||
OWWriteBit(data & 0x01);
|
||||
data >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
int OWReadByte(void)
|
||||
{
|
||||
int loop, result = 0;
|
||||
|
||||
for (loop = 0; loop < 8; loop++) {
|
||||
result >>= 1;
|
||||
if (OWReadBit())
|
||||
result |= 0x80;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned short val;
|
||||
int result;
|
||||
int i;
|
||||
unsigned char ow_id[6];
|
||||
char str[32];
|
||||
|
||||
/*
|
||||
* Clear 1-wire bit (open drain with pull-up)
|
||||
*/
|
||||
val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
|
||||
CONFIG_SYS_FPGA_MODE));
|
||||
val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
|
||||
out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
|
||||
CONFIG_SYS_FPGA_MODE), val);
|
||||
|
||||
result = OWTouchReset();
|
||||
if (result != 0)
|
||||
puts("No 1-wire device detected!\n");
|
||||
|
||||
OWWriteByte(0x33); /* send read rom command */
|
||||
OWReadByte(); /* skip family code ( == 0x01) */
|
||||
for (i = 0; i < 6; i++)
|
||||
ow_id[i] = OWReadByte();
|
||||
OWReadByte(); /* read crc */
|
||||
|
||||
sprintf(str, "%02X%02X%02X%02X%02X%02X",
|
||||
ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
|
||||
printf("Setting environment variable 'ow_id' to %s\n", str);
|
||||
setenv("ow_id", str);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
onewire, 1, 1, do_onewire,
|
||||
"Read 1-write ID",
|
||||
""
|
||||
);
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
|
||||
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
|
||||
|
||||
/*
|
||||
* Write backplane ip-address...
|
||||
*/
|
||||
int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
char *buf;
|
||||
ulong crc;
|
||||
char str[32];
|
||||
char *ptr;
|
||||
IPaddr_t ipaddr;
|
||||
|
||||
buf = malloc(CONFIG_ENV_SIZE_2);
|
||||
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
|
||||
(uchar *)buf, CONFIG_ENV_SIZE_2))
|
||||
puts("\nError reading backplane EEPROM!\n");
|
||||
else {
|
||||
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
|
||||
if (crc != *(ulong *)buf) {
|
||||
printf("ERROR: crc mismatch %08lx %08lx\n",
|
||||
crc, *(ulong *)buf);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find bp_ip
|
||||
*/
|
||||
ptr = strstr(buf+4, "bp_ip=");
|
||||
if (ptr == NULL) {
|
||||
printf("ERROR: bp_ip not found!\n");
|
||||
return -1;
|
||||
}
|
||||
ptr += 6;
|
||||
ipaddr = string_to_ip(ptr);
|
||||
|
||||
/*
|
||||
* Update whole ip-addr
|
||||
*/
|
||||
sprintf(str, "%pI4", &ipaddr);
|
||||
setenv("ipaddr", str);
|
||||
printf("Updated ip_addr from bp_eeprom to %s!\n", str);
|
||||
}
|
||||
|
||||
free(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
getbpip, 1, 1, do_get_bpip,
|
||||
"Update IP-Address with Backplane IP-Address",
|
||||
""
|
||||
);
|
||||
|
||||
/*
|
||||
* Set and print backplane ip...
|
||||
*/
|
||||
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
char *buf;
|
||||
char str[32];
|
||||
ulong crc;
|
||||
|
||||
if (argc < 2) {
|
||||
puts("ERROR!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("Setting bp_ip to %s\n", argv[1]);
|
||||
buf = malloc(CONFIG_ENV_SIZE_2);
|
||||
memset(buf, 0, CONFIG_ENV_SIZE_2);
|
||||
sprintf(str, "bp_ip=%s", argv[1]);
|
||||
strcpy(buf+4, str);
|
||||
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
|
||||
*(ulong *)buf = crc;
|
||||
|
||||
if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
|
||||
0, (uchar *)buf, CONFIG_ENV_SIZE_2))
|
||||
puts("\nError writing backplane EEPROM!\n");
|
||||
|
||||
free(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
setbpip, 2, 1, do_set_bpip,
|
||||
"Write Backplane IP-Address",
|
||||
""
|
||||
);
|
||||
|
||||
#endif /* CONFIG_CPCI405AB */
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long calc_size(unsigned long size)
|
||||
{
|
||||
switch (size) {
|
||||
case 1 << 20:
|
||||
return 0;
|
||||
case 2 << 20:
|
||||
return 1;
|
||||
case 4 << 20:
|
||||
return 2;
|
||||
case 8 << 20:
|
||||
return 3;
|
||||
case 16 << 20:
|
||||
return 4;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0, size_b1;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0, base_b1;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
base_b0 = FLASH_BASE0_PRELIM;
|
||||
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0 << 20);
|
||||
}
|
||||
|
||||
base_b1 = FLASH_BASE1_PRELIM;
|
||||
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
if (size_b1) {
|
||||
if (size_b1 < (1 << 20)) {
|
||||
/* minimum CS size on PPC405GP is 1MB !!! */
|
||||
size_b1 = 1 << 20;
|
||||
}
|
||||
base_b1 = -size_b1;
|
||||
mtdcr (EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr (EBC0_CFGDATA);
|
||||
mtdcr (EBC0_CFGADDR, PB0CR);
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
|
||||
mtdcr (EBC0_CFGDATA, pbcr);
|
||||
#if 0 /* test-only */
|
||||
printf("size_b1=%x base_b1=%x PB1CR = %x\n",
|
||||
size_b1, base_b1, pbcr); /* test-only */
|
||||
#endif
|
||||
}
|
||||
|
||||
if (size_b0) {
|
||||
if (size_b0 < (1 << 20)) {
|
||||
/* minimum CS size on PPC405GP is 1MB !!! */
|
||||
size_b0 = 1 << 20;
|
||||
}
|
||||
base_b0 = base_b1 - size_b0;
|
||||
mtdcr (EBC0_CFGADDR, PB1CR);
|
||||
pbcr = mfdcr (EBC0_CFGDATA);
|
||||
mtdcr (EBC0_CFGADDR, PB1CR);
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
|
||||
mtdcr (EBC0_CFGDATA, pbcr);
|
||||
#if 0 /* test-only */
|
||||
printf("size_b0=%x base_b0=%x PB0CR = %x\n",
|
||||
size_b0, base_b0, pbcr); /* test-only */
|
||||
#endif
|
||||
}
|
||||
|
||||
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
|
||||
|
||||
flash_get_offsets (base_b0, &flash_info[0]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
base_b0 + size_b0 - monitor_flash_len,
|
||||
base_b0 + size_b0 - 1, &flash_info[0]);
|
||||
|
||||
if (size_b1) {
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
|
||||
|
||||
flash_get_offsets (base_b1, &flash_info[1]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
base_b1 + size_b1 - monitor_flash_len,
|
||||
base_b1 + size_b1 - 1, &flash_info[1]);
|
||||
/* monitor protection OFF by default (one is enough) */
|
||||
flash_protect (FLAG_PROTECT_CLEAR,
|
||||
base_b0 + size_b0 - monitor_flash_len,
|
||||
base_b0 + size_b0 - 1, &flash_info[0]);
|
||||
} else {
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].sector_count = -1;
|
||||
}
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
flash_info[1].size = size_b1;
|
||||
|
||||
return (size_b0 + size_b1);
|
||||
}
|
||||
|
|
@ -0,0 +1,683 @@
|
|||
0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
|
||||
0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
|
||||
0x63, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35, 0x32,
|
||||
0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
|
||||
0x73, 0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31,
|
||||
0x30, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
|
||||
0x30, 0x31, 0x2f, 0x30, 0x35, 0x2f, 0x31, 0x30,
|
||||
0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x31,
|
||||
0x35, 0x3a, 0x32, 0x33, 0x00, 0x65, 0xe2, 0x01,
|
||||
0x00, 0x00, 0x15, 0x08, 0xff, 0x30, 0xe8, 0x01,
|
||||
0x01, 0x01, 0x01, 0xe7, 0xe6, 0x04, 0x01, 0x02,
|
||||
0x11, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
|
||||
0x03, 0x04, 0x04, 0x0b, 0x02, 0x02, 0x01, 0x04,
|
||||
0x02, 0x01, 0x0b, 0x07, 0x01, 0x01, 0x0d, 0x03,
|
||||
0x05, 0x09, 0x03, 0x05, 0x03, 0x05, 0x03, 0x0b,
|
||||
0x13, 0x01, 0x06, 0xe5, 0xe5, 0x02, 0x03, 0x0c,
|
||||
0x01, 0xe6, 0x11, 0x08, 0x13, 0x16, 0x08, 0x1e,
|
||||
0x0b, 0xe5, 0xe6, 0x0e, 0x09, 0x09, 0x09, 0x09,
|
||||
0x0b, 0x07, 0xe6, 0x08, 0x02, 0xe5, 0x04, 0x01,
|
||||
0xe6, 0x04, 0x0e, 0x01, 0x01, 0x14, 0x09, 0x09,
|
||||
0x09, 0x09, 0x05, 0x05, 0xe5, 0xe6, 0x04, 0x03,
|
||||
0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0x0c, 0xe5,
|
||||
0x5b, 0x01, 0x01, 0x05, 0x01, 0x11, 0x02, 0xe5,
|
||||
0xe5, 0x48, 0x13, 0x1a, 0x01, 0xe6, 0x3e, 0x0b,
|
||||
0x10, 0x03, 0x05, 0x13, 0x03, 0x01, 0x28, 0x14,
|
||||
0x11, 0x24, 0x03, 0xe5, 0xe6, 0xe5, 0x5d, 0x01,
|
||||
0x17, 0xe5, 0x01, 0x01, 0x0b, 0xe5, 0x12, 0x09,
|
||||
0x49, 0x03, 0x01, 0x01, 0x0d, 0x31, 0x0a, 0x2f,
|
||||
0x01, 0xe6, 0x28, 0x15, 0x1e, 0x1b, 0xe5, 0x01,
|
||||
0x10, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09,
|
||||
0x09, 0x09, 0x05, 0x02, 0x04, 0x03, 0x10, 0x09,
|
||||
0x09, 0x04, 0x04, 0x09, 0x01, 0x05, 0x03, 0x09,
|
||||
0x13, 0x05, 0x03, 0x0e, 0x01, 0xe5, 0x0c, 0xe5,
|
||||
0x07, 0xe5, 0x04, 0x02, 0xe5, 0x04, 0x02, 0xe5,
|
||||
0x04, 0x02, 0xe5, 0x04, 0x03, 0xe6, 0x07, 0xe5,
|
||||
0x04, 0x02, 0xe5, 0x05, 0x01, 0xe5, 0xe5, 0x05,
|
||||
0xe5, 0x0e, 0x03, 0x10, 0x09, 0x09, 0x09, 0x09,
|
||||
0x06, 0x0d, 0x0a, 0xe5, 0x06, 0x0a, 0x0e, 0x01,
|
||||
0xe5, 0x05, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x01, 0x05, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07,
|
||||
0xe5, 0x02, 0x04, 0xe5, 0xe5, 0x01, 0x03, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0x02, 0x05, 0xe6, 0x0e, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0d, 0x13, 0x03, 0x05, 0x02,
|
||||
0xe5, 0x02, 0x08, 0x05, 0xe8, 0x0c, 0x07, 0x01,
|
||||
0x09, 0x09, 0x06, 0x02, 0x05, 0x03, 0x01, 0x02,
|
||||
0x02, 0x01, 0x01, 0x06, 0x02, 0x02, 0x06, 0x02,
|
||||
0x06, 0x0a, 0x06, 0xe5, 0xe5, 0x0c, 0x02, 0x06,
|
||||
0x02, 0x06, 0x02, 0x04, 0x01, 0x02, 0x06, 0x02,
|
||||
0x06, 0x01, 0x02, 0x06, 0x02, 0x06, 0x01, 0xe6,
|
||||
0x02, 0xe6, 0xe6, 0x05, 0x02, 0x0d, 0x02, 0xe5,
|
||||
0x02, 0x2b, 0x01, 0x06, 0x0b, 0x0c, 0x06, 0x01,
|
||||
0x01, 0xe5, 0x14, 0x02, 0x03, 0xe5, 0xe6, 0x13,
|
||||
0x23, 0x0a, 0x14, 0x04, 0x1c, 0xe5, 0xe6, 0x27,
|
||||
0x01, 0x0e, 0x0a, 0x03, 0x13, 0x1d, 0x02, 0xe5,
|
||||
0x0d, 0x04, 0xe7, 0x14, 0x0e, 0x05, 0xe5, 0x05,
|
||||
0x0c, 0x03, 0x0a, 0x01, 0x09, 0x0a, 0x01, 0x10,
|
||||
0x04, 0xe5, 0x02, 0x09, 0x09, 0x09, 0x09, 0xe6,
|
||||
0x08, 0x09, 0x09, 0xe5, 0x07, 0x0e, 0xe5, 0xe5,
|
||||
0x32, 0x0d, 0x10, 0x02, 0x02, 0x03, 0x02, 0x02,
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0x03, 0x15, 0xe6, 0x47, 0x09, 0x02, 0x09, 0x07,
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0x12, 0xe5, 0xe6, 0x24, 0x1c, 0x12, 0x09, 0x16,
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0x03, 0xe5, 0x01, 0x06, 0x27, 0x16, 0x04, 0x08,
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0x22, 0x05, 0x01, 0x47, 0x15, 0x09, 0x05, 0x0c,
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0x02, 0xe5, 0x40, 0xe5, 0x11, 0xe6, 0x06, 0x01,
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0x18, 0xe8, 0x05, 0x3e, 0x0f, 0x0c, 0x18, 0x01,
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0xe5, 0x2f, 0x0f, 0x13, 0x08, 0xe6, 0x19, 0xe6,
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0xe5, 0x0b, 0x2b, 0x15, 0x14, 0x05, 0x10, 0x01,
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0xe6, 0x3f, 0x28, 0x07, 0x0a, 0xe6, 0x09, 0x2e,
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0x2d, 0x12, 0xe8, 0x59, 0x08, 0x0f, 0xe5, 0x04,
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0x01, 0x01, 0x23, 0x07, 0x01, 0x01, 0x17, 0x2c,
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0x05, 0xe8, 0x22, 0x09, 0x02, 0x28, 0x0a, 0x15,
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0xe6, 0xe5, 0x12, 0x0d, 0xe5, 0x01, 0x06, 0x2e,
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0x09, 0x16, 0xe8, 0x74, 0xe5, 0xe5, 0xe7, 0x01,
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0x01, 0x50, 0xe5, 0x1d, 0x01, 0x02, 0x01, 0x01,
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0x04, 0x52, 0x18, 0x01, 0x02, 0x01, 0x03, 0xe7,
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||||
0x01, 0x52, 0x1a, 0x06, 0x02, 0x03, 0x57, 0x11,
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0x01, 0x05, 0x06, 0xe5, 0x03, 0x02, 0x52, 0x03,
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0x01, 0x02, 0x0a, 0x01, 0x01, 0x06, 0x02, 0x02,
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0x01, 0xe7, 0x55, 0x11, 0x01, 0x0b, 0x02, 0xe5,
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0x01, 0x55, 0x13, 0x01, 0x0e, 0xe5, 0xe6, 0x04,
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0xe5, 0x01, 0x02, 0x6c, 0xe7, 0xe5, 0x04, 0x04,
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0x6f, 0xe6, 0xe6, 0x09, 0x03, 0x09, 0x09, 0x09,
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0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06,
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0xe6, 0xe6, 0x01, 0x6c, 0x02, 0x09, 0xe6, 0x6e,
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||||
0x08, 0x01, 0xe5, 0xe6, 0x22, 0x09, 0x4e, 0x01,
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0x23, 0xe5, 0x07, 0xe5, 0x4a, 0xe9, 0x1e, 0x02,
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0x09, 0x4d, 0x01, 0xe5, 0x14, 0xe5, 0x07, 0xe5,
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0x01, 0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0xe5,
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0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
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0x07, 0xe5, 0x05, 0x01, 0x02, 0x09, 0x19, 0x09,
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0x50, 0x23, 0x09, 0x4c, 0xe5, 0x01, 0x23, 0x09,
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0x4c, 0x02, 0xe5, 0x08, 0x19, 0x09, 0x4c, 0xe5,
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||||
0xe6, 0x1e, 0x59, 0x02, 0xe6, 0x10, 0x01, 0x01,
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0x04, 0xe5, 0xe5, 0x06, 0x01, 0x01, 0x05, 0x01,
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||||
0x07, 0x01, 0x09, 0x01, 0x02, 0x04, 0x01, 0x07,
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||||
0x01, 0x07, 0x01, 0x07, 0x01, 0x0a, 0xe6, 0xe5,
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||||
0x77, 0x02, 0x02, 0xe5, 0x28, 0x04, 0x03, 0x08,
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0x03, 0x13, 0x24, 0xe6, 0xe6, 0x3e, 0x3b, 0xe5,
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||||
0xe6, 0x22, 0x1a, 0x39, 0x02, 0xe6, 0x3e, 0x3a,
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||||
0x01, 0x01, 0xe5, 0x11, 0x2b, 0x1b, 0x1d, 0xe5,
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||||
0x02, 0x3f, 0x32, 0x07, 0xe5, 0xe6, 0x07, 0x36,
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||||
0x3c, 0x01, 0x1a, 0x24, 0xe5, 0x38, 0xe6, 0xe5,
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||||
0x0a, 0x0a, 0x28, 0x3c, 0x01, 0x1b, 0x5f, 0xe7,
|
||||
0x7a, 0xe7, 0x7a, 0x02, 0x01, 0x01, 0x73, 0xe5,
|
||||
0x02, 0xe6, 0x01, 0x72, 0x01, 0x03, 0xe7, 0x03,
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||||
0x6b, 0x01, 0x02, 0x01, 0x02, 0x01, 0xe7, 0xe5,
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||||
0x6b, 0xe5, 0x05, 0x02, 0x03, 0xe5, 0x77, 0x02,
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||||
0xe7, 0xe5, 0x73, 0x03, 0xe8, 0x77, 0x01, 0xe8,
|
||||
0x78, 0xe6, 0xe5, 0x78, 0xe5, 0x01, 0xe5, 0x7a,
|
||||
0xe8, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09,
|
||||
0x09, 0x09, 0x09, 0x0d, 0xe5, 0xe7, 0x01, 0x77,
|
||||
0xe8, 0x77, 0x01, 0x02, 0xe5, 0x6f, 0x0d, 0x7a,
|
||||
0x01, 0xe6, 0x78, 0xe5, 0xe5, 0xe5, 0x14, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
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||||
0x07, 0xe5, 0x09, 0xe5, 0x7a, 0xe5, 0xe5, 0x79,
|
||||
0x01, 0xe6, 0x79, 0x01, 0x01, 0x7e, 0x7c, 0xe6,
|
||||
0x10, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01,
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||||
0x02, 0x04, 0x01, 0x01, 0x05, 0x01, 0x07, 0x01,
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||||
0x02, 0x05, 0x04, 0xe5, 0x7b, 0xe7, 0x1e, 0x29,
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||||
0x08, 0x25, 0xe9, 0x3e, 0x3c, 0x01, 0x03, 0xe5,
|
||||
0x39, 0x3d, 0xe7, 0x3c, 0x3b, 0x02, 0xe5, 0x2f,
|
||||
0x0d, 0x3b, 0xe5, 0xe6, 0x3d, 0x3a, 0x01, 0x01,
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||||
0x3f, 0x3c, 0xe7, 0x03, 0x25, 0xe6, 0x10, 0x1f,
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||||
0xe6, 0x1a, 0xe5, 0x2d, 0x10, 0x21, 0x18, 0xe5,
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||||
0xe6, 0x15, 0x63, 0xe6, 0xe5, 0x13, 0x22, 0x41,
|
||||
0xe7, 0xe5, 0x36, 0x42, 0x01, 0x01, 0x01, 0x76,
|
||||
0xe5, 0x01, 0xe6, 0x01, 0x01, 0x70, 0x01, 0x06,
|
||||
0x01, 0xe5, 0xe5, 0x6f, 0x04, 0xe5, 0x01, 0x02,
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||||
0x74, 0x06, 0xe5, 0x0a, 0x6e, 0x01, 0xe5, 0xe6,
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||||
0x06, 0xe6, 0x69, 0x04, 0x01, 0x02, 0x76, 0xe9,
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||||
0x79, 0xe5, 0xe7, 0x7a, 0x01, 0x63, 0x16, 0xe9,
|
||||
0x0d, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09,
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||||
0x09, 0x09, 0x04, 0x01, 0x06, 0x02, 0xe6, 0x71,
|
||||
0x04, 0x02, 0x02, 0xe5, 0xe5, 0x60, 0x0b, 0x0b,
|
||||
0xe5, 0xe5, 0x36, 0x27, 0x01, 0x16, 0x03, 0x01,
|
||||
0x37, 0xe5, 0x25, 0x01, 0x01, 0x16, 0x01, 0xe7,
|
||||
0x26, 0x0e, 0x27, 0x01, 0x03, 0x14, 0xe5, 0x01,
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||||
0x15, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
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||||
0x01, 0x05, 0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07,
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||||
0xe6, 0xe5, 0x04, 0xe5, 0x07, 0xe5, 0x09, 0xe5,
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||||
0x2d, 0x08, 0x2a, 0x17, 0xe6, 0xe5, 0x2d, 0x08,
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||||
0x2a, 0x18, 0xe5, 0xe5, 0x08, 0x2d, 0x08, 0x39,
|
||||
0x02, 0xe5, 0x2d, 0x08, 0x2c, 0x19, 0xe5, 0x12,
|
||||
0xe5, 0x63, 0x01, 0xe6, 0x05, 0x0a, 0x01, 0x07,
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||||
0x01, 0x07, 0x01, 0x02, 0x04, 0x01, 0x07, 0x01,
|
||||
0x01, 0x02, 0x04, 0x01, 0x07, 0x01, 0x07, 0x01,
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||||
0x07, 0x01, 0x07, 0x01, 0x0a, 0xe5, 0xe6, 0xe5,
|
||||
0x06, 0x4a, 0x0e, 0x16, 0xe9, 0x32, 0x09, 0x13,
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||||
0x13, 0x12, 0xe5, 0x02, 0x0a, 0x33, 0xe6, 0x12,
|
||||
0x09, 0x1b, 0x01, 0x01, 0xe5, 0x07, 0x06, 0x03,
|
||||
0x1a, 0x1a, 0x16, 0x17, 0x01, 0x02, 0x13, 0x2b,
|
||||
0xe5, 0x0e, 0x2b, 0x01, 0xe5, 0x0a, 0x32, 0x03,
|
||||
0x17, 0x03, 0xe6, 0x16, 0x02, 0x01, 0x26, 0x02,
|
||||
0x01, 0x07, 0x0b, 0x01, 0xe6, 0x04, 0x15, 0x01,
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||||
0x18, 0xe8, 0x08, 0x1e, 0x02, 0x13, 0x3a, 0x03,
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||||
0x05, 0x02, 0x36, 0x15, 0xe5, 0x06, 0xe7, 0x17,
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||||
0xe5, 0xe6, 0x38, 0x05, 0x15, 0x02, 0x07, 0x1a,
|
||||
0x02, 0x02, 0x13, 0x16, 0x2a, 0x0e, 0x03, 0x12,
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||||
0x19, 0x04, 0x0d, 0x03, 0x0b, 0x2d, 0xe5, 0x11,
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||||
0x19, 0x20, 0x2f, 0x11, 0x01, 0x01, 0x49, 0x02,
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||||
0xe6, 0x0d, 0x02, 0xe5, 0x04, 0x0e, 0x03, 0x01,
|
||||
0x02, 0x01, 0x41, 0x04, 0x03, 0xe5, 0x0d, 0x02,
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||||
0x06, 0x0b, 0x01, 0x03, 0x02, 0x01, 0xe5, 0xe5,
|
||||
0x22, 0xe5, 0x05, 0x1a, 0x10, 0x01, 0xe5, 0xe5,
|
||||
0x01, 0x04, 0x02, 0x08, 0x04, 0x01, 0x01, 0x02,
|
||||
0x48, 0x10, 0xe5, 0xe5, 0xe5, 0x06, 0xe6, 0xe5,
|
||||
0xe6, 0x05, 0x02, 0xe9, 0x04, 0x05, 0x20, 0x04,
|
||||
0x01, 0x0c, 0x01, 0x07, 0x0e, 0x04, 0x01, 0xe5,
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||||
0x05, 0x02, 0x03, 0x01, 0x06, 0xe5, 0xe5, 0xe5,
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||||
0xe6, 0x07, 0x23, 0x01, 0x02, 0x0c, 0x01, 0x01,
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||||
0x05, 0x03, 0x0f, 0x01, 0xe5, 0x05, 0x03, 0x04,
|
||||
0x04, 0x02, 0xe8, 0x01, 0x3e, 0x01, 0x07, 0x0d,
|
||||
0x02, 0x01, 0xe5, 0xe5, 0x06, 0x05, 0xe6, 0x06,
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||||
0xe7, 0xe5, 0x40, 0x01, 0x07, 0x10, 0x01, 0xe5,
|
||||
0xe6, 0x05, 0x01, 0xe5, 0x02, 0x0a, 0x01, 0xe6,
|
||||
0x1b, 0x02, 0x10, 0x26, 0x09, 0x09, 0x04, 0x07,
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||||
0x01, 0xe7, 0x01, 0x1b, 0xe5, 0x13, 0x23, 0xe5,
|
||||
0x0b, 0x09, 0xe5, 0x09, 0x01, 0xe5, 0x0d, 0x09,
|
||||
0x09, 0x04, 0x01, 0x02, 0x09, 0x0b, 0x09, 0x09,
|
||||
0xe6, 0x06, 0xe5, 0x02, 0xe6, 0x01, 0xe5, 0xe5,
|
||||
0xe5, 0xe5, 0x05, 0x01, 0x02, 0x16, 0x13, 0x33,
|
||||
0x13, 0x04, 0x02, 0xe5, 0xe6, 0xe5, 0x10, 0x14,
|
||||
0x32, 0x14, 0x0b, 0xe6, 0x16, 0x01, 0x11, 0x01,
|
||||
0x24, 0x05, 0xe5, 0x04, 0x01, 0xe5, 0x05, 0x01,
|
||||
0xe6, 0x0d, 0x01, 0x16, 0xe5, 0xe6, 0x0f, 0x01,
|
||||
0xe5, 0x29, 0x05, 0x01, 0x07, 0x01, 0x0f, 0xe8,
|
||||
0x15, 0x01, 0x11, 0x01, 0x2a, 0x08, 0x07, 0x01,
|
||||
0x01, 0x0c, 0xe5, 0xe6, 0x03, 0x10, 0xe6, 0xe5,
|
||||
0x04, 0x09, 0xe6, 0xe5, 0x04, 0xe5, 0x07, 0xe5,
|
||||
0x07, 0x02, 0x06, 0x01, 0xe5, 0x06, 0xe7, 0xe5,
|
||||
0x02, 0x01, 0xe6, 0xe5, 0x04, 0xe5, 0x08, 0x01,
|
||||
0x17, 0x01, 0x05, 0x0b, 0x01, 0x0f, 0x09, 0x0b,
|
||||
0x04, 0xe5, 0x04, 0x01, 0x09, 0x0f, 0xe5, 0xe5,
|
||||
0x16, 0x01, 0x06, 0x0a, 0x01, 0x30, 0xe5, 0xe5,
|
||||
0x05, 0xe5, 0xe5, 0x0d, 0x01, 0xe7, 0x17, 0x05,
|
||||
0x0b, 0x01, 0x0f, 0x02, 0x08, 0x07, 0x01, 0x08,
|
||||
0x04, 0x03, 0x01, 0x16, 0x17, 0x01, 0x03, 0xe5,
|
||||
0x0d, 0x0d, 0x15, 0x08, 0x01, 0x01, 0xe5, 0xe5,
|
||||
0x03, 0xe6, 0x10, 0xe6, 0xe5, 0x10, 0x1c, 0x03,
|
||||
0x18, 0x13, 0xe5, 0xe5, 0x05, 0x14, 0x11, 0x01,
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||||
0x01, 0x05, 0x01, 0x02, 0x04, 0x01, 0x01, 0x05,
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||||
0x01, 0x07, 0x01, 0x01, 0x02, 0x04, 0x01, 0x04,
|
||||
0x02, 0x01, 0x07, 0x01, 0x03, 0x03, 0x01, 0x03,
|
||||
0x03, 0x01, 0x0b, 0xe7, 0xe5, 0x12, 0x15, 0x05,
|
||||
0x0a, 0x10, 0xe5, 0x17, 0x03, 0xe5, 0x0c, 0x01,
|
||||
0xe7, 0x48, 0x03, 0x0e, 0x0c, 0x03, 0x01, 0x08,
|
||||
0x04, 0x05, 0x02, 0x0b, 0x0b, 0x09, 0x08, 0xe5,
|
||||
0x03, 0x05, 0x0b, 0x01, 0x02, 0x0b, 0x0e, 0x01,
|
||||
0x0c, 0x01, 0xe6, 0xe5, 0x01, 0x0f, 0x02, 0xe6,
|
||||
0x03, 0x0e, 0x03, 0x18, 0x0d, 0x20, 0xea, 0x01,
|
||||
0x06, 0x20, 0x03, 0x0f, 0x05, 0x21, 0x14, 0x01,
|
||||
0xe5, 0x15, 0x1f, 0x07, 0x09, 0x1b, 0x13, 0x04,
|
||||
0xe5, 0x06, 0x04, 0x0c, 0x0a, 0xe5, 0x09, 0x04,
|
||||
0x06, 0xe6, 0x24, 0x03, 0x01, 0x0e, 0x01, 0xe6,
|
||||
0x0a, 0x03, 0x17, 0xe5, 0x15, 0x11, 0x11, 0x09,
|
||||
0x0c, 0x02, 0xe6, 0x06, 0x02, 0x0b, 0xe6, 0x17,
|
||||
0x09, 0x02, 0x07, 0x12, 0x04, 0xe6, 0x06, 0xe5,
|
||||
0xe6, 0x0c, 0xe7, 0x18, 0x15, 0xe5, 0x0d, 0x10,
|
||||
0x11, 0x06, 0x01, 0x0e, 0x01, 0xe6, 0x3c, 0x06,
|
||||
0x03, 0x22, 0x0e, 0x01, 0xe6, 0x09, 0x04, 0x58,
|
||||
0x11, 0x02, 0xe5, 0x08, 0x05, 0x2a, 0x01, 0x1c,
|
||||
0x0f, 0x10, 0xe6, 0xe5, 0xe5, 0x01, 0x05, 0xe5,
|
||||
0xe5, 0x01, 0xe5, 0x01, 0x01, 0x03, 0xe5, 0x11,
|
||||
0x09, 0x02, 0xe5, 0x06, 0xe5, 0x22, 0x0e, 0x01,
|
||||
0x03, 0x02, 0x06, 0xe5, 0x01, 0xe6, 0x21, 0xe5,
|
||||
0xe5, 0x2f, 0x01, 0xe5, 0x0a, 0x01, 0x06, 0x01,
|
||||
0xe5, 0xe5, 0x04, 0x01, 0xe5, 0xe5, 0xe5, 0x08,
|
||||
0x1b, 0x02, 0x0a, 0x23, 0x06, 0xe5, 0x02, 0x06,
|
||||
0x01, 0xe5, 0xe5, 0x06, 0x02, 0x27, 0x33, 0x05,
|
||||
0xe5, 0x05, 0x02, 0x02, 0xe6, 0x09, 0x01, 0x01,
|
||||
0x27, 0x06, 0x25, 0x04, 0x01, 0x02, 0x09, 0xe5,
|
||||
0xe6, 0xe8, 0x09, 0x01, 0x01, 0x02, 0x01, 0x1e,
|
||||
0x03, 0x02, 0xe6, 0x29, 0x01, 0x01, 0x09, 0x02,
|
||||
0x03, 0x02, 0x0a, 0x01, 0x18, 0x01, 0x07, 0x01,
|
||||
0x02, 0x04, 0x01, 0x07, 0x01, 0x20, 0x01, 0x01,
|
||||
0x06, 0x02, 0x04, 0x01, 0xe5, 0xe5, 0x09, 0x01,
|
||||
0x18, 0x01, 0x0a, 0x12, 0xe5, 0x18, 0x05, 0x01,
|
||||
0x0e, 0xe8, 0xe5, 0x10, 0x02, 0x24, 0xe5, 0x0b,
|
||||
0x07, 0xe5, 0x07, 0x06, 0x02, 0xe5, 0x04, 0x02,
|
||||
0x02, 0x06, 0xe7, 0xe5, 0x13, 0x3d, 0x09, 0x01,
|
||||
0x03, 0xe5, 0x01, 0x05, 0xe5, 0x01, 0xe5, 0x0b,
|
||||
0xe5, 0x0a, 0x02, 0x02, 0xe6, 0xe5, 0x01, 0x09,
|
||||
0x09, 0x04, 0x01, 0x02, 0x0b, 0x09, 0x03, 0x05,
|
||||
0x05, 0x03, 0xe5, 0x01, 0x05, 0xe6, 0x03, 0x06,
|
||||
0x01, 0xe5, 0xe5, 0x0a, 0xe5, 0x08, 0x27, 0x32,
|
||||
0xe5, 0x03, 0x03, 0x01, 0xe5, 0xe5, 0x08, 0x07,
|
||||
0x27, 0x27, 0x0b, 0x0b, 0xe5, 0xe5, 0x0c, 0x01,
|
||||
0x04, 0x04, 0x1a, 0xe5, 0xe5, 0x08, 0x01, 0x07,
|
||||
0x01, 0x07, 0x01, 0x04, 0x02, 0x01, 0xe5, 0x05,
|
||||
0x01, 0xe6, 0x0f, 0x02, 0x0a, 0x01, 0xe5, 0x05,
|
||||
0x02, 0x1a, 0x01, 0xe5, 0x07, 0x01, 0xe5, 0x05,
|
||||
0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05, 0x01, 0xe6,
|
||||
0x01, 0x01, 0xe5, 0xe7, 0x0b, 0xe5, 0x01, 0xe5,
|
||||
0x0a, 0xe5, 0xe5, 0x08, 0x03, 0x13, 0x05, 0x03,
|
||||
0xe5, 0x03, 0x01, 0x25, 0x01, 0xe5, 0x07, 0x04,
|
||||
0x03, 0x0d, 0x01, 0x05, 0xe6, 0x04, 0xe5, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe6, 0x04, 0x01, 0xe5, 0x01,
|
||||
0x01, 0x05, 0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x05,
|
||||
0xe5, 0xe6, 0xe5, 0x04, 0xe5, 0x0a, 0x09, 0x05,
|
||||
0x09, 0xe5, 0x02, 0x05, 0xe5, 0x07, 0x08, 0x05,
|
||||
0x05, 0xe6, 0x02, 0x01, 0x01, 0x05, 0x01, 0x01,
|
||||
0xe5, 0x02, 0x02, 0x01, 0xe5, 0x02, 0x02, 0x01,
|
||||
0x0e, 0xe8, 0x03, 0x08, 0x01, 0x07, 0x02, 0x05,
|
||||
0x14, 0x05, 0x05, 0x09, 0x01, 0x07, 0x01, 0x06,
|
||||
0xe5, 0xe6, 0x04, 0xe5, 0xe5, 0x0f, 0xe6, 0x08,
|
||||
0x03, 0x01, 0x09, 0x03, 0x01, 0xe5, 0x0c, 0x08,
|
||||
0x05, 0x02, 0x02, 0x05, 0x09, 0x04, 0x05, 0x06,
|
||||
0x01, 0xe5, 0x01, 0x0e, 0x03, 0x04, 0x08, 0x01,
|
||||
0x07, 0x02, 0x02, 0xe5, 0x04, 0x09, 0x06, 0x02,
|
||||
0x02, 0x05, 0x02, 0x13, 0x03, 0x07, 0xe6, 0x01,
|
||||
0x01, 0x02, 0x0b, 0x02, 0xe6, 0x02, 0x08, 0x01,
|
||||
0xe5, 0x0c, 0x19, 0x0f, 0x1a, 0x05, 0x01, 0xe5,
|
||||
0x0b, 0x01, 0x01, 0xe5, 0x02, 0x02, 0x07, 0x02,
|
||||
0x01, 0x07, 0x01, 0x01, 0x05, 0x01, 0x07, 0x01,
|
||||
0x01, 0x05, 0x01, 0x04, 0x04, 0x01, 0x07, 0x01,
|
||||
0x07, 0x01, 0x01, 0x05, 0x01, 0x01, 0x02, 0x02,
|
||||
0x01, 0x0b, 0x02, 0x01, 0x01, 0x07, 0x14, 0x0c,
|
||||
0x01, 0x05, 0x07, 0xe5, 0x06, 0x03, 0x0c, 0xe6,
|
||||
0x06, 0xe6, 0x13, 0x01, 0x02, 0xe6, 0x06, 0x24,
|
||||
0xe5, 0x01, 0x02, 0x04, 0x02, 0x12, 0x01, 0x02,
|
||||
0xe5, 0xe5, 0x06, 0x08, 0x07, 0x08, 0xe6, 0xe6,
|
||||
0x08, 0x14, 0x01, 0x07, 0x01, 0x0e, 0x02, 0xe7,
|
||||
0x0f, 0x0f, 0x19, 0xe5, 0xe6, 0x03, 0x08, 0x06,
|
||||
0x10, 0x0e, 0xe5, 0x03, 0x08, 0x01, 0x1f, 0xe6,
|
||||
0xe5, 0x03, 0x0a, 0x02, 0x01, 0xe5, 0x01, 0x0c,
|
||||
0x16, 0xe5, 0x07, 0xe5, 0x03, 0x05, 0x01, 0xe6,
|
||||
0x03, 0x01, 0x15, 0x08, 0x04, 0x0e, 0xe5, 0xe6,
|
||||
0x11, 0x01, 0x02, 0xe5, 0x1b, 0xe5, 0x06, 0x03,
|
||||
0x05, 0x05, 0x0b, 0x1d, 0xe7, 0xe6, 0x06, 0x03,
|
||||
0x0d, 0x0e, 0x0b, 0x01, 0x01, 0xe6, 0x02, 0x01,
|
||||
0xe7, 0x05, 0x1d, 0x11, 0x02, 0x28, 0x06, 0x03,
|
||||
0x07, 0xe5, 0x01, 0x0b, 0x18, 0x06, 0x06, 0x07,
|
||||
0x03, 0xe5, 0x1e, 0x01, 0x07, 0x07, 0x0c, 0x07,
|
||||
0x02, 0xe5, 0xe5, 0x02, 0x02, 0xe6, 0x06, 0x15,
|
||||
0x05, 0x02, 0xe5, 0x1c, 0x05, 0x10, 0x05, 0x04,
|
||||
0x05, 0x12, 0x01, 0x15, 0x09, 0x02, 0xe5, 0x0b,
|
||||
0x07, 0x0e, 0x04, 0xe5, 0x02, 0x02, 0x10, 0x01,
|
||||
0xe5, 0xe5, 0xe5, 0x0b, 0xe6, 0x01, 0x01, 0x1d,
|
||||
0xe6, 0xe5, 0xe5, 0x0f, 0x09, 0x05, 0xe6, 0x06,
|
||||
0xe5, 0x04, 0x03, 0x0b, 0x0b, 0x07, 0xe5, 0x03,
|
||||
0x0a, 0x02, 0x01, 0x07, 0x04, 0xe8, 0x11, 0x01,
|
||||
0x0d, 0x05, 0x04, 0x09, 0x02, 0x01, 0x05, 0x03,
|
||||
0xe5, 0x0e, 0x04, 0x0e, 0x03, 0x0a, 0xe5, 0xe6,
|
||||
0x01, 0x0e, 0x06, 0xe5, 0xe5, 0x0f, 0x02, 0x12,
|
||||
0x03, 0x10, 0x08, 0xe6, 0x10, 0x02, 0x03, 0xe5,
|
||||
0xe5, 0x03, 0x01, 0xe6, 0x02, 0x03, 0x07, 0x0b,
|
||||
0x07, 0x01, 0x12, 0x02, 0x09, 0xe5, 0x04, 0x0a,
|
||||
0x08, 0x05, 0x0b, 0xe5, 0xe7, 0x17, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x04, 0x02, 0x02, 0xe5, 0x06,
|
||||
0xe5, 0x04, 0x02, 0xe5, 0x07, 0xe5, 0x04, 0x17,
|
||||
0xe5, 0x01, 0xe5, 0xe5, 0x01, 0x01, 0x01, 0x06,
|
||||
0xe5, 0x0a, 0x08, 0xe5, 0x05, 0xe5, 0x01, 0x05,
|
||||
0xe6, 0x09, 0xe5, 0x09, 0x09, 0x10, 0x0b, 0x01,
|
||||
0x02, 0x01, 0xe6, 0x03, 0x01, 0x08, 0x0e, 0x01,
|
||||
0x0c, 0x07, 0x01, 0x02, 0x08, 0x01, 0x05, 0x13,
|
||||
0x06, 0x01, 0xe5, 0xe5, 0x03, 0x01, 0x02, 0x01,
|
||||
0x03, 0x01, 0xe5, 0x0c, 0x1d, 0x05, 0xe5, 0x01,
|
||||
0x01, 0x0b, 0x09, 0x1b, 0x01, 0x04, 0x06, 0x02,
|
||||
0x03, 0x0f, 0x06, 0xe5, 0xe5, 0x09, 0x08, 0x06,
|
||||
0xe5, 0xe6, 0x04, 0x02, 0x08, 0x03, 0x03, 0x01,
|
||||
0x0a, 0x08, 0xe5, 0xe5, 0x03, 0xe6, 0x04, 0xe5,
|
||||
0x02, 0xe5, 0x01, 0x02, 0x07, 0x03, 0x03, 0x01,
|
||||
0x01, 0x01, 0x07, 0x01, 0x05, 0x03, 0x03, 0x01,
|
||||
0x01, 0xe5, 0x03, 0xe5, 0x03, 0x01, 0x03, 0xe5,
|
||||
0x05, 0x02, 0x11, 0xe7, 0xe5, 0xe5, 0x01, 0x01,
|
||||
0x01, 0x02, 0x06, 0x01, 0x0d, 0x07, 0x01, 0x03,
|
||||
0xe5, 0x0d, 0x07, 0x01, 0x04, 0xe6, 0x01, 0x07,
|
||||
0x15, 0x09, 0x01, 0x0b, 0x02, 0xe5, 0x01, 0x0d,
|
||||
0x09, 0x01, 0x04, 0x01, 0x03, 0x06, 0x09, 0x02,
|
||||
0x03, 0x06, 0x25, 0x01, 0x10, 0xe6, 0x08, 0x1d,
|
||||
0x02, 0x06, 0x06, 0x02, 0x01, 0xe5, 0x11, 0x02,
|
||||
0x10, 0x02, 0x06, 0xe5, 0x01, 0xe5, 0x03, 0x04,
|
||||
0x0a, 0x01, 0x1b, 0x09, 0x01, 0x13, 0xe5, 0x07,
|
||||
0x10, 0xe5, 0xe5, 0x08, 0x03, 0x06, 0x02, 0xe5,
|
||||
0x07, 0x05, 0x09, 0x06, 0x02, 0x02, 0x02, 0x03,
|
||||
0x03, 0x05, 0xe5, 0x04, 0x04, 0x09, 0x04, 0xe6,
|
||||
0x01, 0x04, 0x01, 0x02, 0x03, 0x05, 0x03, 0x02,
|
||||
0x06, 0x01, 0xe7, 0x01, 0x1a, 0x02, 0x13, 0x08,
|
||||
0xe5, 0x1e, 0x09, 0x06, 0x0a, 0x01, 0xe6, 0x1e,
|
||||
0x13, 0x07, 0x21, 0x07, 0x12, 0x02, 0xe7, 0xe5,
|
||||
0x0a, 0x01, 0x15, 0x05, 0x01, 0x07, 0x01, 0xe5,
|
||||
0x07, 0x01, 0x13, 0x04, 0x02, 0x01, 0x07, 0x01,
|
||||
0x0f, 0xe5, 0xe5, 0x0c, 0x01, 0xe5, 0x16, 0x02,
|
||||
0x01, 0x01, 0x04, 0xe5, 0xe5, 0x05, 0x02, 0x01,
|
||||
0xe5, 0x08, 0x06, 0x01, 0xe5, 0x05, 0x01, 0x01,
|
||||
0x01, 0x02, 0xe5, 0xe6, 0x0c, 0xe5, 0xe6, 0x0c,
|
||||
0x01, 0x0d, 0x07, 0x0c, 0x04, 0x09, 0x01, 0x13,
|
||||
0x09, 0x07, 0x01, 0x0d, 0xe6, 0x01, 0x0d, 0x01,
|
||||
0x03, 0xe7, 0x05, 0xe7, 0x05, 0xe6, 0xe5, 0x04,
|
||||
0xe8, 0xe5, 0x03, 0xe6, 0x01, 0x01, 0x03, 0x02,
|
||||
0x06, 0xe5, 0xe6, 0xe5, 0x02, 0xe8, 0x06, 0xe5,
|
||||
0x01, 0x05, 0xe5, 0x07, 0x02, 0x13, 0xe5, 0xe5,
|
||||
0x02, 0xe5, 0xe5, 0x05, 0x04, 0x01, 0x01, 0x04,
|
||||
0x02, 0x01, 0xe5, 0x07, 0x01, 0xe5, 0x08, 0xe5,
|
||||
0x0e, 0x01, 0x07, 0x01, 0x0e, 0xe5, 0xe6, 0x14,
|
||||
0xe5, 0x06, 0x01, 0x07, 0x01, 0xe5, 0xe5, 0x05,
|
||||
0xe5, 0xe5, 0x05, 0x04, 0x03, 0x02, 0x07, 0x01,
|
||||
0x09, 0xe5, 0xe5, 0x08, 0x0e, 0xe5, 0x01, 0xe5,
|
||||
0x0a, 0x08, 0x09, 0x01, 0x02, 0x02, 0x01, 0x07,
|
||||
0x01, 0xe6, 0xe6, 0x02, 0xe5, 0x01, 0xe5, 0xe6,
|
||||
0x03, 0xe6, 0xe5, 0x02, 0x01, 0x07, 0xe6, 0x0a,
|
||||
0x01, 0x0e, 0xe8, 0x13, 0x05, 0x03, 0xe6, 0x02,
|
||||
0x03, 0x02, 0x04, 0xe5, 0xe5, 0xe5, 0xe6, 0x01,
|
||||
0x01, 0xe5, 0x01, 0x01, 0xe5, 0x01, 0xe5, 0x01,
|
||||
0x01, 0xe5, 0x02, 0x01, 0x07, 0xe6, 0x04, 0x06,
|
||||
0x0e, 0x02, 0xe5, 0x01, 0x07, 0x16, 0x0d, 0xe5,
|
||||
0x03, 0x02, 0xe5, 0x08, 0xe5, 0x05, 0x02, 0x10,
|
||||
0x02, 0x06, 0x02, 0x0c, 0xe6, 0xe6, 0x10, 0x01,
|
||||
0xe5, 0x05, 0x01, 0xe5, 0x02, 0x02, 0x01, 0x01,
|
||||
0x05, 0x01, 0x04, 0x02, 0x01, 0x04, 0x04, 0x01,
|
||||
0x02, 0x01, 0x01, 0xe7, 0x06, 0x01, 0x03, 0x03,
|
||||
0x01, 0x04, 0x02, 0x01, 0xe5, 0x0a, 0xe6, 0xe5,
|
||||
0x20, 0xe5, 0x07, 0xe5, 0x05, 0x02, 0x05, 0x04,
|
||||
0xe5, 0xe5, 0x03, 0x01, 0x11, 0x09, 0x0e, 0x05,
|
||||
0xe5, 0x0a, 0x07, 0x0a, 0x03, 0x01, 0x01, 0x03,
|
||||
0x01, 0x06, 0xe5, 0x01, 0x0a, 0x0e, 0x13, 0x12,
|
||||
0xe9, 0x03, 0x05, 0x16, 0x05, 0x02, 0x11, 0x02,
|
||||
0x01, 0x03, 0x07, 0x02, 0x03, 0x11, 0x13, 0x03,
|
||||
0xe5, 0x0a, 0xe7, 0x03, 0x0e, 0x04, 0x0b, 0xe7,
|
||||
0xe5, 0x05, 0xe7, 0x03, 0x02, 0x01, 0x07, 0x01,
|
||||
0x05, 0x01, 0xe5, 0x16, 0xe5, 0x02, 0xe5, 0x35,
|
||||
0x08, 0x01, 0x03, 0x05, 0x01, 0x08, 0xe5, 0x03,
|
||||
0x1e, 0xe8, 0x07, 0x03, 0x05, 0x04, 0xe5, 0x02,
|
||||
0x02, 0xe7, 0x01, 0x05, 0xe5, 0x02, 0xe6, 0x06,
|
||||
0x01, 0xe6, 0x02, 0x0d, 0x05, 0x0f, 0x11, 0xe9,
|
||||
0x20, 0x09, 0x0c, 0x06, 0x01, 0x01, 0x02, 0x0b,
|
||||
0x02, 0x05, 0x11, 0x0c, 0x02, 0xe5, 0x0b, 0x16,
|
||||
0x02, 0x03, 0x02, 0x05, 0x0a, 0xe5, 0x03, 0x01,
|
||||
0x0a, 0x05, 0xe6, 0xe5, 0x07, 0x15, 0x02, 0xe5,
|
||||
0x0c, 0xe5, 0x15, 0x02, 0x07, 0x03, 0xe5, 0x08,
|
||||
0x07, 0x02, 0x0b, 0x02, 0x15, 0x0a, 0xe6, 0xe5,
|
||||
0x03, 0x05, 0x05, 0x24, 0x06, 0xe5, 0xe6, 0x03,
|
||||
0x09, 0x03, 0x04, 0x25, 0x0e, 0x05, 0x02, 0x01,
|
||||
0x02, 0x07, 0x02, 0x0f, 0x02, 0x08, 0x04, 0x02,
|
||||
0x01, 0x04, 0xe5, 0x03, 0xe5, 0x20, 0xe7, 0x08,
|
||||
0x0f, 0x01, 0x0d, 0x01, 0x01, 0x03, 0x04, 0xe5,
|
||||
0xe5, 0x01, 0x03, 0xe5, 0xe5, 0x08, 0x09, 0x23,
|
||||
0x01, 0xe5, 0x01, 0x15, 0x1d, 0x04, 0x05, 0x0a,
|
||||
0x03, 0x06, 0x22, 0xe6, 0xe5, 0x0c, 0x09, 0x09,
|
||||
0x18, 0xe6, 0x03, 0x02, 0xe6, 0xe5, 0xe5, 0x02,
|
||||
0x03, 0xe5, 0x05, 0x07, 0xe6, 0x06, 0x01, 0x08,
|
||||
0xe5, 0xe5, 0x01, 0xe5, 0x03, 0x08, 0x09, 0xe5,
|
||||
0x07, 0xe5, 0x17, 0xe5, 0x03, 0x05, 0xe5, 0x06,
|
||||
0x01, 0xe5, 0x0e, 0x05, 0xe5, 0x02, 0x06, 0x01,
|
||||
0x02, 0xe5, 0xe6, 0x03, 0x08, 0x05, 0xe5, 0x03,
|
||||
0x04, 0xe5, 0x02, 0x03, 0xe5, 0x08, 0x01, 0x02,
|
||||
0x04, 0x01, 0x02, 0x01, 0x01, 0xe5, 0xe6, 0xe5,
|
||||
0x0b, 0x12, 0x04, 0xe5, 0x02, 0x01, 0x02, 0x01,
|
||||
0x01, 0x02, 0x0a, 0x06, 0xe5, 0xe5, 0x05, 0xe5,
|
||||
0xe5, 0x05, 0x09, 0x02, 0x06, 0x04, 0x01, 0x07,
|
||||
0x0a, 0x01, 0x10, 0x0d, 0x03, 0xe8, 0x04, 0x05,
|
||||
0xe5, 0x08, 0x01, 0x06, 0x02, 0x03, 0x01, 0xe6,
|
||||
0xe6, 0xe6, 0xe6, 0x04, 0x02, 0xe5, 0x01, 0x01,
|
||||
0x11, 0x04, 0x10, 0x06, 0x05, 0xe6, 0x01, 0xe5,
|
||||
0x01, 0x07, 0xe7, 0x02, 0x05, 0x01, 0x01, 0x01,
|
||||
0x01, 0xe6, 0x05, 0x01, 0xe5, 0x01, 0x05, 0x05,
|
||||
0x01, 0xe6, 0x01, 0x01, 0x01, 0x09, 0x07, 0x04,
|
||||
0x01, 0x0a, 0x03, 0x03, 0xe5, 0x03, 0x02, 0xe5,
|
||||
0x01, 0xe5, 0x0b, 0x09, 0x01, 0x09, 0x07, 0x01,
|
||||
0x02, 0x01, 0xe5, 0x02, 0x09, 0x01, 0x07, 0x06,
|
||||
0x01, 0xe5, 0x02, 0x02, 0x0e, 0x05, 0x05, 0x02,
|
||||
0x02, 0xe5, 0x0c, 0x09, 0x01, 0x07, 0x09, 0x01,
|
||||
0xe6, 0x01, 0xe5, 0xe5, 0x0a, 0x01, 0x07, 0x05,
|
||||
0xe5, 0x03, 0x03, 0xe6, 0x0a, 0x05, 0xe5, 0x08,
|
||||
0x03, 0xe5, 0x07, 0x13, 0x09, 0xe5, 0x04, 0x04,
|
||||
0x04, 0x02, 0x0b, 0x09, 0x09, 0x02, 0x1a, 0xe9,
|
||||
0x0b, 0x13, 0x04, 0x0a, 0x01, 0xe5, 0x07, 0xe6,
|
||||
0x08, 0xe6, 0x06, 0xe6, 0x03, 0x20, 0x01, 0xe7,
|
||||
0x0d, 0x09, 0x09, 0x06, 0x02, 0xe5, 0x07, 0x06,
|
||||
0x04, 0x09, 0x04, 0x01, 0x02, 0xe5, 0xe5, 0x05,
|
||||
0x09, 0x0d, 0x04, 0x27, 0x0c, 0x08, 0xe5, 0x0a,
|
||||
0x09, 0x1d, 0x08, 0x01, 0xe5, 0xe5, 0x2e, 0x0b,
|
||||
0x09, 0x0b, 0x1b, 0x08, 0x01, 0x01, 0x01, 0x1e,
|
||||
0x0c, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x07, 0x01,
|
||||
0x06, 0xe5, 0xe5, 0x08, 0x01, 0x16, 0x01, 0x09,
|
||||
0xe6, 0x19, 0x0a, 0x01, 0x03, 0x01, 0x01, 0x02,
|
||||
0x01, 0xe5, 0xe7, 0x06, 0x01, 0xe5, 0x05, 0x01,
|
||||
0xe5, 0x08, 0xe5, 0xe5, 0x1e, 0x01, 0xe6, 0x07,
|
||||
0x0c, 0xe5, 0x05, 0x08, 0x03, 0x01, 0x09, 0x06,
|
||||
0x02, 0x01, 0x07, 0x01, 0x04, 0x01, 0x04, 0x1f,
|
||||
0x03, 0xe6, 0x12, 0xe7, 0x06, 0x09, 0xe6, 0xe5,
|
||||
0x03, 0xe7, 0xe5, 0x02, 0xe5, 0xe5, 0x01, 0x01,
|
||||
0x04, 0xe7, 0xe5, 0x02, 0xe7, 0x05, 0x02, 0x08,
|
||||
0xe5, 0x07, 0xe5, 0x06, 0xe8, 0x0f, 0x03, 0x01,
|
||||
0x08, 0x01, 0x01, 0x06, 0x03, 0xe5, 0x02, 0xe6,
|
||||
0xe6, 0x09, 0xe5, 0x04, 0xe5, 0xe5, 0x09, 0x22,
|
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0xe5, 0xe5, 0x0f, 0x04, 0xe5, 0x08, 0xe5, 0xe5,
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0x04, 0xe5, 0x06, 0x01, 0xe5, 0xe6, 0x04, 0x02,
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0x01, 0x04, 0xe7, 0xe5, 0x03, 0xe6, 0x02, 0x05,
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0x1b, 0x01, 0x01, 0x15, 0x01, 0x07, 0x09, 0x09,
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0x01, 0x01, 0x03, 0xe7, 0xe6, 0xe6, 0x03, 0x03,
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0x03, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x1a, 0xe5,
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0x01, 0x10, 0x02, 0x03, 0x05, 0xe5, 0x06, 0xe6,
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0x01, 0x02, 0x01, 0xe6, 0x01, 0x01, 0xe5, 0xe7,
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0x03, 0x01, 0xe5, 0x01, 0xe5, 0x01, 0x01, 0xe5,
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0x02, 0x07, 0xe6, 0x1c, 0xe5, 0x01, 0x0d, 0x01,
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0xe5, 0x05, 0x02, 0x09, 0x07, 0x01, 0x12, 0x01,
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0xe5, 0x05, 0xe5, 0xe5, 0x1d, 0x0b, 0xe5, 0xe5,
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||||
0xe5, 0x08, 0xe5, 0x02, 0x02, 0x01, 0x03, 0x03,
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0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x04,
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0x01, 0x02, 0x01, 0x01, 0x05, 0x01, 0x01, 0x05,
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0x01, 0x01, 0x05, 0x01, 0x07, 0x01, 0x0b, 0x02,
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||||
0x0b, 0x09, 0x01, 0x09, 0x0f, 0x05, 0xe5, 0x09,
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0xe5, 0x06, 0x03, 0x08, 0x08, 0x15, 0x03, 0x01,
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0xe5, 0x06, 0x15, 0x17, 0x07, 0x02, 0x02, 0x09,
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0xe5, 0x0d, 0x01, 0x05, 0x12, 0x03, 0xe5, 0x02,
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0x0f, 0xe5, 0x05, 0x0b, 0xe5, 0x05, 0x06, 0x08,
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0x03, 0x15, 0x0e, 0x04, 0x08, 0x04, 0x01, 0xe6,
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0x08, 0x12, 0x03, 0x01, 0x07, 0x01, 0x04, 0x02,
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0x01, 0xe5, 0x07, 0xe7, 0x0e, 0xe7, 0x03, 0x12,
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0xe5, 0x07, 0x01, 0xe5, 0xe5, 0x0a, 0x05, 0x0d,
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0x01, 0x01, 0x08, 0x01, 0x07, 0xe5, 0x06, 0xe5,
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0xe5, 0x02, 0x0e, 0x27, 0xe6, 0x07, 0x09, 0x04,
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0xe5, 0x02, 0xe5, 0x0c, 0xe5, 0x01, 0x0a, 0x03,
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0xe5, 0x01, 0x04, 0x0a, 0x03, 0x05, 0x11, 0x09,
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0xe5, 0x02, 0x24, 0x16, 0x03, 0x02, 0x01, 0x0a,
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0x05, 0x01, 0x1d, 0x05, 0xe5, 0xe5, 0x02, 0x22,
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0x09, 0x0e, 0xe5, 0x03, 0x03, 0x06, 0x07, 0x21,
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0xe5, 0x01, 0x08, 0x0f, 0x0e, 0x0b, 0x0a, 0xe5,
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0x04, 0x02, 0x01, 0x09, 0x03, 0x19, 0x01, 0x06,
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0x02, 0x13, 0x04, 0x19, 0xe5, 0x04, 0x02, 0x02,
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0x19, 0x1b, 0x05, 0xe7, 0x04, 0x22, 0x12, 0x09,
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||||
0xe5, 0x05, 0x0e, 0x21, 0x06, 0x03, 0x1a, 0x1d,
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0x03, 0x05, 0x01, 0xe5, 0x11, 0x04, 0x13, 0x01,
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||||
0x05, 0x0b, 0x13, 0x1c, 0x08, 0x01, 0x26, 0x05,
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||||
0xe6, 0xe5, 0xe5, 0x17, 0xe6, 0xe5, 0xe5, 0x02,
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||||
0xe5, 0x15, 0x01, 0x05, 0xe5, 0x01, 0xe5, 0x03,
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||||
0xe5, 0x0e, 0x05, 0xe5, 0x01, 0x02, 0xe5, 0x09,
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||||
0xe8, 0xe5, 0x01, 0x01, 0x15, 0x02, 0xe5, 0x01,
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||||
0xe5, 0x01, 0x02, 0xe5, 0x10, 0xe5, 0x03, 0xe5,
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||||
0x11, 0xe5, 0x07, 0x06, 0x01, 0xe5, 0x0a, 0x01,
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||||
0x02, 0xe5, 0x01, 0x04, 0x05, 0xe5, 0xe5, 0xe5,
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||||
0x12, 0x1d, 0x01, 0x01, 0x01, 0xe5, 0x03, 0x01,
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||||
0x05, 0x01, 0x07, 0x09, 0x03, 0x07, 0x08, 0x02,
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||||
0x0a, 0x01, 0x11, 0x1f, 0x01, 0x09, 0x07, 0x01,
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||||
0x07, 0x09, 0x0d, 0x03, 0x02, 0xe5, 0x08, 0x01,
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||||
0x0a, 0x01, 0x09, 0x06, 0xe5, 0xe5, 0x12, 0x01,
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||||
0x03, 0x02, 0xe5, 0xe6, 0x05, 0x01, 0x06, 0xe5,
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||||
0x08, 0x0a, 0x06, 0x01, 0xe5, 0x01, 0x06, 0x02,
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||||
0x04, 0x05, 0x01, 0x01, 0x05, 0x03, 0x03, 0xe6,
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||||
0xe5, 0xe5, 0x10, 0x03, 0x05, 0x01, 0x07, 0x01,
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||||
0x01, 0x02, 0xe7, 0x02, 0x05, 0x03, 0x06, 0x02,
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||||
0x02, 0x01, 0x01, 0xe5, 0x0b, 0x01, 0x07, 0x01,
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||||
0x04, 0x04, 0x05, 0x01, 0x01, 0x13, 0x01, 0x07,
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||||
0x01, 0x07, 0x01, 0x07, 0x06, 0x02, 0x0a, 0x04,
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||||
0x02, 0xe6, 0x0c, 0x01, 0x07, 0x01, 0x04, 0xe5,
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||||
0xe5, 0x08, 0x01, 0x13, 0x01, 0x07, 0x01, 0x07,
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||||
0x01, 0x07, 0x05, 0xe6, 0xe5, 0x0f, 0xe5, 0xe7,
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||||
0x07, 0xe5, 0x13, 0x2e, 0x02, 0x02, 0x06, 0x22,
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||||
0x02, 0x4f, 0x09, 0x01, 0x1b, 0xe5, 0x01, 0xe5,
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||||
0x0a, 0x02, 0x09, 0x06, 0x02, 0x09, 0x09, 0x04,
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||||
0x01, 0x04, 0x02, 0x01, 0x01, 0x02, 0x04, 0xe6,
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||||
0x01, 0x03, 0x05, 0x09, 0x0d, 0xe5, 0xe7, 0x01,
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||||
0x06, 0x02, 0x12, 0xe5, 0x1c, 0x0b, 0x2c, 0x04,
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||||
0xe6, 0x08, 0x13, 0x1d, 0x0b, 0x32, 0x01, 0x01,
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||||
0x0f, 0x10, 0x02, 0x1f, 0x07, 0x01, 0xe5, 0x05,
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||||
0x01, 0x04, 0x1d, 0xe5, 0x01, 0x0d, 0x02, 0x10,
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||||
0x02, 0x19, 0x02, 0x02, 0x06, 0x01, 0xe5, 0x04,
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||||
0xe5, 0xe6, 0x24, 0x0f, 0x04, 0x0e, 0x18, 0x01,
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||||
0x04, 0x07, 0x01, 0x09, 0x21, 0xe5, 0x01, 0xe5,
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||||
0x0c, 0x05, 0xe5, 0xe5, 0x07, 0xe6, 0x04, 0xe5,
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||||
0xe5, 0x06, 0xe6, 0x07, 0xe5, 0x01, 0x05, 0x02,
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||||
0xe5, 0x04, 0x02, 0xe5, 0x06, 0xe5, 0x07, 0xe5,
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||||
0x07, 0xe5, 0x05, 0xe6, 0xe6, 0x0e, 0x03, 0xe5,
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||||
0x04, 0xe5, 0x06, 0x1d, 0x01, 0xe6, 0x04, 0x01,
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||||
0x07, 0x01, 0x0a, 0xe5, 0x15, 0xe5, 0x01, 0x0d,
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||||
0x08, 0x0a, 0x05, 0x02, 0x09, 0x0c, 0x08, 0xe5,
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||||
0xe5, 0x06, 0x01, 0x22, 0x03, 0x0f, 0x05, 0xe5,
|
||||
0x0b, 0x04, 0xe6, 0x06, 0x01, 0x0c, 0x01, 0x03,
|
||||
0x01, 0xe6, 0xe5, 0x02, 0x01, 0x01, 0x01, 0x22,
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||||
0xe6, 0xe5, 0x0c, 0x06, 0x05, 0x06, 0x02, 0x02,
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||||
0x06, 0x03, 0x0e, 0x02, 0x02, 0xe5, 0x01, 0x01,
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||||
0x07, 0x01, 0x0a, 0x1a, 0xe5, 0x40, 0xe5, 0xe5,
|
||||
0x19, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x0b, 0x01,
|
||||
0x01, 0xe5, 0x10, 0x01, 0x07, 0x01, 0x07, 0x01,
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||||
0x07, 0x01, 0x07, 0x01, 0x09, 0x01, 0xe5, 0x04,
|
||||
0xe7, 0x06, 0x01, 0x03, 0x03, 0x01, 0x07, 0x01,
|
||||
0x0b, 0x01, 0xe5, 0x22, 0x0d, 0x01, 0xe5, 0x08,
|
||||
0x03, 0x07, 0x02, 0xe5, 0x18, 0x01, 0x0a, 0x05,
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||||
0xe8, 0x0a, 0x16, 0xe5, 0x21, 0xe5, 0x01, 0x26,
|
||||
0x06, 0x01, 0x01, 0xe5, 0x30, 0x06, 0x03, 0x02,
|
||||
0x0d, 0x0b, 0x24, 0xe5, 0x03, 0x2c, 0x05, 0x06,
|
||||
0x03, 0x04, 0x02, 0xe5, 0x01, 0x05, 0x01, 0x18,
|
||||
0x09, 0xe8, 0x04, 0x05, 0x07, 0x0b, 0x1f, 0xe5,
|
||||
0x0f, 0x06, 0x03, 0x1b, 0x01, 0x03, 0xe5, 0xe5,
|
||||
0x19, 0x07, 0x0b, 0x09, 0x03, 0xe6, 0x07, 0x04,
|
||||
0x03, 0x01, 0x24, 0x03, 0x01, 0x03, 0x1a, 0x17,
|
||||
0x06, 0x12, 0x1c, 0x0a, 0xe6, 0xe5, 0x05, 0x0e,
|
||||
0x06, 0x01, 0x07, 0x09, 0x0d, 0xe5, 0x10, 0x16,
|
||||
0x12, 0xe7, 0x12, 0x02, 0x09, 0x09, 0x08, 0xe5,
|
||||
0x09, 0xe5, 0x08, 0x04, 0x2c, 0xe6, 0x27, 0x13,
|
||||
0xe5, 0xe6, 0x05, 0x33, 0x02, 0x09, 0x01, 0x05,
|
||||
0x01, 0x09, 0xe5, 0x07, 0x1b, 0x02, 0x06, 0x09,
|
||||
0x22, 0xe8, 0x31, 0x10, 0x08, 0xe5, 0x07, 0xe5,
|
||||
0x05, 0x0e, 0x0b, 0xe5, 0xe7, 0x07, 0x15, 0x10,
|
||||
0x0e, 0x02, 0xe5, 0x09, 0x09, 0x17, 0x0a, 0xe5,
|
||||
0x01, 0xe6, 0x48, 0x09, 0x22, 0xe5, 0x01, 0xe6,
|
||||
0x01, 0x01, 0x46, 0xe6, 0x01, 0x04, 0x1f, 0x01,
|
||||
0x02, 0x03, 0x04, 0x43, 0x01, 0x02, 0x04, 0x01,
|
||||
0x02, 0x0e, 0xe5, 0xe5, 0xe5, 0x08, 0x04, 0x02,
|
||||
0xe5, 0x01, 0x45, 0x04, 0x09, 0x0e, 0x02, 0x01,
|
||||
0x0b, 0x02, 0xe6, 0xe5, 0x48, 0x01, 0x01, 0x07,
|
||||
0x11, 0x14, 0x01, 0x02, 0x48, 0x01, 0x01, 0x05,
|
||||
0x03, 0x13, 0x09, 0x02, 0x02, 0xe6, 0x4b, 0x09,
|
||||
0x04, 0x0c, 0x01, 0x08, 0x04, 0xe6, 0x01, 0x31,
|
||||
0xe5, 0x19, 0x09, 0x05, 0x0b, 0x01, 0x10, 0xe6,
|
||||
0x08, 0x47, 0x02, 0x06, 0x02, 0x15, 0x06, 0xe7,
|
||||
0x09, 0x01, 0x45, 0xe5, 0x07, 0x1d, 0x03, 0xe5,
|
||||
0x07, 0x05, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x04,
|
||||
0x01, 0x02, 0x09, 0x05, 0x03, 0x09, 0x0d, 0x01,
|
||||
0xe7, 0x01, 0x47, 0x09, 0x22, 0x04, 0xe6, 0x46,
|
||||
0x09, 0x28, 0xe5, 0xe6, 0x42, 0x06, 0x02, 0x07,
|
||||
0x01, 0x20, 0x03, 0x01, 0x43, 0xe5, 0x08, 0x08,
|
||||
0xe5, 0x20, 0x03, 0xe5, 0x41, 0x06, 0x07, 0x02,
|
||||
0x28, 0x15, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x03, 0x05, 0xe5, 0x01, 0x05,
|
||||
0xe5, 0x01, 0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
|
||||
0x06, 0xe6, 0xe5, 0x2d, 0xe5, 0x12, 0x13, 0xe6,
|
||||
0x1f, 0x02, 0xe5, 0x42, 0x11, 0x01, 0x22, 0xe5,
|
||||
0x01, 0x43, 0x13, 0x21, 0xe7, 0xe5, 0x2d, 0x14,
|
||||
0x11, 0x02, 0x1c, 0xe5, 0x03, 0x02, 0x4b, 0x01,
|
||||
0xe5, 0x05, 0x23, 0xe7, 0xe5, 0x10, 0x01, 0x07,
|
||||
0x01, 0x07, 0x01, 0x07, 0xe6, 0x06, 0x01, 0x09,
|
||||
0x01, 0x02, 0xe5, 0x02, 0x01, 0x04, 0x02, 0x01,
|
||||
0x07, 0x01, 0x07, 0x01, 0x01, 0x03, 0xe5, 0x06,
|
||||
0x2f, 0x2e, 0x1c, 0x02, 0xe5, 0x1e, 0x28, 0x1e,
|
||||
0x10, 0xe6, 0xe6, 0x1a, 0x14, 0x0e, 0x09, 0xe5,
|
||||
0x2a, 0x03, 0x02, 0xe6, 0x08, 0x14, 0x19, 0x05,
|
||||
0x07, 0x03, 0xe6, 0x06, 0x06, 0x17, 0x06, 0xe7,
|
||||
0x3e, 0x0b, 0x0b, 0x22, 0xe9, 0x07, 0x09, 0x09,
|
||||
0x10, 0x09, 0x04, 0x01, 0x04, 0xe6, 0x27, 0x0a,
|
||||
0x02, 0xe5, 0x29, 0x14, 0x0a, 0x2a, 0x04, 0x02,
|
||||
0xe5, 0x0a, 0x12, 0x20, 0x3a, 0xe5, 0xe6, 0x0a,
|
||||
0x07, 0x10, 0x18, 0x01, 0x05, 0x0b, 0x08, 0x19,
|
||||
0x06, 0xe5, 0xe5, 0x1b, 0x13, 0x0e, 0xe5, 0x0d,
|
||||
0x09, 0x21, 0x02, 0x32, 0x1c, 0x2a, 0x01, 0x01,
|
||||
0x0a, 0x2f, 0x15, 0x0b, 0x1c, 0xe5, 0xe7, 0x09,
|
||||
0x27, 0x41, 0x06, 0xe9, 0x4f, 0xe5, 0xe5, 0x02,
|
||||
0xe5, 0x1c, 0xe5, 0x01, 0x01, 0x02, 0x01, 0x4c,
|
||||
0xe5, 0x21, 0x01, 0x03, 0xe5, 0xe5, 0x03, 0x0e,
|
||||
0xe5, 0x01, 0x01, 0x17, 0xe5, 0x01, 0x01, 0x1d,
|
||||
0x03, 0x1b, 0x05, 0x01, 0xe5, 0x01, 0x11, 0xe5,
|
||||
0xe5, 0xe5, 0x17, 0xe5, 0xe5, 0xe5, 0x3e, 0x02,
|
||||
0xe8, 0x54, 0x04, 0x03, 0x1c, 0x02, 0x02, 0x18,
|
||||
0x1d, 0x20, 0x01, 0xe6, 0x17, 0x03, 0x01, 0xe6,
|
||||
0x15, 0x01, 0x1b, 0x01, 0x1d, 0x23, 0xe5, 0x01,
|
||||
0xe5, 0x16, 0x01, 0x1b, 0x01, 0x22, 0x1f, 0x03,
|
||||
0x09, 0x02, 0x4e, 0x1e, 0xe8, 0xe5, 0x59, 0x01,
|
||||
0x1d, 0xe7, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x0b,
|
||||
0x09, 0x09, 0x03, 0x05, 0x09, 0x0d, 0x01, 0x01,
|
||||
0xe5, 0x01, 0x74, 0x04, 0xe6, 0x7a, 0xe5, 0xe5,
|
||||
0x79, 0xe5, 0xe6, 0x53, 0x03, 0xe5, 0x1f, 0xe9,
|
||||
0x53, 0x01, 0x21, 0xe5, 0x01, 0xe5, 0x08, 0x0b,
|
||||
0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x09, 0xe5, 0x07, 0xe6, 0xe5, 0x04, 0xe5,
|
||||
0x07, 0xe5, 0x07, 0xe5, 0x05, 0x01, 0x02, 0x55,
|
||||
0x01, 0x26, 0x55, 0x01, 0x22, 0x03, 0x40, 0x14,
|
||||
0x01, 0x23, 0x02, 0x04, 0x50, 0x01, 0x02, 0x22,
|
||||
0xe5, 0x01, 0x0e, 0x43, 0x1b, 0x0b, 0xe5, 0x02,
|
||||
0xe5, 0x0b, 0x01, 0x07, 0x01, 0x07, 0x01, 0xe5,
|
||||
0x05, 0x01, 0x07, 0x01, 0x04, 0x04, 0x01, 0x01,
|
||||
0x05, 0x01, 0x07, 0x01, 0x01, 0x04, 0xe5, 0xe5,
|
||||
0x06, 0x01, 0x02, 0x05, 0x04, 0xe5, 0x53, 0x01,
|
||||
0x27, 0xe5, 0x72, 0x04, 0xe7, 0xe5, 0x2f, 0x0e,
|
||||
0xe5, 0x11, 0x0a, 0x09, 0x11, 0x03, 0xe5, 0x1b,
|
||||
0x1b, 0x1b, 0x01, 0x01, 0x14, 0x0e, 0xe5, 0x1c,
|
||||
0x13, 0x07, 0x05, 0xe5, 0x16, 0x15, 0x0b, 0xe5,
|
||||
0x01, 0xe5, 0x0c, 0xe5, 0xe5, 0x17, 0x02, 0x0a,
|
||||
0x06, 0xe5, 0x05, 0x0d, 0x1a, 0x0a, 0x01, 0xe5,
|
||||
0x12, 0x17, 0xe5, 0x11, 0x0f, 0x17, 0x12, 0x01,
|
||||
0xe6, 0x1b, 0x10, 0x11, 0x19, 0x20, 0xe5, 0x01,
|
||||
0x1e, 0x20, 0x3e, 0x3f, 0x24, 0x19, 0x02, 0x0a,
|
||||
0x01, 0x30, 0xe5, 0xe5, 0x28, 0x0d, 0xe5, 0xe5,
|
||||
0x0e, 0x33, 0x2c, 0x08, 0x02, 0xe6, 0x0e, 0x17,
|
||||
0x1a, 0x37, 0xe5, 0xe6, 0x02, 0x0b, 0xe5, 0x07,
|
||||
0xe5, 0x07, 0xe5, 0x05, 0xe7, 0x07, 0xe5, 0x06,
|
||||
0xe8, 0x05, 0xe7, 0x05, 0xe7, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x0b, 0xe6, 0xe6, 0x0f, 0x09, 0x09, 0x07,
|
||||
0x01, 0x09, 0x09, 0x01, 0x05, 0x01, 0x01, 0x07,
|
||||
0x01, 0x09, 0x07, 0x01, 0x01, 0x0b, 0xe6, 0xe5,
|
||||
0x0e, 0x0a, 0x03, 0x04, 0xe5, 0x07, 0x0a, 0x07,
|
||||
0x02, 0x01, 0x02, 0x04, 0x09, 0x05, 0xe5, 0x01,
|
||||
0x04, 0x04, 0x10, 0x01, 0x11, 0x4b, 0x1c, 0xe6,
|
||||
0xe5, 0x18, 0x09, 0x04, 0x06, 0x07, 0x01, 0x09,
|
||||
0x09, 0x09, 0x09, 0x09, 0x02, 0x0b, 0x02, 0xe5,
|
||||
0x0c, 0xe6, 0x05, 0xe6, 0x01, 0x05, 0xe5, 0x07,
|
||||
0xe6, 0x06, 0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07,
|
||||
0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x06, 0x04,
|
||||
0x03, 0x02, 0x03, 0x09, 0x09, 0x01, 0x07, 0x01,
|
||||
0x07, 0x09, 0x01, 0x05, 0x03, 0x09, 0x09, 0x09,
|
||||
0x09, 0x11, 0x02, 0x0e, 0xe5, 0x07, 0x09, 0x09,
|
||||
0xe5, 0x07, 0x0b, 0x02, 0x06, 0xe5, 0xe5, 0x05,
|
||||
0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
|
||||
0x0e, 0xe5, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x0b,
|
||||
0x09, 0x09, 0x09, 0x09, 0x0f, 0xe5, 0x01, 0x12,
|
||||
0x06, 0x09, 0xe5, 0x11, 0x05, 0x05, 0xe5, 0x37,
|
||||
0xe5, 0x0d, 0x06, 0x02, 0x09, 0x09, 0x09, 0x08,
|
||||
0x02, 0x09, 0x09, 0x09, 0x09, 0x0f, 0xe8, 0x3e,
|
||||
0x1d, 0x20, 0x10, 0x09, 0x09, 0x09, 0x09, 0x0b,
|
||||
0x09, 0x09, 0x09, 0x09, 0x0d, 0x02, 0xe5, 0x03,
|
||||
0x04, 0x1f, 0x33, 0x20, 0x3f, 0x3b, 0xe5, 0xe5,
|
||||
0x17, 0x1d, 0x08, 0x02, 0x33, 0x05, 0xe6, 0x03,
|
||||
0x13, 0x06, 0x02, 0x13, 0x06, 0x0b, 0x16, 0x06,
|
||||
0x13, 0x01, 0xe5, 0x03, 0x4c, 0x0c, 0x1b, 0xe5,
|
||||
0x01, 0x17, 0x08, 0x14, 0x08, 0xe5, 0x1e, 0x13,
|
||||
0x06, 0x01, 0xe6, 0x20, 0x1d, 0x34, 0x06, 0xe5,
|
||||
0xe5, 0x48, 0x15, 0x07, 0x12, 0xe8, 0x13, 0x02,
|
||||
0xe5, 0x04, 0xe8, 0x04, 0x09, 0x02, 0xe5, 0x04,
|
||||
0xe6, 0x08, 0xe6, 0x06, 0x09, 0x02, 0xe5, 0x04,
|
||||
0xe6, 0x06, 0x09, 0xe8, 0x0d, 0xe5, 0x06, 0xe6,
|
||||
0x05, 0xe7, 0x08, 0x07, 0xe6, 0x05, 0xe5, 0x01,
|
||||
0xe5, 0x05, 0x02, 0x09, 0x07, 0xe6, 0x05, 0x02,
|
||||
0x0e, 0xe8, 0x25, 0x18, 0x3b, 0x01, 0xe5, 0x14,
|
||||
0x05, 0x03, 0x09, 0x01, 0x07, 0x05, 0x03, 0x07,
|
||||
0x03, 0x01, 0x03, 0x05, 0x03, 0x0d, 0x01, 0x03,
|
||||
0x0c, 0x01, 0xe6, 0x0a, 0x03, 0x02, 0x01, 0x06,
|
||||
0xe5, 0x07, 0x02, 0x03, 0x03, 0x01, 0x07, 0x08,
|
||||
0x0b, 0x04, 0x05, 0x03, 0x0e, 0x04, 0xe9, 0x03,
|
||||
0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff,
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,53 @@
|
|||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
# ifneq ($(OBJTREE),$(SRCTREE))
|
||||
# $(shell mkdir -p $(obj)../common/xilinx_jtag)
|
||||
# endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
# Objects for Xilinx JTAG programming (CPLD)
|
||||
# CPLD = ../common/xilinx_jtag/lenval.o \
|
||||
# ../common/xilinx_jtag/micro.o \
|
||||
# ../common/xilinx_jtag/ports.o
|
||||
|
||||
# COBJS = $(BOARD).o flash.o $(CPLD)
|
||||
COBJS = $(BOARD).o strataflash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* cpci5200.c - main board support/init for the esd cpci5200.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc5xxx.h>
|
||||
#include <pci.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#include "mt46v16m16-75.h"
|
||||
|
||||
void init_ata_reset(void);
|
||||
|
||||
static void sdram_start(int hi_addr)
|
||||
{
|
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
||||
|
||||
/* unlock mode register */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL =
|
||||
SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* precharge all banks */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL =
|
||||
SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* set mode register: extended mode */
|
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* set mode register: reset DLL */
|
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* precharge all banks */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL =
|
||||
SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* auto refresh */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL =
|
||||
SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* set mode register */
|
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* normal operation */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
/*
|
||||
* ATTENTION: Although partially referenced initdram does NOT make real use
|
||||
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
|
||||
* is something else than 0x00000000.
|
||||
*/
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
ulong dramsize = 0;
|
||||
ulong test1, test2;
|
||||
|
||||
/* setup SDRAM chip selects */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* setup config registers */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
|
||||
*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* set tap delay */
|
||||
*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
/* find RAM size using SDRAM CS0 only */
|
||||
sdram_start(0);
|
||||
test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
|
||||
sdram_start(1);
|
||||
test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
|
||||
|
||||
if (test1 > test2) {
|
||||
sdram_start(0);
|
||||
dramsize = test1;
|
||||
} else {
|
||||
dramsize = test2;
|
||||
}
|
||||
|
||||
/* memory smaller than 1MB is impossible */
|
||||
if (dramsize < (1 << 20)) {
|
||||
dramsize = 0;
|
||||
}
|
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */
|
||||
if (dramsize > 0) {
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
|
||||
0x13 + __builtin_ffs(dramsize >> 20) - 1;
|
||||
/* let SDRAM CS1 start right after CS0 */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
|
||||
} else {
|
||||
#if 0
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
|
||||
/* let SDRAM CS1 start right after CS0 */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
|
||||
#else
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
|
||||
0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
|
||||
/* let SDRAM CS1 start right after CS0 */
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
|
||||
#endif
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* find RAM size using SDRAM CS1 only */
|
||||
sdram_start(0);
|
||||
get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
||||
sdram_start(1);
|
||||
get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
|
||||
sdram_start(0);
|
||||
#endif
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */
|
||||
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
||||
|
||||
init_ata_reset();
|
||||
return (dramsize);
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: esd CPCI5200 (cpci5200)\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flash_preinit(void)
|
||||
{
|
||||
/*
|
||||
* Now, when we are in RAM, enable flash write
|
||||
* access for detection process.
|
||||
* Note that CS_BOOT cannot be cleared when
|
||||
* executing in flash.
|
||||
*/
|
||||
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
}
|
||||
|
||||
void flash_afterinit(ulong size)
|
||||
{
|
||||
if (size == 0x02000000) {
|
||||
/* adjust mapping */
|
||||
*(vu_long *) MPC5XXX_BOOTCS_START =
|
||||
*(vu_long *) MPC5XXX_CS0_START =
|
||||
START_REG(CONFIG_SYS_BOOTCS_START | size);
|
||||
*(vu_long *) MPC5XXX_BOOTCS_STOP =
|
||||
*(vu_long *) MPC5XXX_CS0_STOP =
|
||||
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void) {
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
||||
|
||||
void init_ide_reset(void)
|
||||
{
|
||||
debug("init_ide_reset\n");
|
||||
|
||||
/* Configure PSC1_4 as GPIO output for ATA reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
|
||||
}
|
||||
|
||||
void ide_set_reset(int idereset)
|
||||
{
|
||||
debug("ide_reset(%d)\n", idereset);
|
||||
|
||||
if (idereset) {
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
|
||||
} else {
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
|
||||
#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
|
||||
#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
|
||||
#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
|
||||
|
||||
#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
|
||||
#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
|
||||
#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
|
||||
#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
|
||||
|
||||
#define GPIO_WU6 0x40000000UL
|
||||
#define GPIO_USB0 0x00010000UL
|
||||
#define GPIO_USB9 0x08000000UL
|
||||
#define GPIO_USB9S 0x00080000UL
|
||||
|
||||
void init_ata_reset(void)
|
||||
{
|
||||
debug("init_ata_reset\n");
|
||||
|
||||
/* Configure GPIO_WU6 as GPIO output for ATA reset */
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
|
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
|
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
|
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
|
||||
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
|
||||
__asm__ volatile ("sync");
|
||||
|
||||
if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
|
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int size;
|
||||
int i;
|
||||
volatile unsigned long *ptr;
|
||||
|
||||
addr = simple_strtol(argv[1], NULL, 16);
|
||||
size = simple_strtol(argv[2], NULL, 16);
|
||||
|
||||
printf("\nWriting at addr %08x, size %08x.\n", addr, size);
|
||||
|
||||
while (1) {
|
||||
ptr = (volatile unsigned long *)addr;
|
||||
for (i = 0; i < (size >> 2); i++) {
|
||||
*ptr++ = i;
|
||||
}
|
||||
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
putc('.');
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(writepci, 3, 1, do_writepci,
|
||||
"Write some data to pcibus",
|
||||
"<addr> <size>\n"
|
||||
""
|
||||
);
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define SDRAM_DDR 1 /* is DDR */
|
||||
|
||||
/* Settings for XLB = 132 MHz */
|
||||
#define SDRAM_MODE 0x018D0000
|
||||
#define SDRAM_EMODE 0x40090000
|
||||
#define SDRAM_CONTROL 0x705f0f00
|
||||
#define SDRAM_CONFIG1 0x73722930
|
||||
#define SDRAM_CONFIG2 0x47770000
|
||||
#define SDRAM_TAPDELAY 0x10000000
|
||||
|
|
@ -0,0 +1,802 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#undef DEBUG_FLASH
|
||||
/*
|
||||
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
|
||||
* The width of the port and the width of the chips are determined at initialization.
|
||||
* These widths are used to calculate the address for access CFI data structures.
|
||||
* It has been tested on an Intel Strataflash implementation.
|
||||
*
|
||||
* References
|
||||
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
|
||||
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
|
||||
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
|
||||
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
|
||||
*
|
||||
* TODO
|
||||
* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
|
||||
* Add support for other command sets Use the PRI and ALT to determine command set
|
||||
* Verify erase and program timeouts.
|
||||
*/
|
||||
|
||||
#define FLASH_CMD_CFI 0x98
|
||||
#define FLASH_CMD_READ_ID 0x90
|
||||
#define FLASH_CMD_RESET 0xff
|
||||
#define FLASH_CMD_BLOCK_ERASE 0x20
|
||||
#define FLASH_CMD_ERASE_CONFIRM 0xD0
|
||||
#define FLASH_CMD_WRITE 0x40
|
||||
#define FLASH_CMD_PROTECT 0x60
|
||||
#define FLASH_CMD_PROTECT_SET 0x01
|
||||
#define FLASH_CMD_PROTECT_CLEAR 0xD0
|
||||
#define FLASH_CMD_CLEAR_STATUS 0x50
|
||||
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
|
||||
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
|
||||
|
||||
#define FLASH_STATUS_DONE 0x80
|
||||
#define FLASH_STATUS_ESS 0x40
|
||||
#define FLASH_STATUS_ECLBS 0x20
|
||||
#define FLASH_STATUS_PSLBS 0x10
|
||||
#define FLASH_STATUS_VPENS 0x08
|
||||
#define FLASH_STATUS_PSS 0x04
|
||||
#define FLASH_STATUS_DPS 0x02
|
||||
#define FLASH_STATUS_R 0x01
|
||||
#define FLASH_STATUS_PROTECT 0x01
|
||||
|
||||
#define FLASH_OFFSET_CFI 0x55
|
||||
#define FLASH_OFFSET_CFI_RESP 0x10
|
||||
#define FLASH_OFFSET_WTOUT 0x1F
|
||||
#define FLASH_OFFSET_WBTOUT 0x20
|
||||
#define FLASH_OFFSET_ETOUT 0x21
|
||||
#define FLASH_OFFSET_CETOUT 0x22
|
||||
#define FLASH_OFFSET_WMAX_TOUT 0x23
|
||||
#define FLASH_OFFSET_WBMAX_TOUT 0x24
|
||||
#define FLASH_OFFSET_EMAX_TOUT 0x25
|
||||
#define FLASH_OFFSET_CEMAX_TOUT 0x26
|
||||
#define FLASH_OFFSET_SIZE 0x27
|
||||
#define FLASH_OFFSET_INTERFACE 0x28
|
||||
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
|
||||
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
|
||||
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
|
||||
#define FLASH_OFFSET_PROTECT 0x02
|
||||
#define FLASH_OFFSET_USER_PROTECTION 0x85
|
||||
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
|
||||
|
||||
#define FLASH_MAN_CFI 0x01000000
|
||||
|
||||
typedef union {
|
||||
unsigned char c;
|
||||
unsigned short w;
|
||||
unsigned long l;
|
||||
} cfiword_t;
|
||||
|
||||
typedef union {
|
||||
unsigned char *cp;
|
||||
unsigned short *wp;
|
||||
unsigned long *lp;
|
||||
} cfiptr_t;
|
||||
|
||||
#define NUM_ERASE_REGIONS 4
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
|
||||
static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
|
||||
uchar cmd);
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset,
|
||||
uchar cmd);
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_detect_cfi(flash_info_t * info);
|
||||
static ulong flash_get_size(ulong base, int banknum);
|
||||
static int flash_write_cfiword(flash_info_t * info, ulong dest,
|
||||
cfiword_t cword);
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector,
|
||||
ulong tout, char *prompt);
|
||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
|
||||
int len);
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* create an address based on the offset and the port width
|
||||
*/
|
||||
inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
|
||||
{
|
||||
return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a character at a port width address
|
||||
*/
|
||||
inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
|
||||
{
|
||||
uchar *cp;
|
||||
cp = flash_make_addr(info, 0, offset);
|
||||
return (cp[info->portwidth - 1]);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a short word by swapping for ppc format.
|
||||
*/
|
||||
ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar *addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ((addr[(2 * info->portwidth) - 1] << 8) |
|
||||
addr[info->portwidth - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a long word by picking the least significant byte of each maiximum
|
||||
* port size word. Swap for ppc format.
|
||||
*/
|
||||
ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar *addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ((addr[(2 * info->portwidth) - 1] << 24) |
|
||||
(addr[(info->portwidth) - 1] << 16) |
|
||||
(addr[(4 * info->portwidth) - 1] << 8) |
|
||||
addr[(3 * info->portwidth) - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long size;
|
||||
int i;
|
||||
unsigned long address;
|
||||
|
||||
/* The flash is positioned back to back, with the demultiplexing of the chip
|
||||
* based on the A24 address line.
|
||||
*
|
||||
*/
|
||||
|
||||
address = CONFIG_SYS_FLASH_BASE;
|
||||
size = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size += flash_info[i].size = flash_get_size(address, i);
|
||||
address += CONFIG_SYS_FLASH_INCREMENT;
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf
|
||||
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i, flash_info[0].size, flash_info[i].size << 20);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 /* test-only */
|
||||
/* Monitor protection ON by default */
|
||||
#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
|
||||
for (i = 0;
|
||||
flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
|
||||
i++)
|
||||
(void)flash_real_protect(&flash_info[0], i, 1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int rcode = 0;
|
||||
int prot;
|
||||
int sect;
|
||||
|
||||
if (info->flash_id != FLASH_MAN_CFI) {
|
||||
printf("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
printf("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot) {
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
|
||||
|
||||
if (flash_full_status_check
|
||||
(info, sect, info->erase_blk_tout, "erase")) {
|
||||
rcode = 1;
|
||||
} else
|
||||
printf(".");
|
||||
}
|
||||
}
|
||||
printf(" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info(flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id != FLASH_MAN_CFI) {
|
||||
printf("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("CFI conformant FLASH (%d x %d)",
|
||||
(info->portwidth << 3), (info->chipwidth << 3));
|
||||
printf(" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
printf
|
||||
(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
|
||||
info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
|
||||
info->buffer_size);
|
||||
|
||||
printf(" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf("\n");
|
||||
printf(" %08lX%5s",
|
||||
info->start[i], info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp;
|
||||
ulong cp;
|
||||
int aln;
|
||||
cfiword_t cword;
|
||||
int i, rc;
|
||||
|
||||
/* get lower aligned address */
|
||||
wp = (addr & ~(info->portwidth - 1));
|
||||
|
||||
/* handle unaligned start */
|
||||
if ((aln = addr - wp) != 0) {
|
||||
cword.l = 0;
|
||||
cp = wp;
|
||||
for (i = 0; i < aln; ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *) cp));
|
||||
|
||||
for (; (i < info->portwidth) && (cnt > 0); i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
cnt--;
|
||||
cp++;
|
||||
}
|
||||
for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *) cp));
|
||||
if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp = cp;
|
||||
}
|
||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
while (cnt >= info->portwidth) {
|
||||
i = info->buffer_size > cnt ? cnt : info->buffer_size;
|
||||
if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
|
||||
return rc;
|
||||
wp += i;
|
||||
src += i;
|
||||
cnt -= i;
|
||||
}
|
||||
#else
|
||||
/* handle the aligned part */
|
||||
while (cnt >= info->portwidth) {
|
||||
cword.l = 0;
|
||||
for (i = 0; i < info->portwidth; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
}
|
||||
if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp += info->portwidth;
|
||||
cnt -= info->portwidth;
|
||||
}
|
||||
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
cword.l = 0;
|
||||
for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
--cnt;
|
||||
}
|
||||
for (; i < info->portwidth; ++i, ++cp) {
|
||||
flash_add_byte(info, &cword, (*(uchar *) cp));
|
||||
}
|
||||
|
||||
return flash_write_cfiword(info, wp, cword);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect(flash_info_t * info, long sector, int prot)
|
||||
{
|
||||
int retcode = 0;
|
||||
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
|
||||
if (prot)
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
|
||||
else
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
|
||||
|
||||
if ((retcode =
|
||||
flash_full_status_check(info, sector, info->erase_blk_tout,
|
||||
prot ? "protect" : "unprotect")) == 0) {
|
||||
|
||||
info->protect[sector] = prot;
|
||||
/* Intel's unprotect unprotects all locking */
|
||||
if (prot == 0) {
|
||||
int i;
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if (info->protect[i])
|
||||
flash_real_protect(info, i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* wait for XSR.7 to be set. Time out with an error if it does not.
|
||||
* This routine does not set the flash to read-array mode.
|
||||
*/
|
||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
|
||||
char *prompt)
|
||||
{
|
||||
ulong start;
|
||||
|
||||
/* Wait for command completion */
|
||||
start = get_timer(0);
|
||||
while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
|
||||
if (get_timer(start) > info->erase_blk_tout) {
|
||||
printf("Flash %s timeout at address %lx\n", prompt,
|
||||
info->start[sector]);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
}
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
|
||||
* This routine sets the flash to read-array mode.
|
||||
*/
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector,
|
||||
ulong tout, char *prompt)
|
||||
{
|
||||
int retcode;
|
||||
retcode = flash_status_check(info, sector, tout, prompt);
|
||||
if ((retcode == ERR_OK)
|
||||
&& !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
|
||||
retcode = ERR_INVAL;
|
||||
printf("Flash %s error at address %lx\n", prompt,
|
||||
info->start[sector]);
|
||||
if (flash_isset
|
||||
(info, sector, 0,
|
||||
FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
|
||||
printf("Command Sequence Error.\n");
|
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
|
||||
printf("Block Erase Error.\n");
|
||||
retcode = ERR_NOT_ERASED;
|
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
|
||||
printf("Locking Error\n");
|
||||
}
|
||||
if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
|
||||
printf("Block locked.\n");
|
||||
retcode = ERR_PROTECTED;
|
||||
}
|
||||
if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
|
||||
printf("Vpp Low Error.\n");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return retcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
|
||||
{
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cword->c = c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cword->w = (cword->w << 8) | c;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cword->l = (cword->l << 8) | c;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths
|
||||
*/
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
|
||||
{
|
||||
int i;
|
||||
uchar *cp = (uchar *) cmdbuf;
|
||||
for (i = 0; i < info->portwidth; i++)
|
||||
*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address
|
||||
*/
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
|
||||
uchar cmd)
|
||||
{
|
||||
|
||||
volatile cfiptr_t addr;
|
||||
cfiword_t cword;
|
||||
addr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*addr.cp = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*addr.wp = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*addr.lp = cword.l;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = (cptr.cp[0] == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = (cptr.wp[0] == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = (cptr.lp[0] == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI)
|
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
*
|
||||
*/
|
||||
static int flash_detect_cfi(flash_info_t * info)
|
||||
{
|
||||
|
||||
for (info->portwidth = FLASH_CFI_8BIT;
|
||||
info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
|
||||
for (info->chipwidth = FLASH_CFI_BY8;
|
||||
info->chipwidth <= info->portwidth;
|
||||
info->chipwidth <<= 1) {
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
|
||||
FLASH_CMD_CFI);
|
||||
if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
|
||||
&& flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
|
||||
'R')
|
||||
&& flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
|
||||
'Y'))
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*
|
||||
*/
|
||||
static ulong flash_get_size(ulong base, int banknum)
|
||||
{
|
||||
flash_info_t *info = &flash_info[banknum];
|
||||
int i, j;
|
||||
int sect_cnt;
|
||||
unsigned long sector;
|
||||
unsigned long tmp;
|
||||
int size_ratio = 0;
|
||||
uchar num_erase_regions;
|
||||
int erase_region_size;
|
||||
int erase_region_count;
|
||||
|
||||
info->start[0] = base;
|
||||
#if 0
|
||||
invalidate_dcache_range(base, base + 0x400);
|
||||
#endif
|
||||
if (flash_detect_cfi(info)) {
|
||||
|
||||
size_ratio = info->portwidth / info->chipwidth;
|
||||
num_erase_regions =
|
||||
flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
|
||||
|
||||
sect_cnt = 0;
|
||||
sector = base;
|
||||
for (i = 0; i < num_erase_regions; i++) {
|
||||
if (i > NUM_ERASE_REGIONS) {
|
||||
printf("%d erase regions found, only %d used\n",
|
||||
num_erase_regions, NUM_ERASE_REGIONS);
|
||||
break;
|
||||
}
|
||||
tmp =
|
||||
flash_read_long(info, 0,
|
||||
FLASH_OFFSET_ERASE_REGIONS);
|
||||
erase_region_size =
|
||||
(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
|
||||
tmp >>= 16;
|
||||
erase_region_count = (tmp & 0xffff) + 1;
|
||||
for (j = 0; j < erase_region_count; j++) {
|
||||
info->start[sect_cnt] = sector;
|
||||
sector += (erase_region_size * size_ratio);
|
||||
info->protect[sect_cnt] =
|
||||
flash_isset(info, sect_cnt,
|
||||
FLASH_OFFSET_PROTECT,
|
||||
FLASH_STATUS_PROTECT);
|
||||
sect_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
info->sector_count = sect_cnt;
|
||||
/* multiply the size by the number of chips */
|
||||
info->size =
|
||||
(1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
|
||||
size_ratio;
|
||||
info->buffer_size =
|
||||
(1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
|
||||
info->erase_blk_tout =
|
||||
(tmp *
|
||||
(1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
|
||||
info->buffer_write_tout =
|
||||
(tmp *
|
||||
(1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
|
||||
info->write_tout =
|
||||
(tmp *
|
||||
(1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
|
||||
1000;
|
||||
info->flash_id = FLASH_MAN_CFI;
|
||||
}
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
|
||||
#endif
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("found %d erase regions\n", num_erase_regions);
|
||||
#endif
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
|
||||
#endif
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
|
||||
{
|
||||
|
||||
cfiptr_t cptr;
|
||||
int flag;
|
||||
|
||||
cptr.cp = (uchar *)dest;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
flag = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
flag = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
flag = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
return 2;
|
||||
}
|
||||
if (!flag)
|
||||
return 2;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
|
||||
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cptr.cp[0] = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cptr.wp[0] = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cptr.lp[0] = cword.l;
|
||||
break;
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address
|
||||
* we have a match
|
||||
*/
|
||||
static int find_sector(flash_info_t * info, ulong addr)
|
||||
{
|
||||
int sector;
|
||||
for (sector = info->sector_count - 1; sector >= 0; sector--) {
|
||||
if (addr >= info->start[sector])
|
||||
break;
|
||||
}
|
||||
return sector;
|
||||
}
|
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
|
||||
int len)
|
||||
{
|
||||
|
||||
int sector;
|
||||
int cnt;
|
||||
int retcode;
|
||||
volatile cfiptr_t src;
|
||||
volatile cfiptr_t dst;
|
||||
|
||||
src.cp = cp;
|
||||
dst.cp = (uchar *) dest;
|
||||
sector = find_sector(info, dest);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
|
||||
if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
|
||||
"write to buffer")) == ERR_OK) {
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cnt = len;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cnt = len >> 1;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cnt = len >> 2;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
|
||||
while (cnt-- > 0) {
|
||||
switch (info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*dst.cp++ = *src.cp++;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*dst.wp++ = *src.wp++;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*dst.lp++ = *src.lp++;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
flash_write_cmd(info, sector, 0,
|
||||
FLASH_CMD_WRITE_BUFFER_CONFIRM);
|
||||
retcode =
|
||||
flash_full_status_check(info, sector,
|
||||
info->buffer_write_tout,
|
||||
"buffer write");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
return retcode;
|
||||
}
|
||||
#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
* for cpci750 Reinhard Arlt
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* main board support/init for the cpci750.
|
||||
*/
|
||||
|
||||
#ifndef __64360_H__
|
||||
#define __64360_H__
|
||||
|
||||
/* CPU Configuration bits */
|
||||
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
|
||||
#define CPU_CONF_SINGLE_CPU (1 << 11)
|
||||
#define CPU_CONF_ENDIANESS (1 << 12)
|
||||
#define CPU_CONF_PIPELINE (1 << 13)
|
||||
#define CPU_CONF_STOP_RETRY (1 << 17)
|
||||
#define CPU_CONF_MULTI_DECODE (1 << 18)
|
||||
#define CPU_CONF_DP_VALID (1 << 19)
|
||||
#define CPU_CONF_PERR_PROP (1 << 22)
|
||||
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
|
||||
#define CPU_CONF_AP_VALID (1 << 26)
|
||||
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
|
||||
|
||||
/* CPU Master Control bits */
|
||||
#define CPU_MAST_CTL_ARB_EN (1 << 8)
|
||||
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
|
||||
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
|
||||
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
|
||||
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
|
||||
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
|
||||
|
||||
#endif /* __64360_H__ */
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../../Marvell/common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
SOBJS = misc.o
|
||||
|
||||
COBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
|
||||
mv_eth.o mpsc.o i2c.o \
|
||||
sdram_init.o ide.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
1108
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/cpci750.c
Normal file
1108
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/cpci750.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __EVB64360_ETH_H__
|
||||
#define __EVB64360_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
|
||||
|
||||
int db64360_eth0_poll(void);
|
||||
int db64360_eth0_transmit(unsigned int s, volatile char *p);
|
||||
void db64360_eth0_disable(void);
|
||||
bool network_start(bd_t *bis);
|
||||
|
||||
int mv6436x_eth_initialize(bd_t *);
|
||||
|
||||
#endif /* __EVB64360_ETH_H__ */
|
||||
491
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/i2c.c
Normal file
491
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/i2c.c
Normal file
|
|
@ -0,0 +1,491 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
|
||||
* extra improvments by Brain Waite
|
||||
* for cpci750 by reinhard.arlt@esd-electronics.com
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <malloc.h>
|
||||
#include <i2c.h>
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
#include "../../Marvell/include/core.h"
|
||||
|
||||
#define I2C_DELAY 100
|
||||
#undef DEBUG_I2C
|
||||
|
||||
#ifdef DEBUG_I2C
|
||||
#define DP(x) x
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
/* Assuming that there is only one master on the bus (us) */
|
||||
|
||||
void i2c_init (int speed, int slaveaddr)
|
||||
{
|
||||
unsigned int n, m, freq, margin, power;
|
||||
unsigned int actualN = 0, actualM = 0;
|
||||
unsigned int minMargin = 0xffffffff;
|
||||
unsigned int tclk = CONFIG_SYS_TCLK;
|
||||
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
|
||||
|
||||
DP (puts ("i2c_init\n"));
|
||||
/* gtI2cMasterInit */
|
||||
for (n = 0; n < 8; n++) {
|
||||
for (m = 0; m < 16; m++) {
|
||||
power = 2 << n; /* power = 2^(n+1) */
|
||||
freq = tclk / (10 * (m + 1) * power);
|
||||
if (i2cFreq > freq)
|
||||
margin = i2cFreq - freq;
|
||||
else
|
||||
margin = freq - i2cFreq;
|
||||
if (margin < minMargin) {
|
||||
minMargin = margin;
|
||||
actualN = n;
|
||||
actualM = m;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DP (puts ("setup i2c bus\n"));
|
||||
|
||||
/* Setup bus */
|
||||
/* gtI2cReset */
|
||||
GT_REG_WRITE (I2C_SOFT_RESET, 0);
|
||||
asm(" sync");
|
||||
GT_REG_WRITE (I2C_CONTROL, 0);
|
||||
asm(" sync");
|
||||
|
||||
DP (puts ("set baudrate\n"));
|
||||
|
||||
GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
|
||||
asm(" sync");
|
||||
|
||||
DP (puts ("udelay...\n"));
|
||||
|
||||
udelay (I2C_DELAY);
|
||||
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
|
||||
asm(" sync");
|
||||
}
|
||||
|
||||
|
||||
static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
|
||||
{
|
||||
unsigned int status, data, bits = 7;
|
||||
unsigned int control;
|
||||
int count = 0;
|
||||
|
||||
DP (puts ("i2c_select_device\n"));
|
||||
|
||||
/* Output slave address */
|
||||
|
||||
if (ten_bit) {
|
||||
bits = 10;
|
||||
}
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &control);
|
||||
control |= (0x1 << 2);
|
||||
GT_REG_WRITE (I2C_CONTROL, control);
|
||||
asm(" sync");
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &control);
|
||||
control |= (0x1 << 5); /* generate the I2C_START_BIT */
|
||||
GT_REG_WRITE (I2C_CONTROL, control);
|
||||
asm(" sync");
|
||||
RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
|
||||
asm(" sync");
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
|
||||
count = 0;
|
||||
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
|
||||
if (count > 200) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to set startbit: 0x%02x\n", status);
|
||||
#endif
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
asm(" sync");
|
||||
return (status);
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
}
|
||||
|
||||
DP (puts ("i2c_select_device:write addr byte\n"));
|
||||
|
||||
/* assert the address */
|
||||
|
||||
data = (dev_addr << 1);
|
||||
/* set the read bit */
|
||||
data |= read;
|
||||
GT_REG_WRITE (I2C_DATA, data);
|
||||
asm(" sync");
|
||||
RESET_REG_BITS (I2C_CONTROL, BIT3);
|
||||
asm(" sync");
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count = 0;
|
||||
while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
|
||||
if (count > 200) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to write address: 0x%02x\n", status);
|
||||
#endif
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
return (status);
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
asm(" sync");
|
||||
count++;
|
||||
}
|
||||
|
||||
if (bits == 10) {
|
||||
printf ("10 bit I2C addressing not yet implemented\n");
|
||||
return (0xff);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uchar i2c_get_data (uchar * return_data, int len)
|
||||
{
|
||||
|
||||
unsigned int data, status;
|
||||
int count = 0;
|
||||
|
||||
DP (puts ("i2c_get_data\n"));
|
||||
|
||||
while (len) {
|
||||
|
||||
RESET_REG_BITS (I2C_CONTROL, BIT3);
|
||||
asm(" sync");
|
||||
|
||||
/* Get and return the data */
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
while ((status & 0xff) != 0x50) {
|
||||
if (count > 20) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to get data len status: 0x%02x\n", status);
|
||||
#endif
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
asm(" sync");
|
||||
return 0;
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
}
|
||||
GT_REG_READ (I2C_DATA, &data);
|
||||
len--;
|
||||
*return_data = (uchar) data;
|
||||
return_data++;
|
||||
|
||||
}
|
||||
RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
|
||||
asm(" sync");
|
||||
count = 0;
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
while ((status & 0xff) != 0x58) {
|
||||
if (count > 2000) {
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
return (status);
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
}
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
|
||||
asm(" sync");
|
||||
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
|
||||
asm(" sync");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
static uchar i2c_write_data (unsigned int *data, int len)
|
||||
{
|
||||
unsigned int status;
|
||||
int count;
|
||||
unsigned int temp;
|
||||
unsigned int *temp_ptr = data;
|
||||
|
||||
DP (puts ("i2c_write_data\n"));
|
||||
|
||||
while (len) {
|
||||
count = 0;
|
||||
temp = (unsigned int) (*temp_ptr);
|
||||
GT_REG_WRITE (I2C_DATA, temp);
|
||||
asm(" sync");
|
||||
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
|
||||
asm(" sync");
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
while ((status & 0xff) != 0x28) {
|
||||
if (count > 200) {
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
asm(" sync");
|
||||
return (status);
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
}
|
||||
len--;
|
||||
temp_ptr++;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
static uchar i2c_write_byte (unsigned char *data, int len)
|
||||
{
|
||||
unsigned int status;
|
||||
int count;
|
||||
unsigned int temp;
|
||||
unsigned char *temp_ptr = data;
|
||||
|
||||
DP (puts ("i2c_write_byte\n"));
|
||||
|
||||
while (len) {
|
||||
count = 0;
|
||||
/* Set and assert the data */
|
||||
temp = *temp_ptr;
|
||||
GT_REG_WRITE (I2C_DATA, temp);
|
||||
asm(" sync");
|
||||
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
|
||||
asm(" sync");
|
||||
|
||||
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
while ((status & 0x08) != 0x08) {
|
||||
GT_REG_READ (I2C_CONTROL, &status);
|
||||
}
|
||||
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
while ((status & 0xff) != 0x28) {
|
||||
if (count > 200) {
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
|
||||
asm(" sync");
|
||||
return (status);
|
||||
}
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
|
||||
count++;
|
||||
}
|
||||
len--;
|
||||
temp_ptr++;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uchar
|
||||
i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
|
||||
int alen)
|
||||
{
|
||||
uchar status;
|
||||
unsigned int table[2];
|
||||
|
||||
table[1] = (offset ) & 0x0ff; /* low byte */
|
||||
table[0] = (offset >> 8) & 0x0ff; /* high byte */
|
||||
|
||||
DP (puts ("i2c_set_dev_offset\n"));
|
||||
|
||||
status = i2c_select_device (dev_addr, 0, ten_bit);
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
22 printf ("Failed to select device setting offset: 0x%02x\n",
|
||||
status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
/* check the address offset length */
|
||||
if (alen == 0)
|
||||
/* no address offset */
|
||||
return (0);
|
||||
else if (alen == 1) {
|
||||
/* 1 byte address offset */
|
||||
status = i2c_write_data (&offset, 1);
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to write data: 0x%02x\n", status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
} else if (alen == 2) {
|
||||
/* 2 bytes address offset */
|
||||
status = i2c_write_data (table, 2);
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to write data: 0x%02x\n", status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
} else {
|
||||
/* address offset unknown or not supported */
|
||||
printf ("Address length offset %d is not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
return 0; /* sucessful completion */
|
||||
}
|
||||
|
||||
int
|
||||
i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
|
||||
int len)
|
||||
{
|
||||
uchar status = 0;
|
||||
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
|
||||
|
||||
DP (puts ("i2c_read\n"));
|
||||
|
||||
/* set the i2c frequency */
|
||||
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to set slave address & offset: 0x%02x\n",
|
||||
status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
|
||||
status = i2c_select_device (dev_addr, 1, 0);
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to select device for data read: 0x%02x\n",
|
||||
status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
|
||||
status = i2c_get_data (data, len);
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Data not read: 0x%02x\n", status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void i2c_stop (void)
|
||||
{
|
||||
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
|
||||
asm(" sync");
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
|
||||
int len)
|
||||
{
|
||||
uchar status = 0;
|
||||
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
|
||||
|
||||
DP (puts ("i2c_write\n"));
|
||||
|
||||
/* set the i2c frequency */
|
||||
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to set slave address & offset: 0x%02x\n",
|
||||
status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
status = i2c_write_byte (data, len); /* write the data */
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Data not written: 0x%02x\n", status);
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
/* issue a stop bit */
|
||||
i2c_stop ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int i2c_probe (uchar chip)
|
||||
{
|
||||
|
||||
#ifdef DEBUG_I2C
|
||||
unsigned int i2c_status;
|
||||
#endif
|
||||
uchar status = 0;
|
||||
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
|
||||
|
||||
DP (puts ("i2c_probe\n"));
|
||||
|
||||
/* set the i2c frequency */
|
||||
i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
|
||||
if (status) {
|
||||
#ifdef DEBUG_I2C
|
||||
printf ("Failed to set slave address: 0x%02x\n", status);
|
||||
#endif
|
||||
return (int) status;
|
||||
}
|
||||
#ifdef DEBUG_I2C
|
||||
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
|
||||
printf ("address %#x returned %#x\n", chip, i2c_status);
|
||||
#endif
|
||||
/* issue a stop bit */
|
||||
i2c_stop ();
|
||||
return 0; /* successful completion */
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
|
||||
*/
|
||||
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
/* function declarations */
|
||||
uchar i2c_read(uchar, unsigned int, int, uchar*, int);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
/* ide.c - ide support functions */
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_CMD_IDE)
|
||||
#include <ata.h>
|
||||
#include <ide.h>
|
||||
#include <pci.h>
|
||||
|
||||
extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
|
||||
int cpci_hd_type;
|
||||
|
||||
int ata_device(int dev)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = (dev & 1) << 4;
|
||||
if (cpci_hd_type == 2)
|
||||
retval ^= 1 << 4;
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
int ide_preinit (void)
|
||||
{
|
||||
int status;
|
||||
pci_dev_t devbusfn;
|
||||
int l;
|
||||
|
||||
status = 1;
|
||||
cpci_hd_type = 0;
|
||||
if (CPCI750_SLAVE_TEST != 0)
|
||||
return status;
|
||||
for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
|
||||
ide_bus_offset[l] = -ATA_STATUS;
|
||||
}
|
||||
devbusfn = pci_find_device (0x1103, 0x0004, 0);
|
||||
if (devbusfn != -1) {
|
||||
cpci_hd_type = 1;
|
||||
} else {
|
||||
devbusfn = pci_find_device (0x1095, 0x3114, 0);
|
||||
if (devbusfn != -1) {
|
||||
cpci_hd_type = 2;
|
||||
}
|
||||
}
|
||||
if (devbusfn != -1) {
|
||||
ulong *ide_bus_offset_ptr;
|
||||
|
||||
status = 0;
|
||||
|
||||
ide_bus_offset_ptr = &ide_bus_offset[0];
|
||||
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
|
||||
(u32 *)ide_bus_offset_ptr);
|
||||
ide_bus_offset[0] &= 0xfffffffe;
|
||||
ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
|
||||
ide_bus_offset_ptr = &ide_bus_offset[1];
|
||||
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
|
||||
(u32 *)ide_bus_offset_ptr);
|
||||
ide_bus_offset[1] &= 0xfffffffe;
|
||||
ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void ide_set_reset (int flag) {
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* of CONFIG_CMDS_IDE */
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* include/local.h - local configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __LOCAL_H
|
||||
#define __LOCAL_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
/* This tells PPCBoot that the config options are compiled in */
|
||||
/* #undef ENV_IS_EMBEDDED */
|
||||
/* Don't touch this! PPCBOOT figures this out based on other
|
||||
* magic. */
|
||||
|
||||
/* Uncomment and define any of the below options */
|
||||
|
||||
/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
|
||||
#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/
|
||||
|
||||
/* These want string arguments */
|
||||
/* #define CONFIG_BOOTARGS */
|
||||
/* #define CONFIG_BOOTCOMMAND */
|
||||
/* #define CONFIG_RAMBOOTCOMMAND */
|
||||
/* #define CONFIG_NFSBOOTCOMMAND */
|
||||
/* #define CONFIG_SYS_AUTOLOAD */
|
||||
/* #define CONFIG_PREBOOT */
|
||||
|
||||
/* These don't */
|
||||
|
||||
/* #define CONFIG_BOOTDELAY */
|
||||
/* #define CONFIG_BAUDRATE */
|
||||
/* #define CONFIG_LOADS_ECHO */
|
||||
/* #define CONFIG_ETHADDR */
|
||||
/* #define CONFIG_ETH2ADDR */
|
||||
/* #define CONFIG_ETH3ADDR */
|
||||
/* #define CONFIG_IPADDR */
|
||||
/* #define CONFIG_SERVERIP */
|
||||
/* #define CONFIG_ROOTPATH */
|
||||
/* #define CONFIG_GATEWAYIP */
|
||||
/* #define CONFIG_NETMASK */
|
||||
/* #define CONFIG_HOSTNAME */
|
||||
/* #define CONFIG_BOOTFILE */
|
||||
/* #define CONFIG_LOADADDR */
|
||||
|
||||
/* these hardware addresses are pretty bogus, please change them to
|
||||
suit your needs */
|
||||
|
||||
/* first ethernet */
|
||||
/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */
|
||||
#define CONFIG_ETHADDR 64:36:00:00:00:01
|
||||
|
||||
/* next two ethernet hwaddrs */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
#include <config.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "version.h"
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
#ifdef CONFIG_ECC
|
||||
/* Galileo specific asm code for initializing ECC */
|
||||
.globl board_relocate_rom
|
||||
board_relocate_rom:
|
||||
mflr r7
|
||||
/* update the location of the GT registers */
|
||||
lis r11, CONFIG_SYS_GT_REGS@h
|
||||
/* if we're using ECC, we must use the DMA engine to copy ourselves */
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
.globl board_init_ecc
|
||||
board_init_ecc:
|
||||
mflr r7
|
||||
/* NOTE: r10 still contains the location we've been relocated to
|
||||
* which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
|
||||
|
||||
/* now that we're running from ram, init the rest of main memory
|
||||
* for ECC use */
|
||||
lis r8, CONFIG_SYS_MONITOR_LEN@h
|
||||
ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
|
||||
|
||||
divw r3, r10, r8
|
||||
|
||||
/* set up the counter, and init the starting address */
|
||||
mtctr r3
|
||||
li r12, 0
|
||||
|
||||
/* bytes per transfer */
|
||||
mr r5, r8
|
||||
about_to_init_ecc:
|
||||
1: mr r3, r12
|
||||
mr r4, r12
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
add r12, r12, r8
|
||||
bdnz 1b
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
/* r3: dest addr
|
||||
* r4: source addr
|
||||
* r5: byte count
|
||||
* r11: gt regbase
|
||||
* trashes: r6, r5
|
||||
*/
|
||||
start_idma_transfer_0:
|
||||
/* set the byte count, including the OWN bit */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the source address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
|
||||
stwbrx r4, 0, (r6)
|
||||
|
||||
/* set the dest address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
|
||||
stwbrx r3, 0, (r6)
|
||||
|
||||
/* set the next record pointer */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the low control register */
|
||||
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
|
||||
bit 12 is channel enable */
|
||||
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
|
||||
/* 15 shifted by 16 (oris) == bit 31 */
|
||||
oris r5, r5, (1 << 15)
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
|
||||
/* this waits for the bytecount to return to zero, indicating
|
||||
* that the trasfer is complete */
|
||||
wait_for_idma_0:
|
||||
mr r5, r11
|
||||
lis r6, 0xff
|
||||
ori r6, r6, 0xffff
|
||||
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
|
||||
1: lwbrx r4, 0, (r5)
|
||||
and. r4, r4, r6
|
||||
bne 1b
|
||||
|
||||
blr
|
||||
|
||||
/* this turns off channel 0 of the idma engine */
|
||||
stop_idma_engine_0:
|
||||
/* shut off the DMA engine */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_BOARD_ASM_INIT
|
||||
/* NOTE: trashes r3-r7 */
|
||||
.globl board_asm_init
|
||||
board_asm_init:
|
||||
/* just move the GT registers to where they belong */
|
||||
lis r3, CONFIG_SYS_DFL_GT_REGS@h
|
||||
ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
|
||||
lis r4, CONFIG_SYS_GT_REGS@h
|
||||
ori r4, r4, CONFIG_SYS_GT_REGS@l
|
||||
li r5, INTERNAL_SPACE_DECODE
|
||||
|
||||
/* test to see if we've already moved */
|
||||
lwbrx r6, r5, r4
|
||||
andi. r6, r6, 0xffff
|
||||
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
|
||||
/* rlwinm r7, r4, 8, 16, 31
|
||||
rlwinm r7, r4, 12, 16, 31 */ /* original */
|
||||
rlwinm r7, r4, 16, 16, 31
|
||||
/* -----------------------------------------------------*/
|
||||
cmp cr0, r7, r6
|
||||
beqlr
|
||||
|
||||
/* nope, have to move the registers */
|
||||
lwbrx r6, r5, r3
|
||||
andis. r6, r6, 0xffff
|
||||
or r6, r6, r7
|
||||
stwbrx r6, r5, r3
|
||||
|
||||
/* now, poll for the change */
|
||||
1: lwbrx r7, r5, r4
|
||||
cmp cr0, r7, r6
|
||||
bne 1b
|
||||
|
||||
lis r3, CONFIG_SYS_INT_SRAM_BASE@h
|
||||
ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
|
||||
rlwinm r3, r3, 16, 16, 31
|
||||
lis r4, CONFIG_SYS_GT_REGS@h
|
||||
ori r4, r4, CONFIG_SYS_GT_REGS@l
|
||||
li r5, INTEGRATED_SRAM_BASE_ADDR
|
||||
stwbrx r3, r5, r4
|
||||
|
||||
2: lwbrx r6, r5, r4
|
||||
cmp cr0, r3, r6
|
||||
bne 2b
|
||||
|
||||
/* done! */
|
||||
blr
|
||||
#endif
|
||||
|
||||
/* For use of the debug LEDs */
|
||||
.global led_on0_relocated
|
||||
led_on0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0_relocated
|
||||
led_off0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on0
|
||||
led_on0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0
|
||||
led_off0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on1
|
||||
led_on1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off1
|
||||
led_off1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on2
|
||||
led_on2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x0000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off2
|
||||
led_off2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
1018
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mpsc.c
Normal file
1018
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mpsc.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* mpsc.h - header file for MPSC in uart mode (console driver)
|
||||
*/
|
||||
|
||||
#ifndef __MPSC_H__
|
||||
#define __MPSC_H__
|
||||
|
||||
/* include actual Galileo defines */
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
/* driver related defines */
|
||||
|
||||
int mpsc_init(int baud);
|
||||
void mpsc_sdma_init(void);
|
||||
void mpsc_init2(void);
|
||||
int galbrg_set_baudrate(int channel, int rate);
|
||||
|
||||
int mpsc_putchar_early(char ch);
|
||||
char mpsc_getchar_debug(void);
|
||||
int mpsc_test_char_debug(void);
|
||||
|
||||
int mpsc_test_char_sdma(void);
|
||||
|
||||
extern int (*mpsc_putchar)(char ch);
|
||||
extern char (*mpsc_getchar)(void);
|
||||
extern int (*mpsc_test_char)(void);
|
||||
|
||||
#define CHANNEL CONFIG_MPSC_PORT
|
||||
|
||||
#define TX_DESC 5
|
||||
#define RX_DESC 20
|
||||
|
||||
#define DESC_FIRST 0x00010000
|
||||
#define DESC_LAST 0x00020000
|
||||
#define DESC_OWNER_BIT 0x80000000
|
||||
|
||||
#define TX_DEMAND 0x00800000
|
||||
#define TX_STOP 0x00010000
|
||||
#define RX_ENABLE 0x00000080
|
||||
|
||||
#define SDMA_RX_ABORT (1 << 15)
|
||||
#define SDMA_TX_ABORT (1 << 31)
|
||||
#define MPSC_TX_ABORT (1 << 7)
|
||||
#define MPSC_RX_ABORT (1 << 23)
|
||||
#define MPSC_ENTER_HUNT (1 << 31)
|
||||
|
||||
/* MPSC defines */
|
||||
|
||||
#define GALMPSC_CONNECT 0x1
|
||||
#define GALMPSC_DISCONNECT 0x0
|
||||
|
||||
#define GALMPSC_UART 0x1
|
||||
|
||||
#define GALMPSC_STOP_BITS_1 0x0
|
||||
#define GALMPSC_STOP_BITS_2 0x1
|
||||
#define GALMPSC_CHAR_LENGTH_8 0x3
|
||||
#define GALMPSC_CHAR_LENGTH_7 0x2
|
||||
|
||||
#define GALMPSC_PARITY_ODD 0x0
|
||||
#define GALMPSC_PARITY_EVEN 0x2
|
||||
#define GALMPSC_PARITY_MARK 0x3
|
||||
#define GALMPSC_PARITY_SPACE 0x1
|
||||
#define GALMPSC_PARITY_NONE -1
|
||||
|
||||
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
|
||||
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
|
||||
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
|
||||
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
|
||||
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
|
||||
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
|
||||
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
|
||||
|
||||
#define GALMPSC_REG_GAP 0x1000
|
||||
|
||||
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
|
||||
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
|
||||
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
|
||||
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
|
||||
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
|
||||
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
|
||||
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
|
||||
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
|
||||
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
|
||||
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
|
||||
|
||||
#define GALSDMA_COMMAND_FIRST (1 << 16)
|
||||
#define GALSDMA_COMMAND_LAST (1 << 17)
|
||||
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
|
||||
#define GALSDMA_COMMAND_AUTO (1 << 30)
|
||||
#define GALSDMA_COMMAND_OWNER (1 << 31)
|
||||
|
||||
#define GALSDMA_RX 0
|
||||
#define GALSDMA_TX 1
|
||||
|
||||
/* CHANNEL2 should be CHANNEL1, according to documentation,
|
||||
* but to work with the current GTREGS file...
|
||||
*/
|
||||
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
|
||||
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
|
||||
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
|
||||
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
|
||||
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
|
||||
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
|
||||
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
|
||||
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
|
||||
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
|
||||
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
|
||||
#define GALSDMA_REG_DIFF 0x2000
|
||||
|
||||
/* WRONG in gt64260R.h */
|
||||
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
|
||||
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
|
||||
#define GALMPSC_0_INT_CAUSE 0xb804
|
||||
#define GALMPSC_0_INT_MASK 0xb884
|
||||
|
||||
#define GALSDMA_MODE_UART 0
|
||||
#define GALSDMA_MODE_BISYNC 1
|
||||
#define GALSDMA_MODE_HDLC 2
|
||||
#define GALSDMA_MODE_TRANSPARENT 3
|
||||
|
||||
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
|
||||
#define GALBRG_REG_GAP 0x0008
|
||||
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
|
||||
|
||||
#endif /* __MPSC_H__ */
|
||||
3162
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mv_eth.c
Normal file
3162
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mv_eth.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,842 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* based on - Driver for MV64360X ethernet ports
|
||||
* Copyright (C) 2002 rabeeh@galileo.co.il
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* mv_eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __DB64360_ETH_H__
|
||||
#define __DB64360_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include "mv_regs.h"
|
||||
#include <asm/errno.h>
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The first part is the high level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
|
||||
#ifndef MAX_SKB_FRAGS
|
||||
#define MAX_SKB_FRAGS 0
|
||||
#endif
|
||||
|
||||
/* Port attributes */
|
||||
/*#define MAX_RX_QUEUE_NUM 8*/
|
||||
/*#define MAX_TX_QUEUE_NUM 8*/
|
||||
#define MAX_RX_QUEUE_NUM 1
|
||||
#define MAX_TX_QUEUE_NUM 1
|
||||
|
||||
|
||||
/* Use one TX queue and one RX queue */
|
||||
#define MV64360_TX_QUEUE_NUM 1
|
||||
#define MV64360_RX_QUEUE_NUM 1
|
||||
|
||||
/*
|
||||
* Number of RX / TX descriptors on RX / TX rings.
|
||||
* Note that allocating RX descriptors is done by allocating the RX
|
||||
* ring AND a preallocated RX buffers (skb's) for each descriptor.
|
||||
* The TX descriptors only allocates the TX descriptors ring,
|
||||
* with no pre allocated TX buffers (skb's are allocated by higher layers.
|
||||
*/
|
||||
|
||||
/* Default TX ring size is 10 descriptors */
|
||||
#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
|
||||
#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64360_TX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
/* Default RX ring size is 4 descriptors */
|
||||
#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
|
||||
#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64360_RX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RX_BUFFER_SIZE
|
||||
#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64360_RX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TX_BUFFER_SIZE
|
||||
#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64360_TX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Network device statistics. Akin to the 2.0 ether stats but
|
||||
* with byte counters.
|
||||
*/
|
||||
|
||||
struct net_device_stats
|
||||
{
|
||||
unsigned long rx_packets; /* total packets received */
|
||||
unsigned long tx_packets; /* total packets transmitted */
|
||||
unsigned long rx_bytes; /* total bytes received */
|
||||
unsigned long tx_bytes; /* total bytes transmitted */
|
||||
unsigned long rx_errors; /* bad packets received */
|
||||
unsigned long tx_errors; /* packet transmit problems */
|
||||
unsigned long rx_dropped; /* no space in linux buffers */
|
||||
unsigned long tx_dropped; /* no space available in linux */
|
||||
unsigned long multicast; /* multicast packets received */
|
||||
unsigned long collisions;
|
||||
|
||||
/* detailed rx_errors: */
|
||||
unsigned long rx_length_errors;
|
||||
unsigned long rx_over_errors; /* receiver ring buff overflow */
|
||||
unsigned long rx_crc_errors; /* recved pkt with crc error */
|
||||
unsigned long rx_frame_errors; /* recv'd frame alignment error */
|
||||
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
|
||||
unsigned long rx_missed_errors; /* receiver missed packet */
|
||||
|
||||
/* detailed tx_errors */
|
||||
unsigned long tx_aborted_errors;
|
||||
unsigned long tx_carrier_errors;
|
||||
unsigned long tx_fifo_errors;
|
||||
unsigned long tx_heartbeat_errors;
|
||||
unsigned long tx_window_errors;
|
||||
|
||||
/* for cslip etc */
|
||||
unsigned long rx_compressed;
|
||||
unsigned long tx_compressed;
|
||||
};
|
||||
|
||||
|
||||
/* Private data structure used for ethernet device */
|
||||
struct mv64360_eth_priv {
|
||||
unsigned int port_num;
|
||||
struct net_device_stats *stats;
|
||||
|
||||
/* to buffer area aligned */
|
||||
char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
|
||||
char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
|
||||
|
||||
/* Size of Tx Ring per queue */
|
||||
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
|
||||
|
||||
|
||||
/* Size of Rx Ring per queue */
|
||||
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Magic Number for Ethernet running */
|
||||
unsigned int eth_running;
|
||||
|
||||
};
|
||||
|
||||
|
||||
int mv64360_eth_init (struct eth_device *dev);
|
||||
int mv64360_eth_stop (struct eth_device *dev);
|
||||
int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
|
||||
int mv64360_eth_open (struct eth_device *dev);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The second part is the low level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
* Header File for : MV-643xx network interface header
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This header file contains macros typedefs and function declaration for
|
||||
* the Marvell Gig Bit Ethernet Controller.
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
|
||||
#ifdef CONFIG_MV64360_SRAM_CACHEABLE
|
||||
/* In case SRAM is cacheable but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case SRAM is cache coherent or non-cacheable */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif
|
||||
#else
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
/* In case of descriptors on DDR but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case of descriptors on DDR and cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif /* CONFIG_NOT_COHERENT_CACHE */
|
||||
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
|
||||
|
||||
|
||||
#define CPU_PIPE_FLUSH \
|
||||
{ \
|
||||
__asm__ __volatile__ ("eieio"); \
|
||||
}
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
/* Default port configuration value */
|
||||
#define PORT_CONFIG_VALUE \
|
||||
ETH_UNICAST_NORMAL_MODE | \
|
||||
ETH_DEFAULT_RX_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
|
||||
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
|
||||
ETH_RECEIVE_BC_IF_IP | \
|
||||
ETH_RECEIVE_BC_IF_ARP | \
|
||||
ETH_CAPTURE_TCP_FRAMES_DIS | \
|
||||
ETH_CAPTURE_UDP_FRAMES_DIS | \
|
||||
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_BPDU_QUEUE_0
|
||||
|
||||
/* Default port extend configuration value */
|
||||
#define PORT_CONFIG_EXTEND_VALUE \
|
||||
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
|
||||
ETH_PARTITION_DISABLE
|
||||
|
||||
|
||||
/* Default sdma control value */
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_16_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_16_64BIT;
|
||||
#else
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_4_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_4_64BIT;
|
||||
#endif
|
||||
|
||||
#define GT_ETH_IPG_INT_RX(value) \
|
||||
((value & 0x3fff) << 8)
|
||||
|
||||
/* Default port serial control value */
|
||||
#define PORT_SERIAL_CONTROL_VALUE \
|
||||
ETH_FORCE_LINK_PASS | \
|
||||
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
|
||||
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
|
||||
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
|
||||
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
|
||||
ETH_FORCE_BP_MODE_NO_JAM | \
|
||||
BIT9 | \
|
||||
ETH_DO_NOT_FORCE_LINK_FAIL | \
|
||||
ETH_RETRANSMIT_16_ETTEMPTS | \
|
||||
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
|
||||
ETH_DTE_ADV_0 | \
|
||||
ETH_DISABLE_AUTO_NEG_BYPASS | \
|
||||
ETH_AUTO_NEG_NO_CHANGE | \
|
||||
ETH_MAX_RX_PACKET_1552BYTE | \
|
||||
ETH_CLR_EXT_LOOPBACK | \
|
||||
ETH_SET_FULL_DUPLEX_MODE | \
|
||||
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
|
||||
|
||||
#define RX_BUFFER_MAX_SIZE 0xFFFF
|
||||
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
|
||||
|
||||
#define RX_BUFFER_MIN_SIZE 0x8
|
||||
#define TX_BUFFER_MIN_SIZE 0x8
|
||||
|
||||
/* Tx WRR confoguration macros */
|
||||
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
|
||||
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
|
||||
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
|
||||
|
||||
/* MAC accepet/reject macros */
|
||||
#define ACCEPT_MAC_ADDR 0
|
||||
#define REJECT_MAC_ADDR 1
|
||||
|
||||
/* Size of a Tx/Rx descriptor used in chain list data structure */
|
||||
#define RX_DESC_ALIGNED_SIZE 0x20
|
||||
#define TX_DESC_ALIGNED_SIZE 0x20
|
||||
|
||||
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
|
||||
#define TX_BUF_OFFSET_IN_DESC 0x18
|
||||
/* Buffer offset from buffer pointer */
|
||||
#define RX_BUF_OFFSET 0x2
|
||||
|
||||
/* Gap define */
|
||||
#define ETH_BAR_GAP 0x8
|
||||
#define ETH_SIZE_REG_GAP 0x8
|
||||
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
|
||||
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
|
||||
|
||||
/* Gigabit Ethernet Unit Global Registers */
|
||||
|
||||
/* MIB Counters register definitions */
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
|
||||
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
|
||||
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
|
||||
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
|
||||
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
|
||||
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
|
||||
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
|
||||
#define ETH_MIB_FRAMES_64_OCTETS 0x20
|
||||
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
|
||||
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
|
||||
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
|
||||
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
|
||||
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
|
||||
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
|
||||
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
|
||||
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
|
||||
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
|
||||
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
|
||||
#define ETH_MIB_FC_SENT 0x54
|
||||
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
|
||||
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
|
||||
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
|
||||
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
|
||||
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
|
||||
#define ETH_MIB_JABBER_RECEIVED 0x6c
|
||||
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
|
||||
#define ETH_MIB_BAD_CRC_EVENT 0x74
|
||||
#define ETH_MIB_COLLISION 0x78
|
||||
#define ETH_MIB_LATE_COLLISION 0x7c
|
||||
|
||||
/* Port serial status reg (PSR) */
|
||||
#define ETH_INTERFACE_GMII_MII 0
|
||||
#define ETH_INTERFACE_PCM BIT0
|
||||
#define ETH_LINK_IS_DOWN 0
|
||||
#define ETH_LINK_IS_UP BIT1
|
||||
#define ETH_PORT_AT_HALF_DUPLEX 0
|
||||
#define ETH_PORT_AT_FULL_DUPLEX BIT2
|
||||
#define ETH_RX_FLOW_CTRL_DISABLED 0
|
||||
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
|
||||
#define ETH_GMII_SPEED_100_10 0
|
||||
#define ETH_GMII_SPEED_1000 BIT4
|
||||
#define ETH_MII_SPEED_10 0
|
||||
#define ETH_MII_SPEED_100 BIT5
|
||||
#define ETH_NO_TX 0
|
||||
#define ETH_TX_IN_PROGRESS BIT7
|
||||
#define ETH_BYPASS_NO_ACTIVE 0
|
||||
#define ETH_BYPASS_ACTIVE BIT8
|
||||
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
|
||||
#define ETH_PORT_AT_PARTITION_STATE BIT9
|
||||
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
|
||||
#define ETH_PORT_TX_FIFO_EMPTY BIT10
|
||||
|
||||
|
||||
/* These macros describes the Port configuration reg (Px_cR) bits */
|
||||
#define ETH_UNICAST_NORMAL_MODE 0
|
||||
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
|
||||
#define ETH_DEFAULT_RX_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
|
||||
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
|
||||
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
|
||||
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
|
||||
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
|
||||
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
|
||||
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
|
||||
#define ETH_RECEIVE_BC_IF_IP 0
|
||||
#define ETH_REJECT_BC_IF_IP BIT8
|
||||
#define ETH_RECEIVE_BC_IF_ARP 0
|
||||
#define ETH_REJECT_BC_IF_ARP BIT9
|
||||
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
|
||||
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
|
||||
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
|
||||
|
||||
|
||||
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
|
||||
#define ETH_CLASSIFY_EN BIT0
|
||||
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
|
||||
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
|
||||
#define ETH_PARTITION_DISABLE 0
|
||||
#define ETH_PARTITION_ENABLE BIT2
|
||||
|
||||
|
||||
/* Tx/Rx queue command reg (RQCR/TQCR)*/
|
||||
#define ETH_QUEUE_0_ENABLE BIT0
|
||||
#define ETH_QUEUE_1_ENABLE BIT1
|
||||
#define ETH_QUEUE_2_ENABLE BIT2
|
||||
#define ETH_QUEUE_3_ENABLE BIT3
|
||||
#define ETH_QUEUE_4_ENABLE BIT4
|
||||
#define ETH_QUEUE_5_ENABLE BIT5
|
||||
#define ETH_QUEUE_6_ENABLE BIT6
|
||||
#define ETH_QUEUE_7_ENABLE BIT7
|
||||
#define ETH_QUEUE_0_DISABLE BIT8
|
||||
#define ETH_QUEUE_1_DISABLE BIT9
|
||||
#define ETH_QUEUE_2_DISABLE BIT10
|
||||
#define ETH_QUEUE_3_DISABLE BIT11
|
||||
#define ETH_QUEUE_4_DISABLE BIT12
|
||||
#define ETH_QUEUE_5_DISABLE BIT13
|
||||
#define ETH_QUEUE_6_DISABLE BIT14
|
||||
#define ETH_QUEUE_7_DISABLE BIT15
|
||||
|
||||
|
||||
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
|
||||
#define ETH_RIFB BIT0
|
||||
#define ETH_RX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
|
||||
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
|
||||
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
|
||||
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
|
||||
#define ETH_BLM_RX_NO_SWAP BIT4
|
||||
#define ETH_BLM_RX_BYTE_SWAP 0
|
||||
#define ETH_BLM_TX_NO_SWAP BIT5
|
||||
#define ETH_BLM_TX_BYTE_SWAP 0
|
||||
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
|
||||
#define ETH_DESCRIPTORS_NO_SWAP 0
|
||||
#define ETH_TX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
|
||||
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
|
||||
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
|
||||
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
|
||||
|
||||
|
||||
/* These macros describes the Port serial control reg (PSCR) bits */
|
||||
#define ETH_SERIAL_PORT_DISABLE 0
|
||||
#define ETH_SERIAL_PORT_ENABLE BIT0
|
||||
#define ETH_FORCE_LINK_PASS BIT1
|
||||
#define ETH_DO_NOT_FORCE_LINK_PASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
|
||||
#define ETH_ADV_NO_FLOW_CTRL 0
|
||||
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
|
||||
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
|
||||
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
|
||||
#define ETH_FORCE_BP_MODE_NO_JAM 0
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
|
||||
#define ETH_FORCE_LINK_FAIL 0
|
||||
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
|
||||
#define ETH_RETRANSMIT_16_ETTEMPTS 0
|
||||
#define ETH_RETRANSMIT_FOREVER BIT11
|
||||
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
|
||||
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
|
||||
#define ETH_DTE_ADV_0 0
|
||||
#define ETH_DTE_ADV_1 BIT14
|
||||
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
|
||||
#define ETH_AUTO_NEG_NO_CHANGE 0
|
||||
#define ETH_RESTART_AUTO_NEG BIT16
|
||||
#define ETH_MAX_RX_PACKET_1518BYTE 0
|
||||
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
|
||||
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
|
||||
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
|
||||
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
|
||||
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
|
||||
#define ETH_SET_EXT_LOOPBACK BIT20
|
||||
#define ETH_CLR_EXT_LOOPBACK 0
|
||||
#define ETH_SET_FULL_DUPLEX_MODE BIT21
|
||||
#define ETH_SET_HALF_DUPLEX_MODE 0
|
||||
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
|
||||
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
|
||||
#define ETH_SET_GMII_SPEED_TO_10_100 0
|
||||
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
|
||||
#define ETH_SET_MII_SPEED_TO_10 0
|
||||
#define ETH_SET_MII_SPEED_TO_100 BIT24
|
||||
|
||||
|
||||
/* SMI reg */
|
||||
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
|
||||
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
|
||||
|
||||
/* SDMA command status fields macros */
|
||||
|
||||
/* Tx & Rx descriptors status */
|
||||
#define ETH_ERROR_SUMMARY (BIT0)
|
||||
|
||||
/* Tx & Rx descriptors command */
|
||||
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
|
||||
|
||||
/* Tx descriptors status */
|
||||
#define ETH_LC_ERROR (0 )
|
||||
#define ETH_UR_ERROR (BIT1 )
|
||||
#define ETH_RL_ERROR (BIT2 )
|
||||
#define ETH_LLC_SNAP_FORMAT (BIT9 )
|
||||
|
||||
/* Rx descriptors status */
|
||||
#define ETH_CRC_ERROR (0 )
|
||||
#define ETH_OVERRUN_ERROR (BIT1 )
|
||||
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
|
||||
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
|
||||
#define ETH_VLAN_TAGGED (BIT19)
|
||||
#define ETH_BPDU_FRAME (BIT20)
|
||||
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
|
||||
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
|
||||
#define ETH_OTHER_FRAME_TYPE (BIT22)
|
||||
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
|
||||
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
|
||||
#define ETH_FRAME_HEADER_OK (BIT25)
|
||||
#define ETH_RX_LAST_DESC (BIT26)
|
||||
#define ETH_RX_FIRST_DESC (BIT27)
|
||||
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
|
||||
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
|
||||
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
|
||||
|
||||
/* Rx descriptors byte count */
|
||||
#define ETH_FRAME_FRAGMENTED (BIT2)
|
||||
|
||||
/* Tx descriptors command */
|
||||
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
|
||||
#define ETH_FRAME_SET_TO_VLAN (BIT15)
|
||||
#define ETH_TCP_FRAME (0 )
|
||||
#define ETH_UDP_FRAME (BIT16)
|
||||
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
|
||||
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
|
||||
#define ETH_ZERO_PADDING (BIT19)
|
||||
#define ETH_TX_LAST_DESC (BIT20)
|
||||
#define ETH_TX_FIRST_DESC (BIT21)
|
||||
#define ETH_GEN_CRC (BIT22)
|
||||
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
|
||||
#define ETH_AUTO_MODE (BIT30)
|
||||
|
||||
/* Address decode parameters */
|
||||
/* Ethernet Base Address Register bits */
|
||||
#define EBAR_TARGET_DRAM 0x00000000
|
||||
#define EBAR_TARGET_DEVICE 0x00000001
|
||||
#define EBAR_TARGET_CBS 0x00000002
|
||||
#define EBAR_TARGET_PCI0 0x00000003
|
||||
#define EBAR_TARGET_PCI1 0x00000004
|
||||
#define EBAR_TARGET_CUNIT 0x00000005
|
||||
#define EBAR_TARGET_AUNIT 0x00000006
|
||||
#define EBAR_TARGET_GUNIT 0x00000007
|
||||
|
||||
/* Window attributes */
|
||||
#define EBAR_ATTR_DRAM_CS0 0x00000E00
|
||||
#define EBAR_ATTR_DRAM_CS1 0x00000D00
|
||||
#define EBAR_ATTR_DRAM_CS2 0x00000B00
|
||||
#define EBAR_ATTR_DRAM_CS3 0x00000700
|
||||
|
||||
/* DRAM Target interface */
|
||||
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
|
||||
|
||||
/* Device Bus Target interface */
|
||||
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
|
||||
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
|
||||
|
||||
/* PCI Target interface */
|
||||
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
|
||||
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
|
||||
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
|
||||
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
|
||||
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
|
||||
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
|
||||
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
|
||||
|
||||
/* CPU 60x bus or internal SRAM interface */
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
|
||||
#define EBAR_ATTR_CBS_SRAM 0x00000000
|
||||
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
|
||||
|
||||
/* Window access control */
|
||||
#define EWIN_ACCESS_NOT_ALLOWED 0
|
||||
#define EWIN_ACCESS_READ_ONLY BIT0
|
||||
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
|
||||
#define EWIN0_ACCESS_MASK 0x0003
|
||||
#define EWIN1_ACCESS_MASK 0x000C
|
||||
#define EWIN2_ACCESS_MASK 0x0030
|
||||
#define EWIN3_ACCESS_MASK 0x00C0
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef enum _eth_port
|
||||
{
|
||||
ETH_0 = 0,
|
||||
ETH_1 = 1,
|
||||
ETH_2 = 2
|
||||
}ETH_PORT;
|
||||
|
||||
typedef enum _eth_func_ret_status
|
||||
{
|
||||
ETH_OK, /* Returned as expected. */
|
||||
ETH_ERROR, /* Fundamental error. */
|
||||
ETH_RETRY, /* Could not process request. Try later. */
|
||||
ETH_END_OF_JOB, /* Ring has nothing to process. */
|
||||
ETH_QUEUE_FULL, /* Ring resource error. */
|
||||
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
|
||||
}ETH_FUNC_RET_STATUS;
|
||||
|
||||
typedef enum _eth_queue
|
||||
{
|
||||
ETH_Q0 = 0,
|
||||
ETH_Q1 = 1,
|
||||
ETH_Q2 = 2,
|
||||
ETH_Q3 = 3,
|
||||
ETH_Q4 = 4,
|
||||
ETH_Q5 = 5,
|
||||
ETH_Q6 = 6,
|
||||
ETH_Q7 = 7
|
||||
} ETH_QUEUE;
|
||||
|
||||
typedef enum _addr_win
|
||||
{
|
||||
ETH_WIN0,
|
||||
ETH_WIN1,
|
||||
ETH_WIN2,
|
||||
ETH_WIN3,
|
||||
ETH_WIN4,
|
||||
ETH_WIN5
|
||||
} ETH_ADDR_WIN;
|
||||
|
||||
typedef enum _eth_target
|
||||
{
|
||||
ETH_TARGET_DRAM ,
|
||||
ETH_TARGET_DEVICE,
|
||||
ETH_TARGET_CBS ,
|
||||
ETH_TARGET_PCI0 ,
|
||||
ETH_TARGET_PCI1
|
||||
}ETH_TARGET;
|
||||
|
||||
typedef struct _eth_rx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short buf_size ; /* Buffer size */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_RX_DESC;
|
||||
|
||||
|
||||
typedef struct _eth_tx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_TX_DESC;
|
||||
|
||||
/* Unified struct for Rx and Tx operations. The user is not required to */
|
||||
/* be familier with neither Tx nor Rx descriptors. */
|
||||
typedef struct _pkt_info
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} PKT_INFO;
|
||||
|
||||
|
||||
typedef struct _eth_win_param
|
||||
{
|
||||
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
|
||||
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
|
||||
unsigned short attributes; /* BAR attributes. See above macros. */
|
||||
unsigned int base_addr; /* Window base address in unsigned int form */
|
||||
unsigned int high_addr; /* Window high address in unsigned int form */
|
||||
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
|
||||
bool enable; /* Enable/disable access to the window. */
|
||||
unsigned short access_ctrl; /* Access ctrl register. see above macros */
|
||||
} ETH_WIN_PARAM;
|
||||
|
||||
|
||||
/* Ethernet port specific infomation */
|
||||
|
||||
typedef struct _eth_port_ctrl
|
||||
{
|
||||
ETH_PORT port_num; /* User Ethernet port number */
|
||||
int port_phy_addr; /* User phy address of Ethrnet port */
|
||||
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
|
||||
unsigned int port_config; /* User port configuration value */
|
||||
unsigned int port_config_extend; /* User port config extend value */
|
||||
unsigned int port_sdma_config; /* User port SDMA config value */
|
||||
unsigned int port_serial_control; /* User port serial control value */
|
||||
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
|
||||
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
|
||||
|
||||
/* User function to cast virtual address to CPU bus address */
|
||||
unsigned int (*port_virt_to_phys)(unsigned int addr);
|
||||
/* User scratch pad for user specific data structures */
|
||||
void *port_private;
|
||||
|
||||
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
|
||||
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
|
||||
|
||||
/* Tx/Rx rings managment indexes fields. For driver use */
|
||||
|
||||
/* Next available Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
|
||||
/* Returning Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Next available Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* Returning Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* An extra Tx index to support transmit of multiple buffers per packet */
|
||||
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
|
||||
|
||||
/* Tx/Rx rings size and base variables fields. For driver use */
|
||||
|
||||
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
|
||||
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
|
||||
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
|
||||
|
||||
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
|
||||
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
|
||||
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
|
||||
|
||||
} ETH_PORT_INFO;
|
||||
|
||||
|
||||
/* ethernet.h API list */
|
||||
|
||||
/* Port operation control routines */
|
||||
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
static void eth_port_reset(ETH_PORT eth_port_num);
|
||||
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
|
||||
|
||||
/* Port MAC address routines */
|
||||
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue);
|
||||
#if 0 /* FIXME */
|
||||
static void eth_port_mc_addr (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue,
|
||||
int option);
|
||||
#endif
|
||||
|
||||
/* PHY and MIB routines */
|
||||
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
|
||||
|
||||
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int value);
|
||||
|
||||
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int* value);
|
||||
|
||||
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
|
||||
|
||||
/* Port data flow control routines */
|
||||
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
|
||||
|
||||
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
int tx_desc_num,
|
||||
int tx_buff_size,
|
||||
unsigned int tx_desc_base_addr,
|
||||
unsigned int tx_buff_base_addr);
|
||||
|
||||
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
int rx_desc_num,
|
||||
int rx_buff_size,
|
||||
unsigned int rx_desc_base_addr,
|
||||
unsigned int rx_buff_base_addr);
|
||||
|
||||
#endif /* MV64360_ETH_ */
|
||||
1124
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mv_regs.h
Normal file
1124
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/mv_regs.h
Normal file
File diff suppressed because it is too large
Load diff
1045
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/pci.c
Normal file
1045
root/package/utils/sysupgrade-helper/src/board/esd/cpci750/pci.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* modified for cpci750 board by
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* serial.c - serial support for esd cpci750 board
|
||||
*/
|
||||
|
||||
/* supports the MPSC */
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "serial.h"
|
||||
|
||||
#include "mpsc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int serial_init (void)
|
||||
{
|
||||
mpsc_init (gd->baudrate);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
mpsc_putchar ('\r');
|
||||
|
||||
mpsc_putchar (c);
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
return mpsc_getchar ();
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
return mpsc_test_char ();
|
||||
}
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
|
||||
}
|
||||
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
void kgdb_serial_init (void)
|
||||
{
|
||||
}
|
||||
|
||||
void putDebugChar (int c)
|
||||
{
|
||||
serial_putc (c);
|
||||
}
|
||||
|
||||
void putDebugStr (const char *str)
|
||||
{
|
||||
serial_puts (str);
|
||||
}
|
||||
|
||||
int getDebugChar (void)
|
||||
{
|
||||
return serial_getc ();
|
||||
}
|
||||
|
||||
void kgdb_interruptible (int yes)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* serial.h - mostly useful for DUART serial_init in serial.c */
|
||||
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#if 0
|
||||
|
||||
#define B230400 1
|
||||
#define B115200 2
|
||||
#define B57600 4
|
||||
#define B38400 82
|
||||
#define B19200 163
|
||||
#define B9600 24
|
||||
#define B4800 651
|
||||
#define B2400 1302
|
||||
#define B1200 2604
|
||||
#define B600 5208
|
||||
#define B300 10417
|
||||
#define B150 20833
|
||||
#define B110 28409
|
||||
#define BDEFAULT B115200
|
||||
|
||||
/* this stuff is important to initialize
|
||||
the DUART channels */
|
||||
|
||||
#define Scale 0x01L /* distance between port addresses */
|
||||
#define COM1 0x000003f8 /* Keyboard */
|
||||
#define COM2 0x000002f8 /* Host */
|
||||
|
||||
|
||||
/* Port Definitions relative to base COM port addresses */
|
||||
#define DataIn (0x00*Scale) /* data input port */
|
||||
#define DataOut (0x00*Scale) /* data output port */
|
||||
#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
|
||||
#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
|
||||
#define Ier (0x01*Scale) /* interrupt enable register */
|
||||
#define Iir (0x02*Scale) /* interrupt identification register */
|
||||
#define Lcr (0x03*Scale) /* line control register */
|
||||
#define Mcr (0x04*Scale) /* modem control register */
|
||||
#define Lsr (0x05*Scale) /* line status register */
|
||||
#define Msr (0x06*Scale) /* modem status register */
|
||||
|
||||
/* Bit Definitions for above ports */
|
||||
#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
|
||||
#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
|
||||
|
||||
#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
|
||||
#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
|
||||
#define McrDflt (McrRts|McrDtr)
|
||||
|
||||
#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
|
||||
/* b6: transmitter empty */
|
||||
#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
|
||||
|
||||
#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
|
||||
#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
|
||||
#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
|
||||
|
||||
#define IerRda 0xf /* b0: Enable received data available interrupt */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_H__ */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "cpciiser4.h"
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG2
|
||||
#endif
|
||||
|
||||
/* fpga configuration data - generated by bin2cc */
|
||||
const unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
int index, len, i;
|
||||
int status;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
|
||||
if (status != 0) {
|
||||
/* booting FPGA failed */
|
||||
#ifndef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
printf ("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf ("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf ("Rebooting in %2d seconds \r", i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay (1000);
|
||||
}
|
||||
putc ('\n');
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Init FPGA via RESET (read access on CS3)
|
||||
*/
|
||||
in_8((void *)0xf0200000);
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
|
||||
/* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
|
||||
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
|
||||
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming AR405");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
/* printf("PB1CR = %x\n", pbcr); */
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-monitor_flash_len,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,48 @@
|
|||
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define OK 0
|
||||
#define ERROR (-1)
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
|
||||
extern u_long pci9054_iobase;
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
*
|
||||
* Routines for PLX PCI9054 eeprom access
|
||||
*
|
||||
*/
|
||||
|
||||
static unsigned int PciEepromReadLongVPD (int offs)
|
||||
{
|
||||
unsigned int value;
|
||||
unsigned int ret;
|
||||
int count;
|
||||
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
|
||||
(offs << 16) | 0x0003);
|
||||
count = 0;
|
||||
|
||||
for (;;) {
|
||||
udelay (10 * 1000);
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
|
||||
if ((ret & 0x80000000) != 0) {
|
||||
break;
|
||||
} else {
|
||||
count++;
|
||||
if (count > 10) {
|
||||
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
static int PciEepromWriteLongVPD (int offs, unsigned int value)
|
||||
{
|
||||
unsigned int ret;
|
||||
int count;
|
||||
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
|
||||
(offs << 16) | 0x80000003);
|
||||
count = 0;
|
||||
|
||||
for (;;) {
|
||||
udelay (10 * 1000);
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
|
||||
if ((ret & 0x80000000) == 0) {
|
||||
break;
|
||||
} else {
|
||||
count++;
|
||||
if (count > 10) {
|
||||
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
static void showPci9054 (void)
|
||||
{
|
||||
int val;
|
||||
int l, i;
|
||||
|
||||
/* read 9054-values */
|
||||
for (l = 0; l < 6; l++) {
|
||||
printf ("%02x: ", l * 0x10);
|
||||
for (i = 0; i < 4; i++) {
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
|
||||
l * 16 + i * 4,
|
||||
(unsigned int *)&val);
|
||||
printf ("%08x ", val);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
for (l = 0; l < 7; l++) {
|
||||
printf ("%02x: ", l * 0x10);
|
||||
for (i = 0; i < 4; i++)
|
||||
printf ("%08x ",
|
||||
PciEepromReadLongVPD ((i + l * 4) * 4));
|
||||
printf ("\n");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
static void updatePci9054 (void)
|
||||
{
|
||||
/*
|
||||
* Set EEPROM write-protect register to 0
|
||||
*/
|
||||
out_be32 ((void *)(pci9054_iobase + 0x0c),
|
||||
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
|
||||
|
||||
/* Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x00, 0x905410b5);
|
||||
PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
|
||||
PciEepromWriteLongVPD (0x08, 0x28140100);
|
||||
|
||||
PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
|
||||
PciEepromWriteLongVPD (0x10, 0x00000000);
|
||||
|
||||
/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
|
||||
PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
|
||||
PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
|
||||
|
||||
PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
|
||||
PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
|
||||
|
||||
PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
|
||||
PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
|
||||
|
||||
PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
|
||||
|
||||
PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
|
||||
PciEepromWriteLongVPD (0x34, 0x00000000);
|
||||
PciEepromWriteLongVPD (0x38, 0x00000000);
|
||||
|
||||
PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
|
||||
PciEepromWriteLongVPD (0x40, 0x00000000);
|
||||
|
||||
/* Extra Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
|
||||
|
||||
/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
|
||||
/* Offset to LAS1: Group 1: 0x00040000 */
|
||||
/* Group 2: 0x00080000 */
|
||||
/* Group 3: 0x000c0000 */
|
||||
PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
|
||||
PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
|
||||
PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
|
||||
|
||||
PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
|
||||
|
||||
printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
|
||||
}
|
||||
|
||||
|
||||
static void clearPci9054 (void)
|
||||
{
|
||||
/*
|
||||
* Set EEPROM write-protect register to 0
|
||||
*/
|
||||
out_be32 ((void *)(pci9054_iobase + 0x0c),
|
||||
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
|
||||
|
||||
/* Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x00, 0xffffffff);
|
||||
PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
|
||||
|
||||
printf ("Finished clearing PLX PCI9054 EEPROM!\n");
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
if (strcmp (argv[1], "info") == 0) {
|
||||
showPci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (strcmp (argv[1], "update") == 0) {
|
||||
updatePci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (strcmp (argv[1], "clear") == 0) {
|
||||
clearPci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pci9054, 3, 1, do_pci9054,
|
||||
"PLX PCI9054 EEPROM access",
|
||||
"pci9054 info - print EEPROM values\n"
|
||||
"pci9054 update - updates EEPROM with default values"
|
||||
);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include "dasa_sim.h"
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#undef FPGA_DEBUG
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* fpga configuration data - generated by bit2inc */
|
||||
static unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
|
||||
#define LOAD_LONG(a) a
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* sysFpgaBoot - Load fpga-image into fpga
|
||||
*
|
||||
*/
|
||||
static int fpgaBoot (void)
|
||||
{
|
||||
int i, j, index, len;
|
||||
unsigned char b;
|
||||
int imageSize;
|
||||
|
||||
imageSize = sizeof (fpgadata);
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
/* search for preamble 0xFF2X */
|
||||
for (index = 0; index < imageSize - 1; index++) {
|
||||
if ((fpgadata[index] == 0xff)
|
||||
&& ((fpgadata[index + 1] & 0xf0) == 0x20))
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable cs1 instead of user0... */
|
||||
*(unsigned long *) 0x50000084 &= ~0x00000002;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
|
||||
*(unsigned long *) 0x50000084 &= ~0x00000400;
|
||||
udelay (FPGA_PRG_SLEEP * 1000);
|
||||
|
||||
*(unsigned long *) 0x50000084 |= 0x00000400;
|
||||
udelay (FPGA_PRG_SLEEP * 1000);
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* cs1: disable burst, disable ready */
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000300;
|
||||
|
||||
/* cs1: set write timing */
|
||||
*(unsigned long *) 0x50000118 |= 0x00010900;
|
||||
|
||||
/* write configuration-data into fpga... */
|
||||
for (i = index; i < imageSize; i++) {
|
||||
b = fpgadata[i];
|
||||
for (j = 0; j < 8; j++) {
|
||||
*(unsigned long *) 0x30000000 =
|
||||
((b & 0x80) == 0x80)
|
||||
? LOAD_LONG (0x03030101)
|
||||
: LOAD_LONG (0x02020000);
|
||||
b <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* set cs1 to 32 bit data-width, disable burst, enable ready */
|
||||
*(unsigned long *) 0x50000114 |= 0x00000202;
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000100;
|
||||
|
||||
/* cs1: set iop access to little endian */
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000010;
|
||||
|
||||
/* cs1: set read and write timing */
|
||||
*(unsigned long *) 0x50000118 = 0x00010000;
|
||||
*(unsigned long *) 0x5000011c = 0x00010001;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* wait for 30 ms... */
|
||||
udelay (30 * 1000);
|
||||
/* check if fpga's DONE signal - correctly booted ? */
|
||||
if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* Init pci regs
|
||||
*/
|
||||
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
|
||||
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
|
||||
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
|
||||
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
|
||||
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
|
||||
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
|
||||
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
int fpga;
|
||||
unsigned short val;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
fpga = fpgaBoot ();
|
||||
|
||||
if (!i || strncmp (str, "DASA_SIM", 8)) {
|
||||
puts ("### No HW ID - assuming DASA_SIM");
|
||||
}
|
||||
|
||||
puts (str);
|
||||
|
||||
if (fpga == 0) {
|
||||
val = *(unsigned short *) 0x30000202;
|
||||
printf (" (Id=%d Version=%d Revision=%d)",
|
||||
(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
} else {
|
||||
puts ("\nFPGA: Booting failed!");
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
return (16 * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define EEPROM_CAP 0x50000358
|
||||
#define EEPROM_DATA 0x5000035c
|
||||
|
||||
|
||||
unsigned int eepromReadLong(int offs)
|
||||
{
|
||||
unsigned int value;
|
||||
unsigned short ret;
|
||||
int count;
|
||||
|
||||
out_be16((void *)EEPROM_CAP, offs);
|
||||
|
||||
count = 0;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
count++;
|
||||
ret = in_be16((void *)EEPROM_CAP);
|
||||
|
||||
if ((ret & 0x8000) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
value = in_be32((void *)EEPROM_DATA);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
unsigned char eepromReadByte(int offs)
|
||||
{
|
||||
unsigned int valueLong;
|
||||
unsigned char *ptr;
|
||||
|
||||
valueLong = eepromReadLong(offs & ~3);
|
||||
ptr = (unsigned char *)&valueLong;
|
||||
|
||||
return ptr[offs & 3];
|
||||
}
|
||||
|
||||
|
||||
void eepromWriteLong(int offs, unsigned int value)
|
||||
{
|
||||
unsigned short ret;
|
||||
int count;
|
||||
|
||||
count = 0;
|
||||
|
||||
out_be32((void *)EEPROM_DATA, value);
|
||||
out_be16((void *)EEPROM_CAP, 0x8000 + offs);
|
||||
|
||||
for (;;)
|
||||
{
|
||||
count++;
|
||||
ret = in_be16((void *)EEPROM_CAP);
|
||||
|
||||
if ((ret & 0x8000) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void eepromWriteByte(int offs, unsigned char valueByte)
|
||||
{
|
||||
unsigned int valueLong;
|
||||
unsigned char *ptr;
|
||||
|
||||
valueLong = eepromReadLong(offs & ~3);
|
||||
ptr = (unsigned char *)&valueLong;
|
||||
|
||||
ptr[offs & 3] = valueByte;
|
||||
|
||||
eepromWriteLong(offs & ~3, valueLong);
|
||||
}
|
||||
|
||||
|
||||
void i2c_read (uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int i;
|
||||
int len2, ptr;
|
||||
|
||||
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
|
||||
|
||||
ptr = *(short *)addr;
|
||||
|
||||
/*
|
||||
* Read till lword boundary
|
||||
*/
|
||||
len2 = 4 - (*(short *)addr & 0x0003);
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*buffer++ = eepromReadByte(ptr++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read all lwords
|
||||
*/
|
||||
len2 = (len - len2) >> 2;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*(unsigned int *)buffer = eepromReadLong(ptr);
|
||||
buffer += 4;
|
||||
ptr += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read last bytes
|
||||
*/
|
||||
len2 = (*(short *)addr + len) & 0x0003;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*buffer++ = eepromReadByte(ptr++);
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_write (uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int i;
|
||||
int len2, ptr;
|
||||
|
||||
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
|
||||
|
||||
ptr = *(short *)addr;
|
||||
|
||||
/*
|
||||
* Write till lword boundary
|
||||
*/
|
||||
len2 = 4 - (*(short *)addr & 0x0003);
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteByte(ptr++, *buffer++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write all lwords
|
||||
*/
|
||||
len2 = (len - len2) >> 2;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteLong(ptr, *(unsigned int *)buffer);
|
||||
buffer += 4;
|
||||
ptr += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write last bytes
|
||||
*/
|
||||
len2 = (*(short *)addr + len) & 0x0003;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteByte(ptr++, *buffer++);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-monitor_flash_len,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
KEEP(*(.resetvec))
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/ppc4xx/start.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end__ = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common/xilinx_jtag)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
# Objects for Xilinx JTAG programming (CPLD)
|
||||
CPLD = ../common/xilinx_jtag/lenval.o \
|
||||
../common/xilinx_jtag/micro.o \
|
||||
../common/xilinx_jtag/ports.o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
128
root/package/utils/sysupgrade-helper/src/board/esd/dp405/dp405.c
Normal file
128
root/package/utils/sysupgrade-helper/src/board/esd/dp405/dp405.c
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
|
||||
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
|
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
|
||||
*/
|
||||
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
|
||||
|
||||
/*
|
||||
* Reset CPLD via GPIO13 (CS4) pin
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
|
||||
udelay(1000); /* wait 1ms */
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof(str));
|
||||
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
|
||||
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
|
||||
unsigned char id1, id2, rev;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1)
|
||||
puts ("### No HW ID - assuming DP405");
|
||||
else
|
||||
puts(str);
|
||||
|
||||
id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
|
||||
id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
|
||||
|
||||
rev = in_8((void *)0xf0001000);
|
||||
if (rev & 0x10) /* old DP405 compatibility */
|
||||
rev = in_8((void *)0xf0000800);
|
||||
|
||||
switch (rev & 0xc0) {
|
||||
case 0x00:
|
||||
puts(" (HW=DP405");
|
||||
break;
|
||||
case 0x80:
|
||||
puts(" (HW=DP405/CO");
|
||||
break;
|
||||
case 0xc0:
|
||||
puts(" (HW=DN405");
|
||||
break;
|
||||
}
|
||||
printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
|
||||
|
||||
if ((rev & 0xc0) == 0xc0) {
|
||||
printf(", C5V=%s",
|
||||
in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
|
||||
}
|
||||
puts(")\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
101
root/package/utils/sysupgrade-helper/src/board/esd/dp405/flash.c
Normal file
101
root/package/utils/sysupgrade-helper/src/board/esd/dp405/flash.c
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
int size_val = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
switch (size_b0) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CONFIG_SYS_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
203
root/package/utils/sysupgrade-helper/src/board/esd/du405/du405.c
Normal file
203
root/package/utils/sysupgrade-helper/src/board/esd/du405/du405.c
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "du405.h"
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/ppc4xx-i2c.h>
|
||||
#include <command.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define FPGA_DEBUG2
|
||||
#endif
|
||||
|
||||
/* fpga configuration data - generated by bin2cc */
|
||||
const unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
/*
|
||||
* include common fpga code (for esd boards)
|
||||
*/
|
||||
#include "../common/fpga.c"
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
int index, len, i;
|
||||
int status;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
|
||||
if (status != 0) {
|
||||
/* booting FPGA failed */
|
||||
#ifndef FPGA_DEBUG
|
||||
/* set up serial port with default baudrate */
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
serial_init ();
|
||||
console_init_f ();
|
||||
#endif
|
||||
printf ("\nFPGA: Booting failed ");
|
||||
switch (status) {
|
||||
case ERROR_FPGA_PRG_INIT_LOW:
|
||||
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_INIT_HIGH:
|
||||
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
|
||||
break;
|
||||
case ERROR_FPGA_PRG_DONE:
|
||||
printf ("(Timeout: DONE not high after programming FPGA)\n ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
putc ('\n');
|
||||
/* delayed reboot */
|
||||
for (i = 20; i > 0; i--) {
|
||||
printf ("Rebooting in %2d seconds \r", i);
|
||||
for (index = 0; index < 1000; index++)
|
||||
udelay (1000);
|
||||
}
|
||||
putc ('\n');
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
* IRQ 16 405GP internally generated; active low; level sensitive
|
||||
* IRQ 17-24 RESERVED
|
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
|
||||
* IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
|
||||
* IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
|
||||
* IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
|
||||
* IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
|
||||
* IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
|
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||
*/
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
|
||||
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
|
||||
mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
|
||||
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 100 us
|
||||
*/
|
||||
mtebc (EBC0_CFG, 0xb8400000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned long CPC0_CR0Reg;
|
||||
|
||||
/*
|
||||
* Setup UART1 handshaking: use CTS instead of DSR
|
||||
*/
|
||||
CPC0_CR0Reg = mfdcr(CPC0_CR0);
|
||||
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming DU405");
|
||||
} else {
|
||||
puts (str);
|
||||
}
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
/*
|
||||
* Reset external DUART via FPGA
|
||||
*/
|
||||
out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
|
||||
out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_LXT971_NO_SLEEP)
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
123
root/package/utils/sysupgrade-helper/src/board/esd/du405/flash.c
Normal file
123
root/package/utils/sysupgrade-helper/src/board/esd/du405/flash.c
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0, size_b1;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0, base_b1;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
base_b0 = FLASH_BASE0_PRELIM;
|
||||
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0 << 20);
|
||||
}
|
||||
|
||||
base_b1 = FLASH_BASE1_PRELIM;
|
||||
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
if (size_b1) {
|
||||
mtdcr (EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr (EBC0_CFGDATA);
|
||||
mtdcr (EBC0_CFGADDR, PB0CR);
|
||||
base_b1 = -size_b1;
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b1 |
|
||||
(((size_b1 / 1024 / 1024) - 1) << 17);
|
||||
mtdcr (EBC0_CFGDATA, pbcr);
|
||||
/* printf("PB1CR = %x\n", pbcr); */
|
||||
}
|
||||
|
||||
if (size_b0) {
|
||||
mtdcr (EBC0_CFGADDR, PB1CR);
|
||||
pbcr = mfdcr (EBC0_CFGDATA);
|
||||
mtdcr (EBC0_CFGADDR, PB1CR);
|
||||
base_b0 = base_b1 - size_b0;
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 |
|
||||
(((size_b0 / 1024 / 1024) - 1) << 17);
|
||||
mtdcr (EBC0_CFGDATA, pbcr);
|
||||
/* printf("PB0CR = %x\n", pbcr); */
|
||||
}
|
||||
|
||||
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
|
||||
|
||||
flash_get_offsets (base_b0, &flash_info[0]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
base_b0 + size_b0 - monitor_flash_len,
|
||||
base_b0 + size_b0 - 1, &flash_info[0]);
|
||||
|
||||
if (size_b1) {
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
|
||||
|
||||
flash_get_offsets (base_b1, &flash_info[1]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
base_b1 + size_b1 - monitor_flash_len,
|
||||
base_b1 + size_b1 - 1, &flash_info[1]);
|
||||
/* monitor protection OFF by default (one is enough) */
|
||||
flash_protect (FLAG_PROTECT_CLEAR,
|
||||
base_b0 + size_b0 - monitor_flash_len,
|
||||
base_b0 + size_b0 - 1, &flash_info[0]);
|
||||
} else {
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].sector_count = -1;
|
||||
}
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
flash_info[1].size = size_b1;
|
||||
|
||||
return (size_b0 + size_b1);
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue