mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,49 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,101 @@
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/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long * addr, flash_info_t * info);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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int i;
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uint pbcr;
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unsigned long base_b0;
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int size_val = 0;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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/* Re-do sizing to get full correct info */
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mtdcr(EBC0_CFGADDR, PB0CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGADDR, PB0CR);
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base_b0 = -size_b0;
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switch (size_b0) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
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mtdcr(EBC0_CFGDATA, pbcr);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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return (size_b0);
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}
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2358
root/package/utils/sysupgrade-helper/src/board/esd/plu405/fpgadata.c
Normal file
2358
root/package/utils/sysupgrade-helper/src/board/esd/plu405/fpgadata.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,361 @@
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/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <sja1000.h>
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#undef FPGA_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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/*
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* generate a short spike on the CAN tx line
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* to bring the couplers in sync
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*/
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void init_coupler(u32 addr)
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{
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struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
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/* reset */
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out_8(&ctrl->cr, CR_RR);
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/* dominant */
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out_8(&ctrl->btr0, 0x00); /* btr setup is required */
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out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
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out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
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OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
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out_8(&ctrl->cr, 0x00);
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/* delay */
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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/* reset */
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out_8(&ctrl->cr, CR_RR);
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}
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int board_early_init_f(void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to
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* 512 ebc-clks -> ca. 15 us
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*/
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mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
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return 0;
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}
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int misc_init_r(void)
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{
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unsigned char *dst;
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unsigned char fctr;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
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(uchar *)fpgadata, &len) != 0) {
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printf("GUNZIP ERROR - must RESET board to recover\n");
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do_reset(NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low "
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"after asserting PROGRAM*)\n");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high "
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"after deasserting PROGRAM*)\n");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high "
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"after programming FPGA)\n");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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/*
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* Reset external DUARTs
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*/
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
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udelay(10);
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
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udelay(1000);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) &
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~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
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/*
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* Setup EEPROM write protection
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*/
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
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out_be32((void*)GPIO0_TCR,
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in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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out_8((void *)DUART0_BA + 4, 0x08);
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out_8((void *)DUART1_BA + 4, 0x08);
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/*
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* Enable auto RS485 mode in 2nd external uart
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*/
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out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
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fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
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fctr |= 0x08; /* enable RS485 mode */
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out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
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out_8((void *)DUART1_BA + 3, 0); /* write LCR */
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/*
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* Init magnetic couplers
|
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*/
|
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if (!getenv("noinitcoupler")) {
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init_coupler(CAN0_BA);
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init_coupler(CAN1_BA);
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}
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return 0;
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}
|
||||
|
||||
/*
|
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* Check Board Identity:
|
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*/
|
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int checkboard(void)
|
||||
{
|
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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puts("Board: ");
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if (i == -1)
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puts("### No HW ID - assuming PLU405");
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else
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puts(str);
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putc('\n');
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return 0;
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||||
}
|
||||
|
||||
#ifdef CONFIG_IDE_RESET
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#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
|
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void ide_set_reset(int on)
|
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{
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) { /* assert RESET */
|
||||
out_be16((void *)FPGA_CTRL,
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||||
in_be16((void *)FPGA_CTRL) &
|
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~CONFIG_SYS_FPGA_CTRL_CF_RESET);
|
||||
} else { /* release RESET */
|
||||
out_be16((void *)FPGA_CTRL,
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||||
in_be16((void *)FPGA_CTRL) |
|
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CONFIG_SYS_FPGA_CTRL_CF_RESET);
|
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}
|
||||
}
|
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#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
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#endif
|
||||
}
|
||||
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#if defined(CONFIG_SYS_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
|
||||
* 0: disable write
|
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
|
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int eeprom_write_enable(unsigned dev_addr, int state)
|
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{
|
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if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
|
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return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO0. */
|
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out_be32((void*)GPIO0_OR,
|
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in_be32((void*)GPIO0_OR) &
|
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~CONFIG_SYS_EEPROM_WP);
|
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state = 0;
|
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break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR,
|
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in_be32((void*)GPIO0_OR) |
|
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CONFIG_SYS_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = ((in_be32((void*)GPIO0_OR) &
|
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CONFIG_SYS_EEPROM_WP) == 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf("Write access for device 0x%0x is %sabled.\n",
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if (argv[1][0] == '0') {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
1);
|
||||
}
|
||||
if (state < 0)
|
||||
puts("Setup of write access state failed.\n");
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"Enable / disable / query EEPROM write access",
|
||||
""
|
||||
);
|
||||
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
|
||||
Loading…
Add table
Add a link
Reference in a new issue