mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,38 @@
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#
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# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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#
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# Based on ti/evm/Makefile
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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101
root/package/utils/sysupgrade-helper/src/board/htkw/mcx/mcx.c
Normal file
101
root/package/utils/sysupgrade-helper/src/board/htkw/mcx/mcx.c
Normal file
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on ti/evm/evm.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include "errno.h"
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#include <i2c.h>
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "mcx.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(void)
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{
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return omap_ehci_hcd_init(&usbhs_bdata);
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}
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int ehci_hcd_stop(void)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_MCX();
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}
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0);
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}
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#endif
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#ifdef CONFIG_USB_EHCI_OMAP
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#define USB_HOST_PWR_EN 132
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int board_usb_init(void)
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{
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if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
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puts("Failed to get USB_HOST_PWR_EN pin\n");
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return -ENODEV;
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}
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gpio_direction_output(USB_HOST_PWR_EN, 1);
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return 0;
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}
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#endif
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408
root/package/utils/sysupgrade-helper/src/board/htkw/mcx/mcx.h
Normal file
408
root/package/utils/sysupgrade-helper/src/board/htkw/mcx/mcx.h
Normal file
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@ -0,0 +1,408 @@
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on ti/evm/evm.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef _AM3517EVM_H_
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#define _AM3517EVM_H_
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"HTKW mcx Board",
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"NAND",
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};
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_MCX() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_CKE0), (M0)) \
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MUX_VAL(CP(SDRC_CKE1), (M0)) \
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MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly0*/\
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MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly1*/\
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/* GPMC */\
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MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
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/* GPIO_43 LCD buffer enable */ \
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
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/* GPIO_57 TS_PenIRQn */\
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
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/* GPIO_58 ETHERNET RESET */\
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MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
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/* GPIO_61 SD-CARD CD */ \
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MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
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/* GPIO_62 Nand write protect, keep enabled */ \
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
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/* GPIO_65 SD-CARD WP */\
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/* DSS */\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
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/* CAMERA */\
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MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
|
||||
/* MMC */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_131 LCD Enable */ \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_132 USB host Enable */\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_133 HDMI PD */\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_152 USB phy2 reset */\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_153 */\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_154 USB phy1 reset */\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_155 TS_BUSY */\
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat7 */\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat4 */\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat5 */\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat6 */\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat3 */\
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
|
||||
/* SYS_nRESWARM */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_stp */ \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_clk */\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue