mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,428 @@
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/*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* (C) Copyright 2011
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* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <command.h>
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#include <malloc.h>
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#include <hush.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <linux/ctype.h>
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#if defined(CONFIG_POST)
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#include "post.h"
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#endif
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#include "common.h"
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#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
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#include <i2c.h>
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#endif
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#if !defined(CONFIG_MPC83xx)
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static void i2c_write_start_seq(void);
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Set Keymile specific environment variables
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* Currently only some memory layout variables are calculated here
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* ... ------------------------------------------------
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* ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM
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* ... |<------------------- pram ------------------->|
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* ... ------------------------------------------------
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* @END_OF_RAM: denotes the RAM size
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* @pnvramaddr: Startadress of pseudo non volatile RAM in hex
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* @pram : preserved ram size in k
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* @varaddr : startadress for /var mounted into RAM
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*/
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int set_km_env(void)
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{
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uchar buf[32];
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unsigned int pnvramaddr;
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unsigned int pram;
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unsigned int varaddr;
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unsigned int kernelmem;
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char *p;
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unsigned long rootfssize = 0;
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pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
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- CONFIG_KM_PNVRAM;
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sprintf((char *)buf, "0x%x", pnvramaddr);
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setenv("pnvramaddr", (char *)buf);
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/* try to read rootfssize (ram image) from envrionment */
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p = getenv("rootfssize");
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if (p != NULL)
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strict_strtoul(p, 16, &rootfssize);
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pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
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CONFIG_KM_PNVRAM) / 0x400;
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sprintf((char *)buf, "0x%x", pram);
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setenv("pram", (char *)buf);
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varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
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sprintf((char *)buf, "0x%x", varaddr);
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setenv("varaddr", (char *)buf);
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kernelmem = gd->ram_size - 0x400 * pram;
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sprintf((char *)buf, "0x%x", kernelmem);
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setenv("kernelmem", (char *)buf);
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return 0;
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}
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#if defined(CONFIG_SYS_I2C_INIT_BOARD)
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#if !defined(CONFIG_MPC83xx)
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static void i2c_write_start_seq(void)
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{
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set_sda(1);
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udelay(DELAY_HALF_PERIOD);
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set_scl(1);
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udelay(DELAY_HALF_PERIOD);
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set_sda(0);
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udelay(DELAY_HALF_PERIOD);
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set_scl(0);
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udelay(DELAY_HALF_PERIOD);
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}
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/*
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* I2C is a synchronous protocol and resets of the processor in the middle
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* of an access can block the I2C Bus until a powerdown of the full unit is
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* done. This function toggles the SCL until the SCL and SCA line are
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* released, but max. 16 times, after this a I2C start-sequence is sent.
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* This I2C Deblocking mechanism was developed by Keymile in association
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* with Anatech and Atmel in 1998.
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*/
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int i2c_make_abort(void)
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{
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#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
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i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
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/*
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* disable I2C controller first, otherwhise it thinks we want to
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* talk to the slave port...
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*/
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clrbits_8(&i2c->i2c_i2mod, 0x01);
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/* Set the PortPins to GPIO */
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setports(1);
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#endif
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int scl_state = 0;
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int sda_state = 0;
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int i = 0;
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int ret = 0;
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if (!get_sda()) {
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ret = -1;
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while (i < 16) {
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i++;
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set_scl(0);
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udelay(DELAY_ABORT_SEQ);
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set_scl(1);
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udelay(DELAY_ABORT_SEQ);
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scl_state = get_scl();
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sda_state = get_sda();
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if (scl_state && sda_state) {
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ret = 0;
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printf("[INFO] i2c abort after %d clocks\n", i);
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break;
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}
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}
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}
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if (ret == 0)
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for (i = 0; i < 5; i++)
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i2c_write_start_seq();
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else
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printf("[ERROR] i2c abort failed\n");
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/* respect stop setup time */
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udelay(DELAY_ABORT_SEQ);
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set_scl(1);
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udelay(DELAY_ABORT_SEQ);
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set_sda(1);
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get_sda();
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#if defined(CONFIG_HARD_I2C)
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/* Set the PortPins back to use for I2C */
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setports(0);
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#endif
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return ret;
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}
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#endif
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/**
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* i2c_init_board - reset i2c bus. When the board is powercycled during a
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* bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
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*/
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void i2c_init_board(void)
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{
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/* Now run the AbortSequence() */
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i2c_make_abort();
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}
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#endif
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#if !defined(MACH_TYPE_KM_KIRKWOOD)
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int ethernet_present(void)
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{
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
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return in_8(&base->bprth) & PIGGY_PRESENT;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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if (ethernet_present())
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return cpu_eth_init(bis);
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return -1;
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}
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/*
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* do_setboardid command
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* read out the board id and the hw key from the intventory EEPROM and set
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* this values as environment variables.
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*/
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static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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{
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unsigned char buf[32];
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char *p;
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p = get_local_var("IVM_BoardId");
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if (p == NULL) {
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printf("can't get the IVM_Boardid\n");
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return 1;
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}
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sprintf((char *)buf, "%s", p);
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setenv("boardid", (char *)buf);
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printf("set boardid=%s\n", buf);
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p = get_local_var("IVM_HWKey");
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if (p == NULL) {
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printf("can't get the IVM_HWKey\n");
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return 1;
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}
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sprintf((char *)buf, "%s", p);
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setenv("hwkey", (char *)buf);
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printf("set hwkey=%s\n", buf);
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printf("Execute manually saveenv for persistent storage.\n");
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return 0;
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}
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U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and "
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"hwkey from IVM and set in environment");
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/*
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* command km_checkbidhwk
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* if "boardid" and "hwkey" are not already set in the environment, do:
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* if a "boardIdListHex" exists in the environment:
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* - read ivm data for boardid and hwkey
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* - compare each entry of the boardIdListHex with the
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* IVM data:
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* if match:
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* set environment variables boardid, boardId,
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* hwkey, hwKey to the found values
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* both (boardid and boardId) are set because
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* they might be used differently in the
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* application and in the init scripts (?)
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* return 0 in case of match, 1 if not match or error
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*/
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int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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{
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unsigned long ivmbid = 0, ivmhwkey = 0;
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unsigned long envbid = 0, envhwkey = 0;
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char *p;
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int verbose = argc > 1 && *argv[1] == 'v';
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int rc = 0;
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/*
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* first read out the real inventory values, these values are
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* already stored in the local hush variables
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*/
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p = get_local_var("IVM_BoardId");
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if (p == NULL) {
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printf("can't get the IVM_Boardid\n");
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return 1;
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}
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rc = strict_strtoul(p, 16, &ivmbid);
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p = get_local_var("IVM_HWKey");
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if (p == NULL) {
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printf("can't get the IVM_HWKey\n");
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return 1;
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}
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rc = strict_strtoul(p, 16, &ivmhwkey);
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if (!ivmbid || !ivmhwkey) {
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printf("Error: IVM_BoardId and/or IVM_HWKey not set!\n");
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return rc;
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}
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/* now try to read values from environment if available */
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p = getenv("boardid");
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if (p != NULL)
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rc = strict_strtoul(p, 16, &envbid);
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p = getenv("hwkey");
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if (p != NULL)
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rc = strict_strtoul(p, 16, &envhwkey);
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if (rc != 0) {
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printf("strict_strtoul returns error: %d", rc);
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return rc;
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}
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if (!envbid || !envhwkey) {
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/*
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* BoardId/HWkey not available in the environment, so try the
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* environment variable for BoardId/HWkey list
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*/
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char *bidhwklist = getenv("boardIdListHex");
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if (bidhwklist) {
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int found = 0;
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char *rest = bidhwklist;
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char *endp;
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if (verbose) {
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printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n",
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ivmbid, ivmhwkey);
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printf("boardIdHwKeyList: %s\n",
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bidhwklist);
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}
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while (!found) {
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/* loop over each bid/hwkey pair in the list */
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unsigned long bid = 0;
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unsigned long hwkey = 0;
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while (*rest && !isxdigit(*rest))
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rest++;
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/*
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* use simple_strtoul because we need &end and
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* we know we got non numeric char at the end
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*/
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bid = simple_strtoul(rest, &endp, 16);
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/* BoardId and HWkey are separated with a "_" */
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if (*endp == '_') {
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rest = endp + 1;
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/*
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* use simple_strtoul because we need
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* &end
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*/
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hwkey = simple_strtoul(rest, &endp, 16);
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rest = endp;
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while (*rest && !isxdigit(*rest))
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rest++;
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}
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if ((!bid) || (!hwkey)) {
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/* end of list */
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break;
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}
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if (verbose) {
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printf("trying bid=0x%lX, hwkey=%ld\n",
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bid, hwkey);
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}
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/*
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* Compare the values of the found entry in the
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* list with the valid values which are stored
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* in the inventory eeprom. If they are equal
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* set the values in environment variables.
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*/
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if ((bid == ivmbid) && (hwkey == ivmhwkey)) {
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char buf[10];
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found = 1;
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envbid = bid;
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envhwkey = hwkey;
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sprintf(buf, "%lx", bid);
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setenv("boardid", buf);
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sprintf(buf, "%lx", hwkey);
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setenv("hwkey", buf);
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}
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} /* end while( ! found ) */
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}
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}
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/* compare now the values */
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if ((ivmbid == envbid) && (ivmhwkey == envhwkey)) {
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printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey);
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rc = 0; /* match */
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} else {
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printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid,
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envhwkey);
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printf(" IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey);
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rc = 1; /* don't match */
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}
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return rc;
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}
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U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk,
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"check boardid and hwkey",
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"[v]\n - check environment parameter "\
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"\"boardIdListHex\" against stored boardid and hwkey "\
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"from the IVM\n v: verbose output"
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);
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/*
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* command km_checktestboot
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* if the testpin of the board is asserted, return 1
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* * else return 0
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*/
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int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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{
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int testpin = 0;
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char *s = NULL;
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int testboot = 0;
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int verbose = argc > 1 && *argv[1] == 'v';
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#if defined(CONFIG_POST)
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testpin = post_hotkeys_pressed();
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s = getenv("test_bank");
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#endif
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/* when test_bank is not set, act as if testpin is not asserted */
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testboot = (testpin != 0) && (s);
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if (verbose) {
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printf("testpin = %d\n", testpin);
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printf("test_bank = %s\n", s ? s : "not set");
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printf("boot test app : %s\n", (testboot) ? "yes" : "no");
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}
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/* return 0 means: testboot, therefore we need the inversion */
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return !testboot;
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}
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U_BOOT_CMD(km_checktestboot, 2, 0, do_checktestboot,
|
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"check if testpin is asserted",
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"[v]\n v - verbose output"
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);
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|
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@ -0,0 +1,155 @@
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/*
|
||||
* (C) Copyright 2008
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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||||
*/
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#ifndef __KEYMILE_COMMON_H
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#define __KEYMILE_COMMON_H
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#define WRG_RESET 0x80
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#define H_OPORTS_14 0x40
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#define WRG_LED 0x02
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#define WRL_BOOT 0x01
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#define OPRTL_XBUFENA 0x20
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#define H_OPORTS_SCC4_ENA 0x10
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#define H_OPORTS_SCC4_FD_ENA 0x04
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#define H_OPORTS_FCC1_PW_DWN 0x01
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#define PIGGY_PRESENT 0x80
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struct km_bec_fpga {
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unsigned char id;
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unsigned char rev;
|
||||
unsigned char oprth;
|
||||
unsigned char oprtl;
|
||||
unsigned char res1[3];
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||||
unsigned char bprth;
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unsigned char bprtl;
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unsigned char gprt3;
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unsigned char gprt2;
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unsigned char gprt1;
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unsigned char gprt0;
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unsigned char res2[2];
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unsigned char prst;
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unsigned char res3[0xfff0];
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unsigned char pgy_id;
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unsigned char pgy_rev;
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unsigned char pgy_outputs;
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unsigned char pgy_eth;
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||||
};
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||||
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#define BFTICU_DIPSWITCH_MASK 0x0f
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|
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/*
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||||
* BFTICU FPGA iomap
|
||||
* BFTICU is used on mgcoge and mgocge3ne
|
||||
*/
|
||||
struct bfticu_iomap {
|
||||
u8 xi_ena; /* General defect enable */
|
||||
u8 pack1[3];
|
||||
u8 en_csn;
|
||||
u8 pack2;
|
||||
u8 safe_mem;
|
||||
u8 pack3;
|
||||
u8 id;
|
||||
u8 pack4;
|
||||
u8 rev;
|
||||
u8 build;
|
||||
u8 p_frc;
|
||||
u8 p_msk;
|
||||
u8 pack5[2];
|
||||
u8 xg_int;
|
||||
u8 pack6[15];
|
||||
u8 s_conf;
|
||||
u8 pack7;
|
||||
u8 dmx_conf12;
|
||||
u8 pack8;
|
||||
u8 s_clkslv;
|
||||
u8 pack9[11];
|
||||
u8 d_conf;
|
||||
u8 d_mask_ca;
|
||||
u8 d_pll_del;
|
||||
u8 pack10[16];
|
||||
u8 t_conf_ca;
|
||||
u8 t_mask_ca;
|
||||
u8 pack11[13];
|
||||
u8 m_def0;
|
||||
u8 m_def1;
|
||||
u8 m_def2;
|
||||
u8 m_def3;
|
||||
u8 m_def4;
|
||||
u8 m_def5;
|
||||
u8 m_def_trap0;
|
||||
u8 m_def_trap1;
|
||||
u8 m_def_trap2;
|
||||
u8 m_def_trap3;
|
||||
u8 m_def_trap4;
|
||||
u8 m_def_trap5;
|
||||
u8 m_mask_def0;
|
||||
u8 m_mask_def1;
|
||||
u8 m_mask_def2;
|
||||
u8 m_mask_def3;
|
||||
u8 m_mask_def4;
|
||||
u8 m_mask_def5;
|
||||
u8 m_def_mask0;
|
||||
u8 m_def_mask1;
|
||||
u8 m_def_mask2;
|
||||
u8 m_def_mask3;
|
||||
u8 m_def_mask4;
|
||||
u8 m_def_mask5;
|
||||
u8 m_def_pri;
|
||||
u8 pack12[11];
|
||||
u8 hw_status;
|
||||
u8 pack13;
|
||||
u8 hw_control1;
|
||||
u8 hw_control2;
|
||||
u8 hw_control3;
|
||||
u8 pack14[7];
|
||||
u8 led_on; /* Leds */
|
||||
u8 pack15;
|
||||
u8 sfp_control; /* SFP modules */
|
||||
u8 pack16;
|
||||
u8 alarm_control; /* Alarm output */
|
||||
u8 pack17;
|
||||
u8 icps; /* ICN clock pulse shaping */
|
||||
u8 mswitch; /* Read mode switch */
|
||||
u8 pack18[6];
|
||||
u8 pb_dbug;
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
|
||||
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
|
||||
#endif
|
||||
|
||||
int ethernet_present(void);
|
||||
int ivm_read_eeprom(void);
|
||||
|
||||
int trigger_fpga_config(void);
|
||||
int wait_for_fpga_config(void);
|
||||
int fpga_reset(void);
|
||||
int toggle_eeprom_spi_bus(void);
|
||||
|
||||
int set_km_env(void);
|
||||
int fdt_set_node_and_value(void *blob,
|
||||
char *nodename,
|
||||
char *regname,
|
||||
void *var,
|
||||
int size);
|
||||
int fdt_get_node_and_value(void *blob,
|
||||
char *nodename,
|
||||
char *propname,
|
||||
void **var);
|
||||
|
||||
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
|
||||
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
|
||||
|
||||
int i2c_soft_read_pin(void);
|
||||
int i2c_make_abort(void);
|
||||
#endif /* __KEYMILE_COMMON_H */
|
||||
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hush.h>
|
||||
#include <i2c.h>
|
||||
#include "common.h"
|
||||
|
||||
int ivm_calc_crc(unsigned char *buf, int len)
|
||||
{
|
||||
const unsigned short crc_tab[16] = {
|
||||
0x0000, 0xCC01, 0xD801, 0x1400,
|
||||
0xF001, 0x3C00, 0x2800, 0xE401,
|
||||
0xA001, 0x6C00, 0x7800, 0xB401,
|
||||
0x5000, 0x9C01, 0x8801, 0x4400};
|
||||
|
||||
unsigned short crc = 0; /* final result */
|
||||
unsigned short r1 = 0; /* temp */
|
||||
unsigned char byte = 0; /* input buffer */
|
||||
int i;
|
||||
|
||||
/* calculate CRC from array data */
|
||||
for (i = 0; i < len; i++) {
|
||||
byte = buf[i];
|
||||
|
||||
/* lower 4 bits */
|
||||
r1 = crc_tab[crc & 0xF];
|
||||
crc = ((crc) >> 4) & 0x0FFF;
|
||||
crc = crc ^ r1 ^ crc_tab[byte & 0xF];
|
||||
|
||||
/* upper 4 bits */
|
||||
r1 = crc_tab[crc & 0xF];
|
||||
crc = (crc >> 4) & 0x0FFF;
|
||||
crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
||||
static int ivm_set_value(char *name, char *value)
|
||||
{
|
||||
char tempbuf[256];
|
||||
|
||||
if (value != NULL) {
|
||||
sprintf(tempbuf, "%s=%s", name, value);
|
||||
return set_local_var(tempbuf, 0);
|
||||
} else {
|
||||
unset_local_var(name);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
|
||||
int check)
|
||||
{
|
||||
unsigned short val;
|
||||
unsigned char valbuf[30];
|
||||
|
||||
if ((buf[off + 0] != buf[off + 2]) &&
|
||||
(buf[off + 2] != buf[off + 4])) {
|
||||
printf("%s Error corrupted %s\n", __func__, name);
|
||||
val = -1;
|
||||
} else {
|
||||
val = buf[off + 0] + (buf[off + 1] << 8);
|
||||
if ((val == 0) && (check == 1))
|
||||
val = -1;
|
||||
}
|
||||
sprintf((char *)valbuf, "%x", val);
|
||||
ivm_set_value(name, (char *)valbuf);
|
||||
return val;
|
||||
}
|
||||
|
||||
#define INV_BLOCKSIZE 0x100
|
||||
#define INV_DATAADDRESS 0x21
|
||||
#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3)
|
||||
|
||||
#define IVM_POS_SHORT_TEXT 0
|
||||
#define IVM_POS_MANU_ID 1
|
||||
#define IVM_POS_MANU_SERIAL 2
|
||||
#define IVM_POS_PART_NUMBER 3
|
||||
#define IVM_POS_BUILD_STATE 4
|
||||
#define IVM_POS_SUPPLIER_PART_NUMBER 5
|
||||
#define IVM_POS_DELIVERY_DATE 6
|
||||
#define IVM_POS_SUPPLIER_BUILD_STATE 7
|
||||
#define IVM_POS_CUSTOMER_ID 8
|
||||
#define IVM_POS_CUSTOMER_PROD_ID 9
|
||||
#define IVM_POS_HISTORY 10
|
||||
#define IVM_POS_SYMBOL_ONLY 11
|
||||
|
||||
static char convert_char(char c)
|
||||
{
|
||||
return (c < ' ' || c > '~') ? '.' : c;
|
||||
}
|
||||
|
||||
static int ivm_findinventorystring(int type,
|
||||
unsigned char *const string,
|
||||
unsigned long maxlen,
|
||||
unsigned char *buf)
|
||||
{
|
||||
int xcode = 0;
|
||||
unsigned long cr = 0;
|
||||
unsigned long addr = INV_DATAADDRESS;
|
||||
unsigned long size = 0;
|
||||
unsigned long nr = type;
|
||||
int stop = 0; /* stop on semicolon */
|
||||
|
||||
memset(string, '\0', maxlen);
|
||||
switch (type) {
|
||||
case IVM_POS_SYMBOL_ONLY:
|
||||
nr = 0;
|
||||
stop = 1;
|
||||
break;
|
||||
default:
|
||||
nr = type;
|
||||
stop = 0;
|
||||
}
|
||||
|
||||
/* Look for the requested number of CR. */
|
||||
while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
|
||||
if ((buf[addr] == '\r'))
|
||||
cr++;
|
||||
addr++;
|
||||
}
|
||||
|
||||
/*
|
||||
* the expected number of CR was found until the end of the IVM
|
||||
* content --> fill string
|
||||
*/
|
||||
if (addr < INVENTORYDATASIZE) {
|
||||
/* Copy the IVM string in the corresponding string */
|
||||
for (; (buf[addr] != '\r') &&
|
||||
((buf[addr] != ';') || (!stop)) &&
|
||||
(size < (maxlen - 1) &&
|
||||
(addr < INVENTORYDATASIZE)); addr++) {
|
||||
size += sprintf((char *)string + size, "%c",
|
||||
convert_char (buf[addr]));
|
||||
}
|
||||
|
||||
/*
|
||||
* copy phase is done: check if everything is ok. If not,
|
||||
* the inventory data is most probably corrupted: tell
|
||||
* the world there is a problem!
|
||||
*/
|
||||
if (addr == INVENTORYDATASIZE) {
|
||||
xcode = -1;
|
||||
printf("Error end of string not found\n");
|
||||
} else if ((size >= (maxlen - 1)) &&
|
||||
(buf[addr] != '\r')) {
|
||||
xcode = -1;
|
||||
printf("string too long till next CR\n");
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* some CR are missing...
|
||||
* the inventory data is most probably corrupted
|
||||
*/
|
||||
xcode = -1;
|
||||
printf("not enough cr found\n");
|
||||
}
|
||||
return xcode;
|
||||
}
|
||||
|
||||
#define GET_STRING(name, which, len) \
|
||||
if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
|
||||
ivm_set_value(name, (char *)valbuf); \
|
||||
}
|
||||
|
||||
static int ivm_check_crc(unsigned char *buf, int block)
|
||||
{
|
||||
unsigned long crc;
|
||||
unsigned long crceeprom;
|
||||
|
||||
crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
|
||||
crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
|
||||
buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
|
||||
if (crc != crceeprom) {
|
||||
if (block == 0)
|
||||
printf("Error CRC Block: %d EEprom: calculated: \
|
||||
%lx EEprom: %lx\n", block, crc, crceeprom);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ivm_analyze_block2(unsigned char *buf, int len)
|
||||
{
|
||||
unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
|
||||
unsigned long count;
|
||||
|
||||
/* IVM_MAC Adress begins at offset 1 */
|
||||
sprintf((char *)valbuf, "%pM", buf + 1);
|
||||
ivm_set_value("IVM_MacAddress", (char *)valbuf);
|
||||
/* if an offset is defined, add it */
|
||||
#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
|
||||
if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) {
|
||||
unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
|
||||
|
||||
val += CONFIG_PIGGY_MAC_ADRESS_OFFSET;
|
||||
buf[4] = (val >> 16) & 0xff;
|
||||
buf[5] = (val >> 8) & 0xff;
|
||||
buf[6] = val & 0xff;
|
||||
sprintf((char *)valbuf, "%pM", buf + 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef MACH_TYPE_KM_KIRKWOOD
|
||||
setenv((char *)"ethaddr", (char *)valbuf);
|
||||
#else
|
||||
if (getenv("ethaddr") == NULL)
|
||||
setenv((char *)"ethaddr", (char *)valbuf);
|
||||
#endif
|
||||
|
||||
/* IVM_MacCount */
|
||||
count = (buf[10] << 24) +
|
||||
(buf[11] << 16) +
|
||||
(buf[12] << 8) +
|
||||
buf[13];
|
||||
if (count == 0xffffffff)
|
||||
count = 1;
|
||||
sprintf((char *)valbuf, "%lx", count);
|
||||
ivm_set_value("IVM_MacCount", (char *)valbuf);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ivm_analyze_eeprom(unsigned char *buf, int len)
|
||||
{
|
||||
unsigned short val;
|
||||
unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
|
||||
unsigned char *tmp;
|
||||
|
||||
if (ivm_check_crc(buf, 0) != 0)
|
||||
return -1;
|
||||
|
||||
ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
|
||||
"IVM_BoardId", 0, 1);
|
||||
val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
|
||||
"IVM_HWKey", 6, 1);
|
||||
if (val != 0xffff) {
|
||||
sprintf((char *)valbuf, "%x", ((val / 100) % 10));
|
||||
ivm_set_value("IVM_HWVariant", (char *)valbuf);
|
||||
sprintf((char *)valbuf, "%x", (val % 100));
|
||||
ivm_set_value("IVM_HWVersion", (char *)valbuf);
|
||||
}
|
||||
ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
|
||||
"IVM_Functions", 12, 0);
|
||||
|
||||
GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
|
||||
GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
|
||||
tmp = (unsigned char *) getenv("IVM_DeviceName");
|
||||
if (tmp) {
|
||||
int len = strlen((char *)tmp);
|
||||
int i = 0;
|
||||
|
||||
while (i < len) {
|
||||
if (tmp[i] == ';') {
|
||||
ivm_set_value("IVM_ShortText",
|
||||
(char *)&tmp[i + 1]);
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
if (i >= len)
|
||||
ivm_set_value("IVM_ShortText", NULL);
|
||||
} else {
|
||||
ivm_set_value("IVM_ShortText", NULL);
|
||||
}
|
||||
GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
|
||||
GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
|
||||
GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
|
||||
GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
|
||||
GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
|
||||
GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
|
||||
GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
|
||||
GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
|
||||
GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
|
||||
|
||||
if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
|
||||
return 0;
|
||||
ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
|
||||
CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ivm_read_eeprom(void)
|
||||
{
|
||||
#if defined(CONFIG_I2C_MUX)
|
||||
I2C_MUX_DEVICE *dev = NULL;
|
||||
#endif
|
||||
uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
|
||||
uchar *buf;
|
||||
unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
|
||||
int ret;
|
||||
|
||||
#if defined(CONFIG_I2C_MUX)
|
||||
/* First init the Bus, select the Bus */
|
||||
#if defined(CONFIG_SYS_I2C_IVM_BUS)
|
||||
dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS);
|
||||
#else
|
||||
buf = (unsigned char *) getenv("EEprom_ivm");
|
||||
if (buf != NULL)
|
||||
dev = i2c_mux_ident_muxstring(buf);
|
||||
#endif
|
||||
if (dev == NULL) {
|
||||
printf("Error couldnt add Bus for IVM\n");
|
||||
return -1;
|
||||
}
|
||||
i2c_set_bus_num(dev->busid);
|
||||
#endif
|
||||
|
||||
buf = (unsigned char *) getenv("EEprom_ivm_addr");
|
||||
if (buf != NULL) {
|
||||
ret = strict_strtoul((char *)buf, 16, &dev_addr);
|
||||
if (ret != 0)
|
||||
return -3;
|
||||
}
|
||||
|
||||
/* add deblocking here */
|
||||
i2c_make_abort();
|
||||
|
||||
ret = i2c_read(dev_addr, 0, 1, i2c_buffer,
|
||||
CONFIG_SYS_IVM_EEPROM_MAX_LEN);
|
||||
if (ret != 0) {
|
||||
printf("Error reading EEprom\n");
|
||||
return -2;
|
||||
}
|
||||
|
||||
return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2001-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,431 @@
|
|||
/*
|
||||
* (C) Copyright 2007 - 2008
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8260.h>
|
||||
#include <ioports.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA31 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA30 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA29 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA28 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA27 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA26 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA25 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA24 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA23 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA22 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA21 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA20 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA19 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA18 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA17 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA16 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA15 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA14 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA13 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA12 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA11 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA10 */
|
||||
{ 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA7 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA6 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA5 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA4 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA3 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA2 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PA1 */
|
||||
{ 0, 0, 0, 0, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB31 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB30 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB29 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB28 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB27 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB26 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB25 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB24 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB23 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB22 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB21 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB20 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB19 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PB18 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC31 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC30 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC29 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC28 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC27 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC26 */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC23 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC22 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC21 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC20 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC19 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC18 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC17 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC16 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC15 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC14 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC13 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC12 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC11 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC10 */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC7 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC6 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC5 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC4 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC3 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC2 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC1 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PC0 */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD31 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD30 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD29 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD28 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD27 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD26 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD25 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD24 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD23 */
|
||||
{ 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
|
||||
{ 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
|
||||
{ 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD19 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD18 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD17 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD16 */
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
{ 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
|
||||
{ 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
|
||||
#else
|
||||
{ 1, 0, 0, 0, 1, 1 }, /* PD15 */
|
||||
{ 1, 0, 0, 1, 1, 1 }, /* PD14 */
|
||||
#endif
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD9 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD8 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD7 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD6 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD5 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD4 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
{ 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
|
||||
*
|
||||
* This routine performs standard 8260 initialization sequence
|
||||
* and calculates the available memory size. It may be called
|
||||
* several times to try different SDRAM configurations on both
|
||||
* 60x and local buses.
|
||||
*/
|
||||
static long int try_init(memctl8260_t *memctl, ulong sdmr,
|
||||
ulong orx, uchar *base)
|
||||
{
|
||||
uchar c = 0xff;
|
||||
ulong maxsize, size;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be
|
||||
* mapped by the controller. That means, that the initial mapping has
|
||||
* to be (at least) twice as large as the maximum expected size.
|
||||
*/
|
||||
maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
|
||||
|
||||
out_be32(&memctl->memc_or1, orx);
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address
|
||||
* CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
|
||||
out_8(base, c);
|
||||
|
||||
out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
|
||||
for (i = 0; i < 8; i++)
|
||||
out_8(base, c);
|
||||
|
||||
out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
|
||||
/* setting MR on address lines */
|
||||
out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
|
||||
|
||||
out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
|
||||
out_8(base, c);
|
||||
|
||||
size = get_ram_size((long *)base, maxsize);
|
||||
out_be32(&memctl->memc_or1, orx | ~(size - 1));
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
memctl8260_t *memctl = &immap->im_memctl;
|
||||
|
||||
long psize;
|
||||
|
||||
out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
|
||||
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* 60x SDRAM setup:
|
||||
*/
|
||||
psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
icache_enable();
|
||||
|
||||
return psize;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#if defined(CONFIG_MGCOGE)
|
||||
puts("Board: Keymile mgcoge");
|
||||
#else
|
||||
puts("Board: Keymile mgcoge3ne");
|
||||
#endif
|
||||
if (ethernet_present())
|
||||
puts(" with PIGGY.");
|
||||
puts("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
struct bfticu_iomap *base =
|
||||
(struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
|
||||
u8 dip_switch;
|
||||
|
||||
dip_switch = in_8(&base->mswitch);
|
||||
dip_switch &= BFTICU_DIPSWITCH_MASK;
|
||||
/* dip switch 'full reset' or 'db erase' */
|
||||
if (dip_switch & 0x1 || dip_switch & 0x2) {
|
||||
/* start bootloader */
|
||||
puts("DIP: Enabled\n");
|
||||
setenv("actual_bank", "0");
|
||||
}
|
||||
set_km_env();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MGCOGE3NE
|
||||
static void set_pin(int state, unsigned long mask);
|
||||
|
||||
/*
|
||||
* For mgcoge3ne boards, the mgcoge3un control is controlled from
|
||||
* a GPIO line on the PPC CPU. If bobcatreset is set the line
|
||||
* will toggle once what forces the mgocge3un part to restart
|
||||
* immediately.
|
||||
*/
|
||||
void handle_mgcoge3un_reset(void)
|
||||
{
|
||||
char *bobcatreset = getenv("bobcatreset");
|
||||
if (bobcatreset) {
|
||||
if (strcmp(bobcatreset, "true") == 0) {
|
||||
puts("Forcing bobcat reset\n");
|
||||
set_pin(0, 0x00000004); /* clear PD29 to reset arm */
|
||||
udelay(1000);
|
||||
set_pin(1, 0x00000004);
|
||||
} else
|
||||
set_pin(1, 0x00000004); /* set PD29 to not reset arm */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Early board initalization.
|
||||
*/
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
struct km_bec_fpga *base =
|
||||
(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
|
||||
|
||||
/* setup the UPIOx */
|
||||
/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
|
||||
out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
|
||||
/* SCC4 enable, halfduplex, FCC1 powerdown */
|
||||
out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
|
||||
H_OPORTS_FCC1_PW_DWN));
|
||||
|
||||
#ifdef CONFIG_MGCOGE3NE
|
||||
handle_mgcoge3un_reset();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hush_init_var(void)
|
||||
{
|
||||
ivm_read_eeprom();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define SDA_MASK 0x00010000
|
||||
#define SCL_MASK 0x00020000
|
||||
|
||||
static void set_pin(int state, unsigned long mask)
|
||||
{
|
||||
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
|
||||
|
||||
if (state)
|
||||
setbits_be32(&iop->pdat, mask);
|
||||
else
|
||||
clrbits_be32(&iop->pdat, mask);
|
||||
|
||||
setbits_be32(&iop->pdir, mask);
|
||||
}
|
||||
|
||||
static int get_pin(unsigned long mask)
|
||||
{
|
||||
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
|
||||
|
||||
clrbits_be32(&iop->pdir, mask);
|
||||
return 0 != (in_be32(&iop->pdat) & mask);
|
||||
}
|
||||
|
||||
void set_sda(int state)
|
||||
{
|
||||
set_pin(state, SDA_MASK);
|
||||
}
|
||||
|
||||
void set_scl(int state)
|
||||
{
|
||||
set_pin(state, SCL_MASK);
|
||||
}
|
||||
|
||||
int get_sda(void)
|
||||
{
|
||||
return get_pin(SDA_MASK);
|
||||
}
|
||||
|
||||
int get_scl(void)
|
||||
{
|
||||
return get_pin(SCL_MASK);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
static void setports(int gpio)
|
||||
{
|
||||
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
|
||||
|
||||
if (gpio) {
|
||||
clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
|
||||
clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
|
||||
} else {
|
||||
setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
|
||||
clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
|
||||
setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS += $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2007 Logic Product Development, Inc.
|
||||
* Peter Barada <peterb@logicpd.com>
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* (C) Copyright 2008 - 2010
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
#include <libfdt.h>
|
||||
#include <post.h>
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
/* port pin dir open_drain assign */
|
||||
#if defined(CONFIG_MPC8360)
|
||||
/* MDIO */
|
||||
{0, 1, 3, 0, 2}, /* MDIO */
|
||||
{0, 2, 1, 0, 1}, /* MDC */
|
||||
|
||||
/* UCC4 - UEC */
|
||||
{1, 14, 1, 0, 1}, /* TxD0 */
|
||||
{1, 15, 1, 0, 1}, /* TxD1 */
|
||||
{1, 20, 2, 0, 1}, /* RxD0 */
|
||||
{1, 21, 2, 0, 1}, /* RxD1 */
|
||||
{1, 18, 1, 0, 1}, /* TX_EN */
|
||||
{1, 26, 2, 0, 1}, /* RX_DV */
|
||||
{1, 27, 2, 0, 1}, /* RX_ER */
|
||||
{1, 24, 2, 0, 1}, /* COL */
|
||||
{1, 25, 2, 0, 1}, /* CRS */
|
||||
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
|
||||
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
|
||||
|
||||
/* DUART - UART2 */
|
||||
{5, 0, 1, 0, 2}, /* UART2_SOUT */
|
||||
{5, 2, 1, 0, 1}, /* UART2_RTS */
|
||||
{5, 3, 2, 0, 2}, /* UART2_SIN */
|
||||
{5, 1, 2, 0, 3}, /* UART2_CTS */
|
||||
#else
|
||||
/* Local Bus */
|
||||
{0, 16, 1, 0, 3}, /* LA00 */
|
||||
{0, 17, 1, 0, 3}, /* LA01 */
|
||||
{0, 18, 1, 0, 3}, /* LA02 */
|
||||
{0, 19, 1, 0, 3}, /* LA03 */
|
||||
{0, 20, 1, 0, 3}, /* LA04 */
|
||||
{0, 21, 1, 0, 3}, /* LA05 */
|
||||
{0, 22, 1, 0, 3}, /* LA06 */
|
||||
{0, 23, 1, 0, 3}, /* LA07 */
|
||||
{0, 24, 1, 0, 3}, /* LA08 */
|
||||
{0, 25, 1, 0, 3}, /* LA09 */
|
||||
{0, 26, 1, 0, 3}, /* LA10 */
|
||||
{0, 27, 1, 0, 3}, /* LA11 */
|
||||
{0, 28, 1, 0, 3}, /* LA12 */
|
||||
{0, 29, 1, 0, 3}, /* LA13 */
|
||||
{0, 30, 1, 0, 3}, /* LA14 */
|
||||
{0, 31, 1, 0, 3}, /* LA15 */
|
||||
|
||||
/* MDIO */
|
||||
{3, 4, 3, 0, 2}, /* MDIO */
|
||||
{3, 5, 1, 0, 2}, /* MDC */
|
||||
|
||||
/* UCC4 - UEC */
|
||||
{1, 18, 1, 0, 1}, /* TxD0 */
|
||||
{1, 19, 1, 0, 1}, /* TxD1 */
|
||||
{1, 22, 2, 0, 1}, /* RxD0 */
|
||||
{1, 23, 2, 0, 1}, /* RxD1 */
|
||||
{1, 26, 2, 0, 1}, /* RxER */
|
||||
{1, 28, 2, 0, 1}, /* Rx_DV */
|
||||
{1, 30, 1, 0, 1}, /* TxEN */
|
||||
{1, 31, 2, 0, 1}, /* CRS */
|
||||
{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
|
||||
#endif
|
||||
|
||||
/* END of table */
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END},
|
||||
};
|
||||
|
||||
static int board_init_i2c_busses(void)
|
||||
{
|
||||
I2C_MUX_DEVICE *dev = NULL;
|
||||
uchar *buf;
|
||||
|
||||
/* Set up the Bus for the DTTs */
|
||||
buf = (unsigned char *) getenv("dtt_bus");
|
||||
if (buf != NULL)
|
||||
dev = i2c_mux_ident_muxstring(buf);
|
||||
if (dev == NULL) {
|
||||
printf("Error couldn't add Bus for DTT\n");
|
||||
printf("please setup dtt_bus to where your\n");
|
||||
printf("DTT is found.\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SUVD3)
|
||||
const uint upma_table[] = {
|
||||
0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
|
||||
0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
|
||||
0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
|
||||
0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
|
||||
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
struct km_bec_fpga *base =
|
||||
(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
|
||||
#if defined(CONFIG_SUVD3)
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
fsl_lbc_t *lbc = &immap->im_lbc;
|
||||
u32 *mxmr = &lbc->mamr;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC8360)
|
||||
unsigned short svid;
|
||||
/*
|
||||
* Because of errata in the UCCs, we have to write to the reserved
|
||||
* registers to slow the clocks down.
|
||||
*/
|
||||
svid = SVR_REV(mfspr(SVR));
|
||||
switch (svid) {
|
||||
case 0x0020:
|
||||
/*
|
||||
* MPC8360ECE.pdf QE_ENET10 table 4:
|
||||
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
|
||||
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
|
||||
*/
|
||||
setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
|
||||
break;
|
||||
case 0x0021:
|
||||
/*
|
||||
* MPC8360ECE.pdf QE_ENET10 table 4:
|
||||
* IMMR + 0x14AC[24:27] = 1010
|
||||
*/
|
||||
clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
|
||||
0x00000050, 0x000000a0);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* enable the PHY on the PIGGY */
|
||||
setbits_8(&base->pgy_eth, 0x01);
|
||||
/* enable the Unit LED (green) */
|
||||
setbits_8(&base->oprth, WRL_BOOT);
|
||||
/* enable Application Buffer */
|
||||
setbits_8(&base->oprtl, OPRTL_XBUFENA);
|
||||
|
||||
#if defined(CONFIG_SUVD3)
|
||||
/* configure UPMA for APP1 */
|
||||
upmconfig(UPMA, (uint *) upma_table,
|
||||
sizeof(upma_table) / sizeof(uint));
|
||||
out_be32(mxmr, CONFIG_SYS_MAMR);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
/* add board specific i2c busses */
|
||||
board_init_i2c_busses();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
#if defined(CONFIG_KMCOGE5NE)
|
||||
struct bfticu_iomap *base =
|
||||
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
|
||||
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
|
||||
|
||||
if (dip_switch != 0) {
|
||||
/* start bootloader */
|
||||
puts("DIP: Enabled\n");
|
||||
setenv("actual_bank", "0");
|
||||
}
|
||||
#endif
|
||||
set_km_env();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fixed_sdram(void)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = 0;
|
||||
u32 ddr_size;
|
||||
u32 ddr_size_log2;
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
|
||||
out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
|
||||
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
|
||||
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
|
||||
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
||||
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
|
||||
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
|
||||
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
||||
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
|
||||
udelay(200);
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
|
||||
msize = CONFIG_SYS_DDR_SIZE << 20;
|
||||
disable_addr_trans();
|
||||
msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
|
||||
enable_addr_trans();
|
||||
msize /= (1024 * 1024);
|
||||
if (CONFIG_SYS_DDR_SIZE != msize) {
|
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0;
|
||||
(ddr_size > 1);
|
||||
ddr_size = ddr_size >> 1, ddr_size_log2++)
|
||||
if (ddr_size & 1)
|
||||
return -1;
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar,
|
||||
(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
|
||||
out_be32(&im->ddr.csbnds[0].csbnds,
|
||||
(((msize / 16) - 1) & 0xff));
|
||||
}
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = 0;
|
||||
|
||||
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
|
||||
msize = fixed_sdram();
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
/*
|
||||
* Initialize DDR ECC byte
|
||||
*/
|
||||
ddr_enable_ecc(msize * 1024 * 1024);
|
||||
#endif
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return msize * 1024 * 1024;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
|
||||
|
||||
if (ethernet_present())
|
||||
puts(" with PIGGY.");
|
||||
puts("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HUSH_INIT_VAR)
|
||||
int hush_init_var(void)
|
||||
{
|
||||
ivm_read_eeprom();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
int testpin = 0;
|
||||
struct km_bec_fpga *base =
|
||||
(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
|
||||
int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
|
||||
testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
|
||||
debug("post_hotkeys_pressed: %d\n", !testpin);
|
||||
return testpin;
|
||||
}
|
||||
|
||||
ulong post_word_load(void)
|
||||
{
|
||||
void* addr = (ulong *) (CPM_POST_WORD_ADDR);
|
||||
debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
|
||||
return in_le32(addr);
|
||||
|
||||
}
|
||||
void post_word_store(ulong value)
|
||||
{
|
||||
void* addr = (ulong *) (CPM_POST_WORD_ADDR);
|
||||
debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
|
||||
out_le32(addr, value);
|
||||
}
|
||||
|
||||
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
||||
{
|
||||
*vstart = CONFIG_SYS_MEMTEST_START;
|
||||
*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
|
||||
debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/ctype.h>
|
||||
#include "../common/common.h"
|
||||
|
||||
static void i2c_write_start_seq(void)
|
||||
{
|
||||
struct fsl_i2c *dev;
|
||||
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
out_8(&dev->cr, (I2C_CR_MEN));
|
||||
}
|
||||
|
||||
int i2c_make_abort(void)
|
||||
{
|
||||
struct fsl_i2c *dev;
|
||||
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
|
||||
uchar last;
|
||||
int nbr_read = 0;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
/* wait after each operation to finsh with a delay */
|
||||
out_8(&dev->cr, (I2C_CR_MSTA));
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
in_8(&dev->dr);
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
last = in_8(&dev->dr);
|
||||
nbr_read++;
|
||||
|
||||
/*
|
||||
* do read until the last bit is 1, but stop if the full eeprom is
|
||||
* read.
|
||||
*/
|
||||
while (((last & 0x01) != 0x01) &&
|
||||
(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
last = in_8(&dev->dr);
|
||||
nbr_read++;
|
||||
}
|
||||
if ((last & 0x01) != 0x01)
|
||||
ret = -2;
|
||||
if ((last != 0xff) || (nbr_read > 1))
|
||||
printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
|
||||
nbr_read, last);
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
out_8(&dev->cr, (I2C_CR_MEN));
|
||||
udelay(DELAY_ABORT_SEQ);
|
||||
/* clear status reg */
|
||||
out_8(&dev->sr, 0);
|
||||
|
||||
for (i = 0; i < 5; i++)
|
||||
i2c_write_start_seq();
|
||||
if (ret != 0)
|
||||
printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
|
||||
nbr_read, last);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
|
||||
|
||||
ifdef CONFIG_KM_FPGA_CONFIG
|
||||
COBJS += fpga_config.o
|
||||
endif
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/errno.h>
|
||||
|
||||
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
|
||||
#define KM_XLX_PROGRAM_B_PIN 39
|
||||
|
||||
#define BOCO_ADDR 0x10
|
||||
|
||||
#define ID_REG 0x00
|
||||
#define BOCO2_ID 0x5b
|
||||
|
||||
static int check_boco2(void)
|
||||
{
|
||||
int ret;
|
||||
u8 id;
|
||||
|
||||
ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
|
||||
if (ret) {
|
||||
printf("%s: error reading the BOCO id !!\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return (id == BOCO2_ID);
|
||||
}
|
||||
|
||||
static int boco_clear_bits(u8 reg, u8 flags)
|
||||
{
|
||||
int ret;
|
||||
u8 regval;
|
||||
|
||||
/* give access to the EEPROM from FPGA */
|
||||
ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
|
||||
if (ret) {
|
||||
printf("%s: error reading the BOCO @%#x !!\n",
|
||||
__func__, reg);
|
||||
return ret;
|
||||
}
|
||||
regval &= ~flags;
|
||||
ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
|
||||
if (ret) {
|
||||
printf("%s: error writing the BOCO @%#x !!\n",
|
||||
__func__, reg);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int boco_set_bits(u8 reg, u8 flags)
|
||||
{
|
||||
int ret;
|
||||
u8 regval;
|
||||
|
||||
/* give access to the EEPROM from FPGA */
|
||||
ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
|
||||
if (ret) {
|
||||
printf("%s: error reading the BOCO @%#x !!\n",
|
||||
__func__, reg);
|
||||
return ret;
|
||||
}
|
||||
regval |= flags;
|
||||
ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
|
||||
if (ret) {
|
||||
printf("%s: error writing the BOCO @%#x !!\n",
|
||||
__func__, reg);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define SPI_REG 0x06
|
||||
#define CFG_EEPROM 0x02
|
||||
#define FPGA_PROG 0x04
|
||||
#define FPGA_INIT_B 0x10
|
||||
#define FPGA_DONE 0x20
|
||||
|
||||
static int fpga_done(void)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 regval;
|
||||
|
||||
/* this is only supported with the boco2 design */
|
||||
if (!check_boco2())
|
||||
return 0;
|
||||
|
||||
ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
|
||||
if (ret) {
|
||||
printf("%s: error reading the BOCO @%#x !!\n",
|
||||
__func__, SPI_REG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return regval & FPGA_DONE ? 1 : 0;
|
||||
}
|
||||
|
||||
int skip;
|
||||
|
||||
int trigger_fpga_config(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* if the FPGA is already configured, we do not want to
|
||||
* reconfigure it */
|
||||
skip = 0;
|
||||
if (fpga_done()) {
|
||||
printf("PCIe FPGA config: skipped\n");
|
||||
skip = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (check_boco2()) {
|
||||
/* we have a BOCO2, this has to be triggered here */
|
||||
|
||||
/* make sure the FPGA_can access the EEPROM */
|
||||
ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* trigger the config start */
|
||||
ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* small delay for the pulse */
|
||||
udelay(10);
|
||||
|
||||
/* up signal for pulse end */
|
||||
ret = boco_set_bits(SPI_REG, FPGA_PROG);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* finally, raise INIT_B to remove the config delay */
|
||||
ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
} else {
|
||||
/* we do it the old way, with the gpio pin */
|
||||
kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
|
||||
kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
|
||||
/* small delay for the pulse */
|
||||
udelay(10);
|
||||
kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wait_for_fpga_config(void)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 spictrl;
|
||||
u32 timeout = 20000;
|
||||
|
||||
if (skip)
|
||||
return 0;
|
||||
|
||||
if (!check_boco2()) {
|
||||
/* we do not have BOCO2, this is not really used */
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("PCIe FPGA config:");
|
||||
do {
|
||||
ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
|
||||
if (ret) {
|
||||
printf("%s: error reading the BOCO spictrl !!\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
if (timeout-- == 0) {
|
||||
printf(" FPGA_DONE timeout\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
udelay(10);
|
||||
} while (!(spictrl & FPGA_DONE));
|
||||
|
||||
printf(" done\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PRST1 0x4
|
||||
#define PCIE_RST 0x10
|
||||
#define TRAFFIC_RST 0x04
|
||||
|
||||
int fpga_reset(void)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 resets;
|
||||
|
||||
if (!check_boco2()) {
|
||||
/* we do not have BOCO2, this is not really used */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* if we have skipped, we only want to reset the PCIe part */
|
||||
resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
|
||||
|
||||
ret = boco_clear_bits(PRST1, resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* small delay for the pulse */
|
||||
udelay(10);
|
||||
|
||||
ret = boco_set_bits(PRST1, resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
|
||||
* is available from the Bobcat SPI bus */
|
||||
int toggle_eeprom_spi_bus(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!check_boco2()) {
|
||||
/* we do not have BOCO2, this is not really used */
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = boco_set_bits(SPI_REG, CFG_EEPROM);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,530 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <nand.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <spi.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* BOCO FPGA definitions
|
||||
*/
|
||||
#define BOCO 0x10
|
||||
#define REG_CTRL_H 0x02
|
||||
#define MASK_WRL_UNITRUN 0x01
|
||||
#define MASK_RBX_PGY_PRESENT 0x40
|
||||
#define REG_IRQ_CIRQ2 0x2d
|
||||
#define MASK_RBI_DEFECT_16 0x01
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_PEX_RST_OUTn,
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
MPP8_GPIO, /* SDA */
|
||||
MPP9_GPIO, /* SCL */
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
#endif
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO, /* Reserved */
|
||||
MPP13_UART1_TXD,
|
||||
MPP14_UART1_RXD,
|
||||
MPP15_GPIO, /* Not used */
|
||||
MPP16_GPIO, /* Not used */
|
||||
MPP17_GPIO, /* Reserved */
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GPIO,
|
||||
MPP21_GPIO,
|
||||
MPP22_GPIO,
|
||||
MPP23_GPIO,
|
||||
MPP24_GPIO,
|
||||
MPP25_GPIO,
|
||||
MPP26_GPIO,
|
||||
MPP27_GPIO,
|
||||
MPP28_GPIO,
|
||||
MPP29_GPIO,
|
||||
MPP30_GPIO,
|
||||
MPP31_GPIO,
|
||||
MPP32_GPIO,
|
||||
MPP33_GPIO,
|
||||
MPP34_GPIO, /* CDL1 (input) */
|
||||
MPP35_GPIO, /* CDL2 (input) */
|
||||
MPP36_GPIO, /* MAIN_IRQ (input) */
|
||||
MPP37_GPIO, /* BOARD_LED */
|
||||
MPP38_GPIO, /* Piggy3 LED[1] */
|
||||
MPP39_GPIO, /* Piggy3 LED[2] */
|
||||
MPP40_GPIO, /* Piggy3 LED[3] */
|
||||
MPP41_GPIO, /* Piggy3 LED[4] */
|
||||
MPP42_GPIO, /* Piggy3 LED[5] */
|
||||
MPP43_GPIO, /* Piggy3 LED[6] */
|
||||
MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
|
||||
MPP45_GPIO, /* Piggy3 LED[8] */
|
||||
MPP46_GPIO, /* Reserved */
|
||||
MPP47_GPIO, /* Reserved */
|
||||
MPP48_GPIO, /* Reserved */
|
||||
MPP49_GPIO, /* SW_INTOUTn */
|
||||
0
|
||||
};
|
||||
|
||||
#if defined(CONFIG_KM_MGCOGE3UN)
|
||||
/*
|
||||
* Wait for startup OK from mgcoge3ne
|
||||
*/
|
||||
int startup_allowed(void)
|
||||
{
|
||||
unsigned char buf;
|
||||
|
||||
/*
|
||||
* Read CIRQ16 bit (bit 0)
|
||||
*/
|
||||
if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
|
||||
printf("%s: Error reading Boco\n", __func__);
|
||||
else
|
||||
if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
|
||||
/*
|
||||
* All boards with PIGGY4 connected via a simple switch have ethernet always
|
||||
* present.
|
||||
*/
|
||||
int ethernet_present(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#else
|
||||
int ethernet_present(void)
|
||||
{
|
||||
uchar buf;
|
||||
int ret = 0;
|
||||
|
||||
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
||||
printf("%s: Error reading Boco\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
|
||||
ret = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
int initialize_unit_leds(void)
|
||||
{
|
||||
/*
|
||||
* Init the unit LEDs per default they all are
|
||||
* ok apart from bootstat
|
||||
*/
|
||||
uchar buf;
|
||||
|
||||
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
||||
printf("%s: Error reading Boco\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
buf |= MASK_WRL_UNITRUN;
|
||||
if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
|
||||
printf("%s: Error writing Boco\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
void set_bootcount_addr(void)
|
||||
{
|
||||
uchar buf[32];
|
||||
unsigned int bootcountaddr;
|
||||
bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
|
||||
sprintf((char *)buf, "0x%x", bootcountaddr);
|
||||
setenv("bootcountaddr", (char *)buf);
|
||||
}
|
||||
#endif
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *str;
|
||||
int mach_type;
|
||||
|
||||
str = getenv("mach_type");
|
||||
if (str != NULL) {
|
||||
mach_type = simple_strtoul(str, NULL, 10);
|
||||
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
|
||||
gd->bd->bi_arch_number = mach_type;
|
||||
}
|
||||
#if defined(CONFIG_KM_MGCOGE3UN)
|
||||
char *wait_for_ne;
|
||||
wait_for_ne = getenv("waitforne");
|
||||
if (wait_for_ne != NULL) {
|
||||
if (strcmp(wait_for_ne, "true") == 0) {
|
||||
int cnt = 0;
|
||||
int abort = 0;
|
||||
puts("NE go: ");
|
||||
while (startup_allowed() == 0) {
|
||||
if (tstc()) {
|
||||
(void) getc(); /* consume input */
|
||||
abort = 1;
|
||||
break;
|
||||
}
|
||||
udelay(200000);
|
||||
cnt++;
|
||||
if (cnt == 5)
|
||||
puts("wait\b\b\b\b");
|
||||
if (cnt == 10) {
|
||||
cnt = 0;
|
||||
puts(" \b\b\b\b");
|
||||
}
|
||||
}
|
||||
if (abort == 1)
|
||||
printf("\nAbort waiting for ne\n");
|
||||
else
|
||||
puts("OK\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
initialize_unit_leds();
|
||||
set_km_env();
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
set_bootcount_addr();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
u32 tmp;
|
||||
|
||||
/* set the 2 bitbang i2c pins as output gpios */
|
||||
tmp = readl(KW_GPIO0_BASE + 4);
|
||||
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
|
||||
#endif
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
/*
|
||||
* The KM_FLASH_GPIO_PIN switches between using a
|
||||
* NAND or a SPI FLASH. Set this pin on start
|
||||
* to NAND mode.
|
||||
*/
|
||||
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
|
||||
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
/*
|
||||
* Reinit the GPIO for I2C Bitbang driver so that the now
|
||||
* available gpio framework is consistent. The calls to
|
||||
* direction output in are not necessary, they are already done in
|
||||
* board_early_init_f
|
||||
*/
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
|
||||
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KM_FPGA_CONFIG)
|
||||
trigger_fpga_config();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#if defined(CONFIG_KMCOGE5UN)
|
||||
/* I/O pin to erase flash RGPP09 = MPP43 */
|
||||
#define KM_FLASH_ERASE_ENABLE 43
|
||||
u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
|
||||
|
||||
/* if pin 1 do full erase */
|
||||
if (dip_switch != 0) {
|
||||
/* start bootloader */
|
||||
puts("DIP: Enabled\n");
|
||||
setenv("actual_bank", "0");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KM_FPGA_CONFIG)
|
||||
wait_for_fpga_config();
|
||||
fpga_reset();
|
||||
toggle_eeprom_spi_bus();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
/* Fix this */
|
||||
gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
|
||||
kw_sdram_bs(0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
|
||||
gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
|
||||
kw_sdram_bs(i));
|
||||
}
|
||||
}
|
||||
|
||||
#if (defined(CONFIG_KM_PIGGY4_88E6061))
|
||||
|
||||
#define PHY_LED_SEL_REG 0x18
|
||||
#define PHY_LED0_LINK (0x5)
|
||||
#define PHY_LED1_ACT (0x8<<4)
|
||||
#define PHY_LED2_INT (0xe<<8)
|
||||
#define PHY_SPEC_CTRL_REG 0x1c
|
||||
#define PHY_RGMII_CLK_STABLE (0x1<<10)
|
||||
#define PHY_CLSA (0x1<<1)
|
||||
|
||||
/* Configure and enable MV88E3018 PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
char *name = "egiga0";
|
||||
unsigned short reg;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* RGMII clk transition on data stable */
|
||||
if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
|
||||
printf("Error reading PHY spec ctrl reg\n");
|
||||
if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
|
||||
reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
|
||||
printf("Error writing PHY spec ctrl reg\n");
|
||||
|
||||
/* leds setup */
|
||||
if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
|
||||
PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
|
||||
printf("Error writing PHY LED reg\n");
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
|
||||
}
|
||||
#else
|
||||
/* Configure and enable MV88E1118 PHY on the piggy*/
|
||||
void reset_phy(void)
|
||||
{
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_HUSH_INIT_VAR)
|
||||
int hush_init_var(void)
|
||||
{
|
||||
ivm_read_eeprom();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
const ulong patterns[] = { 0x00000000,
|
||||
0xFFFFFFFF,
|
||||
0xFF00FF00,
|
||||
0x0F0F0F0F,
|
||||
0xF0F0F0F0};
|
||||
const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
|
||||
const ulong OFFS_PATTERN = 3;
|
||||
const ulong REPEAT_PATTERN = 1000;
|
||||
|
||||
void bootcount_store(ulong a)
|
||||
{
|
||||
ulong *save_addr;
|
||||
ulong size = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
size += gd->bd->bi_dram[i].size;
|
||||
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
|
||||
writel(a, save_addr);
|
||||
writel(BOOTCOUNT_MAGIC, &save_addr[1]);
|
||||
|
||||
for (i = 0; i < REPEAT_PATTERN; i++)
|
||||
writel(patterns[i % NBR_OF_PATTERNS],
|
||||
&save_addr[i+OFFS_PATTERN]);
|
||||
|
||||
}
|
||||
|
||||
ulong bootcount_load(void)
|
||||
{
|
||||
ulong *save_addr;
|
||||
ulong size = 0;
|
||||
ulong counter = 0;
|
||||
int i, tmp;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
size += gd->bd->bi_dram[i].size;
|
||||
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
|
||||
|
||||
counter = readl(&save_addr[0]);
|
||||
|
||||
/* Is the counter reliable, check in the big pattern for bit errors */
|
||||
for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
|
||||
tmp = readl(&save_addr[i+OFFS_PATTERN]);
|
||||
if (tmp != patterns[i % NBR_OF_PATTERNS])
|
||||
counter = 0;
|
||||
}
|
||||
return counter;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
void set_sda(int state)
|
||||
{
|
||||
I2C_ACTIVE;
|
||||
I2C_SDA(state);
|
||||
}
|
||||
|
||||
void set_scl(int state)
|
||||
{
|
||||
I2C_SCL(state);
|
||||
}
|
||||
|
||||
int get_sda(void)
|
||||
{
|
||||
I2C_TRISTATE;
|
||||
return I2C_READ;
|
||||
}
|
||||
|
||||
int get_scl(void)
|
||||
{
|
||||
return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
|
||||
#define KM_POST_EN_L 44
|
||||
#define POST_WORD_OFF 8
|
||||
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
#if defined(CONFIG_KM_COGE5UN)
|
||||
return kw_gpio_get_value(KM_POST_EN_L);
|
||||
#else
|
||||
return !kw_gpio_get_value(KM_POST_EN_L);
|
||||
#endif
|
||||
}
|
||||
|
||||
ulong post_word_load(void)
|
||||
{
|
||||
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
||||
return in_le32(addr);
|
||||
|
||||
}
|
||||
void post_word_store(ulong value)
|
||||
{
|
||||
void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
|
||||
out_le32(addr, value);
|
||||
}
|
||||
|
||||
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
||||
{
|
||||
*vstart = CONFIG_SYS_SDRAM_BASE;
|
||||
|
||||
/* we go up to relocation plus a 1 MB margin */
|
||||
*size = CONFIG_SYS_TEXT_BASE - (1<<20);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||
{
|
||||
kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
|
||||
|
||||
return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011
|
||||
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: MPPSel0 2, NF_IO[2]
|
||||
# bit 7-4: MPPSel1 2, NF_IO[3]
|
||||
# bit 12-8: MPPSel2 2, NF_IO[4]
|
||||
# bit 15-12: MPPSel3 2, NF_IO[5]
|
||||
# bit 19-16: MPPSel4 1, NF_IO[6]
|
||||
# bit 23-20: MPPSel5 1, NF_IO[7]
|
||||
# bit 27-24: MPPSel6 1, SYSRST_O
|
||||
# bit 31-28: MPPSel7 0, GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: MPPSel16 0, GPIO[16]
|
||||
# bit 7-4: MPPSel17 0, GPIO[17]
|
||||
# bit 12-8: MPPSel18 1, NF_IO[0]
|
||||
# bit 15-12: MPPSel19 1, NF_IO[1]
|
||||
# bit 19-16: MPPSel20 0, GPIO[20]
|
||||
# bit 23-20: MPPSel21 0, GPIO[21]
|
||||
# bit 27-24: MPPSel22 0, GPIO[22]
|
||||
# bit 31-28: MPPSel23 0, GPIO[23]
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
|
||||
#Dram initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit13-0: 0x4E0 (DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0 reserved
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x00000001 # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x16
|
||||
# bit3-2: 00, Cs0size=2Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd disabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 0, DDR ODT control msb disabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add a sample stage
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit3-0 : 0000, required
|
||||
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
|
||||
# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
|
||||
# bit15-12: 0100, internal ODT assertion 4 cycles after read
|
||||
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
|
||||
# bit31-20: 0 , required
|
||||
|
||||
DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
|
||||
# bit3-0 : 0001, M_ODT assertion same cycle as write
|
||||
# bit7-4 : 0101, M_ODT de-assertion x cycles after write
|
||||
# bit11-8 : 0100, internal ODT assertion x cycles after write
|
||||
# bit15-12: 1000, internal ODT de-assertion x cycles after write
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 00, ODT1 controlled by register
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
|
||||
# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
|
||||
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
|
||||
# bit14 :1, STARTBURST ODT enabled
|
||||
# bit15 :1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: MPPSel0 2, NF_IO[2]
|
||||
# bit 7-4: MPPSel1 2, NF_IO[3]
|
||||
# bit 12-8: MPPSel2 2, NF_IO[4]
|
||||
# bit 15-12: MPPSel3 2, NF_IO[5]
|
||||
# bit 19-16: MPPSel4 1, NF_IO[6]
|
||||
# bit 23-20: MPPSel5 1, NF_IO[7]
|
||||
# bit 27-24: MPPSel6 1, SYSRST_O
|
||||
# bit 31-28: MPPSel7 0, GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: MPPSel16 0, GPIO[16]
|
||||
# bit 7-4: MPPSel17 0, GPIO[17]
|
||||
# bit 12-8: MPPSel18 1, NF_IO[0]
|
||||
# bit 15-12: MPPSel19 1, NF_IO[1]
|
||||
# bit 19-16: MPPSel20 0, GPIO[20]
|
||||
# bit 23-20: MPPSel21 0, GPIO[21]
|
||||
# bit 27-24: MPPSel22 0, GPIO[22]
|
||||
# bit 31-28: MPPSel23 0, GPIO[23]
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
|
||||
#Dram initalization
|
||||
DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
|
||||
# bit13-0: 0x400 (DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0 reserved
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000000D # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x16
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
DATA 0xFFD01420 0x00000044 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 1, DDR ODT control lsd disabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 0 , no sample stage
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
DATA 0xFFD01428 0x00074510
|
||||
DATA 0xFFD0147c 0x00007451
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
|
||||
# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 00, ODT1 controlled by register
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
|
||||
# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit9-8: 1, ODTEn, never active
|
||||
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
#
|
||||
# (C) Copyright 2010
|
||||
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
#
|
||||
# (C) Copyright 2012
|
||||
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
|
||||
# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
|
||||
#
|
||||
# (C) Copyright 2012
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
|
||||
# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
|
||||
# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
|
||||
# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
|
||||
# bit 19-16: 1, MPPSel4 NF_IO[6]
|
||||
# bit 23-20: 1, MPPSel5 NF_IO[7]
|
||||
# bit 27-24: 1, MPPSel6 SYSRST_O
|
||||
# bit 31-28: 0, MPPSel7 GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
|
||||
# bit 3-0: 0, MPPSel8 GPIO[8]
|
||||
# bit 7-4: 0, MPPSel9 GPIO[9]
|
||||
# bit 12-8: 3, MPPSel10 UA0_TXD
|
||||
# bit 15-12: 3, MPPSel11 UA0_RXD
|
||||
# bit 19-16: 0, MPPSel12 not connected
|
||||
# bit 23-20: 3, MPPSel13 UA1_TXD
|
||||
# bit 27-24: 3, MPPSel14 UA1_RXD
|
||||
# bit 31-28: 0, MPPSel15 GPIO[15]
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: 0, MPPSel16 GPIO[16]
|
||||
# bit 7-4: 0, MPPSel17 not connected
|
||||
# bit 12-8: 1, MPPSel18 NF_IO[0]
|
||||
# bit 15-12: 1, MPPSel19 NF_IO[1]
|
||||
# bit 19-16: 0, MPPSel20 GPIO[20]
|
||||
# bit 23-20: 0, MPPSel21 GPIO[21]
|
||||
# bit 27-24: 0, MPPSel22 GPIO[22]
|
||||
# bit 31-28: 0, MPPSel23 GPIO[23]
|
||||
|
||||
# MPP Control 3-6 Register untouched (MPP24-49)
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
# bit 2-0: 3, Reserved
|
||||
# bit 5-3: 3, Reserved
|
||||
# bit 6: 0, Reserved
|
||||
# bit 7: 0, RGMII-pads voltage = 3.3V
|
||||
# bit 10-8: 3, Reserved
|
||||
# bit 13-11: 3, Reserved
|
||||
# bit 14: 0, Reserved
|
||||
# bit 15: 0, MPP RGMII-pads voltage = 3.3V
|
||||
# bit 31-16 0x1B1B, Reserved
|
||||
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
# bit 0-1: 2, Tag RAM RTC RAM0
|
||||
# bit 3-2: 1, Tag RAM WTC RAM0
|
||||
# bit 7-4: 6, Reserve
|
||||
# bit 9-8: 2, Valid RAM RTC RAM
|
||||
# bit 11-10: 1, Valid RAM WTC RAM
|
||||
# bit 13-12: 2, Dirty RAM RTC RAM
|
||||
# bit 15-14: 1, Dirty RAM WTC RAM
|
||||
# bit 17-16: 2, Data RAM RTC RAM0
|
||||
# bit 19-18: 1, Data RAM WTC RAM0
|
||||
# bit 21-20: 2, Data RAM RTC RAM1
|
||||
# bit 23-22: 1, Data RAM WTC RAM1
|
||||
# bit 25-24: 2, Data RAM RTC RAM2
|
||||
# bit 27-26: 1, Data RAM WTC RAM2
|
||||
# bit 29-28: 2, Data RAM RTC RAM3
|
||||
# bit 31-30: 1, Data RAM WTC RAM4
|
||||
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
# bit 15-0: ???, Reserve
|
||||
# bit 17-16: 2, ECC RAM RTC RAM0
|
||||
# bit 19-18: 1, ECC RAM WTC RAM0
|
||||
# bit 31-20: ???,Reserve
|
||||
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
# bit 23-0: 0x000200, Addr Config tuning
|
||||
# bit 31-24: 0, Reserved
|
||||
|
||||
# ??? Missing register # CPU RAM Management Control2 Register
|
||||
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
# bit 15-0: 0x1C00, Opmux Tuning
|
||||
# bit 31-16: 0, Pc Dp Tuning
|
||||
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
# bit 1-0: 1, addr clk tune
|
||||
# bit 3-2: 0, reserved
|
||||
# bit 5-4: 0, dtcmp clk tune
|
||||
# bit 7-6: 0, reserved
|
||||
# bit 9-8: 0, macdrv clk tune
|
||||
# bit 11-10: 0, opmuxgm2 clk tune
|
||||
# bit 15-14: 0, rf clk tune
|
||||
# bit 17-16: 0, rfbypass clk tune
|
||||
# bit 19-18: 0, pc dp clk tune
|
||||
# bit 23-20: 0, icache clk tune
|
||||
# bit 27:24: 0, dcache clk tune
|
||||
# bit 31:28: 0, regfile tunin
|
||||
|
||||
# SDRAM initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit 13-0: 0x4E0, DDR2 clks refresh rate
|
||||
# bit 14: 0, reserved
|
||||
# bit 15: 0, reserved
|
||||
# bit 16: 0, CPU to Dram Write buffer policy
|
||||
# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
|
||||
# bit 19-18: 0, reserved
|
||||
# bit 23-20: 0, reserved
|
||||
# bit 24: 1, enable exit self refresh mode on DDR access
|
||||
# bit 25: 1, required
|
||||
# bit 29-26: 0, reserved
|
||||
# bit 31-30: 1, reserved
|
||||
|
||||
DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0, reserved
|
||||
# bit 4: 0, 2T mode =addr/cmd in same cycle
|
||||
# bit 5: 0, clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0, use recommended falling edge of clk for addr/cmd
|
||||
# bit 7-11: 0, reserved
|
||||
# bit 12-13: 1, reserved, required 1
|
||||
# bit 14: 0, input buffer always powered up
|
||||
# bit 17-15: 0, reserved
|
||||
# bit 18: 1, cpu lock transaction enabled
|
||||
# bit 19: 0, reserved
|
||||
# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
|
||||
# bit 30-28: 3, required
|
||||
# bit 31: 0,no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
|
||||
# bit 3-0: 0xE, TRAS, 15 clk (45 ns)
|
||||
# bit 7-4: 0x4, TRCD, 5 clk (15 ns)
|
||||
# bit 11-8: 0x4, TRP, 5 clk (15 ns)
|
||||
# bit 15-12: 0x4, TWR, 5 clk (15 ns)
|
||||
# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
|
||||
# bit 20: 0, extended TRAS msb
|
||||
# bit 23-21: 0, reserved
|
||||
# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
|
||||
# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
|
||||
|
||||
DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
|
||||
# bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
|
||||
# bit 8-7: 0, TR2R
|
||||
# bit 10-9: 0, TR2W
|
||||
# bit 12-11: 0, TW2W
|
||||
# bit 31-13: 0, reserved
|
||||
|
||||
DATA 0xFFD01410 0x00000001 # DDR Address Control
|
||||
# bit 1-0: 1, Cs0width=x16
|
||||
# bit 3-2: 0, Cs0size=2Gb
|
||||
# bit 5-4: 0, Cs1width=nonexistent
|
||||
# bit 7-6: 0, Cs1size =nonexistent
|
||||
# bit 9-8: 0, Cs2width=nonexistent
|
||||
# bit 11-10: 0, Cs2size =nonexistent
|
||||
# bit 13-12: 0, Cs3width=nonexistent
|
||||
# bit 15-14: 0, Cs3size =nonexistent
|
||||
# bit 16: 0, Cs0AddrSel
|
||||
# bit 17: 0, Cs1AddrSel
|
||||
# bit 18: 0, Cs2AddrSel
|
||||
# bit 19: 0, Cs3AddrSel
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit 0: 0, OpenPage enabled
|
||||
# bit 31-1: 0, required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit 3-0: 0, DDR cmd
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
# bit 2-0: 2, Burst Length = 4
|
||||
# bit 3: 0, Burst Type
|
||||
# bit 6-4: 5, CAS Latency = 5
|
||||
# bit 7: 0, Test mode
|
||||
# bit 8: 0, DLL Reset
|
||||
# bit 11-9: 3, Write recovery for auto-precharge must be 3
|
||||
# bit 12: 0, Active power down exit time, fast exit
|
||||
# bit 14-13: 0, reserved
|
||||
# bit 31-15: 0, reserved
|
||||
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit 0: 0, DDR DLL enabled
|
||||
# bit 1: 1, DDR drive strength reduced
|
||||
# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
|
||||
# bit 5-3: 0, required
|
||||
# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
|
||||
# bit 9-7: 0, required
|
||||
# bit 10: 0, differential DQS enabled
|
||||
# bit 11: 0, required
|
||||
# bit 12: 0, DDR output buffer enabled
|
||||
# bit 31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit 2-0: 7, required
|
||||
# bit 3: 1, MBUS Burst Chop disabled
|
||||
# bit 6-4: 7, required
|
||||
# bit 7: 0, reserved
|
||||
# bit 8: 1, add sample stage required for f > 266 MHz
|
||||
# bit 9: 0, no half clock cycle addition to dataout
|
||||
# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit 15-12:0xf, required
|
||||
# bit 31-16: 0, required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit 3-0: 0, required
|
||||
# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
|
||||
# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
|
||||
# (ODT turn off delay 2,5 clk cycles)
|
||||
# bit 15-12: 4, internal ODT time based on bit 7-4
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
|
||||
# bit 3-0: 2, M_ODT assertion same as bit 11-8
|
||||
# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
|
||||
# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
# bit 23-0: 0, reserved
|
||||
# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
|
||||
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit 0: 1, Window enabled
|
||||
# bit 1: 0, Write Protect disabled
|
||||
# bit 3-2: 0, CS0 hit selected
|
||||
# bit 23-4:ones, required
|
||||
# bit 31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
|
||||
# bit 11-8: 0, required
|
||||
# big 15-11: 0, required
|
||||
# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
|
||||
# bit 27-24: 0, required
|
||||
# bit 31-28: 0, required
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
|
||||
# bit 3-2: 0, ODT1 controlled by register
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
|
||||
# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
|
||||
# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
|
||||
# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
|
||||
# bit 14: 1, STARTBURST ODT enabled
|
||||
# bit 15: 1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit 0: 1, enable DDR init upon this register write
|
||||
# bit 31-1: 0, reserved
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
#
|
||||
# (C) Copyright 2012
|
||||
# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
|
||||
# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
|
||||
# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
# This configuration applies to COGE5 design (ARM-part)
|
||||
# Two 8-Bit devices are connected on the 16-Bit bus on the same
|
||||
# chip-select. The supported devices are
|
||||
# MT47H256M8EB-3IT:C
|
||||
# MT47H256M8EB-25EIT:C
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
|
||||
# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
|
||||
# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
|
||||
# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
|
||||
# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
|
||||
# bit 19-16: 1, MPPSel4 NF_IO[6]
|
||||
# bit 23-20: 1, MPPSel5 NF_IO[7]
|
||||
# bit 27-24: 1, MPPSel6 SYSRST_O
|
||||
# bit 31-28: 0, MPPSel7 GPO[7]
|
||||
|
||||
DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
|
||||
# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
|
||||
# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
|
||||
# bit 12-8: 3, MPPSel10 UA0_TXD
|
||||
# bit 15-12: 3, MPPSel11 UA0_RXD
|
||||
# bit 19-16: 0, MPPSel12 not connected
|
||||
# bit 23-20: 3, MPPSel13 GPIO[14]
|
||||
# bit 27-24: 3, MPPSel14 GPIO[15]
|
||||
# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
|
||||
|
||||
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
|
||||
# bit 3-0: 0, MPPSel16 GPIO[16]
|
||||
# bit 7-4: 0, MPPSel17 not connected
|
||||
# bit 11-8: 1, MPPSel18 NF_IO[0]
|
||||
# bit 15-12: 1, MPPSel19 NF_IO[1]
|
||||
# bit 19-16: 0, MPPSel20 GPIO[20]
|
||||
# bit 23-20: 0, MPPSel21 GPIO[21]
|
||||
# bit 27-24: 0, MPPSel22 GPIO[22]
|
||||
# bit 31-28: 0, MPPSel23 GPIO[23]
|
||||
|
||||
# MPP Control 3-6 Register untouched (MPP24-49)
|
||||
|
||||
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
|
||||
# bit 2-0: 3, Reserved
|
||||
# bit 5-3: 3, Reserved
|
||||
# bit 6: 0, Reserved
|
||||
# bit 7: 0, RGMII-pads voltage = 3.3V
|
||||
# bit 10-8: 3, Reserved
|
||||
# bit 13-11: 3, Reserved
|
||||
# bit 14: 0, Reserved
|
||||
# bit 15: 0, MPP RGMII-pads voltage = 3.3V
|
||||
# bit 31-16 0x1B1B, Reserved
|
||||
|
||||
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
|
||||
# bit 0-1: 2, Tag RAM RTC RAM0
|
||||
# bit 3-2: 1, Tag RAM WTC RAM0
|
||||
# bit 7-4: 6, Reserved
|
||||
# bit 9-8: 2, Valid RAM RTC RAM
|
||||
# bit 11-10: 1, Valid RAM WTC RAM
|
||||
# bit 13-12: 2, Dirty RAM RTC RAM
|
||||
# bit 15-14: 1, Dirty RAM WTC RAM
|
||||
# bit 17-16: 2, Data RAM RTC RAM0
|
||||
# bit 19-18: 1, Data RAM WTC RAM0
|
||||
# bit 21-20: 2, Data RAM RTC RAM1
|
||||
# bit 23-22: 1, Data RAM WTC RAM1
|
||||
# bit 25-24: 2, Data RAM RTC RAM2
|
||||
# bit 27-26: 1, Data RAM WTC RAM2
|
||||
# bit 29-28: 2, Data RAM RTC RAM3
|
||||
# bit 31-30: 1, Data RAM WTC RAM4
|
||||
|
||||
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
|
||||
# bit 15-0: ?, Reserved
|
||||
# bit 17-16: 2, ECC RAM RTC RAM0
|
||||
# bit 19-18: 1, ECC RAM WTC RAM0
|
||||
# bit 31-20: ?,Reserved
|
||||
|
||||
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
|
||||
# bit 23-0: 0x000200, Addr Config tuning
|
||||
# bit 31-24: 0, Reserved
|
||||
|
||||
# ??? Missing register # CPU RAM Management Control2 Register
|
||||
|
||||
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
|
||||
# bit 15-0: 0x1C00, Opmux Tuning
|
||||
# bit 31-16: 0, Pc Dp Tuning
|
||||
|
||||
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
|
||||
# bit 1-0: 1, addr clk tune
|
||||
# bit 3-2: 0, reserved
|
||||
# bit 5-4: 0, dtcmp clk tune
|
||||
# bit 7-6: 0, reserved
|
||||
# bit 9-8: 0, macdrv clk tune
|
||||
# bit 11-10: 0, opmuxgm2 clk tune
|
||||
# bit 15-14: 0, rf clk tune
|
||||
# bit 17-16: 0, rfbypass clk tune
|
||||
# bit 19-18: 0, pc dp clk tune
|
||||
# bit 23-20: 0, icache clk tune
|
||||
# bit 27:24: 0, dcache clk tune
|
||||
# bit 31:28: 0, regfile tunin
|
||||
|
||||
# SDRAM initalization
|
||||
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
|
||||
# bit 13-0: 0x4E0, DDR2 clks refresh rate
|
||||
# bit 14: 0, reserved
|
||||
# bit 15: 0, reserved
|
||||
# bit 16: 0, CPU to Dram Write buffer policy
|
||||
# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
|
||||
# bit 19-18: 0, reserved
|
||||
# bit 23-20: 0, reserved
|
||||
# bit 24: 1, enable exit self refresh mode on DDR access
|
||||
# bit 25: 1, required
|
||||
# bit 29-26: 0, reserved
|
||||
# bit 31-30: 1, reserved
|
||||
|
||||
DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
|
||||
# bit 3-0: 0, reserved
|
||||
# bit 4: 0, 2T mode =addr/cmd in same cycle
|
||||
# bit 5: 0, clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0, use recommended falling edge of clk for addr/cmd
|
||||
# bit 7-11: 0, reserved
|
||||
# bit 12-13: 1, reserved, required 1
|
||||
# bit 14: 0, input buffer always powered up
|
||||
# bit 17-15: 0, reserved
|
||||
# bit 18: 1, cpu lock transaction enabled
|
||||
# bit 19: 0, reserved
|
||||
# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
|
||||
# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
|
||||
# bit 30-28: 3, required
|
||||
# bit 31: 0, no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
|
||||
# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
|
||||
# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
|
||||
# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
|
||||
# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
|
||||
# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
|
||||
# bit 20: 0, extended TRAS msb
|
||||
# bit 23-21: 0, reserved
|
||||
# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
|
||||
# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
|
||||
|
||||
DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
|
||||
# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
|
||||
# bit 8-7: 0, TR2R
|
||||
# bit 10-9: 0, TR2W
|
||||
# bit 12-11: 0, TW2W
|
||||
# bit 31-13: 0, reserved
|
||||
|
||||
DATA 0xFFD01410 0x00000000 # DDR Address Control
|
||||
# bit 1-0: 0, Cs0width=x8 (2 devices)
|
||||
# bit 3-2: 0, Cs0size=2Gb
|
||||
# bit 5-4: 0, Cs1width=nonexistent
|
||||
# bit 7-6: 0, Cs1size =nonexistent
|
||||
# bit 9-8: 0, Cs2width=nonexistent
|
||||
# bit 11-10: 0, Cs2size =nonexistent
|
||||
# bit 13-12: 0, Cs3width=nonexistent
|
||||
# bit 15-14: 0, Cs3size =nonexistent
|
||||
# bit 16: 0, Cs0AddrSel
|
||||
# bit 17: 0, Cs1AddrSel
|
||||
# bit 18: 0, Cs2AddrSel
|
||||
# bit 19: 0, Cs3AddrSel
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit 0: 0, OpenPage enabled
|
||||
# bit 31-1: 0, required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit 3-0: 0, DDR cmd
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0141C 0x00000652 # DDR Mode
|
||||
# bit 2-0: 2, Burst Length = 4
|
||||
# bit 3: 0, Burst Type
|
||||
# bit 6-4: 5, CAS Latency = 5
|
||||
# bit 7: 0, Test mode
|
||||
# bit 8: 0, DLL Reset
|
||||
# bit 11-9: 3, Write recovery for auto-precharge must be 3
|
||||
# bit 12: 0, Active power down exit time, fast exit
|
||||
# bit 14-13: 0, reserved
|
||||
# bit 31-15: 0, reserved
|
||||
|
||||
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
|
||||
# bit 0: 0, DDR DLL enabled
|
||||
# bit 1: 1, DDR drive strenght reduced
|
||||
# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
|
||||
# bit 5-3: 0, required
|
||||
# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
|
||||
# bit 9-7: 0, required
|
||||
# bit 10: 0, differential DQS enabled
|
||||
# bit 11: 0, required
|
||||
# bit 12: 0, DDR output buffer enabled
|
||||
# bit 31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit 2-0: 7, required
|
||||
# bit 3: 1, MBUS Burst Chop disabled
|
||||
# bit 6-4: 7, required
|
||||
# bit 7: 0, reserved
|
||||
# bit 8: 1, add sample stage required for > 266Mhz
|
||||
# bit 9: 0, no half clock cycle addition to dataout
|
||||
# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit 15-12:0xf, required
|
||||
# bit 31-16: 0, required
|
||||
|
||||
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
|
||||
# bit 3-0: 0, required
|
||||
# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
|
||||
# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
|
||||
# (ODT turn off delay 2,5 clk cycles)
|
||||
# bit 15-12: 4, internal ODT time based on bit 7-4
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 31-20: 0, required
|
||||
|
||||
DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
|
||||
# bit 3-0: 2, M_ODT assertion same as bit 11-8
|
||||
# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
|
||||
# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
|
||||
# with the considered SDRAM internal delay
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
# bit 23-0: 0, reserved
|
||||
# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
|
||||
|
||||
DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
|
||||
# bit 0: 1, Window enabled
|
||||
# bit 1: 0, Write Protect disabled
|
||||
# bit 3-2: 0, CS0 hit selected
|
||||
# bit 23-4:ones, required
|
||||
# bit 31-24:0x1F, Size (i.e. 512MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
|
||||
# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
|
||||
# bit 11-8: 0, required
|
||||
# big 15-11: 0, required
|
||||
# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
|
||||
# bit 27-24: 0, required
|
||||
# bit 31-28: 0, required
|
||||
|
||||
DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
|
||||
# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
|
||||
# bit 3-2: 1, ODT1 never active
|
||||
# bit 31-4: 0, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
|
||||
# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
|
||||
# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
|
||||
# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
|
||||
# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
|
||||
# bit 14: 1, STARTBURST ODT enabled
|
||||
# bit 15: 1, Use ODT Block
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
# bit 0: 1, enable DDR init upon this register write
|
||||
# bit 31-1: 0, reserved
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
These scripts are needed for our development usecases. Copy this directory
|
||||
into your tftp root directory to be able to use this scripts.
|
||||
cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/
|
||||
|
||||
To load and configure these usecase, two environment variables in the u-boot
|
||||
default environment must be parsed:
|
||||
run develop : setup environment to configure for rootfs via nfs
|
||||
run ramfs : setup environment to configure for rootfs in ram
|
||||
|
||||
Last change: 24.11.2011
|
||||
|
||||
develop-common.txt
|
||||
============================
|
||||
This file defines variables for working with rootfs via nfs for powerpc and
|
||||
arm.
|
||||
|
||||
develop-<arch>.txt
|
||||
============================
|
||||
This file defines architecture specific variables for working with rootfs via
|
||||
nfs arm.
|
||||
|
||||
|
||||
ramfs-common.txt
|
||||
============================
|
||||
This file defines variables for working with rootfs inside the ram for powerpc
|
||||
and arm.
|
||||
|
||||
ramfs-<arch>.txt
|
||||
============================
|
||||
This file defines architecture specific variables for working with rootfs inside
|
||||
ram.
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=true
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
altbootcmd=run ${subbootcmds}
|
||||
bootcmd=run ${subbootcmds}
|
||||
configure=km_setboardid && saveenv && reset
|
||||
subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
|
||||
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
|
||||
tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
|
||||
toolchain=/opt/eldk
|
||||
rootfssize=0
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=true
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
|
||||
actual_bank=-1
|
||||
altbootcmd=run ${subbootcmds}
|
||||
bootcmd=run ${subbootcmds}
|
||||
subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
|
||||
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
|
||||
configure=km_setboardid && saveenv && reset
|
||||
rootfsfile=${hostname}/rootfsImage
|
||||
setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
|
||||
tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
|
||||
tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
|
||||
tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
|
||||
Loading…
Add table
Add a link
Reference in a new issue