mirror of
https://github.com/Ysurac/openmptcprouter.git
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Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,431 @@
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/*
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* (C) Copyright 2007 - 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <ioports.h>
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#include <malloc.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
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#include <i2c.h>
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#endif
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#include "../common/common.h"
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A */
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{ /* conf ppar psor pdir podr pdat */
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{ 0, 0, 0, 0, 0, 0 }, /* PA31 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA30 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA29 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA28 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA27 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA26 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA25 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA24 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA23 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA22 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA21 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA20 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA19 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA18 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA17 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA16 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA15 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA14 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA13 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA12 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA11 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA10 */
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{ 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
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{ 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
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{ 0, 0, 0, 0, 0, 0 }, /* PA7 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA6 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA5 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA4 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA3 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA2 */
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{ 0, 0, 0, 0, 0, 0 }, /* PA1 */
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{ 0, 0, 0, 0, 0, 0 } /* PA0 */
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},
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/* Port B */
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{ /* conf ppar psor pdir podr pdat */
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{ 0, 0, 0, 0, 0, 0 }, /* PB31 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB30 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB29 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB28 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB27 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB26 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB25 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB24 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB23 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB22 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB21 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB20 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB19 */
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{ 0, 0, 0, 0, 0, 0 }, /* PB18 */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 } /* non-existent */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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{ 0, 0, 0, 0, 0, 0 }, /* PC31 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC30 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC29 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC28 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC27 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC26 */
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{ 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
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{ 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
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{ 0, 0, 0, 0, 0, 0 }, /* PC23 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC22 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC21 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC20 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC19 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC18 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC17 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC16 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC15 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC14 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC13 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC12 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC11 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC10 */
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{ 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
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{ 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
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{ 0, 0, 0, 0, 0, 0 }, /* PC7 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC6 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC5 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC4 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC3 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC2 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC1 */
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{ 0, 0, 0, 0, 0, 0 }, /* PC0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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{ 0, 0, 0, 0, 0, 0 }, /* PD31 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD30 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD29 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD28 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD27 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD26 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD25 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD24 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD23 */
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{ 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
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{ 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
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{ 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
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{ 0, 0, 0, 0, 0, 0 }, /* PD19 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD18 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD17 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD16 */
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#if defined(CONFIG_HARD_I2C)
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{ 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
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{ 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
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#else
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{ 1, 0, 0, 0, 1, 1 }, /* PD15 */
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{ 1, 0, 0, 1, 1, 1 }, /* PD14 */
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#endif
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{ 0, 0, 0, 0, 0, 0 }, /* PD13 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD12 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD11 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD10 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD9 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD8 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD7 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD6 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD5 */
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{ 0, 0, 0, 0, 0, 0 }, /* PD4 */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 }, /* non-existent */
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{ 0, 0, 0, 0, 0, 0 } /* non-existent */
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}
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};
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/*
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* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
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*
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* This routine performs standard 8260 initialization sequence
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* and calculates the available memory size. It may be called
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* several times to try different SDRAM configurations on both
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* 60x and local buses.
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*/
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static long int try_init(memctl8260_t *memctl, ulong sdmr,
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ulong orx, uchar *base)
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{
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uchar c = 0xff;
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ulong maxsize, size;
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int i;
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/*
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* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be
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* mapped by the controller. That means, that the initial mapping has
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* to be (at least) twice as large as the maximum expected size.
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*/
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maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
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out_be32(&memctl->memc_or1, orx);
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
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*
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* "At system reset, initialization software must set up the
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* programmable parameters in the memory controller banks registers
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
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* system software should execute the following initialization sequence
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* for each SDRAM device.
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*
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* 1. Issue a PRECHARGE-ALL-BANKS command
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* 2. Issue eight CBR REFRESH commands
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* 3. Issue a MODE-SET command to initialize the mode register
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*
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address
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* CONFIG_SYS_SDRAM_BASE.
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*/
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out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
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out_8(base, c);
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out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
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for (i = 0; i < 8; i++)
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out_8(base, c);
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out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
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/* setting MR on address lines */
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out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
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out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
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out_8(base, c);
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size = get_ram_size((long *)base, maxsize);
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out_be32(&memctl->memc_or1, orx | ~(size - 1));
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return size;
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}
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phys_size_t initdram(int board_type)
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{
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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memctl8260_t *memctl = &immap->im_memctl;
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long psize;
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out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
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out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
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#ifndef CONFIG_SYS_RAMBOOT
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/* 60x SDRAM setup:
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*/
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psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
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(uchar *) CONFIG_SYS_SDRAM_BASE);
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#endif /* CONFIG_SYS_RAMBOOT */
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icache_enable();
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return psize;
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}
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int checkboard(void)
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{
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#if defined(CONFIG_MGCOGE)
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puts("Board: Keymile mgcoge");
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#else
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puts("Board: Keymile mgcoge3ne");
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#endif
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if (ethernet_present())
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puts(" with PIGGY.");
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puts("\n");
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return 0;
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}
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int last_stage_init(void)
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{
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struct bfticu_iomap *base =
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(struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
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u8 dip_switch;
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dip_switch = in_8(&base->mswitch);
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dip_switch &= BFTICU_DIPSWITCH_MASK;
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/* dip switch 'full reset' or 'db erase' */
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if (dip_switch & 0x1 || dip_switch & 0x2) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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setenv("actual_bank", "0");
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}
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set_km_env();
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return 0;
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}
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#ifdef CONFIG_MGCOGE3NE
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static void set_pin(int state, unsigned long mask);
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/*
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* For mgcoge3ne boards, the mgcoge3un control is controlled from
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* a GPIO line on the PPC CPU. If bobcatreset is set the line
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* will toggle once what forces the mgocge3un part to restart
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* immediately.
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*/
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void handle_mgcoge3un_reset(void)
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{
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char *bobcatreset = getenv("bobcatreset");
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if (bobcatreset) {
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if (strcmp(bobcatreset, "true") == 0) {
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puts("Forcing bobcat reset\n");
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set_pin(0, 0x00000004); /* clear PD29 to reset arm */
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udelay(1000);
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set_pin(1, 0x00000004);
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} else
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set_pin(1, 0x00000004); /* set PD29 to not reset arm */
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}
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}
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#endif
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/*
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* Early board initalization.
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*/
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int board_early_init_r(void)
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{
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
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/* setup the UPIOx */
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/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
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out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
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/* SCC4 enable, halfduplex, FCC1 powerdown */
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out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
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H_OPORTS_FCC1_PW_DWN));
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#ifdef CONFIG_MGCOGE3NE
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handle_mgcoge3un_reset();
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#endif
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return 0;
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}
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int hush_init_var(void)
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{
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ivm_read_eeprom();
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return 0;
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}
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#define SDA_MASK 0x00010000
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#define SCL_MASK 0x00020000
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static void set_pin(int state, unsigned long mask)
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{
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ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
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if (state)
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setbits_be32(&iop->pdat, mask);
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else
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clrbits_be32(&iop->pdat, mask);
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setbits_be32(&iop->pdir, mask);
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}
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static int get_pin(unsigned long mask)
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{
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ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
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clrbits_be32(&iop->pdir, mask);
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return 0 != (in_be32(&iop->pdat) & mask);
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}
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void set_sda(int state)
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{
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set_pin(state, SDA_MASK);
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}
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void set_scl(int state)
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{
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set_pin(state, SCL_MASK);
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}
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int get_sda(void)
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{
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return get_pin(SDA_MASK);
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}
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int get_scl(void)
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{
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return get_pin(SCL_MASK);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
static void setports(int gpio)
|
||||
{
|
||||
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
|
||||
|
||||
if (gpio) {
|
||||
clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
|
||||
clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
|
||||
} else {
|
||||
setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
|
||||
clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
|
||||
setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
Loading…
Add table
Add a link
Reference in a new issue