mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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SOBJS := init.o
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COBJS := ppmc7xx.o pci.o flash.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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494
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/flash.c
Normal file
494
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/flash.c
Normal file
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@ -0,0 +1,494 @@
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/*
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* flash.c
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* -------
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*
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* Flash programming routines for the Wind River PPMC 74xx/7xx
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* based on flash.c from the TQM8260 board.
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*
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* By Richard Danter (richard.danter@windriver.com)
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* Copyright (C) 2005 Wind River Systems
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <74xx_7xx.h>
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#define DWORD unsigned long long
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/* Local function prototypes */
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static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
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static void write_via_fpu (volatile DWORD* addr, DWORD* data);
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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/*-----------------------------------------------------------------------
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*/
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void flash_reset (void)
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{
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unsigned long msr;
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DWORD cmd_reset = 0x00F000F000F000F0LL;
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if (flash_info[0].flash_id != FLASH_UNKNOWN) {
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msr = get_msr ();
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set_msr (msr | MSR_FP);
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write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
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set_msr (msr);
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}
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}
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/*-----------------------------------------------------------------------
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*/
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ulong flash_get_size (ulong baseaddr, flash_info_t * info)
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{
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int i;
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unsigned long msr;
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DWORD flashtest;
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DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
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0x0090009000900090LL };
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/* Enable FPU */
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msr = get_msr ();
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set_msr (msr | MSR_FP);
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/* Write auto-select command sequence */
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write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
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write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
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write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
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/* Restore FPU */
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set_msr (msr);
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/* Read manufacturer ID */
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flashtest = *(volatile DWORD*)baseaddr;
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switch ((int)flashtest) {
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case AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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case FUJ_MANUFACT:
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info->flash_id = FLASH_MAN_FUJ;
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break;
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default:
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/* No, faulty or unknown flash */
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0);
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}
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/* Read device ID */
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flashtest = *(volatile DWORD*)(baseaddr + 8);
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switch ((long)flashtest) {
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case AMD_ID_LV800T:
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info->flash_id += FLASH_AM800T;
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info->sector_count = 19;
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info->size = 0x00400000;
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break;
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case AMD_ID_LV800B:
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info->flash_id += FLASH_AM800B;
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info->sector_count = 19;
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info->size = 0x00400000;
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break;
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case AMD_ID_LV160T:
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info->flash_id += FLASH_AM160T;
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info->sector_count = 35;
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info->size = 0x00800000;
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break;
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case AMD_ID_LV160B:
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00800000;
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break;
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case AMD_ID_DL322T:
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info->flash_id += FLASH_AMDL322T;
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info->sector_count = 71;
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info->size = 0x01000000;
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break;
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case AMD_ID_DL322B:
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info->flash_id += FLASH_AMDL322B;
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info->sector_count = 71;
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info->size = 0x01000000;
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break;
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case AMD_ID_DL323T:
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info->flash_id += FLASH_AMDL323T;
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info->sector_count = 71;
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info->size = 0x01000000;
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break;
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case AMD_ID_DL323B:
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info->flash_id += FLASH_AMDL323B;
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info->sector_count = 71;
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info->size = 0x01000000;
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break;
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case AMD_ID_LV640U:
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info->flash_id += FLASH_AM640U;
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info->sector_count = 128;
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info->size = 0x02000000;
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break;
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default:
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/* Unknown flash type */
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info->flash_id = FLASH_UNKNOWN;
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return (0);
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}
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if ((long)flashtest == AMD_ID_LV640U) {
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/* set up sector start adress table (uniform sector type) */
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = baseaddr + (i * 0x00040000);
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} else if (info->flash_id & FLASH_BTYPE) {
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/* set up sector start adress table (bottom sector type) */
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info->start[0] = baseaddr + 0x00000000;
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info->start[1] = baseaddr + 0x00010000;
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info->start[2] = baseaddr + 0x00018000;
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info->start[3] = baseaddr + 0x00020000;
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
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}
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} else {
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/* set up sector start adress table (top sector type) */
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i = info->sector_count - 1;
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info->start[i--] = baseaddr + info->size - 0x00010000;
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info->start[i--] = baseaddr + info->size - 0x00018000;
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info->start[i--] = baseaddr + info->size - 0x00020000;
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for (; i >= 0; i--) {
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info->start[i] = baseaddr + i * 0x00040000;
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}
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
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info->protect[i] = 1; /* D0 = 1 if protected */
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} else {
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info->protect[i] = 0;
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}
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}
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flash_reset ();
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0 = 0;
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int i;
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/* Init: no FLASHes known */
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here (only one bank) */
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size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0 >> 20);
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}
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/*
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* protect monitor and environment sectors
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*/
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
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#endif
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#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
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# ifndef CONFIG_ENV_SIZE
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# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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# endif
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
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#endif
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return (size_b0);
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf ("AMD ");
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break;
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case FLASH_MAN_FUJ:
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printf ("FUJITSU ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM800T:
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printf ("29LV800T (8 M, top sector)\n");
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break;
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case FLASH_AM800B:
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printf ("29LV800T (8 M, bottom sector)\n");
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break;
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case FLASH_AM160T:
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printf ("29LV160T (16 M, top sector)\n");
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break;
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case FLASH_AM160B:
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printf ("29LV160B (16 M, bottom sector)\n");
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break;
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case FLASH_AMDL322T:
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printf ("29DL322T (32 M, top sector)\n");
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break;
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case FLASH_AMDL322B:
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printf ("29DL322B (32 M, bottom sector)\n");
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break;
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case FLASH_AMDL323T:
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printf ("29DL323T (32 M, top sector)\n");
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break;
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case FLASH_AMDL323B:
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printf ("29DL323B (32 M, bottom sector)\n");
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break;
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case FLASH_AM640U:
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printf ("29LV640D (64 M, uniform sector)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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unsigned long msr;
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DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
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0x0080008000800080LL, 0x00AA00AA00AA00AALL,
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0x0055005500550055LL, 0x0030003000300030LL };
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect])
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prot++;
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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l_sect = -1;
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/* Enable FPU */
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msr = get_msr();
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set_msr ( msr | MSR_FP );
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
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write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
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write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
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write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
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write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
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udelay (1000);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
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l_sect = sect;
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts ();
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/* Restore FPU */
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set_msr (msr);
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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/*
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* We wait for the last triggered sector
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*/
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if (l_sect < 0)
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goto DONE;
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start = get_timer (0);
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last = start;
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while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
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!= 0x0080008000800080LL )
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{
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if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return 1;
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}
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/* show that we're waiting */
|
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if ((now - last) > 1000) { /* every second */
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serial_putc ('.');
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last = now;
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}
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}
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DONE:
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/* reset to read mode */
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flash_reset ();
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printf (" done\n");
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return 0;
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}
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|
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|
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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ulong dp;
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static unsigned char bb[8];
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int i, l, rc, cc = cnt;
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dp = (addr & ~7); /* get lower dword aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - dp) != 0) {
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for (i = 0; i < 8; i++)
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bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
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if ((rc = write_dword (info, dp, bb)) != 0) {
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return (rc);
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}
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dp += 8;
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cc -= 8 - l;
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}
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/*
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* handle word aligned part
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*/
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while (cc >= 8) {
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if ((rc = write_dword (info, dp, src)) != 0) {
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return (rc);
|
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}
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dp += 8;
|
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src += 8;
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cc -= 8;
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}
|
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|
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if (cc <= 0) {
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return (0);
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}
|
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|
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/*
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* handle unaligned tail bytes
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*/
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for (i = 0; i < 8; i++) {
|
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bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
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}
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return (write_dword (info, dp, bb));
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}
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|
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/*-----------------------------------------------------------------------
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* Write a dword to Flash, returns:
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* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
|
||||
{
|
||||
ulong start;
|
||||
unsigned long msr;
|
||||
int flag, i;
|
||||
DWORD data;
|
||||
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
|
||||
0x00A000A000A000A0LL };
|
||||
|
||||
for (data = 0, i = 0; i < 8; i++)
|
||||
data = (data << 8) + *pdata++;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*(DWORD*)dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Enable FPU */
|
||||
msr = get_msr();
|
||||
set_msr( msr | MSR_FP );
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
|
||||
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
|
||||
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
|
||||
write_via_fpu ((DWORD*)dest, &data );
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* Restore FPU */
|
||||
set_msr(msr);
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while (*(volatile DWORD*)dest != data ) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void write_via_fpu (volatile DWORD* addr, DWORD* data)
|
||||
{
|
||||
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
|
||||
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
|
||||
__asm__ __volatile__ ("eieio");
|
||||
}
|
||||
336
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/init.S
Normal file
336
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/init.S
Normal file
|
|
@ -0,0 +1,336 @@
|
|||
/*
|
||||
* init.S
|
||||
* ------
|
||||
*
|
||||
* Wind River PPMC 7xx/74xx init code.
|
||||
*
|
||||
* By Richard Danter (richard.danter@windriver.com)
|
||||
* Copyright (C) 2005 Wind River Systems
|
||||
*
|
||||
* NOTE: The following code was generated automatically by Workbench
|
||||
* from the ppmc7400_107.reg register file.
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
|
||||
|
||||
.globl board_asm_init
|
||||
board_asm_init:
|
||||
|
||||
lis r4,0xFEC0
|
||||
ori r4,r4,0x0000
|
||||
lis r5,0xFEE0
|
||||
ori r5,r5,0x0000
|
||||
lis r3,0x8000 # ADDR_00
|
||||
ori r3,r3,0x0000
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x1057 # VENDOR
|
||||
li r8, 0x0
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_02
|
||||
ori r3,r3,0x0002
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x0004 # ID
|
||||
li r8, 0x2
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_04
|
||||
ori r3,r3,0x0004
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x0006 # PCICMD
|
||||
li r8, 0x0
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_06
|
||||
ori r3,r3,0x0006
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00A0 # PCISTAT
|
||||
li r8, 0x2
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_08
|
||||
ori r3,r3,0x0008
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x10 # REVID
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_09
|
||||
ori r3,r3,0x0009
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # PROGIR
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_0A
|
||||
ori r3,r3,0x000A
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # SUBCCODE
|
||||
stb r3,0x2(r5)
|
||||
lis r3,0x8000 # ADDR_0B
|
||||
ori r3,r3,0x000B
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x06 # PBCCR
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_0C
|
||||
ori r3,r3,0x000C
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x08 # PCLSR
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_0D
|
||||
ori r3,r3,0x000D
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # PLTR
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_0E
|
||||
ori r3,r3,0x000E
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # HEADTYPE
|
||||
stb r3,0x2(r5)
|
||||
lis r3,0x8000 # ADDR_0F
|
||||
ori r3,r3,0x000F
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # BISTCTRL
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_10
|
||||
ori r3,r3,0x0010
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0000 # LMBAR
|
||||
ori r3,r3,0x0008
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_14
|
||||
ori r3,r3,0x0014
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xF000 # PCSRBAR
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_3C
|
||||
ori r3,r3,0x003C
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # ILR
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_3D
|
||||
ori r3,r3,0x003D
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x01 # INTPIN
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_3E
|
||||
ori r3,r3,0x003E
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # MIN_GNT
|
||||
stb r3,0x2(r5)
|
||||
lis r3,0x8000 # ADDR_3F
|
||||
ori r3,r3,0x003F
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # MAX_LAT
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_40
|
||||
ori r3,r3,0x0040
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # BUSNB
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_41
|
||||
ori r3,r3,0x0041
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # SBUSNB
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_46
|
||||
ori r3,r3,0x0046
|
||||
stwbrx r3,0,r4
|
||||
# li r3,0xE080 # PCIARB
|
||||
li r3,-0x1F80 # PCIARB
|
||||
li r8, 0x2
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_70
|
||||
ori r3,r3,0x0070
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x0000 # PMCR1
|
||||
li r8, 0x0
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_72
|
||||
ori r3,r3,0x0072
|
||||
stwbrx r3,0,r4
|
||||
li r3,0xC0 # PMCR2
|
||||
stb r3,0x2(r5)
|
||||
lis r3,0x8000 # ADDR_73
|
||||
ori r3,r3,0x0073
|
||||
stwbrx r3,0,r4
|
||||
li r3,0xEF # ODCR
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_74
|
||||
ori r3,r3,0x0074
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x7D00 # CLKDCR
|
||||
li r8, 0x0
|
||||
sthbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_76
|
||||
ori r3,r3,0x0076
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # MDCR
|
||||
stb r3,0x2(r5)
|
||||
lis r6,0xFCE0
|
||||
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
|
||||
lis r3,0x8000 # ADDR_78
|
||||
ori r3,r3,0x0078
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFCE0 # EUMBBAR
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_80
|
||||
ori r3,r3,0x0080
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFFFF # MSADDR1
|
||||
ori r3,r3,0x4000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_84
|
||||
ori r3,r3,0x0084
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFFFF # MSADDR2
|
||||
ori r3,r3,0xFFFF
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_88
|
||||
ori r3,r3,0x0088
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0303 # EMSADDR1
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_8C
|
||||
ori r3,r3,0x008C
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0303 # EMSADDR2
|
||||
ori r3,r3,0x0303
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_90
|
||||
ori r3,r3,0x0090
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFFFF # EMEADDR1
|
||||
ori r3,r3,0x7F3F
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_94
|
||||
ori r3,r3,0x0094
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFFFF # EMEADDR2
|
||||
ori r3,r3,0xFFFF
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_98
|
||||
ori r3,r3,0x0098
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0303 # EXTEMEM1
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_9C
|
||||
ori r3,r3,0x009C
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0303 # EXTEMEM2
|
||||
ori r3,r3,0x0303
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_A0
|
||||
ori r3,r3,0x00A0
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x03 # MEMBNKEN
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_A3
|
||||
ori r3,r3,0x00A3
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # MEMPMODE
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_B8
|
||||
ori r3,r3,0x00B8
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # ECCCNT
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_B9
|
||||
ori r3,r3,0x00B9
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # ECCTRG
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_C0
|
||||
ori r3,r3,0x00C0
|
||||
stwbrx r3,0,r4
|
||||
li r3,0xFF # ERRENR1
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_C1
|
||||
ori r3,r3,0x00C1
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # ERRDR1
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_C3
|
||||
ori r3,r3,0x00C3
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x50 # IPBESR
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_C4
|
||||
ori r3,r3,0x00C4
|
||||
stwbrx r3,0,r4
|
||||
li r3,0xBF # ERRENR2
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_C5
|
||||
ori r3,r3,0x00C5
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # ERRDR2
|
||||
stb r3,0x1(r5)
|
||||
lis r3,0x8000 # ADDR_C7
|
||||
ori r3,r3,0x00C7
|
||||
stwbrx r3,0,r4
|
||||
li r3,0x00 # PCIBESR
|
||||
stb r3,0x3(r5)
|
||||
lis r3,0x8000 # ADDR_C8
|
||||
ori r3,r3,0x00C8
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0000 # BERRADDR
|
||||
ori r3,r3,0xE0FE
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_E0
|
||||
ori r3,r3,0x00E0
|
||||
stwbrx r3,0,r4
|
||||
li r3,0xC0 # AMBOR
|
||||
stb r3,0x0(r5)
|
||||
lis r3,0x8000 # ADDR_F4
|
||||
ori r3,r3,0x00F4
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0000 # MCCR2
|
||||
ori r3,r3,0x020C
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_F8
|
||||
ori r3,r3,0x00F8
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0230 # MCCR3
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_FC
|
||||
ori r3,r3,0x00FC
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x2532 # MCCR4
|
||||
ori r3,r3,0x2220
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_F0
|
||||
ori r3,r3,0x00F0
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFFC8 # MCCR1
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_A8
|
||||
ori r3,r3,0x00A8
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0xFF14 # PICR1
|
||||
ori r3,r3,0x1CC8
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
lis r3,0x8000 # ADDR_AC
|
||||
ori r3,r3,0x00AC
|
||||
stwbrx r3,0,r4
|
||||
lis r3,0x0000 # PICR2
|
||||
ori r3,r3,0x0000
|
||||
li r8, 0x0
|
||||
stwbrx r3,r8,r5
|
||||
|
||||
blr
|
||||
97
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/pci.c
Normal file
97
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/pci.c
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* (C) Copyright 2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI initialisation for the MPC10x.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <mpc106.h>
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
struct pci_controller local_hose;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
struct pci_controller* hose = (struct pci_controller *)&local_hose;
|
||||
u16 reg16;
|
||||
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CONFIG_SYS_PCI_MEM_BUS,
|
||||
CONFIG_SYS_PCI_MEM_PHYS,
|
||||
CONFIG_SYS_PCI_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* ISA/PCI memory space */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CONFIG_SYS_ISA_MEM_BUS,
|
||||
CONFIG_SYS_ISA_MEM_PHYS,
|
||||
CONFIG_SYS_ISA_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CONFIG_SYS_PCI_IO_BUS,
|
||||
CONFIG_SYS_PCI_IO_PHYS,
|
||||
CONFIG_SYS_PCI_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
/* ISA/PCI I/O space */
|
||||
pci_set_region(hose->regions + 4,
|
||||
CONFIG_SYS_ISA_IO_BUS,
|
||||
CONFIG_SYS_ISA_IO_PHYS,
|
||||
CONFIG_SYS_ISA_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 5;
|
||||
|
||||
pci_setup_indirect(hose,
|
||||
MPC106_REG_ADDR,
|
||||
MPC106_REG_DATA);
|
||||
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
|
||||
/* Initialises the MPC10x PCI Configuration regs. */
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
|
||||
|
||||
/* Clear non-reserved bits in status register */
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
112
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/ppmc7xx.c
Normal file
112
root/package/utils/sysupgrade-helper/src/board/ppmc7xx/ppmc7xx.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* ppmc7xx.c
|
||||
* ---------
|
||||
*
|
||||
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
|
||||
*
|
||||
* By Richard Danter (richard.danter@windriver.com)
|
||||
* Copyright (C) 2005 Wind River Systems
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
|
||||
|
||||
/* Define some MPC107 (memory controller) registers */
|
||||
#define MPC107_EUMB_GCR 0xfce41020
|
||||
#define MPC107_EUMB_IACKR 0xfce600a0
|
||||
|
||||
|
||||
/* Function prototypes */
|
||||
extern void _start(void);
|
||||
|
||||
|
||||
/*
|
||||
* initdram()
|
||||
*
|
||||
* This function normally initialises the (S)DRAM of the system. For this board
|
||||
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
|
||||
* return the size of RAM.
|
||||
*/
|
||||
phys_size_t initdram( int board_type )
|
||||
{
|
||||
return CONFIG_SYS_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* after_reloc()
|
||||
*
|
||||
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
|
||||
* us an opportunity to do some additional setup before the rest of the system
|
||||
* is initialised. We don't need to do anything, so we just call board_init_r()
|
||||
* which should never return.
|
||||
*/
|
||||
void after_reloc( ulong dest_addr, gd_t* gd )
|
||||
{
|
||||
/* Jump to the main U-Boot board init code */
|
||||
board_init_r( gd, dest_addr );
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* checkboard()
|
||||
*
|
||||
* We could do some board level checks here, such as working out what version
|
||||
* it is, but for this board we simply display it's name (on the console).
|
||||
*/
|
||||
int checkboard( void )
|
||||
{
|
||||
puts( "Board: Wind River PPMC 7xx/74xx\n" );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* misc_init_r
|
||||
*
|
||||
* Used for other setup which needs to be done late in the bring-up phase.
|
||||
*/
|
||||
int misc_init_r( void )
|
||||
{
|
||||
/* Reset the EPIC and clear pending interrupts */
|
||||
out32r(MPC107_EUMB_GCR, 0xa0000000);
|
||||
while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
|
||||
out32r( MPC107_EUMB_GCR, 0x20000000 );
|
||||
while( in32r( MPC107_EUMB_IACKR ) != 0xff );
|
||||
|
||||
/* Enable the I-Cache */
|
||||
icache_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* do_reset()
|
||||
*
|
||||
* Shell command to reset the board.
|
||||
*/
|
||||
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
printf( "Resetting...\n" );
|
||||
|
||||
/* Disabe and invalidate cache */
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
|
||||
/* Jump to cold reset point (in RAM) */
|
||||
_start();
|
||||
|
||||
/* Should never get here */
|
||||
while(1)
|
||||
;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue