mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,5 @@
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ifdef CONFIG_NAND_LP
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PAD_TO = 0xFFF20000
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else
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PAD_TO = 0xFFF04000
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endif
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@ -0,0 +1,193 @@
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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* Copyright (C) Sheldon Instruments, Inc. 2008
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*
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* Author: Ron Madrid <info@sheldoninst.com>
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <spd_sdram.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static long fixed_sdram(void);
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#if defined(CONFIG_NAND_SPL)
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void si_wait_i2c(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
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;
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__raw_writeb(0x00, &im->i2c[0].sr);
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sync();
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return;
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}
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void si_read_i2c(u32 lbyte, int count, u8 *buffer)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 i;
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u8 chip = 0x50 << 1; /* boot sequencer I2C */
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u32 ubyte = (lbyte & 0xff00) >> 8;
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lbyte &= 0xff;
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/*
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* Set up controller
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*/
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__raw_writeb(0x3f, &im->i2c[0].fdr);
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__raw_writeb(0x00, &im->i2c[0].adr);
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__raw_writeb(0x00, &im->i2c[0].sr);
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__raw_writeb(0x00, &im->i2c[0].dr);
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while (__raw_readb(&im->i2c[0].sr) & 0x20)
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;
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/*
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* Writing address to device
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*/
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__raw_writeb(0xb0, &im->i2c[0].cr);
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sync();
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__raw_writeb(chip, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xb0, &im->i2c[0].cr);
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sync();
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__raw_writeb(ubyte, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(lbyte, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xb4, &im->i2c[0].cr);
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sync();
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__raw_writeb(chip + 1, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xa0, &im->i2c[0].cr);
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sync();
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/*
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* Dummy read
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*/
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__raw_readb(&im->i2c[0].dr);
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si_wait_i2c();
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/*
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* Read actual data
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*/
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for (i = 0; i < count; i++)
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{
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if (i == (count - 2)) /* Reached next to last byte, No ACK */
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__raw_writeb(0xa8, &im->i2c[0].cr);
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if (i == (count - 1)) /* Reached last byte, STOP */
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__raw_writeb(0x88, &im->i2c[0].cr);
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/* Read byte of data */
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buffer[i] = __raw_readb(&im->i2c[0].dr);
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if (i == (count - 1))
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break;
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si_wait_i2c();
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}
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return;
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}
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#endif /* CONFIG_NAND_SPL */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &im->im_lbc;
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u32 msize;
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if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
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msize = fixed_sdram();
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/* Local Bus setup lbcr and mrtpr */
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__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
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__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
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sync();
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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/*************************************************************************
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* fixed sdram init -- reads values from boot sequencer I2C
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************************************************************************/
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static long fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msizelog2, msize = 1;
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#if defined(CONFIG_NAND_SPL)
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u32 i;
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const u8 bytecount = 135;
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u8 buffer[bytecount];
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u32 addr, data;
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si_read_i2c(0, bytecount, buffer);
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for (i = 18; i < bytecount; i += 7){
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addr = (u32)buffer[i];
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addr <<= 8;
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addr |= (u32)buffer[i + 1];
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addr <<= 2;
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data = (u32)buffer[i + 2];
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data <<= 8;
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data |= (u32)buffer[i + 3];
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data <<= 8;
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data |= (u32)buffer[i + 4];
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data <<= 8;
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data |= (u32)buffer[i + 5];
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__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
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}
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sync();
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/* enable DDR controller */
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__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
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#endif /* (CONFIG_NAND_SPL) */
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msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
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msize <<= (msizelog2 - 20);
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return msize;
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}
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@ -0,0 +1,166 @@
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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* Copyright (C) Sheldon Instruments, Inc. 2008
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*
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* Author: Ron Madrid <info@sheldoninst.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_NAND_SPL
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int checkboard(void)
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{
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puts("Board: Sheldon Instruments SIMPC8313\n");
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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/*
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* Miscellaneous late-boot configurations
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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fsl_lbc_t *lbus = &immap->im_lbc;
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u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
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/* UPM Table Configuration Code */
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static uint UPMATable[] = {
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/* Read Single-Beat (RSS) */
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0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Read Burst (RBS) */
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0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
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0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Write Single-Beat (WSS) */
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0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Write Burst (WBS) */
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0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
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0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
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0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Refresh Timer (RTS) */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Exception Condition (EXS) */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
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};
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upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
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/* Set LUPWAIT to be active low and enabled */
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out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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#else /* CONFIG_NAND_SPL */
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void board_init_f(ulong bootflag)
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{
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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puts("NAND boot... ");
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init_timebase();
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initdram(0);
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (gd->flags & GD_FLG_SILENT)
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return;
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if (c == '\n')
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
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}
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#endif
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