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https://github.com/Ysurac/openmptcprouter.git
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Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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* Copyright (C) Sheldon Instruments, Inc. 2008
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*
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* Author: Ron Madrid <info@sheldoninst.com>
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <spd_sdram.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static long fixed_sdram(void);
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#if defined(CONFIG_NAND_SPL)
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void si_wait_i2c(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
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;
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__raw_writeb(0x00, &im->i2c[0].sr);
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sync();
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return;
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}
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void si_read_i2c(u32 lbyte, int count, u8 *buffer)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 i;
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u8 chip = 0x50 << 1; /* boot sequencer I2C */
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u32 ubyte = (lbyte & 0xff00) >> 8;
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lbyte &= 0xff;
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/*
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* Set up controller
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*/
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__raw_writeb(0x3f, &im->i2c[0].fdr);
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__raw_writeb(0x00, &im->i2c[0].adr);
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__raw_writeb(0x00, &im->i2c[0].sr);
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__raw_writeb(0x00, &im->i2c[0].dr);
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while (__raw_readb(&im->i2c[0].sr) & 0x20)
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;
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/*
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* Writing address to device
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*/
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__raw_writeb(0xb0, &im->i2c[0].cr);
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sync();
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__raw_writeb(chip, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xb0, &im->i2c[0].cr);
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sync();
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__raw_writeb(ubyte, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(lbyte, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xb4, &im->i2c[0].cr);
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sync();
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__raw_writeb(chip + 1, &im->i2c[0].dr);
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si_wait_i2c();
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__raw_writeb(0xa0, &im->i2c[0].cr);
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sync();
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/*
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* Dummy read
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*/
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__raw_readb(&im->i2c[0].dr);
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si_wait_i2c();
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/*
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* Read actual data
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*/
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for (i = 0; i < count; i++)
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{
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if (i == (count - 2)) /* Reached next to last byte, No ACK */
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__raw_writeb(0xa8, &im->i2c[0].cr);
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if (i == (count - 1)) /* Reached last byte, STOP */
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__raw_writeb(0x88, &im->i2c[0].cr);
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/* Read byte of data */
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buffer[i] = __raw_readb(&im->i2c[0].dr);
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if (i == (count - 1))
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break;
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si_wait_i2c();
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}
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return;
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}
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#endif /* CONFIG_NAND_SPL */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &im->im_lbc;
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u32 msize;
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if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
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msize = fixed_sdram();
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/* Local Bus setup lbcr and mrtpr */
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__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
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__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
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sync();
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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/*************************************************************************
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* fixed sdram init -- reads values from boot sequencer I2C
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************************************************************************/
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static long fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msizelog2, msize = 1;
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#if defined(CONFIG_NAND_SPL)
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u32 i;
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const u8 bytecount = 135;
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u8 buffer[bytecount];
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u32 addr, data;
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si_read_i2c(0, bytecount, buffer);
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for (i = 18; i < bytecount; i += 7){
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addr = (u32)buffer[i];
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addr <<= 8;
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addr |= (u32)buffer[i + 1];
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addr <<= 2;
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data = (u32)buffer[i + 2];
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data <<= 8;
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data |= (u32)buffer[i + 3];
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data <<= 8;
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data |= (u32)buffer[i + 4];
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data <<= 8;
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data |= (u32)buffer[i + 5];
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__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
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}
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sync();
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/* enable DDR controller */
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__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
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#endif /* (CONFIG_NAND_SPL) */
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msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
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msize <<= (msizelog2 - 20);
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return msize;
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}
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